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V62C1161024L

更新时间：2024-09-18 02:10:44

品牌：MOSEL

描述：Ultra Low Power 64K x 16 CMOS SRAM

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V62C1161024L 概述

Ultra Low Power 64K x 16 CMOS SRAM 超低功耗64K ×16的CMOS SRAM

V62C1161024L 数据手册

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V62C1161024L(L)

Ultra Low Power

64K x 16 CMOS SRAM

Features

Functional Description

The V62C1161024L is a Low Power CMOS Static RAM

organized as 65,536 words by 16 bits. Easy memory exp-

ansion is provided by an active LOW (CE) and (OE) pin.

• Ultra Low-power consumption

- Active: 30mA I_CCat 70ns

- Stand-by: 5 mA(CMOS input/output)

1 mA (CMOS input/output, Lversion)

This device has an automatic power-down mode feature

when deselected. Separate Byte Enable controls (BLE

• 70/85/100/120 ns access time

• Equal access and cycle time

• Single +1.8V to 2.2V Power Supply

• Tri-state output

and BHE

) allow individual bytes to be accessed. BLE

controls the lower bits I/O1 - I/O8. BHE controls the

upper bits I/O9 - I/O16.

Writing to these devices is performed by taking Chip

Enable (CE) with Write Enable (WE) and Byte Enable

(BLE/BHE) LOW.

• Automatic power-down when deselected

Reading from the device is performed by taking Chip

Enable (CE) with Output Enable (OE) and Byte Enable

(BLE/BHE) LOW while Write Enable (WE) is held

HIGH.

• Multiple center power and ground pins for

improved noise immunity

• Individual byte controls for both Read and

Write cycles

• Available in 44 pin TSOP (II) Package

Logic Block Diagram

TSOP(II)

Pre-Charge Circuit

I/O1

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

Vcc

Vss

Memory Array

1024 X 1024

BHE

BLE

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

Data

Cont

I/O1 - I/O8

I/O Circuit

Data

Cont

I/O9 - I/O16

Column Select

A10 A11 A12 A13 A14 A15

A15

A14

A13

A12

A10

A11

BHE

BLE

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Absolute Maximum Ratings *

Parameter

Symbol Minimum Maximum

Unit

Voltage on Any Pin Relative to Gnd

Power Dissipation

-0.5

+4.0

1.0

Storage Temperature (Plastic)

Tstg

-55

+150

Temperature Under Bias

Tbias

-40

+85

* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-

ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-

ification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.

Truth Table

OE WE BLE BHE I/O1-I/O8 I/O9-I/O16

Power

Standby

Active

Mode

High-Z

Data Out

High-Z

Standby

Low Byte Read

High Byte Read

Word Read

Data Out

Data In

High-Z

Data Out

Data In

High-Z

Word Write

Low Byte Write

High Byte Write

Output Disable

Data In

High-Z

* Key: X = Don’t Care, L = Low, H = High

Recommended Operating Conditions (T_A= 0^oC to +70^oC / -40^oC to 85^oC**)

Parameter

Symbol

Min

1.8

Typ

Max

2.2

Unit

2.0

0.0

Supply Voltage

Gnd

0.0

1.6

+ 0.2

Input Voltage

-0.5*

0.4

* V_ILmin = -2.0V for pulse width less than t_RC/2.

** For Industrial Temperature

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

DC Operating Characteristics (V_cc= 2V+10%, Gnd = 0V, T_A= 0⁰C to +70⁰C / -40⁰C to 85⁰C)

-70

-85

-100

-120

Parameter

Sym Test Conditions

Unit

Min Max Min Max Min Max Min Max

V_cc= Max,

V_in= Gnd to V_cc

Input Leakage Current

= V_IHor V_cc= Max,

V_OUT= Gnd to V_cc

Output Leakage

Current

II_LO

Operating Power

Supply Current

I_CC

= V_IL, V_IN= V_IHor V_IL,

I_OUT=0

I_OUT= 0mA,

Min Cycle, 100% Duty

Average Operating

Current

I_CC1

I_CC2

I_OUT= 0mA,

< 0.2V

Cycle Time=1ms, Duty=100%

CE = V_IH

0.5

Standby Power Supply I_SB

Current (TTL Level)

CE > V_cc- 0.2V

V_IN< 0.2V or

Standby Power Supply I_SB1

Current (CMOS Level)

V >

V_cc- 0.2V

I_OL= 2 mA

I_OH= -1 mA

0.4

Output Low Voltage

Output High Voltage

V_OL

V_OH

1.6

Capacitance (f = 1MHz, T_A= 25⁰C)

Parameter*

Input Capacitance

Symbol

C_in

Test Condition

Max

Unit

= 0V

I/O Capacitance

C_I/O

= V = 0V

out

* This parameter is guaranteed by device characterization and is not production tested.

AC Test Conditions

Input Pulse Level

Input Rise and Fall Time 5ns

Input and Output Timing

0.4V to 1.6V

TTL

C_L

Reference Level

1.0V

Output Load Condition

70ns/85ns

Load for 100ns/120ns

C_L= 30pf + 1TTL Load

C_L= 100pf + 1TTL Load

Figure A.

* Including Scope and Jig Capacitance

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Read Cycle ⁽⁹⁾(V_cc= 2V+0.2V, Gnd = 0V, T_A= 0⁰C to +70⁰C / -40⁰C to +85⁰C)

Note

Unit

Parameter

Sym

-70

-85

-100

-120

Min Max Min Max Min Max Min Max

100

120

Read Cycle Time

t_RC

t_AA

t_ACE

t_OE

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Output Hold from Address Change

Chip Enable to Output in Low-Z

Chip Disable to Output in High-Z

Output Enable to Output in Low-Z

Output Disable to Output in High-Z

BLE, BHE Enable to Output in Low-Z

BLE, BHE Disable to Output in High-Z

BLE, BHE Access Time

t_OH

4,5

t _LZ

3,4,5

t_HZ

t_OLZ

t_OHZ

t_BLZ

t_BHZ

t_BA

4,5

3,4,5

Write Cycle ⁽¹¹⁾(V_cc=2V+0.2V, Gnd = 0V, T_A= 0⁰C to +70⁰C / -40⁰C to +85⁰C)

Note

Unit

Parameter

Symbol

-70

-85

-100

-120

Min Max Min Max Min Max Min Max

100

120

Write Cycle Time

t_WC

t_CW

t_AW

Chip Enable to Write End

Address Setup to Write End

Address Setup Time

t_AS

Write Pulse Width

t _WP

t_WR

t _DW

t_DH

t _WHZ

t_OW

Write Recovery Time

Data Valid to Write End

Data Hold Time

Write Enable to Output in High-Z

Output Active from Write End

BLE, BHE Setup to Write End

t_BW

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Timing Waveform of Read Cycle 1 (Address Controlled)

t_RC

Address

t_AA

t_OH

Data Out

Previous Data Valid

Data Valid

Timing Waveform of Read Cycle 2

t_RC

Address

t_AA

t_HZ(3,4,5)

t_ACE

t_LZ(4,5)

t_BA

t_BHZ(3,4,5)

(BLE/BHE)

t_BLZ(4,5)

t_OHZ

t_OE

t_OH

t_OLZ

High-Z

Data Valid

Data Out

Notes (Read Cycle)

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit condition referenced to V_OHor V_OLlevels.

4. At any given temperature and voltage condition t_HZ(max.) is less than t_LZ(min.) both for a given device and from device to

device.

5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.

6. Device is continuously selected with CE = V_IL.

7. Address valid prior to coincident with CE transition Low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

9. For test conditions, see AC Test Condition, Figure A.

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Timing Waveform of Write Cycle 1 (Address Controlled)

t_WC

Address

t_AW

t_{WR (5)}

t_{CW (3)}

t_BW

BLE/BHE

t_{AS (4)}

t_{WP (2)}

t_DW

t_DH

High-Z

Data In

t_{OHZ (6)}

t_OW

High-Z (8)

Data Out

Timing Waveform of Write Cycle 2 (CE Controlled)

t_WC

Address

t_AW

t_{WR (5)}

t_{CW (3)}

t_{AS (4)}

t_BW

BLE/BHE

t_{WP (2)}

t_DW

t_DH

High-Z

Data In

t_{WHZ (6)}

t_LZ

High-Z

High-Z (8)

Data Out

Timing Waveform of Write Cycle 3 (BLE/BHE Controlled)

t_WC

Address

t_AW

t_{WR (5)}

t_{CW (3)}

t_{AS (4)}

t_BW

BLE/BHE

t_{WP (2)}

t_DW

t_DH

High-Z

Data In

Data Out

t_{WHZ (6)}

t_BLZ

High-Z

High-Z (8)

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Notes (Write Cycle)

1. All write timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going

low: A write ends at the earliest transition among CE going high and WE going high. t_WPis measured from the beginning

of write to the end of write.

3. t_CWis measured from the later of CE going low to end of write.

4. t_ASis measured from the address valid to the beginning of write.

5. t_WRis measured from the end of write to the address change.

6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and

write cycle.

8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9. D^OUTis the read data of the new address.

10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should

not be applied.

11. For test conditions, see AC Test Condition, Figure A & B.

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Data Retention Characteristics (L Version Only)⁽¹⁾

Parameter

Symbol

Test Condition

Min Max Unit

for Data Retention

V _DR

CE >

V_CC- 0.2V

1.0

Data Retention Current

I _CCDR

Chip Deselect to Data Retention Time

Operation Recovery Time⁽²⁾

t _CDR

V_IN>V_CC- 0.2V or

0.2V

t_R

t_RC

V <

Data Retention Waveform (L Version Only) (T_A= 0⁰C to +70⁰C / -40⁰C to +85⁰C)

Data Retention Mode

V_CC

Vcc_typ

1.0V

Vcc_typ

t_CDR

t_R

Notes

1. L-version includes this feature.

2. This Parameter is sampled and not 100% tested.

3. For test conditions, see AC Test Condition, Figure A.

4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is High for read cycle.

7. CE and OE are LOW for read cycle.

8. Address valid prior to or coincident with CE transition LOW.

9. All read cycle timings are referenced from the last valid address to the first transtion address.

10. CE or WE must be HIGH during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

REV. 1.1 April 2001 V62C1161024L(L)

V62C1161024L(L)

Ordering Information

Device Type*

Speed

Package

44-pin TSOP Type 2

V62C1161024L-70T

V62C1161024L-85T

V62C1161024L-100T

V62C1161024L-120T

70 ns

85 ns

100 ns

120 ns

V62C1161024LL-70T

V62C1161024LL-85T

V62C1161024LL-100T

V62C1161024LL-120T

70 ns

85 ns

100 ns

120 ns

* For Industrial temperature tested devices, an “I” designator will be added to the end of the device number.

REV. 1.1 April 2001 V62C1161024L(L)

MOSEL VITELIC WORLDWIDE OFFICES

V62C1161024L(L)

U.S.A.

TAIWAN

SINGAPORE

UK & IRELAND

SUITE 50, GROVEWOOD

BUSINESS CENTRE

STRATHCLYDE BUSINESS

PARK

BELLSHILL, LANARKSHIRE,

SCOTLAND, ML4 3NQ

PHONE: 44-1698-748515

FAX: 44-1698-748516

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SAN JOSE, CA 95134

PHONE: 408-433-6000

FAX: 408-433-0952

7F, NO. 102

10 ANSON ROAD #23-13

INTERNATIONAL PLAZA

SINGAPORE 079903

PHONE: 65-3231801

FAX: 65-3237013

MIN-CHUAN E. ROAD, SEC. 3

TAIPEI

PHONE: 886-2-2545-1213

FAX: 886-2-2545-1209

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JAPAN

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PHONE: +49 7032 2796-0

FAX: +49 7032 2796 22

U.S. SALES OFFICES

NORTHWESTERN

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PHONE: 408-433-6000

FAX: 408-433-0952

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PHONE: 214-826-6176

FAX: 214-828-9754

4/01

Printed in U.S.A.

The information in this document is subject to change without

notice.

MOSEL VITELIC subjects its products to normal quality control

sampling techniques which are intended to provide an assurance

of high quality products suitable for usual commercial applica-

tions. MOSEL VITELIC does not do testing appropriate to provide

100% product quality assurance and does not assume any liabil-

ity for consequential or incidental arising from any use of its prod-

ucts. If such products are to be used in applications in which

personal injury might occur from failure, purchaser must do its

own quality assurance testing appropriate to such applications.

MOSEL VITELIC makes no commitment to update or keep cur-

rent the information contained in this document. No part of this

document may be copied or reproduced in any form or by any

means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC ^{3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461}

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