V62C21164096LL-70T [MOSEL]
256K x 16, 0.20 um CMOS STATIC RAM; 256K ×16 ， 0.20微米CMOS静态RAM
| 型号： | V62C21164096LL-70T |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 256K x 16, 0.20 um CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V62C21164096
256K x 16, 0.20 µm CMOS STATIC RAM
Features
Description
■ High-speed: 70, 85 ns
■ Ultra low CMOS standby current of 4µA (max.)
■ Fully static operation
■ All inputs and outputs directly TTL compatible
■ Three state outputs
The V62C21164096 is a 4,194,304-bit static
random-access memory organized as 262,144
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
■ Ultra low data retention current (V
■ Operating voltage: 2.3V – 3.0V
■ Packages
= 1.2V)
CC
– 44-pin TSOP (Standard)
– 48-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
A0
VCC
GND
A6
A7
A8
A9
Row
Decoder
1024 x 4096
Memory Array
I/O1
Column I/O
Input
Data
Circuit
Column Decoder
I/O16
A10
A17
UBE
LBE
OE
WE
CE1
CE2
Control
Circuit
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
•
B
•
70
•
85
•
L
LL
•
0°C to 70°C
•
Blank
I
–40°C to +85°C
•
•
•
•
•
V62C21164096 Rev. 1.6 October 2001
1
V62C21164096
UBE, LBE Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
Pin Descriptions
A –A Address Inputs
These 18 address inputs select one of the 256K x
16 bit segments in the RAM.
0
17
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
CE , CE * Chip Enable Inputs
1
2
CE is active LOW and CE is active HIGH. Both
1
2
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O –I/O
Data Input and Data Output Ports
1
16
These 16 bidirectional ports are used to read data
from and write data into the RAM.
OE
Output Enable Input
The output enable input is active LOW. With chip
enabled, when OE is Low and WE High, data will
be presented on the I/O pins. The I/O pins will be in
the high impedance state when OE is High.
V
Power Supply
Ground
CC
GND
*CE is available on BGA package only.
2
Pin Configurations (Top View)
44-Pin TSOP-II (Standard)
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UBE
LBE
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O12
I/O11
I/O10
I/O9
NC
CE1
I/O1
I/O2
I/O3
I/O4
VCC
GND
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
A16
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
A17
48 BGA
1
2
3
4
5
6
1
2
3
4
5
6
BLE OE A0 A1 A2 CE2
I/O9 BHE A3 A4 CE1 I/O1
I/O10 I/O11 A5 A6 I/O2 I/O3
VSS I/O12 A17 A7 I/O4 VCC
A
B
C
A
B
C
D
E
F
D
VCC I/O13 NC A16 I/O5 VSS
I/O15 I/O14 A14 A15 I/O6 I/O7
I/O16 NC A12 A13 WE I/O8
E
F
G
G
NC
A8 A9 A10 A11 NC
H
H
Note: NC means no connect.
TOP VIEW
TOP VIEW
V62C21164096 Rev. 1.6 October 2001
2
V62C21164096
Part Number Information
V
62
C
21
16 4096
–
MOSEL-VITELIC
MANUFACTURED
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
4096K
SPEED
PKG
BLANK = 0°C to 70°C
I = -40°C to +85°C
PWR.
62 = STANDARD
70 ns
85 ns
C = CMOS PROCESS
T = TSOP STANDARD
B = BGA
21 = 2.3V–3.0V
ORGANIZATION
L = LOW POWER
LL = DOUBLE LOW POWER
16 = 16-bit
Absolute Maximum Ratings (1)
Symbol
Parameter
Supply Voltage
Input Voltage
Commercial
Industrial
Units
V
V
-0.5 to V
-0.5 to V
+ 0.5
+ 0.5
-0.5 to V
+ 0.5
CC
CC
CC
CC
CC
V
N
-0.5 to V
+ 0.5
V
V
Input/Output Voltage Applied
Temperature Under Bias
Storage Temperature
V
+ 0.3
V
+ 0.3
V
DQ
CC
CC
T
-10 to +125
-55 to +125
-65 to +135
-65 to +150
°C
°C
BIAS
T
STG
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance* T = 25°C, f = 1.0MHz
A
Symbol Parameter
Conditions Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
VI/O = 0V
6
8
pF
pF
COUT
NOTE:
1. This parameter is guaranteed and not tested.
Truth Table
I/O9-16
I/O1-8
Mode
Standby
CE
H
X
L
CE
X
OE
X
X
X
H
L
WE UBE LBE Operation Operation
1
2
X
X
X
H
H
H
H
L
X
X
H
X
L
X
X
H
X
L
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
Standby
L
Output Disable
Output Disable
Read
H
H
H
H
H
H
H
H
L
L
D
D
OUT
OUT
Read
L
L
L
H
L
D
High Z
OUT
Read
L
L
H
L
High Z
D
OUT
Write
Write
L
X
X
X
L
D
D
IN
IN
L
L
L
H
L
D
High Z
IN
Write
L
L
H
High Z
D
IN
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C21164096 Rev. 1.6 October 2001
3
V62C21164096
DC Electrical Characteristics (over all temperature ranges, V = 2.3V – 3.0V)
CC
Symbol Parameter
Test Conditions
Min.
-0.3
2.0
-1
Typ.
—
Max.
Units
V
(1,2)
(1)
VIL
VIH
IIL
Input LOW Voltage
0.4
Input HIGH Voltage
—
V
+ 0.3
V
CC
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
VCC = Max, VIN = 0V to VCC
VCC = Max, CE = VIH, VOUT = 0V to VCC
VCC = Min, IOL = 2.1mA
—
1
µA
µA
V
IOL
-1
—
1
VOL
VOH
—
—
0.4
—
VCC = Min, IOH = -0.5mA
V
– 0.4
—
V
CC
Symbol Parameter
ICC1 Average Operating Current, CE1 = VIL, CE2 = VCC – 0.2V, Output Open,
Power Com.(3) Ind.(3)
Units
f = fmax
35
4
40
5
mA
V
CC = Max.
f = 1 MHz
ISB
TTL Standby Current
L
0.5
0.3
10
4
1
mA
CE ≥ VIH, VCC = Max., f = 0
LL
L
1
ISB1
CMOS Standby Current, CE1 ≥ VCC – 0.2V, CE2 < 0.2V
15
6
µA
V
IN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max., f = 0
LL
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. IL (Min.) = -3.0V for pulse width < 20ns.
V
3. Maximum values.
AC Test Conditions
Key to Switching Waveforms
Input Pulse Levels
0 to 2.0V
5 ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Timing Reference Levels
Output Load
MUST BE
STEADY
WILL BE
STEADY
1.1V
see below
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
AC Test Loads and Waveforms
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
TTL
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
CL*
CENTER
DOES NOT
APPLY
LINE IS HIGH
IMPEDANCE
“OFF” STATE
* Includes scope and jig capacitance
CL = 30 pF + 1 TTL Load
V62C21164096 Rev. 1.6 October 2001
4
V62C21164096
Data Retention Characteristics
Symbol
Parameter
Power
Min.
Typ.(2)
Max.
Units
VDR
VCC for Data Retention
1.2
—
3.0
V
CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V
ICCDR
Data Retention Current
Com’l
L
LL
L
—
—
—
—
1
0.5
—
—
—
—
3
2
µA
CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, VDR = 1.2V
Ind.
5
LL
4
tCDR
tR
NOTES:
Chip Deselect to Data Retention Time
0
—
—
ns
ns
(1)
Operation Recovery Time (see Retention Waveform)
t
RC
1.
2.
t
T
RC = Read Cycle Time
A = +25°C.
Low VCC Data Retention Waveform (CE Controlled)
Data Retention Mode
DR ≥ 1.2V
VCC
CE1
2.3V
tCDR
2.3V
V
tR
CE1 ≥ VCC – 0.2V
2.0V
2.0V
V62C21164096 Rev. 1.6 October 2001
5
V62C21164096
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
70
85
Parameter
Name
Parameter
Min.
70
—
—
—
—
10
10
5
Max.
—
Min.
85
—
—
—
—
10
10
10
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
—
85
85
85
35
—
—
—
30
30
30
—
RC
Address Access Time
70
70
70
35
—
AA
Chip Enable Access Time
UBE, LBE Access Time
ACS
BA
Output Enable to Output Valid
Chip Enable to Output in Low Z
UBE, LBE to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
UBE, LBE to Output in High Z
Output Hold from Address Change
OE
CLZ
BLZ
OLZ
CHZ
OHZ
BHZ
OH
—
—
0
25
25
25
—
0
0
0
0
5
10
Write Cycle
70
85
Parameter
Name
Parameter
Min.
70
60
0
Max.
—
Min.
85
70
0
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Write Cycle Time
WC
t
Chip Enable to End of Write
Address Setup Time
—
—
CW
t
—
—
AS
t
Address Valid to End of Write
Write Pulse Width
60
50
0
—
70
60
0
—
AW
t
—
—
WP
t
Write Recovery Time
Write to Output High-Z
Data Setup to End of Write
Data Hold from End of Write
UBE, LBE to End of Write
—
—
WR
t
0
20
—
0
25
—
WHZ
t
35
0
40
0
DW
t
—
—
DH
t
60
—
70
—
BW
V62C21164096 Rev. 1.6 October 2001
6
V62C21164096
Switching Waveforms (Read Cycle)
(1, 2, 7)
Read Cycle 1
tRC
ADDRESS
OE
tAA
tOE
(5)
tOHZ
tOLZ
tBLZ
tBHZ
UBE, LBE
I/O
tBA
(1, 2, 4, 6, 7)
Read Cycle 2
tRC
ADDRESS
tAA
tOH
tOH
I/O
(1, 3, 4, 6, 7)
Read Cycle 3
ADDRESS
tACS
CE1
CE2
I/O
(5)
tCHZ
(5)
tCLZ
NOTES:
1. WE = VIH
.
2. CE1 = VIL. CE2 = VIH
.
3. Address valid prior to or coincident with CE transition LOW.
4. OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested.
6. UBE = VIL, LBE = VIL.
7. CE2 is offered on BGA package only.
V62C21164096 Rev. 1.6 October 2001
7
V62C21164096
Switching Waveforms (Write Cycle)
(4, 7)
Write Cycle 1 (WE Controlled)
tWC
ADDRESS
(2)
tWR
(6)
tCW
CE1
CE2
tAW
(6)
tCW
tAS
WE
(1)
tWP
OUTPUT
tDW
tDH
tWHZ
INPUT
Write Cycle 2 (CE Controlled)
ADDRESS
(4, 7)
tWC
(2)
tWR
(6)
tCW
(4)
CE1
CE2
WE
tAW
(6)
tCW
tAS
High-Z
OUTPUT
INPUT
tDW
tDH
(5)
NOTES:
1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2.
tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6.
tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
7. CE2 is available on BGA package only.
V62C21164096 Rev. 1.6 October 2001
8
V62C21164096
Package Diagrams
44-pin 400 mil TSOP-II
+0.004
-0.002
0.006
0.15
+0.01
-0.05
44
23
0.020 ± 0.006
[0.50 ± .019]
1
22
0°–5°
0.741[18.81] MAX
0.725 ± 0.004
[18.41 ± 0.10]
0.047 [1.20] MAX
0.004 MAX
Unit in inches [mm]
0.014 ± 0.004
[0.35 ± 0.10]
0.000 [0.0] MIN
0.031
[0.80]
0.032
[0.80]
48 Ball—8x10 BGA
D
SYMBOL
UNIT.MM
D1
A
A1
b
1.05+0.15
0.25±0.05
0.35±.0.05
0.30(TYP)
10.00±0.10
5.25
6
5
4
3
2
c
D
D1
E
8.00±0.10
3.75
E1
e
0.75TYP
0.10
aaa
1
A
B
C
D
E
F
G
H
b
SOLDER BALL
BOTTOM VIEW
aaa
SIDE VIEW
V62C21164096 Rev. 1.6 October 2001
9
WORLDWIDE OFFICES
V62C21164096
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
NO 19 LI HSIN ROAD
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-352-3775
FAX: 214-904-9029
© Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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