V62C2162048L-70T [MOSEL]
Ultra Low Power 128K x 16 CMOS SRAM; 超低功耗128K ×16的CMOS SRAM
| 型号： | V62C2162048L-70T |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | Ultra Low Power 128K x 16 CMOS SRAM |
| 文件： | 总13页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V62C2162048L(L)
Ultra Low Power
128K x 16 CMOS SRAM
Features
Functional Description
• Low-power consumption
The V62C2162048L is a Low Power CMOS Static
RAM organized as 131,072 words by 16 bits. Easy
memory expansion is provided by an active LOW (CE)
and (OE) pin.
- Active: 65mA I
at 35ns
CC
- Stand-by: 10 mA (CMOS input/output)
2 mA (CMOS input/output, L version)
• 35/45/55/70/85/100 ns access time
• Equal access and cycle time
• Single +2.2V to 2.7V Power Supply
• Tri-state output
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
• Automatic power-down when deselected
• Multiple center power and ground pins for
improved noise immunity
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
• Individual byte controls for both Read and
Write cycles
• Available in 44 pin TSOP II / 48-fpBGA
Logic Block Diagram
TSOPII / 48-fpBGA
Pre-Charge Circuit
A0
A1
A2
A3
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
Vcc
Vss
A4
Memory Array
A5
A6
BHE
BLE
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
CE
1024 X 2048
A7
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
A8
A9
Data
Cont
I/O1 - I/O8
I/O Circuit
Data
Cont
I/O9 - I/O16
Column Select
A10 A11 A12 A13 A14 A15 A16
A8
A9
A10
A11
NC
WE
OE
BHE
BLE
CE
1
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
MOSEL VITELIC V62C2162048L(L)B
1
2
3
4
5
6
1
2
3
4
5
6
BLE
I/O9
I/O10
VSS
VCC
I/O15
OE
A0
A1
A2
NC
I/O1
I/O3
A
B
C
BHE
I/O11
I/O12
I/O13
I/O14
A3
A4
CE
I/O2
A5
A6
NC
NC
A14
A7
I/O4 VCC
D
E
A16
A15
I/O5
I/O6
VSS
I/O7
F
G
H
I/O16
NC
NC
A8
A12
A9
A13
A10
WE
A11
I/O8
NC
Note: NC means no Ball.
Top View
Top View
48 Ball - 9x12 fpBGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SYMBOL
UNIT:MM
1.05+0.15
0.25+0.05
0.35+.05
0.30(TYP)
12.00+0.10
5.25
A
A1
b
aaa
SIDE VIEW
c
D
D
D1
D1
E
9.00+0.10
3.75
6
E1
e
0.75TYP
0.10
5
aaa
4
3
2
1
A
B
C
D
E
F
G
H
b
BOTTOM VIEW
SOLDER BALL
2
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Absolute Maximum Ratings *
Parameter
Symbol Minimum Maximum
Unit
Voltage on Any Pin Relative to Gnd
Power Dissipation
Vt
PT
-0.5
-
+4.6
1.0
V
W
0
Storage Temperature (Plastic)
Tstg
-55
+150
C
0
Temperature Under Bias
Tbias
-40
+85
C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE
H
L
OE WE BLE BHE I/O1-I/O8 I/O9-I/O16
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Mode
X
L
X
H
H
H
L
X
L
X
H
L
High-Z
Data Out
High-Z
High-Z
High-Z
Standby
Low Byte Read
High Byte Read
Word Read
L
L
H
L
Data Out
Data Out
Data In
High-Z
L
L
L
Data Out
Data In
Data In
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Output Disable
Output Disable
L
L
H
X
H
Data In
High-Z
L
H
X
X
H
High-Z
L
High-Z
High-Z
* Key: X = Don’t Care, L = Low, H = High
0
0
0
0
Recommended Operating Conditions (T = 0 C to +70 C / -40 C to 85 C**)
A
Parameter
Symbol
Min
2.2
Typ
Max
2.7
Unit
V
2.5
0.0
-
V
V
V
V
CC
Supply Voltage
Gnd
0.0
0.0
V
2.2
V
+ 0.2
IH
CC
Input Voltage
V
-0.5*
-
0.8
IL
* V min = -1.0V for pulse width less than t /2.
IL
RC
** For Industrial Temperature
3
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
0
0
0
0
DC Operating Characteristics (V = 2.2 to 2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to 85 C)
cc
A
-55
-70
-85
-100
Parameter
Sym Test Conditions
Unit
Min Max Min Max Min Max Min Max
V = Max,
-
-
-
1
1
5
-
-
-
1
1
5
-
-
-
1
1
5
-
-
-
1
1
5
mA
Input Leakage Current
cc
II I
LI
V = Gnd to V
in
cc
CE = V or V = Max,
mA
Output Leakage
Current
IH
cc
IILOI
V
= Gnd to V
OUT
cc
CE = V , V = V or V ,
mA
Operating Power
Supply Current
ICC
IL
IN
IH
IL
I
=0
OUT
I
= 0mA,
-
-
50
3
-
-
45
3
-
-
40
3
-
-
40
3
mA
mA
Average Operating
Current
ICC1
ICC2
OUT
Min Cycle, 100% Duty
CE < 0.2V
I
= 0mA,
OUT
Cycle Time=1ms, Duty=100%
CE = V
-
0.5
-
0.5
-
0.5
-
0.5
mA
Standby Power Supply ISB
Current (TTL Level)
IH
CE > V - 0.2V
-
10
-
10
-
10
-
10
mA
mA
Standby Power Supply ISB1
Current (CMOS
Level)
cc
V < 0.2V or
IN
-
2
-
2
-
2
-
2
V > V - 0.2V
L
IN
OL
OH
cc
I
I
= 2 mA
-
0.4
-
-
0.4
-
-
0.4
-
-
0.4
-
V
V
Output Low Voltage
Output High Voltage
VOL
VOH
= -2 mA
2.4
2.4
2.4
2.4
o
Capacitance (f = 1MHz, T = 25 C)
A
Parameter*
Input Capacitance
Symbol
Cin
Test Condition
Max
7
Unit
pF
V = 0V
in
I/O Capacitance
CI/O
V = V = 0V
8
pF
in
out
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time 5ns
Input and Output Timing
Reference Level 1.4V
0.6V to 2.2V
TTL
CL
*
Output Load Condition
55ns/70ns/85ns
Load for 100ns
C = 30pf + 1TTL Load
CLL
Figure A.
* Including Scope and Jig Capacitance
= 100pf + 1TTL Load
4
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
0
0
0
0
DC Operating Characteristics (V = 2.2 to 2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to 85 C)
cc
A
-35
-45
Parameter
Sym Test Conditions
Unit
Min Max Min Max
V = Max,
-
-
-
1
1
5
-
-
-
1
1
5
mA
Input Leakage Current
cc
II I
LI
V = Gnd to V
in
cc
CE = V or V = Max,
mA
Output Leakage
Current
IH
cc
IILOI
V
= Gnd to V
OUT
cc
CE = V , V = V or V ,
mA
Operating Power
Supply Current
ICC
IL
IN
IH
IL
I
=0
OUT
I
= 0mA,
-
-
65
3
-
-
60
3
mA
mA
Average Operating
Current
ICC1
ICC2
OUT
Min Cycle, 100% Duty
CE < 0.2V
I
= 0mA,
OUT
Cycle Time=1ms, Duty=100%
CE = V
-
0.5
-
0.5
mA
Standby Power Supply
Current (TTL Level)
ISB
IH
CE > V - 0.2V
-
10
-
10
mA
mA
Standby Power Supply
Current (CMOS
Level)
ISB1
cc
V < 0.2V or
IN
-
2
-
2
V > V - 0.2V
L
IN
OL
OH
cc
I
I
= 2 mA
-
0.4
-
-
0.4
-
V
V
Output Low Voltage
Output High Voltage
VOL
VOH
= -2 mA
2.4
2.4
5
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
0
0
0
0
Read Cycle (9) (V = 2.2 to 2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
Note
Unit
Parameter
Sym
-55
-70
-85
-100
Min Max Min Max Min Max Min Max
t
55
-
-
70
-
-
85
-
-
100
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
RC
t
55
55
35
-
70
70
40
-
85
85
40
-
-
-
Address Access Time
AA
t
-
-
-
Chip Enable Access Time
ACE
t
-
-
-
-
Output Enable Access Time
OE
t
10
10
-
10
10
-
10
10
-
10
10
-
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
BLE, BHE Enable to Output in Low-Z
BLE, BHE Disable to Output in High-Z
BLE, BHE Access Time
OH
t
-
-
-
-
4,5
LZ
t
25
-
30
-
35
-
40
-
3,4,5
HZ
t
5
-
5
-
5
-
5
-
OLZ
t
25
-
25
-
30
-
35
-
OHZ
t
5
-
5
-
5
-
5
-
4,5
BLZ
t
25
35
25
40
30
40
35
50
3,4,5
BHZ
t
-
-
-
-
BA
0
0
0
0
Write Cycle (11) (V = 2.2 to2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
Note
Unit
Parameter
Symbol
-55
-70
-85
-100
Min Max Min Max Min Max Min Max
t
55
50
50
0
-
-
70
60
60
0
-
-
85
70
70
0
-
-
100
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
WC
t
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
CW
t
-
-
-
-
AW
t
-
-
-
-
AS
t
45
0
-
50
0
-
60
0
-
70
0
-
Write Pulse Width
WP
t
-
-
-
-
Write Recovery Time
WR
t
25
0
-
30
0
-
35
0
-
40
0
-
Data Valid to Write End
Data Hold Time
DW
t
-
-
-
-
DH
t
-
25
-
-
30
-
-
35
-
-
40
-
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
WHZ
t
5
5
5
5
OW
t
50
-
60
-
70
-
80
-
BW
6
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
0
0
0
0
Read Cycle (9) (V = 2.2 to 2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
Note
Unit
Parameter
Sym
-35
-45
Min Max Min Max
t
35
-
-
45
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
RC
t
35
35
20
-
45
45
25
-
Address Access Time
AA
t
-
-
Chip Enable Access Time
ACE
t
-
-
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
BLE, BHE Enable to Output in Low-Z
BLE, BHE Disable to Output in High-Z
BLE, BHE Access Time
OE
t
5
5
-
5
5
-
OH
t
-
-
4,5
LZ
t
15
-
20
-
3,4,5
HZ
t
5
-
5
-
OLZ
t
15
-
20
-
OHZ
t
5
-
5
-
4,5
BLZ
t
15
20
20
25
3,4,5
BHZ
t
-
-
BA
0
0
0
0
Write Cycle (11) (V = 2.2 to 2.7V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
Note
Unit
Parameter
Sym
-35
-45
Min Max Min Max
t
35
30
30
0
-
-
45
35
35
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
WC
t
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
CW
t
-
-
AW
t
-
-
AS
t
30
0
-
35
0
-
Write Pulse Width
WP
t
-
-
Write Recovery Time
WR
t
20
0
-
25
0
-
Data Valid to Write End
Data Hold Time
DW
t
-
-
DH
t
-
25
-
-
25
-
Write Enable to Output in High-Z
Output Active from Write End
BLE, BHE Setup to Write End
WHZ
t
5
5
OW
t
30
-
35
-
BW
7
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Timing Waveform of Read Cycle 1
(Address Controlled)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle 2
tRC
Address
tAA
tHZ(3,4,5)
tACE
CE
tLZ(4,5)
tBA
tBHZ(3,4,5)
(BLE/BHE)
tBLZ(4,5)
tOHZ
tOE
OE
tOH
tOLZ
High-Z
Data Valid
Data Out
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V .
IL
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
8
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Timing Waveform of Write Cycle 1
(Address Controlled)
tWC
Address
tAW
tWR (5)
tCW (3)
tBW
CE
BLE/BHE
tAS (4)
tWP (2)
WE
tDW
tDH
High-Z
Data In
tOHZ (6)
tOW
High-Z (8)
Data Out
Timing Waveform of Write Cycle 2
(CE Controlled)
tWC
Address
tAW
tWR (5)
tCW (3)
CE
tAS (4)
tBW
BLE/BHE
WE
tWP (2)
tDW
tDH
High-Z
Data In
tWHZ (6)
tLZ
High-Z
High-Z (8)
Data Out
Timing Waveform of Write Cycle 3
(BLE/BHE Controlled)
tWC
Address
tAW
tWR (5)
tCW (3)
CE
tAS (4)
tBW
BLE/BHE
WE
tWP (2)
tDW
tDH
High-Z
Data In
tWHZ (6)
tBLZ
High-Z
High-Z (8)
Data Out
9
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Notes (Write Cycle)
1. All write timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going
low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning
of write to the end of write.
3. tCW is measured from the later of CE going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change.
6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should
not be applied.
11. For test conditions, see AC Test Condition, Figure A.
10
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Data Retention Characteristics (L Version Only)(1)
Parameter
Symbol
VDR
Test Condition
Min
Max Unit
-
VCC for Data Retention
CE > VCC - 0.2V
2.0
-
V
Data Retention Current
ICCDR
tCDR
1
-
mA
ns
Chip Deselect to Data Retention Time
Operation Recovery Time(2)
VIN > VCC - 0.2V or
VIN < 0.2V
0
tR
tRC
-
ns
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Mode
VCC
Vcc_typ
V
>
2.0V
Vcc_typ
DR
tCDR
tR
CE
V
V
V
IH
DR
IH
Notes (Write Cycle)
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is High for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
11
REV. 1.3 OCT 2001 V62C2162048L(L)
V62C2162048L(L)
Ordering Information
Device Type*
Speed
Package
44-pin TSOP Type 2
V62C2162048L-35T
V62C2162048L-45T
V62C2162048L-55T
V62C2162048L-70T
V62C2162048L-85T
V62C2162048L-100T
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
V62C2162048LL-35T
V62C2162048LL-45T
V62C2162048LL-55T
V62C2162048LL-70T
V62C2162048LL-85T
V62C2162048LL-100T
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
V62C2162048L(L)-35B
V62C2162048L(L)-45B
V62C2162048L(L)-55B
V62C2162048L(L)-70B
V62C2162048L(L)-85B
V62C2162048L(L)-100B
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
48-fpBGA
* For Industrial temperature tested devices, an “I” designator will be added to the end of the device number.
12
REV. 1.3 OCT 2001 V62C2162048L(L)
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MOSEL VITELIC WORLDWIDE OFFICES
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
NO 19 LI HSIN ROAD
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-826-6176
FAX: 214-828-9754
© Copyright 2001, MOSEL VITELIC Inc.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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