V62C3802048L-45V [MOSEL]
Ultra Low Power 256K x 8 CMOS SRAM; 超低功耗256K ×8 CMOS SRAM
| 型号： | V62C3802048L-45V |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | Ultra Low Power 256K x 8 CMOS SRAM |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V62C3802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
Functional Description
The V62C3802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an acti-
ve LOW OE , and Tri-state I/O’s. This device has an autom-
atic power-down mode feature when deselected.
- Active: 40mA at 35ns
- Stand-by: 10 mA (CMOS input/output)
2 mA CMOS input/output, L version
• Single + 2.7 to 3.3V Power Supply
• Equal access and cycle time
Writing to the device is accomplished by taking Chip En-
able 1 (CE1) with Write Enable (WE) LOW, and Chip Enab-
le 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance sta-
te when the device is deselected: the outputs are disabled d-
uring a write cycle.
• 35/45/55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
The V62C3802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C3802048L is available in
a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type
48-fpBGA packages.
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
• 48 Ball CSP_BGA
32-Pin TSOP1 / STSOP(CSP_BGA see next page)
Logic Block Diagram
A11
A9
OE
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A8
3
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
4
INPUT BUFFER
5
A
0
6
A
A
1
2
7
8
I/O8
I/O1
A
A
3
4
9
10
11
12
13
14
15
16
A
A
5
6
Cell Array
A6
A1
A
A
7
8
A5
A2
A4
A3
A9
OE
COLUMN DECODER
WE
CE1
CE2
CONTROL
CIRCUIT
A10
A
11
A12
A
13
A
14
A
15
A
16
A17
1
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
MOSEL VITELIC V62C3802048L(L)B
1
2
3
4
5
6
1
2
3
4
5
6
A0
A1
A2
NC
NC
NC
NC
CS2
WE
NC
NC
NC
NC
A3
A6
A7
NC
NC
NC
NC
A8
A
B
I/O5
I/O6
VSS
VCC
I/O7
A4
I/O1
I/O2
VCC
VSS
I/O3
C
A5
NC
NC
A17
D
E
F
G
H
I/O8
A9
OE
CS1
A11
A16
A12
A15
A13
I/O4
A14
A10
Note: NC means no Ball.
Top View
Top View
48 Ball - 9x12 fpBGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SYMBOL
UNIT:MM
1.05+0.15
0.25+0.05
0.35+.05
0.30(TYP)
12.00+0.10
5.25
A
A1
b
aaa
SIDE VIEW
c
D
D
D1
D1
E
9.00+0.10
3.75
6
E1
e
0.75TYP
0.10
5
aaa
4
3
2
1
A
B
C
D
E
F
G
H
b
BOTTOM VIEW
SOLDER BALL
2
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
Absolute Maximum Ratings *
Parameter
Symbol Minimum Maximum
Unit
Voltage on Any Pin Relative to Gnd
Power Dissipation
Vt
-0.5
4.6
1.0
V
P
-
W
T
0
Storage Temperature (Plastic)
Temperature Under Bias
Tstg
-55
-40
+150
+85
C
0
Tbias
C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE1
CE2
WE
OE
X
Data
High-Z
High-Z
Data Out
High-Z
Data In
Mode
H
X
L
L
L
X
L
X
X
H
H
L
Standby
X
Standby
H
H
H
L
Active, Read
H
Active, Output Disable
Active, Write
X
* Key: X = Don’t Care, L = Low, H = High
0
0
0
0
Recommended Operating Conditions (T = 0 C to +70 C / -40 C to 85 C**)
A
Parameter
Symbol
Min
2.7
Typ
Max
3.3
Unit
V
3.0
0.0
-
V
V
V
V
CC
Supply Voltage
Gnd
0.0
0.0
V
2.2
V
+ 0.2
IH
CC
Input Voltage
V
-0.5*
-
0.6
IL
* V min = -2.0V for pulse width less than t /2.
IL
RC
** For Industrial Temperature.
3
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
0
0
0
0
DC Operating Characteristics (V = 2.7 to 3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to 85 C)
cc
A
-55
-70
-85
-100
Parameter
Sym Test Conditions
Unit
Min Max Min Max Min Max Min Max
V = Max,
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
-
-
-
1
1
3
mA
Input Leakage Current
cc
II I
LI
V = Gnd to V
in
cc
CE1 = V or CE2 = V
mA
Output Leakage
Current
IH
IL
IILOI
V = Max, V
= Gnd to V
cc
OUT
cc
CE1 = V , CE2 = V
mA
Operating Power
Supply Current
ICC
IL
IH
V =V orV ,I =0mA
IN
IH
IL OUT
CE1 = V , CE2 = V
-
-
35
3
-
-
35
3
-
-
30
3
-
-
25
3
mA
mA
ICC1
IL
IH
Average Operating
Current
I
= 0mA,
OUT
Min Cycle, 100% Duty
CE1 = 0.2V ,
ICC2
CE2 =V - 0.2V
cc
I
= 0mA,
OUT
Cycle Time=1ms, 100% Duty
CE1 = V or CE2 = V
-
-
0.5
10
-
-
0.5
10
-
-
0.5
10
-
-
0.5
10
mA
Standby Power Supply ISB
IH
IL
Current (TTL Level)
CE1 > V - 0.2V or
mA
Standby Power Supply ISB1
Current (CMOS Level)
cc
CE2 < 0.2V, f = 0
V < 0.2V or
IN
-
-
2
0.4
-
-
-
2
0.4
-
-
-
2
0.4
-
-
-
2
0.4
-
mA
V
V > V - 0.2V
L
IN
OL
OH
cc
I
I
= 2 mA
Output Low Voltage
Output High Voltage
VOL
VOH
= -2 mA
2.4
2.4
2.4
2.4
V
0
Capacitance (f = 1MHz, T = 25 C)
A
Parameter*
Input Capacitance
Symbol
Cin
Test Condition
Max
7
Unit
pF
V = 0V
in
I/O Capacitance
CI/O
V = V = 0V
8
pF
in
out
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.6V to 2.2V
5ns
CL
*
50% of input level
(VIL+VIH)/2
Output Load Condition
70ns/85 ns CL = 30pf + 1TTL Load
Load 100ns/120 ns CL = 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
4
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
0
0
0
0
DC Operating Characteristics (V = 2.7 to 3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to 85 C)
cc
A
-35
-45
Parameter
Sym Test Conditions
Unit
Min Max Min Max
V = Max,
-
-
-
1
1
3
-
-
-
1
1
3
mA
Input Leakage Current
cc
II I
LI
V = Gnd to V
in
cc
CE1 = V or CE2 = V
IL
mA
Output Leakage
Current
IILOI
IH
V = Max, V
= Gnd to V
cc
OUT
cc
CE1 = V , CE2 = V
mA
Operating Power
Supply Current
ICC
IL
IH
V =V orV ,I =0mA
IN
IH
IL OUT
CE1 = V , CE2 = V
-
-
40
3
-
-
40
3
mA
mA
ICC1
IL
IH
Average Operating
Current
I
= 0mA,
OUT
Min Cycle, 100% Duty
CE1 = 0.2V ,
ICC2
CE2 =V - 0.2V
cc
I
= 0mA,
OUT
Cycle Time=1ms, 100% Duty
CE1 = V or CE2 = V
-
-
0.5
10
-
-
0.5
10
mA
Standby Power Supply ISB
IH
IL
Current (TTL Level)
CE1 > V - 0.2V or
mA
Standby Power Supply ISB1
Current (CMOS Level)
cc
CE2 < 0.2V, f = 0
V < 0.2V or
IN
-
-
2
0.4
-
-
-
2
0.4
-
mA
V
V > V - 0.2V
L
IN
OL
OH
cc
I
I
= 2 mA
Output Low Voltage
Output High Voltage
VOL
VOH
= -2 mA
2.4
2.4
V
5
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
0
0
0
0
Read Cycle (3,9) (V = 2.7 to3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
Note
Unit
Parameter
Symbol
-55
-70
-85
-100
Min Max Min Max Min Max Min Max
t
55
-
-
55
55
40
-
70
-
-
70
70
40
-
85
-
-
85
85
40
-
100
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
RC
t
-
-
Address Access Time
AA
t
-
-
-
Chip Enable Access Time
Output Enable Access Time
OutputHold fromAddress Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
ACE
t
-
-
-
-
OE
t
10
10
-
10
10
-
10
10
-
10
10
-
OH
t
-
-
-
-
4,5
4,5
4,5
4,5
5
CLZ
t
25
-
30
-
35
-
40
-
CHZ
t
5
-
5
-
5
-
5
-
OLZ
t
20
-
25
-
30
-
35
-
OHZ
t
0
-
0
-
0
-
0
-
PU
t
55
70
85
100
5
Power-Down Time
PD
0
0
0
0
Write Cycle (3,11) (V = 2.7 to 3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
A
cc
Note
Unit
Parameter
Symbol
-55
-70
-85
-100
Min Max Min Max Min Max Min Max
t
55
40
40
0
-
-
70
60
60
0
-
-
85
70
70
0
-
-
100
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Chip Enable to Write End
WC
t
CW
t
-
-
-
-
Address Setup to Write End
Address Setup Time
AW
t
-
-
-
-
AS
t
40
0
-
50
0
-
60
0
-
70
0
-
Write Pulse Width
WP
t
-
-
-
-
Write Recovering Time
Data Valid to Write End
Data Hold Time
WR
t
25
0
-
30
0
-
35
0
-
40
0
-
DW
t
-
-
-
-
DH
t
-
25
-
-
30
-
-
35
-
-
40
-
4,5
4,5
Write Enable to Output in High-Z
Output Active from Write End
WZ
t
5
5
5
5
OW
6
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
0
0
0
0
Read Cycle (3,9) (V = 2.7 to3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
cc
A
-35
-45
Note
Unit
Parameter
Symbol
Min Max Min Max
t
35
-
-
45
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
RC
t
35
35
20
-
45
45
20
-
Address Access Time
AA
t
-
-
Chip Enable Access Time
Output Enable Access Time
OutputHold fromAddress Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
ACE
t
-
-
OE
t
5
5
-
5
5
-
OH
t
-
-
4,5
4,5
4,5
4,5
5
CLZ
t
20
-
25
-
CHZ
t
5
-
5
-
OLZ
t
15
-
20
-
OHZ
t
0
-
0
-
PU
t
35
45
5
Power-Down Time
PD
0
0
0
0
Write Cycle (3,11) (V = 2.7 to 3.3V, Gnd = 0V, T = 0 C to +70 C / -40 C to +85 C)
A
cc
-35
-45
Note
Unit
Parameter
Symbol
Min Max Min Max
t
35
30
30
0
-
-
45
40
40
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
WC
t
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
CW
t
-
-
AW
t
-
-
AS
t
30
0
-
35
0
-
Write Pulse Width
WP
t
-
-
Write Recovering Time
Data Valid to Write End
Data Hold Time
WR
t
20
0
-
25
0
-
DW
t
-
-
DH
t
-
20
-
-
25
-
4,5
4,5
Write Enable to Output in High-Z
Output Active from Write End
WZ
t
5
5
OW
7
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
tRC
Address
tAA
tOH
DOUT
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled)
tRC
CE1
tOE
OE
tOHZ
tCHZ
tOLZ
tACE
DOUT
Data Valid
tPD
tCLZ
tPU
ICC
ISB
Supply Current
50%
50%
Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled)
tRC
CE2
tOE
OE
tOHZ
tCHZ
tOLZ
tACE
DOUT
Data Valid
tPD
tCLZ
tPU
ICC
ISB
Supply Current
50%
50%
8
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
Timing Waveform of Write Cycle 1 (10,11) (WE Controlled)
tWC
tAW
tWR
Address
tWP
WE
tAS
tDW
tDH
DIN
Data Valid
tWZ
tOW
DOUT
(10,11) (CE1 Controlled)
Timing Waveform of Write Cycle 2
tWC
tAW
tWR
Address
tAS
tCW
CE1
tWP
WE
tWZ
tDW
tDH
DIN
Data Valid
DOUT
Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled)
tWC
tAW
tWR
Address
tAS
tCW
CE2
WE
tWP
tWZ
tDW
tDH
DIN
Data Valid
DOUT
9
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
Data Retention Characteristics (L Version Only)(1)
Parameter
Symbol
VDR
Test Condition
Min
Max Unit
-
V
for Data Retention
CE > VCC - 0.2V or
1.0
V
CC
1
Data Retention Current
ICCDR
CE < + 0.2V
mA
2
-
1
Chip Deselect to Data Retention Time
Operation Recovery Time(2)
tCDR
tR
VIN > VCC - 0.2V or
VIN < 0.2V
0
-
-
ns
ns
t
RC
0
0
0
0
Data Retention Waveform (L Version Only) (T = 0 C to +70 C / -40 C to +85 C)
A
Data Retention Mode
VCC
Vcc_typ
V
>
1.0V
Vcc_typ
DR
tCDR
tR
CE
V
V
V
IH
DR
IH
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
10
REV. 1.2 May 2001 V62C3802048L(L)
V62C3802048L(L)
Ordering Information
Device Type*
Speed
Package
8x13.4 mm 32-pin Plastic STSOP
V62C3802048L-35V
V62C3802048L-45V
V62C3802048L-55V
V62C3802048L-70V
V62C3802048L-85V
V62C3802048L-100V
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
V62C3802048LL-35V
V62C3802048LL-45V
V62C3802048LL-55V
V62C3802048LL-70V
V62C3802048LL-85V
V62C3802048LL-100V
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
V62C3802048L-35T
V62C3802048L-45T
V62C3802048L-55T
V62C3802048L-70T
V62C3802048L-85T
V62C3802048L-100T
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
8 x 20 mm 32-pin Plastic TSOP1
V62C3802048LL-35T
V62C3802048LL-45T
V62C3802048LL-55T
V62C3802048LL-70T
V62C3802048LL-85T
V62C3802048LL-100T
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
V62C3802048L(L)-35B
V62C3802048L(L)-45B
V62C3802048L(L)-55B
V62C3802048L(L)-70B
V62C3802048L(L)-85B
V62C3802048L(L)-100B
35 ns
45 ns
55 ns
70 ns
85 ns
100 ns
CSP type 48-fpBGA
* For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device number.
11
REV. 1.2 May 2001 V62C3802048L(L)
MOSEL VITELIC WORLDWIDE OFFICES
V62C3802048L(L)
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
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JAPAN
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GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
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PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-826-6176
FAX: 214-828-9754
5/01
Printed in U.S.A.
© Copyright 2001, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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