BCW61BLT1 [MOTOROLA]
General Purpose Transistors; 通用晶体管
| 型号： | BCW61BLT1 |
| 厂家： | 
MOTOROLA |
| 描述： | General Purpose Transistors |
| 文件： | 总8页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by BCW61BLT1/D
SEMICONDUCTOR TECHNICAL DATA
PNP Silicon
COLLECTOR
3
1
BASE
3
2
EMITTER
1
MAXIMUM RATINGS
2
Rating
Collector–Emitter Voltage
Collector–Base Voltage
Symbol
Value
Unit
Vdc
V
CEO
–32
–32
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
V
Vdc
CBO
EBO
Emitter–Base Voltage
V
–5.0
–100
Vdc
Collector Current — Continuous
THERMAL CHARACTERISTICS
Characteristic
I
C
mAdc
Symbol
Max
Unit
(1)
Total Device Dissipation FR–5 Board
P
225
mW
D
T
= 25°C
A
Derate above 25°C
1.8
556
300
mW/°C
°C/W
mW
Thermal Resistance Junction to Ambient
Total Device Dissipation
R
JA
D
P
(2)
Alumina Substrate,
T
A
= 25°C
Derate above 25°C
2.4
417
mW/°C
°C/W
°C
Thermal Resistance Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
R
JA
T , T
J stg
–55 to +150
BCW61BLT1 = BB, BCW61CLT1 = BC, BCW61DLT1 = BD
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Max
Unit
Collector–Emitter Breakdown Voltage
V
–32
—
—
Vdc
Vdc
(BR)CEO
(I = –2.0 mAdc, I = 0)
C
B
Emitter–Base Breakdown Voltage
(I = –1.0 Adc, I = 0)
V
–5.0
(BR)EBO
E
C
Collector Cutoff Current
I
CES
(V
CE
(V
CE
= –32 Vdc)
= –32 Vdc, T = 150°C)
—
—
–20
–20
nAdc
µAdc
A
1. FR–5 = 1.0
0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Thermal Clad is a trademark of the Bergquist Company
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)
A
Characteristic
ON CHARACTERISTICS
Symbol
Min
Max
Unit
DC Current Gain
(I = –10 µAdc, V
C CE
h
FE
—
= –5.0 Vdc)
BCW61B
BCW61C
BCW61D
30
40
100
—
—
—
(I = –2.0 mAdc, V
= –5.0 Vdc)
= –1.0 Vdc)
BCW61B
BCW61C
BCW61D
140
250
380
310
460
630
C
CE
(I = –50 mAdc, V
C
BCW61B
BCW61C
BCW61D
80
100
100
—
—
—
CE
AC Current Gain
h
fe
—
(V
CE
= –5.0 Vdc, I = –2.0 mAdc, f = 1.0 kHz)
BCW61B
BCW61C
BCW61D
175
250
350
350
500
700
C
Collector–Emitter Saturation Voltage
(I = –50 mAdc, I = –1.25 mAdc)
V
V
Vdc
Vdc
Vdc
CE(sat)
—
—
–0.55
–0.25
C
B
(I = –10 mAdc, I = –0.25 mAdc)
C
B
Base–Emitter Saturation Voltage
(I = –50 mAdc, I = –1.25 mAdc)
BE(sat)
–0.68
–0.6
–1.05
–0.85
C
C
B
B
(I = –10 mAdc, I = –0.25 mAdc)
Base–Emitter On Voltage
(I = –2.0 mAdc, V = –5.0 Vdc)
V
BE(on)
–0.6
–0.75
C
CE
SMALL–SIGNAL CHARACTERISTICS
Output Capacitance
C
pF
dB
obo
(V
CE
= –10 Vdc, I = 0, f = 1.0 MHz)
—
—
6.0
6.0
C
Noise Figure
(V = –5.0 Vdc, I = –0.2 mAdc, R = 2.0 kΩ, f = 1.0 kHz, BW = 200 Hz)
NF
CE
C
S
SWITCHING CHARACTERISTICS
Turn–On Time
(I = –10 mAdc, I = –1.0 mAdc)
C
t
t
ns
ns
on
—
—
150
800
B1
Turn–Off Time
(I = –1.0 mAdc, V
B2
off
= –3.6 Vdc, R = R = 5.0 kΩ, R = 990 Ω)
1 2 L
BB
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TYPICAL NOISE CHARACTERISTICS
(V
= –5.0 Vdc, T = 25°C)
CE
A
10
7.0
5.0
1.0
7.0
5.0
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
R
≈ 0
S
R
≈∞
S
I = 1.0 mA
C
I
= 10
µA
3.0
2.0
C
300
100
µA
30
100
300
µA
1.0
3.0
2.0
µA
0.7
0.5
µA
µA
1.0 mA
0.3
0.2
30
10
µ
A
A
µ
1.0
0.1
10
20
50
100
200
500 1.0 k 2.0 k
5.0 k 10 k
10
20
50
100 200
500
1.0 k 2.0 k
5.0 k 10 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 1. Noise Voltage
Figure 2. Noise Current
NOISE FIGURE CONTOURS
(V
= –5.0 Vdc, T = 25°C)
CE
A
1.0 M
500 k
1.0 M
500 k
BANDWIDTH = 1.0 Hz
BANDWIDTH = 1.0 Hz
200 k
100 k
50 k
200 k
100 k
50 k
20 k
10 k
20 k
10 k
0.5 dB
0.5 dB
5.0 k
2.0 k
5.0 k
2.0 k
1.0 dB
1.0 dB
2.0 dB
2.0 dB
1.0 k
500
1.0 k
500
3.0 dB
5.0 dB
3.0 dB
200
100
200
100
5.0 dB
500 700 1.0 k
10
20 30
50 70 100
200 300
A)
500 700 1.0 k
10
20 30
50 70 100
200 300
I
, COLLECTOR CURRENT (
µ
I , COLLECTOR CURRENT (µ
C
A)
C
Figure 3. Narrow Band, 100 Hz
Figure 4. Narrow Band, 1.0 kHz
1.0 M
500 k
10 Hz to 15.7 kHz
200 k
100 k
Noise Figure is Defined as:
50 k
2
R
n S
2
1 2
2
e
n
4KTR
4KTR
I
S
20 k
10 k
NF
20 log
10
S
0.5 dB
e
= Noise Voltage of the Transistor referred to the input. (Figure 3)
= Noise Current of the Transistor referred to the input. (Figure 4)
n
5.0 k
2.0 k
I
n
1.0 dB
2.0 dB
–23
= Boltzman’s Constant (1.38 x 10
K
T
R
j/°K)
1.0 k
500
= Temperature of the Source Resistance (°K)
= Source Resistance (Ohms)
S
3.0 dB
5.0 dB
200
100
20
30
50 70 100
200 300
500 700 1.0 k
10
I
, COLLECTOR CURRENT (µA)
C
Figure 5. Wideband
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
TYPICAL STATIC CHARACTERISTICS
1.0
0.8
100
I
B
= 400 µA
T
= 25°C
T
= 25
BCW61
°
C
A
A
PULSE WIDTH = 300
DUTY CYCLE 2.0%
µ
s
350 µA
≤
80
60
300 µA
250
200
µA
I
= 1.0 mA
10 mA
50 mA
100 mA
C
0.6
0.4
0.2
0
µA
150 µA
40
20
0
100
50
µA
µA
0.002 0.005 0.01 0.02 0.05 0.1 0.2
0.5 1.0 2.0
5.0 10 20
0
5.0
10
15
20
25
30
35
40
I
, BASE CURRENT (mA)
V
, COLLECTOR–EMITTER VOLTAGE (VOLTS)
B
CE
Figure 6. Collector Saturation Region
Figure 7. Collector Characteristics
1.4
1.2
1.6
0.8
0
T
= 25°C
J
*APPLIES for I /I
C B
≤
h
/2
FE
1.0
0.8
0.6
0.4
25°C to 125°C
*
for V
CE(sat)
VC
–55°C to 25°C
V
@ I /I = 10
C B
BE(sat)
0.8
1.6
2.4
V
@ V = 1.0 V
CE
BE(on)
25°C to 125°C
–55°C to 25°C
for V
BE
0.2
0
VB
V
@ I /I = 10
C B
CE(sat)
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50 100
0.1
0.2
0.5
I
1.0
2.0
5.0
10
20
50
100
I
, COLLECTOR CURRENT (mA)
, COLLECTOR CURRENT (mA)
C
C
Figure 8. “On” Voltages
Figure 9. Temperature Coefficients
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
TYPICAL DYNAMIC CHARACTERISTICS
500
1000
V
I
= –3.0 V
/I = 10
= I
= 25°C
V
I
= 3.0 V
CC
C B
CC
/I = 10
700
500
300
200
C B
I
T
T
= 25°C
B1 B2
J
t
s
300
200
J
100
70
50
100
70
50
30
20
t
r
t
f
30
20
t
@ V
BE(off)
= 0.5 V
10
d
10
7.0
5.0
1.0
10
–1.0
2.0 3.0
5.0 7.0
20
30
50 70 100
–2.0 –3.0
–10
–20 –30
, COLLECTOR CURRENT (mA)
C
–100
–50 –70
–5.0 –7.0
I
, COLLECTOR CURRENT (mA)
I
C
Figure 10. Turn–On Time
Figure 11. Turn–Off Time
500
10
7.0
5.0
T
J
= 25°C
T
= 25°C
J
V
= 20 V
300
200
CE
C
ib
5.0 V
3.0
2.0
100
70
C
ob
50
1.0
0.05 0.1
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20
30
50
0.2
0.5
V , REVERSE VOLTAGE (VOLTS)
R
1.0
2.0
5.0
10
20
50
I
, COLLECTOR CURRENT (mA)
C
Figure 12. Current–Gain — Bandwidth Product
Figure 13. Capacitance
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
0.1
0.1
0.07
0.05
FIGURE 19
1
0.05
DUTY CYCLE, D = t /t
1 2
P
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
(pk)
0.02
0.01
0.03
0.02
t
READ TIME AT t (SEE AN–569)
1
θ
(pk)
Z
T
= r(t)
•
R
SINGLE PULSE
θ
J(pk)
JA(t)
JA
t
2
– T = P
Z
θJA(t)
A
0.01
0.01 0.02
0.05 0.1 0.2
0.5
1.0
2.0
5.0
10
20
50
100 200
500 1.0 k 2.0 k
5.0 k 10 k 20 k
100 k
50 k
t, TIME (ms)
Figure 14. Thermal Response
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
4
10
10
10
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
V
= 30 V
CC
A train of periodical power pulses can be represented by the model
as shown in Figure 15. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 14 was calculated for various duty cycles.
3
2
I
CEO
To find Z
steady state value R
, multiply the value obtained from Figure 14 by the
θJA(t)
.
1
θJA
10
10
I
CBO
Example:
AND
The MPS3905 is dissipating 2.0 watts peak under the following
conditions:
I
@ V
= 3.0 V
0
CEX
BE(off)
t
= 1.0 ms, t = 5.0 ms (D = 0.2)
1
2
–1
10
10
Using Figure 14 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
–2
The peak rise in junction temperature is therefore
–4
0
–2
0
0
+20 +40 +60 +80 +100 +120 +140 +160
T , JUNCTION TEMPERATURE ( C)
∆T = r(t) x P
(pk)
x R
= 0.22 x 2.0 x 200 = 88°C.
θJA
°
J
For more information, see AN–569.
Figure 15. Typical Collector Leakage Current
6
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
SOLDERING PRECAUTIONS
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
by T
, the maximum rated junction temperature of the
, the thermal resistance from the device junction to
J(max)
die, R
θJA
ambient, and the operating temperature, T . Using the
A
values provided on the data sheet for the SOT–23 package,
P
can be calculated as follows:
D
•
•
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
T
– T
A
J(max)
P
=
D
R
θJA
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature T of 25°C, one can
A
calculate the power dissipation of the device which in this
case is 225 milliwatts.
•
•
•
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
150°C – 25°C
556°C/W
P
=
= 225 milliwatts
D
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad . Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
•
Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
7
PACKAGE DIMENSIONS
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
3
S
B
1
2
INCHES
MIN MAX
MILLIMETERS
DIM
A
B
C
D
G
H
J
MIN
2.80
1.20
0.89
0.37
1.78
0.013
0.085
0.45
0.89
2.10
0.45
MAX
3.04
1.40
1.11
0.50
2.04
0.100
0.177
0.60
1.02
2.50
0.60
V
G
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
C
K
L
S
H
J
D
V
K
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
CASE 318–08
ISSUE AE
SOT–23 (TO–236AB)
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
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