DSP56156FE60 [MOTOROLA]
16-bit Digital Signal Processor; 16位数字信号处理器
| 型号： | DSP56156FE60 |
| 厂家： | 
MOTOROLA |
| 描述： | 16-bit Digital Signal Processor |
| 文件： | 总76页 (文件大小：1020K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by DSP56156/D
REV 1
Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
DSP56156
DSP56156ROM
Advance Information
16-bit Digital Signal Processor
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-
gram and data memories, a number of peripherals, and system support circuitry. Unique features
of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com-
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.
The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-
based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to be performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightforward generation of efficient, compact code. The basic architectures and devel-
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.
On-Chip Emulation (OnCETM port) circuitry provides convenient and inexpensive debug facil-
ities normally available only through expensive external hardware. Development costs are re-
duced and in-field testing is greatly simplified using the OnCETM port. Figure 1 illustrates the
DSP56156 in detail.
16-bit Bus
7
2
5
5
15
Sigma-
Delta
16-bit
Sync.
Sync.
Host
Program
Data
Timer/
Event
Serial
(SSI)
or I/O
Serial Interface
Memory *
Memory
Codec
(SSI)
(HI)
2048 × 16 RAM 2048 × 16 RAM
Counter
or I/O
or I/O
64 × 16 ROM
(boot)
External
Address
Bus
PAB
16-bit
Address
16
Address
XAB1
XAB2
Generation
Unit
56100 DSP
Core
Switch
GDB
PDB
XDB
Internal
Data
External
Data
Data
16
Bus
Bus
Switch
Switch
OnCE™ Port
Clock
Control
9
Program
Decode
Program
Data ALU
16 x 16 + 40 —> 40-bit MAC
Two 40-bit Accumulators
Interrupt
Control
Bus
Address
Controller
Generator
Control
PLL
Gen.
Program Control Unit
3
4
IRQ
2
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM
Figure 1 DSP56156 Block Diagram
Specifications and information herein are subject to change without notice.
OnCE is a trademark of Motorola, Inc.
MOTOROLA INC., 1994
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Introduction
DSP56156 Features
DSP56156 Features
Digital Signal Processing Core
• Efficient, object code compatible, 16-bit 56100-Family DSP engine
— Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
— Up to 180 Million Operations Per Second (MOPS) at 60 MHz
— Highly parallel instruction set with unique DSP addressing modes
— Two 40-bit accumulators including extension byte
— Parallel 16 × 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
— Double precision 32 × 32-bit multiply with 72-bit result in 6 instruction cycles
— Least Mean Square (LMS) adaptive loop filter in 2 instructions
— 40-bit Addition/ Subtraction in 1 instruction cycle
— Fractional and integer arithmetic with support for multiprecision arithmetic
— Hardware support for block-floating point FFT
— Hardware-nested DO loops including infinite loops
— Zero-overhead fast interrupts (2 instruction cycles)
— Three 16-bit internal data buses and three 16-bit internal address buses for
maximum information transfer on-chip
Memory
• On-chip Harvard architecture permitting simultaneous accesses to program
and memories
• 2048 × 16-bit on-chip program RAM and 64 × 16-bit bootstrap ROM
(or 12 k × 16-bit on-chip program ROM on the DSP56156ROM)
• 2048 × 16-bit on-chip data RAM
• External memory expansion with 16-bit address and data buses
• Bootstrap loading from external data bus, Host Interface, or
Synchronous Serial Interface
Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with Direct Memory Access support
• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and
synchronous serial devices
— Built in µ-law and A-law compression/ expansion
— Up to 32 software-selectable time slots in network mode
• 16-bit Timer/ Event Counter also generates and measures digital waveforms
• On-chip sigma-delta voice band Codec:
— Sampling clock rates between 100 kHz and 3 MHz
— Four software-programmable decimation/ interpolation ratios
2
— Internal voltage reference ( / of positive power supply)
5
— No external components required
2
DSP56156 Data Sheet
MOTOROLA
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Introduction
DSP56156 Features
Documentation
• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 27 general purpose I/ O pins
• Two external interrupt request pins
• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent
debugging
• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the
core clock
Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC
• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20 × 20 × 3 mm
• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.5 mm
• 5 V power supply
Product Documentation
This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156
description and are necessary to properly design with the part. Documentation is available
from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera-
ture Distribution Center.
Table 1 DSP56156 Documentation
Topic
Description
Order Number
DSP56100 Family Manual
Detailed description of the 56000-
family architecture and the 16-bit core
processor and instruction set
DSP56100FAMUM/AD
DSP56156 User’s Manual
DSP56156 Data Sheet
Detailed description of memory,
peripherals, and interfaces
DSP56156UM/AD
DSP56156/D
Pin and package descriptions, and
electrical and timing specifications
MOTOROLA
DSP56156 Data Sheet
3
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Introduction
Documentation
Data Sheet Contents
Related Documentation
Table 2 lists additional documentation relevant to the DSP56156.
Table 2 Related Motorola Documentation
Topic
DSP Family Brochure
Development Tools
Description
Order Number
Overview of all DSP product families BR1105/D
Product Brief. Includes ordering
information
DSPTOOLSP/D
Fractional and Integer Arithmetic
Fast Fourier Transforms (FFTs)
Application Report. Includes code
APR3/D
APR4/D
Application Report. Comprehensive
FFT algorithms and code for
DSP56001, DSP56156, and
DSP96002
G.722 Audio Processing
Dr. BuB Bulletin Board
Application Report. Theory and code APR404/D
using SB-ADPCM
Flyer. Motorola’s electronic bulletin
board where free DSP software is
available
BR297/D
Third Party Compendium
Brochures from companies selling
hardware and software that supports
Motorola DSPs
DSP3RDPTYPAK/D
BR382/D
University Support Program
Flyer. Motorola’s program that sup-
ports universities in DSP research
and education
Data Sheet Contents
This data sheet contains:
• signal definitions and pin locations
• electrical specifications and timings
• package descriptions
• design considerations
• ordering information
4
DSP56156 Data Sheet
MOTOROLA
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Freescale Semiconductor, Inc.
Introduction
Pin Groupings
Pin Groupings
The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic
Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional
groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.
Table 3 Functional Pin Groupings
Functional Group
Number of Pins
Address
16
16
9
Data Bus
Bus Control
Host Interface (HI)
15
10
2
Synchronous Serial Interfaces (SSI)
Timer Interface
Interrupt and Mode Control
Phase-Locked Loop (PLL) and Clock
On-Chip Emulation (OnCETM Port)
On-Chip Codec
4
3
4
7
Power (VCC
)
10
16
112
Ground (GND)
Total
NOTE:
OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-
cally a TTL logic low — VIL or VOL) when the function is logically true. These signals are, likewise, at
VCC voltage (typically a TTL logic high — VIH or VOH) when the function is logically false.
MOTOROLA
DSP56156 Data Sheet
5
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Introduction
Pin Functions
DSP56156
A0-A15
D0-D15
RD
H0-H7*
HA0-HA2*
HR/W*
HEN*
Host
Interface (HI)
WR
BR
BG
BS
HREQ*
HACK*
External
Bus
TA
PS/DS
R/W
BB
STD0*
SRD0*
SCK0*
SC00-SC10*
Two
Synchronous
Serial
Interfaces
(SSI)
MODA/IRQA
MODB/IRQB
MODC
STD1*
SRD1*
SCK1*
SC01-SC11*
Interrupt/
Mode
Control
RESET
DSO
DSI/OS0
DSCK/OS1
DR
TIN*
TOUT*
Timer/Event
Counter
On-Chip
Emulator
(OnCE )
Port
Clock
and
Phase-locked
Loop
EXTAL
CLKO
SXFC
MIC
AUX
(PLL)
SPKP
SPKM
BIAS
On-Chip
Codec
VREF
VDIV
VCC
GND
112 pins
* These pins have an alternate function of general purpose input/output.
Figure 2 DSP56156 Pin Functions
6
DSP56156 Data Sheet
MOTOROLA
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Pin Descriptions
Address and Data Bus
Bus Control
(t0, t1, t2, t3), R/ W goes high in t0. R/ W
Pin Descriptions
is three-stated during hardware reset.
Address and Data Bus
WR (Write Enable) — three-state, active
low output. This output is asserted dur-
ing external memory write cycles. When
WR is asserted in t1, the data bus pins
D0-D15 become outputs and the DSP
puts data on the bus during the leading
edge of t2. When WR is deasserted in t3,
the external data has been latched inside
the external device. When WR is assert-
ed, it qualifies the A0-A15 and PS/ DS
pins. WR can be connected directly to
the WE pin of a static RAM. WR is three-
stated during hardware reset or when
the DSP is not bus master.
A0-A15 (Address Bus) — three-state, active
high outputs. A0-A15 change in t0 and
specify the address for external pro-
gram and data memory accesses. If
there is no external bus activity, A0-A15
remain at their previous values. A0-A15
are three-stated during hardware reset.
D0-D15 (Data Bus) — three-state, active
high, bidirectional input/outputs.
Read data is sampled on the trailing
edge of t2, while write data output is
enabled by the leading edge of t2 and
three-stated at the leading edge of t0. If
there is no external bus activity, D0-D15
are three-stated. D0-D15 are also three-
stated during hardware reset.
RD (Read Enable) — three-state, active
low output. This output is asserted
during external memory read cycles.
When RD is asserted in late t0/ early t1,
the data bus pins D0-D15 become in-
puts and an external device is enabled
onto the data bus. When RD is deas-
serted in t3, the external data is latched
inside the DSP. When RD is asserted, it
qualifies the A0-A15 and PS/ DS pins.
RD can be connected directly to the
OE pin of a static RAM or ROM. RD is
three-stated during hardware reset or
when the DSP is not bus master.
Bus Control
PS/DS (Program/Data Memory Select)
—
three-state, active low output. This out-
put is asserted only when external data
memory is referenced. PS/ DS timing is
the same for the A0-A15 address lines.
PS/ DS is high for program memory ac-
cess and is low for data memory access. If
the external bus is not used during an in-
struction cycle (t0, t1, t2, t3), PS/ DS goes
high in t0. PS/ DS is in the high imped-
ance state during hardware reset.
BS (Bus Strobe) — three-state, active
low output. Asserted at the start of a
bus cycle (during t0) and deasserted at
the end of the bus cycle (during t2).
This pin provides an “early bus start”
signal which can be used as address
latch and as an “early bus end” signal
which can be used by an external bus
controller. BS is three-stated during
hardware reset.
R/W (Read/Write) — three-state, active
low output. Timing is the same as the
address lines, providing an “early
write” signal. R/ W (which changes in
t0) is high for a read access and is low
for a write access. If the external bus is
not used during an instruction cycle
MOTOROLA
DSP56156 Data Sheet
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Pin Descriptions
Bus Control
TA (Transfer Acknowledge) — active
t3 to be sampled high by the leading
edge of T0. If TA is sampled low (assert-
ed) at the leading edge of the t0 begin-
ning the bus cycle, and if no wait states
are specified in the BCR register, zero
wait states will be inserted in the exter-
nal bus cycle, regardless the status of
TA during the leading edge of T2.
low input. If there is no external bus ac-
tivity, the TA input is ignored by the
DSP. When there is external bus cycle
activity, TA can be used to insert wait
states in the external bus cycle. TA is
sampled on the leading edge of the
clock. Any number of wait states from 1
to infinity may be inserted by using TA.
If TA is sampled high on the leading
edge of the clock beginning the bus cy-
cle, the bus cycle will end 2T after the
TA has been sampled low on a leading
edge of the clock; if the Bus Control Reg-
ister (BCR) value does not program
more wait states. The number of wait
states is determined by the TA input or
by the Bus Control Register (BCR),
whichever is longer. TA is still sampled
during the leading edge of the clock
when wait states are controlled by the
BCR value. In that case, TA will have to
be sampled low during the leading edge
of the last period of the bus cycle pro-
grammed by the BCR (2T before the end
of the bus cycle programmed by the
BCR) in order not to add any wait states.
TA should always be deasserted during
BR (Bus Request) — active low output
when in master mode, active low in-
put when in slave mode. After power-
on reset, this pin is an input (slave
mode). In this mode, the bus request
BR allows another device such as a pro-
cessor or DMA controller to become
the master of the DSP external data
bus D0-D15 and external address bus
A0-A15. The DSP asserts BG a few T
states after the BR input is asserted.
The DSP bus controller releases control
of the external data bus D0-D15, ad-
dress bus A0-A15 and bus control pins
PS/ DS, RD, WR, and R/ W at the earli-
est time possible consistent with prop-
er synchronization. These pins are then
placed in the high impedance state and
T0
T0
T2
T2
T2
T2
Tw T2 Tw T3
T1 T2 T3
T1 T2 Tw
T3 T0 T1
T3 T0 T1
CLKO
TA
BS
T0
T2
T2
T2
T2
T2
T3 T0 T1
T1 T2 Tw
Tw T2 Tw
T3 T0 T1
Tw T2 Tw
CLKO
TA
BS
Figure 3 TA Controlled Accesses
8
DSP56156 Data Sheet
MOTOROLA
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Pin Descriptions
Bus Control
the BB pin is deasserted. The DSP con-
nal memory device off and on between
tinues executing instructions only if in-
ternal program and data memory
resources are accessed. If the DSP re-
quests the external bus while BR input
pin is asserted, the DSP bus controller
inserts wait states until the external bus
becomes available (BR and BB deas-
serted). Note that interrupts are not
serviced when a DSP instruction is
waiting for the bus controller. Note
also that BR is prevented from inter-
rupting the execution of a read/ modi-
fy/ write instruction.
internal and external bus accesses. BR
timing is in that case similar to A0-A15,
R/ W and PS/ DS; it is asserted and
deasserted during t0.
BG (Bus Grant) — active low input when
in master mode, active low output
when in slave mode. Output after
power on reset if the slave is selected,
this pin is asserted to acknowledge an
external bus request. It indicates that
the DSP will release control of the ex-
ternal address bus A0-A15, data bus
D0-D15 and bus control pins when BB
is deasserted. The BG output is assert-
ed in response to a BR input. When the
BG output is asserted and BB is deas-
serted, the external address bus A0-A15,
data bus D0-D15 and bus control pins
are in the high impedance state. BG as-
sertion may occur in the middle of an
instruction which requires more than
one external bus cycle for execution.
Note that BG assertion will not occur
during indivisible read-modify-write
instructions (BFSET, BFCLR, BFCHG).
When BR is deasserted, the BG output
is deasserted and the DSP regains con-
trol of the external address bus, data
bus, and bus control pins when the BB
pin is sampled high.
If the master bit in the OMR register is
set, this pin becomes an output (Master
Mode). In this mode, the DSP is not the
external bus master and has to assert
BR to request the bus mastership. The
DSP bus controller will insert wait
states until BG input is asserted and
will then begin normal bus accesses af-
ter the rising of the clock which sam-
pled BB high. The BR output signal will
remain asserted until the DSP no long-
er needs the bus. In this mode, the Re-
quest Hold bit (RH) of the Bus Control
Register (BCR) allows BR to be asserted
under software control.
During external accesses caused by an
instruction executed out of external pro-
gram memory, BR remains asserted low
for consecutive external X memory ac-
cesses and continues toggling for con-
secutive external P memory accesses
unless the Request Hold bit (RH) is set
inside the Bus Control Register (BCR).
This pin becomes an input if the master
bit in the OMR register is set (Master
Mode). It is asserted by an external pro-
cessor when the DSP may become the
bus master. The DSP can start normal
external memory access after the BB pin
has been deasserted by the previous
bus master. When BG is deasserted, the
DSP will release the bus as soon as the
current transfer is completed. The state
of BG may be tested by testing the BS bit
in the Bus Control Register. BG is ig-
nored during hardware reset.
In the master mode, BR can also be
used for non arbitration purpose: if BG
is always asserted, BR is asserted in t0
of every external bus access. It can then
be used as a chip select to turn a exter-
MOTOROLA
DSP56156 Data Sheet
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Pin Descriptions
Bus Control
Interrupt and Mode Control
BB (Bus Busy) — active low input when
not bus master, active low output
MODB/IRQB
(Mode Select B/External In-
terrupt Request B) — input. This in-
when bus master. This pin is asserted
by the DSP when it becomes the bus
master and it performs an external ac-
cess. It is deasserted when the DSP re-
leases bus mastership. BB becomes an
input when the DSP is no longer the
bus master.
put has two functions:
• to select the initial chip operating
mode and,
• to allow an external device to request
a DSP interrupt after internal syn-
chronization.
MODB is read and internally latched in
the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODB pin changes to the external
interrupt request IRQB. After reset, the
chip operating mode can be changed
by software.
Interrupt and Mode Control
MODA/IRQA
(Mode Select A/External In-
terrupt Request A) — input. This in-
put has two functions:
The IRQB input is an external interrupt
request which indicates that an exter-
nal device is requesting service. It may
be programmed to be level sensitive or
negative edge triggered. If level sensi-
tive triggering is selected, an external
pull up resistor is required for wired-
OR operation.
• to select the initial chip operating
mode and,
• to allow an external device to request
a DSP interrupt after internal syn-
chronization.
MODA is read and internally latched
in the DSP when the processor exits the
reset state. MODA and MODB select
the initial chip operating mode. Several
clock cycles after leaving the reset state,
the MODA pin changes to the external
interrupt request IRQA. The chip oper-
ating mode can be changed by soft-
ware after reset.
MODC (Mode Select C) — input. This input
selects the initial bus operating mode.
When tied high, the external bus is pro-
grammed in the master mode (BR out-
put and BG input) and when tied low
the bus is programmed in the slave
mode (BR input and BG output).
MODC is read and internally latched in
the DSP when the processor exits the
reset state. After RESET, the bus operat-
ing mode can be changed by software by
writing the MC bit of the OMR register.
The IRQA input is a synchronized ex-
ternal interrupt request which indi-
cates that an external device is
requesting service. It may be pro-
grammed to be level sensitive or nega-
tive edge triggered. If level sensitive
triggering is selected, an external pull
up resistor is required for wired-OR
operation. If the processor is in the stop
standby state and IRQA is asserted, the
processor will exit the stop state.
RESET (Reset) — input. This input is a direct
hardware reset of the processor. When
RESET is asserted, the DSP is initialized
and placed in the reset state. A Schmitt
10
DSP56156 Data Sheet
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Pin Descriptions
Interrupt and Mode Control
Host Interface
trigger input is used for noise immunity.
HEN (Host Enable) — input*. This input en-
When the reset pin is deasserted, the ini-
tial chip operating mode is latched from
the MODA and MODB pins, and the ini-
tial bus operating mode is latched from
the MODC pin. The internal reset signal
should be deasserted synchronized with
the internal clocks.
ables a data transfer on the host data
bus. When HEN is asserted and HR/ W
is high, H0-H7 becomes an output and
DSP data may be latched by the host
processor. When HEN is asserted and
HR/ W is low, H0-H7 is an input and
host data is latched inside the DSP
when HEN is deasserted. Normally a
chip select signal derived from host ad-
dress decoding and an enable clock is
connected to the Host Enable. HEN
may be programmed as a general pur-
pose I/ O pin called PB12 when the HI
is not being used.
Host Interface
H0-H7 (Host Data Bus) — bidirectional. This
bidirectional data bus is used to transfer
data between the host processor and the
DSP. This bus is an input unless enabled
by a host processor read. H0-H7 may be
programmed as Port B general purpose
parallel I/ O pins called PB0-PB7 when
the Host Interface (HI) is not being used.
HREQ (Host Request) — output*. This open-
drain output signal is used by the HI to
request service from the host proces-
sor. HREQ may be connected to an in-
terrupt request pin of a host processor,
a transfer request of a DMA controller,
or a control input of external circuitry.
HREQ is asserted when an enabled re-
quest occurs in the HI. HREQ is deas-
serted when the enabled request is
cleared or masked, DMA HACK is as-
serted, or the DSP is reset. HREQ may
be programmed as a general purpose
I/ O pin (not open-drain) called PB13
when the HI is not being used.
HA0-HA2 (Host Address 0-2) — input*. These
inputs provide the address selection
for each HI register and are stable
when HEN is asserted. HA0-HA2 may
be programmed as Port B general pur-
pose parallel I/ O pins called PB8-PB10
when the HI is not being used.
HR/W (Host Read/Write) — input*. This in-
put selects the direction of data transfer
for each host processor access. If HR/ W
is high and HEN is asserted, H0-H7 are
outputs and DSP data is transferred to
the host processor. If HR/ W is low and
HEN is asserted, H0-H7 are inputs and
host data is transferred to the DSP.
When HEN is asserted, HR/ W is stable.
HR/ W may be programmed as a gen-
eral purpose I/ O pin called PB11
when the HI is not being used.
HACK (Host Acknowledge) — input*. This
input has two functions:
• to provide a host acknowledge signal
for DMA transfers and,
• to control handshaking and to pro-
vide a host interrupt acknowledge
compatible with MC68000 family
processors.
If programmed as a host acknowledge
signal, HACK may be used as a data
strobe for HI DMA data transfers. If pro-
grammed as an MC68000 host interrupt
* These pins can be bidirectional when programmed as general purpose I/O.
MOTOROLA
DSP56156 Data Sheet
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Pin Descriptions
16-bit Timer
SSI
PC0 and PC5, respectively, when the
acknowledge, HACK enables the HI
Interrupt Vector Register (IVR) onto
the host data bus H0-H7 if the Host Re-
quest HREQ output is asserted. In this
case, all other HI control pins are ig-
nored and the HI state is not affected.
HACK may be programmed as a gen-
eral purpose I/ O pin called PB14 when
the HI is not being used.
STD function is not being used.
SRD0-1 (SSI0-1 Receive Data) — input*.
These input pins receive serial data and
transfer the data to the SSI0-1 Receive
Shift Register. SRD0 and SRD1 may be
programmed as a general purpose I/ O
pin called PC1 and PC6, respectively,
when the SRD function is not being
used.
SCK0-1 (SSI0-1 Serial Clock) — bidirection-
al. These bidirectional pins provide the
serial bit rate clock for the SSI0-1 inter-
face. SCK0 and SCK1 may be pro-
grammed as a general purpose I/ O pin
called PC2 and PC7, respectively,
when the SSI0-1 interfaces are not be-
ing used.
16-bit Timer
TIN (Timer Input) — input*. This input re-
ceives external pulses to be counted by
the on-chip 16-bit timer when external
clocking is selected. The pulses are in-
ternally synchronized to the DSP core
internal clock. TIN may be pro-
grammed as a general purpose I/ O pin
called PC10 when the external event
function is not being used.
SC10-11 (SSI0-1 Serial Control 1) — bidirec-
tional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/ O or flag I/ O. SC10 and
SC11 may be programmed as a general
purpose I/ O pin called PC3 and PC8,
respectively, when the SSI0-1 are not
using these pins.
TOUT (Timer Output) — output*. This out-
put generates pulses or toggles on a
timer overflow event or a compare
event. TOUT may be programmed as a
general purpose I/ O pin called PC11
when disabled by the timer out enable
bits (TO2-TO0).
SC00-01 (SSI0-1 Serial Control 0) — bidirec-
tional. These bidirectional pins are
used by the SSI0-1 serial interface as
frame sync I/ O or flag I/ O. SC00 and
SC01 may be programmed as a general
purpose I/ O pin called PC4 and PC9,
respectively, when the SSI0-1 are not
using these pins.
Synchronous Serial
Interfaces (SSI)
STD0-1 (SSI0-1 Transmit Data) — output*.
These output pins transmit serial data
from the SSI0-1 Transmit Shift Register.
STD0 and STD1 may be programmed
as a general purpose I/ O pin called
* These pins can be bidirectional when programmed as general purpose I/O.
12
DSP56156 Data Sheet
MOTOROLA
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Pin Descriptions
OnCE
On-Chip Codec
cycle) to indicate that the serial shift reg-
On-Chip Emulation
(OnCETM Port)
ister is ready to receive clocks in order to
deliver the data. When the chip enters
the debug mode due to an external de-
bug request (DR), an internal software
debug request (DEBUG), a hardware
breakpoint occurrence or a trace/ step
occurrence, this line will be asserted for
three T cycles to indicate that the chip
has entered the debug mode and is wait-
ing for commands. Data is always shift-
ed out the OnCE serial port with the
most significant bit first.
DSI/OS0 (Debug Serial Input/Chip Status 0) —
bidirectional. The DSI/ OS0 pin, when
an input, is the pin through which seri-
al data or commands are provided to
the OnCE port controller. The data re-
ceived on the DSI pin will be recog-
nized only when the DSP has entered
the debug mode of operation. Data
must have valid TTL logic levels before
the serial clock falling edge. Data is al-
ways shifted into the OnCE serial port
most significant bit (MSB) first. When the
DSP is not in the debug mode, the DSI/
OS0 pin provides information about the
chip status if it is an output and used in
conjunction with the OS1 pin.
DR (Debug Request) — input. The debug
request input provides a means of en-
tering the debug mode of operation.
This pin, when asserted, will cause the
DSP to finish the current instruction be-
ing executed, enter the debug mode,
and wait for commands to be entered
from the debug serial input line.
DSCK/OS1 (Debug Serial Clock/Chip Status 1)
— bidirectional. The DSCK/ OS1 pin,
when an input, is the pin through
which the serial clock is supplied to the
OnCE port. The serial clock provides
pulses required to shift data into and
out of the OnCE serial port. Data is
clocked into the OnCE port on the fall-
ing edge and is clocked out of the
OnCE serial port on the rising edge. If
the DSCK/ OS1 pin is an output and
used in conjunction with the OS0 pin, it
provides information about the chip
status when the DSP is not in the debug
mode.
On-Chip Codec
AUX (Auxiliary) — input. This pin is select-
ed as the analog input to the A/ D con-
verter when the INS bit is set in the
codec control register COCR. This pin
should be left floating when the codec
is not used.
BIAS (Bias current) — input. This input is
used to determine the bias current for
the analog circuitry. Connecting a re-
sistor between BIAS and GNDA will
program the current bias generator.
This pin should be left floating when
the codec is not used.
DSO (Debug Serial) — output. The debug
serial output provides the data con-
tained in one of the OnCE port control-
ler registers as specified by the last
command received from the command
controller. When idle, this pin is high.
When the requested data is available, the
DSO line will be asserted (negative true
logic) for four T cycles (one instruction
MIC (Microphone) — input. This pin is se-
lected as the analog input to the A/ D
converter when the INS bit is cleared in
MOTOROLA
DSP56156 Data Sheet
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13
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Freescale Semiconductor, Inc.
Pin Descriptions
On-Chip Codec
Power, Ground, and Clock
the codec control register COCR. This
GNDS (Synthesizer Ground) — This pin sup-
plies a quiet ground source to the PLL
to provide greater frequency stability.
pin should be left floating when the co-
dec is not used.
SPKP (Speaker Plus) — output. This pin is
the positive analog output from the on-
chip D/ A converter. This pin should be
left floating when the codec is not used.
VCCA (Analog Power) — This pin is the posi-
tive analog supply input. It should be con-
nected to VCC when the codec is not used.
GNDA (Analog Ground) — This pin is the an-
alog ground return. It should be con-
nected to digital GND when the codec
is not used.
SPKM (Speaker Minus) — output. This pin is
the negative analog output from the
on-chip D/ A converter. This pin
should be left floating when the codec
is not used.
EXTAL (External Clock) — input. This input
should be driven by an external clock or
by an external oscillator. After being
squared, the input frequency can be
used as the DSP core internal clock. In
that case, it is divided by two to produce
a four phase instruction cycle clock, the
minimum instruction time being two in-
put clock periods. This input frequency
is also used, after division, as input
clock for the on-chip codec and the on-
chip PLL.
VREF (Voltage Reference) — output. This
pin is the op-amp buffer output in the
reference voltage generator. It has a
2
value of ( / )VCCA. This pin should al-
5
ways be connected to the GNDA
through two capacitors, even when the
codec is not used.
VDIV (Voltage Division) — output. This
output pin is also the output to the on-
chip op-amp buffer in the reference
voltage generator. It is connected to a
resistor divider network located within
CLKO (Clock Output) — output. This pin
outputs a buffered clock signal. By pro-
gramming two bits (CS1-CS0) inside
the PLL Control Register (PLCR), the
user can select between outputting a
squared version of the signal applied to
EXTAL, a squared version of the signal
applied to EXTAL divided by 2, and a
delayed version of the DSP core master
clock. The clock frequency on this pin
can be disabled by setting the Clockout
Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). When disabled,
the pin can be left floating.
the codec block which provides a volt-
2
age equal to ( / )VCCA. This pin should
5
be connected to the GND via a capacitor
when the codec is used and should be
left floating when the codec is not used.
Power, Ground, and Clock
VCC (Power) — Power pins
GND (Ground) — Ground pins
SXFC (External Filter Capacitor) — This pin
adds an external capacitor to the PLL
filter circuit. A low leakage capacitor
should be connected between and lo-
VCCS (Synthesizer Power) — This pin sup-
plies a quiet power source to the Phase-
Locked Loop (PLL) to provide greater
frequency stability.
cated very close to SXFC and VCCS
.
14
DSP56156 Data Sheet
MOTOROLA
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Electrical Characteristics and Timing
Electrical Characteristics and Timing
CAUTION:
Exceeding maximum electrical ratings will permanently damage or
disable the chip, or impair the chip’s long term reliability.
The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS
compatible outputs.
Table 4 Maximum Electrical Ratings (GND = 0 Vdc)
Rating
Symbol
Value
Unit
Supply Voltage
VCC
VIN
I
-0.3 to +7.0
GND - 0.5 to VCC + 0.5
10
V
V
All Input Voltages
Current Drain per Pin excluding VCC and GND
Storage Temperature
mA
°C
Tstg
-55 to +150
Table 5 Operating Conditions
Supply Voltage
VCC
Junction Temperature
TJ (°C)
Min
Max
Min
Max
4.5
5.5
-40
115
Table 6 Thermal Characteristics of CQFP and TQFP Packages
Value
Thermal Resistance
Symbol
Rating
Characteristics
CQFP
TQFP
Junction to Ambient
Junction to Case (estimated)
ΘJA
ΘJC
40
7
49
8
°C/W
°C/W
NOTE: This device contains protective circuitry to guard against damage due to high static voltage or electrical
fields. However, normal precautions are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied
to an appropriate logic voltage level (e.g., either GND or VCC).
MOTOROLA
DSP56156 Data Sheet
15
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Electrical Characteristics and Timing
Analog I/O Characteristics
Analog I/O Characteristics
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C)
A
The analog I/ O characteristics of this device are listed in Table 7.
For additional information regarding the use of analog signals, see “Design Considerations”
at the end of this document.
Table 7 Analog I/O Characteristics
Characteristic
Min
Typ
Max
Unit
Input Impedance on MIC and AUX
Input Capacitance on MIC and AUX
(See Note 1)
46
78
1400
kΩ
—
—
10
pF
Peak Input Voltage on the MIC/AUX Input for Full Scale
Linearity (0.14 dBm0):
(See Note 2)
6 dB - MGS1 - 0 = 00
0 dB - MGS1 - 0 = 01
6 dB - MGS1 - 0 = 10
17 dB - MGS1 - 0 = 11
—
—
—
—
—
—
—
—
1.414
0.707
354
Vp
Vp
mVp
mVp
100
Internal Input Gain Variation;
G = -6 dB, 0 dB, 6 dB or 17 dB
G - 0.83
G
G + 0.83
dB
(±0.83 dB variation due to 10% variation on VCC):
VREF Output Voltage
1.8
—
—
0
2
2.2
±1
V
VREF Output Current
—
—
—
mA
mV
µF
DC Offset Between SPKP and SPKM
100
0.05
Allowable Differential Load Capacitance on
SPKP and SPKM (with 1 kΩ in series)
Allowable Single-ended Load Capacitance on
SPKP or SPKM (with 0.5 kΩ in series)
0
—
100
0.1
µF
(See Note 3)
Maximum Single-ended Signal Output Level
Maximum Differential Signal Output Level
Single-ended Load Resistance
Differential Load Resistance
—
—
—
—
—
—
1
2
Vp
Vp
Ω
500
1
—
—
—
kΩ
kΩ
Resistance BIAS
—
10
(See
Note 4)
Internal Output Volume Control Variation
VC - 0.83
VC
VC + 0.83
dB
VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB
(± 0.83 dB variation due to 10% variation on VCC
)
NOTES: 1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz
2. 0 dBm0 corresponds to 3.14 dB below the input saturation level
3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF
4. ± 10%
16
DSP56156 Data Sheet
MOTOROLA
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Electrical Characteristics and Timing
A/D and D/A Performance
A/D and D/A Performance
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C)
The A/ D and D/ A performance of the codec section are given in Table 8 with an
example presented in Figure 4.
Table 8 A/D and D/A Performance of Codec
Typ
(See Note 1)
Level
Min
Max
Characteristic
Unit
Analog to Digital Section Signal to Noise
plus Distortion Ratio (S/N+T)
0 dBm0
(See Note 2)
55
65
—
dB
-50 dBm0
0 dB
15
55
15
20
65
20
—
—
—
dB
dB
dB
Digital to Analog Section Signal to Noise
plus Distortion Ratio (S/N+T)
-50 dB
NOTES: 1. 0 dB gain on the A/D and D/A; Codec clock at 1.538 MHz with 128 decimation/interpolation ratio and
tested at 1502 Hz
2. 0 dBm0 corresponds to -3.14 dB below the input saturation level
80
2 MHz
S/N
COCR=$E400
Codec
÷ 6.5
70
60
50
40
30
20
10
0
S/N+T
13 MHz
1 MHz
52 MHz
÷ 13
PLL
÷(12+1)x4
Signal in dB
Figure 4 Example: S/N and S/N+T Performance for the A/D Section
MOTOROLA
DSP56156 Data Sheet
17
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Electrical Characteristics and Timing
Other On-Chip Codec Characteristics
Other On-Chip Codec Characteristics
(VCCA = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
The analog I/ O characteristics of this device are shown in Table 9.
Table 9 Analog I/O Characteristics of On-Chip Codec
Characteristic
Min
Typ
Max
Unit
Codec Master Clock
0.1
78
—
2.048
16000
—
3
37000
0.2
MHz
Hz
Codec Sampling Rate
A/D Section Group Delay
D/A Section Group Delay
msec
msec
—
—
0.2
18
DSP56156 Data Sheet
MOTOROLA
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DC Electrical Characteristics and Timing
DC Electrical Characteristics
(GND = 0 V dc)
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
The DC electrical characteristics of this device are shown in Table 10.
Table 10 DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Input High Voltage
VIH
2.0
—
VCC
V
except EXTAL, RESET, MODA, MODB, MODC
Input Low Voltage
except EXTAL, MODA, MODB, MODC
VIL
-0.5
—
0.8
V
V
Input High Voltage
VIHC
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
70% of VCC
1
—
—
VCC
VCC
Input Low Voltage
VILC
V
EXTAL DC coupled
EXTAL AC coupled (See Note 1)
-0.5
-0.5
—
—
20% of VCC
VCC-1
Input High Voltage RESET
VIHR
VIHM
VILM
IIN
2.5
3.5
—
—
—
—
VCC
VCC
2.0
V
V
V
Input High Voltage MODA, MODB, MODC
Input Low Voltage MODA, MODB, MODC
-0.5
Input Leakage Current
EXTAL
-100
-1
100
1
µA
µA
RESET, MODA, MODB, MODC, TA, DR, BR
Three-State (Off-State) Input Current
(@2.4 V/0.5 V)
TSI
-10
—
10
µA
Output High Voltage (IOH = -10 µA)
Output High Voltage (IOH = -0.4 mA)
Output Low Voltage (IOL = 10 µA)
VOHC
VOH
VOLC
VOL
VCC -0.1
—
—
—
—
—
—
V
V
V
V
2.4
—
0.1
0.4
Output Low Voltage (IOL = 3.2 mA
R/W IOL = 1.6 mA; Open Drain
—
HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA)
Input Capacitance (See Note 2)
CIN
—
10
—
pF
NOTES: 1. When EXTAL is AC coupled, VIHC - VILC Š 1 V must be true.
2. Input capacitance is periodically sampled and not 100% tested in production.
MOTOROLA
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Clock Operation Timing
AC Electrical Characteristics
(GND = 0 V dc)
The timing waveforms in the AC Electrical Characteristics are tested with a V maximum of
IL
0.5 V and a V minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and
IH
MODC. These five pins are tested using the input levels set forth in the DC Electrical Charac-
teristics. AC timing specifications which are referenced to a device input signal are measured
in production with respect to the 50% point of the respective input signal’s transition. The
DSP56156 output levels are measured with the production test machine V and V
refer-
OL
OH
ence levels set at 0.8 V and 2.0 V respectively.
Clock Operation Timing
The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in
Figure 6.
Table 11 Clock Operation Timing
40 MHz
50 MHz
60 MHz
Num
Characteristics
Sym
Unit
Min
Max
Min
Max
Min
Max
1
2
3
4
5
6
7
Frequency of Operation (EXTAL)
Instruction Cycle Time = 2TC
Wait State Time = TC = 2T
EXTAL Cycle Period
f
0
40
×
0
50
×
0
33
60
×
MHz
ns
ICYC
—
50
25
25
—
—
12
40
20
20
—
×
×
16.6
16.6
—
×
ns
TC
×
×
×
ns
EXTAL Rise Time (See Note 1)
EXTAL Fall Time (See Note 1)
4
3
3
ns
4
—
3
—
3
ns
EXTAL Width High
48-52% duty cycle
(See Notes 2, 3, 4)
TH
TL
×
9.6
×
8
×
ns
8
EXTAL Width Low
48%-52% duty cycle
(See Notes 2, 3, 4)
12
×
9.6
×
8
×
ns
NOTES: 1. Rise and fall time may be relaxed to 12 ns maximum if the EXTAL input frequency is less than or equal
to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should
meet the specified values in the 40 MHz column (4 ns maximum).
2. The duty cycle may be relaxed to 43-57% if the EXTAL input frequency is less than or equal to 20 MHz.
If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that TH
and TL meet the specified values in the 40 MHz column (12 ns minimum).
3. T = ICYC / 4 is used in the electrical characteristics. The exact length of each T is affected by the duty
cycle of the external clock input.
4. Duty cycles and EXTAL widths are measured at the EXTAL input signal midpoint when AC coupled and
at VCC/2 when not AC coupled.
20
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Clock Operation Timing
PLL
TH
TL
VIHC
90%
EXTAL
Midpoint
VILC
10%
7
8
6
5
4
2
Figure 5 External Clock Timing
Other Clock and PLL Operation Timing
Clock and PLL timings are listed in Table 12 and the clocking configurations are illustrated in
Figure 6.
Table 12 Clock and PLL Timing
Characteristics
PLL Output frequency
Min
Max
Unit
10
Max Fosc
(See Note 1)
MHz
EXTAL Input Clock Amplitude (See Note 2)
1
VCC
Vpp
NOTES: 1. Maximum DSP operating frequency. See Table 11.
2. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level
range (VILC>20% of VCC or VIHC<70% of VCC).
10 nF
XFC
0.01 µF
0.1 µF
VCCS
GNDS
SXFC
PLLE=1
PLLE=0
÷ 1 to ÷ 16
VCO
PFD
Fosc
100 KΩ
ED3-ED0
EXTAL
LF
÷ 1 to ÷ 16
YD3-YD0
÷ 4
1000 pF
PLL
GSM
÷ 6.5
CS1-CS0
CODEC
CLKO
÷ 2
internal phase PH0 at Fosc
Figure 6 Clocking Configurations
MOTOROLA
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
1
cyc = Clock cycle = / instruction cycle = 2 T cycles
2
ws = Number of wait states programmed into external bus access using BCR (WS = 0 - 31)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
40 MHz
50 MHz
Max
60 MHz
Max
Num
Characteristics
Unit
Min
Max
Min
Min
—
25
—
23
—
21
ns
10
11
RESET Assertion to Address, Data and
Control Signals High Impedance
Minimum Stabilization Duration
600KT
60T
—
—
600KT
60T
—
—
600KT
60T
—
—
ns
ns
(See Note 1)
OMR bit 6=0
OMR bit 6=1
16T
18T+20
16T
18T+17
16T
18T+15
ns
ns
ns
12
13
14
Asynchronous RESET Deassertion to
First External Address Output
(See Note 7)
7
cyc-4
6
cyc-3
5
cyc-2
Synchronous Reset Setup Time from
RESET Deassertion to Rising Edge of
CLKO
16T+3
16T+20
16T+ 3
16T+18
16T+3
16T+16
Synchronous Reset Delay Time from
CLKO High to the First External Access
(See Note 7)
22
0
—
—
—
20
0
—
—
—
18
0
—
—
—
ns
ns
ns
15
16
17
18
Mode Select Setup Time
Mode Select Hold Time
13
11
9
Edge-triggered Interrupt Request Width
Delay from IRQA, IRQB Assertion to
External Data Memory Access Out Valid
- Caused by First Interrupt
Instruction Fetch
- Caused by First Interrupt
Instruction Execution
11T+4
19T+4
—
11T+4
19T+4
—
—
11T+3
19T+3
—
—
ns
ns
—
—
19
20
Delay from IRQA, IRQB Assertion to
General Purpose Output Valid Caused
by the Execution of the First Interrupt
Instruction
22T+5
22T+4
—
22T+3
—
ns
Delay from External Data Memory
Address Output Valid Caused by First
Interrupt Instruction Execution to Inter-
rupt Request Deassertion for Level Sen-
sitive Fast Interrupts (See Note 2)
—
5T-26
+
cyc × ws
—
5T-24
+
cyc × ws
—
5T-22
+
cyc × ws
ns
22
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)
40 MHz
50 MHz
Min
60 MHz
Num
Characteristics
Unit
Min
Max
Max
Min
Max
21
Delay from General-Purpose
Output Valid Caused by the
Execution of the First Inter-
rupt Instruction to IRQA,
IRQB Deassertion for Level
Sensitive Fast Interrupts — If
2nd Interrupt Instruction is:
Single Cycle
—
—
14
cyc - 29
3 cyc - 29
cyc-3
—
—
13
cyc - 27
3 cyc - 27
cyc-2
—
—
12
cyc - 26
3 cyc - 26
cyc-1
ns
ns
ns
(See Note 2)
Two Cycles
22
23
Synchronous setup time from
IRQA, IRQB assertion to
Synchronous falling edge of
CLKO (See Notes 5 and 6)
27T+3
27T+20
27T+3
27T+18
27T+3
27T+16
ns
ns
Falling Edge of CLKO to First
Interrupt Vector Address Out
Valid after Synchronous
recovery from Wait State
(See Notes 3 and 5)
15
—
13
—
12
—
24
25
IRQA Width Assertion to
Recover from Stop State
(See Note 4)
Delay from IRQA Assertion to
Fetch of first instruction (exit-
ing Stop)
(See Notes 1 and 3)
OMR bit 6=0
524303T+4
47T+4
—
—
524303T+3
47T+3
—
—
524303T+3
47T+3
—
—
ns
ns
OMR bit 6=1
28
29
Duration for Level Sensitive
IRQA Assertion to Cause the
Fetch of First IRQA Interrupt
Instruction (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
524303T
47T
—
—
524303T
47T
—
—
524303T
47T
—
—
ns
ns
OMR bit 6=1
Delay from Level Sensitive
IRQA Assertion to First Inter-
rupt Vector Address Out
Valid (exiting Stop)
(See Notes 1 and 3)
OMR bit 6=0
524303T+4
47T+4
—
—
524303T+3
47T+3
—
—
524303T+3
47T+3
—
—
ns
ns
OMR bit 6=1
MOTOROLA
DSP56156 Data Sheet
23
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTES: 1. Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset
• when recovering from Stop mode
2. When using fast interrupts, IRQA or IRQB is defined as level-sensitive, then timings 20 and 21
apply to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-trig-
gered mode is recommended when using fast interrupts.
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover
from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted.
5. Timing #22 is for all IRQx interrupts while timing #23 is only when exiting the Wait state.
6. Timing #22 triggers off T1 in the normal state and off phi1 when exiting the Wait state.
7. The instruction fetch is visible on the pins only in Mode 2 and Mode 3.
VIHR
RESET
12
11
10
D0-D15
A0-A15
PS/DS
R/W
First Fetch
BS
Figure 7 Asynchronous Reset Timing
CLKO
13
RESET
14
A0-A15
PS/DS
BS
R/W
Figure 8 Synchronous Reset Timing
24
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
VIHR
RESET
15
16
VIHM
VILM
VIH
MODA
MODB
MODC
IRQA
VIL
IRQB
Figure 9 Operating Mode Select Timing
IRQA
IRQB
17
Figure 10 External Interrupt Timing (Negative Edge-Triggered)
A0-A15
PS/DS
BS
First Interrupt Instruction Execution
R/W
18
20
IRQA
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
19
21
IRQA
IRQB
b) General Purpose I/O
Figure 11 External Level-Sensitive Fast Interrupt Timing
MOTOROLA
DSP56156 Data Sheet
25
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
T1, T3
phi1
T0, T2
CLKO
phi0
22
IRQA
IRQB
23
A0-A15
PD/DS
BS
First Interrupt
Instruction Fetch
R/W
Figure 12 Synchronous Interrupt from Wait State Timing
24
IRQA
25
A0-A15
PD/DS
BS
First Instruction Fetch
Not IRQA Interrupt Vector
R/W
Figure 13 Recovery from Stop State Using Asynchronous Interrupt Timing
28
IRQA
29
A0-A15
PD/DS
BS
First IRQA Interrupt
Instruction Fetch
R/W
Figure 14 Recovery from Stop State Using IRQA Interrupt Service
26
DSP56156 Data Sheet
MOTOROLA
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 14 Wait and Stop Timings
40 MHz
50 MHz
60 MHz
Num
Characteristics
Unit
Min
Max
Min
Max
Min
Max
30
DR Asserted to CLK high (Setup
Time for Synchronous Recovery
from Wait State)
10
cyc - 4
9
cyc - 3
8
cyc - 2
ns
31
CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Syn-
chronous Recovery from Wait
State
18 cyc
—
18 cyc
—
18 cyc
—
ns
32
DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery
from Stop State
- After Asynchronous Recovery
from Wait State
29 cyc
18 cyc
—
—
29 cyc
18 cyc
—
—
29 cyc
18 cyc
—
—
ns
ns
33
DR Assertion Width
- to Recover from Wait/Stop
without entering debug mode
- to Recover from Wait/Stop
short wake-up and enter
debug mode
12
10 cyc
—
11
10 cyc
—
10
10 cyc
—
ns
ns
29 cyc
29 cyc
29 cyc
- to Recover from Stop
long wake-up and enter
debug mode
262157
cyc
—
262157
cyc
—
262157
cyc
—
ns
33
DR
(input)
32
DSO
(output)
Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing
MOTOROLA
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Capacitance Derating
T1, T3
T0, T2
CLKO
(output)
33
DR
(input)
30
31
DSO
(output)
Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing
Capacitance Derating
The DSP56156 External Bus Timing Specifications are designed and tested at the maximum ca-
pacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the Exter-
nal Bus pins (A0-A15, D0-D15, PS/ DS, RD, BS, WR, R/ W) derates linearly at 1 ns per 12 pF of
additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns
per 5 pF of additional capacitance from 50 pF to 250 pF of loading.
When an internal memory access follows an external memory access, the PS/ DS, R/ W, RD
and WR strobes remain deasserted and A0-A15 do not change from their previous state.
28
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
External Bus Synchronous Timing
External Bus Synchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings
with no wait states and two wait states, respectively.
Table 15 External Bus Synchronous Timing
40 MHz
50 MHz
60 MHz
Max
Num
Characteristic
Unit
Min
Max
Min
Max
Min
34
35
EXTAL CLK In High to CLKO High
2.4
9
2.4
9
2.4
9
ns
CLKO High to
a. A0-A15 Valid
4.7
4.7
12
14
—
4.7
4.7
12
14
—
4.7
4.7
9.8
12
ns
ns
ns
ns
ns
(See Note)
b. PS/DS, R/W Valid, BS, RD Asserted
BS Width Deasserted
4
—
36
37
38
18.3
13.4
CLKO High to WR Asserted Low
T+3.1 T+12.4 T+3.1 T+12.4 T+3.1
T+12.4
11.8
WR and RD Deasserted High to BS
14.3
15.8
11.8
13.3
10.2
Asserted Low (2 Successive Bus Cycles)
39
40
<intentionally blank>
CLKO High to BS Deasserted
TA Valid to CLKO High (Setup)
CLKO High to TA Invalid (Hold)
CLKO High to D0-D15 Out Valid
CLKO High to D0-D15 Out Invalid
D0-D15 In Valid to CLKO Low (Setup)
CLKO Low to D0-D15 In Invalid (Hold)
CLKO Low to WR, RD Deasserted
WR, RD Hold Time from CLKO Low
CLKO High to D0-D15 Three-state
CLKO High to D0-D15 Out Active
CLKO High to A0-A15, PS/DS, R/W Invalid
10 ns CL = 25 pF
2.6
4.5
0
10.3
—
—
7.1
—
—
—
10
—
6
2.6
4.5
0
10.3
—
—
7.1
—
—
—
10
—
6
2.6
4.5
0
10.3
—
—
7.1
—
—
—
10
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41
42
43
1.7
2.0
6
1.7
2.0
6
1.7
2.0
6
44
45
46
0
0
0
47
—
2.2
0
—
2.2
0
—
2.2
0
48
49
50
1.2
2.8
4.2
—
1.2
2.8
4.2
—
1.2
2.8
4.2
—
51
NOTE:
MOTOROLA
DSP56156 Data Sheet
29
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AC Electrical Characteristics and Timing
External Bus Synchronous Timing
T0
T1
T2
T3
T0
T1
T2
EXTAL
(Input)
CLKO
34
(Output)
35
35
51
A0-A15
PS/DS
R/W
(See Note)
36
BS
(Output)
40
37
35
WR
(Output)
47
48
48
RD
(Output)
47
41
42
41
TA
(Input)
43
44
D0-D15
(Output)
Data Out
49
50
45
46
D0-D15
(Input)
Data In
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
Figure 17 External Bus Synchronous Timing — No Wait States
30
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
External Bus Synchronous Timing
T0
T1
T2
Tw
T2
Tw
T2
T3
T0
EXTAL
(Input)
CLKO
(Output)
34
35
35
37
51
A0-A15,
PS/DS, R/W
(Outputs)
36
BS
(Output)
40
WR
(Output)
47
48
48
35
RD
(Output)
47
41
41
42
42
TA
(Input)
44
43
50
49
D0-D15
(Output)
Data Out
46
45
D0-D15
(Input)
Data In
Figure 18 External Bus Synchronous Timing – Two Wait States
MOTOROLA
DSP56156 Data Sheet
31
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AC Electrical Characteristics and Timing
External Bus Asynchronous Timing
External Bus Asynchronous Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
1
cyc = Clock cycle = / instruction cycle = 2 T cycles
2
WS = Number of Wait States, Determined by BCR Register (WS = 0 to 31)
WT = WS × cyc = 2T × WS
32
DSP56156 Data Sheet
MOTOROLA
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AC Electrical Characteristics and Timing
External Bus Asynchronous Timing
A0-A15,
PS/DS, R/W
(See Note)
60
59
BS
RD
64
62
66
67
55
52
53
68
56
54
69
WR
65
63
58
57
61
Data Out
Data In
D0-D15
NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state.
Figure 19 External Bus Asynchronous Timing
MOTOROLA
DSP56156 Data Sheet
33
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AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
Bus Arbitration Timing — Slave Mode
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
cyc = Clock cycle = 1/ 2 instruction cycle = 2 T cycles
WS = Number of Wait States for external X or P memory, Determined by BCR
Register (WS = 0 to 31)
WT = WS × cyc=2T × WS
WX = Number of Wait States for external X memory, Determined by BCR
Register (WS = 0 to 31)
WP = Number of Wait States for external P memory, Determined by BCR
Register (WS = 0 to 31)
Table 17 Slave Mode
40/50/60 MHz
Num
Characteristics
Unit
Min
Max
70
71
BR Input to CLKO low setup time
0
1
ns
ns
Delay from BR Input Assertion to
BG Output Assertion
(See Note 1)
(See Note 2)
(See Note 3)
5T+1.9
3T+1.9
5T+1.9
9T+4.2
6T+WT+4.2
26T+4T x WX
+2T x WP+4.2
NA
(See Note 4)
(See Note 5)
NA
T+1.9
3T+4.2
72
73
CLKO high to BG Output Assertion
BG Output Deassertion Duration
1.9
5.2
ns
ns
(See Note 1)
(See Note 5)
(See Note 6)
5T-0.5
2T-0.5
3T-0.5
—
—
—
74
75
76
77
CLKO High to Control Bus High Impedance
CLKO High to BB Output Deassertion
CLKO High to BB Input
2.7
3.2
3.3
6.5
7.8
8.1
ns
ns
ns
ns
BR Input Deassertion to
BG Output Deassertion
(See Note 1)
(See Note 5)
(See Note 7)
4T+2.5
3T+3.2
3T+3.2
9T+6.4
8T+7.8
8T+8.0
78
CLKO Low to BG Deassertion
CLKO High to BG Deassertion
CLKO High to BG Deassertion
(See Note 1)
(See Note 5)
(See Note 7)
2.5
3.2
3.2
6.4
7.8
8.0
ns
79
80
81
82
CLKO High to BB Output Active
1.3
2.3
1
3.6
5
ns
ns
ns
ns
CLKO High to BB Output Assertion
CLKO High to Address and Control Bus Active
CLKO High to Address and Control Bus Valid
3
2
4.4
NOTES: 1. With no external access from the DSP56156
2. During external read or write access
3. During external read-modify-write access
4. During Stop mode — external bus is released and BG is always low
5. During Wait mode
6. With external accesses pending by the DSP56156
7. Slave mode, when bus is still busy after bus request has been deasserted
34
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
CLKO
(Output)
70
71
73
BR
(Input)
72
BG
(Output)
75
BB
(I/O)
76
A0-A15
PS/DS
R/W
74
D0-D15
74
Figure 20 Bus Arbitration Timing — Slave Mode — Bus Release
MOTOROLA
DSP56156 Data Sheet
35
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AC Electrical Characteristics and Timing
Bus Arbitration Timing — Slave Mode
CLKO
(Output)
70
BR
77
(Input)
78
BG
(Output)
79
BB
(I/O)
80
82
81
A0-A15
PS/DS
R/W
Figure 21 Bus Arbitration Timing — Slave Mode — Bus Acquisition
36
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Bus Arbitration Timing — Master Mode
Bus Arbitration Timing — Master Mode
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
Table 18 Master Mode
40 MHz
50 MHz
60 MHz
Num
Characteristic
Unit
Min Max Min Max Min Max
85
86
CLKO High to BR Output Assertion
CLKO High to BR Output Deassertion
4.7
12
4.7
12
4.7
12
ns
BG Input Asserted/ Deasserted to CLKO
Low (Setup)
9.2
—
6.5
—
4.5
—
ns
87
88
89
90
CLKO Low to BG Input Invalid (Hold)
BB Input Deasserted to CLKO Low (Setup)
CLKO Low to BB Input Deasserted (Hold)
CLKO High to BB Output Asserted
0
9.2
0
—
—
—
12
0
—
—
—
12
0
4.5
0
—
—
—
12
ns
ns
ns
ns
6.5
0
4.7
4.7
4.7
CLKO
(Output)
85
BR
(Output)
87
BG
(Input)
86
88
BB
Three-state
(I/O)
89
90
82
81
A0-A15
PS/DS
R/W
Figure 22 Bus Arbitration Timing — Master Mode — Bus Acquisition
MOTOROLA
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Bus Arbitration Timing — Master Mode
CLKO
(Output)
85
BR
(Output)
86
87
BG
(Input)
75
BB
76
(I/O)
A0-A15
PS/DS
R/W
74
Figure 23 Bus Arbitration Timing — Master Mode — Bus Release
38
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Host Port Timing
Host Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
T
= ICYC / 4
cyc = Clock cycle = 1/ 2 instruction cycle= 2 T cycle
t
= Host Synchronization Delay Time (See Note 1)
= Host Processor Data Setup Time
HSDL
t
suh
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifica-
tions.
Table 19 Host Port Timing
40 MHz
50 MHz
60 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
100
101
tHSDL Host Synchronous Delay
(See Note 1)
T
3T
T
3T
T
3T
ns
HEN/HACK Assertion Width
• CVR, ICR, ISR Read
• Read
2T+36
32+tsuh
32
2T+33
29+tsuh
29
2T+30
26+tsuh
26
ns
—
—
—
—
—
—
• Write
(See Notes 2, 4)
102
103
HEN/HACK Deassertion Width
(See Note 2)
31
—
—
29
—
—
27
—
—
ns
ns
Minimum Cycle Time Between Two
HEN Assertion for Consecutive
CVR, ICR, ISR Reads
4T+36
4T+33
4T+30
104
105
106
107
108
109
Host Data Input Setup Time before
HEN/HACK Deassertion
5
7
—
—
—
32
20
—
4
6
—
—
3
5
—
—
—
26
17
—
ns
ns
ns
ns
ns
ns
Host Data Input Hold Time after
HEN/HACK Deassertion
HEN/HACK Assertion to Output
Data Active from High Impedance
0
0
—
0
HEN/HACK Assertion to Output
Data Valid
—
—
5
—
—
5
29
—
—
4
HEN/HACK Deassertion to Output
Data High Impedance
18.5
—
Output Data Hold Time after
HEN/HACK Deassertion
MOTOROLA
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AC Electrical Characteristics and Timing
Host Port Timing
Table 19 Host Port Timing (continued)
40 MHz 50 MHz
Min Max
60 MHz
Min Max
Num
Characteristic
Unit
Min
Max
110
111
112
113
HR/W Low Setup Time before HEN Assertion
HR/W Low Hold Time after HEN Deassertion
HR/W High Setup Time to HEN Assertion
6
6
6
5
—
—
—
—
5
5
5
4
—
—
—
—
4
4
4
3
—
—
—
—
ns
ns
ns
ns
HR/W High Hold Time after HEN/HACK
Deassertion
114
115
116
HA0-HA2 Setup Time before HEN Assertion
HA0-HA2 Hold Time after HEN Deassertion
9
8
5
—
—
7.5
7
—
—
6
6
4
—
—
ns
ns
ns
DMA HACK Assertion to HREQ Deassertion
(See Note 3)
2T
+37
5
2T
+36
2T
+35
117
DMA HACK Deassertion to HREQ
Assertion (See Note 3)
for DMA RXL Read
tHSDL
+3T+5
—
tHSDL
3T+5
—
tHSDL
+3T+4
—
ns
ns
ns
for DMA TXL Write
tHSDL
+2T+5
—
—
tHSDL
+2T+5
—
—
tHSDL
+2T+4
—
—
for All Other Cases
5
5
4
118
119
120
Delay from HEN Deassertion to HREQ
Assertion for RXL Read (See Note 3)
tHSDL
+3T+5
—
—
tHSDL
+3T+5
—
—
tHSDL
+3T+4
—
—
ns
ns
ns
Delay from HEN Deassertion to HREQ
Assertion for TXL Write (See Note 3)
tHSDL
+2T+5
tHSDL
+2T+5
tHSDL
+2T+4
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(See Note 3)
5
2T
+37
5
2T
+36
5
2T
+35
NOTES: 1. “Host Synchronization Delay (tHSDL)” is the time period required for the DSP56156 to sample any
external asynchronous input signal, determine whether it is high or low, and synchronize it to the
internal clock.
2. See Host Port Considerations.
3. HREQ is pulled up by 1 kΩ.
4. Only if two consecutive reads from one of these registers are executed.
40
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
Host Port Timing
External
Internal
100
100
Figure 24 Host Synchronization Delay
HREQ
(Output)
103
101
102
HACK
(Input)
113
112
HR/W
(Input)
107
108
109
106
H0-H7
Data
Valid
(Output)
Figure 25 Host Interrupt Vector Register (IVR) Read
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AC Electrical Characteristics and Timing
Host Port Timing
120
HREQ
(Output)
118
103
HEN
RXH
Read
RXL
Read
(Input)
101
114
102
115
HA0-HA2
(Input)
Address
Valid
Address
Valid
112
113
HR/W
(Input)
107
106
108
109
Data
Valid
Data
Valid
H0-H7
(Output)
Figure 26 Host Read Cycle (Non-DMA Mode)
HREQ
120
119
(Output)
103
HEN
TXH
TXL
(Input)
Write
Write
101
114
102
115
HA0-HA2
(Input)
Address
Valid
Address
Valid
110
111
HR/W
(Input)
104
105
H0-H7
(Input)
Data
Valid
Data
Valid
Figure 27 Host Write Cycle (Non-DMA Mode)
42
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AC Electrical Characteristics and Timing
Host Port Timing
HREQ
(Output)
116
117
102
101
RXH
Read
RXL
Read
HACK
(Input)
108
107
106
109
H0-H7
Data
Valid
Data
Valid
(Output)
Figure 28 Host Read Cycle (DMA Mode)
HREQ
(Output)
116
104
117
101
102
HACK
(Input)
TXH
Write
TXL
Write
105
H0-H7
(Input)
Data
Valid
Data
Valid
Figure 29 Host Write Cycle (DMA Mode)
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AC Electrical Characteristics and Timing
SSI Timing
Synchronous Serial Interfaces (SSI) Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to + 125°C, C = 50 pF + 1 TTL Load)
L
T = ICYC / 4
SCK = Serial Clock Pin
FST (Transmit Frame Sync) = SCx0 Pin
FSR (Receive Frame Sync) = SCx1 Pin
i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous
implies that FSR and FST are two different frame syncs)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies
that only one frame sync FS is used)
bl = bit length
wl = word length
Table 20 Synchronous Serial Interfaces Timing
40/50/60 MHz
Num
Characteristic
Case
Unit
Min
Max
130
131
132
133
134
Clock Cycle (See Note)
Clock High Period
100
45
45
—
—
—
—
7
—
—
—
—
ns
ns
ns
ns
ns
Clock Low Period
Output Clock Rise/Fall Time
SCK Rising Edge to FSR Out
(bl) High
—
—
32
18
x ck
i ck a
135
136
137
138
139
SCK Rising Edge to FSR Out
(bl) Low
—
—
32
15
x ck
i ck a
ns
ns
ns
ns
ns
SCK Rising Edge to FSR Out
(wl) High
—
—
32
15
x ck
i ck a
SCK Rising Edge to FSR Out
(wl) Low
—
—
32
15
x ck
i ck a
Data In Setup Time before SCK
Falling Edge
30
40
—
—
x ck
i ck
Data In Hold Time after SCK
Falling Edge
25
12
—
—
x ck
i ck
NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-
inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables
and in the figures.
44
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
SSI Timing
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AC Electrical Characteristics and Timing
SSI Timing
Table 20 Synchronous Serial Interfaces Timing (continued)
40/50/60MHz
Num
Characteristic
Case
Unit
Min
Max
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
FSR Input (bl) High before SCK
Falling Edge
7
15
—
—
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSR Input (wl) High before SCK
Falling Edge
7
15
—
—
x ck
i ck a
FSR Input Hold Time after SCK
Falling Edge
15
7
—
—
x ck
i ck a
Flags Input Setup before SCK
Falling Edge
7
15
—
—
x ck
i ck
Flags Input Hold Time after SCK
Falling Edge
15
7
—
—
x ck
i ck
SCK Rising Edge to FST Out
(bl) High
—
—
33
15
x ck
i ck
SCK Rising Edge to FST Out
(bl) Low
—
—
30
15
x ck
i ck
SCK Rising Edge to FST Out
(wl) High
—
—
30
15
x ck
i ck
SCK Rising Edge to FST Out
(wl) Low
—
—
33
15
x ck
i ck
SCK Rising Edge to Data Out
Enable from High Impedance
—
—
30
12
x ck
i ck
SCK Rising Edge to Data Out Valid
—
—
30
12
x ck
i ck
SCK Rising Edge to Data Out High
Impedance
—
—
30
20
x ck
i ck
FST Input (bl) Setup Time before SCK
Falling Edge
6
16
—
—
x ck
i ck
FST Input (wl) to Data Out Enable from
High Impedance
—
36
—
FST Input (wl) Setup Time before SCK
Falling Edge
8
17
—
—
x ck
i ck
FST Input Hold Time after SCK
Falling Edge
15
4
—
—
x ck
i ck
Flag Output Valid after SCK
Rising Edge
—
—
32
15
x ck
i ck
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AC Electrical Characteristics and Timing
SSI Timing
130
131
132
135
136
133
SCK
(Input/Output)
134
FSR (Bit)
Out
137
FSR (Word)
Out
138
139
First Bit
Last Bit
Data In
140
142
FSR (Bit)
In
141
142
144
FSR (Word)
In
143
Flags In
Figure 30 SSI Receiver Timing
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AC Electrical Characteristics and Timing
Timer Timing
130
131
132
146
133
SCK
(Input/Output)
145
FST (Bit)
Out
147
148
FST (Word)
Out
150
149
150
151
Data Out
First Bit
Last Bit
152
155
FST (Bit)
In
153
154
155
FST (Word)
In
156
(See Note)
Flags Out
Figure 31 SSI Transmitter Timing
NOTE: In the Network mode, output flag transitions can occur at the start of each time slot within the frame.
In the Normal mode, the output flag state is asserted for the entire frame period.
48
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
OnCE Port Timing
Timer Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
Table 21 Timer Timing
40/50/60 MHz
Num
Characteristic
Unit
Min
Max
170
171
172
173
174
175
TIN Valid to CLKO Low (Setup time)
CLKO Low to TIN Invalid (Hold time)
CLKO High to TOUT Asserted
CLKO High to TOUT Deasserted
TIN Period
6
—
—
ns
ns
ns
ns
ns
ns
0
3.5
5.1
8T
4T
14
20.7
—
TIN High/Low Period
—
CLKO
(Output)
170
TIN
(Input)
172
173
171
TOUT
(Output)
Figure 32 Timer Timing
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AC Electrical Characteristics and Timing
OnCE Port Timing
OnCETM Port Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, C = 50 pF + 1 TTL Load)
L
Table 22 OnCE Port Timing
40/50/60 MHz
Num
Characteristic
Unit
Min
Max
180
181
182
183
184
185
186
187
188
DSCK High to DSO Valid
—
5.2
0
37
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
DSI Valid to DSCK Low (Setup)
DSCK Low to DSI Invalid (Hold)
DSCK High
—
(See Note 1)
(See Note 1)
(See Note 1)
2Tc
2Tc
4Tc
—
DSCK Low
—
DSCK Cycle Time
—
CLKO High to OS0-OS1 Valid
CLKO High to OS0-OS1 Invalid
14.5
—
—
Last DSCK High to OS0-OS1
Last DSCK High to ACK Active (data)
Last DSCK High to ACK Active (command)
(See Note 2)
(See Note 2)
(See Note 2)
10T+Td+14.5
10T+Td+13.5
21T+Td+13.5
—
—
189
190
191
DSO (ACK) Asserted to OS0-OS1 Three-state
DSO (ACK) Asserted to First DSCK High
—
0
ns
ns
3Tc
—
DSO (ACK) Width Asserted:
• when entering debug mode
3T-2
2Tc+0.5
3T-5
2Tc+3
ns
ns
• when acknowledging command/data transfer
192
Last DSCK High of Read Register to First
DSCK High of Next Command
6Tc
—
ns
193
194
DSCK High to DSO Invalid
(See Note 2)
Td+11.2
—
—
ns
ns
DR asserted to DSO (ACK) Asserted
11T+19.5
NOTES: 1. 45%-55% duty cycle
2. Td = DSCK High (Timing #183)
50
DSP56156 Data Sheet
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AC Electrical Characteristics and Timing
OnCE Port Timing
183
DSCK
(Input)
184
185
Figure 33 OnCE Port Serial Clock Timing
DR
(Input)
194
DSO
(Output)
ACK
Figure 34 OnCE Port Acknowledge Timing
DSCK
(Input)
(Last)
(OS1)
(See Note)
193
180
DSO
(ACK)
(OS0)
(Output)
DSI
(Input)
181
182
188
NOTE: Three-state, external pull-down resistor
Figure 35 OnCE Port Data I/O To Status Timing
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Pin-out and Package
Top View
Pin-out and Package Information
GND4
D2
1
MODA/IRQA
RESET
D3
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
Orientation Mark
VCC3
D4
D5
GND5
D6
D7
D8
TOUT/PC11
HA0/PB8
GND10
D9
GND6
D10
D11
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
VCC4
D12
D13
GND7
D14
D15
TA
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
H3/PB3
H2/PB2
VCC6
(Top View)
H5/PB5
H6/PB6
57
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
Figure 39 Top View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages
52
DSP56156 Data Sheet
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Bottom View
MODA/IRQA
RESET
1
GND4
D2
STD0/PC0
SRD0/PC1
SCK0/PC2
SC10/PC3
SC00/PC4
TIN/PC10
VCC7
D3
Orientation Mark
(on Top side)
VCC3
D4
D5
GND5
D6
D7
TOUT/PC11
HA0/PB8
GND10
D8
D9
GND6
D10
D11
HA1/PB9
HA2/PB10
HR/W/PB11
HEN/PB12
HACK/PB14
HREQ/PB13
H0/PB0
VCC4
D12
D13
GND7
D14
D15
TA
H1/PB1
STD1/PC5
SRD1/PC6
H4/PB4
DR
VCCA
SPKP
SPKM
GNDA
VDIV
VREF
H3/PB3
H2/PB2
VCC6
(Bottom View)
H5/PB5
H6/PB6
57
NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
Figure 40 Bottom View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages
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Pin-out and Package
General Purpose I/O
Table 23 DSP56156 General Purpose I/O Pin Identification
DSP56156
112-pin
Package
Pin #
DSP56156
Primary Pin
Function
General
Purpose I/O
ID
66
65
60
61
62
58
57
56
74
72
71
70
69
67
68
82
81
80
79
78
64
63
55
54
52
77
75
H0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
H1
H2
H3
H4
H5
H6
H7
HA0
HA1
HA2
HR/W
HEN
HREQ
HACK
STD0
SRD0
SCK0
SC10
SC00
STD1
SRD1
SCK1
SC11
SC01
TIN
TOUT
NOTES: 1. In Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low).
2. For more information on power and ground, see Table 26 under Design Considerations.
54
DSP56156 Data Sheet
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Pin Number
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Pin-out and Package
Signal Name
Table 24 DSP56156 Pin Identification by Pin Number
112-pin
Package
Pin #
112-pin
Package
Pin #
112-pin
Package
Pin #
Signal Name
Signal Name
Signal Name
1
GND4
39
RD
76
VCC7
2
3
4
D2
40
41
42
PS/DS
BS
77
78
79
TIN/PC10
SC00/PC4
SC10/PC3
D3
VCC3
R/W
5
6
D4
43
44
45
46
47
48
49
50
DSO
80
81
82
83
84
85
86
87
SCK0/PC2
SRD0/PC1
STD0/PC0
RESET
D5
DSCK/OS1
DSI/OS0
CLKO
7
GND5
D6
8
9
D7
GNDQ0
GNDS
SXFC
MODA/IRQA
MODB/IRQB
MODC
10
11
12
D8
D9
GND6
VCCS
A0
13
14
15
D10
D11
51
52
53
EXTAL
88
89
90
A1
SC01/PC9
GND9
GND0
A2
VCC4
16
17
D12
D13
54
55
SC11/PC8
SCK1/PC7
91
92
A3
VCC1
18
19
20
21
GND7
D14
D15
TA
56
57
58
59
H7/PB7
H6/PB6
H5/PB5
VCC6
93
94
95
96
A4
A5
GND1
VCCQ1
22
23
DR
60
61
H2/PB2
H3/PB3
97
98
A6
A7
VCCA
24
25
26
27
28
SPKP
SPKM
GNDA
VDIV
62
63
64
65
66
H4/PB4
99
100
101
102
103
A8
SRD1/PC6
STD1/PC5
H1/PB1
A9
GND2
A10
VCC2
VREF
H0/PB0
29
30
31
32
33
MIC
67
68
69
70
71
HREQ/PB13
HACK/PB14
HEN/PB12
HR/W/PB11
HA2/PB10
104
105
106
107
108
GNDQ1
A11
AUX
BIAS
BG
A12
A13
VCCQ0
GND3
34
35
36
BR
72
73
74
HA1/PB9
GND10
109
110
111
A14
A15
D0
BB
VCC5
HA0/PB8
37
38
WR
75
TOUT/PC11
112
D1
GND8
56
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Signal Name
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Pin-out and Package
Table 25 DSP56156 Pin Identification by Signal Name
112-pin
Package Signal Name Package Signal Name Package Signal Name
Pin # Pin # Pin #
112-pin
112-pin
87 47
A0
6
8
9
D5
GNDQ0
GNDQ1
GNDS
H0
88
90
A1
D6
104
48
66
65
60
61
62
58
57
56
74
72
71
68
69
70
67
84
85
29
84
85
86
45
44
66
65
A2
D7
91
A3
10
11
13
14
16
17
19
20
22
44
45
43
51
89
95
101
108
1
D8
93
A4
D9
H1
94
A5
D10
H2
97
A6
D11
H3
98
A7
D12
H4
99
A8
D13
H5
100
102
105
106
107
109
110
30
A9
D14
H6
A10
A11
A12
A13
A14
A15
AUX
BB
D15
H7
DR
HA0
DSCK
DSI
HA1
HA2
DSO
EXTAL
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GNDA
HACK
HEN
HR/W
HREQ
IRQA
IRQB
MIC
35
32
BG
BIAS
BR
BS
31
34
41
7
MODA
MODB
MODC
OS0
OS1
PB0
46
CLKO
D0
12
18
38
53
73
26
111
112
2
D1
D2
3
D3
5
D4
PB1
58
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Pin-out and Package
Table 25 DSP56156 Pin Identification by Signal Name (continued)
112-pin
Package Signal Name Package Signal Name Package Signal Name
Pin # Pin # Pin #
112-pin
112-pin
60 55 64
PB2
PB3
PB4
PB5
PB6
PB7
PC7
STD1
SXFC
TA
61
62
58
57
56
54
52
77
75
40
PC8
49
21
77
75
92
PC9
PC10
PC11
PS/DS
TIN
TOUT
VCC1
74
72
71
70
69
67
68
82
81
80
PB8
42
39
83
78
52
79
54
80
55
25
R/W
103
4
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCCA
VCCQ0
VCCQ1
VCCS
PB9
RD
PB10
PB11
PB12
PB13
PB14
PC0
RESET
SC00
SC01
SC10
SC11
SCK0
SCK1
SPKM
15
36
59
76
23
33
96
50
PC1
PC2
79
78
64
63
PC3
PC4
PC5
PC6
24
81
63
82
SPKP
SRD0
SRD1
STD0
27
28
37
VDIV
VREF
WR
60
DSP56156 Data Sheet
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Pin-out and Package
112 CQFP
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Pin-out and Package
S
TOP
VIEW
S
S
0.20 (0.008) M
S
S
T L-M
N
N
A
0.20 (0.008)
M
T
L-M
J1
J1
PIN 1
Identifier
112
85
1
84
VIEW Y
P
-L-, -M-, -N-
VIEW Y
-L-
-M-
3 Place
B
V
PLATING
F
28
57
B1
J
29
56
-N-
BASE
METAL
D
M
S
S
0.127 (0.005)
L-M
N
T
VIEW P
C
E
SECTION J1-J1
112 Place
VIEW ROTATED 90°
DATUM
PLANE
-H-
0.15 (0.006)
SEATING
PLANE
W
-T-
G 108 Place
A1
Case 915-01
MILLIMETERS
MIN MAX
INCHES
θ1
DIM
A
MIN
MAX
R R1
18.880 20.400
18.880 20.400
0.743
0.743
0.108
0.009
0.092
0.009
0.803
0.803
0.135
0.015
0.120
0.013
B
DATUM
PLANE
-H-
C
2.740
0.220
2.340
0.220
3.450
0.380
3.060
0.330
R R2
D
E
θ2
F
G
0.650 BSC
0.0256 BSC
K
J
0.130
0.650
0.230
0.950
0.005
0.026
0.009
0.037
K
C1
P
0.325 BSC
22.950 23.450
22.950 23.450
0.300
0.0128 BSC
0.904
0.904
0.012
0.008
0.923
VIEW P
S
V
0.923
0.024
W
A1
B1
C1
R1
NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
0.200
0.120
0.600
2. Controlling dimension: millimeter.
0.132 0.0047 0.0052
3. Datum plane -H- is coincident with the bottom of the lead
where the lead exits the ceramic body.
1.800 REF
0.200 REF
0.200 REF
0.070 REF
0.008 REF
0.008 REF
4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
R2
θ1
8°
8°
8°
8°
0°
0°
0°
0°
6. Dimensions A and B define maximum ceramic body dimensions
including glass protrusion and mismatch.
θ2
NOTE: BSC = Between Statistical Center
(i.e., typical)
Figure 41 DSP56156 112-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information
62
DSP56156 Data Sheet
MOTOROLA
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Pin-out and Package
112 TQFP
MOTOROLA
DSP56156 Data Sheet
63
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Pin-out and Package
4x
0.200 (0.008) H
L-M N
J1
J1
4x 28 TIPS
85
0.200 (0.008) T L-M N
PIN 1
Identifier
4x
P
112
-L-, -M-, -N-
1
84
VIEW Y
108x
G
-M-
-L-
VIEW Y
B
V
J
AA
B1
V1
BASE
METAL
F
D
M
28
57
M
0.13 (0.005)
T L-M
M
C
29
56
-N-
TOP
VIEW
SECTION J1-J1
(VIEW ROTATED 90° COUNTER CLOCKWISE)
A1
S1
A
S
Case 987-01
C2
VIEW AB
0.050 (0.002)
S
C
θ2
θ3
MILLIMETERS
MIN MAX
INCHES
MIN MAX
0.100 (0.004)
DIM
A
-H-
SEATING
-T-
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
0.790 BSC
0.395 BSC
0.790 BSC
0.395 BSC
PLANE
A1
B
B1
C
θ
1.400
1.600
0.150
1.450
0.370
0.750
0.330
0.055
0.063
0.006
0.057
0.014
0.030
0.013
C1 0.050
C2 1.350
0.002
0.053
0.011
0.018
0.011
R2
R1
D
E
F
0.270
0.450
0.270
0.25 (0.010)
GAGE PLANE
G
J
0.650 BSC
0.0256 BSC
0.115
0.175
0.006
0.007
K
P
0.500 BSC
0.325 BSC
0.020 BSC
0.013 BSC
K
C1
R1 0.100
R2 0.100
0.200
0.200
0.004
0.004
0.008
0.008
θ1
E
Y
S
S1
V
22.000 BSC
11.000 BSC
0.866 BSC
Z
0.433 BSC
0.866 BSC
0.433 BSC
0.010 REF
0.039 REF
VIEW AB
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
V1
Y
NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M, 1982.
2. Controlling dimension: Millimeter.
Z
3. Datum plane -H- is located at bottom of lead and is coincident with the lead
where the lead exits the plastic body at the bottom of the parting line.
4. Datums -L-, -M- and -N- to be determined at datum plane -H-.
5. Dimensions S and V to be determined at seating plane -T-.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is
0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are
determined at datum plane -H-.
AA 0.115
0.135
8°
0.004
0.005
θ
0°
3°
0°
3°
8°
7°
θ1
θ2
θ3
7°
11°
11°
13°
13°
11°
11°
13°
13°
NOTE: BSC = Between Statistical Center
7. Dimension D does not include dambar protrusion. Allowable dambar
protrusion shall not cause the D dimension to exceed 0.43 (0.017).
(i.e., typical)
Figure 42 DSP56156 112-pin Plastic Thin Quad Flat Pack (TQFP) Mechanical Information
64
DSP56156 Data Sheet
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Design Considerations
Heat Dissipation
Power, Ground, and Noise
Design Considerations
ΘJC is device-related and cannot be influ-
Heat Dissipation
enced by the user. However, ΘCA is user-de-
pendent and can be minimized by such
thermal management techniques as heat
sinks, ambient air cooling, and thermal con-
vection. Thus, good thermal management on
the part of the user can significantly reduce
ΘCA so that ΘJA approximately equals ΘJC.
Substitution of ΘJC for ΘJA in equation (1) will
result in a lower semiconductor junction
temperature. Values for thermal resistance
presented in this document, unless estimat-
ed, were derived using the procedure de-
scribed in Motorola Reliability Report 7843,
“Thermal Resistance Measurement Method
for MC68XX Microcomponent Devices”, and
are provided for design purposes only. Ther-
mal measurements are complex and depen-
dent on procedure and setup. User-derived
values for thermal resistance may differ.
The average chip junction temperature, TJ, in
°C, can be obtained from:
TJ = TA + (PD × ΘJA)
Where:
(1)
TA = ambient temperature, °C
ΘJA = package thermal resistance,
junction-to-ambient, °C/ W
PD = PINT + PI/ O
PINT = ICC × VCC watts — chip internal
power
PI/ O = power dissipation on input and
output pins — user determined
For most applications PI/ O < PINT and PI/ O can
be neglected. An appropriate relationship be-
tween PD and TJ (if PI/ O is neglected) is:
PD = K/ (TJ + 273)
(2)
Solving equations (1) and (2) for K gives:
Power, Ground, and
Noise
K = PD × (TA + 273) + PD × ΘJA
(3)
Where K is a constant pertaining to the partic-
ular package. K can be determined from
equation (2) by measuring PD (at equilibri-
um) for a known TA. Using this value of K, the
values of PD and TJ can be obtained by solv-
ing equations (1) and (2) iteratively for any
value of TA. The total thermal resistance of a
package (ΘJA) can be separated into two com-
ponents, ΘJC and ΘCA, representing the barrier
to heat flow from the semiconductor junction
to the package (case) surface (ΘJC) and from
the case to the outside ambient (ΘCA). These
terms are related by the equation:
Each DSP56156 V pin should be provided
CC
with a low-impedance path to +5 volts. Each
DSP56156 GND pin should likewise be pro-
vided with a low-impedance path to ground.
The power supply pins drive distinct groups
of logic on chip as shown in Table 26.
The V power supply should be by-
CC
passed to GND ground using at least six
0.01 – 0.1 µF bypass capacitors located ei-
ther underneath the chip’s socket or as close
as possible to the four sides of the package.
The capacitor leads and the associated
printed circuit traces connecting to chip V
CC
and GND should be kept to less than 0.5” per
ΘJA = ΘJC + ΘCA
(4)
60
DSP56156 Data Sheet
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Design Considerations
Power, Ground, and Noise
capacitor lead. The use of at least a four lay-
er board is recommended, employing two
device loads as well as parasitic capacitanc-
es due to PCB traces. Attention to proper
PCB layout and bypassing becomes espe-
cially critical in systems with higher capac-
itive loads because these loads create
inner layers as V and GND planes. All
CC
output pins on this DSP have fast rise and
fall times. Printed Circuit Board (PCB)
trace length should be minimized in order
to minimize undershoot and reflections
caused by these fast output switching
times. This recommendation particularly
applies to the address and data buses as
well as the PS/ DS, BS, RD, WR, R/ W, inter-
rupt, and HEN pins. Maximum PCB trace
lengths on the order of 6" are recommended.
Capacitance calculations should consider all
higher transient currents in the V and
CC
GND circuits.
Clock signals should not be run across
many signals and should be kept away
from analog power and ground traces as
well as any analog signals. See Figure 44 for
more details.
Table 26 Power and Ground Connections
Power
Signal
Ground
Signal
Circuitry
Pin #
Pin #
Name
Name
VCC1
VCC2
GND0
GND1
GND2
GND3
Address Bus Buffers
Data Bus Buffers
92
103
89
95
101
108
VCC3
VCC4
GND4
GND5
GND6
GND7
4
15
1
7
12
18
VCC5
VCCA
GND8
GNDA
Bus Control Buffers
Codec
36
23
38
26
VCC6
VCC7
GND9
GND10
Digital Peripherals
59
76
53
73
VCCQ0
VCCQ1
GNDQ0
GNDQ1
Internal logic
33
96
47
104
VCCS
GNDS
Phase-Locked Loop (PLL)
50
48
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Design Considerations
Power Consumption
Power Consumption
(V = 5.0 V dc ± 10%, T = -40° to +125°C, C = 50 pF + 1 TTL Load)
CC
J
L
The DC electrical characteristics of this device are shown in Table 27. Power consumption is
application dependant. The data in Table 27 is collected by running the following code using
internal memory after having programmed all pins of port B and C as input and after having
three-stated the data bus (MC = 0 in OMR) and pulled high:
move
move
move
move
clr
move
move
rep
#0,r0
#0,r3
#$100,r2
#$00ff,m0
a
x:(r0)+,a
a1,a0
#30
loop
;initial value to accumulator
mac
x0,y0,a
a,p:(r2)
#0,r3
x:(r3)+,x0
;mac on typical data
;store the mac result
move
move
jmp
loop
Table 27 DC Electrical Characteristics
Typical
Conditions
Symbol
Unit
40
50
60
MHz
MHz
MHz
Digital current with Codec and PLL disabled
ICC
ICC
91
12
112
14
133
17
mA
mA
Digital current Wait Mode with Codec
and PLL disabled
Digital current Wait Mode with Codec Enabled
and PLL disabled
ICC
92
113
134
mA
Stop mode with PLL and CLKO disabled
Digital current drawn by the PLL when active
Digital current drawn by CLKO when active
Analog current with Codec enabled
ICC
—
—
—
—
—
250
1
—
—
—
—
—
µA
mA
mA
mA
µA
ICC
ICC
3.6
12
70
ICCA
ICCA
Analog current with Codec disabled
To minimize the power dissipation, all unused digital input pins should be tied inactive to
ground or power; and all unused I/ O pins should be tied inactive through a 10K¾ resistor to
ground or power. When the codec is not used, GNDA should be connected to GND; and V
CCA
should be connected to V . Also, all codec pins should be left floating, except VREF which
CC
should still be decoupled.
62
DSP56156 Data Sheet
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Design Considerations
Host Port Considerations
by the DSP, but the possibility exists that
Host Port
Considerations
Careful synchronization is required when
reading multi-bit registers that are written by
another asynchronous system. This is a com-
mon problem when two asynchronous sys-
tems are connected. The situation exists in
the host interface. The considerations for
proper operation are discussed below.
the state of the bit could be changing dur-
ing the read operation. This is generally
not a system problem, since the bit will
be read correctly in the next pass of any
host polling routine.
However, if the host asserts HEN for
more than timing number 101 (T101),
with a minimum cycle time of timing
number 103 (T103), then these status bits
are guaranteed to be stable. Care must
be exercised when reading status bits
HF3 and HF2 as an encoded pair. If the
DSP changes HF3 and HF2 from 00 to 11,
there is a small probability that the host
could read the bits during the transition
and receive 01 or 10 instead of 11. If the
combination of HF3 and HF2 has signif-
icance, the host could read the wrong
combination. Therefore, read the bits
twice and check for consensus.
Host Programming
Considerations
1. Unsynchronized Reading of
Receive Byte Registers
When reading receive byte registers,
RXH or RXL, the host program should
use interrupts or poll the RXDF flag
which indicates that data is available.
This assures that the data in the receive
byte registers will be stable.
4. Overwriting the Host Vector
The host program should change the
Host Vector register only when the Host
Command bit (HC) is clear. This change
will guarantee that the DSP interrupt
control logic will receive a stable vector.
2. Overwriting Transmit Byte Registers
The host program should not write to the
transmit byte registers, TXH or TXL, un-
less the TXDE bit is set indicating that the
transmit byte registers are empty. This
guarantees that the transmit byte regis-
ters will transfer valid data to the HRX
register.
5. Cancelling a Pending Host Command
Exception
The host processor may elect to clear the
HC bit to cancel the host command ex-
ception request at any time before it is
recognized by the DSP. Because the host
does not know exactly when the excep-
tion will be recognized (due to exception
processing synchronization and pipeline
delays), the DSP may execute the host
command exception after the HC bit is
cleared. For these reasons, the HV bits
must not be changed at the same time
that the HC bit is cleared.
3. Synchronization of Status Bits from
DSP to Host
HC, HREQ, DMA, HF3, HF2, TRDY,
TXDE, and RXDF status bits are set or
cleared from inside the DSP and read by
the host processor (refer to DSP56156 Us-
er’s Manual, I/ O Interface section, Host/
DMA Interface Programming Model for
descriptions of these status bits). The
host can read these status bits very quick-
ly without regard to the clock rate used
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Design Considerations
DSP Programming Considerations
Bus Operation
DSP Programming
Considerations
2. Reading HF0 and HF1 as an
1. Synchronization of Status Bits
from Host to DSP
Encoded Pair
Care must be exercised when reading
status bits HF0 and HF1 as an encod-
ed pair, i.e., the four combinations 00,
01, 10, and 11 each have significance.
A very small probability exists that
the DSP will read the status bits syn-
chronized during transition. There-
fore, HF0 and HF1 should be read
twice and checked for consensus.
DMA, HF1, HF0, and HCP, HTDE,
and HRDF status bits are set or
cleared by the host processor side of
the interface. These bits are individ-
ually synchronized to the DSP clock.
(Refer to the DSP56156 User’s Manual,
I/ O Interface section, Host/ DMA In-
terface Programming Model for de-
scriptions of these status bits.)
Bus Operation
Figure 43 depicts the operation of the external memory interface with multiple wait states.
T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1
T
CLKO
BS
PS/DS
A0-A15
R/W
WR
RD
Data out
Data in
D0-D15
Figure 43 Read and Write Bus Operation (3 Wait States)
64
DSP56156 Data Sheet
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Design Considerations
Analog I/O Considerations
Analog I/O Considerations
Figure 44 describes the recommended analog I/ O and power supply configurations. The two
analog inputs are electrically identical. When one is not used, it can be left floating. When
used, an AC coupling capacitor is required. The value of the capacitor along with the input
impedance of the pin determine the cut off frequency of a high pass filter. The input imped-
ance of the MIC and AUX varies as a function of the sigma-delta (²ý) modulator master clock.
78 kΩ is a typical value at 2 MHz. An AC capacitor of 1µF defines a high pass filter pole of 2
Hz. A smaller capacitor value will move this pole higher in frequency.
MGS1-0 bits
VREF
INS bit
-6 dB
1 µF
600 Ω
MIC
VREF
V
CCA
Σ∆
modulator
0.001 µF
600 Ω
6 dB
AUX
Bias
1 µF
0.001 µF
17 dB
GNDA
R
Bias
10 KΩ
VREF
(to microphone)
(≤ ±1mA)
2.0 V ±10%
(2/5 V
+
)
CC
0.1 µF
15 µF
54 KΩ
36 KΩ
VDIV
GNDA
Š10 µF
SPKP
ð50 nF
3 POLE
2 ZERO
Low Pass
Š1 KΩ
+5 dB
SPKM
Filter (LPF)
VC3-VC0
digital V
CC
GNDA
V
CCA
digital GND
Single trace
0.01 µF
+
0.1 µF
15 µF
220 µF
+
Analog Decoupling
near DSP
GND
+5 V
External Supply
GNDA
External
GND
Single trace
Figure 44 Recommended Analog I/O Configuration
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Design Considerations
Analog I/O Considerations
Figure 45 shows three possible single-ended output configurations. Configuration (a) is highly
recommended. For configurations (b) and (c), an AC coupling capacitor is required since the
load resistor is tied to GNDA.
VREF
V
CCA
SPKP
SPKM
0 < C ð 100 nF
Š 500 Ω
SPKP
SPKM
SPKP
SPKM
0 < C ð 100 nF
Š 500 Ω
47 K¾
47 K¾
+
NC
0 < C ð 100 nF
Š 500 Ω
(c)
GNDA
47 K¾
(a)
(b)
Figure 45 Single-ended Output Configurations
Figure 46 shows a recommended layout for power and ground planes.
84
57
1
28
Analog Ground and
Power planes
Digital Ground and
Power planes
Figure 46 Ground and Power planes
66
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Design Considerations
Analog I/O Considerations
A four level board is recommended. The top layer (directly under the parts) and the bottom
layer should be interconnect layers. The two center layers should be power and ground.
Ground and power planes should be completely separated. The digital and analog power/
ground planes should not overlap. All codec pins should be over the analog planes. The ana-
log planes should not encompass any digital pins. All codec signal traces should be over the
analog planes.
Figure 47 shows that 0.1 µF bypass caps should be located as close to the pins being bypassed
as possible. The ground side of these caps should be connected as close as possible to the V
CCA
pin. The ground side of the bypass cap should be connected to the V
pin by short traces.
CCA
BIAS
AUX
MIC
28
10 kΩ
0.1 µF
0.1 µF
Š10 µF
65 µF
25 µF
Figure 47 Suggested Top Layer Bypassing
The pins with 0.1 µF bypass caps are VREF and GNDA. The largest size practical bypass
caps should also be added for each of these pins as well as for the VDIV pin; 10 µF bypass
caps should be considered a minimum value for the larger caps (65 µF on VDIV may be
used). These caps should be near the package but do not have to be right next to the pins.
The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48.
MOTOROLA
DSP56156 Data Sheet
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Design Considerations
Analog I/O Considerations
BIAS
0.25 µF
AUX
MIC IN
MIC
28
1nF
5.6 kΩ
47 kΩ
47 kΩ
47 kΩ
Copper Fill of unused board space
should be connected to the analog ground plane.
47 kΩ
SPK OUT
Figure 48 Suggested Bottom Layer Routing
The output should be used differentially if at all possible. Analog signal traces should be
shielded by running traces connected to analog ground next to them. Unused board area on
both interconnect levels should be copper filled and connected to analog ground. The copper
fill is only shown on this page for clarity and simplicity. The ADC input anti-aliasing should
be done with respect to VREF.
Figure 49 presents four options for good power supply connections.
68
DSP56156 Data Sheet
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Design Considerations
Analog I/O Considerations
10Ω
BIAS
AUX
MIC
BIAS
AUX
MIC
28
28
Voltage
Regulator
Voltage
Regulator
Second Choice — One power supply.
Two regulators, one for the digital supply, one for
the analog supply. Ground planes connected with
a 10 ¾ resistor as close as possible to the VCCA
pin on the codec.
Ideal Choice — Two separate power supplies.
Ground planes connected with a single trace as
close as possible to the VCCA pin on the codec.
10Ω
10Ω
BIAS
AUX
MIC
BIAS
AUX
MIC
28
28
Voltage
Regulator
Fourth Choice — One power supply. Ground
planes connected at source. Ground planes
connected with a 10 ¾ resistor as close as pos-
sible to the VCCA pin on the codec.
Third Choice — One power supply.
One regulator for the analog supply. Digital sup-
plies driven directly by voltage source. Ground
planes connected with a 10 ¾ resistor as close as
possible to the VCCA pin on the codec.
Figure 49 Four Possible Power Supply Connections
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DSP56156 Data Sheet
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Ordering Information
Ordering Information
Table 28 lists information for ordering parts.
Table 28 DSP56156 Ordering Information
Supply
Voltage
Frequency
(MHz)
Package Type
Pin Count
112
Order Number
Ceramic Quad Flat
Pack (CQFP)
40
60
40
60
DSP56156FE40
DSP56156FE60
DSP56156FV40
DSP56156FV60
5 V
5 V
Plastic Thin Quad
Flat Pack (TQFP)
112
70
DSP56156 Data Sheet
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Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc.
is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
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Hong Kong.
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