KMCL705KJ1CDW_技术文档

MC68HC705JK1

MC68HRC705KJ1

MC68HLC705KJ1

Data Sheet

To provide the most up-to-date information, the revision of our documents on the

World Wide Web will be the most current. Your printed copy may be an earlier

revision. To verify you have the latest information available, refer to:

http://motorola.com/semiconductors/

The following revision history table summarizes changes contained in this

document. For your convenience, the page number designators have been linked

to the appropriate location.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA

Data Sheet

3

Revision History

Revision

Level

Page

Number(s)

Date

Description

Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask

Option — changed PA7 designator to OSC1 in two places

17

18

Figure 1-5. Crystal Connections without Oscillator Internal Resistor

Mask Option — changed PA7 designator to OSC1 in two places

Figure 1-6. Ceramic Resonator Connections with Oscillator Internal

Resistor Mask Option — changed PA7 designator to OSC1 in two places

April, 2002

3.0

Figure 1-7. Ceramic Resonator Connections without Oscillator Internal

Resistor Mask Option — changed PA7 designator to OSC1 in two places

Figure 1-8. External Clock Connections — changed PA7 designator to

OSC1 in two places

19

107

Figure B-1. Crystal Connections — added OSC2 designation

Table B-3. MC68HLC705KJ1 (Low Frequency) Order Numbers —

Corrected table title

108

Reformatted to new publications standards.

Throughout

104

May, 2003

4.0

Figure A-2. Typical Internal Operating Frequency for Various V_DDat

25°C — RC Oscillator Option Only — replaced graph

Data Sheet

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Revision History MOTOROLA

Data Sheet — MC68HC705KJ1

List of Sections

Section 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Section 3. Computer Operating Properly Module (COP). . . . . . . . . . .31

Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . .35

Section 5. External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . .53

Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Section 7. Parallel I/O Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . .65

Section 8. Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Section 9. Multifunction Timer Module. . . . . . . . . . . . . . . . . . . . . . . . .81

Section 10. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .87

Section 11. Ordering Information

and Mechanical Specifications . . . . . . . . . . . . . . . . . . . .99

Appendix A. MC68HRC705KJ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Appendix B. MC68HLC705KJ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA List of Sections

Data Sheet

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List of Sections

Data Sheet

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List of Sections MOTOROLA

Data Sheet — MC68HC705KJ1

Table of Contents

Section 1. Introduction

1.1

1.2

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4

1.4.1

1.4.2

1.4.2.1

1.4.2.2

1.4.2.3

1.4.2.4

1.4.3

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

V_DDand V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

External Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IRQ/V_PP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PB2 and PB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4.4

1.4.5

1.4.6

Section 2. Memory

2.1

2.2

2.3

2.4

2.5

2.6

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Input/Output Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.7

EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.7.1

2.7.2

2.7.3

2.8

2.9

Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Section 3. Computer Operating Properly Module (COP)

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1

3.2

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3.3

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

COP Watchdog Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3.1

3.3.2

3.3.3

3.4

3.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.6

3.6.1

3.6.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Section 4. Central Processor Unit (CPU)

4.1

4.2

4.3

4.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.5

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.6

4.6.1

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.1.1

4.6.1.2

4.6.1.3

4.6.1.4

4.6.1.5

4.6.1.6

4.6.1.7

4.6.1.8

4.6.2

4.6.2.1

4.6.2.2

4.6.2.3

4.6.2.4

4.6.2.5

4.6.3

4.7

Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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Section 5. External Interrupt Module (IRQ)

5.1

5.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3

5.3.1

5.3.2

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IRQ/V_PPPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.4

5.5

IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Section 6. Low-Power Modes

6.1

6.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3

6.3.1

Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.1.1

6.3.1.2

6.3.2

6.3.2.1

6.3.2.2

6.3.3

6.3.3.1

6.3.3.2

6.3.4

6.3.4.1

6.3.4.2

6.3.5

6.3.5.1

6.3.5.2

6.4

6.5

Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Section 7. Parallel I/O Ports (PORTS)

7.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.2

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port LED Drive Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

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7.3

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.3.1

7.3.2

7.3.3

7.4

I/O Port Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Section 8. Resets and Interrupts

8.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.1

8.2.2

8.2.3

8.2.4

8.3

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.1

8.3.2

8.3.3

8.3.3.1

8.3.3.2

8.3.4

Section 9. Multifunction Timer Module

9.1

9.2

9.3

9.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.5

9.5.1

9.5.2

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.6

9.6.1

9.6.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Section 10. Electrical Specifications

10.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.2 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.4 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.5 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.6 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.7 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Data Sheet

10

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Table of Contents

MOTOROLA

Table of Contents

10.8 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.9 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 94

10.10 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Section 11. Ordering Information and Mechanical Specifications

11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11.2 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11.3 16-Pin PDIP — Case #648. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

11.4 16-Pin SOIC — Case #751G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

11.5 16-Pin Cerdip — Case #620A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Appendix A. MC68HRC705KJ1

A.1

A.2

A.3

A.4

A.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Typical Internal Operating Frequency for RC Oscillator Option . . . . . . 104

RC Oscillator Connections (No External Resistor) . . . . . . . . . . . . . . . . 105

Typical Internal Operating Frequency versus Temperature

(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

A.6

Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Appendix B. MC68HLC705KJ1

B.1

B.2

B.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 108

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Table of Contents

Data Sheet

11

Table of Contents

Data Sheet

12

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Table of Contents MOTOROLA

Data Sheet — MC68HC705KJ1

Section 1. Introduction

1.1 Features

Features on the MC68HC705KJ1 include:

•

Robust noise immunity

4.0-MHz internal operating frequency at 5.0 V

1240 Bytes of EPROM/OTPROM (electrically programmable read-only

memory/one-time programmable read-only memory), including eight bytes

for user vectors

•

64 bytes of user RAM

Peripheral modules:

–

15-stage multifunction timer

Computer operating properly (COP) watchdog

•

10 bidirectional input/output (I/O) lines, including:

–

10-mA sink capability on all I/O pins

Software programmable pulldowns on all I/O pins

Keyboard scan with selectable interrupt on four I/O pins

5.5-mA source capability on six I/O pins

•

Selectable sensitivity on external interrupt (edge- and level-sensitive or

edge-sensitive only)

On-chip oscillator with connections for:

–

Crystal

Ceramic resonator

Resistor-capacitor (RC) oscillator (MC68HRC705KJ1) with or without

external resistor

–

External clock

Low-speed (32-kHz) crystal (MC68HLC705KJ1)

•

Memory-mapped I/O registers

Fully static operation with no minimum clock speed

Power-saving stop, halt, wait, and data-retention modes

External interrupt mask bit and acknowledge bit

Illegal address reset

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Introduction

Data Sheet

13

Introduction

•

Internal steering diode and pullup resistor from RESET pin to V_DD

Selectable EPROM security⁽¹⁾

Selectable oscillator bias resistor

1.2 Structure

OSC1

OSC2

15-STAGE

DIVIDE

INTERNAL

OSCILLATOR

MULTIFUNCTION

TIMER SYSTEM

BY ³2

WATCHDOG AND

ILLEGAL ADDRESS

DETECT

CPU CONTROL

ALU

RESET

68HC05 CPU

PB3⁽¹⁾

IRQ/V_PP

ACCUMULATOR

CPU REGISTERS

INDEX REGISTER

PB2⁽¹⁾

STK PTR

0 0 0 0 0 0 0 0 1 1

PROGRAM COUNTER

CONDITION CODE

PA7

1 1 1 H I N Z C

REGISTER

PA6

PA5

PA4

STATIC RAM (SRAM) – 64 BYTES

PA3^{(1) (2)}

PA2^{(1) (2)}

PA1^{(1) (2)}

PA0^{(1) (2)}

USER EPROM – 1240 BYTES

10-mA sink capability on all I/O pins

Notes:

1. 5.5 mA source capability

2. External interrupt capability

MASK OPTION REGISTER (MOR)

Figure 1-1. Block Diagram

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading

or copying the EPROM/OTPROM difficult for unauthorized users.

Data Sheet

14

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Introduction

MOTOROLA

Introduction

Programmable Options

1.3 Programmable Options

The options in Table 1-1 are programmable in the mask option register.

Table 1-1. Programmable Options

Feature

COP watchdog timer

Option

Enabled or disabled

External interrupt triggering

Port A IRQ pin interrupts

Port pulldown resistors

Edge-sensitive only or edge- and level-sensitive

Enabled or disabled

STOP instruction mode

Crystal oscillator internal resistor

EPROM security

Stop mode or halt mode

Enabled or disabled

Short oscillator delay counter

Enabled or disabled

1.4 Pin Functions

Pin assignments are shown in Figure 1-2 with the functions described in the

following subsections.

RESET

OSC1

OSC2

PB3

IRQ/V_PP

PA0

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PA1

PA2

PA3

PA4

PA5

PA6

PB2

V_DD

V_SS

PA7

Figure 1-2. Pin Assignments

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Introduction

Data Sheet

15

Introduction

1.4.1 V_DDand V_SS

V_DDand V_SSare the power supply and ground pins. The MCU operates from a

single power supply.

Very fast signal transitions occur on the MCU pins, placing high, short-duration

current demands on the power supply. To prevent noise problems, take special

care, as Figure 1-3 shows, by placing the bypass capacitors as close as possible

to the MCU. C2 is an optional bulk current bypass capacitor for use in applications

that require the port pins to source high current levels.

V+

V_DD

C2

C1

+

C1

0.1 µF

MCU

C2

V_SS

Figure 1-3. Bypassing Layout Recommendation

1.4.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the connections for the on-chip oscillator.

The oscillator can be driven by any of the following:

1. Standard crystal (See Figure 1-4 and Figure 1-5.)

2. Ceramic resonator (See Figure 1-6 and Figure 1-7.)

3. Resistor/capacitor (RC) oscillator (Refer to Appendix A.

MC68HRC705KJ1.)

4. External clock signal as shown in (See Figure 1-8.)

5. Low speed (32 kHz) crystal connections (Refer to Appendix B.

MC68HLC705KJ1.)

The frequency, f_OSC, of the oscillator or external clock source is divided by two to

produce the internal operating frequency, f_OP

.

1.4.2.1 Crystal Oscillator

Figure 1-4 and Figure 1-5 show a typical crystal oscillator circuit for an AT-cut,

parallel resonant crystal. Follow the crystal supplier’s recommendations, as the

crystal parameters determine the external component values required to provide

reliable startup and maximum stability. The load capacitance values used in the

oscillator circuit design should include all stray layout capacitances.

Data Sheet

16

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Introduction

MOTOROLA

Introduction

Pin Functions

To minimize output distortion, mount the crystal and capacitors as close as

possible to the pins. An internal startup resistor of approximately 2 MΩ is provided

between OSC1 and OSC2 for the crystal oscillator as a programmable mask

option.

NOTE:

Use an AT-cut crystal and not an AT-strip crystal because the MCU can overdrive

an AT-strip crystal.

V_SS

MCU

C3

OSC1

XTAL

OSC2

C4

XTAL

C3

27 pF

C4

27 pF

V_DD

C2 C1

V_SS

Figure 1-4. Crystal Connections with

Oscillator Internal Resistor Mask Option

V_SS

C3

MCU

OSC1

R

XTAL

C4

R

10 MΩ

OSC2

V_DD

XTAL

C3

27 pF

C4

27 pF

C2 C1

V_SS

Figure 1-5. Crystal Connections without

Oscillator Internal Resistor Mask Option

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Introduction

Data Sheet

17

Introduction

1.4.2.2 Ceramic Resonator Oscillator

To reduce cost, use a ceramic resonator instead of the crystal. The circuits shown

in Figure 1-6 and Figure 1-7 show ceramic resonator circuits. Follow the resonator

manufacturer’s recommendations, as the resonator parameters determine the

external component values required for maximum stability and reliable starting.

The load capacitance values used in the oscillator circuit design should include all

stray capacitances.

Mount the resonator and components as close as possible to the pins for startup

stabilization and to minimize output distortion. An internal startup resistor of

approximately 2 MΩ is provided between OSC1 and OSC2 as a programmable

mask option.

V_SS

MCU

C3

OSC1

OSC2

CERAMIC

RESONATOR

C4

C3

27 pF

C4

27 pF

V_DD

C2 C1

V_SS

Figure 1-6. Ceramic Resonator Connections with

Oscillator Internal Resistor Mask Option

V_SS

C3

MCU

OSC1

R

OSC2

10 MΩ

C4

V_DD

CERAMIC

RESONATOR

C2 C1

C4

C3

27 pF

V_SS

Figure 1-7. Ceramic Resonator Connections without

Oscillator Internal Resistor Mask Option

Data Sheet

18

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Introduction

MOTOROLA

Introduction

Pin Functions

1.4.2.3 RC Oscillator

1.4.2.4 External Clock

Refer to Appendix A. MC68HRC705KJ1.

An external clock from another CMOS-compatible device can be connected to the

OSC1 input, with the OSC2 input not connected, as shown in Figure 1-8. This

configuration is possible regardless of whether the crystal/ceramic resonator or the

RC oscillator is enabled.

MCU

EXTERNAL

CMOS CLOCK

Figure 1-8. External Clock Connections

1.4.3 RESET

Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An

internal reset also pulls the RESET pin low. An internal resistor to V_DDpulls the

RESET pin high. A steering diode between the RESET and V_DDpins discharges

any RESET pin voltage when power is removed from the MCU. The RESET pin

contains an internal Schmitt trigger to improve its noise immunity as an input. Refer

to Section 8. Resets and Interrupts for more information.

1.4.4 IRQ/V_PP

The external interrupt/programming voltage pin (IRQ/V_PP) drives the

asynchronous IRQ interrupt function of the CPU. Additionally, it is used to program

the user EPROM and mask option register. (See Section 2. Memory and Section

5. External Interrupt Module (IRQ).)

The LEVEL bit in the mask option register provides negative edge-sensitive

triggering or both negative edge-sensitive and low level-sensitive triggering for the

interrupt function.

If level-sensitive triggering is selected, the IRQ/V_PPinput requires an external

resistor to V_DDfor wired-OR operation. If the IRQ/V_PPpin is not used, it must be

tied to the V_DDsupply.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Introduction

Data Sheet

19

Introduction

The IRQ/V_PPpin contains an internal Schmitt trigger as part of its input to improve

noise immunity. The voltage on this pin should not exceed V_DDexcept when the

pin is being used for programming the EPROM.

NOTE:

The mask option register can enable the PA0–PA3 pins to function as external

interrupt pins.

1.4.5 PA0–PA7

These eight input/output (I/O) lines comprise port A, a general-purpose

bidirectional I/O port. (See Section 5. External Interrupt Module (IRQ) for

information on PA0–PA3 external interrupts.)

1.4.6 PB2 and PB3

These two I/O lines comprise port B, a general-purpose bidirectional I/O port.

Data Sheet

20

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Introduction

MOTOROLA

Data Sheet — MC68HC705KJ1

Section 2. Memory

2.1 Introduction

This section provides:

•

Memory map (Figure 2-1)

Summary of the input/output registers (Figure 2-2)

Description of:

–

Random-access memory (RAM)

EPROM/OTPROM (electrically programmable read-only

memory/one-time programmable read-only memory)

–

Mask option register

Memory features include:

•

1232 Bytes of User EPROM, Plus Eight Bytes for User Vectors

64 Bytes of User RAM

2.2 Unimplemented Memory Locations

Accessing an unimplemented location can have unpredictable effects on MCU

operation. In Figure 2-2 and in register figures in this document, unimplemented

locations are shaded.

2.3 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation.

In Figure 2-2 and in register figures in this document, reserved locations are

marked with the word Reserved or with the letter R.

2.4 Memory Map

See Figure 2-1.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Memory

Data Sheet

21

Memory

PORT A DATA REGISTER (PORTA)

PORT B DATA REGISTER (PORTB)

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

↓

UNIMPLEMENTED

DATA DIRECTION REGISTER A (DDRA)

DATA DIRECTION REGISTER B (DDRB)

UNIMPLEMENTED

TIMER STATUS AND CONTROL REGISTER (TSCR)

TIMER CONTROL REGISTER (TCR)

$0000

↓

IRQ STATUS AND CONTROL REGISTER (ISCR)

I/O REGISTERS

32 BYTES

$001F

$0020

↓

UNIMPLEMENTED

$000F

$0010

$0011

$0012

↓

UNIMPLEMENTED

160 BYTES

PULLDOWN REGISTER PORT A (PDRA)

PULLDOWN REGISTER PORT B (PDRB)

$00BF

$00C0

↓

RAM

64 BYTES

UNIMPLEMENTED

EPROM PROGRAMMING REGISTER (EPROG)

UNIMPLEMENTED

$00FF

$0100

↓

$0017

$0018

$0019

↓

UNIMPLEMENTED

512 BYTES

$02FF

$0300

↓

$001E

$001F

EPROM

1232 BYTES

RESERVED

$07CF

$07D0

↓

COP REGISTER (COPR)⁽¹⁾

$07F0

$07F1

$07F2

↓

UNIMPLEMENTED

30 BYTES

MASK OPTION REGISTER (MOR)

$07ED

$07EE

$07EF

$07F0

↓

RESERVED

TEST ROM

2 BYTES

$07F7

$07F8

$07F9

$07FA

$07FB

$07FC

$07FD

$07FE

$07FF

TIMER INTERRUPT VECTOR HIGH

TIMER INTERRUPT VECTOR LOW

EXTERNAL INTERRUPT VECTOR HIGH

EXTERNAL INTERRUPT VECTOR LOW

SOFTWARE INTERRUPT VECTOR HIGH

SOFTWARE INTERRUPT VECTOR LOW

RESET VECTOR HIGH

REGISTERS AND EPROM

16 BYTES

$07FF

RESET VECTOR LOW

Note 1. Writing to bit 0 of $07F0 clears the COP watchdog.

Figure 2-1. Memory Map

Data Sheet

22

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Memory MOTOROLA

Memory

Input/Output Register Summary

2.5 Input/Output Register Summary

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Port A Data Register

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

$0000

(PORTA) Write:

See page 66.

Reset:

Read:

Unaffected by reset

0

Refer to Section 7.

Parallel I/O Ports

(PORTS)

Refer to Section 7.

Parallel I/O Ports

(PORTS)

Port B Data Register

(PORTB) Write:

See page 69.

PB3

PB2

$0001

Reset:

Unaffected by reset

$0002

$0003

Unimplemented

Read:

Data Direction Register A

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

$0004

$0005

(DDRA) Write:

See page 66.

Reset:

0

DDRB3

0

DDRB2

0

Read:

Refer to Section 7.

Parallel I/O Ports

(PORTS)

Refer to Section 7.

Parallel I/O Ports

(PORTS)

Data Direction Register B

(DDRB) Write:

See page 69.

Reset:

0

$0006

$0007

Unimplemented

Read:

TOF

RTIF

0

Timer Status and Control

TOIE

RTIE

RT1

RT0

$0008

$0009

$000A

Register (TSCR) Write:

See page 83.

Reset:

TOFR

0

RTIFR

0

1

Read:

TCR7

TCR6

TCR5

TCR4

TCR3

TCR2

TCR1

TCR0

Timer Counter Register

(TCR) Write:

See page 84.

Reset:

Read:

0

IRQE

1

0

IRQF

IRQ Status and Control

Register (ISCR) Write:

See page 57.

Reset:

R

0

IRQR

0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. I/O Register Summary (Sheet 1 of 2)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Memory

Data Sheet

23

Memory

Addr.

$000B

↓

Register Name

Unimplemented

Bit 7

6

5

4

3

2

1

Bit 0

$000F

Unimplemented

Read:

Pulldown Register Port A

(PDRA) Write: PDIA7

$0010

$0011

PDIA6

0

PDIA5

0

PDIA4

0

PDIA3

0

PDIA2

0

PDIA1

0

PDIA0

0

See page 68.

Reset:

Read:

0

Pulldown Register Port B

Refer to Section 7.

Parallel I/O Ports

(PORTS)

Refer to Section 7.

Parallel I/O Ports

(PORTS)

(PDRB) Write:

See page 71.

PDIB3

0

PDIB2

0

Reset:

0

$0012

↓

Unimplemented

$0017

Read:

Write:

Reset:

0

R

0

R

0

R

0

R

0

EPROM Programming

Register (EPROG)

See page 26.

ELAT

0

MPGM

0

EPGM

0

$0018

$0019

↓

Unimplemented

Reserved

$001E

$001F

$07F0

$07F1

R

U

R

U

R

Read:

Write:

Reset:

Read:

Write:

Reset:

COP Register (COPR)

See page 32.

COPC

0

U

SOSCD

EPMSEC OSCRES

SWAIT

PDI

PIRQ

LEVEL

COPEN

Mask Option Register (MOR)

See page 27.

Unaffected by reset

R = Reserved

= Unimplemented

U = Unaffected

Figure 2-2. I/O Register Summary (Sheet 2 of 2)

Data Sheet

24

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Memory MOTOROLA

Memory

RAM

2.6 RAM

The 64 addresses from $00C0 to $00FF serve as both the user RAM and the stack

RAM. Before processing an interrupt, the CPU uses five bytes of the stack to save

the contents of the CPU registers. During a subroutine call, the CPU uses two bytes

of the stack to store the return address. The stack pointer decrements when the

CPU stores a byte on the stack and increments when the CPU retrieves a byte from

the stack.

NOTE:

Be careful when using nested subroutines or multiple interrupt levels. The CPU

may overwrite data in the RAM during a subroutine or during the interrupt stacking

operation.

2.7 EPROM/OTPROM

An MCU with a quartz window has 1240 bytes of erasable, programmable ROM

(EPROM). The quartz window allows EPROM erasure with ultraviolet light.

NOTE:

Keep the quartz window covered with an opaque material except when erasing the

MCU. Ambient light can affect MCU operation.

In an MCU without the quartz window, the EPROM cannot be erased and serves

as 1240 bytes of one-time programmable ROM (OTPROM).

The following addresses are user EPROM/OTPROM locations:

•

$0300–$07CF

$07F8–$07FF, used for user-defined interrupt and reset vectors

The COP register (COPR) is an EPROM/OTPROM location at address $07F0.

The mask option register (MOR) is an EPROM/OTPROM location at address

$07F1.

2.7.1 EPROM/OTPROM Programming

The two ways to program the EPROM/OTPROM are:

•

Manipulating the control bits in the EPROM programming register to

program the EPROM/OTPROM on a byte-by-byte basis

•

Programming the EPROM/OTPROM with the M68HC705J In-Circuit

Simulator (M68HC705JICS) available from Motorola

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Memory

Data Sheet

25

Memory

2.7.2 EPROM Programming Register

The EPROM programming register (EPROG) contains the control bits for

programming the EPROM/OTPROM.

Address:

$0018

Bit 7

0

6

5

0

4

0

3

2

ELAT

0

1

MPGM

0

Bit 0

EPGM

0

Read:

Write:

Reset:

0

R

0

R

0

R

0

= Unimplemented

R

= Reserved

Figure 2-3. EPROM Programming Register (EPROG)

ELAT — EPROM Bus Latch Bit

This read/write bit latches the address and data buses for EPROM/OTPROM

programming. Clearing the ELAT bit automatically clears the EPGM bit.

EPROM/OTPROM data cannot be read while the ELAT bit is set. Reset clears

the ELAT bit.

1 = Address and data buses configured for EPROM/OTPROM programming

the EPROM

0 = Address and data buses configured for normal operation

MPGM — MOR Programming Bit

This read/write bit applies programming power from the IRQ/V_PPpin to the

mask option register. Reset clears MPGM.

1 = Programming voltage applied to MOR

0 = Programming voltage not applied to MOR

EPGM — EPROM Programming Bit

This read/write bit applies the voltage from the IRQ/V_PPpin to the EPROM. To

write the EPGM bit, the ELAT bit must be set already. Reset clears EPGM.

1 = Programming voltage (IRQ/V_PPpin) applied to EPROM

0 = Programming voltage (IRQ/V_PPpin) not applied to EPROM

NOTE:

Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT

and clears EPGM. ELAT must be set first by a separate instruction.

Bits [7:3] — Reserved

Take the following steps to program a byte of EPROM/OTPROM:

1. Apply the programming voltage, V_PP, to the IRQ/V_PPpin.

2. Set the ELAT bit.

3. Write to any EPROM/OTPROM address.

4. Set the EPGM bit and wait for a time, t_EPGM

5. Clear the ELAT bit.

.

Data Sheet

26

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Memory MOTOROLA

Memory

Mask Option Register

2.7.3 EPROM Erasing

The erased state of an EPROM bit is logic 0. Erase the EPROM by exposing it to

15 Ws/cm²of ultraviolet light with a wavelength of 2537 angstroms. Position the

ultraviolet light source one inch from the EPROM. Do not use a shortwave filter.

2.8 Mask Option Register

The mask option register (MOR) is an EPROM/OTPROM byte that controls the

following options:

•

COP watchdog (enable or disable)

External interrupt pin triggering (edge-sensitive only or edge- and

level-sensitive)

•

Port A external interrupts (enable or disable)

Port pulldown resistors (enable or disable)

STOP instruction (stop mode or halt mode)

Crystal oscillator internal resistor (enable or disable)

EPROM security (enable or disable)

Short oscillator delay (enable or disable)

Take the following steps to program the mask option register (MOR):

1. Apply the programming voltage, V_PP, to the IRQ/V_PPpin.

2. Write to the MOR.

3. Set the MPGM bit and wait for a time, t_MPGM

4. Clear the MPGM bit.

.

5. Reset the MCU.

Address:

$07F1

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

SOSCD

EPMSEC OSCRES

SWAIT

SWPDI

PIRQ

LEVEL

COPEN

Unaffected by reset

Figure 2-4. Mask Option Register (MOR)

SOSCD — Short Oscillator Delay Bit

The SOSCD bit controls the oscillator stabilization counter. The normal

stabilization delay following reset or exit from stop mode is 4064 t_cyc. Setting

SOSCD enables a 128 t_cycstabilization delay.

1 = Short oscillator delay enabled

0 = Short oscillator delay disabled

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Memory

Data Sheet

27

Memory

EPMSEC — EPROM Security Bit

The EPMSEC bit controls access to the EPROM/OTPROM.

1 = External access to EPROM/OTPROM denied

0 = External access to EPROM/OTPROM not denied

OSCRES — Oscillator Internal Resistor Bit

The OSCRES bit enables a 2-MΩ internal resistor in the oscillator circuit.

1 = Oscillator internal resistor enabled

0 = Oscillator internal resistor disabled

NOTE:

Program the OSCRES bit to logic 0 in devices using low-speed crystal or RC

oscillators with external resistor.

SWAIT — Stop-to-Wait Conversion Bit

The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU

interprets the STOP instruction as a WAIT instruction, and the MCU enters halt

mode. Halt mode is the same as wait mode, except that an oscillator

stabilization delay of 1 to 4064 t_cycoccurs after exiting halt mode.

1 = Halt mode enabled

0 = Halt mode not enabled

SWPDI — Software Pulldown Inhibit Bit

The SWPDI bit inhibits software control of the I/O port pulldown devices. The

SWPDI bit overrides the pulldown inhibit bits in the port pulldown inhibit

registers.

1 = Software pulldown control inhibited

0 = Software pulldown control not inhibited

PIRQ — Port A External Interrupt Bit

The PIRQ bit enables the PA0–PA3 pins to function as external interrupt pins.

1 = PA0–PA3 enabled as external interrupt pins

0 = PA0–PA3 not enabled as external interrupt pins

LEVEL —External Interrupt Sensitivity Bit

The LEVEL bit controls external interrupt triggering sensitivity.

1 = External interrupts triggered by active edges and active levels

0 = External interrupts triggered only by active edges

COPEN — COP Enable Bit

The COPEN bit enables the COP watchdog.

1 = COP watchdog enabled

0 = COP watchdog disabled

Data Sheet

28

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Memory

MOTOROLA

Memory

EPROM Programming Characteristics

2.9 EPROM Programming Characteristics

Table 2-1. EPROM Programming Characteristics⁽¹⁾

Characteristic

Symbol

Min

16.0

—¦

Typ

16.5

3.0

Max

17.0

10.0

Unit

Programming Voltage

V_PP

V

IRQ/V_PP

Programming Current

IRQ/V_PP

I_PP

mA

ms

Programming Time

Per Array Byte

MOR

t

EPGM

4

—

t

MPGM

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T = –40°C to +85°C

A

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Memory

Data Sheet

29

Memory

Data Sheet

30

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Memory MOTOROLA

Data Sheet — MC68HC705KJ1

Section 3. Computer Operating Properly Module (COP)

3.1 Introduction

The computer operating properly (COP) watchdog resets the MCU in case of

software failure. Software that is operating properly periodically services the COP

watchdog and prevents COP reset. The COP watchdog function is programmable

by the COPEN bit in the mask option register.

3.2 Features

3.3 Operation

The computer operating properly module (COP) includes these features:

•

Protection from runaway software

Wait mode and halt mode operations

Operation of the COP module is discussed here.

3.3.1 COP Watchdog Timeout

Four counter stages at the end of the timer make up the COP watchdog. The COP

resets the MCU if the timeout period occurs before the COP watchdog timer is

cleared by application software and the IRQ/V_PPpin voltage is between V_SSand

V_DD. Periodically clearing the counter starts a new timeout period and prevents

COP reset. A COP watchdog timeout indicates that the software is not executing

instructions in the correct sequence.

NOTE:

The internal clock drives the COP watchdog. Therefore, the COP watchdog cannot

generate a reset for errors that cause the internal clock to stop.

The COP watchdog depends on a power supply voltage at or above a minimum

specification and is not guaranteed to protect against brownout.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Computer Operating Properly Module (COP)

Data Sheet

31

Computer Operating Properly Module (COP)

3.3.2 COP Watchdog Timeout Period

The COP watchdog timer function is implemented by dividing the output of the

real-time interrupt circuit (RTI) by eight. The RTI select bits in the timer status and

control register control RTI output, and the selected output drives the COP

watchdog. (See timer status and control register in Section 9. Multifunction

Timer Module.)

NOTE:

The minimum COP timeout period is seven times the RTI period. The COP is

cleared asynchronously with the value in the RTI divider; hence, the COP timeout

period will vary between 7x and 8x the RTI period.

3.3.3 Clearing the COP Watchdog

To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0

(COPC) of the COP register at location $07F0 (see Figure 3-1). Clearing the COP

bit disables the COP watchdog timer regardless of the IRQ/V_PPpin voltage.

If the main program executes within the COP timeout period, the clearing routine

should be executed only once. If the main program takes longer than the COP

timeout period, the clearing routine must be executed more than once.

NOTE:

Place the clearing routine in the main program and not in an interrupt routine.

Clearing the COP watchdog in an interrupt routine might prevent COP watchdog

timeouts even though the main program is not operating properly.

3.4 Interrupts

The COP watchdog does not generate interrupts.

3.5 COP Register

The COP register (COPR) is a write-only register that returns the contents of

EPROM location $07F0 when read.

Address:

$07F0

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

COPC

0

U

= Unimplemented

U = Unaffected

Figure 3-1. COP Register (COPR)

COPC — COP Clear Bit

This write-only bit resets the COP watchdog. Reading address $07F0 returns

undefined results.

Data Sheet

32

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Computer Operating Properly Module (COP)

MOTOROLA

Computer Operating Properly Module (COP)

Low-Power Modes

3.6 Low-Power Modes

The STOP and WAIT instructions have the following effects on the COP watchdog.

3.6.1 Stop Mode

The STOP instruction clears the COP watchdog counter and disables the clock to

the COP watchdog.

NOTE:

To prevent the STOP instruction from disabling the COP watchdog, program the

stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1.

Upon exit from stop mode by external reset:

•

The counter begins counting from $0000.

The counter is cleared again after the oscillator stabilization delay and

begins counting from $0000 again.

Upon exit from stop mode by external interrupt:

•

The counter begins counting from $0000.

The counter is not cleared again after the oscillator stabilization delay and

continues counting throughout the oscillator stabilization delay.

NOTE:

Immediately after exiting stop mode by external interrupt, service the COP to

ensure a full COP timeout period.

3.6.2 Wait Mode

The WAIT instruction has no effect on the COP watchdog.

NOTE:

To prevent a COP timeout during wait mode, exit wait mode periodically to service

the COP.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Computer Operating Properly Module (COP)

Data Sheet

33

Computer Operating Properly Module (COP)

Data Sheet

34

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Computer Operating Properly Module (COP) MOTOROLA

Data Sheet — MC68HC705KJ1

Section 4. Central Processor Unit (CPU)

4.1 Introduction

The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic

unit (ALU), and five CPU registers. The CPU control unit fetches and decodes

instructions. The ALU executes the instructions. The CPU registers contain data,

addresses, and status bits that reflect the results of CPU operations.

4.2 Features

Features of the CPU include:

•

4.0-MHz bus frequency on standard part

8-bit accumulator

8-bit index register

11-bit program counter

6-bit stack pointer

Condition code register with five status flags

62 instructions

8 addressing modes

Power-saving stop, wait, halt, and data-retention modes

The programming model is shown in Figure 4-1.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

35

Central Processor Unit (CPU)

ARITHMETIC/LOGIC UNIT

CPU CONTROL UNIT

7

6

5

4

3

2

1

0

ACCUMULATOR (A)

0

INDEX REGISTER (X)

15 14 13 12 11 10

9

0

8

0

7

1

6

1

0

STACK POINTER (SP)

15 14 13 12 11 10

9

8

7

6

0

PROGRAM COUNTER (PC)

CONDITION CODE REGISTER (CCR)

7

1

6

1

5

1

4

3

I

2

1

Z

0

H

N

C

HALF-CARRY FLAG

INTERRUPT MASK

NEGATIVE FLAG

ZERO FLAG

CARRY/BORROW FLAG

Figure 4-1. Programming Model

4.3 CPU Control Unit

The CPU control unit fetches and decodes instructions during program operation.

The control unit selects the memory locations to read and write and coordinates the

timing of all CPU operations.

4.4 Arithmetic/Logic Unit

The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation

operations decoded from the instruction set by the CPU control unit. The ALU

produces the results called for by the program and sets or clears status and control

bits in the condition code register (CCR).

Data Sheet

36

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU)

MOTOROLA

Central Processor Unit (CPU)

CPU Registers

4.5 CPU Registers

The M68HC05 CPU contains five registers that control and monitor MCU

operation:

•

Accumulator

Index register

Stack pointer

Program counter

Condition code register

CPU registers are not memory mapped.

4.5.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the

accumulator to hold operands and results of ALU operations.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Unaffected by reset

Figure 4-2. Accumulator (A)

4.5.2 Index Register

In the indexed addressing modes, the CPU uses the byte in the index register to

determine the conditional address of the operand. The index register also can

serve as a temporary storage location or a counter.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Unaffected by reset

Figure 4-3. Index Register (X)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

37

Central Processor Unit (CPU)

4.5.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location

on the stack. During a reset or after the reset stack pointer instruction (RSP), the

stack pointer is preset to $00FF. The address in the stack pointer decrements after

a byte is stacked and increments before a byte is unstacked.

Bit

0

15 14 13 12 11 10

9

0

8

0

7

1

6

1

5

1

4

1

3

1

2

1

Read:

Write:

Reset:

0

1

= Unimplemented

Figure 4-4. Stack Pointer (SP)

The 10 most significant bits of the stack pointer are permanently fixed at

0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If

subroutines and interrupts use more than 64 stack locations, the stack pointer

wraps around to address $00FF and begins writing over the previously stored data.

A subroutine uses two stack locations; an interrupt uses five locations.

4.5.4 Program Counter

The program counter is a 16-bit register that contains the address of the next

instruction or operand to be fetched. The five most significant bits of the program

counter are ignored and appear as 00000.

Normally, the address in the program counter automatically increments to the next

sequential memory location every time an instruction or operand is fetched. Jump,

branch, and interrupt operations load the program counter with an address other

than that of the next sequential location.

Bit

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Reset:

0

Loaded with vector from $07FE and $07FF

Figure 4-5. Program Counter (PC)

Data Sheet

38

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

CPU Registers

4.5.5 Condition Code Register

The condition code register is an 8-bit register whose three most significant bits are

permanently fixed at 111. The condition code register contains the interrupt mask

and four flags that indicate the results of the instruction just executed.

Bit 7

1

6

1

5

1

4

H

U

3

I

2

N

U

1

Z

U

Bit 0

C

Read:

Write:

Reset:

1

U

= Unimplemented

U = Unaffected

Figure 4-6. Condition Code Register (CCR)

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of

the accumulator during an ADD or ADC operation. The half-carry flag is required

for binary-coded decimal (BCD) arithmetic operations.

I — Interrupt Mask

Setting the interrupt mask disables interrupts. If an interrupt request occurs

while the interrupt mask is logic 0, the CPU saves the CPU registers on the

stack, sets the interrupt mask, and then fetches the interrupt vector. If an

interrupt request occurs while the interrupt mask is logic 1, the interrupt request

is latched. Normally, the CPU processes the latched interrupt request as soon

as the interrupt mask is cleared again.

A return from interrupt instruction (RTI) unstacks the CPU registers, restoring

the interrupt mask to its cleared state. After any reset, the interrupt mask is set

and can be cleared only by a software instruction.

N — Negative Flag

The CPU sets the negative flag when an ALU operation produces a negative

result.

Z — Zero Flag

The CPU sets the zero flag when an ALU operation produces a result of $00.

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation produces a

carry out of bit 7 of the accumulator or when a subtraction operation requires a

borrow. Some logical operations and data manipulation instructions also clear

or set the carry/borrow flag.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

39

Central Processor Unit (CPU)

4.6 Instruction Set

The MCU instruction set has 62 instructions and uses eight addressing modes.

4.6.1 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. The

addressing modes provide eight different ways for the CPU to find the data

required to execute an instruction. The eight addressing modes are:

•

Inherent

Immediate

Direct

Extended

Indexed, no offset

Indexed, 8-bit offset

Indexed, 16-bit offset

Relative

4.6.1.1 Inherent

4.6.1.2 Immediate

4.6.1.3 Direct

Inherent instructions are those that have no operand, such as return-from-interrupt

(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU

registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent

instructions require no operand address and are one byte long.

Immediate instructions are those that contain a value to be used in an operation

with the value in the accumulator or index register. Immediate instructions require

no operand address and are two bytes long. The opcode is the first byte, and the

immediate data value is the second byte.

Direct instructions can access any of the first 256 memory locations with two bytes.

The first byte is the opcode, and the second is the low byte of the operand address.

In direct addressing, the CPU automatically uses $00 as the high byte of the

operand address.

4.6.1.4 Extended

Extended instructions use three bytes and can access any address in memory. The

first byte is the opcode; the second and third bytes are the high and low bytes of

the operand address.

Data Sheet

40

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU)

MOTOROLA

Central Processor Unit (CPU)

Instruction Set

When using the Motorola assembler, the programmer does not need to specify

whether an instruction is direct or extended. The assembler automatically selects

the shortest form of the instruction.

4.6.1.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can access data with

variable addresses within the first 256 memory locations. The index register

contains the low byte of the effective address of the operand. The CPU

automatically uses $00 as the high byte, so these instructions can address

locations $0000–$00FF.

Indexed, no offset instructions are often used to move a pointer through a table or

to hold the address of a frequently used RAM or input/output (I/O) location.

4.6.1.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access data with

variable addresses within the first 511 memory locations. The CPU adds the

unsigned byte in the index register to the unsigned byte following the opcode. The

sum is the effective address of the operand. These instructions can access

locations $0000–$01FE.

Indexed 8-bit offset instructions are useful for selecting the kth element in an

n-element table. The table can begin anywhere within the first 256 memory

locations and could extend as far as location 510 ($01FE). The k value is typically

in the index register, and the address of the beginning of the table is in the byte

following the opcode.

4.6.1.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access data with

variable addresses at any location in memory. The CPU adds the unsigned byte in

the index register to the two unsigned bytes following the opcode. The sum is the

effective address of the operand. The first byte after the opcode is the high byte of

the 16-bit offset; the second byte is the low byte of the offset.

Indexed, 16-bit offset instructions are useful for selecting the kth element in an

n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler determines the

shortest form of indexed addressing.

4.6.1.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true,

the CPU finds the effective branch destination by adding the signed byte following

the opcode to the contents of the program counter. If the branch condition is not

true, the CPU goes to the next instruction. The offset is a signed, two’s complement

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

41

Central Processor Unit (CPU)

byte that gives a branching range of –128 to +127 bytes from the address of the

next location after the branch instruction.

When using the Motorola assembler, the programmer does not need to calculate

the offset because the assembler determines the proper offset and verifies that it

is within the span of the branch.

4.6.2 Instruction Types

The MCU instructions fall into the following five categories:

•

Register/memory instructions

Read-modify-write instructions

Jump/branch instructions

Bit manipulation instructions

Control instructions

4.6.2.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations. Most of them

use two operands. One operand is in either the accumulator or the index register.

The CPU finds the other operand in memory.

Table 4-1. Register/Memory Instructions

Instruction

Add Memory Byte and Carry Bit to Accumulator

Add Memory Byte to Accumulator

AND Memory Byte with Accumulator

Bit Test Accumulator

Mnemonic

ADC

ADD

AND

BIT

Compare Accumulator

CMP

CPX

EOR

LDA

Compare Index Register with Memory Byte

EXCLUSIVE OR Accumulator with Memory Byte

Load Accumulator with Memory Byte

Load Index Register with Memory Byte

Multiply

LDX

MUL

ORA

SBC

STA

OR Accumulator with Memory Byte

Subtract Memory Byte and Carry Bit from Accumulator

Store Accumulator in Memory

Store Index Register in Memory

STX

Subtract Memory Byte from Accumulator

SUB

Data Sheet

42

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

Instruction Set

4.6.2.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and

write the modified value back to the memory location or to the register.

NOTE:

Do not use read-modify-write instructions on registers with write-only bits.

Table 4-2. Read-Modify-Write Instructions

Instruction

Arithmetic Shift Left (Same as LSL)

Arithmetic Shift Right

Mnemonic

ASL

ASR

BCLR⁽¹⁾

Bit Clear

BSET⁽¹⁾

CLR

COM

DEC

INC

Bit Set

Clear Register

Complement (One’s Complement)

Decrement

Increment

Logical Shift Left (Same as ASL)

Logical Shift Right

LSL

LSR

Negate (Two’s Complement)

Rotate Left through Carry Bit

Rotate Right through Carry Bit

Test for Negative or Zero

NEG

ROL

ROR

TST⁽²⁾

1. Unlike other read-modify-write instructions, BCLR and

BSET use only direct addressing.

2. TST is an exception to the read-modify-write sequence

because it does not write a replacement value.

4.6.2.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program

counter. The unconditional jump instruction (JMP) and the jump-to-subroutine

instruction (JSR) have no register operand. Branch instructions allow the CPU to

interrupt the normal sequence of the program counter when a test condition is met.

If the test condition is not met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state of any

readable bit in the first 256 memory locations. These 3-byte instructions use a

combination of direct addressing and relative addressing. The direct address of the

byte to be tested is in the byte following the opcode. The third byte is the signed

offset byte. The CPU finds the effective branch destination by adding the third byte

to the program counter if the specified bit tests true. The bit to be tested and its

condition (set or clear) is part of the opcode. The span of branching is from –128

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

43

Central Processor Unit (CPU)

to +127 from the address of the next location after the branch instruction. The CPU

also transfers the tested bit to the carry/borrow bit of the condition code register.

NOTE:

Do not use BRCLR or BRSET instructions on registers with write-only bits.

Table 4-3. Jump and Branch Instructions

Instruction

Branch if Carry Bit Clear

Mnemonic

BCC

BCS

Branch if Carry Bit Set

Branch if Equal

BEQ

BHCC

BHCS

BHI

Branch if Half-Carry Bit Clear

Branch if Half-Carry Bit Set

Branch if Higher

Branch if Higher or Same

Branch if IRQ Pin High

Branch if IRQ Pin Low

Branch if Lower

BHS

BIH

BIL

BLO

Branch if Lower or Same

Branch if Interrupt Mask Clear

Branch if Minus

BLS

BMC

BMI

Branch if Interrupt Mask Set

Branch if Not Equal

Branch if Plus

BMS

BNE

BPL

Branch Always

BRA

Branch if Bit Clear

BRCLR

BRN

BRSET

BSR

Branch Never

Branch if Bit Set

Branch to Subroutine

Unconditional Jump

Jump to Subroutine

JMP

JSR

Data Sheet

44

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

Instruction Set

4.6.2.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory, which

includes I/O registers and on-chip RAM locations. The CPU can also test and

branch based on the state of any bit in any of the first 256 memory locations.

Table 4-4. Bit Manipulation Instructions

Instruction

Mnemonic

BCLR

Bit Clear

Branch if Bit Clear

Branch if Bit Set

Bit Set

BRCLR

BRSET

BSET

NOTE:

Do not use bit manipulation instructions on registers with write-only bits.

4.6.2.5 Control Instructions

These instructions act on CPU registers and control CPU operation during program

execution.

Table 4-5. Control Instructions

Instruction

Mnemonic

CLC

CLI

Clear Carry Bit

Clear Interrupt Mask

No Operation

NOP

RSP

RTI

Reset Stack Pointer

Return from Interrupt

Return from Subroutine

Set Carry Bit

RTS

SEC

SEI

Set Interrupt Mask

Stop Oscillator and Enable IRQ Pin

Software Interrupt

STOP

SWI

Transfer Accumulator to Index Register

Transfer Index Register to Accumulator

Stop CPU Clock and Enable Interrupts

TAX

TXA

WAIT

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

45

Central Processor Unit (CPU)

4.6.3 Instruction Set Summary

Table 4-6. Instruction Set Summary (Sheet 1 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

ii

dd

hh ll

ee ff

ff

ADC #opr

IMM

DIR

EXT

IX2

IX1

IX

A9

B9

C9

D9

E9

F9

2

3

4

5

4

3

ADC opr

ADC opr,X

ADC ,X

Add with Carry

Add without Carry

Logical AND

A ← (A) + (M) + (C)

ꢀ —

— —

ꢀ

ii

dd

hh ll

ee ff

ff

ADD #opr

ADD opr

ADD opr,X

ADD ,X

IMM

DIR

EXT CB

IX2

IX1

IX

AB

BB

2

3

4

5

4

3

A ← (A) + (M)

ꢀ

DB

EB

FB

ii

dd

hh ll

ee ff

ff

AND #opr

AND opr

AND opr,X

AND ,X

IMM

DIR

EXT

IX2

IX1

IX

A4

B4

C4

D4

E4

F4

2

3

4

5

4

3

A ← (A) ∧ (M)

ꢀ —

dd

ASL opr

ASLA

ASLX

ASL opr,X

ASL ,X

DIR

INH

IX1

IX

38

48

58

68

78

5

3

6

5

C

0

Arithmetic Shift Left (Same as LSL)

— —

ꢀ

b7

b0

ff

dd

ASR opr

ASRA

ASRX

ASR opr,X

ASR ,X

DIR

INH

IX1

IX

37

47

57

67

77

5

3

6

5

C

Arithmetic Shift Right

ff

BCC rel

Branch if Carry Bit Clear

PC ← (PC) + 2 + rel ? C = 0

— — — — — REL

24 rr

3

DIR (b0) 11 dd

DIR (b1) 13 dd

DIR (b2) 15 dd

DIR (b3) 17 dd

DIR (b4) 19 dd

DIR (b5) 1B dd

DIR (b6) 1D dd

DIR (b7) 1F dd

5

BCLR n opr

Clear Bit n

Mn ← 0

— — — — —

BCS rel

BEQ rel

BHCC rel

BHCS rel

BHI rel

Branch if Carry Bit Set (Same as BLO)

Branch if Equal

PC ← (PC) + 2 + rel ? C = 1

PC ← (PC) + 2 + rel ? Z = 1

PC ← (PC) + 2 + rel ? H = 0

PC ← (PC) + 2 + rel ? H = 1

— — — — — REL

25 rr

27 rr

28 rr

29 rr

22 rr

24 rr

2F rr

3

Branch if Half-Carry Bit Clear

Branch if Half-Carry Bit Set

Branch if Higher

PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — — REL

PC ← (PC) + 2 + rel ? C = 0 — — — — — REL

PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL

BHS rel

BIH rel

Branch if Higher or Same

Branch if IRQ Pin High

Data Sheet

46

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

Instruction Set

Table 4-6. Instruction Set Summary (Sheet 2 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

BIL rel

Branch if IRQ Pin Low

PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL

2E rr

3

ii

dd

hh ll

ee ff

ff

BIT #opr

BIT opr

BIT opr,X

BIT ,X

IMM

DIR

EXT

IX2

IX1

IX

A5

B5

C5

D5

E5

F5

2

3

4

5

4

3

Bit Test Accumulator with Memory Byte

(A) ∧ (M)

— — ꢀ ꢀ —

BLO rel

BLS rel

BMC rel

BMI rel

BMS rel

BNE rel

BPL rel

BRA rel

Branch if Lower (Same as BCS)

Branch if Lower or Same

Branch if Interrupt Mask Clear

Branch if Minus

PC ← (PC) + 2 + rel ? C = 1

— — — — — REL

25 rr

23 rr

2C rr

2B rr

2D rr

26 rr

2A rr

20 rr

3

PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — — REL

PC ← (PC) + 2 + rel ? I = 0

PC ← (PC) + 2 + rel ? N = 1

PC ← (PC) + 2 + rel ? I = 1

PC ← (PC) + 2 + rel ? Z = 0

PC ← (PC) + 2 + rel ? N = 0

PC ← (PC) + 2 + rel ? 1 = 1

— — — — — REL

Branch if Interrupt Mask Set

Branch if Not Equal

Branch if Plus

Branch Always

DIR (b0) 01 dd rr

DIR (b1) 03 dd rr

DIR (b2) 05 dd rr

DIR (b3) 07 dd rr

DIR (b4) 09 dd rr

DIR (b5) 0B dd rr

DIR (b6) 0D dd rr

DIR (b7) 0F dd rr

5

BRCLR n opr rel Branch if Bit n Clear

PC ← (PC) + 2 + rel ? Mn = 0 — — — — ꢀ

BRN rel

Branch Never

PC ← (PC) + 2 + rel ? 1 = 0

— — — — — REL

21 rr

3

DIR (b0) 00 dd rr

DIR (b1) 02 dd rr

DIR (b2) 04 dd rr

DIR (b3) 06 dd rr

DIR (b4) 08 dd rr

DIR (b5) 0A dd rr

DIR (b6) 0C dd rr

DIR (b7) 0E dd rr

5

BRSET n opr rel Branch if Bit n Set

PC ← (PC) + 2 + rel ? Mn = 1 — — — — ꢀ

DIR (b0) 10 dd

DIR (b1) 12 dd

DIR (b2) 14 dd

DIR (b3) 16 dd

DIR (b4) 18 dd

DIR (b5) 1A dd

DIR (b6) 1C dd

DIR (b7) 1E dd

5

BSET n opr

Set Bit n

Mn ← 1

— — — — —

PC ← (PC) + 2; push (PCL)

SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

BSR rel

Branch to Subroutine

— — — — — REL AD rr

6

PC ← (PC) + rel

CLC

CLI

Clear Carry Bit

C ← 0

I ← 0

— — — — 0

— 0 — — —

INH

98

2

Clear Interrupt Mask

9A

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

47

Central Processor Unit (CPU)

Table 4-6. Instruction Set Summary (Sheet 3 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

dd

ff

CLR opr

CLRA

CLRX

CLR opr,X

CLR ,X

M ← $00

A ← $00

X ← $00

M ← $00

DIR

INH

IX1

IX

3F

4F

5F

6F

7F

5

3

6

5

Clear Byte

— — 0 1 —

ii

dd

hh ll

ee ff

ff

CMP #opr

CMP opr

CMP opr,X

CMP ,X

IMM

DIR

EXT

IX2

IX1

IX

A1

B1

C1

D1

E1

F1

2

3

4

5

4

3

Compare Accumulator with Memory Byte

Complement Byte (One’s Complement)

Compare Index Register with Memory Byte

Decrement Byte

(A) – (M)

— —

ꢀ

1

ꢀ

dd

ff

COM opr

COMA

COMX

COM opr,X

COM ,X

M ← (M) = $FF – (M)

A ← (A) = $FF – (A)

X ← (X) = $FF – (X)

M ← (M) = $FF – (M)

DIR

INH

IX1

IX

33

43

53

63

73

5

3

6

5

ii

dd

hh ll

ee ff

ff

CPX #opr

CPX opr

CPX opr,X

CPX ,X

IMM

DIR

EXT

IX2

IX1

IX

A3

B3

C3

D3

E3

F3

2

3

4

5

4

3

(X) – (M)

dd

ff

DEC opr

DECA

DECX

DEC opr,X

DEC ,X

M ← (M) – 1

A ← (A) – 1

X ← (X) – 1

M ← (M) – 1

DIR

INH

IX1

IX

3A

4A

5A

6A

7A

5

3

6

5

ꢀ —

ii

dd

hh ll

ee ff

ff

EOR #opr

EOR opr

EOR opr,X

EOR ,X

IMM

DIR

EXT

IX2

IX1

IX

A8

B8

C8

D8

E8

F8

2

3

4

5

4

3

EXCLUSIVE OR Accumulator with Memory

Byte

A ← (A) ⊕ (M)

dd

ff

INC opr

INCA

INCX

INC opr,X

INC ,X

M ← (M) + 1

A ← (A) + 1

X ← (X) + 1

M ← (M) + 1

DIR

INH

IX1

IX

3C

4C

5C

6C

7C

5

3

6

5

Increment Byte

dd

hh ll

ee ff

ff

JMP opr

JMP opr,X

JMP ,X

DIR

EXT CC

IX2

IX1

IX

BC

2

3

4

3

2

Unconditional Jump

PC ← Jump Address

— — — — —

DC

EC

FC

Data Sheet

48

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

Instruction Set

Table 4-6. Instruction Set Summary (Sheet 4 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

dd

hh ll

ee ff

ff

JSR opr

DIR

EXT CD

IX2

IX1

IX

BD

5

6

7

6

5

PC ← (PC) + n (n = 1, 2, or 3)

Push (PCL); SP ← (SP) – 1

Push (PCH); SP ← (SP) – 1

PC ← Effective Address

JSR opr

JSR opr,X

JSR ,X

Jump to Subroutine

— — — — —

DD

ED

FD

ii

dd

hh ll

ee ff

ff

LDA #opr

LDA opr

LDA opr,X

LDA ,X

IMM

DIR

EXT

IX2

IX1

IX

A6

B6

C6

D6

E6

F6

2

3

4

5

4

3

Load Accumulator with Memory Byte

A ← (M)

— —

ꢀ

ꢀ —

ii

dd

hh ll

ee ff

ff

LDX #opr

LDX opr

LDX opr,X

LDX ,X

IMM

DIR

EXT CE

IX2

IX1

IX

AE

BE

2

3

4

5

4

3

Load Index Register with Memory Byte

Logical Shift Left (Same as ASL)

X ← (M)

— —

ꢀ —

DE

EE

FE

dd

LSL opr

LSLA

LSLX

LSL opr,X

LSL ,X

DIR

INH

IX1

IX

38

48

58

68

78

5

3

6

5

C

0

— — ꢀ

ꢀ

b7

b0

ff

dd

LSR opr

LSRA

LSRX

LSR opr,X

LSR ,X

DIR

INH

IX1

IX

34

44

54

64

74

5

3

6

5

0

C

Logical Shift Right

Unsigned Multiply

— — 0

b7

b0

ff

1

MUL

X : A ← (X) × (A)

0 — — — 0

INH

42

dd

ff

NEG opr

NEGA

NEGX

NEG opr,X

NEG ,X

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X)

M ← –(M) = $00 – (M)

DIR

INH

IX1

IX

30

40

50

60

70

5

3

6

5

Negate Byte (Two’s Complement)

No Operation

— — ꢀ ꢀ ꢀ

NOP

— — — — —

INH

9D

2

ii

dd

hh ll

ee ff

ff

ORA #opr

ORA opr

ORA opr,X

ORA ,X

IMM

DIR

EXT CA

IX2

IX1

IX

AA

BA

2

3

4

5

4

3

Logical OR Accumulator with Memory

Rotate Byte Left through Carry Bit

A ← (A) ∨ (M)

— —

ꢀ

ꢀ —

DA

EA

FA

dd

ff

ROL opr

ROLA

ROLX

ROL opr,X

ROL ,X

DIR

INH

IX1

IX

39

49

59

69

79

5

3

6

5

C

— —

ꢀ ꢀ

b7

b0

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

49

Central Processor Unit (CPU)

Table 4-6. Instruction Set Summary (Sheet 5 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

dd

ff

ROR opr

RORA

RORX

ROR opr,X

ROR ,X

DIR

INH

IX1

IX

36

46

56

66

76

5

3

6

5

C

Rotate Byte Right through Carry Bit

— — ꢀ ꢀ ꢀ

b7

b0

RSP

Reset Stack Pointer

Return from Interrupt

SP ← $00FF

— — — — —

INH

9C

2

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A)

SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

RTI

ꢀ

ꢀ ꢀ ꢀ ꢀ

INH

80

9

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

RTS

Return from Subroutine

— — — — —

INH

81

6

ii

dd

hh ll

ee ff

ff

SBC #opr

SBC opr

SBC opr,X

SBC ,X

IMM

DIR

EXT

IX2

IX1

IX

A2

B2

C2

D2

E2

F2

2

3

4

5

4

3

Subtract Memory Byte and Carry Bit from

Accumulator

A ← (A) – (M) – (C)

— — ꢀ ꢀ ꢀ

SEC

SEI

Set Carry Bit

C ← 1

I ← 1

— — — — 1

— 1 — — —

INH

99

2

Set Interrupt Mask

9B

dd

hh ll

ee ff

ff

STA opr

STA opr,X

STA ,X

DIR

EXT

IX2

IX1

IX

B7

C7

D7

E7

F7

4

5

6

5

4

Store Accumulator in Memory

Stop Oscillator and Enable IRQ Pin

Store Index Register In Memory

M ← (A)

— — ꢀ ꢀ —

STOP

— 0 — — —

INH

8E

2

dd

hh ll

ee ff

ff

STX opr

STX opr,X

STX ,X

DIR

EXT

IX2

IX1

IX

BF

CF

DF

EF

FF

4

5

6

5

4

M ← (X)

— —

ꢀ

ꢀ —

ii

dd

hh ll

ee ff

ff

SUB #opr

SUB opr

SUB opr,X

SUB ,X

IMM

DIR

EXT

IX2

IX1

IX

A0

B0

C0

D0

E0

F0

2

3

4

5

4

3

Subtract Memory Byte from Accumulator

A ← (A) – (M)

ꢀ ꢀ

PC ← (PC) + 1; Push (PCL)

SP ← (SP) – 1; Push (PCH)

SP ← (SP) – 1; Push (X)

SP ← (SP) – 1; Push (A)

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

1

0

SWI

Software Interrupt

— 1 — — —

INH

83

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

Data Sheet

50

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Central Processor Unit (CPU) MOTOROLA

Central Processor Unit (CPU)

Opcode Map

Table 4-6. Instruction Set Summary (Sheet 6 of 6)

Effect

Source

Form

on CCR

Operation

Description

H I N Z C

TAX

Transfer Accumulator to Index Register

X ← (A)

— — — — —

INH

97

2

dd

ff

TST opr

TSTA

TSTX

TST opr,X

TST ,X

DIR

INH

IX1

IX

3D

4D

5D

6D

7D

4

3

5

4

Test Memory Byte for Negative or Zero

(M) – $00

— — ꢀ ꢀ —

TXA

Transfer Index Register to Accumulator

Stop CPU Clock and Enable Interrupts

A ← (X)

— — — — —

— 0 — — —

INH

9F

8F

2

WAIT

A

C

Accumulator

Carry/borrow flag

opr

PC

Operand (one or two bytes)

Program counter

CCR Condition code register

PCH Program counter high byte

PCL Program counter low byte

REL Relative addressing mode

dd

Direct address of operand

dd rr

DIR

ee ff

EXT

ff

Direct address of operand and relative offset of branch instruction

Direct addressing mode

High and low bytes of offset in indexed, 16-bit offset addressing

Extended addressing mode

Offset byte in indexed, 8-bit offset addressing

Half-carry flag

rel

rr

SP

X

Relative program counter offset byte

Stack pointer

Index register

H

Z

Zero flag

hh ll

I

High and low bytes of operand address in extended addressing

Interrupt mask

#

∧

Immediate value

Logical AND

ii

Immediate operand byte

∨

Logical OR

IMM

INH

IX

IX1

IX2

M

Immediate addressing mode

Inherent addressing mode

Indexed, no offset addressing mode

Indexed, 8-bit offset addressing mode

Indexed, 16-bit offset addressing mode

Memory location

⊕

( )

–( )

←

?

Logical EXCLUSIVE OR

Contents of

Negation (two’s complement)

Loaded with

If

:

ꢀ

Concatenated with

Set or cleared

N

Negative flag

n

Any bit

—

Not affected

4.7 Opcode Map

See Table 4-7.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Central Processor Unit (CPU)

Data Sheet

51

Data Sheet — MC68HC705KJ1

Section 5. External Interrupt Module (IRQ)

5.1 Introduction

The external interrupt (IRQ) module provides asynchronous external interrupts to

the CPU. The following sources can generate external interrupts:

•

IRQ/V_PPpin

PA0–PA3 pins

5.2 Features

The external interrupt module (IRQ) includes these features:

•

Dedicated external interrupt pin (IRQ/V_PP)

Selectable interrupt on four input/output (I/O) pins (PA0–PA3)

Programmable edge-only or edge- and level-interrupt sensitivity

5.3 Operation

The interrupt request/programming voltage pin (IRQ/V_PP) and port A pins 0–3

(PA0–PA3) provide external interrupts. The PIRQ bit in the mask option register

(MOR) enables PA0–PA3 as IRQ interrupt sources, which are combined into a

single OR’ing function to be latched by the IRQ latch. Figure 5-1 shows the

structure of the IRQ module.

After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch

is set, the CPU then tests the I bit in the condition code register and the IRQE bit

in the IRQ status and control register. If the I bit is clear and the IRQE bit is set, the

CPU then begins the interrupt sequence. This interrupt is serviced by the interrupt

service routine located at $07FA and $07FB.

The CPU clears the IRQ latch while it fetches the interrupt vector, so that another

external interrupt request can be latched during the interrupt service routine. As

soon as the I bit is cleared during the return from interrupt, the CPU can recognize

the new interrupt request. Figure 5-3 shows the sequence of events caused by an

interrupt.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA External Interrupt Module (IRQ)

Data Sheet

53

External Interrupt Module (IRQ)

TO BIH & BIL

INSTRUCTION

PROCESSING

IRQ

LEVEL-SENSITIVE TRIGGER

(MOR LEVEL BIT)

IRQF

V

DD

EXTERNAL

INTERRUPT

REQUEST

IRQ

LATCH

D

Q

PA3

PA2

PA1

PA0

CK

IRQE

CLR

PIRQ

(MOR)

RESET

IRQ VECTOR FETCH

IRQR

Figure 5-1. IRQ Module Block Diagram

Addr.

Register Name

Bit 7

IRQE

1

6

5

4

0

3

2

1

0

Bit 0

Read:

0

IRQF

0

IRQ Status and Control

$000A

Register (ISCR) Write:

See page 57.

Reset:

R

0

IRQR

0

= Unimplemented

R

= Reserved

Figure 5-2. IRQ Module I/O Register Summary

5.3.1 IRQ/V_PPPin

An interrupt signal on the IRQ/V_PPpin latches an external interrupt request. The

LEVEL bit in the mask option register provides negative edge-sensitive triggering

or both negative edge-sensitive and low level-sensitive triggering for the interrupt

function.

If edge- and level-sensitive triggering is selected, a falling edge or a low level on the

IRQ/V_PPpin latches an external interrupt request. Edge- and level-sensitive

triggering allows the use of multiple wired-OR external interrupt sources. An

external interrupt request is latched as long as any source is holding the IRQ/V_PP

pin low.

If level-sensitive triggering is selected, the IRQ/V_PPinput requires an external

resistor to V_DDfor wired-OR operation. If the IRQ/V_PPpin is not used, it must be

tied to the V_DDsupply.

Data Sheet

54

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

External Interrupt Module (IRQ)

MOTOROLA

External Interrupt Module (IRQ)

Operation

FROM RESET

YES

I BIT SET?

NO

YES

EXTERNAL

INTERRUPT?

CLEAR IRQ LATCH.

NO

TIMER

INTERRUPT?

YES

STACK PCL, PCH, X, A, CCR.

SET I BIT.

LOAD PC WITH INTERRUPT VECTOR.

NO

FETCH NEXT

INSTRUCTION.

SWI

INSTRUCTION?

YES

NO

RTI

INSTRUCTION?

YES

UNSTACK CCR, A, X, PCH, PCL.

EXECUTE INSTRUCTION.

NO

Figure 5-3. Interrupt Flowchart

If edge-sensitive-only triggering is selected, a falling edge on the IRQ/V_PPpin

latches an external interrupt request. A subsequent external interrupt request can

be latched only after the voltage level on the IRQ/V_PPpin returns to logic 1 and then

falls again to logic 0.

The IRQ/V_PPpin contains an internal Schmitt trigger as part of its input to improve

noise immunity. The voltage on this pin can affect the mode of operation and

should not exceed V_DD

.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA External Interrupt Module (IRQ)

Data Sheet

55

External Interrupt Module (IRQ)

5.3.2 Optional External Interrupts

The inputs for the lower four bits of port A (PA0–PA3) can be connected to the IRQ

pin input of the CPU if enabled by the PIRQ bit in the mask option register. This

capability allows keyboard scan applications where the transitions or levels on the

I/O pins will behave the same as the IRQ/V_PPpin except for the inverted phase

(logic 1, rising edge). The active state of the IRQ/V_PPpin is a logic 0 (falling edge).

The PA0–PA3 pins are selected as a group to function as IRQ interrupts and are

enabled by the IRQE bit in the IRQ status and control register. The PA0–PA3 pins

can be positive-edge triggered only or positive-edge and high-level triggered.

If edge- and level-sensitive triggering is selected, a rising edge or a high level on a

PA0–PA3 pin latches an external interrupt request. Edge- and level-sensitive

triggering allows the use of multiple wired-OR external interrupt sources. As long

as any source is holding a PA0–PA3 pin high, an external interrupt request is

latched, and the CPU continues to execute the interrupt service routine.

If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3 pin

latches an external interrupt request. A subsequent external interrupt request can

be latched only after the voltage level of the previous interrupt signal returns to logic

0 and then rises again to logic 1.

NOTE:

The BIH and BIL instructions apply only to the level on the IRQ/V_PPpin itself and

not to the output of the logic OR function with the PA0–PA3 pins. The state of the

individual port A pins can be checked by reading the appropriate port A pins as

inputs.

Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether these pins

are configured as inputs or outputs.

The IRQ pin has an internal Schmitt trigger. The optional external interrupts

(PA0–PA3) do not have internal Schmitt triggers.

The interrupt mask bit (I) in the condition code register (CCR) disables all maskable

interrupt requests, including external interrupt requests.

Data Sheet

56

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

External Interrupt Module (IRQ)

MOTOROLA

External Interrupt Module (IRQ)

IRQ Status and Control Register

5.4 IRQ Status and Control Register

The IRQ status and control register (ISCR) controls and monitors operation of the

IRQ module. All unused bits in the ISCR read as logic 0s. The IRQF bit is cleared

and the IRQE bit is set by reset.

Address:

$000A

Bit 7

6

0

5

0

4

0

3

2

0

1

0

Bit 0

0

Read:

Write:

Reset:

IRQF

IRQE

1

R

0

IRQR

0

= Unimplemented

R

= Reserved

Figure 5-4. IRQ Status and Control Register (ISCR)

IRQR — Interrupt Request Reset Bit

This write-only bit clears the external interrupt request flag.

1 = Clears external interrupt and IRQF bit

0 = No effect on external interrupt and IRQF bit

IRQF — External Interrupt Request Flag

The external interrupt request flag is a clearable, read-only bit that is set when

an external interrupt request is pending. Reset clears the IRQF bit.

1 = External interrupt request pending

0 = No external interrupt request pending

IRQE — External Interrupt Request Enable Bit

This read/write bit enables external interrupts. Reset sets the IRQE bit.

1 = External interrupt requests enabled

0 = External interrupt requests disabled

The STOP and WAIT instructions set the IRQE bit so that an external interrupt can

bring the MCU out of these low-power modes. In addition, reset sets the I bit which

masks all interrupt sources.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA External Interrupt Module (IRQ)

Data Sheet

57

External Interrupt Module (IRQ)

5.5 Timing

t_ILIL

t_ILIH

IRQ/V_PPPIN

t_ILIH

IRQ₁

.

IRQ_n

IRQ (INTERNAL)

Figure 5-5. External Interrupt Timing

Table 5-1. External Interrupt Timing (V_DD= 5.0 Vdc)⁽¹⁾

Characteristic

Symbol

Min

Max

Unit

IRQ Interrupt Pulse Width Low

(Edge-Triggered)

(2)

t_ILIH

1.5

—

t_cyc

IRQ Interrupt Pulse Width

(Edge- and Level-Triggered)

Note⁽³⁾

—

t_ILIH

t_ILIL

t_ILIH

1.5

PA0–PA3 Interrupt Pulse Width High

(Edge-Triggered)

PA0–PA3 Interrupt Pulse Width High (Edge-

and Level-Triggered)

Note⁽³⁾

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to + 85°C, unless otherwise noted.

2. t_cyc= 1/f_OP; f_OP= f_OSC/2.

3. The minimum t_ILILshould not be less than the number of interrupt service routine cycles plus

19 t_cyc

.

Table 5-2. External Interrupt Timing (V_DD= 3.3 Vdc)⁽¹⁾

Characteristic

Symbol

Min

Max

Unit

IRQ Interrupt Pulse Width Low

(Edge-Triggered)

(2)

t_ILIH

1.5

—

t_cyc

IRQ Interrupt Pulse Width

(Edge- and Level-Triggered)

Note⁽³⁾

—

t_ILIH

t_ILIL

t_ILIH

1.5

PA0–PA3 Interrupt Pulse Width High

(Edge-Triggered)

PA0–PA3 Interrupt Pulse Width High (Edge-

and Level-Triggered)

Note⁽³⁾

1. V_DD= 3.3 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to + 85°C, unless otherwise noted.

2. t_cyc= 1/f_OP; f_OP= f_OSC/2.

3. The minimum t_ILILshould not be less than the number of interrupt service routine cycles plus

19 t_cyc

.

Data Sheet

58

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

External Interrupt Module (IRQ) MOTOROLA

Data Sheet — MC68HC705KJ1

Section 6. Low-Power Modes

6.1 Introduction

The MCU can enter the following low-power standby modes:

•

Stop mode — The STOP instruction puts the MCU in its lowest

power-consumption mode.

Wait mode — The WAIT instruction puts the MCU in an intermediate

power-consumption mode.

Halt mode — Halt mode is identical to wait mode, except that an oscillator

stabilization delay of 1 to 4064 internal clock cycles occurs when the MCU

exits halt mode. The stop-to-wait conversion bit, SWAIT, in the mask option

register, enables halt mode.

Enabling halt mode prevents the computer operating properly (COP)

watchdog from being inadvertently turned off by a STOP instruction.

•

Data-retention mode — In data-retention mode, the MCU retains RAM

contents and CPU register contents at V_DDvoltages as low as 2.0 Vdc. The

data-retention feature allows the MCU to remain in a low

power-consumption state during which it retains data, but the CPU cannot

execute instructions.

6.2 Exiting Stop and Wait Modes

The following events bring the MCU out of stop mode and load the program counter

with the reset vector or with an interrupt vector:

Exiting Stop Mode

•

External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU

clock, and loads the program counter with the contents of locations $07FE

and $07FF.

External interrupt — A high-to-low transition on the IRQ/V_PPpin or a

low-to-high transition on an enabled port A external interrupt pin starts the

CPU clock and loads the program counter with the contents of locations

$07FA and $07FB.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Low-Power Modes

Data Sheet

59

Low-Power Modes

Exiting Wait Mode

•

External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU

clock, and loads the program counter with the contents of locations $07FE

and $07FF.

•

External interrupt — A high-to-low transition on the IRQ/V_PPpin or a

low-to-high transition on an enabled port A external interrupt pin starts the

CPU clock and loads the program counter with the contents of locations

$07FA and $07FB.

•

COP watchdog reset — A timeout of the COP watchdog resets the MCU,

starts the CPU clock, and loads the program counter with the contents of

locations $07FE and $07FF. Software can enable timer interrupts so that the

MCU periodically can exit wait mode to reset the COP watchdog.

Timer interrupt — Real-time interrupt requests and timer overflow interrupt

requests start the MCU clock and load the program counter with the

contents of locations $07F8 and $07F9.

6.3 Effects of Stop and Wait Modes

The STOP and WAIT instructions have the following effects on MCU modules.

6.3.1 Clock Generation

Effects of STOP and WAIT on clock generation are discussed here.

6.3.1.1 STOP

The STOP instruction disables the internal oscillator, stopping the CPU clock and

all peripheral clocks.

After exiting stop mode, the CPU clock and all enabled peripheral clocks begin

running after the oscillator stabilization delay.

NOTE:

The oscillator stabilization delay holds the MCU in reset for the first 4064 internal

clock cycles.

6.3.1.2 WAIT

The WAIT instruction disables the CPU clock.

After exiting wait mode, the CPU clock and all enabled peripheral clocks

immediately begin running.

Data Sheet

60

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Low-Power Modes

MOTOROLA

Low-Power Modes

Effects of Stop and Wait Modes

6.3.2 CPU

Effects of STOP and WAIT on the CPU are discussed here.

6.3.2.1 STOP

The STOP instruction:

•

Clears the interrupt mask (I bit) in the condition code register, enabling

external interrupts

•

Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator

stabilization delay.

After exit from stop mode by external interrupt, the I bit remains clear.

After exit from stop mode by reset, the I bit is set.

6.3.2.2 WAIT

The WAIT instruction:

•

Clears the interrupt mask (I bit) in the condition code register, enabling

interrupts

•

Disables the CPU clock

After exit from wait mode by interrupt, the I bit remains clear.

After exit from wait mode by reset, the I bit is set.

6.3.3 COP Watchdog

Effects of STOP and WAIT on the COP watchdog are discussed here.

6.3.3.1 STOP

The STOP instruction:

•

Clears the COP watchdog counter

Disables the COP watchdog clock

NOTE:

To prevent the STOP instruction from disabling the COP watchdog, program the

stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1.

After exit from stop mode by external interrupt, the COP watchdog counter

immediately begins counting from $0000 and continues counting throughout the

oscillator stabilization delay.

Immediately after exiting stop mode by external interrupt, service the COP to

ensure a full COP timeout period.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Low-Power Modes

Data Sheet

61

Low-Power Modes

After exit from stop mode by reset:

•

The COP watchdog counter immediately begins counting from $0000.

The COP watchdog counter is cleared at the end of the oscillator

stabilization delay and begins counting from $0000 again.

6.3.3.2 WAIT

The WAIT instruction has no effect on the COP watchdog.

NOTE:

To prevent a COP timeout during wait mode, exit wait mode periodically to service

the COP.

6.3.4 Timer

Effects of STOP and WAIT on the timer are discussed here.

6.3.4.1 STOP

The STOP instruction:

•

Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and control

register, disabling timer interrupt requests and removing any pending timer

interrupt requests

Disables the clock to the timer

After exiting stop mode by external interrupt, the timer immediately resumes

counting from the last value before the STOP instruction and continues counting

throughout the oscillator stabilization delay.

After exiting stop mode by reset and after the oscillator stabilization delay, the timer

resumes operation from its reset state.

6.3.4.2 WAIT

The WAIT instruction has no effect on the timer.

6.3.5 EPROM/OTPROM

Effects of STOP and WAIT on the EPROM/OTPROM are discussed here.

6.3.5.1 STOP

The STOP instruction during EPROM programming clears the EPGM bit in the

EPROM programming register, removing the programming voltage from the

EPROM.

Data Sheet

62

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Low-Power Modes

MOTOROLA

Low-Power Modes

Data-Retention Mode

6.3.5.2 WAIT

The WAIT instruction has no effect on EPROM/OTPROM operation.

6.4 Data-Retention Mode

In data-retention mode, the MCU retains RAM contents and CPU register contents

at V_DDvoltages as low as 2.0 Vdc. The data-retention feature allows the MCU to

remain in a low power-consumption state during which it retains data, but the CPU

cannot execute instructions.

To put the MCU in data-retention mode:

1. Drive the RESET pin to logic 0.

2. Lower the V_DDvoltage. The RESET pin must remain low continuously

during data-retention mode.

To take the MCU out of data-retention mode:

1. Return V_DDto normal operating voltage.

2. Return the RESET pin to logic 1.

6.5 Timing

OSC

(NOTE 1)

t_RL

RESET

t_ILIH

IRQ/V_PP

(NOTE 2)

OSCILLATOR STABILIZATION DELAY⁽⁵⁾

IRQ/V_PP

(NOTE 3)

INTERNAL

CLOCK

INTERNAL

$07FE

(NOTE 4)

ADDRESS

BUS

$07FE

$07FF

Notes:

RESET OR INTERRUPT

VECTOR FETCH

1. Internal clocking from OSC1 pin

2. Edge-triggered external interrupt mask option

3. Edge- and level-triggered external interrupt mask option

4. Reset vector shown as example

5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR

Figure 6-1. Stop Mode Recovery Timing

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Low-Power Modes

Data Sheet

63

Low-Power Modes

STOP

SWAIT

BIT SET?

YES

HALT

WAIT

NO

CLEAR I BIT IN CCR.

SET IRQE BIT IN ISCR.

CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR.

TURN OFF INTERNAL OSCILLATOR.

CLEAR I BIT IN CCR.

SET IRQE BIT IN ISCR.

TURN OFF CPU CLOCK.

TIMER CLOCK ACTIVE.

CLEAR I BIT IN CCR.

SET IRQE BIT IN ISCR.

TURN OFF CPU CLOCK.

TIMER CLOCK ACTIVE.

YES

EXTERNAL

RESET?

EXTERNAL

RESET?

YES

EXTERNAL

RESET?

NO

YES

EXTERNAL

INTERRUPT?

EXTERNAL

INTERRUPT?

YES

EXTERNAL

INTERRUPT?

NO

TIMER

INTERRUPT?

TIMER

INTERRUPT?

TURN ON INTERNAL OSCILLATOR.

RESET STABILIZATION TIMER.

NO

COP

RESET?

COP

RESET?

END OF

YES

STABILIZATION

DELAY?

NO

TURN ON CPU CLOCK.

1. LOAD PC WITH RESET VECTOR

OR

2. SERVICE INTERRUPT.

a. SAVE CPU REGISTERS ON STACK.

b. SET I BIT IN CCR.

c. LOAD PC WITH INTERRUPT VECTOR.

Figure 6-2. STOP/HALT/WAIT Flowchart

Data Sheet

64

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Low-Power Modes MOTOROLA

Data Sheet — MC68HC705KJ1

Section 7. Parallel I/O Ports (PORTS)

7.1 Introduction

Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port.

All the bidirectional port pins are programmable as inputs or outputs.

NOTE:

Connect any unused I/O pins to an appropriate logic level, either V_DDor V_SS.

Although the I/O ports do not require termination for proper operation, termination

reduces excess current consumption and the possibility of electrostatic damage.

Addr.

Register Name:

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Port A Data Register

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

$0000

(PORTA) Write:

See page 66.

Reset:

Read:

Unaffected by reset

0

Port B Data Register

See Note

PB3

PB2

See Note

$0001

$0004

$0005

$0010

$0011

Note:

(PORTB) Write:

See page 69.

Reset:

Read:

Unaffected by reset

Data Direction Register A

DDRA7

DDRA6

DDRA5

0

DDRA4

0

DDRA3

DDRA2

DDRA1

0

DDRA0

0

(DDRA) Write:

See page 66.

Reset:

Read:

0

DDRB3

0

DDRB2

0

Data Direction Register B

See Note

(DDRB) Write:

See page 69.

Reset:

Read:

0

Port A Pulldown Register

(PDRA) Write:

PDIA7

0

PDIA6

0

PDIA5

0

PDIA4

0

PDIA3

0

PDIA2

0

PDIA1

0

PDIA0

0

See page 68.

Reset:

Read:

Port B Pulldown Register

(PDRB) Write:

See page 71.

See Note

PDIB3

0

PDIB2

0

See Note

Reset:

0

= Unimplemented

PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not

available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly

terminating them.

Figure 7-1. Parallel I/O Port Register Summary

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Parallel I/O Ports (PORTS)

Data Sheet

65

Parallel I/O Ports (PORTS)

7.2 Port A

Port A is an 8-bit bidirectional port.

7.2.1 Port A Data Register

The port A data register contains a latch for each port A pin.

Address:

$0000

Bit 7

6

5

4

3

2

1

Bit 0

PA0

Read:

Write:

Reset:

PA7

PA6

PA5

PA4

PA3

PA2

PA1

Unaffected by reset

Figure 7-2. Port A Data Register (PORTA)

PA[7:0] — Port A Data Bits

These read/write bits are software programmable. Data direction of each port A

pin is under the control of the corresponding bit in data direction register A.

Reset has no effect on port A data.

7.2.2 Data Direction Register A

Data direction register A determines whether each port A pin is an input or an

output.

Address:

$0004

Bit 7

6

DDRA6

0

5

DDRA5

0

4

DDRA4

0

3

DDRA3

0

2

DDRA2

0

1

DDRA1

0

Bit 0

DDRA0

0

Read:

Write:

Reset:

DDRA7

0

Figure 7-3. Data Direction Register A (DDRA)

DDRA[7:0] — Data Direction Register A Bits

These read/write bits control port A data direction. Reset clears DDRA[7:0],

configuring all port A pins as inputs.

1 = Corresponding port A pin configured as output

0 = Corresponding port A pin configured as input

NOTE:

Avoid glitches on port A pins by writing to the port A data register before changing

data direction register A bits from 0 to 1.

Figure 7-4 shows the I/O logic of port A.

Data Sheet

66

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Parallel I/O Ports (PORTS)

MOTOROLA

Parallel I/O Ports (PORTS)

Port A

READ DDRA

WRITE DDRA

WRITE PORTA

DDRAx

PAx

10-mA SINK CAPABILITY

(PINS PA4–PA7 ONLY)

PAx

(PA0–PA3 TO

IRQ MODULE)

READ PORTA

WRITE PDRA

100-µA

PULLDOWN

PDRAx

RESET

SWPDI

Figure 7-4. Port A I/O Circuitry

Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port

A pin; a logic 0 disables the output buffer.

When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch.

When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the

pin. The data latch can always be written, regardless of the state of its data

direction bit. Table 7-1 summarizes the operation of the port A pins.

Table 7-1. Port A Pin Operation

Accesses to Data Bit

Data Direction Bit

I/O Pin Mode

Read

Write

Latch⁽¹⁾

Latch

0

1

Input, high-impedance

Output

Latch

1. Writing affects the data register but does not affect input.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Parallel I/O Ports (PORTS)

Data Sheet

67

Parallel I/O Ports (PORTS)

7.2.3 Pulldown Register A

Pulldown register A inhibits the pulldown devices on port A pins programmed as

inputs.

NOTE:

If the SWPDI bit in the mask option register is programmed to logic 1, reset

initializes all port A pins as inputs with disabled pulldown devices.

Address:

$0010

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

PDIA7

0

PDIA6

0

PDIA5

0

PDIA4

0

PDIA3

0

PDIA2

0

PDIA1

0

PDIA0

0

= Unimplemented

Figure 7-5. Pulldown Register A (PDRA)

PDIA[7:0] — Pulldown Inhibit A Bits

PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0].

1 = Corresponding port A pulldown device disabled

0 = Corresponding port A pulldown device not disabled

7.2.4 Port LED Drive Capability

All outputs can drive light-emitting diodes (LEDs). These pins can sink

approximately 10 mA of current to V_SS.

7.2.5 Port A I/O Pin Interrupts

If the PIRQ bit in the mask option register is programmed to logic 1, PA0–PA3 pins

function as external interrupt pins. (See Section 5. External Interrupt Module

(IRQ).)

Data Sheet

68

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Parallel I/O Ports (PORTS)

MOTOROLA

Parallel I/O Ports (PORTS)

Port B

7.3 Port B

Port B is a 2-bit bidirectional port.

7.3.1 Port B Data Register

The port B data register contains a latch for each port B pin.

Address:

$0001

Bit 7

0

6

0

5

4

3

2

1

Bit 0

See Note

Read:

Write:

Reset:

See Note

PB3

PB2

Unaffected by reset

= Unimplemented

Note:

PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are

available for read/write but are not available externally. Configuring them as inputs will

ensure that the pulldown devices are enabled, thus properly terminating them.

Figure 7-6. Port B Data Register (PORTB)

PB[3:2] — Port B Data Bits

These read/write bits are software programmable. Data direction of each port B pin

is under the control of the corresponding bit in data direction register B. Reset has

no effect on port B data.

NOTE:

PB4–PB5 and PB0–PB1 should be configured as inputs at all times. These bits are

available for read/write but are not available externally. Configuring them as inputs

will ensure that the pulldown devices are enabled, thus properly terminating them.

7.3.2 Data Direction Register B

Data direction register B determines whether each port B pin is an input or an

output.

Address:

$0005

Bit 7

0

6

0

5

0

4

0

3

DDRB3

0

2

DDRB2

0

1

0

Bit 0

See Note

Read:

Write:

Reset:

See Notes

0

= Unimplemented

Note:

DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These

bits are available for read/write but are not available externally. Configuring them as inputs

will ensure that the pulldown devices are enabled, thus properly terminating them.

Figure 7-7. Data Direction Register B (DDRB)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Parallel I/O Ports (PORTS)

Data Sheet

69

Parallel I/O Ports (PORTS)

DDRB[3:2] — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears DDRB[3:2],

configuring all port B pins as inputs.

1 = Corresponding port B pin configured as output

0 = Corresponding port B pin configured as input

NOTE:

Avoid glitches on port B pins by writing to the port B data register before changing

data direction register B bits from 0 to 1.

Figure 7-8 shows the I/O logic of port B.

READ DDRB

WRITE DDRB

DDRBx

WRITE PORTB

PBx

READ PORTB

WRITE PDRB

100-µA

PULLDOWN

PDRBx

RESET

SWPDI

Figure 7-8. Port B I/O Circuitry

Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port

B pin; a logic 0 disables the output buffer.

When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch.

When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the

pin. The data latch can always be written, regardless of the state of its data

direction bit. Table 7-2 summarizes the operation of the port B pins.

Table 7-2. Port B Pin Operation

Accesses to Data Bit

Data Direction Bit

I/O Pin Mode

Read

Write

Latch⁽¹⁾

Latch

0

1

Input, high-impedance

Output

Latch

1. Writing affects the data register, but does not affect input.

Data Sheet

70

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Parallel I/O Ports (PORTS) MOTOROLA

Parallel I/O Ports (PORTS)

Port B

7.3.3 Pulldown Register B

Pulldown register B inhibits the pulldown devices on port B pins programmed as

inputs.

NOTE:

If the SWPDI bit in the mask option register is programmed to logic 1, reset

initializes all port B pins as inputs with disabled pulldown devices.

Address:

$0011

Bit 7

6

5

0

4

0

3

2

1

0

Bit 0

Read:

Write:

Reset:

See Note

PDIB3

0

PDIB2

0

See Note

0

= Unimplemented

Note:

These pulldown devices are permanently enabled when PB5, PB4, PB1 and PB0 are

configured as inputs.

Figure 7-9. Pulldown Register B (PDRB)

PDIB[3:2] — Pulldown Inhibit B Bits

PDIB[3:2] disable the port B pulldown devices. Reset clears PDIB[3:2].

1 = Corresponding port B pulldown device disabled

0 = Corresponding port B pulldown device not disabled

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Parallel I/O Ports (PORTS)

Data Sheet

71

Parallel I/O Ports (PORTS)

7.4 I/O Port Electrical Characteristics

Table 7-3. I/O Port DC Electrical Characteristics (V_DD= 5.0 V)⁽¹⁾

Typ⁽²⁾

Characteristic

Current Drain Per Pin

Symbol

Min

Max

Unit

I

—

25

mA

Output High Voltage

(I_Load= –2.5 mA) PA4–PA7

V_DD–0.8

V_OH

—

V

(I_Load= –5.5 mA) PB2–PB3, PA0–PA3

Output Low Voltage

(I_Load= 10.0 mA) PA0–PA7, PB2–PB3

V_OL

V_IH

V_IL

—

0.8

V_DD

V

Input High Voltage

PA0–PA7, PB2–PB3

0.7 x V_DD

—

Input Low Voltage

PA0–PA7, PB2–PB3

0.2 x V_DD

V_SS

—

I/O Ports Hi-Z Leakage Current

PA0–PA7, PB2–PB3 (Without Individual

Pulldown Activated)

I_IL

0.2

±1

µA

Input Pulldown Current

PA0–PA7, PB2–PB3 (With Individual

Pulldown Activated)

I_IL

35

80

200

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to +85°C, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25°C.

Table 7-4. I/O Port DC Electrical Characteristics (V_DD= 3.3 V)⁽¹⁾

Typ⁽²⁾

Characteristic

Symbol

Min

Max

Unit

Current Drain Per Pin

Output High Voltage

I

—

25

mA

(I_Load= –0.8 mA) PA4–PA7

V_DD–0.3

V_OH

—

V

(I_Load= –1.5 mA) PA0–PA3, PB2–PB3

Output Low Voltage

(I_Load= 5.0 mA) PA4–PA7

V_OL

—

0.5

(I_Load= 3.5 mA) PA0–PA3, PB2–PB3

Input High Voltage

PA0–PA7, PB2–PB3

V_IH

V_IL

0.7 x V_DD

V_SS

V_DD

—

V

Input Low Voltage

PA0–PA7, PB2–PB3

0.2 x V_DD

I/O Ports Hi-Z Leakage Current

PA0–PA7, PB2–PB3 (Without Individual Pulldown

Activated)

I_IL

—

0.1

30

±1

µA

Input Pulldown Current

PA0–PA7, PB2–PB3 (With Individual Pulldown Activated)

I_IL

12

100

1. V_DD= 3.3 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to +85°C, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25°C.

Data Sheet

72

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Parallel I/O Ports (PORTS) MOTOROLA

Data Sheet — MC68HC705KJ1

Section 8. Resets and Interrupts

8.1 Introduction

Reset initializes the MCU by returning the program counter to a known address and

by forcing control and status bits to known states.

Interrupts temporarily change the sequence of program execution to respond to

events that occur during processing.

8.2 Resets

A reset immediately stops the operation of the instruction being executed,

initializes certain control and status bits, and loads the program counter with a

user-defined reset vector address. The following sources can generate a reset:

•

Power-on reset (POR) circuit

RESET pin

Computer operating properly (COP) watchdog

Illegal address

ILLEGAL ADDRESS

COP WATCHDOG

POWER-ON RESET

V_DD

TO CPU AND

PERIPHERAL

MODULES

RST

S

RESET PIN

D

Q

CK

RESET

LATCH

INTERNAL CLOCK

Figure 8-1. Reset Sources

8.2.1 Power-On Reset

A positive transition on the V_DDpin generates a power-on reset.

NOTE:

The power-on reset is strictly for power-up conditions and cannot be used to detect

drops in power supply voltage.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Resets and Interrupts

Data Sheet

73

Resets and Interrupts

A 4064-t_cyc(internal clock cycle) delay after the oscillator becomes active allows

the clock generator to stabilize. If any reset source is active at the end of this delay,

the MCU remains in the reset condition until all reset sources are inactive.

V_DD

OSCILLATOR STABILIZATION DELAY⁽²⁾

(NOTE 1)

OSC1 PIN

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

$07FE

$07FF

INTERNAL

DATA BUS

NEW PCL

NEW PCH

Notes:

1. Power-on reset threshold is typically between 1 V and 2 V.

2. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR

3. Internal clock, internal address bus, and internal data bus are not available externally.

Figure 8-2. Power-On Reset Timing

8.2.2 External Reset

A logic 0 applied to the RESET pin for 1 1/2 t_cycgenerates an external reset. A

Schmitt trigger senses the logic level at the RESET pin.

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

$07FE

$07FF

NEW PC NEW PC

OP

NEW

PCH

NEW

PCL

INTERNAL

DATA BUS

DUMMY

CODE

t_RL

RESET

Notes:

1. Internal clock, internal address bus, and internal data bus are not available externally.

2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.

Figure 8-3. External Reset Timing

Table 8-1. External Reset Timing

Characteristic

RESET Pulse Width

Symbol

Min

Max

Unit

t_RL

t_cyc

1.5

—

Data Sheet

74

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Resets and Interrupts MOTOROLA

Resets and Interrupts

Interrupts

8.2.3 COP Watchdog Reset

A timeout of the COP watchdog generates a COP reset. The COP watchdog is part

of a software error detection system and must be cleared periodically to start a new

timeout period. To clear the COP watchdog and prevent a COP reset, write a

logic 0 to bit 0 (COPC) of the COP register at location $07F0.

8.2.4 Illegal Address Reset

An opcode fetch from an address not in RAM or EPROM generates a reset.

The following sources can generate interrupts:

8.3 Interrupts

•

SWI instruction

External interrupt pins

–

IRQ/V_PPpin

PA0–PA3 pins

•

Timer

–

Real-time interrupt flag (RTIF)

Timer overflow flag (TOF)

An interrupt temporarily stops the program sequence to process a particular event.

An interrupt does not stop the operation of the instruction being executed, but takes

effect when the current instruction completes its execution. Interrupt processing

automatically saves the CPU registers on the stack and loads the program counter

with a user-defined interrupt vector address.

8.3.1 Software Interrupt

The software interrupt (SWI) instruction causes a non-maskable interrupt.

8.3.2 External Interrupt

An interrupt signal on the IRQ/V_PPpin latches an external interrupt request. When

the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is

set, the CPU then tests the I bit in the condition code register. If the I bit is clear,

the CPU then begins the interrupt sequence.

The CPU clears the IRQ latch during interrupt processing, so that another interrupt

signal on the IRQ/V_PPpin can latch another interrupt request during the interrupt

service routine. As soon as the I bit is cleared during the return from interrupt, the

CPU can recognize the new interrupt request. Figure 8-4 shows the IRQ/V_PPpin

interrupt logic.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Resets and Interrupts

Data Sheet

75

Resets and Interrupts

TO BIH & BIL

INSTRUCTION

PROCESSING

IRQ

LEVEL-SENSITIVE TRIGGER

(MOR LEVEL BIT)

IRQF

V

DD

EXTERNAL

INTERRUPT

REQUEST

IRQ

LATCH

CK

D

Q

PA3

PA2

PA1

PA0

IRQE

CLR

PIRQ

(MOR)

RESET

IRQ VECTOR FETCH

IRQR

Figure 8-4. External Interrupt Logic

Setting the I bit in the condition code register disables external interrupts.

The port A external interrupt bit (PIRQ) in the mask option register enables pins

PA0–PA3 to function as external interrupt pins.

The external interrupt sensitivity bit (LEVEL) in the mask option register controls

interrupt triggering sensitivity of external interrupt pins. The IRQ/V_PPpin can be

negative-edge triggered only or negative-edge and low-level triggered. Port A

external interrupt pins can be positive-edge triggered only or both positive-edge

and high-level triggered. The level-sensitive triggering option allows multiple

external interrupt sources to be wire-ORed to an external interrupt pin. An external

interrupt request, shown in Figure 8-5, is latched as long as any source is holding

an external interrupt pin low.

t_ILIL

t_ILIH

EXT. INT. PIN

t_ILIH

EXT. INT. PIN₁

.

EXT. INT. PIN_n

IRQ

(INTERNAL)

Figure 8-5. External Interrupt Timing

Data Sheet

76

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Resets and Interrupts

MOTOROLA

Resets and Interrupts

Interrupts

Table 8-2. External Interrupt Timing (V_DD= 5.0 Vdc)⁽¹⁾

Characteristic

Interrupt Pulse Width Low (Edge-Triggered)

Interrupt Pulse Period

Symbol

Min

Max

—

Unit

ns

t_ILIH

125

Note⁽²⁾

t_ILIL

t_cyc

—

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= –40°C to +85°C, unless otherwise noted.

2. The minimum t_ILILshould not be less than the number of interrupt service routine cycles plus

19 t_cyc

.

Table 8-3. External Interrupt Timing (V_DD= 3.3 Vdc)⁽¹⁾

Characteristic

Symbol

Min

Max

—

Unit

ns

t_ILIH

Interrupt Pulse Width Low (Edge-Triggered)

Interrupt Pulse Period

250

Note⁽²⁾

t_ILIL

t_cyc

—

1. V_DD= 3.3 Vdc ±10%, V_SS= 0 Vdc, T_A= –40°C to +85°C unless otherwise noted.

2. The minimum t_ILILshould not be less than the number of interrupt service routine cycles plus

19 t_cyc

.

8.3.3 Timer Interrupts

The timer can generate the following interrupt requests:

•

Real time

Timer overflow

Setting the I bit in the condition code register disables timer interrupts.

8.3.3.1 Real-Time Interrupt

A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while

the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer

status and control register.

8.3.3.2 Timer Overflow Interrupt

A timer overflow interrupt request occurs if the timer overflow flag, TOF, becomes

set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE

are in the timer status and control register.

8.3.4 Interrupt Processing

The CPU takes the following actions to begin servicing an interrupt:

•

Stores the CPU registers on the stack in the order shown in

Figure 8-6

•

Sets the I bit in the condition code register to prevent further interrupts

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Resets and Interrupts

Data Sheet

77

Resets and Interrupts

•

Loads the program counter with the contents of the appropriate interrupt

vector locations:

–

$07FC and $07FD (software interrupt vector)

$07FA and $07FB (external interrupt vector)

$07F8 and $07F9 (timer interrupt vector)

The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU

registers from the stack as shown in Figure 8-6.

$00C0 (BOTTOM OF STACK)

$00C1

$00C2

•

UNSTACKING

ORDER

5

4

3

2

1

2

3

4

5

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER

PROGRAM COUNTER (HIGH BYTE)

PROGRAM COUNTER (LOW BYTE)

•

STACKING

ORDER

•

$00FD

$00FE

$00FF (TOP OF STACK)

Figure 8-6. Interrupt Stacking Order

Table 8-4. Reset/Interrupt Vector Addresses

Local

Mask

Global

Mask

Priority

(1 = Highest)

Vector

Address

Function

Source

Power-On

RESET Pin

COP Watchdog⁽¹⁾

Reset

None

1

$07FE–$07FF

Illegal Address

Software Interrupt

(SWI)

Same Priority

as Instruction

User Code

None

IRQE

None

I Bit

$07FC–$07FD

$07FA–$07FB

$07F8–$07F9

IRQ/V_PPPin

External Interrupt

Timer Interrupts

2

3

RTIF Bit

TOF Bit

RTIE Bit

TOIE Bit

I Bit

1. The COP watchdog is programmable in the mask option register.

Data Sheet

78

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Resets and Interrupts MOTOROLA

Resets and Interrupts

Interrupts

FROM RESET

YES

I BIT SET?

NO

YES

EXTERNAL

INTERRUPT?

CLEAR IRQ LATCH.

NO

TIMER

INTERRUPT?

YES

STACK PC, X, A, CCR.

SET I BIT.

LOAD PC WITH INTERRUPT VECTOR.

NO

FETCH NEXT

INSTRUCTION.

SWI

INSTRUCTION?

YES

NO

RTI

INSTRUCTION?

YES

UNSTACK CCR, A, X, PC.

EXECUTE INSTRUCTION.

NO

Figure 8-7. Interrupt Flowchart

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Resets and Interrupts

Data Sheet

79

Resets and Interrupts

Data Sheet

80

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Resets and Interrupts MOTOROLA

Data Sheet — MC68HC705KJ1

Section 9. Multifunction Timer Module

9.1 Introduction

The multifunction timer provides a timing reference with programmable real-time

interrupt capability. Figure 9-2 shows the timer organization.

9.2 Features

9.3 Operation

Features of the multifunction timer include:

•

Timer overflow

Four selectable interrupt rates

Computer operating properly (COP) watchdog timer

A 15-stage ripple counter, preceded by a prescaler that divides the internal clock

signal by four, provides the timing reference for the timer functions. The value of

the first eight timer stages can be read at any time by accessing the timer counter

register at address $0009. A timer overflow function at the eighth stage allows a

timer interrupt every 1024 internal clock cycles.

The next four stages lead to the real-time interrupt (RTI) circuit. The RT1 and RT0

bits in the timer status and control register at address $0008 allow a timer interrupt

every 16,384, 32,768, 65,536, or 131,072 clock cycles. The last four stages drive

the selectable COP system. For information on the COP, refer to Section 3.

Computer Operating Properly Module (COP).

Addr.

Register Name

Bit 7

6

5

4

3

0

2

0

1

Bit 0

Read:

TOF

RTIF

Timer Status and Control Register

(TSCR) Write:

See page 83.

TOIE

RTIE

RT1

RT0

$0008

TOFR

0

RTIFR

0

Reset:

0

1

Timer Counter Register Read:

(TCR)

TMR7

TMR6

TMR5

TMR4

TMR3

TMR2

TMR1

TMR0

$0009

Write:

See page 84.

Reset:

0

= Unimplemented

Figure 9-1. I/O Register Summary

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Multifunction Timer Module

Data Sheet

81

Multifunction Timer Module

RESET

OVERFLOW

INTERNAL CLOCK

÷ 4

TIMER COUNTER REGISTER

(XTAL ÷ 2)

BITS [0:7] OF 15-STAGE

RIPPLE COUNTER

RESET

INTERRUPT

REQUEST

TIMER STATUS/CONTROL REGISTER

RTI RATE SELECT

RESET

÷ 2

BITS [8:14] OF 15-STAGE RIPPLE COUNTER

COP RESET

÷ 8

S

R

Q

RESET

Figure 9-2. Multifunction Timer Block Diagram

9.4 Interrupts

The following timer sources can generate interrupts:

•

Timer overflow flag (TOF) — The TOF bit is set when the first eight stages

of the counter roll over from $FF to $00. The timer overflow interrupt enable

bit, TOIE, enables TOF interrupt requests.

•

Real-time interrupt flag (RTIF) — The RTIF bit is set when the selected RTI

output becomes active. The real-time interrupt enable bit, RTIE, enables

RTIF interrupt requests.

Data Sheet

82

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Multifunction Timer Module

MOTOROLA

Multifunction Timer Module

I/O Registers

9.5 I/O Registers

The following registers control and monitor the timer operation:

•

Timer status and control register (TSCR)

Timer counter register (TCR)

9.5.1 Timer Status and Control Register

The read/write timer status and control register performs the following functions:

•

Flags timer interrupts

Enables timer interrupts

Resets timer interrupt flags

Selects real-time interrupt rates

Address:

$0008

Bit 7

6

5

TOIE

0

4

RTIE

0

3

2

1

RT1

1

Bit 0

RT0

1

Read:

Write:

Reset:

TOF

RTIF

0

TOFR

0

RTIFR

0

= Unimplemented

Figure 9-3. Timer Status and Control Register (TSCR)

TOF — Timer Overflow Flag

This read-only flag becomes set when the first eight stages of the counter roll

over from $FF to $00. TOF generates a timer overflow interrupt request if TOIE

is also set. Clear TOF by writing a logic 1 to the TOFR bit. Writing to TOF has

no effect. Reset clears TOF.

RTIF — Real-Time Interrupt Flag

This read-only flag becomes set when the selected RTI output becomes active.

RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF by

writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears

RTIF.

TOIE — Timer Overflow Interrupt Enable Bit

This read/write bit enables timer overflow interrupts. Reset clears TOIE.

1 = Timer overflow interrupts enabled

0 = Timer overflow interrupts disabled

RTIE — Real-Time Interrupt Enable Bit

This read/write bit enables real-time interrupts. Reset clears RTIE.

1 = Real-time interrupts enabled

0 = Real-time interrupts disabled

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Multifunction Timer Module

Data Sheet

83

Multifunction Timer Module

TOFR — Timer Overflow Flag Reset Bit

Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always reads as

logic 0. Reset clears TOFR.

RTIFR — Real-Time Interrupt Flag Reset Bit

Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads

as logic 0. Reset clears RTIFR.

RT1 and RT0 — Real-Time Interrupt Select Bits

These read/write bits select one of four real-time interrupt rates, as shown in

Table 9-1. Because the selected RTI output drives the COP watchdog,

changing the real-time interrupt rate also changes the counting rate of the COP

watchdog. Reset sets RT1 and RT0.

NOTE:

Changing RT1 and RT0 when a COP timeout is imminent can cause a real-time

interrupt request to be missed or an additional real-time interrupt request to be

generated. To prevent this occurrence, clear the COP timer before changing RT1

and RT0.

Table 9-1. Real-Time Interrupt Rate Selection

Minimum COP Timeout

RTI Period

(f_OP= 2 MHz)

COP Timeout Period

(–0/+1 RTI Period)

Period

(f_OP= 2 MHz)

RT1:RT0

RTI Rate

f_OP÷ 2¹⁴

f_OP÷ 2¹⁵

f_OP÷ 2¹⁶

f_OP÷ 2¹⁷

0 0

0 1

1 0

1 1

8.2 ms

16.4 ms

32.8 ms

65.5 ms

8 x RTI Period

65.5 ms

131.1 ms

262.1 ms

524.3 ms

9.5.2 Timer Counter Register

A 15-stage ripple counter is the core of the timer. The value of the first eight

stages is readable at any time from the read-only timer counter register shown in

Figure 9-4.

Address:

$0009

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

TCR7

TCR6

TCR5

TCR4

TCR3

TCR2

TCR1

TCR0

0

= Unimplemented

Figure 9-4. Timer Counter Register (TCR)

Data Sheet

84

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Multifunction Timer Module MOTOROLA

Multifunction Timer Module

Low-Power Modes

Power-on clears the entire counter chain and the internal clock begins clocking the

counter. After 4064 cycles (or 16 cycles if the SOSCD bit in the mask option

register is set), the power-on reset circuit is released, clearing the counter again

and allowing the MCU to come out of reset.

A timer overflow function at the eighth counter stage allows a timer interrupt every

1024 internal clock cycles.

9.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby

states.

9.6.1 Stop Mode

The STOP instruction has the following effects on the timer:

•

Clears the timer counter

Clears interrupt flags (TOF and RTIF) and interrupt enable bits (TOFE and

RTIE) in TSCR, removing any pending timer interrupt requests and disabling

further timer interrupts

9.6.2 Wait Mode

The timer remains active after a WAIT instruction. Any enabled timer interrupt

request can bring the MCU out of wait mode.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Multifunction Timer Module

Data Sheet

85

Multifunction Timer Module

Data Sheet

86

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Multifunction Timer Module MOTOROLA

Data Sheet — MC68HC705KJ1

10.1 Maximum Ratings

Section 10. Electrical Specifications

Maximum ratings are the extreme limits to which the MCU can be exposed without

permanently damaging it.

NOTE:

This device is not guaranteed to operate properly at the maximum ratings. For

guaranteed operating conditions, refer to 10.5 5.0-V DC Electrical

Characteristics and 10.6 3.3-V DC Electrical Characteristics

Table 10-1. Maximum Ratings⁽¹⁾

Rating

Symbol

Value

Unit

V_DD

Supply Voltage

–0.3 to +7.0

V

Current Drain per Pin

(Excluding V_DD, V_SS

I

25

mA

)

V_In

V_PP

V_SS– 0.3 to V_DD+ 0.3

V_SS– 0.3 to 2 x V_DD+ 0.3

–65 to +150

Input Voltage

IRQ/V_PPPin

V

T_STG

Storage Temperature Range

°C

1. Voltages are referenced to V

.

SS

10.2 Operating Temperature Range

Value (T_Lto T_H)

Package Type

Symbol

Unit

MC68HC705KJ1C⁽¹⁾P⁽²⁾, CDW⁽³⁾, CS⁽⁴⁾

T_A

–40 to +85

°C

1. C = extended temperature range

2. P = plastic dual in-line package (PDIP)

3. DW = small outline integrated circuit (SOIC)

4. S = ceramic DIP (Cerdip)

10.3 Thermal Characteristics

Characteristic

Thermal Resistance

Symbol

Value

Unit

MC68HC705KJ1P⁽¹⁾

MC68HC705KJ1DW⁽²⁾

MC68HC705KJ1S⁽³⁾

θ_JA

60

°C/W

1. P = plastic dual in-line package (PDIP)

2. DW = small outline integrated circuit (SOIC)

3. S = ceramic DIP (Cerdip)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Data Sheet

87

MOTOROLA

Electrical Specifications

10.4 Power Considerations

The average chip junction temperature, T_J, in °C can be obtained from:

T

= T + (P × θ

)

(1)

J

A

D

JA

where:

T_A= ambient temperature in °C

θ_JA= package thermal resistance, junction to ambient in °C/W

P_D= P_INT+ P_I/O

P_INT= I_CC× V_CC= chip internal power dissipation

P_I/O= power dissipation on input and output pins (user-determined)

For most applications, P_I/O

P_INTand can be neglected.

Ignoring P_I/O, the relationship between P_Dand T_Jis approximately:

K

P

= -----------------------------------

(2)

(3)

D

T

+ 273 °C

J

Solving equations (1) and (2) for K gives:

= P x (T + 273°C) + ΘJ x (P )

D

A

D

where K is a constant pertaining to the particular part. K can be determined from

equation (3) by measuring P_D(at equilibrium) for a known T_A. Using this value of

K, the values of P_Dand T_Jcan be obtained by solving equations (1) and (2)

iteratively for any value of T_A.

Data Sheet

88

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Electrical Specifications

MOTOROLA

Electrical Specifications

5.0-V DC Electrical Characteristics

10.5 5.0-V DC Electrical Characteristics

Characteristic⁽¹⁾

Typ⁽²⁾

Symbol

Min

Max

Unit

Output high voltage

(I_Load= –2.5 mA) PA4–PA7

V_DD–0.8

V_OH

—

V

(I_Load= –5.5 mA) PB2–PB3, PA0–PA3

Output low voltage⁽⁸⁾

(I_Load= 10.0 mA) PA0–PA7, PB2–PB3

V_OL

V_IH

V_IL

—

0.7 × V_DD

V_SS

—

0.8

V_DD

V

Input high voltage

PA0–PA7, PB2–PB3, IRQ/V_PP, RESET, OSC1

Input low voltage

PA0–PA7, PB2–PB3, IRQ/V_PP, RESET, OSC1

0.2 × V_DD

Supply current (f_OP= 2.1 MHz; f_OSC= 4.2 MHz)

Run mode⁽³⁾

Wait mode⁽⁴⁾

Stop mode⁽⁵⁾

—

4.0

1.0

0.1

6.0

2.8

5.0

mA

µA

I_DD

Supply current (f_OP= 4.0 MHz; f_OSC= 8.0 MHz)

Run mode⁽³⁾

Wait mode⁽⁴⁾

Stop mode⁽⁵⁾

—

5.2

1.1

0.1

7.0

3.3

5.0

mA

µA

I_DD

I/O Ports Hi-Z leakage current

PA0–PA7, PB2–PB3 (without individual pulldown activated)

I_IL

—

35

0.2

80

±1

µA

Input pulldown current

PA0–PA7, PB2–PB3 (with individual pulldown activated)

200

–85

Input pullup current

RESET

–15

–35

Input current⁽⁶⁾

RESET, IRQ/V_PP, OSC1

I_In

—

0.2

±1

µA

pF

Capacitance

Ports (As Inputs or Outputs)

RESET, IRQ, OSC1, OSC2

C_Out

C_In

—

12

8

Crystal/ceramic resonator oscillator mode internal resistor

OSC1 to OSC2⁽⁷⁾

R_OSC

1.0

2.0

3.0

MΩ

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to +85°C, unless otherwise noted.

2. Typical values at midpoint of voltage range, 25°C only

3. Run mode I_DDis measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF

on all outputs; C_L= 20 pF on OSC2.

4. Wait mode I_DD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured

with all ports configured as inputs; V_IL= 0.2 V; V_IH= V_DD– 0.2 V. Wait mode I_DDis measured using external square wave

clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C_L= 20 pF on OSC2.

5. Stop mode I_DDis measured with OSC1 = V_SS. Stop mode I_DDis measured with all ports configured as inputs; V_IL= 0.2 V;

V_IH= V_DD– 0.2 V.

6. Only input high current rated to +1 µA on RESET.

7. The R_OSCvalue selected for RC oscillator versions of this device is unspecified.

8. Maximum current drain for all I/O pins combined should not exceed 100 mA.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Data Sheet

89

MOTOROLA

Electrical Specifications

10.6 3.3-V DC Electrical Characteristics

Characteristic⁽¹⁾

Typ⁽²⁾

Symbol

Min

Max

Unit

Output high voltage

(I_Load= –0.8 mA) PA4–PA7

V_DD–0.3

V_OH

—

V

(I_Load= –1.5 mA) PA0–PA3, PB2–PB3

Output low voltage

(I_Load= 5.0 mA) PA4–PA7

V_OL

—

0.5

V

(I_Load= 3.5 mA) PA0–PA3, PB2–PB3

Input high voltage

PA0–PA7, PB2–PB3, IRQ/V_PP, RESET, OSC1

V_IH

V_IL

0.7 × V_DD

V_DD

—

V

Input low voltage

PA0–PA7, PB2–PB3, IRQ/V_PP, RESET, OSC1

V_SS

0.2 × V_DD

Supply current (f_OP= 1.0 MHz; f_OSC= 2.0 MHz)

Run mode⁽³⁾

Wait mode⁽⁴⁾

Stop mode⁽⁵⁾

—

1.2

0.3

0.1

2.5

0.8

5.0

mA

µA

I_DD

Supply current (f_OP= 2.1 MHz; f_OSC= 4.2 MHz)

Run mode⁽³⁾

Wait mode⁽⁴⁾

Stop mode⁽⁵⁾

—

1.4

0.3

0.1

3.0

1.0

5.0

mA

µA

I_DD

I/O ports hi-z leakage current

PA0–PA7, PB2–PB3 (without individual pulldown activated)

I_IL

—

12

0.1

30

±1

µA

Input pulldown current

PA0–PA7, PB2–PB3 (with individual pulldown activated)

100

–45

Input pullup current

RESET

–10

–25

Input current⁽⁶⁾

RESET, IRQ/V_PP, OSC1

I_In

—

0.1

±1

µA

pF

Capacitance

Ports (as inputs or outputs)

RESET, IRQ/V_PP, OSC1, OSC2

C_Out

C_In

—

12

8

Crystal/ceramic resonator oscillator mode internal resistor

OSC1 to OSC2⁽⁷⁾

R_OSC

1.0

2.0

3.0

MΩ

1. V_DD= 3.3 Vdc ± 10%, V_SS= 0 Vdc, T_A= –40°C to +85°C, unless otherwise noted.

2. Typical values at midpoint of voltage range, 25°C only

3. Run mode I_DDis measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF

on all outputs; C_L= 20 pF on OSC2.

4. Wait mode I_DD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured

with all ports configured as inputs; V_IL= 0.2 V; V_IH= V_DD– 0.2 V. Wait mode I_DDis measured using external square wave

clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; C_L= 20 pF on OSC2.

5. Stop mode I_DDis measured with OSC1 = V_SS. Stop mode I_DDis measured with all ports configured as inputs; V_IL= 0.2 V;

V_IH= V_DD– 0.2 V.

6. Only input high current rated to +1 µA on RESET.

7. The R_OSCvalue selected for RC oscillator versions of this device is unspecified.

Data Sheet

90

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Electrical Specifications MOTOROLA

Electrical Specifications

Driver Characteristics

10.7 Driver Characteristics

800

700

600

500

400

300

200

100

0

85°C

25°C

700

600

500

400

300

200

100

0

–40°C

V_DD= 5.0 V

V_DD= 3.3 V

0

–2

–4

–6

–8

–10

0

–2

–4

–6

–8

–10

I

_OH(mA)

I_OH(mA)

Notes:

1. At V_DD= 5.0 V, devices are specified and tested for (V_DD– V_OH) ≤ 800 mV @ I_OH= –2.5 mA.

2. At V_DD= 3.3 V, devices are specified and tested for (V_DD– V_OH) ≤ 300 mV @ I_OH= –0.8 mA.

Figure 10-1. PA4–PA7 Typical High-Side Driver Characteristics

800

700

600

500

400

300

200

100

0

800

85°C

25°C

700

600

500

400

300

200

100

0

85°C

–40°C

V_DD= 5.0 V

V_DD= 3.3 V

0

–2

–4

–6

–8

–10

0

–2

–4

–6

–8

–10

I

_OH(mA)

I_OH(mA)

Notes:

1. At V_DD= 5.0 V, devices are specified and tested for (V_DD– V_OH) ≤ 800 mV @ I_OH= –5.5 mA.

2. At V_DD= 3.3 V, devices are specified and tested for (V_DD– V_OH) ≤ 300 mV @ I_OH= –1.5 mA.

Figure 10-2. PA0–PA3 and PB2–PB3 Typical High-Side Driver Characteristics

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Data Sheet

91

MOTOROLA

Electrical Specifications

800

700

800

700

600

500

400

300

200

100

0

85°C

25°C

85°C

25°C

600

500

–40°C

400

300

200

100

0

V_DD= 5.0 V

V_DD= 3.3 V

0

10

20

30

I_OL(mA)

40

50

0

10

20

30

I_OL(mA)

40

50

Notes:

1. At V_DD= 5.0 V, devices are specified and tested for V_OL≤ 800 mV @ I_OL= 10.0 mA.

2. At V_DD= 3.3 V, devices are specified and tested for V_OL≤ 500 mV @ I_OL= 5.0 mA.

Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics

800

700

600

500

400

300

200

100

0

85°C

700

600

500

400

300

200

100

0

25°C

–40°C

25°C

–40°C

V_DD= 5.0 V

V_DD= 3.3 V

0

10

20

30

0

10

20

30

I_OL(mA)

I

_OL(mA)

Notes:

1. At V_DD= 5.0 V, devices are specified and tested for V_OL≤ 800 mV @ I_OL= 10.0 mA.

2. At V_DD= 3.3 V, devices are specified and tested for V_OL≤ 500 mV @ I_OL= 3.5 mA.

Figure 10-4. PA0–PA3 and PB2–PB3 Typical Low-Side Driver Characteristics

Data Sheet

92

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Electrical Specifications MOTOROLA

Electrical Specifications

Typical Supply Currents

10.8 Typical Supply Currents

7.0 mA

SEE NOTE 1

6.0 mA

5.0 mA

5.5 V

SEE NOTE 2

4.0 mA

4.5 V

3.0 mA

2.0 mA

1.0 mA

0

3.6 V

3.0 V

Notes:

1. At V_DD= 5.0 V, devices are specified and

tested for I_DD≤ 7.0 mA @ f_OP= 4.0 MHz.

2. At V_DD= 3.3 V, devices are specified and

tested for I_DD≤ 4.25 mA @ f_OP= 2.1 MHz.

0

1.0 MHz

2.0 MHz

3.0 MHz

4.0 MHz

INTERNAL OPERATING FREQUENCY (f_OP

)

Figure 10-5. Typical Operating I_DD(25°C)

SEE NOTE 1

SEE NOTE 2

700 µA

5.5 V

600 µA

500 µA

400 µA

300 µA

200 µA

100 µA

0

4.5 V

3.6 V

3.0 V

Notes:

1. At V_DD= 5.0 V, devices are specified and

tested for I_DD≤ 3.25 mA @ f_OP= 4.0 MHz.

2. At V_DD= 3.3 V, devices are specified and

tested for I_DD≤ 1.75 mA @ f_OP= 2.1 MHz.

0

1.0 MHz

2.0 MHz

3.0 MHz

4.0 MHz

INTERNAL OPERATING FREQUENCY (f_OP

)

Figure 10-6. Typical Wait Mode I_DD(25°C)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Electrical Specifications

Data Sheet

93

Electrical Specifications

Control Timing

Table 10-3. Control Timing (V_DD= 3.3 Vdc)⁽¹⁾

Characteristic

Oscillator frequency

Symbol

Min

Max

Unit

f_OSC

Crystal oscillator option

External clock source

—

dc

4.2

MHz

Internal operating frequency (f_OSC÷ 2)

f_OP

—

dc

2.1

MHz

Crystal oscillator

External clock

Cycle time (1 ÷ f_OP

)

t_cyc

t_RL

476

1.5

—

ns

t_cyc

RESET pulse width low

IRQ interrupt pulse width low

(edge-triggered)

t_ILIH

t_ILIL

t_IHIL

t_cyc

1.5

—

IRQ interrupt pulse width low

(edge- and level-triggered)

Note⁽²⁾

—

PA0–PA3 interrupt pulse width high

(edge-triggered)

PA0–PA3 interrupt pulse width

(edge- and level-triggered)

Note⁽²⁾

—

t_IHIH

t_cyc

ns

1.5

t_OH, t_OL

OSC1 pulse width

200

1. V_DD= 3.3 Vdc ± 10%, V_SS= 0 Vdc, T = –40°C to +85°C, unless otherwise noted.

A

2. The maximum width t_ILILor t_ILIHshould not be more than the number of cycles it takes to

execute the interrupt service routine plus 19 t_cycor the interrupt service routine will be

re-entered.

t_ILIL

t_ILIH

IRQ PIN

t_ILIH

IRQ₁

.

IRQ_n

IRQ

(INTERNAL)

Figure 10-7. External Interrupt Timing

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Electrical Specifications

Data Sheet

95

Electrical Specifications

OSC (NOTE 1)

t_RL

RESET

t_ILIH

IRQ (NOTE 2)

OSCILLATOR STABILIZATION DELAY⁽⁵⁾

IRQ (NOTE 3)

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

07FE

(NOTE 4)

07FE

07FF

RESET OR INTERRUPT

VECTOR FETCH

Notes:

1. Internal clocking from OSC1 pin

2. Edge-triggered external interrupt mask option

3. Edge- and level-triggered external interrupt mask option

4. Reset vector shown as example

5. 4064 t_cycor 128 t_cyc, depending on the state of SOSCD bit in MOR

Figure 10-8. Stop Mode Recovery Timing

V_DD

(NOTE 1)

OSCILLATOR STABILIZATION DELAY⁽³⁾

OSC1 PIN

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

07FE

07FF

INTERNAL

DATA BUS

NEW

PCH

NEW

PCL

NOTES:

1. Power-on reset threshold is typically between 1 V and 2 V.

2. Internal clock, internal address bus, and internal data bus are not available externally.

3. 4064 t_cycor 128 t_cycdepending on the state of SOSCD bit in MOR

Figure 10-9. Power-On Reset Timing

Data Sheet

96

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Electrical Specifications MOTOROLA

Electrical Specifications

Control Timing

INTERNAL

CLOCK

INTERNAL

ADDRESS BUS

07FE

07FF

NEW PC

OP

INTERNAL

DATA BUS

NEW

PCH

NEW

PCL

DUMMY

CODE

t_RL

NOTES:

1. Internal clock, internal address bus, and internal data bus are not available externally.

2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.

Figure 10-10. External Reset Timing

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Data Sheet

97

MOTOROLA

Electrical Specifications

Data Sheet

98

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

Electrical Specifications MOTOROLA

Data Sheet — MC68HC705KJ1

Section 11. Ordering Information and Mechanical Specifications

11.1 Introduction

The MC68HC705J1A, the RC oscillator, and low-speed option devices described

in Appendix A. MC68HRC705KJ1 and Appendix B. MC68HLC705KJ1 are

available in these packages:

•

648 — Plastic dual in-line package (PDIP)

751G — Small outline integrated circuit (SOIC)

620A — Ceramic DIP (Cerdip) (windowed)

This section contains ordering information and mechanical specifications for the

available package types.

11.2 MCU Order Numbers

Table 11-1 lists the MC order numbers.

(1)

Table 11-1. Order Numbers

Package

Type

Case

Outline

Count

Operating

Temperature

Order Number

PDIP

SOIC

Cerdip

648

16

–40 to +85°C

MC68HC705KJ1C⁽²⁾

MC68HC705KJ1CDW⁽³⁾

MC68HC705KJ1CS⁽⁴⁾

751G

620A

1. Refer to Appendix A. MC68HRC705KJ1 and Appendix B. MC68HLC705KJ1 for ordering

information on optional low-speed and resistor-capacitor oscillator devices.

2. C = extended temperature range

3. DW = small outline integrated circuit (SOIC)

4. S = ceramic dual in-line package (Cerdip)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Ordering Information and Mechanical Specifications

Data Sheet

99

Ordering Information and Mechanical Specifications

16-Pin Cerdip — Case #620A

11.5 16-Pin Cerdip — Case #620A

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

B

A

M

16

1

9

8

B

L

INCHES

DIM MIN MAX

MILLIMETERS

MIN

19.05

6.10

–––

MAX

19.93

7.49

5.08

0.50

A

B

C

D

E

F

0.750

0.240

–––

0.785

0.295

0.200

0.020

16X J

0.015

0.39

M

0.25 (0.010)

T

B

0.050 BSC

1.27 BSC

E

0.055

0.065

1.40

1.65

G

H

K

L

0.100 BSC

2.54 BSC

F

0.008

0.125

0.015

0.170

0.21

3.18

0.38

4.31

0.300 BSC

7.62 BSC

M

N

0

0.020

15

0.040

0

0.51

15

1.01

C

STYLE 1:

K

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. CATHODE

9. ANODE

SEATING

PLANE

T

N

G

16X D

M

0.25 (0.010)

T A

10. ANODE

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA Ordering Information and Mechanical Specifications

Data Sheet

101

Data Sheet — MC68HC705KJ1

Appendix A. MC68HRC705KJ1

A.1 Introduction

This appendix introduces the MC68HRC705KJ1, a resistor-capacitor (RC)

oscillator mask option version of the MC68HC705KJ1. All of the information in

MC68HC705KJ1 Technical Data applies to the MC68HRC705KJ1 with the

exceptions given in this appendix.

A.2 RC Oscillator Connections

For greater cost reduction, the RC oscillator mask option allows the configuration

shown in Figure A-1 to drive the on-chip oscillator. Mount the RC components as

close as possible to the pins for startup stabilization and to minimize output

distortion.

OSC1

R

OSC2

MCU

R

V_DD

C2 C1

V_SS

Figure A-1. RC Oscillator Connections

NOTE:

The optional internal resistor is not recommended for configurations that use the

RC oscillator connections as shown in Figure A-1. For such configurations, the

oscillator internal resistor (OSCRES) bit of the mask option register should be

programmed to a logic 0.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA MC68HRC705KJ1

Data Sheet

103

MC68HRC705KJ1

RC Oscillator Connections (No External Resistor)

A.4 RC Oscillator Connections (No External Resistor)

For maximum cost reduction, the RC oscillator mask connections shown in

Figure A-3 allow the on-chip oscillator to be driven with no external components.

This can be accomplished by programming the oscillator internal resistor

(OSCRES) bit in the mask option register to a logic 1. When programming the

OSCRES bit for the MC68HRC705KJ1, an internal resistor is selected which yields

typical internal oscillator frequencies as shown in Figure A-4. The internal

resistance for this device is different than the resistance of the selectable internal

resistor on the MC68HC705KJ1 and the MC68HRC705KJ1 devices.

OSC1

R

OSC2

MCU

V_DD

C2 C1

(EXTERNAL CONNECTIONS LEFT OPEN)

V_SS

Figure A-3. RC Oscillator Connections (No External Resistor)

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA MC68HRC705KJ1

Data Sheet

105

MC68HRC705KJ1

A.5 Typical Internal Operating Frequency Versus Temperature (No External Resistor)

3.00

2.50

3.0 V

3.6 V

4.5 V

5.0 V

5.5 V

2.00

1.50

1.00

0.50

0.00

–50

0

50

100

150

Temperature (°C)

Figure A-4. Typical Internal Operating Frequency

versus Temperature (OSCRES Bit = 1)

NOTE:

Due to process variations, operating voltages, and temperature requirements, the

internal resistance and tolerance are unspecified. Typically for a given voltage and

temperature, the frequency should not vary more than ± 500 kHz. However, this

data is not guaranteed. It is the user’s responsibility to ensure that the resulting

internal operating frequency meets user’s requirements.

A.6 Package Types and Order Numbers

Table A-1. MC68HRC705KJ1 (RC Oscillator Option)

Order Numbers⁽¹⁾

Package

Type

Case

Outline

Count

Operating

Order Number

Temperature

–40 to +85°C

MC68HRC705KJ1C⁽²⁾P⁽³⁾

MC68HRC705KJ1CDW⁽⁴⁾

MC68HRC705KJ1CS⁽⁵⁾

PDIP

SOIC

Cerdip

648

16

751G

620A

16

1. Refer to Section 11. Ordering Information and Mechanical Specifications for standard

part ordering information.

2. C = extended temperature range

3. P = plastic dual in-line package (PDIP)

4. DW = small outline integrated circuit (SOIC)

5. S = ceramic dual in-line package (Cerdip)

Data Sheet

106

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MC68HRC705KJ1

MOTOROLA

Data Sheet — MC68HC705KJ1

Appendix B. MC68HLC705KJ1

B.1 Introduction

This appendix introduces the MC68HLC705KJ1, a low-frequency version of the

MC68HC705KJ1 optimized for 32-kHz oscillators. All of the information in

MC68HC705KJ1 Technical Data applies to the MC68HLC705KJ1 with the

exceptions given in this appendix.

B.2 DC Electrical Characteristics

Table B-1. DC Electrical Characteristics (V_DD= 5 V)

Characteristic

Symbol

Min

Typ

Max

Unit

Supply Current (f_OP= 16.0 kHz, f_OSC= 32.0 kHz)

I_DD

—

45

20

60

30

µA

Run

Wait

Table B-2. DC Electrical Characteristics (V_DD= 3.3 V)

Characteristic

Symbol

Min

Typ

Max

Unit

Supply Current (f_OP= 16.0 kHz, f_OSC= 32.0 kHz)

I_DD

—

25

10

35

15

µA

Run

Wait

MCU

R_S

R_P

32 kHz

C_L

Figure B-1. Crystal Connections

NOTE:

Supply current is impacted by crystal type and external components.Since each

crystal has its own characteristics, the user should consult the crystal manufacturer

for appropriate values for external components.

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MOTOROLA MC68HLC705KJ1

Data Sheet

107

MC68HLC705KJ1

B.3 Package Types and Order Numbers

Table B-3. MC68HLC705KJ1 (Low Frequency) Order Numbers⁽¹⁾

Package

Type

Case

Outline

Count

Operating

Temperature

Order Number

MC68HLC705KJ1C⁽²⁾

P

PDIP

SOIC

Cerdip

648

16

–40 to +85°C

MC68HLC705KJ1CDW⁽³⁾

MC68HLC705KJ1CS⁽⁴⁾

751G

620A

1. Refer to Section 11. Ordering Information and Mechanical Specifications for standard

part ordering information.

2. C = extended temperature range

3. DW = small outline integrated circuit (SOIC)

4. S = ceramic dual in-line package (Cerdip)

Data Sheet

108

MC68HC705KJ1•MC68HRC705KJ1•MC68HLC705KJ1 — Rev. 4.0

MC68HLC705KJ1

MOTOROLA

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

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P.O. Box 5405

Denver, Colorado 80217

1-800-521-6274 or 480-768-2130

JAPAN:

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SPS, Technical Information Center

3-20-1, Minami-Azabu, Minato-ku

Tokyo 106-8573, Japan

81-3-3440-3569

ASIA/PACIFIC:

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2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

852-26668334

HOME PAGE:

http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to use Motorola products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or

integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume

any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts.

Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,

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MC68HC705KJ1/D

Rev. 4

5/2003

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68HC705KJ1 : Microcontroller

Page Contents:

The MC68HC05KJ1 is a member of Motorola's low-cost, high-performance M68HC05 Family of 8-bit

microcontroller units (MCUs).These 16 and 20-pin families provide a low-cost, low pin count, 8-bit upgrade

for existing 4-bit applications. They combine a powerful 68HC05 CPU with a flexible, 15-stage

multifunction timer and real-time interrupt capability. The 68HC705KJ1 is Motorola's most cost effective

One Time Programmable (OTP) microcontroller.

Features

Documentation

Tools

Orderable Parts


型号：	KMCL705KJ1CDW
厂家：	MOTOROLA
描述：	8-BIT, OTPROM, 4MHz, MICROCONTROLLER, PDSO16, SOIC-16 可编程只读存储器时钟光电二极管外围集成电路
文件：	总117页 (文件大小：1536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KMCL705KJ1CDW [MOTOROLA]

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