KMPC866TZP133 [MOTOROLA]
RISC Microprocessor, 32-Bit, 133MHz, CMOS, PBGA256, 23 X 23 MM, PLASTIC, BGA-256;
| 型号： | KMPC866TZP133 |
| 厂家： | 
MOTOROLA |
| 描述： | RISC Microprocessor, 32-Bit, 133MHz, CMOS, PBGA256, 23 X 23 MM, PLASTIC, BGA-256 |
| 文件： | 总92页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hardware Specification
MPC866EC/D
Rev. 1, 11/2002
MPC866/859T/859DSL
Hardware Specifications
This document contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications for the
MPC866/859T/859DSL family (refer to Table 1-1 for a list of devices).The
MPC866P is the superset device of the MPC866/859T/859DSL family. This
document contains the following topics:
Topic
Page
Part I, “Overview”
1
Part II, “Features”
2
Part III, “Maximum Tolerated Ratings”
Part IV, “Thermal Characteristics”
Part V, “Power Dissipation”
9
10
10
11
12
16
16
17
46
48
71
73
77
89
Part VI, “DC Characteristics”
Part VII, “Thermal Calculation and Measurement”
Part VIII, “Power Supply and Power Sequencing
Part IX, “Layout Practices”
Part X, “Bus Signal Timing”
Part XI, “IEEE 1149.1 Electrical Specifications”
Part XII, “CPM Electrical Characteristics”
Part XIII, “UTOPIA AC Electrical Specifications”
Part XIV, “FEC Electrical Characteristics”
Part XV, “Mechanical Data and Ordering Information”
Part XVI, “Document Revision History
Part I Overview
The MPC866/859T/859DSL is a derivative of Motorola’s MPC860
PowerQUICC™ family of devices. It is a versatile single-chip integrated
microprocessor and peripheral combination that can be used in a variety of
controller applications and communications and networking systems. The
MPC866/859/859DSL provides enhanced ATM functionality over that of other
ATM-enabled members of the MPC860 family.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 1-1 shows the functionality supported by the members of the
MPC866/859T/859DSL family.
Table 1-1. MPC866 Family Functionality
Cache
Ethernet
Part
SCC SMC
Instruction
Cache
Data Cache
10T
10/100
MPC866P
MPC866T
MPC859T
MPC859DSL
16 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
4 KByte
8 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
Up to 4
1
1
1
1
1
4
4
1
2
2
2
Up to 4
1
1
2
1
2
1
1
3
MPC852T
2
1
1
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does
not support the Time Slot Assigner (TSA)
2
3
On the MPC859DSL, the SMC (SMC1) is for UART only
For more details on the MPC852T, please refer to the MPC852T Hardware
Specifications
Part II Features
The following list summarizes the key MPC866/859T/859DSL features:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without
conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1-1).
– 16-Kbyte instruction cache (MPC866P) is four-way, set-associative with 256
sets;4-Kbyte instruction cache(MPC866T, MPC859T, and MPC859DSL) is
two-way, set-associative with 128 sets.
– 8-Kbyte data cache (MPC866P) is two-way, set-associative with 256 sets;
4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way,
set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit
(4-word) cache blocks.
– Caches are physically addressed, implement a least recently used (LRU)
replacement algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
virtual address spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
2
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
• The MPC866/859T/859DSL provides enhanced ATM functionality over that of the
MPC860SAR. The MPC866/859T/859DSL adds major new features available in
“enhanced SAR” (ESAR) mode, including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace
requirements
— ATM port-to-port switching capability without the need for RAM-based
microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the
total cell transmission time. (The earlier UTOPIA level 1 specification is also
supported.)
– Multi-PHY support on the MPC859T
– Four PHY support on the MPC859DSL
— Parameter RAM for both SPI and I2C can be relocated without RAM-based
microcode
— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side)
operation using a “split” bus
— AAL2/VBR functionality is ROM-resident
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to Page mode/EDO/SDRAM, SRAM, EPROMs, flash
EPROMs, and other memory devices.
— DRAM controller programmable to support most size and speed memory
interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
• General-purpose timers
— Four 16-bit timers cascadable to be two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• Fast Ethernet controller (FEC)
— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the
UTOPIA multiplexed bus.
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
— The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859T
and MPC859DSL have 20 internal interrupt sources
— Programmable priority between SCCs (MPC866P and MPC866T)
— Programmable highest priority request
• Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT,
ENTER HUNT MODE, and RESTART TRANSMIT)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— The MPC866P and MPC866T have 16 serial DMA (SDMA) channels; the
MPC859T and MPC859DSL have 10 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
• Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
4
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
— Autobaud support option
• The MPC866P and MPC866T have four SCCs (serial communication controller),
The MPC859T and MPC859DSL have one SCC, SCC1; the MPC859DSL supports
ethernet only
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• Two SMCs (serial management channels) (The MPC859DSL has one SMC, SMC1
for UART)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
• One inter-integrated circuit (I2C) port
— Supports master and slave modes
— Multiple-master environment support
• Time-slot assigner (TSA) (The MPC859DSL does not have the TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user
defined
— 1- or 8-bit resolution
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
— Allows independent transmit and receive routing, frame synchronization,
clocking
— Allows dynamic changes
— On the MPC866P and MPC866T, can be internally connected to six serial
channels (four SCCs and two SMCs); on the MPC859T, can be connected to
three serial channels (one SCC and two SMCs)
• Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC866/859T/859DSL
or MC68360
• PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one or two PCMCIA sockets dependant upon whether ESAR
functionality is enabled
— 8 memory or I/O windows supported
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
— Supports conditions: = ≠ < >
— Each watchpoint can generate a break point internally
• Normal High and Normal Low Power Modes to conserve power
• 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility, refer to Table 6-6
for a listing of the 5 V Tolerant pins
• 357-pin plastic ball grid array (PBGA) package
• Operation up to 133MHz
The MPC866/859T/859DSL is comprised of three modules that each use the 32-bit internal
bus: the MPC8xx core, the system integration unit (SIU), and the communication processor
module (CPM). The MPC866P block diagram is shown in Figure 2-1. The
MPC859T/859DSL block diagram is shown in Figure 2-2.
6
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
16-Kbyte
Instruction Cache
Instruction
Bus
System Interface Unit (SIU)
Unified
Bus
Memory Controller
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Internal
Bus Interface Bus Interface
Unit Unit
External
8-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
PCMCIA/ATA Interface
32-Entry DTLB
Fast Ethernet
Controller
DMAs
FIFOs
4
Interrupt
8-Kbyte
Timers Controllers Dual-Port RAM
16 Virtual
Serial
and
Parallel I/O
10/100
Base-T
Media Access
Control
4 Baud Rate
Generators
32-Bit RISC Controller
and Program
ROM
2
Independent
DMA
Channels
Parallel Interface Port
and UTOPIA
Timers
MII
2
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I C
TimeSlotAssigner
Serial Interface
Figure 2-1. MPC866P Block Diagram
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
4-Kbyte
Instruction Cache
Instruction
Bus
System Interface Unit (SIU)
Unified
Bus
Memory Controller
Instruction MMU
32-Entry ITLB
Embedded
MPC8xx
Processor
Core
Internal
Bus Interface Bus Interface
Unit Unit
External
4-Kbyte
Data Cache
Load/Store
Bus
System Functions
Data MMU
PCMCIA/ATA Interface
32-Entry DTLB
Fast Ethernet
Controller
DMAs
FIFOs
4
Interrupt
8-Kbyte
Timers Controllers Dual-Port RAM
10 Virtual
Serial
and
Parallel I/O
10/100
Base-T
Media Access
Control
4 Baud Rate
Generators
32-Bit RISC Controller
and Program
ROM
2
Independent
DMA
Channels
Parallel Interface Port
and UTOPIA
Timers
MII
2
SCC1
SMC1
SMC2*
SPI
I C
TimeSlotAssigner*
Serial Interface
* The MPC859DSL does not contain SMC2 nor the Time Slot Assigner, and provides eight SDMA
controllers.
Figure 2-2. MPC859T/MPC859DSL Block Diagram
8
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Part III Maximum Tolerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the
MPC866/859T/859DSL. Table 3-2 provides the maximum tolerated ratings, and Table 3-3
provides the operating temperatures.
Table 3-2. Maximum Tolerated Ratings
Rating
Symbol
VDDH
Value
Unit
1
Supply voltage
-0.3 to 4.0
-0.3 to 2.0
-0.3 to 2.0
V
V
VDDL
VDDSYN
V
Differencebetween 100
VDDL to VDDSYN
mV
2
Input voltage
Storage temperature range
V
GND-0.3 to VDDH
-55 to +150
V
in
T
˚C
stg
1
2
The power supply of the device must start its ramp from 0.0 V.
Functional operating conditions are provided with the DC electrical specifications in Table 6-6.
Absolute maximum ratings are stress ratings only; functional operation at the maxima is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage
to the device. See Section Part VIII, “Power Supply and Power Sequencing”.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This
restriction applies to power-up and normal operation (that is, if the MPC866/859T/859DSL is
unpowered, a voltage greater than 2.5 V must not be applied to its inputs).
Table 3-3. Operating Temperatures
Rating
Symbol
Value
Unit
1
Temperature (standard)
Temperature (extended)
T
0
˚C
˚C
˚C
˚C
A(min)
T
95
-40
100
j(max)
T
A(min)
T
j(max)
1
Minimum temperatures are guaranteed as ambient temperature, T . Maximum temperatures are
A
guaranteed as junction temperature, T .
j
This device contains circuitry protecting against damage due to high-static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid application
of any voltages higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage
level (for example, either GND or VDD).
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
9
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Part IV Thermal Characteristics
Table 4-4 shows the thermal characteristics for the MPC866/859T/859DSL.
Table 4-4. MPC866/859T/859DSL Thermal Resistance Data
Rating
Environment
Single layer board (1s)
Symbol
Value
Unit
1
2
Junction to ambient
Natural Convection
Air flow (200 ft/min)
R
37
23
30
19
13
6
°C/W
θJA
3
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
R
θJMA
3
R
R
θJMA
3
θJMA
4
Junction to board
R
θJB
θJC
5
Junction to case
R
6
Junction to package top Natural Convection
Air flow (200 ft/min)
Ψ
2
JT
JT
Ψ
2
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board,
and board thermal resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature
is measured on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold
plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case
temperature. For exposed pad packages where the pad would be expected to be soldered, junction to case
thermal resistance is a simulated value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
Part V Power Dissipation
Table 5-5 provides power dissipation information. The modes are 1:1, where CPU and bus
speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed.
Table 5-5. Power Dissipation (P )
D
CPU
Frequency
1
2
Die Revision
Bus Mode
Typical
Maximum
Unit
50 MHz
66 MHz
66 Mhz
80 Mhz
100 Mhz
133 Mhz
110
150
140
170
210
260
140
180
160
200
250
320
mW
mW
mW
mW
mW
mW
1:1
0
2:1
1
Typical power dissipation at VDDL and VDDSYN is at 1.8V. and VDDH is at 3.3 V.
10
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
Maximum power dissipation at VDDL and VDDSYN is at 1.9V. and VDDH is at 3.465V.
NOTE
Values in Table 5-5 represent VDDL based power
dissipation and do not include I/O power dissipation
over VDDH. I/O power dissipation varies widely by
application due to buffer current, depending on
external circuitry.
NOTE
The VDDSYN Power Dissipation is negligible.
Part VI DC Characteristics
Table 6-6 provides the DC electrical characteristics for the MPC866/859T/859DSL.
Table 6-6. DC Electrical Specifications
Characteristic
Symbol
VDDL (Core)
Min
Max
Unit
Operating voltage
1.7
1.9
V
VDDH (I/O)
3.135
1.7
-
3.465
1.9
V
1
VDDSYN
V
Difference between
VDDL to VDDSYN
100
mV
Input High Voltage (all inputs except EXTAL and
EXTCLK)
VIH
2.0
3.465
0.8
V
2
Input Low Voltage
VIL
GND
V
EXTAL, EXTCLK Input High Voltage
Input Leakage Current, Vin = 5.5V (Except TMS, TRST,
VIHC
0.7*(VDDH) VDDH
V
I
—
—
—
100
µA
in
In
In
2
DSCK and DSDI pins) for 5 Volts Tolerant Pins
Input Leakage Current, Vin = VDDH (Except TMS, TRST, I
DSCK, and DSDI)
10
µA
µA
Input Leakage Current, Vin = 0V (Except TMS, TRST,
DSCK and DSDI pins)
I
10
3
Input Capacitance
C
—
20
—
pF
V
in
Output High Voltage, IOH = -2.0 mA,
Except XTAL, and Open drain pins
VOH
2.4
Output Low Voltage
VOL
—
0.5
V
IOL = 2.0 mA (CLKOUT)
4
IOL = 3.2 mA
IOL = 5.3 mA
5
IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
IOL = 8.9 mA (TS, TA, TEA, BI, BB, HRESET, SRESET)
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Estimation with Junction-to-Ambient Thermal Resistance
1
The Difference between VDDL and VDDSYN can not be more than 100 mV.
2
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, MII_MDIO are 5V
tolerant.
3
Input capacitance is periodically sampled.
4
A(0:31),TSIZ0/REG,TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1,
L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28,
BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23,
SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14,
L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6,
CTS4/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA, PD14/L1RSYNCA, PD13/L1TSYNCB,
PD12/L1RSYNCB, PD11/RXD3, PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/REJECT2, PD6/RTS4, PD7/RTS3,
PD4/REJECT3, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3].
5
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
Part VII Thermal Calculation and Measurement
For the following discussions, PD= (VDDL x IDDL) + PI/O, where PI/O is the power
dissipation of the I/O drivers.
NOTE
The VDDSYN Power Dissipation is negligible.
7.1 Estimation with Junction-to-Ambient Thermal
Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
TJ = TA +(RθJA x PD)
where:
TA = ambient temperature ºC
RθJA = package junction-to-ambient thermal resistance (ºC/W)
PD = power dissipation in package
The junction-to-ambient thermal resistance is an industry standard value which provides a
quick and easy estimation of thermal performance. However, the answer is only an
estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ-TA)
are possible.
12
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Estimation with Junction-to-Case Thermal Resistance
7.2 Estimation with Junction-to-Case Thermal
Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a
junction-to-case thermal resistance and a case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (ºC/W)
RθJC = junction-to-case thermal resistance (ºC/W)
RθCA = case-to-ambient thermal resistance (ºC/W)
RθJC is device related and cannot be influenced by the user. The user adjusts the thermal
environment to affect the case-to-ambient thermal resistance, RθCA. For instance, the user
can change the air flow around the device, add a heat sink, change the mounting
arrangement on the printed circuit board, or change the thermal dissipation on the printed
circuit board surrounding the device. This thermal model is most useful for ceramic
packages with heat sinks where some 90% of the heat flows through the case and the heat
sink to the ambient environment. For most packages, a better model is required.
7.3 Estimation with Junction-to-Board Thermal
Resistance
A simple package thermal model which has demonstrated reasonable accuracy (about 20%)
is a two resistor model consisting of a junction-to-board and a junction-to-case thermal
resistance. The junction-to-case covers the situation where a heat sink is used or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board
thermal resistance describes the thermal performance when most of the heat is conducted
to the printed circuit board. It has been observed that the thermal performance of most
plastic packages and especially PBGA packages is strongly dependent on the board
temperature; see Figure 7-3.
13
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Estimation Using Simulation
100
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0
0
2 0
4 0
6 0
8 0
Board Temperture Rise Above Ambient Divided by Package
Power
Figure 7-3. Effect of Board Temperature Rise on Thermal Behavior
If the board temperature is known, an estimate of the junction temperature in the
environment can be made using the following equation:
TJ = TB +(RθJB x PD)
where:
RθJB = junction-to-board thermal resistance (ºC/W)
TB = board temperature ºC
PD = power dissipation in package
If the board temperature is known and the heat loss from the package case to the air can be
ignored, acceptable predictions of junction temperature can be made. For this method to
work, the board and board mounting must be similar to the test board used to determine the
junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground
plane) and vias attaching the thermal balls to the ground plane.
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is
needed. The simple two resistor model can be used with the thermal simulation of the
application [2], or a more accurate and complex model of the package can be used in the
thermal simulation.
14
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Experimental Determination
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are
available, the thermal characterization parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using the following equation:
TJ = TT +(ΨJT x PD)
where:
ΨJT = thermal characterization parameter
TT = thermocouple temperature on top of package
PD = power dissipation in package
The thermal characterization parameter is measured per JESD51-2 specification published
by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package
case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about
1 mm of wire extending from the junction. The thermocouple wire is placed flat against the
package case to avoid measurement errors caused by cooling effects of the thermocouple
wire.
7.6 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd
(415) 964-5111
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications
(Available from Global Engineering Documents)
800-854-7179 or
303-397-7956
JEDEC Specifications
http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within
an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego,
1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San
Diego, 1999, pp. 212-220.
15
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Part VIII Power Supply and Power Sequencing
This section provides design considerations for the MPC866/859T/859DSL power supply.
The MPC866/859T/859DSL has a core voltage (VDDL) and PLL voltage (VDDSYN)
which operates at a lower voltage than the I/O voltage VDDH. The I/O section of the
MPC866/859T/859DSL is supplied with 3.3V across VDDH and VSS (GND).
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS,
MII_TXEN, MII_MDIO are 5 V tolerant. All inputs cannot be more than 2.5V greater than
VDDH. In addition, 5 V tolerant pins can not exceed 5.5 V and remaining input pins cannot
exceed 3.465 V. This restriction applies to power up/down and normal operation.
One consequence of multiple power supplies is that when power is initially applied the
voltage rails ramp up at different rates. The rates depend on the nature of the power supply,
the type of load on each power supply, and the manner in which different voltages are
derived. The following restrictions apply:
• VDDL must not exceed VDDH during Power Up and Power Down.
• VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465.
These cautions are necessary for the long term reliability of the part. If they are violated,
the electrostatic discharge (ESD) protection diodes are forward-biased and excessive
current can flow through these diodes. If the system power supply design does not control
the voltage sequencing, the circuit shown in can be added to meet these requirements. The
MUR420 Schottky diodes control the maximum potential difference between the external
bus and core power supplies on power-up and the 1N5820 diodes regulate the maximum
potential difference on power-down.
VDDH
VDDL
MUR420
1N5820
Figure 8-4. Example Voltage Sequencing Circuit
Part IX Layout Practices
Each VDD pin on the MPC866/859T/859DSL should be provided with a low-impedance
path to the board’s supply. Each GND pin should likewise be provided with a
16
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
low-impedance path to ground. The power supply pins drive distinct groups of logic on
chip. The VDD power supply should be bypassed to ground using at least four 0.1 µF
by-pass capacitors located as close as possible to the four sides of the package. Each board
designed should be characterized and additional appropriate decoupling capacitors should
be used if required. The capacitor leads and associated printed circuit traces connecting to
chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should
be used.
All output pins on the MPC866/859T/859DSL have fast rise and fall times. Printed circuit
(PC) trace interconnection length should be minimized in order to minimize undershoot
and reflections caused by these fast output switching times. This recommendation
particularly applies to the address and data busses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing
becomes especially critical in systems with higher capacitive loads because these loads
create higher transient currents in the VDD and GND circuits. Pull up all unused inputs or
signals that will be inputs during reset. Special care should be taken to minimize the noise
levels on the PLL supply pins. For more information, please refer to MPC866 User’s
Manual, Section 14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).
.
Part X Bus Signal Timing
The maximum bus speed supported by the MPC866/859T/859DSL is 66 MHz.
Higher-speed parts must be operated in half-speed bus mode (for example, an
MPC866/859T/859DSL used at 100 MHz must be configured for a 50 MHz bus).
Table 10-7 shows the frequency ranges for standard part frequencies.
Table 10-7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Freq
50MHz
Max
66MHz
Max
Min
Min
Core
Freq
40
50
40
66.67
Bus Freq
40
50
40
66.67
17
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Table 10-8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part Freq
50MHz
Max
66MHz
Max
100MHz
133MHz
Min
Min
Min
Max
Min
Max
Core
Freq
40
50
40
66.67
40
100
40
133.34
BusFreq
20
25
20
33.33
20
50
20
66.67
Table 10-9 provides the timings for the MPC866/859T/859DSL at 33 MHz, 40 Mhz, 50
MHz and 66 Mhz bus operation.
The timing for the MPC866/859T/859DSL bus shown assumes a 50-pF load for maximum
delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum
delay.
Table 10-9. Bus Operation Timings
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1 Bus Period (CLKOUT) See Table 10-7
B1a EXTCLK to CLKOUT phase skew
B1b CLKOUT frequency jitter peak-to-peak
B1c Frequency jitter on EXTCLK
–
-1
–
+1
–
-1
–
+1
–
-1
–
+1
–
-1
–
+1
ns
ns
ns
%
—
1
—
1
—
—
8.0
1
—
—
6.1
1
—
0.50
18.2
—
0.50
15.0
0.50
12.0
0.50
9.1
B2 CLKOUT pulse width low (MIN = 0.4 x
B1, MAX = 0.6 x B1)
12.1
10.0
ns
B3 CLKOUT pulse width high (MIN = 0.4 x 12.1
B1, MAX = 0.6 x B1)
18.2
10.0
15.0
8.0
12.0
6.1
9.1
ns
B4 CLKOUT rise time
B5 CLKOUT fall time
—
—
4.00
4.00
—
—
—
4.00
4.00
—
—
—
4.00
4.00
—
—
—
4.00
4.00
—
ns
ns
ns
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3)
output hold (MIN = 0.25 x B1)
7.60
6.30
5.00
3.80
B7a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3), BDIP, PTR output hold (MIN =
0.25 x B1)
7.60
7.60
–
—
6.30
6.30
–
—
5.00
5.00
–
—
3.80
3.80
–
—
—
ns
ns
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1),
VF(0:2) IWP(0:2), LWP(0:1), STS
output hold (MIN = 0.25 x B1)
—
—
—
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR, BURST, D(0:31), DP(0:3) valid
(MAX = 0.25 x B1 + 6.3)
13.80
13.80
12.50
12.50
11.30
11.30
10.00 ns
10.00 ns
B8a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3) BDIP, PTR valid (MAX = 0.25 x
B1 + 6.3)
–
–
–
–
18
MPC866/859T/859DSLHardwareSpecifications
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MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B8b CLKOUT to BR, BG, VFLS(0:1),
VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS
–
13.80
–
12.50
–
11.30
–
10.00 ns
4
Valid (MAX = 0.25 x B1 + 6.3)
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3),
TSIZ(0:1), REG, RSV, AT(0:3), PTR
High-Z (MAX = 0.25 x B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B11 CLKOUT to TS, BB assertion (MAX =
0.25 x B1 + 6.0)
7.60 13.60 6.30 12.30 5.00 11.00 3.80
9.80
9.80
ns
ns
B11a CLKOUT to TA, BI assertion (when
driven by the memory controller or
2.50
9.30
2.50
9.30
2.50
9.30
2.50
PCMCIA interface) (MAX = 0.00 x B1 +
1
9.30 )
B12 CLKOUT to TS, BB negation (MAX =
0.25 x B1 + 4.8)
7.60 12.30 6.30 11.00 5.00
2.50 9.00 2.50 9.00 2.50
9.80
9.00
3.80
2.50
8.50
9.00
ns
ns
B12a CLKOUT to TA, BI negation (when
driven by the memory controller or
PCMCIA interface) (MAX = 0.00 x B1 +
9.00)
B13 CLKOUT to TS, BB High-Z (MIN = 0.25 7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
x B1)
B13a CLKOUT to TA, BI High-Z (when driven 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
by the memory controller or PCMCIA
interface) (MIN = 0.00 x B1 + 2.5)
B14 CLKOUT toTEA assertion (MAX = 0.00 2.50
x B1 + 9.00)
9.00
2.50
9.00
2.50
9.00
2.50
9.00
ns
B15 CLKOUT to TEA High-Z (MIN = 0.00 x
B1 + 2.50)
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
B16 TA, BI valid to CLKOUT (setup time)
(MIN = 0.00 x B1 + 6.00)
6.00
—
—
—
—
6.00
4.50
4.00
1.00
—
—
—
—
6.00
4.50
4.00
1.00
—
—
—
—
6.00
4.50
4.00
2.00
—
—
—
—
ns
ns
ns
ns
B16a TEA, KR, RETRY, CR valid to CLKOUT 4.50
(setup time) (MIN = 0.00 x B1 + 4.5)
B16b BB, BG, BR, valid to CLKOUT (setup
4.00
2
time) (4MIN = 0.00 x B1 +.00)
B17 CLKOUT to TA, TEA, BI, BB, BG, BR
valid (hold time) (MIN = 0.00 x B1 +
1.00
3
1.00 )
B17a CLKOUT to KR, RETRY, CR valid (hold 2.00
time) (MIN = 0.00 x B1 + 2.00)
—
—
2.00
6.00
—
—
2.00
6.00
—
—
2.00
6.00
—
—
ns
ns
B18 D(0:31), DP(0:3) valid to CLKOUT
6.00
4
rising edge (setup time) (MIN = 0.00 x
B1 + 6.00)
19
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B19 CLKOUT rising edge to D(0:31),
1.00
4.00
2.00
—
1.00
4.00
2.00
—
1.00
4.00
2.00
—
2.00
4.00
2.00
—
ns
4
DP(0:3) valid (hold time) (MIN = 0.00 x
5
B1 + 1.00 )
B20 D(0:31), DP(0:3) valid to CLKOUT
—
—
—
—
—
—
—
—
ns
ns
6
falling edge (setup time) (MIN = 0.00 x
B1 + 4.00)
B21 CLKOUT falling edge to D(0:31),
6
DP(0:3) valid (hold Time) (MIN = 0.00
x B1 + 2.00)
B22 CLKOUT rising edge to CS asserted
GPCM ACS = 00 (MAX = 0.25 x B1 +
6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
B22a CLKOUT falling edge to CS asserted
GPCM ACS = 10, TRLX = 0 (MAX =
0.00 x B1 + 8.00)
—
8.00
—
8.00
—
8.00
—
8.00
ns
B22b CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 x B1 + 6.3)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
B22c CLKOUT falling edge to CS asserted
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 x B1 + 6.6)
B23 CLKOUT rising edge to CS negated
GPCM read access, GPCM write
access ACS = 00, TRLX = 0 & CSNT =
0 (MAX = 0.00 x B1 + 8.00)
2.00
8.00
2.00
8.00
2.00
8.00
2.00
8.00
ns
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 x B1 - 2.00)
5.60
—
—
4.30
—
—
3.00
8.00
—
—
1.80
5.60
—
—
ns
ns
B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11 TRLX = 0
(MIN = 0.50 x B1 - 2.00)
13.20
10.50
B25 CLKOUT rising edge to OE, WE(0:3)
asserted (MAX = 0.00 x B1 + 9.00)
—
9.00
9.00
—
9.00
9.00
—
9.00
9.00
—
9.00
9.00
—
ns
ns
ns
B26 CLKOUT rising edge to OE negated
(MAX = 0.00 x B1 + 9.00)
2.00
35.90
2.00
2.00
2.00
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 x B1 - 2.00)
29.30
23.00
16.90
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 x B1 - 2.00)
43.50
—
—
35.50
—
—
28.00
—
—
20.70
—
—
ns
ns
B28 CLKOUT rising edge to WE(0:3)
negated GPCM write access CSNT = 0
(MAX = 0.00 x B1 + 9.00)
9.00
9.00
9.00
9.00
20
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B28a CLKOUT falling edge to WE(0:3)
negated GPCM write access TRLX = 0,
CSNT = 1, EBDF = 0 (MAX = 0.25 x B1
+ 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B28b CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT =
1 ACS = 10 or ACS = 11, EBDF = 0
(MAX = 0.25 x B1 + 6.80)
—
14.30
—
13.00
—
11.80
—
10.50 ns
B28c CLKOUT falling edge to WE(0:3)
negated GPCM write access TRLX = 0,
CSNT = 1 write access TRLX = 0,
CSNT = 1, EBDF = 1 (MAX = 0.375 x B1
+ 6.6)
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
B28d CLKOUT falling edge to CS negated
GPCM write access TRLX = 0, CSNT =
1, ACS = 10, or ACS = 11, EBDF = 1
(MAX = 0.375 x B1 + 6.6)
—
18.00
—
18.00
—
14.30
—
12.30 ns
B29 WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, CSNT = 0,
EBDF = 0 (MIN = 0.25 x B1 - 2.00)
5.60
—
—
4.30
—
—
3.00
8.00
—
—
1.80
5.60
—
—
ns
ns
B29a WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0 (MIN = 0.50 x B1
- 2.00)
13.20
10.50
B29b CS negated to D(0:31), DP(0:3), High Z 5.60
GPCM write access, ACS = 00, TRLX =
—
—
4.30
—
—
3.00
8.00
—
—
1.80
5.60
—
—
ns
ns
0 & CSNT = 0 (MIN = 0.25 x B1 - 2.00)
B29c CS negated to D(0:31), DP(0:3) High-Z 13.20
GPCM write access, TRLX = 0, CSNT =
1, ACS = 10, or ACS = 11 EBDF = 0
(MIN = 0.50 x B1 - 2.00)
10.50
B29d WE(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0 (MIN = 1.50 x B1
- 2.00)
43.50
—
—
—
35.50
35.50
3.00
—
—
—
28.00
28.00
1.10
—
—
—
20.70
20.70
0.00
—
—
—
ns
ns
ns
B29e CS negated to D(0:31), DP(0:3) High-Z 43.50
GPCM write access, TRLX = 1, CSNT =
1, ACS = 10, or ACS = 11 EBDF = 0
(MIN = 1.50 x B1 - 2.00)
B29f WE(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B1
- 6.30)
5.00
21
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B29g CS negated to D(0:31), DP(0:3) High-Z 5.00
GPCM write access, TRLX = 0, CSNT =
1 ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 x B1 - 6.30)
—
3.00
31.10
31.10
—
1.10
24.20
24.20
—
0.00
17.50
17.50
—
ns
B29h WE(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1 (MIN = 0.375 x B1
- 3.30)
38.40
—
—
—
—
—
—
—
—
ns
ns
B29i CS negated to D(0:31), DP(0:3) High-Z 38.40
GPCM write access, TRLX = 1, CSNT =
1, ACS = 10 or ACS = 11, EBDF = 1
(MIN = 0.375 x B1 - 3.30)
B30 CS, WE(0:3) negated to A(0:31),
BADDR(28:30) Invalid GPCM write
5.60
—
—
4.30
—
—
3.00
8.00
—
—
1.80
5.60
—
—
ns
ns
7
access (MIN = 0.25 x B1 - 2.00)
B30a WE(0:3) negated to A(0:31),
BADDR(28:30) Invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 0, CSNT =1 ACS = 10,
or ACS == 11, EBDF = 0 (MIN = 0.50 x
B1 - 2.00)
13.20
10.50
B30b WE(0:3) negated to A(0:31) Invalid
GPCM BADDR(28:30) invalid GPCM
write access, TRLX = 1, CSNT = 1. CS
negated to A(0:31) Invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10,
or ACS == 11 EBDF = 0 (MIN = 1.50 x
B1 - 2.00)
43.50
—
—
35.50
—
—
28.00
—
—
20.70
—
—
ns
ns
B30c WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS
negated to A(0:31) invalid GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10,
ACS == 11, EBDF = 1 (MIN = 0.375 x
B1 - 3.00)
8.40
6.40
4.50
2.70
B30d WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access TRLX = 1, CSNT =1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10
or 11, EBDF = 1
38.67
1.50
—
31.38
1.50
—
24.50
1.50
—
17.83
1.50
—
ns
ns
B31 CLKOUT falling edge to CS valid - as
requested by control bit CST4 in the
corresponding word in the UPM (MAX =
0.00 X B1 + 6.00)
6.00
6.00
6.00
6.00
22
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B31a CLKOUT falling edge to CS valid - as
requested by control bit CST1 in the
corresponding word in the UPM (MAX =
0.25 x B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B31b CLKOUT rising edge to CS valid - as
requested by control bit CST2 in the
corresponding word in the UPM (MAX =
0.00 x B1 + 8.00)
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B31c CLKOUT rising edge to CS valid- as
requested by control bit CST3 in the
corresponding word in the UPM (MAX =
0.25 x B1 + 6.30)
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B31d CLKOUT falling edge to CS valid, as
requested by control bit CST1 in the
corresponding word in the UPM EBDF
= 1 (MAX = 0.375 x B1 + 6.6)
B32 CLKOUT falling edge to BS valid- as
requested by control bit BST4 in the
corresponding word in the UPM (MAX =
0.00 x B1 + 6.00)
1.50
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B32a CLKOUT falling edge to BS valid - as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 0 (MAX = 0.25 x B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
B32b CLKOUT rising edge to BS valid - as
requested by control bit BST2 in the
corresponding word in the UPM (MAX =
0.00 x B1 + 8.00)
1.50
8.00
1.50
8.00
1.50
8.00
1.50
8.00
ns
B32c CLKOUT rising edge to BS valid - as
requested by control bit BST3 in the
corresponding word in the UPM (MAX =
0.25 x B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
B32d CLKOUT falling edge to BS valid- as
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 1 (MAX = 0.375 x B1 + 6.60)
B33 CLKOUT falling edge to GPL valid - as 1.50
requested by control bit GxT4 in the
corresponding word in the UPM (MAX =
0.00 x B1 + 6.00)
6.00
1.50
6.00
1.50
6.00
1.50
6.00
ns
B33a CLKOUT rising edge to GPL Valid - as
requested by control bit GxT3 in the
corresponding word in the UPM (MAX =
0.25 x B1 + 6.80)
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
23
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Num
Table 10-9. Bus Operation Timings (continued)
33 MHz
40 MHz
50 MHz
66 MHz
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B34 A(0:31), BADDR(28:30), and D(0:31) to 5.60
CS valid - as requested by control bit
CST4 in the corresponding word in the
UPM (MIN = 0.25 x B1 - 2.00)
—
4.30
10.50
16.70
4.30
—
3.00
—
1.80
5.60
9.40
1.80
5.60
9.40
1.80
—
ns
B34a A(0:31), BADDR(28:30), and D(0:31) to 13.20
CS valid - as requested by control bit
CST1 in the corresponding word in the
UPM (MIN = 0.50 x B1 - 2.00)
—
—
—
—
—
—
—
—
—
—
—
—
8.00
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
B34b A(0:31), BADDR(28:30), and D(0:31) to 20.70
CS valid - as requested by CST2 in the
corresponding word in UPM (MIN =
0.75 x B1 - 2.00)
13.00
3.00
B35 A(0:31), BADDR(28:30) to CS valid - as 5.60
requested by control bit BST4 in the
corresponding word in the UPM (MIN =
0.25 x B1 - 2.00)
B35a A(0:31), BADDR(28:30), and D(0:31) to 13.20
BS valid - As Requested by BST1 in the
corresponding word in the UPM (MIN =
0.50 x B1 - 2.00)
10.50
16.70
4.30
8.00
B35b A(0:31), BADDR(28:30), and D(0:31) to 20.70
BS valid - as requested by control bit
BST2 in the corresponding word in the
UPM (MIN = 0.75 x B1 - 2.00)
13.00
3.00
B36 A(0:31), BADDR(28:30), and D(0:31) to 5.60
GPL valid as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 x B1 - 2.00)
8
B37 UPWAIT valid to CLKOUT falling edge
(MIN = 0.00 x B1 + 6.00)
6.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
6.00
1.00
7.00
7.00
—
—
—
—
ns
ns
ns
ns
8
B38 CLKOUT falling edge to UPWAIT valid
(MIN = 0.00 x B1 + 1.00)
1.00
9
B39 AS valid to CLKOUT rising edge (MIN 7.00
= 0.00 x B1 + 7.00)
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge (MIN =
0.00 x B1 + 7.00)
7.00
B41 TS valid to CLKOUT rising edge (setup 7.00
time) (MIN = 0.00 x B1 + 7.00)
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
7.00
2.00
—
—
—
ns
ns
ns
B42 CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00 x B1 + 2.00)
2.00
B43 AS negation to memory controller
signals negation (MAX = TBD)
—
TBD
TBD
TBD
TBD
1
For part speeds above 50MHz, use 9.80ns for B11a.
24
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
2
The timing required for BR input is relevant when the MPC866/859T/859DSL is selected to work with internal bus
arbiter. The timing for BG input is relevant when the MPC866/859T/859DSL is selected to work with external bus
arbiter.
3
For part speeds above 50MHz, use 2ns for B17.
4
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
5
For part speeds above 50MHz, use 2ns for B19.
6
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
7
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 10-20.
9
The AS signal is considered asynchronous to the CLKOUT.The timing B39 is specified in order to allow the behavior
specified in Figure 10-23.
Figure 10-5 is the control timing diagram.
2.0 V
2.0 V
CLKOUT
Outputs
Outputs
Inputs
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
Inputs
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 10-5. Control Timing
25
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
Figure 10-6 provides the timing for the external clock.
CLKOUT
B1
B3
B1
B2
B4
B5
Figure 10-6. External Clock Timing
Figure 10-7 provides the timing for the synchronous output signals.
CLKOUT
B8
B7
B9
B9
Output
Signals
B8a
B8b
B7a
B7b
Output
Signals
Output
Signals
Figure 10-7. Synchronous Output Signals Timing
Figure 10-8 provides the timing for the synchronous active pull-up and open-drain output
signals.
26
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B13
B11
B12
B12a
B15
TS, BB
TA, BI
TEA
B13a
B11a
B14
Figure 10-8. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals
Timing
Figure 10-9 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
TA, BI
B16a
B17a
TEA, KR,
RETRY, CR
B16b
B17
BB, BG, BR
Figure 10-9. Synchronous Input Signals Timing
Figure 10-10 provides normal case timing for input data. It also applies to normal read
accesses under the control of the UPM in the memory controller.
27
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B16
B18
B17
B19
TA
D[0:31],
DP[0:3]
Figure 10-10. Input Data Timing in Normal Case
Figure 10-11 provides the timing for the input data controlled by the UPM for data beats
where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on
the falling edge of CLKOUT.)
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 10-11. Input DataTiming when Controlled by UPM in the Memory Controller
and DLT3 = 1
Figure 10-12 through Figure 10-15 provide the timing for the external bus read controlled
by various GPCM factors.
28
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22
B23
B25
B26
OE
B28
WE[0:3]
B19
B18
D[0:31],
DP[0:3]
Figure 10-12. External Bus Read Timing (GPCM Controlled—ACS = 00)
29
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B23
B22a
B24
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 10-13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B22b
B22c
B23
B24a
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 10-14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
30
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B11
B12
TS
A[0:31]
CSx
B8
B23
B22a
B27
B26
B19
OE
B27a
B22b B22c
B18
D[0:31],
DP[0:3]
Figure 10-15. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10,
ACS = 11)
31
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Figure 10-16 through Figure 10-18 provide the timing for the external bus write controlled
by various GPCM factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B30
B22
B23
B25
B28
WE[0:3]
OE
B26
B29b
B29
B8
B9
D[0:31],
DP[0:3]
Figure 10-16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
32
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B30a B30c
B22
B28b B28d
B23
B25
B29c B29g
WE[0:3]
OE
B26
B29a B29f
B28a B28c
B8
B9
D[0:31],
DP[0:3]
Figure 10-17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
33
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B11
B12
TS
A[0:31]
CSx
B8
B30b B30d
B22
B28b B28d
B23
B25
B29e B29i
B29d B29h
WE[0:3]
OE
B26
B29b
B8
B28a B28c
B9
D[0:31],
DP[0:3]
Figure 10-18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
Figure 10-19 provides the timing for the external bus controlled by the UPM.
34
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31
B31b
CSx
B34
B34a
B34b
B32a B32d
B32c
B32
B32b
BS_A[0:3],
BS_B[0:3]
B35 B36
B35b
B35a
B33a
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 10-19. External Bus Timing (UPM Controlled Signals)
Figure 10-20 provides the timing for the asynchronous asserted UPWAIT signal controlled
by the UPM.
35
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B37
UPWAIT
CSx
B38
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 10-20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles
Timing
Figure 10-21 provides the timing for the asynchronous negated UPWAIT signal controlled
by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 10-21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles
Timing
Figure 10-22 provides the timing for the synchronous external master access controlled by
the GPCM.
36
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
B41
B40
B42
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 10-22. Synchronous External Master AccessTiming (GPCM Handled ACS =
00)
Figure 10-23 provides the timing for the asynchronous external master memory access
controlled by the GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 10-23. Asynchronous External Master Memory Access Timing (GPCM
Controlled—ACS = 00)
Figure 10-24 provides the timing for the asynchronous external master control signals
negation.
37
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 10-24. Asynchronous External Master—Control Signals Negation Timing
Table 10-10 provides interrupt timing for the MPC866/859T/859DSL.
Table 10-10. Interrupt Timing
All Frequencies
1
Num
Characteristic
Unit
Min
Max
I39 IRQx valid to CLKOUT rising edge (set 6.00
up time)
ns
I40 IRQx hold time after CLKOUT
I41 IRQx pulse width low
2.00
3.00
3.00
ns
ns
ns
—
I42 IRQx pulse width high
I43 IRQx edge-to-edge time
4xT
CLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ
lines are tested when being defined as level sensitive. The IRQ lines are
synchronized internally and do not have to be asserted or negated with
reference to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the
IRQ lines detection circuitry, and has no direct relation with the total system
interrupt latency that the MPC866/859T/859DSL is able to support.
Figure 10-25 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 10-25. Interrupt Detection Timing for External Level Sensitive Lines
Figure 10-26 provides the interrupt detection timing for the external edge-sensitive lines.
38
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
I41
I42
IRQx
I43
I43
Figure 10-26. Interrupt Detection Timing for External Edge Sensitive Lines
Table 10-11 shows the PCMCIA timing for the MPC866/859T/859DSL.
Table 10-11. PCMCIA Timing
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Min Max
Num
Characteristic
Unit
A(0:31), REG valid to PCMCIA Strobe 20.70
asserted. (MIN = 0.75 x B1 - 2.00)
—
16.70
—
13.00
—
9.40
—
ns
ns
P44
P45
P46
P47
P48
P49
1
1
A(0:31), REG valid to ALE negation. 28.30
—
23.00
—
18.00
—
13.20
—
(MIN = 1.00 x B1 - 2.00)
CLKOUT to REG valid (MAX = 0.25 x 7.60
B1 + 8.00)
15.60 6.30
7.30
14.30 5.00
6.00
13.00 3.80
4.80
11.80 ns
— ns
CLKOUT to REG Invalid. (MIN = 0.25 8.60
x B1 + 1.00)
—
—
—
CLKOUT to CE1, CE2 asserted.
(MAX = 0.25 x B1 + 8.00)
7.60
15.60 6.30
15.60 6.30
14.30 5.00
14.30 5.00
13.00 3.80
13.00 3.80
11.80 ns
11.80 ns
11.00 ns
CLKOUT to CE1, CE2 negated. (MAX 7.60
= 0.25 x B1 + 8.00)
CLKOUT to PCOE, IORD, PCWE,
—
11.00
—
11.00
—
11.00
—
P50 IOWR assert time. (MAX = 0.00 x B1
+ 11.00)
CLKOUT to PCOE, IORD, PCWE,
P51 IOWR negate time. (MAX = 0.00 x B1
+ 11.00)
2.00
11.00 2.00
13.80 6.30
11.00 2.00
12.50 5.00
11.00 2.00
11.30 3.80
11.00 ns
CLKOUT to ALE assert time (MAX = 7.60
0.25 x B1 + 6.30)
10.00 ns
11.80 ns
P52
P53
P54
P55
CLKOUT to ALE negate time (MAX = —
0.25 x B1 + 8.00)
15.60
—
—
14.30
—
—
13.00
—
—
PCWE, IOWR negated to D(0:31)
5.60
4.30
8.00
2.00
3.00
8.00
2.00
1.80
8.00
2.00
—
—
—
ns
ns
ns
1
invalid. (MIN = 0.25 x B1 - 2.00)
WAITA and WAITB valid to CLKOUT 8.00
—
—
—
1
rising edge. (MIN = 0.00 x B1 + 8.00)
CLKOUT rising edge to WAITA and
2.00
—
—
—
1
P56 WAITB invalid. (MIN = 0.00 x B1 +
2.00)
39
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
PCMCIA Interface in the MPC866 PowerQUICC User s Manual.
Figure 10-27 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
REG
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
B19
D[0:31]
Figure 10-27. PCMCIA Access Cycles Timing External Bus Read
Figure 10-28 provides the PCMCIA access cycle timing for the external bus write.
40
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
TS
A[0:31]
P44
P45
P46
P48
P47
P49
P51
P52
B9
REG
CE1/CE2
PCWE, IOWR
ALE
P50
P53
B8
P54
P52
D[0:31]
Figure 10-28. PCMCIA Access Cycles Timing External Bus Write
Figure 10-29 provides the PCMCIA WAIT signals detection timing.
CLKOUT
P55
P56
WAITx
Figure 10-29. PCMCIA WAIT Signals Detection Timing
Table 10-12 shows the PCMCIA port timing for the MPC866/859T/859DSL.
41
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Table 10-12. PCMCIA Port Timing
33 MHz
Min Max
40 MHz
Min Max
50 MHz
Min Max
66 MHz
Num
Characteristic
Unit
Min
Max
CLKOUT to OPx Valid (MAX = 0.00 x B1 —
+ 19.00)
19.00
—
19.00
—
19.00
—
19.00 ns
P57
P58
P59
P60
1
HRESET negated to OPx drive (MIN = 25.70
—
21.70
5.00
1.00
—
18.00
5.00
1.00
—
14.40
5.00
1.00
—
—
—
ns
ns
ns
0.75 x B1 + 3.00)
IP_Xx valid to CLKOUT rising edge (MIN 5.00
= 0.00 x B1 + 5.00)
—
—
—
CLKOUT rising edge to IP_Xx invalid
(MIN = 0.00 x B1 + 1.00)
1.00
—
—
—
1
OP2 and OP3 only.
Figure 10-30 provides the PCMCIA output port timing for the MPC866/859T/859DSL.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 10-30. PCMCIA Output Port Timing
Figure 10-31 provides the PCMCIA output port timing for the MPC866/859T/859DSL.
CLKOUT
P59
P60
Input
Signals
Figure 10-31. PCMCIA Input Port Timing
Table 10-13 shows the debug port timing for the MPC866/859T/859DSL.
42
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Table 10-13. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
D61
DSCK cycle time
3xT
-
-
CLOCKOUT
D62
D63
D64
D65
D66
D67
DSCK clock pulse width
DSCK rise and fall times
DSDI input data setup time
DSDI data hold time
1.25xT
0.00
8.00
5.00
0.00
0.00
CLOCKOUT
3.00
ns
ns
ns
DSCK low to DSDO data valid
DSCK low to DSDO invalid
15.00 ns
2.00 ns
Figure 10-32 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
D63
Figure 10-32. Debug Port Clock Input Timing
Figure 10-33 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 10-33. Debug Port Timings
43
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
Table 10-14 shows the reset timing for the MPC866/859T/859DSL.
Table 10-14. Reset Timing
33 MHz
40 MHz
50 MHz
66 MHz
Num
Characteristic
Unit
Min
Max
Min
Max
Min
Max
Min
Max
CLKOUT to HRESET high impedance
(MAX = 0.00 x B1 + 20.00)
—
20.00
—
20.00
—
20.00
—
20.00 ns
R69
R70
CLKOUT to SRESET high impedance
(MAX = 0.00 x B1 + 20.00)
—
20.00
—
20.00
—
20.00
—
20.00 ns
R71 RSTCONF pulse width (MIN = 17.00 x B1) 515.20
—
—
—
425.00
—
—
—
—
340.00
—
—
—
—
257.60
—
—
—
—
ns
—
ns
R72
R73
—
—
Configuration data to HRESET rising edge 504.50
set up time (MIN = 15.00 x B1 + 50.00)
425.00
350.00
277.30
Configuration data to RSTCONF rising
edge set up time (MIN = 0.00 x B1 + 350.00)
350.00
—
—
350.00
0.00
—
—
350.00
0.00
—
—
350.00
0.00
—
—
ns
ns
R74
Configuration data hold time after
0.00
R75 RSTCONF negation (MIN = 0.00 x B1 +
0.00)
Configuration data hold time after HRESET 0.00
negation (MIN = 0.00 x B1 + 0.00)
—
0.00
—
—
0.00
—
—
0.00
—
—
ns
R76
R77
R78
HRESET and RSTCONF asserted to data
out drive (MAX = 0.00 x B1 + 25.00)
—
—
—
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00 ns
25.00 ns
25.00 ns
RSTCONF negated to data out high
impedance. (MAX = 0.00 x B1 + 25.00)
—
—
—
CLKOUT of last rising edge before chip
—
—
—
R79 three-states HRESET to data out high
impedance. (MAX = 0.00 x B1 + 25.00)
R80 DSDI, DSCK set up (MIN = 3.00 x B1)
90.90
—
—
75.00
0.00
—
—
60.00
0.00
—
—
45.50
0.00
—
—
ns
ns
DSDI, DSCK hold time (MIN = 0.00 x B1 + 0.00
0.00)
R81
SRESET negated to CLKOUT rising edge 242.40
—
200.00
—
160.00
—
121.20
—
ns
R82 for DSDI and DSCK sample (MIN = 8.00 x
B1)
Figure 10-34 shows the reset timing for the data bus configuration.
44
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
HRESET
R71
R76
RSTCONF
D[0:31] (IN)
R73
R74
R75
Figure 10-34. Reset Timing—Configuration from Data Bus
Figure 10-35 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 10-35. Reset Timing—Data Bus Weak Drive during Configuration
Figure 10-36 provides the reset timing for the debug port configuration.
45
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
References
CLKOUT
R70
R82
R80
SRESET
R80
R81
R81
DSCK, DSDI
Figure 10-36. Reset Timing—Debug Port Configuration
Part XI IEEE 1149.1 Electrical Specifications
Table 11-15 provides the JTAG timings for the MPC866/859T/859DSL shown in
Figure 11-37 to Figure 11-40.
Table 11-15. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82
TCK cycle time
100.00
40.00
0.00
5.00
25.00
—
—
ns
ns
10.00 ns
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
—
TMS, TDI data setup time
—
—
ns
ns
TMS, TDI data hold time
TCK low to TDO data valid
27.00 ns
ns
20.00 ns
TCK low to TDO data invalid
0.00
—
—
TCK low to TDO high impedance
TRST assert time
100.00
40.00
—
—
—
ns
ns
TRST setup time to TCK low
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
50.00 ns
50.00 ns
50.00 ns
—
—
50.00
50.00
—
—
ns
ns
46
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
References
TCK
J82
J83
J82
J83
J84
J84
Figure 11-37. JTAG Test Clock Input Timing
TCK
J85
J86
TMS, TDI
J87
J88
J89
TDO
Figure 11-38. JTAG Test Access Port Timing Diagram
TCK
J91
J90
TRST
Figure 11-39. JTAG TRST Timing Diagram
47
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PIP/PIO AC Electrical Specifications
TCK
J92
J93
J94
Output
Signals
Output
Signals
J95
J96
Output
Signals
Figure 11-40. Boundary Scan (JTAG) Timing Diagram
Part XII CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications
processor module (CPM) of the MPC866/859T/859DSL.
12.1 PIP/PIO AC Electrical Specifications
Table 12-16 provides the PIP/PIO AC timings as shown in Figure 12-41 to Figure 12-45.
Table 12-16. PIP/PIO Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
21 Data-in setup time to STBI low
22 Data-In hold time to STBI high
23 STBI pulse width
0
—
ns
1
2.5 – t3
—
—
—
—
—
2
clk
clk
ns
clk
clk
clk
clk
ns
ns
ns
1.5
24 STBO pulse width
1 clk – 5ns
25 Data-out setup time to STBO low
26 Data-out hold time from STBO high
27 STBI low to STBO low (Rx interlock)
28 STBI low to STBO high (Tx interlock)
29 Data-in setup time to clock high
30 Data-in hold time from clock high
31 Clock low to data-out valid (CPU writes data, control, or direction)
t3 = Specification 23
2
5
—
2
—
—
—
25
15
7.5
—
1
48
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PIP/PIO AC Electrical Specifications
DATA-IN
21
22
23
STBI
27
24
STBO
Figure 12-41. PIP Rx (Interlock Mode) Timing Diagram
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 12-42. PIP Tx (Interlock Mode) Timing Diagram
DATA-IN
21
22
23
24
STBI
(Input)
STBO
(Output)
Figure 12-43. PIP Rx (Pulse Mode) Timing Diagram
49
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Port C Interrupt AC Electrical Specifications
DATA-OUT
25
26
24
23
STBO
(Output)
STBI
(Input)
Figure 12-44. PIP TX (Pulse Mode) Timing Diagram
CLKO
DATA-IN
29
30
31
DATA-OUT
Figure 12-45. Parallel I/O Data-In/Data-Out Timing Diagram
12.2 Port C Interrupt AC Electrical Specifications
Table 12-17 provides the timings for port C interrupts.
Table 12-17. Port C Interrupt Timing
33.34 MHz
Num
Characteristic
Unit
Min
Max
35
36
Port C interrupt pulse width low (edge-triggered mode)
Port C interrupt minimum time between active edges
55
55
—
—
ns
ns
50
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
IDMA Controller AC Electrical Specifications
Figure 12-46 shows the port C interrupt detection timing.
36
Port C
(Input)
35
Figure 12-46. Port C Interrupt Detection Timing
12.3 IDMA Controller AC Electrical Specifications
Table 12-18 provides the IDMA controller timings as shown in Figure 12-47 to
Figure 12-50.
Table 12-18. IDMA Controller Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
40
DREQ setup time to clock high
7
—
—
12
12
20
15
—
ns
41
42
43
44
45
46
DREQ hold time from clock high
3
ns
ns
ns
ns
ns
ns
SDACK assertion delay from clock high
SDACK negation delay from clock low
—
—
—
—
7
SDACK negation delay from TA low
SDACK negation delay from clock high
TA assertion to falling edge of the clock setup time (applies to external TA)
CLKO
(Output)
41
40
DREQ
(Input)
Figure 12-47. IDMA External Requests Timing Diagram
51
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IDMA Controller AC Electrical Specifications
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Input)
SDACK
Figure 12-48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 12-49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
52
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Baud Rate Generator AC Electrical Specifications
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 12-50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
12.4 Baud Rate Generator AC Electrical Specifications
Table 12-19 provides the baud rate generator timings as shown in Figure 12-51.
Table 12-19. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
10
50
BRGO rise and fall time
—
40
40
ns
51
52
BRGO duty cycle
BRGO cycle
60
—
%
ns
50
50
BRGOX
51
51
52
Figure 12-51. Baud Rate Generator Timing Diagram
53
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Timer AC Electrical Specifications
12.5 Timer AC Electrical Specifications
Table 12-20 provides the general-purpose timer timings as shown in Figure 12-52.
Table 12-20. Timer Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
61
TIN/TGATE rise and fall time
TIN/TGATE low time
10
1
—
ns
62
63
64
65
—
—
—
25
clk
clk
clk
ns
TIN/TGATE high time
TIN/TGATE cycle time
CLKO low to TOUT valid
2
3
3
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 12-52. CPM General-Purpose Timers Timing Diagram
12.6 Serial Interface AC Electrical Specifications
Table 12-21 provides the serial interface timings as shown in Figure 12-53 to Figure 12-57.
Table 12-21. SI Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1, 2
70
L1RCLK, L1TCLK frequency (DSC = 0)
L1RCLK, L1TCLK width low (DSC = 0)
L1RCLK, L1TCLK width high (DSC = 0)
—
SYNCCLK/2.5
MHz
2
71
P + 10
P + 10
—
—
ns
ns
ns
ns
3
71a
72
—
L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time
15.00
—
73
L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC 20.00
setup time)
54
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
Table 12-21. SI Timing (continued)
All Frequencies
Max
Num
Characteristic
Unit
Min
74
L1CLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
35.00
—
ns
75
76
77
78
78A
79
80
80A
81
82
83
83a
84
85
86
87
88
L1RSYNC, L1TSYNC rise/fall time
—
15.00
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
L1RXD valid to L1CLK edge (L1RXD setup time)
17.00
L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00
—
4
L1CLK edge to L1ST(1–4) valid
L1SYNC valid to L1ST(1–4) valid
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
10.00
10.00
10.00
10.00
10.00
0.00
45.00
45.00
45.00
55.00
55.00
42.00
4
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)
—
16.00 or SYNCCLK/2
MHz
ns
P + 10
P + 10
—
—
3
—
ns
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
30.00
—
ns
4
1.00
L1TCLK
ns
2
L1GR setup time
42.00
42.00
—
—
L1GR hold time
—
ns
L1CLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
0.00
ns
1
2
3
4
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
55
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
L1RCLK
(FE=0, CE=0)
(Input)
71
70
71a
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
Figure 12-53. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
56
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
L1RCLK
(FE=1, CE=1)
(Input)
72
83a
82
L1RCLK
(FE=0, CE=0)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
74
77
L1RXD
(Input)
BIT0
76
78
79
L1ST(4-1)
(Output)
84
L1CLKO
(Output)
Figure 12-54. SI Receive Timing with Double-Speed Clocking (DSC = 1)
57
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
L1TCLK
(FE=0, CE=0)
(Input)
71
70
72
L1TCLK
(FE=1, CE=1)
(Input)
73
TFSD=0
75
74
L1TSYNC
(Input)
80a
BIT0
80
81
L1TXD
(Output)
79
78
L1ST(4-1)
(Output)
Figure 12-55. SI Transmit Timing Diagram (DSC = 0)
58
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
L1RCLK
(FE=0, CE=0)
(Input)
72
82
83a
L1RCLK
(FE=1, CE=1)
(Input)
TFSD=0
75
L1RSYNC
(Input)
73
74
81
L1TXD
(Output)
BIT0
80
78a
79
L1ST(4-1)
(Output)
78
84
L1CLKO
(Output)
Figure 12-56. SI Transmit Timing with Double Speed Clocking (DSC = 1)
59
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Serial Interface AC Electrical Specifications
Figure 12-57. IDL Timing
60
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SCC in NMSI Mode Electrical Specifications
12.7 SCC in NMSI Mode Electrical Specifications
Table 12-22 provides the NMSI external clock timing.
Table 12-22. NMSI External Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1
100
101
102
103
104
105
106
107
108
RCLK1 and TCLK1 width high
1/SYNCCLK
—
ns
ns
RCLK1 and TCLK1 width low
1/SYNCCLK +5
—
RCLK1 and TCLK1 rise/fall time
—
15.00 ns
50.00 ns
50.00 ns
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
—
—
—
—
ns
ns
ns
ns
2
RXD1 hold time from RCLK1 rising edge
CD1 setup Time to RCLK1 rising edge
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as an external sync signal.
Table 12-23 provides the NMSI internal clock timing.
Table 12-23. NMSI Internal Clock Timing
All Frequencies
Num
Characteristic
Unit
Min
0.00
Max
1
100
RCLK1 and TCLK1 frequency
SYNCCLK/3 MHz
102
103
104
105
106
107
108
RCLK1 and TCLK1 rise/fall time
—
—
ns
ns
ns
ns
ns
ns
ns
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
0.00
0.00
40.00
40.00
0.00
40.00
30.00
30.00
—
—
2
RXD1 hold time from RCLK1 rising edge
—
CD1 setup time to RCLK1 rising edge
—
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
Also applies to CD and CTS hold time when they are used as an external sync signals.
Figure 12-58 through Figure 12-60 show the NMSI timings.
61
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SCC in NMSI Mode Electrical Specifications
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 12-58. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 12-59. SCC NMSI Transmit Timing Diagram
62
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Ethernet Electrical Specifications
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 12-60. HDLC Bus Timing Diagram
12.8 Ethernet Electrical Specifications
Table 12-24 provides the Ethernet timings as shown in Figure 12-61 to Figure 12-65.
Table 12-24. Ethernet Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
120
CLSN width high
RCLK1 rise/fall time
RCLK1 width low
RCLK1 clock period
RXD1 setup time
RXD1 hold time
40
—
40
80
20
5
—
15
—
ns
121
122
123
124
125
126
127
128
129
130
131
132
133
134
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
120
—
—
RENA active delay (from RCLK1 rising edge of the last data bit) 10
—
RENA width low
100
—
TCLK1 rise/fall time
TCLK1 width low
TCLK1 clock period
—
40
99
–
15
—
1
101
50
50
50
50
TXD1 active delay (from TCLK1 rising edge)
TXD1 inactive delay (from TCLK1 rising edge)
TENA active delay (from TCLK1 rising edge)
TENA inactive delay (from TCLK1 rising edge)
6.5
10
10
63
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Ethernet Electrical Specifications
Table 12-24. Ethernet Timing (continued)
All Frequencies
Min Max
Num
Characteristic
Unit
135
RSTRT active delay (from TCLK1 falling edge)
RSTRT inactive delay (from TCLK1 falling edge)
REJECT width low
10
10
1
50
50
—
20
20
ns
136
137
138
139
ns
CLK
ns
2
CLKO1 low to SDACK asserted
—
—
2
CLKO1 low to SDACK negated
ns
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 12-61. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 12-62. Ethernet Receive Timing Diagram
64
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Ethernet Electrical Specifications
TCLK1
128
131
128
129
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 12-63. Ethernet Transmit Timing Diagram
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame Delimiter
RSTRT
(Output)
Figure 12-64. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 12-65. CAM Interface REJECT Timing Diagram
65
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SMC Transparent AC Electrical Specifications
12.9 SMC Transparent AC Electrical Specifications
Table 12-25 provides the SMC transparent timings as shown in Figure 12-66.
Table 12-25. SMC Transparent Timing
All Frequencies
Num
Characteristic
Unit
Min
100
Max
1
150
SMCLK clock period
—
ns
151
151A
152
153
154
155
SMCLK width low
50
50
—
10
20
5
—
—
15
50
—
—
ns
ns
ns
ns
ns
ns
SMCLK width high
SMCLK rise/fall time
SMTXD active delay (from SMCLK falling edge)
SMRXD/SMSYNC setup time
RXD1/SMSYNC hold time
1
SyncCLK must be at least twice as fast as SMCLK.
SMCLK
152
152
151
151A
150
SMTXD
(Output)
NOTE 1
154
153
155
SMSYNC
154
155
SMRXD
(Input)
NOTE:
1. This delay is equal to an integer number of character-length clocks.
Figure 12-66. SMC Transparent Timing Diagram
12.10SPI Master AC Electrical Specifications
Table 12-26 provides the SPI master timings as shown in Figure 12-67 and Figure 12-68.
66
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SPI Master AC Electrical Specifications
Table 12-26. SPI Master Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
1024
160
MASTER cycle time
4
t
t
cyc
161
162
163
164
165
166
167
MASTER clock (SCK) high or low time
MASTER data setup time (inputs)
Master data hold time (inputs)
Master data valid (after SCK edge)
Master data hold time (outputs)
Rise time output
2
512
—
cyc
50
0
ns
ns
ns
ns
ns
ns
—
—
0
20
—
—
—
15
15
Fall time output
SPICLK
(CI=0)
(Output)
161
167
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
166
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 12-67. SPI Master (CP = 0) Timing Diagram
67
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SPI Slave AC Electrical Specifications
SPICLK
(CI=0)
(Output)
161
167
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
166
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 12-68. SPI Master (CP = 1) Timing Diagram
12.11SPI Slave AC Electrical Specifications
Table 12-27 provides the SPI slave timings as shown in Figure 12-69 and Figure 12-70.
Table 12-27. SPI Slave Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
170
Slave cycle time
2
—
t
cyc
171
172
173
174
175
176
177
Slave enable lead time
Slave enable lag time
15
15
1
—
—
—
—
—
—
50
ns
ns
Slave clock (SPICLK) high or low time
Slave sequential transfer delay (does not require deselect)
Slave data setup time (inputs)
t
t
cyc
cyc
1
20
20
—
ns
ns
ns
Slave data hold time (inputs)
Slave access time
68
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
SPI Slave AC Electrical Specifications
SPISEL
(Input)
172
171
174
SPICLK
(CI=0)
(Input)
173
182
181
173
170
SPICLK
(CI=1)
(Input)
177
181
182
180
178
Undef
SPIMISO
(Output)
msb
176
Data
lsb
msb
msb
175
179
181 182
lsb
SPIMOSI
(Input)
msb
Data
Figure 12-69. SPI Slave (CP = 0) Timing Diagram
SPISEL
(Input)
172
174
171
170
SPICLK
(CI=0)
(Input)
173
182
181
182
173
181
SPICLK
(CI=1)
(Input)
177
180
178
SPIMISO
(Output)
msb
msb
msb
Undef
175
Data
lsb
179
176
181 182
Data
SPIMOSI
(Input)
msb
lsb
Figure 12-70. SPI Slave (CP = 1) Timing Diagram
69
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
I2C AC Electrical Specifications
2
12.12I C AC Electrical Specifications
Table 12-28 provides the I2C (SCL < 100 KHz) timings.
2
Table 12-28. I C Timing (SCL < 100 KHZ)
All Frequencies
Num
200
Characteristic
Unit
KHz
Min
Max
100
SCL clock frequency (slave)
SCL clock frequency (master)
0
1
200
202
203
204
205
206
207
208
209
210
211
1.5
4.7
4.7
4.0
4.7
4.0
0
100
—
—
—
—
—
—
—
1
KHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
250
—
SDL/SCL rise time
SDL/SCL fall time
—
300
—
Stop condition setup time
4.7
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Table 12-29 provides the I2C (SCL > 100 KHz) timings.
2
Table 12-29. I C Timing (SCL > 100 KHZ)
All Frequencies
Max
Num
Characteristic
Expression
Unit
Min
200
SCL clock frequency (slave)
SCL clock frequency (master)
fSCL
fSCL
—
0
BRGCLK/48
Hz
1
200
202
203
204
205
206
207
208
209
210
211
BRGCLK/16512
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
0
BRGCLK/48
Hz
s
Bus free time between transmissions
Low period of SCL
—
—
—
s
High period of SCL
—
—
s
Start condition setup time
Start condition hold time
Data hold time
—
—
s
—
—
s
—
—
s
Data setup time
—
1/(40 * fSCL)
—
—
s
SDL/SCL rise time
—
1/(10 * fSCL)
1/(33 * fSCL)
—
s
SDL/SCL fall time
—
—
s
Stop condition setup time
—
1/2(2.2 * fSCL)
s
70
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
I2C AC Electrical Specifications
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
Figure 12-71 shows the I2C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
2
Figure 12-71. I C Bus Timing Diagram
Part XIII UTOPIA AC Electrical Specifications
Table 13-30, Table 13-31, and Table 13-32, shows the AC electrical specifications for the
UTOPIA interface.
Table 13-30. UTOPIA Master (Muxed Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
4ns
50
ns
%
Duty cycle
Frequency
50
33
Mhz
ns
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active
delay (and PHREQ and PHSEL active delay in MPHY mode)
Output
2ns
16ns
U3
U4
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
Input
Input
4ns
1ns
ns
ns
71
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
I2C AC Electrical Specifications
Table 13-31. UTOPIA Master (Split Bus Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
4ns
50
ns
%
Duty cycle
Frequency
50
33
Mhz
ns
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr andTxAddr active delay
(PHREQ and PHSEL active delay in MPHY mode)
Output
2ns
16ns
U3
U4
UTPB_Aux, SOC_Aux, Rxclav and Txclav setup time
UTPB_Aux, SOC_Aux, Rxclav and Txclav hold time
Input
Input
4ns
1ns
ns
ns
Table 13-32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (external clock option)
Duty cycle
Input
4ns
60
ns
%
40
Frequency
33
Mhz
ns
U2
U3
UTPB, SOC, Rxclav and Txclav active delay
Output
Input
2ns
4ns
16ns
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr
setup time
ns
U4
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr
hold time
Input
1ns
ns
Figure 13-72 shows signal timings during UTOPIA receive operations.
72
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
I2C AC Electrical Specifications
U1
U1
UtpClk
U2
PHREQn
U3
U4
RxClav
HighZ at MPHY
HighZ at MPHY
U2
RxEnb
UTPB
SOC
U3
U4
Figure 13-72. UTOPIA Receive Timing
Figure 13-73 shows signal timings during UTOPIA transmit operations.
U1
U1
UtpClk
U2
PHSELn
TxClav
U3
U4
HighZ at MPHY
HighZ at MPHY
U2
TxEnb
UTPB
SOC
U2
Figure 13-73. UTOPIA Transmit Timing
Part XIV FEC Electrical Characteristics
This section provides theAC electrical specifications for the Fast Ethernet controller (FEC).
Note that the timing specifications for the MII signals are independent of system clock
frequency (part speed designation). Also, MII signals use TTL signal levels compatible
with devices operating at either 5.0 V or 3.3 V.
73
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK)
14.1 MII Receive Signal Timing (MII_RXD[3:0],
MII_RX_DV, MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz
+1%. There is no minimum frequency requirement. In addition, the processor clock
frequency must exceed the MII_RX_CLK frequency - 1%.
Table 14-33 provides information on the MII receive signal timing.
Table 14-33. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
M2
M3
M4
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
MII_RX_CLK pulse width high
5
5
—
—
ns
ns
35%
35%
65%
65%
MII_RX_CLK period
MII_RX_CLK period
MII_RX_CLK pulse width low
Figure 14-74 shows MII receive signal timing.
M3
MII_RX_CLK (input)
M4
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 14-74. MII Receive Signal Timing Diagram
14.2 MII Transmit Signal Timing (MII_TXD[3:0],
MII_TX_EN, MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of
25 MHz +1%. There is no minimum frequency requirement. In addition, the processor
clock frequency must exceed the MII_TX_CLK frequency - 1%.
Table 14-34 provides information on the MII transmit signal timing,.
74
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 14-34. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
M8
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5
—
ns
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
—
25
35%
35%
65%
65%
MII_TX_CLK period
MII_TX_CLK period
MII_TX_CLK pulse width low
Figure 14-75 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (input)
M5
M8
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 14-75. MII Transmit Signal Timing Diagram
14.3 MII Async Inputs Signal Timing (MII_CRS,
MII_COL)
Table 14-35 provides information on the MII async inputs signal timing.
Table 14-35. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
Figure 14-76 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 14-76. MII Async Inputs Timing Diagram
75
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
14.4 MII Serial Management Channel Timing
(MII_MDIO, MII_MDC)
Table 14-36 provides information on the MII serial management channel signal timing. The
FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact
upper bound is under investigation.
Table 14-36. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
M12
M13
M14
M15
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
MII_MDIO (input) to MII_MDC rising edge setup
MII_MDIO (input) to MII_MDC rising edge hold
MII_MDC pulse width high
—
25
ns
ns
ns
10
—
0
—
40%
40%
60%
60%
MII_MDC period
MII_MDC period
MII_MDC pulse width low
Figure 14-77 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
M12
M13
Figure 14-77. MII Serial Management Channel Timing Diagram
76
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Part XV Mechanical Data and Ordering Information
Table 15-37 provides information on the MPC866/859T/859DSL derivative devices.
Table 15-37. MPC866/859T/859DSL Derivatives
Number
of
SCCs
Cache Size
Instruction
Ethernet
Support
Multi-Channel
HDLC Support
Device
ATM Support
1
Data
MPC866T
MPC866P
MPC859T
Four
Four
10/100 Mbps
10/100 Mbps
Yes
Yes
Yes
No
Yes
4 Kbyte
16 Kbyte
4 Kbyte
4 Kbyte
4 Kbyte
8 Kbyte
4 Kbyte
4 Kbyte
Yes
Yes
One (SCC1) 10/100 Mbps
MPC859DSL One (SCC1) 10/100 Mbps
Up to 4 addresses
1
Serial communications controller (SCC)
Table 15-38 identifies the packages and operating frequencies orderable for the
MPC866/859T/859DSL derivative devices.
Table 15-38. MPC866/859T/859DSL Package/Frequency Orderable
Package Type
Temperature (Tj)
Frequency (MHz)
Order Number
Plastic ball grid array
(ZP suffix)
0°C to 95°C
50
66
MPC859DSLZP50
MPC859DSLZP66
100
MPC866PZP100
MPC866TZP100
MPC859TZP100
133
MPC866PZP133
MPC866TZP133
MPC859TZP133
1
Plastic ball grid array
(CZP suffix)
-40°C to 100°C
TBD
TBD
1
Additional extended temperature devices can be made available at 50MHz, 66MHz, 80MHz and100MHz
.
15.1 Pin Assignments
Figure 15-78 shows the top view pinout of the PBGA package. For additional information,
see the MPC866 PowerQUICC Family User s Manual.
77
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
NOTE:This is the top view of the device.
W
V
U
T
PD10 PD8
PD14 PD13 PD9
PA0 PB14 PD15
PD3
IRQ7 D0
D4
D1
D2
D3
D5
VDDL
D20
D6
D7
D29
DP1
DP2 CLKOUT IPA3
VSSSYN1
N/C
PD6 M_Tx_EN IRQ0 D13
D27
D10
D14
D18
D24
D28
D30
DP3
DP0
PD4
PD5 IRQ1
D8
D23
D17
D11
D9
D16
D15
D19
D22
D21
D25
D26
D31
IPA5 IPA4 IPA2
N/C VSSSYN
N/C VDDSYN
PA1
PC6
PC5 PC4 PD11
PA2 PB15 PD12
PD7 VDDH D12
VDDH
IPA6 IPA0 IPA1 IPA7
R
P
N
M
L
VDDH
WAIT_B WAIT_A
VDDL RSTCONF
VDDL
PORESET
SRESET
PA4 PB17 PA3 VDDL
PB19 PA5 PB18 PB16
GND
GND
XTAL
TEXP
HRESET
EXTCLK EXTAL
PA7
PC8
PA6
PC7
BADDR28
AS
MODCK2
OP0
BADDR29
VDDL
PB22 PC9
PA8 PB20
OP1 MODCK1
K
J
PC10 PA9 PB23 PB21
PC11 PB24 PA10 PB25
GND
BADDR30 IPB6 ALEA IRQ4
IPB5 IPB1 IPB2 ALEB
M_COL IRQ2 IPB0 IPB7
H
G
F
VDDL M_MDIO TDI
TCK
TRST TMS TDO PA11
PB26 PC12 PA12 VDDL
PB27 PC13 PA13 PB29
PB28 PC14 PA14 PC15
BR
VDDL
CS3
IRQ6 IPB4 IPB3
GND
GND
TS
BI
IRQ3 BURST
VDDH
VDDH
CS6
E
D
C
B
A
BG
BB
A8
A9
N/C
A12
A13
N/C
A16
A17
A15
A20
A21
A19
A24
A23
A25
A18 BSA0 GPLA0 N/C
CS2 GPLA5 BDIP TEA
PB30 PA15 PB31
A3
A6
A26 TSIZ1 BSA1 WE0 GPLA1 GPLA3 CS7
CS0
TA GPLA4
A0
19
A1
A4
A10
A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 CE1A WR GPLB4
A2
18
A5
17
A7
16
A11
15
A14
14
A27
13
A29
12
A30
11
A28
10
A31 VDDL BSA2 WE1 WE3 CS4 CE2A CS1
9
8
7
6
5
4
3
2
1
Figure 15-78. Pinout of the PBGA Package
Table 15-39 contains a list of the MPC866 input and output signals and shows multiplexing
and pin assignments.
78
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Table 15-39. Pin Assignments
Name
Pin Number
Type
A[0:31]
B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15, C14, Bidirectional
B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11, D10, Three-state
C10, A13, A10, A12, A11, A9
TSIZ0
REG
B9
C9
B2
F1
D2
F3
C2
Bidirectional
Three-state
TSIZ1
Bidirectional
Three-state
RD/WR
BURST
Bidirectional
Three-state
Bidirectional
Three-state
BDIP
GPL_B5
Output
TS
Bidirectional
Active Pull-up
TA
Bidirectional
Active Pull-up
TEA
BI
D1
E3
Open-drain
Bidirectional
Active Pull-up
IRQ2
RSV
H3
K1
Bidirectional
Three-state
IRQ4
KR
Bidirectional
Three-state
RETRY
SPKROUT
CR
F2
Input
IRQ3
D[0:31]
W14, W12, W11, W10, W13, W9, W7, W6, U13,T11,V11, U11,T13, Bidirectional
V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, U7, V12, Three-state
V6, W5, U6, T7
DP0
IRQ3
V3
V5
W4
V4
Bidirectional
Three-state
DP1
IRQ4
Bidirectional
Three-state
DP2
IRQ5
Bidirectional
Three-state
DP3
IRQ6
Bidirectional
Three-state
BR
BG
BB
G4
E2
E1
Bidirectional
Bidirectional
Bidirectional
Active Pull-up
79
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
FRZ
G3
IRQ6
IRQ0
IRQ1
V14
U14
W15
Input
Input
Input
M_TX_CLK
IRQ7
CS[0:5]
C3, A2, D4, E4, A4, B4
D5
Output
Output
CS6
CE1_B
CS7
CE2_B
C4
C7
Output
Output
WE0
BS_B0
IORD
WE1
BS_B1
IOWR
A6
B6
A5
Output
Output
Output
WE2
BS_B2
PCOE
WE3
BS_B3
PCWE
BS_A[0:3]
D8, C8, A7, B8
D7
Output
Output
GPL_A0
GPL_B0
OE
GPL_A1
GPL_B1
C6
Output
Output
GPL_A[2:3]
GPL_B[2:3]
CS[2–3]
B5, C5
UPWAITA
GPL_A4
C1
B1
Bidirectional
Bidirectional
UPWAITB
GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
D3
R2
P3
N4
P2
P1
Output
Input
Input
Open-drain
Open-drain
Analog Output
80
MPC866/859T/859DSLHardwareSpecifications
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MOTOROLA
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
EXTAL
N1
W3
N2
N3
K2
Analog Input (3.3V only)
Output
CLKOUT
EXTCLK
TEXP
Input (3.3V only)
Output
ALE_A
Output
MII-TXD1
CE1_A
MII-TXD2
B3
A3
R3
Output
Output
Input
CE2_A
MII-TXD3
WAIT_A
SOC_Split
2
WAIT_B
R4
T5
Input
Input
IP_A0
UTPB_Split0
2
MII-RXD3
IP_A1
UTPB_Split1
MII-RXD2
T4
U3
Input
Input
2
IP_A2
IOIS16_A
UTPB_Split2
2
MII-RXD1
IP_A3
UTPB_Split3
MII-RXD0
W2
U4
U5
T6
T3
J1
Input
Input
Input
Input
Input
2
IP_A4
UTPB_Split4
MII-RXCLK
2
IP_A5
UTPB_Split5
MII-RXERR
2
IP_A6
UTPB_Split6
MII-TXERR
2
IP_A7
UTPB_Split7
MII-RXDV
2
ALE_B
DSCK/AT1
Bidirectional
Three-state
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
H2, J3
Bidirectional
81
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
IP_B2
IOIS16_B
AT2
J2
Three-state
IP_B3
IWP2
VF2
G1
G2
J4
Bidirectional
IP_B4
LWP0
VF0
Bidirectional
Bidirectional
IP_B5
LWP1
VF1
IP_B6
DSDI
AT0
K3
H1
L4
Bidirectional
Three-state
IP_B7
PTR
AT3
Bidirectional
Three-state
OP0
Bidirectional
MII-TXD0
UtpClk_Split
2
OP1
L2
L1
Output
OP2
Bidirectional
MODCK1
STS
OP3
MODCK2
DSDO
M4
K4
Bidirectional
Output
BADDR30
REG
BADDR[28:29]
AS
M3, M2
L3
Output
Input
PA15
RXD1
RXD4
C18
Bidirectional
PA14
TXD1
TXD4
D17
Bidirectional
(Optional: Open-drain)
PA13
RXD2
E17
F17
G16
Bidirectional
PA12
TXD2
Bidirectional
(Optional: Open-drain)
PA11
Bidirectional
L1TXDB
RXD3
(Optional: Open-drain)
82
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
PA10
J17
L1RXDB
TXD3
(Optional: Open-drain)
PA9
K18
Bidirectional
L1TXDA
(Optional: Open-drain)
RXD4
PA8
L17
Bidirectional
L1RXDA
TXD4
(Optional: Open-drain)
PA7
M19
Bidirectional
CLK1
L1RCLKA
BRGO1
TIN1
PA6
CLK2
TOUT1
M17
N18
Bidirectional
Bidirectional
PA5
CLK3
L1TCLKA
BRGO2
TIN2
PA4
CLK4
TOUT2
P19
P17
Bidirectional
Bidirectional
PA3
CLK5
BRGO3
TIN3
PA2
CLK6
TOUT3
L1RCLKB
R18
T19
U19
Bidirectional
Bidirectional
Bidirectional
PA1
CLK7
BRGO4
TIN4
PA0
CLK8
TOUT4
L1TCLKB
PB31
SPISEL
REJECT1
C17
C19
Bidirectional
(Optional: Open-drain)
PB30
Bidirectional
SPICLK
RSTRT2
(Optional: Open-drain)
83
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
PB29
SPIMOSI
E16
D19
(Optional: Open-drain)
PB28
Bidirectional
SPIMISO
BRGO4
(Optional: Open-drain)
PB27
I2CSDA
BRGO1
E19
F19
J16
J18
K17
Bidirectional
(Optional: Open-drain)
PB26
I2CSCL
BRGO2
Bidirectional
(Optional: Open-drain)
PB25
RXADDR3
SMTXD1
Bidirectional
(Optional: Open-drain)
2
PB24
TXADDR3
SMRXD1
Bidirectional
(Optional: Open-drain)
2
PB23
TXADDR2
Bidirectional
(Optional: Open-drain)
2
SDACK1
SMSYN1
PB22
TXADDR4
SDACK2
SMSYN2
L19
K16
Bidirectional
(Optional: Open-drain)
2
PB21
Bidirectional
SMTXD2
L1CLKOB
PHSEL1
(Optional: Open-drain)
1
2
TXADDR1
PB20
L16
Bidirectional
SMRXD2
L1CLKOA
PHSEL0
(Optional: Open-drain)
1
2
TXADDR0
PB19
RTS1
L1ST1
N19
N17
Bidirectional
(Optional: Open-drain)
PB18
RXADDR4
Bidirectional
(Optional: Open-drain)
2
RTS2
L1ST2
PB17
P18
Bidirectional
L1RQb
L1ST3
RTS3
PHREQ1
RXADDR1
(Optional: Open-drain)
1
2
84
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
PB16
N16
L1RQa
L1ST4
RTS4
PHREQ0
RXADDR0
(Optional: Open-drain)
1
2
PB15
BRGO3
TxClav
R17
U18
D16
Bidirectional
Bidirectional
Bidirectional
PB14
RXADDR2
RSTRT1
2
PC15
DREQ0
RTS1
L1ST1
RxClav
PC14
DREQ1
RTS2
D18
E18
F18
Bidirectional
Bidirectional
Bidirectional
L1ST2
PC13
L1RQb
L1ST3
RTS3
PC12
L1RQa
L1ST4
RTS4
PC11
CTS1
J19
Bidirectional
Bidirectional
PC10
K19
CD1
TGATE1
PC9
CTS2
L18
Bidirectional
Bidirectional
PC8
M18
CD2
TGATE2
PC7
CTS3
L1TSYNCB
SDACK2
M16
R19
Bidirectional
Bidirectional
PC6
CD3
L1RSYNCB
85
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
PC5
T18
CTS4
L1TSYNCA
SDACK1
PC4
CD4
L1RSYNCA
T17
U17
Bidirectional
Bidirectional
PD15
L1TSYNCA
MII-RXD3
UTPB0
PD14
V19
V18
R16
T16
W18
V17
W17
T15
V16
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
L1RSYNCA
MII-RXD2
UTPB1
PD13
L1TSYNCB
MII-RXD1
UTPB2
PD12
L1RSYNCB
MII-MDC
UTPB3
PD11
RXD3
MII-TXERR
RXENB
PD10
TXD3
MII-RXD0
TXENB
PD9
RXD4
MII-TXD0
UTPCLK
PD8
TXD4
MII-MDC
MII-RXCLK
PD7
RTS3
MII-RXERR
UTPB4
PD6
RTS4
MII-RXDV
UTPB5
86
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pin Assignments
Name
Table 15-39. Pin Assignments (continued)
Pin Number
Type
Bidirectional
PD5
U15
U16
W16
REJECT2
MII-TXD3
UTPB6
PD4
Bidirectional
Bidirectional
REJECT3
MII-TXD2
UTPB7
PD3
REJECT4
MII-TXD1
SOC
TMS
G18
H17
Input
Input
TDI
DSDI
TCK
H16
Input
DSCK
TRST
G19
G17
Input
TDO
Output
DSDO
MII_CRS
MII_MDIO
MII_TXEN
MII_COL
VSSSYN1
B7
Input
H18
V15
H4
Bidirectional
Output
Input
V1
PLL analog VDD and
GND
VSSSYN
VDDSYN
GND
U1
T1
Power
Power
Power
F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10,
G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14,
J6, J7, J8, J9, J10, J11, J12, J13, J14, K6, K7, K8, K9, K10, K11,
K12, K13, K14, L6, L7, L8, L9, L10, L11, L12, L13, L14, M6, M7, M8,
M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11, N12,
N13, N14, P6, P7, P8, P9, P10, P11, P12, P13, P14
VDDL
VDDH
A8, M1, W8, H19, F4, F16, P4, P16, R1
Power
Power
E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, F5, F15, G5,
G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P5,
P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14
N/C
D6, D13, D14, U2, V2, T2
No-connect
1
Classic SAR mode only
ESAR mode only
2
87
MPC866/859T/859DSLHardwareSpecifications
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MOTOROLA
Mechanical Dimensions of the PBGA Package
15.2 Mechanical Dimensions of the PBGA Package
For more information on the printed circuit board layout of the PBGA package, including
thermal via design and suggested pad layout, please refer to Plastic Ball Grid Array
Application Note (order number: AN1231/D) available from your local Motorola sales
office. Figure 15-79 shows the mechanical dimensions of the PBGA package.
Figure 15-79. Mechanical Dimensions and Bottom Surface Nomenclature of the
PBGA Package
88
MPC866/859T/859DSLHardwareSpecifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Mechanical Dimensions of the PBGA Package
Part XVI Document Revision History
Table 16-40 lists significant changes between revisions of this document.
Table 16-40. Document Revision History
Revision
Date
5/2002 Initial revision
Substantive Changes
0
1
11/2002 Added the 5V Tolerant Pins, new package dimensions, and other changes
MOTOROLA
MPC866/859T/859DSLHardwareSpecifications
89
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Mechanical Dimensions of the PBGA Package
90
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Mechanical Dimensions of the PBGA Package
91
MPC866/859T/859DSLHardwareSpecifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
HOW TO REACH US:
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SPS, Technical Information Center
3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569
Information in this document is provided solely to enable system and software implementers to use
Motorola products.There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document.
ASIA/PACIFIC:
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852-26668334
Motorola reserves the right to make changes without further notice to any products herein.
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for any particular purpose, nor does Motorola assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
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© Motorola, Inc. 2002
MPC866EC/D
相关型号：
KMPC866TZP133A
32-BIT, 133MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM PITCH, PLASTIC, BGA-357
NXP
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