M116S163AST12 [MOTOROLA]
Synchronous DRAM, 1MX16, 9ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP-50;
| 型号： | M116S163AST12 |
| 厂家： | 
MOTOROLA |
| 描述： | Synchronous DRAM, 1MX16, 9ns, CMOS, PDSO50, 0.400 INCH, 0.80 MM PITCH, TSOP-50 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总48页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC16S044T3B/D
SEMICONDUCTOR
TECHNICAL DATA
2 x 2M x 4
MC16S044T3B
Product Preview
2 x 1M x 8
x4, x8, x16
MC16S084T3B
The family of 16M Synchronous Dynamic RAMs is fabricated using 0.45µ
CMOS high–speed silicon gate process technology. It includes devices
organized as 2 banks x 2,097,152 words x 4 bits, 2 banks x 1,048,576 words
x 8 bits, and 2 banks x 524,288 words x 16 bits. Advanced circuit design and
fine line processing provide high performance, improved reliability, and low
cost.
Fully synchronous operations are referenced to the rising edge of the clock
input and can achieve data transfer rates up to 100 MHz. These devices are
ideal for main memory in applications such as workstations, microcomputers,
and refresh memory in CRTs.
These devices are packaged in a standard 400 mil thin small outline
package (TSOP).
T PACKAGE
400 MIL TSOP
CASE 924B–01
•
•
•
•
•
•
•
•
•
•
•
•
Single 3.3 V ± 0.3 V Power Supply
Clock Frequency 100 MHz/83 MHz
Fully Synchronous Operation Referenced to Clock Rising Edge
Dual Bank Operation Controlled by Bank Address (BA)
CAS Latency Programmable to 1/2/3
2 x 512K x 16
M116S163AST
Burst Length Programmable to 1/2/4/8/Page
Burst Type Programmable to Sequential/Interleaved
Auto Precharge: All Bank Precharge Controlled by A10 and BA
Auto–Refresh and Self–Refresh
4096 Refresh Cycles: 64 ms
LVTTL Interface
T PACKAGE
400 MIL TSOP
CASE 985C–01
Package:
MC16S044T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)
MC16S084T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)
M116S163AST: 400 mil, 50–Pin TSOP (0.8 mm Pitch)
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
4/4/97
Motorola, Inc. 1997
PIN ASSIGNMENTS
400 MIL TSOP
44–PIN
400 MIL TSOP
50–PIN
V
1
2
44
43
V
V
1
2
50
49
V
SS
V
V
CC
SS
CC
SS
CC
DQ0
DQ7
DQ0
DQ1
DQ15
DQ14
NC
NC
Q
V
V
Q
3
4
5
6
7
42
41
40
39
38
V
Q
3
4
5
6
7
48
47
46
45
44
V
Q
V
V
SS
SS
SS
SS
DQ1
Q
DQ6
V
V
Q
V
Q
DQ3
DQ0
Q
SS
SS
V
Q
DQ2
DQ3
Q
DQ13
DQ12
V
Q
CC
CC
CC
CC
DQ2
DQ5
NC
NC
V
Q
V
Q
V
Q
V
Q
V
Q
SS
SS
CC
CC
SS
SS
DQ3
8
37
DQ4
DQ4
8
43
DQ11
DQ10
DQ2
DQ1
Q
V
Q
9
36
35
V
Q
DQ5
9
42
41
V
Q
V
CC
CC
CC
CC
NC
NC
WE
10
NC
NC
V
Q
10
V
Q
NC
NC
NC
SS
SS
11
12
34
33
DQ6
DQ7
11
12
40
39
DQ9
DQ8
NC
DQM
DQM
WE
CAS
RAS
CS
13
14
15
32
31
30
CLK
CKE
NC
V
Q
13
14
15
38
37
36
V
Q
CLK
CKE
NC
CAS
RAS
CS
CC
CC
LDQM
WE
NC
UDQM
CLK
BA
A10
A0
16
17
18
29
28
27
A9
A8
A7
CAS
16
35
A9
BA
A10
A0
RAS
CS
17
18
34
33
CKE
NC
A8
A7
A1
A2
A3
19
20
21
22
26
A6
BA
A10
A0
19
20
21
22
23
32
A9
A6
A1
A2
A3
25
24
23
A5
A4
31
30
29
28
27
26
A8
A7
A6
A5
A4
A5
A4
V
A1
V
V
V
CC
CC
SS
SS
A2
A3
24
25
x8
x4
V
V
CC
SS
x16
PIN NAMES
A0 – A10 . . . . . . . . . . . . . . . . . Address Inputs DQM (x4, x8) . . . Output Disable/Write Mask
BA . . . . . . . . . . . . . . . . . . . . . . . Bank Address UDQM/ . . . . . . . . Output Disable/Write Mask
CS . . . . . . . . . . . . . . . . . . . . . . . . . Chip Select
CAS . . . . . . . . . . . . . . Column Address Strobe
DQ0 – DQ15 . . . . . . . . . . . . Data Input/Output
RAS . . . . . . . . . . . . . . . . Row Address Strobe
WE . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
LDQM (x16)
(Upper/Lower Byte)
V
V
V
V
. . . . . . . . . . . . . . . . . . . . . Power (+ 3.3 V)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
Q . . . . . . Power (+ 3.3 V) (for I/O Buffer)
CC
SS
CC
Q . . . . . . . . . . . . . Ground (for I/O Buffer)
SS
CKE . . . . . . . . . . . . . . . . . . . . . . . Clock Enable NC . . . . . . . . . . . . . . . . . . . . . . . No Connection
CLK . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
2
BLOCK DIAGRAM
CLOCK
BUFFER
CLK
CKE
CONTROL
SIGNAL
GENERATOR
CS
RAS
CAS
WE
COLUMN DECODER
COMMAND
DECODER
2048 x 512 x 8*
CELL ARRAY
BANK 0
SENSE AMPLIFIER
A10
MODE
REGISTER
DQ
BUFFER
DATA CONTROL
ADDRESS
BUFFER
DQ0 – DQ7*
CIRCUIT
A0 – A9,
BA
DQM
SENSE AMPLIFIER
COLUMN
COUNTER
REFRESH
COUNTER
2048 x 512 x 8*
CELL ARRAY
BANK 1
COLUMN DECODER
* This figure is for the MC16S084T3B (2 x 1M x 8) device.
Refer to the following table for differences in addressing, array size, and DQ width.
Row
Address
Column
Address
Device
Array Size
DQ Width
MC16S044T3B
MC16S084T3B
M116S163AST
A0 – A10
A0 – A10
A0 – A10
A0 – A9
A0 – A8
A0 – A7
2048 x 1024 x 4
2048 x 512 x 8
2048 x 256 x 16
DQ0 – DQ3
DQ0 – DQ7
DQ0 – DQ15
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
3
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Symbol
Value
Unit
V
Power Supply Voltage (to V
)
V
CC
– 0.3 to + 4.6
– 0.3 to + 4.6
SS
Power Supply Voltage for Output
V
CC
Q
V
(to V Q)
SS
Input Voltage (Relative to V
)
V
in
– 0.3 to + 4.6
– 0.3 to + 4.6
50
V
V
SS
Output Voltage (Relative to V Q)
SS
V
out
out
Output Current
I
mA
mW
°C
Power Dissipation
P
D
1000
Operating Temperature Range
Storage Temperature Range
T
A
0 to + 70
– 55 to + 150
T
stg
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All Voltages Referenced to V
)
SS
Parameter
Symbol
Min
3.0
0
Typ
3.3
0
Max
3.6
0
Unit
Supply Voltage (Operating Voltage Range)
V
CC
V
V
SS
Supply Voltage for Output (Operating Voltage Range)
V
Q
3.0
0
3.3
0
3.6
0
V
CC
V
Q
SS
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
V
2.0
– 0.3
2.4
—
—
—
—
—
—
V
CC
+ 0.3
V
V
IH
V
0.8
—
0.4
5
IL
High Level Output Voltage (I
= – 2 mA)
= 2 mA)
V
OH
V
OH
Low Level Output Voltage (I
V
OL
V
OL
Input Leakage Current (0 V ≤ V < V , All Other Pins Not Under
Test = 0 V)
I
I
– 5
µA
in CC
lkg(1)
Output Leakage Current (0 V ≤ V
< V , Output Disable)
CC
– 5
—
5
µA
out
lkg(0)
NOTE: V (Max) = V /V Q + 1.2 V for pulse width ≤ 5 ns. V (Min) = V /V Q – 1.2 V for pulse width ≤ 5 ns.
IH
CC CC
IL
SS SS
CAPACITANCE
(f = 1.0 MHz @ 25 mV rms, V
= V Q = 3.3 V ± 0.3 V, V
= V Q = 0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
SS
DD
DD
SS
A
Parameter
Symbol
Max
Unit
Input Capacitance
All Non–CLK Inputs
C
4
6
5
pF
in
CLK
I/O Capacitance
DQ0 – DQ15
C
pF
I/O
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
4
AVERAGE SUPPLY CURRENT
Max (x4/x8/x16)
Characteristic
Symbol
Unit
mA
mA
mA
mA
Notes
–10
–12
Operating Current
= Min, t
Single Bank
I
90
80
1
1
1
CC1
t
= Min
CLK
RC
Dual Bank Interleaved
Clock Enabled (CKE = H)
I
130
30
2
115
28
2
CC1B
Standby Current
Both Banks Idle, t
I
CC2
= Min
CLK
Clock Disabled (CKE = L)
(Power Down Mode)
I
I
CC2P
Standby Current
Clock Enabled (CKE = H)
13
2
13
2
mA
mA
CC2S
Both Banks Idle, CLK = L
Active Standby Current
Clock Disabled (CKE = L)
(Power Down Mode)
I
CC2PS
Clock Enabled (CKE = H)
I
75
3
70
3
mA
mA
2
CC3
Both Banks Active, t
= Min, CS = H
CLK
Clock Disabled (CKE = L)
(Power Down Mode)
I
CC3P
Burst Current
Both Banks Active, t
Read Cycle
Write Cycle
I
135
125
65
125
115
60
mA
mA
mA
1, 2
1
CC4R
= Min
CLK
I
CC4W
Auto–Refresh Current
I
1
CC5
t
= Min, t
= Min
CLK
RC
Self–Refresh Current
CKE = 0.2 V
I
2
2
mA
CC6
NOTES:
1. These parameters depend on the specified cycle rate and are measured at minimum t
during CLK.
and t . Input signals are changed one time
RC
CK
2. These parameters depend on output loading. Specified values are obtained with the output open.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= V Q = 3.3 V ± 0.3 V, V
= V Q = 0 V, V = 0.4 V, V = 2.0 V,
SS SS IL IH
CC
CC
T = 0 to 70°C, Input and Output Timing Reference Level = 1.4 V, Unless Otherwise Noted)
A
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
–10
–12
Parameter
Symbol
Unit
Notes
Min
Max
Min
Max
Clock Cycle Time
(CL = 1)
(CL = 2)
(CL = 3)
t
30
15
10
1000
1000
1000
36
18
12
1000
1000
1000
ns
CLK
Clock High Pulse Width
Clock Low Pulse Width
Transition Time of CLK
Data Input Setup Time
Data Input Hold Time
Address Setup Time
NOTES:
t
3
3
1
3
1
3
—
—
10
—
—
—
4
4
1
3
1
3
—
—
10
—
—
—
ns
ns
ns
ns
ns
ns
5
CH
t
CL
t
T
t
DS
DH
t
t
AS
1. See Figure 1 for input and output reference levels and output load conditions.
2. Transition time (rise and fall) of input signals is 2 ns.
3. Transition times are measured between V and V . Transition times (rise and fall) of input signals are fixed slope.
IH IL
4. Power up must be performed in the following sequence:
(1) With the device in the no–operation state, simultaneously apply power to V
(2) Pause for a minimum of 200 µs.
and V Q, and start the CLK signal.
CC
CC
(3) Set DQM and CKE signals to V to ensure high impedance at the DQ outputs.
IH
(4) Precharge both banks.
(5) Initialize the mode register with the mode register set command.
(6) Issue a minimum of eight auto–refresh dummy commands to stabilize the internal device circuitry.
Steps 5 and 6 may be interchanged.
5. t
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V (Min). t
is the pulse width of CLK
CL
CH
IH
measured from the negative edge to the positive edge referenced to V (Max).
IL
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
5
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES (continued)
–10
–12
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
1
Max
—
Min
1
Max
—
Address Hold Time
CKE Setup Time
CKE Hold Time
t
AH
t
3
—
3
—
CKS
CKH
CMS
CMH
t
1
—
1
—
Command Setup Time
Command Hold Time
Row Cycle Time
t
3
—
3
—
t
1
—
1
—
t
100
30
10
60
30
—
120
36
12
72
36
—
6
6
6
6
6
RC
Row to Column Delay
Column to Column Delay
Row Active Time
t
t
—
—
RCD
CCD
—
—
t
100000
—
100000
—
RAS
Row Precharge Time
Write Recovery Time
t
RP
(CL = 1)
(CL = 2)
(CL = 3)
t
30
15
—
36
18
—
WR
1 CLK + 10
1 CLK + 12
Act to Act Delay Time
t
20
20
0
—
—
10
64
—
24
24
0
—
—
12
64
—
ns
ns
ns
ms
ns
6
6
RRD
Mode Register Set Cycle Time
Power Down Mode Entry Time
Refresh Interval Time
t
RSC
t
SB
t
—
—
REF
Access Time from CLK
(CL = 1)
(CL = 2)
(CL = 3)
t
24
9
8.5
27.5
9.5
9
AC
Column Access Time
t
24
3
—
—
—
10
27.5
—
—
—
12
ns
ns
ns
ns
CAC
Output Hold Time from CLK
t
3
0
3
OH
Delay Time, Output Low Impedance from CLK
t
0
LZ
Delay Time, Output High Impedance from CLK
NOTES:
t
3
7
HZ
6. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycle = specified value of timing/clock period
(count fractions as a whole number)
See the Latency Relationship to Frequency table.
7. t
defines the time at which the outputs achieve the open circuit condition and is not a reference level.
HZ
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
6
CLK
1.4 V
1.4 V
V
= 1.4 V
TT
SIGNAL
50
Ω
V
= 1.4 V
REF
V
OUT
50 pF
CLK
DQ
1.4 V
1.4 V
Output Load Condition
t
t
OHZ
AC
t
OH
NOTE: Any AC timing isreferenced
to the input signal crossing
through 1.4 V.
Figure 1.
LATENCY RELATIONSHIP TO FREQUENCY*
–10 Version (Calculation with t = 10 ns – 30 ns)
CLK
t
t
t
t
t
t
t
RRD
(20 ns)
RC
RAS
RP
CAC
RCD
RSC
(100 ns)
(60 ns)
(30 ns)
(24 ns)
(30 ns)
(20 ns)
CLK Period (t
30 ns
)
CLK
4
5
2
3
4
4
5
5
6
1
2
2
2
3
3
3
1
2
2
2
3
3
3
1
2
2
2
3
3
3
1
1
2
2
2
2
2
1
1
2
2
2
2
2
20 ns
18 ns
6
15 ns
7
13 ns
8
12 ns
9
10 ns
10
–12 Version (Calculation with t
CLK
= 12 ns – 36 ns)
t
t
t
t
t
t
t
RRD
(24 ns)
RC
RAS
RP
CAC
RCD
RSC
(120 ns)
(72 ns)
(36 ns)
(27.5 ns)
(36 ns)
(24 ns)
CLK Period (t
36 ns
)
CLK
4
5
2
3
4
4
5
6
6
1
2
2
2
3
3
3
1
2
2
2
3
3
3
1
2
2
2
3
3
3
1
1
2
2
2
2
2
1
1
2
2
2
2
2
24 ns
20 ns
6
18 ns
7
15 ns
8
14 ns
9
12 ns
10
* Units: clock cycles.
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
7
COMMAND INPUT TIMING
t
t
t
CH
CLK
CL
V
V
IH
IL
CLK
t
t
t
T
T
t
t
t
t
t
t
t
t
t
t
CMS
CMS
CMS
CMS
CMS
CMH
CMH
CMH
CMH
AH
CMH
CS
RAS
CAS
WE
t
AS
A0 – A10,
BA
t
t
t
CKH
CKH
CKH
t
t
t
CKS
CKS
CKS
CKE
COMMAND ISSUED
THIS CYCLE
COMMAND IGNORED THIS CYCLE
SINCE CKE LOW PREVIOUS CYCLE
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
8
READ TIMING
READ CAS LATENCY
CLK
CS
RAS
CAS
WE
A0 – A10,
BA
t
t
t
AC
AC
OH
HZ
OH
t
t
t
CAC
t
LZ
DQ
DATA OUT
DATA OUT
BURST LENGTH
READ COMMAND
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
9
CONTROL TIMING OF INPUT DATA (MC16S044T3B/MC16S084T3B)
WORD MASK
CLK
t
t
CMS
CMS
t
t
CMH
CMH
DQM
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DQ0 – DQ7
DATA IN
DATA IN
DATA IN
DATA IN
CLOCK MASK
CLK
t
t
CKS
CKS
t
t
CKH
CKH
CKE
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DQ0 – DQ7
DATA IN
DATA IN
DATA IN
DATA IN
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
10
CONTROL TIMING OF OUTPUT DATA (MC16S044T3B/MC16S084T3B)
OUTPUT ENABLE
CLK
t
t
CMS
CMS
t
t
CMH
CMH
DQM
t
t
t
t
t
AC
AC
HZ
AC
AC
t
t
t
t
LZ
t
OH
OH
OH
OH
DQ0 – DQ7
DATA OUT
DATA OUT
DATA OUT
OPEN
CLOCK MASK
CLK
t
t
CKS
CKS
t
t
CKH
CKH
CKE
t
t
t
t
AC
AC
AC
AC
t
t
t
t
OH
OH
OH
OH
DQ0 – DQ7
DATA OUT
DATA OUT
DATA OUT
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
11
CONTROL TIMING OF INPUT DATA (M116S163AST)
WORD MASK
CLK
t
t
CMS
CMS
t
t
CMH
CMH
LDQM
t
t
CMS
CMS
t
t
CMH
CMH
UDQM
t
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DQ0 – DQ7
DATA IN
t
DATA IN
t
DATA IN
DATA IN
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DATA IN
DATA IN
DATA IN
DQ8 – DQ15
DATA IN
CLOCK MASK
CLK
t
t
CKS
CKS
t
t
CKH
CKH
CKE
t
t
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DQ0 – DQ7
DATA IN
DATA IN
DATA IN
DATA IN
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DQ8 – DQ15
DATA IN
DATA IN
DATA IN
DATA IN
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
12
CONTROL TIMING OF OUTPUT DATA (M116S163AST)
OUTPUT ENABLE
CLK
t
t
CMS
CMS
t
t
t
CMH
CMH
LDQM
UDQM
t
t
CMS
CMS
t
CMH
CMH
t
t
t
t
t
AC
AC
HZ
AC
AC
t
t
t
t
t
OH
OH
OH
LZ
OPEN
OH
DQ0 – DQ7
DATA OUT
DATA OUT
DATA OUT
t
t
t
t
t
AC
AC
AC
AC
HZ
t
t
t
t
t
LZ
OH
OH
OH
OH
OPEN
DQ8 – DQ15
DATA OUT
DATA OUT
DATA OUT
CLOCK MASK
CLK
t
t
CKS
CKS
t
t
CKH
CKH
CKE
DQ0 – DQ7
DQ8 – DQ15
t
t
t
t
AC
AC
AC
AC
t
t
t
t
t
OH
OH
OH
OH
DATA OUT
DATA OUT
DATA OUT
DATA OUT
t
t
t
t
AC
AC
AC
AC
t
t
t
OH
OH
OH
OH
DATA OUT
DATA OUT
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
13
MODE REGISTER SET CYCLE
t
RSC
CLK
t
CMH
t
CMS
CS
t
CMH
CMH
t
CMS
RAS
t
t
CMS
CAS
t
CMH
t
CMS
WE
t
AH
t
AS
A0 – A10,
BA
REGISTER SET DATA
NEXT COMMAND
Burst Length
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BA
A2
0
A1
0
A0 Sequential
Interleave
Burst Length
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Addressing Mode
CAS Latency
0
0
0
1
0
1
1
0
0
0
1
0
Reserved
Full Page
(Test Mode)
Reserved
1
1
Reserved
1
1
Write Mode
0
0
Reserved
A3
0
Addressing Mode
Sequential
Interleave
1
A6
0
A5
0
A4
0
CAS Latency
Reserved
0
0
1
1
0
1
0
2
3
0
1
1
1
x
x
Reserved
A9
0
Single Write Mode
Burst Read and Burst Write
Burst Read and Single Write
1
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
14
OPERATING TIMING EXAMPLES (–10 VERSION) (CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
t
RC
RC
t
RC
RAS
t
t
t
RAS
t
RP
RAS
RP
t
t
RAS
RP
CAS
WE
BA
RAa
RAa
RAb
RAb
RAc
RAc
RAd
RAe
A10
t
RCD
t
t
t
RCD
RCD
RCD
A0 – A9
CAw
CBx
CAy
RAd
CBz
RAe
DQM
CKE
t
t
CAC
t
CAC
t
CAC
CAC
DQ
AW0
AW1
AW2 AW3
BX0 BX1
BX2
BX3
CY0
CY1
CY2
CY3
t
t
t
t
RRD
RRD
RRD
RRD
BANK 0
BANK 1
ACTIVE
READ
PRECHARGE
READ
ACTIVE
READ
PRECHARGE
PRECHARGE
READ
ACTIVE
ACTIVE
ACTIVE
Figure 2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
t
RC
RC
t
RC
RAS
t
t
t
RAS
t
RP
RAS
RP
t
t
RP
RAS
CAS
WE
BA
t
RCD
t
RCD
t
RCD
t
RCD
RAa
RAa
RBb
RBb
RAc
RAc
RBd
RAe
RAe
A10
A0 – A9
CBx
RBd
CAw
CAy
CBz
DQM
CKE
t
t
t
t
CAC
CAC
CAC
CAC
BX3
DQ
CY0
CY1
CY2
t
CY3
AW0
AW1 AW2
AW3
BX0
BX1 BX2
DZ0
t
t
t
RRD
RRD
RRD
RRD
BANK 0
BANK 1
ACTIVE
READ
AP*
ACTIVE
READ
AP*
AP*
ACTIVE
ACTIVE
READ
ACTIVE
READ
* AP is internal precharge start timing.
Figure 3. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
16
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
RAS
t
t
RP
RAS
t
t
RAS
RP
CAS
WE
BA
t
RCD
t
t
RCD
RCD
RAa
RAa
RBb
RBb
RAc
A10
A0 – A9
CBy
RAc
CAx
CAz
DQM
CKE
t
CAC
t
t
CAC
CAC
CZ0
AX0
AX1
AX2
AX3
AX4
AX5
AX6
BY0
BY1
BY4
BY5
BY6
BY7
DQ
t
t
RRD
RRD
BANK 0
BANK 1
ACTIVE
READ
PRECHARGE
PRECHARGE
ACTIVE
READ
ACTIVE
READ
PRECHARGE
Figure 4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
17
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
t
RC
CS
RAS
t
t
RP
RAS
t
RAS
CAS
WE
BA
t
RCD
t
t
RCD
RCD
RAa
RAa
RBb
RBb
RAc
A10
A0 – A9
RAc
CAx
CBy
CAz
DQM
CKE
t
CAC
t
t
CAC
CAC
CZ0
DQ
AX0
AX1
AX2
AX3
AX4
AX5
t
AX6
AX7
BY0
BY1
BY4
BY5
BY6
t
RRD
RRD
BANK 0
BANK 1
ACTIVE
READ
AP*
ACTIVE
READ
ACTIVE
READ
AP*
* AP is internal precharge start timing.
Figure 5. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
18
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
RAS
t
RAS
t
RP
t
RAS
CAS
WE
BA
t
RCD
t
t
RCD
RCD
RAa
RAa
RBb
RBb
RAc
RAc
A10
A0 – A9
CAz
CAx
CBy
DQM
CKE
DQ
AX0
AX1
AX4
AX5
AX6
AX7
BY0
BY1
BY2
BY3
BY4
BY5
BY6
BY7
CZ0
CZ1
CZ2
t
t
RRD
RRD
BANK 0
BANK 1
ACTIVE
WRITE
PRECHARGE
WRITE
ACTIVE
WRITE
ACTIVE
PRECHARGE
Figure 6. Interleaved Bank Write (Burst Length = 8)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
RAS
t
RAS
t
RP
t
RAS
CAS
WE
BA
t
RCD
t
t
RCD
RCD
RAa
RAa
RBb
RBb
RAc
RAc
A10
A0 – A9
CAz
CAx
CBy
DQM
CKE
CZ2
DQ
AX0
AX1
AX4
AX5
AX6
AX7
BY0
BY1
AP*
BY2
BY3
BY4
BY5
BY6
BY7
CZ0
CZ1
t
t
RRD
RRD
BANK 0
BANK 1
ACTIVE
WRITE
ACTIVE
WRITE
ACTIVE
WRITE
AP*
* AP is internal precharge start timing.
Figure 7. Interleaved Bank Write (Burst Length = 8, Auto Precharge)
MC16S044T3B•MC16S084T3B•M116S163AST
20
MOTOROLA DRAM
0
1
2
3
4
5
6
7
8
9
10
t
11
12
13
t
14
15
16
17
18
19
20
21
22
23
CLK
t
CCD
CCD
CCD
CS
t
RAS
t
RAS
RAS
CAS
WE
BA
t
RCD
t
RCD
RAa
RAa
RBb
RBb
A10
A0 – A9
CBx
CAm
CBz
CAl
CAy
DQM
CKE
t
CAC
t
t
t
t
CAC
CAC
CAC
CAC
AY1
DQ
AL0
AL1
AL2
AL3
BX0 BX1
AY0
AY2
AM0
AM1
AM2
BZ0
BZ1
BZ2
BZ3
t
RRD
BANK 0
BANK 1
ACTIVE
READ
READ
READ
PRECHARGE
ACTIVE
READ
READ
AP*
* AP is internal precharge start timing.
Figure 8. Page Mode Read (Burst Length = 4, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
21
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
t
RAS
CAS
WE
BA
t
RCD
RAa
RAa
A10
A0 – A9
CAx
CBy
DQM
CKE
t
CAC
t
WR
DQ
AX0
AX1
AX2
AX3
AX4
AX5
AY0
AY1
AY2
AY3
AY4
Q
Q
Q
Q
Q
Q
D
D
D
D
D
BANK 0
BANK 1
ACTIVE
READ
WRITE
PRECHARGE
NOTE: See Figures 17 and 20.
Figure 9. Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
22
MOTOROLA DRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
RAS
t
t
t
RAS
RAS
RP
CAS
WE
BA
t
RCD
t
RCD
A10
RAa
RAa
RAb
RAb
CAw
A0 – A9
CAx
DQM
CKE
t
t
CAC
CAC
AW0
AW1 AW2
AW3
DQ
BX1
BX0
BX2
AP*
BX3
BANK 0
BANK 1
ACTIVE
READ
AP*
ACTIVE
READ
* AP is internal precharge start timing.
NOTE: See Figure 15.
Figure 10. Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
23
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
t
RC
RC
RAS
t
t
t
RAS
t
RP
RAS
RP
CAS
WE
BA
t
t
RCD
RCD
RAa
RAa
RAb
RAb
RAc
A10
CAw
CAx
RAc
A0 – A9
DQM
CKE
AW0
AW1 AW2
AW3
DQ
BX0
BX1
BX2
BX3
BANK 0
BANK 1
ACTIVE
WRITE
AP*
ACTIVE
WRITE
AP*
ACTIVE
* AP is internal precharge start timing.
NOTE: See Figure 16.
Figure 11. Auto Precharge Write (Burst Length = 4)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
24
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
t
19
20
21
22
23
CLK
t
t
RC
RP
RC
CS
RAS
CAS
WE
BA
A10
A0 – A9
DQM
CKE
DQ
AUTO–REFRESH
(ARBITRARY CYCLE)
BOTH BANKS
PRECHARGE
AUTO–
REFRESH
Figure 12. Auto–Refresh Cycle
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
25
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RP
RAS
CAS
WE
BA
A0 – A10
DQM
CKE
t
t
CKS
t
CKS
SB
t
CKS
DQ
t
RC
NO OPERATION CYCLE
BOTH BANKS PRECHARGE
SELF–REFRESH CYCLE
SELF–REFRESH
ENTRY
ARBITRARY
CYCLE
Figure 13. Self–Refresh Cycle
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
26
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BA
RAa
RAa
RAa
A10
A0 – A9
CAa
RAa
CAa
DQM
CKE
t
t
SB
SB
t
t
CKS
t
CKS
t
CKS
CKS
DQ
AX0
AX1
AX2
AX3
ACTIVE
NOP
PRECHARGE
NOP
ACTIVE
ACTIVE STANDBY
POWER DOWN MODE
PRECHARGE STANDBY
POWER DOWN MODE
NOTES:
1. The Power Down mode is entered by asserting CKE low.
2. All input/output buffers (except CKE buffers) are turned off in the Power Down mode.
3. When CKE goes high, command input must be No Operation at next CLK rising edge.
Figure 14. Power Down Mode
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
27
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
t
RCD
WE
BS
RBa
RBa
A10
A0 – A9
CBw
CBx
CBy
CBz
CBv
DQM
CKE
DQ
t
t
CAC
CAC
AV0
AV1
AV2
AV3
AW0
AZ0
AZ1
AZ2
AZ3
AX0
AY0
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
SINGLE WRITE
ACTIVE
READ
READ
Figure 15. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
28
positive edges of CLK. When RAS and CS are asserted low
and CAS is asserted high, either the Bank Activate command
or the Precharge command is selected by the WE signal.
When WE is asserted high, the Bank Activate command is
selected and the bank designated by BA is turned on to the
active state. When WE is asserted low, the Precharge com-
mand is selected and the bank designated by BA is switched
to the idle state after precharge operation.
PIN FUNCTION
CLOCK INPUT (CLK)
The CLK input is used as the reference for SDRAM opera-
tions. All operations are synchronized to the positive edges
of CLK.
CLOCK ENABLE (CKE)
The CKE input is used to suspend the internal CLK. When
the CKE signal is asserted low, the internal CLK is sus-
pended and output data is held intact while CKE is asserted
low. When the device is not operating in the burst cycle, the
CKE input controls the entry to the Power Down mode.
COLUMN ADDRESS STROBE (CAS)
The CAS input defines the operation commands in con-
junction with the RAS and WE inputs, and is latched at the
positive edges of CLK. When RAS is held high and CS is
asserted low, the column access is started by asserting CAS
low. Then, the Read or Write command is selected by assert-
ing WE low or high.
BANK ACTIVATE (BA)
The 16M SDRAM family devices are organized as two
bank memory cell arrays. The BA input is latched at the time
of assertion of the operation commands and selects the bank
to be used for the operation. Whe BA is asserted low, bank 0
is selected. When BA is asserted high, bank 1 is selected.
WRITE ENABLE (WE)
The WE input defines the operation commands in conjunc-
tion with the RAS and CAS inputs, and is latched at the posi-
tive edges of CLK. The WE input is used to select the Bank
Activate or Precharge command and Read or Write com-
mand.
ADDRESS INPUTS (A0 – A10)
The A0 – A10 inputs are addressed to access the memory
cell array, as in the following table.
DATA INPUT/OUTPUT MASK (DQM OR LDQM, UDQM)
Part Number
M116S163AST
MC16S084T3B
MC16S044T3B
Row Address
A0 – A10
Column Address
A0 – A7
The DQM input functions as the output enable in a read
cycle and as the input data mask in a write cycle. When DQM
is asserted high at the positive edges of CLK, output data is
disabled after two clock cycles during a read cycle, and input
data is masked at the same clock cycle during a write cycle.
In the M116S163AST, the LDQM and UDQM input func-
tions as byte data control. The LDQM input can control DQ0
– DQ7 in a read or write cycle and the UDQM can control
DQ8 – DQ15 in a read or write cycle.
A0 – A10
A0 – A8
A0 – A10
A0 – A9
The row address bits are latched at the Bank Activate
command and column address bits are latched at the Read
or Write command. Also, the A0 – A10 inputs are used to set
the data in the Mode register during a mode register set
cycle.
DATA INPUT/OUTPUT (DQ0 – DQ15)
CHIP SELECT (CS)
The DQ0 – DQ15 input and output data are synchronized
with the positive edges of CLK. In the MC16S044T3B and
MC16S084T3B, these pins are DQ0 – DQ3 and DQ0 – DQ7.
The CS input controls the latching of the commands at the
positive edges of CLK when CS is asserted low. No com-
mands are latched as long as CS is held high.
OPERATION MODE
ROW ADDRESS STROBE (RAS)
Fully synchronous operations are performed to latch the
commands at the positive edges of CLK. See the following
Truth Table for operation commands.
The RAS input defines the operation commands in con-
junction with the CAS and WE input and is latched at the
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
29
TRUTH TABLE (See Notes 1 and 2)
DQM
(Note 3)
Command
Bank Activate
Device State CKE
CKE
BA
A10
A9 – A0
CS
RAS
CAS
WE
n–1
n
Idle
H
X
X
V
V
V
L
L
H
H
(Note 4)
Bank Precharge
Precharge All
Write
Any
Any
H
H
H
X
X
X
X
X
X
V
X
V
L
H
L
X
X
V
L
L
L
L
L
H
H
L
L
L
L
Active
H
(Note 4)
Write with Auto Precharge
Read
Active
(Note 4)
H
H
H
X
X
X
X
X
X
V
V
V
H
L
V
V
V
L
L
L
H
H
H
L
L
L
L
H
H
Active
(Note 4)
Read with Auto Precharge
Active
H
(Note 4)
Mode Register Set
No–Operation
Burst Stop
Idle
Any
H
H
H
X
X
X
X
X
X
V
X
X
V
X
X
V
X
X
L
L
L
L
H
H
L
H
H
L
H
L
Active
(Note 5)
Device Deselect
Auto–Refresh
Any
Idle
H
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
L
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
Self–Refresh Entry
Self–Refresh Exit
Idle
L
L
L
Idle
H
H
L
X
H
X
X
H
X
X
H
X
X
X
H
X
X
H
X
X
H
X
X
(Self–Refresh)
Active
Clock Suspend Mode Entry
Power Down Mode Entry
H
H
L
L
X
X
X
X
X
X
X
X
X
H
L
Any
(Note 6)
Clock Suspend Mode Exit
Power Down Mode Exit
Active
Any
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
(Power Down)
Active
Data Write/Output Enable
Data Write/Output Disable
NOTES:
H
H
X
X
L
X
X
X
X
X
X
X
X
Active
H
1. V = valid, X = don’t care, L = low level, H = high level.
2. CKE signal is input level when commands are provided. CKE
n
signal is input level one clock cycle before the commands are provided.
n–1
3. These are state of bank designated by BA signal.
4. Device state is full page burst operation.
5. LDQM, UDQM (M116S163AST).
6. Device state is not burst operation.
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
30
COMMAND FUNCTION
Read with Auto Precharge
(RAS = H, CAS = L, WE = H, BA = Bank, A10 = H,
A0 – A9 = Column Address)
Bank Activate
(RAS = L, CAS = H, WE = H, BA = Bank,
A0 – A10 = Row Address)
The Read with Auto Precharge command automatically
performs the precharge operation after the read operation.
This command must not be interrupted by any other com-
mand.
The A9 input is a don’t care for the MC16S084T3B and the
A8, A9 inputs are don’t care for the M116S163AST.
The Bank Activate command activates the bank desig-
nated by the BA (Bank Activate) signal.
Row addresses are latched on A0 to A10 at the time of this
command and the cell data is read out of the sense ampli-
fiers. The maximum time that each bank can be held in the
active state is specified as t
(max).
Mode Register Set
RAS
(RAS = L, CAS = L, WE = L,
BA, A0 – A10 = Register Data)
Bank Precharge
(RAS = L, CAS = H, WE = L, BA = Bank, A10 = L,
A0 – A9 = Don’t Care)
The Mode Register Set command programs the values of
CAS latency, Addressing mode, and burst length in the Mode
register. The default values of the Mode register after power–
up are undefined, therefore this command must be issued at
the power–up sequence.
The Bank Precharge command precharges the bank des-
ignated by BA. The precharged bank is switched from the
active state to the idle state.
Also, this command can be issued while both banks are in
the idle state.
Precharge All
(RAS = L, CAS = H, WE = L, BA = Don’t Care, A10 = H,
A0 – A9 = Don’t Care)
No–Operation
(RAS = H, CAS = H, WE = H)
The Precharge All command precharges both banks
simultaneously. Both banks are then switched to the idle
state.
The No–Operation command simply performs no opera-
tion (same command as Device Deselect).
Burst Stop
(RAS = H, CAS = H, WE = L)
Write
(RAS = H, CAS = L, WE = L, BA = Bank, A10 = L,
A0 – A9 = Column Address)
The Burst Stop command is used to stop the burst opera-
tion. This command is effective in full page burst operation.
This command assertion in any other burst length operation
is illegal.
The Write command performs the write operation to the
bank designated by BA. The write data is latched to be syn-
chronized to the positive edges of CLK. The length of the
write data (burst length) and column access sequence
(addressing mode) must be programmed in the Mode regis-
ter at power–up prior to the write operation.
Device Deselect
(CS = H)
The Device Deselect command disables the command de-
coder so that the RAS, CAS, WE, and Address inputs are
ignored. This command is similar to the No–Operation com-
mand.
The A9 input is a don’t care for the MC16S084T3B and the
A8, A9 inputs are don’t care for the M116S163AST.
Write with Auto Precharge
(RAS = H, CAS = L, WE = L, BA = Bank, A10 = H,
A0 – A9 = Column Address)
Auto–Refresh
(RAS = L, CAS = L, WE = H, CKE = H,
BA, A0 – A10 = Don’t Care)
The Write with Auto Precharge command performs the
precharge operation automatically after the write operation.
This command must not be interrupted by any other com-
mand.
The A9 input is a don’t care for the MC16S084T3B and the
A8, A9 inputs are don’t care for the M116S163AST.
The Auto–Refresh command is used to refresh the row ad-
dress provided by the internal refresh counter. Both banks (0
and 1) are refreshed alternately by the Auto–Refresh com-
mand and the refresh counter is automatically incremented.
The refresh operation must be performed 4096 times within
64 ms and the next command can be issued after t
from
RC
Read
the end of the Auto–Refresh command. To provide the Auto–
Refresh command, both banks have need to be in the idle
state. The Auto–Refresh operation is equivalent to the CAS
before RAS operation of the conventional DRAM.
(RAS = H, CAS = L, WE = H, BA = Bank, A10 = L,
A0 – A9 = Column Address)
The Read command performs the read operation to the
bank designated by BA. The read data is issued sequentially,
synchronized to the positive edges of CLK. The length of
read data (burst length), Addressing mode, and CAS latency
(access time from CAS command in clock cycle) must be
programmed in the Mode register at power–up prior to the
write operation.
Self–Refresh Entry
(RAS = L, CAS = L, WE = H, CKE = L,
BA, A0 – A10 = Don’t Care)
The Self–Refresh Entry command is used to enter the
Self–Refresh mode. While the device is in Self–Refresh
mode, all input and output buffers (except the CKE buffer)
are disabled and the refresh operation is automatically
The A9 input is a don’t care for the MC16S084T3B and the
A8, A9 inputs are don’t care for the M116S163AST.
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
31
performed. The Self–Refresh mode is exited by taking CKE
high (Self–Refresh Exit command).
When the precharge operation is performed in a bank dur-
ing a burst read operation, the burst operation is terminated
(Figure 22).
When the burst length is full page, column data is repeat-
edly read out until the Burst Stop command or Precharge
command is issued.
Self–Refresh Exit
(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)
This command is used to exit from the Self–Refresh mode.
Any subsequent commands can be issued after t
end of this command.
from the
RC
WRITE OPERATION
By providing the Write command after t
from the Bank
RCD
Clock Suspend Mode Entry/PowerDown Mode Entry
(CKE = L)
Activate command, the input data is latched sequentially to
synchronize to the positive edges of CLK from the Write
command (burst write operation). The burst length of write
data (burst length) and Addressing mode must be set in the
Mode register at power–up.
When the Write with Auto Precharge command is issued,
the precharge operation is performed automatically after the
write cycle and then the bank is switched to the idle state.
This command can not be interrupted by any other command
for the full length of the burst data. Also, when the burst
The internal CLK is suspended from the subsequent cycle
by issuing this command (asserting CKE low). The device
operation is held intact while CLK is suspended. On the other
hand, when the device is not operating in the burst cycle, this
command performs entry into the Power Down mode. All
input and output buffers (except the CKE buffer) are turned
off in the Power Down mode.
Clock Suspend Mode Exit/PowerDown Mode Exit
(CKE = H)
length is one and t
(min), the timing from the RAS com-
RCD
mand to the Auto Precharge operation is shorter than t
RAS
RCD
(min). Then, t
RAS
(Figures 11 and 18).
(min) must be satisfied by extending t
When the internal CLK has been suspended, the operation
of the internal CLK is resumed by providing this command
(asserting CKE high). When the device is in the Power Down
mode, the device exits this mode and all disabled buffers are
turned on to the active state. Any subsequent commands
can be issued after one clock cycle from the end of this com-
mand.
When the precharge operation is performed in a bank dur-
ing a burst write operation, the burst operation is terminated
(Figure 22).
When the burst length is full page, the input data is repeat-
edly latched until the Burst Stop command or the Precharge
command is issued.
When the Burst Read and Single Write mode is selected,
the write burst length is one, regardless of the read burst
length.
Data Write/Output Enable, Data Mask/Output Disable
(DQM = L/H or LDQM/UDQM = L/H)
During a write cycle, the DQM or LDQM/UDQM signal
functions as Data Mask and can control every word of the in-
put data. During a read cycle, the DQM or LDQM/UDQM
functions as the control of output buffers.
The LDQM signal controls DQ0 – DQ7 and the UDQM sig-
nal controls DQ8 – DQ15.
PRECHARGE
The precharge operation is performed by two commands,
Bank Precharge and Precharge All. When the Bank Pre-
charge command is issued to the active bank, the bank is
precharged and then switched to the idle state. The Bank
Precharge command can precharge one bank independently
from the other bank or hold the unprecharged bank in the
active state. The maximum time each bank can be held in the
READ OPERATION
By providing the Bank Activate command to the idle bank,
the bank is turned on to the active state. When the Read
active state is specified as t
bank must be precharged within t
Activate command.
(max). Therefore, each
RAS
command is issued after t
from the Bank Activate com-
RCD
(max) from the Bank
RAS
mand, the data is sequentially read out synchronized to the
positive edges of CLK (burst read operation). The initial read
The Precharge All command can be used to precharge
both banks simultaneously. Even if both banks are not in the
active state, the Precharge All command can be issued. In
this case, the precharge operation is performed only for the
active bank and the precharged bank is then switched to the
idle state.
data becomes available after a time of t
from the issuance of the Read command. The value of t
in clock cycles
CAC
CAC
in clock cycles (CAS latency) must be set in the Mode regis-
ter at power–up. In addition, the burst length of read data and
Addressing mode must be programmed. Each bank is held in
the active state unless the Precharge command is asserted
so that the sense amplifiers can be used as a secondary
cache.
PAGE MODE
When the Read with Auto Precharge command is issued,
the precharge operation is performed automatically after the
read cycle and then the bank is switched to the idle state.
This command can not be interrupted by any other com-
The Read or Write command can be issued at any clock
cycle.
Whenever a read operation is to be interrupted by a Write
command, the output data must be masked by DQM to avoid
I/O contention. Also, when a write operation is to be inter-
rupted by the Read command, only the input data before the
Read command is enabled and the input data after the Read
command is disabled.
mand. Also, when the burst length is one and t
(min), the
RCD
timing from the RAS command to the Auto Precharge opera-
tion is shorter than t (min). Then, t (min) must be sa-
RAS
tisfied by extending t
RAS
(Figures 10 and 17).
RCD
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
32
BURST TERMINATION
A2
0
A1
0
A0
0
Burst Length
1 word
When the Precharge command is issued for the bank in a
burst cycle, the burst operation is terminated. When the burst
read cycle is interrupted by the Precharge command, read
operation is disabled after clock cycle of (CAS latency – 1)
from the Precharge command (Figure 22). When the burst
write cycle is interrupted by the Precharge command, the in-
put circuit is reset at the same clock cycle at which the Pre-
charge command is issued. In this case, the DQM signal
must be asserted high to prevent writing the invalid data to
the cell array (Figure 22).
0
0
1
2 words
0
1
0
4 words
0
1
1
8 words
1
1
1
Full Page
Addressing Mode Select (A3)
The Addressing mode can be one of two modes: Inter-
leave mode or Sequential mode (Table 1). When the A3 bit is
0, Sequential mode is selected. When the A3 bit is 1, Inter-
leave mode is selected. Both addressing modes support
burst lengths of 1, 2, 4, and 8. Additionally, the Sequential
mode supports full page burst.
When the Burst Stop command is issued for the bank in a
full page burst cycle, the burst operation is terminated. When
the Burst Stop command is issued during full page burst read
cycle, read operation is disabled after clock cycle of (CAS
latency – 1) from the Burst Stop command. When the Burst
Stop command is issued during full page burst write cycle,
the write operation is disabled at the same clock cycle at
which the Burst Stop command is issued (Figure 21).
A3
0
Addressing Mode
Sequential
MODE REGISTER OPERATION
1
Interleave
The Mode register designates the operation mode at the
read or write cycle. This register is divided into three fields: a
Burst Length field to set the length of burst data, an Addres-
sing Mode Selected Bits field to designate the column
access sequence in a burst cycle, and a CAS Latency field to
set the access time at clock cycle.
The Mode register is programmed by the Mode Register
Set command when both banks are in the idle state. The
data to be set in the Mode register is transferred using A0 –
A10 address inputs. The default value of the Mode register
after power–up is undefined; therefore, the Mode Register
Set command must be issued before proper operation.
CAS Latency Field (A6 – A4)
This field specifies the number of clock cycles from the
assertion of the Read command to first read data. The mini-
mum values of CAS latency depend on the frequency of
CLK. The minimum value satisfying the following formula
must be programmed in this field.
t
(min)
CAS Latency x t
CLK
CAC
A6
0
A5
0
A4
1
CAS Latency
1 clock
Burst Length Field (A2 – A0)
This field specifies the data length of column access using
the A2 – A0 pins and selects the burst length to be 1, 2, 4, 8,
or full page.
0
1
0
2 clock
0
1
1
3 clock
Table 1.
Burst Length Starting Address (A2 A1 A0)
Sequential Addressing (Decimal)
0, 1
Interleave Addressing (Decimal)
0, 1
2
xx0
xx1
x00
x01
x10
x11
000
001
010
011
100
101
110
111
1, 0
1, 0
4
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
3, 0, 1, 2
3, 2, 1, 0
8
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
33
Test Mode Entry Bit (A7)
The Self–Refresh mode is entered by providing the Self–
Refresh command (CKE asserted low) when both banks are
in the idle state. The device is in the Self–Refresh mode
while CKE is held low. By entering the Self–Refresh mode,
all input/output buffers (except CKE buffer) are disabled, re-
sulting in lower power dissipation (Figure 13).
This bit is used to enter the test mode and must be pro-
grammed to 0 in normal operation.
Reserved Bits (A8, A10, BA)
These bits are reserved for future operations. They must
be set to 0 in normal operation.
POWER DOWN MODE
Single Write Mode (A9)
When the device enters the Power Down mode, all input/
output buffers (except CKE buffer) are disabled, resulting in
lower power dissipation in standby. The Power Down mode
is entered by asserting CKE low when the device is not oper-
ating the burst cycle. Exit from this mode is performed by tak-
ing CKE high. When CKE goes high, command input must
be No–Operation at next CLK rising edge (Figure 14).
This bit is used to select the write mode. When the A9 bit is
0, Burst Read and Burst Write mode is selected. When the
A9 bit is 1, Burst Read and Single Write mode is selected.
A9
0
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
CLK SUSPENSION AND INPUT/OUTPUT MASK
1
While the device is operating in the burst cycle, the internal
CLK is suspended by asserting CKE low and is frozen from
the next cycle. A Read/Write operation is held intact until the
CKE signal is taken high.
The output disable/write mask signal (DQM) has two func-
tions: controlling the output data in a read cycle and perform-
ing word mask in a write cycle. When the DQM is asserted
high at the positive edge of CLK, the output data is disabled
after two clock cycles for a read and the output data is
masked at the same clock cycle for a write. The timing rela-
tion of CKE to DQM is described in Figures 16a and 16b.
REFRESH OPERATION
Two types of refresh can be performed on the device:
Auto–Refresh and Self–Refresh. Auto–Refresh is similar to
the CAS before RAS Refresh of conventional DRAMs and is
performed by issuing the Auto–Refresh command when both
banks are in the idle state. By repeating the Auto–Refresh
cycle, each bank is in turn, refreshed automatically. The re-
fresh operation must be performed 4096 times (rows) within
64 ms (Figure 12). The period between the Auto–Refresh
command and the next command is specified by t
.
RC
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
34
CLK
CYCLE NO.
1
1
1
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
CLK
CLK
CLK
DQM
DQ
D1
D1
D1
D2
D3
D5
D6
DQM MASK
CKE MASK
(1)
CLK
CYCLE NO.
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
DQM
DQ
D2
D3
D5
D6
DQM MASK
CKE MASK
(2)
CLK
CYCLE NO.
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
DQM
DQ
D2
D3
D4
D5
D6
CKE MASK
(3)
(a) Write Cycle
Figure 16. CKE/DQM Input Timing
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
35
CLK
CYCLE NO.
1
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
CLK
DQM
DQ
Q1
Q2
Q3
Q4
Q6
OPEN
OPEN
(1)
CLK
CYCLE NO.
1
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
CLK
DQM
DQ
Q1
Q2
Q3
Q4
Q6
OPEN
(2)
CLK
CYCLE NO.
1
2
3
4
5
6
7
EXTERNAL
INTERNAL
CKE
CLK
DQM
DQ
Q1
Q2
Q3
Q4
Q5
Q6
(3)
(b) Read Cycle
Figure 16. CKE/DQM Input Timing (continued)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
36
0
1
2
3
4
5
6
7
8
9
10
11
12
13
1. CAS LATENCY = 1
(A) BURST LENGTH = 1
COMMAND
READ
AP
Q0
ACT
t
RP
DQ
(B) BURST LENGTH = 2
COMMAND
READ
READ
READ
AP
Q1
ACT
t
RP
Q0
Q0
DQ
DQ
(C) BURST LENGTH = 4
COMMAND
AP
Q3
ACT
t
RP
Q1
Q1
Q2
Q2
(D) BURST LENGTH = 8
COMMAND
AP
Q7
ACT
t
RP
Q0
AP
Q3
Q4
Q5
Q6
DQ
DQ
2. CAS LATENCY = 2
(A) BURST LENGTH = 1
COMMAND
ACT
READ
t
RP
Q0
(B) BURST LENGTH = 2
COMMAND
AP
Q0
ACT
READ
READ
READ
t
RP
Q1
DQ
DQ
DQ
(C) BURST LENGTH = 4
COMMAND
AP
Q2
ACT
t
RP
Q0
Q0
Q1
Q1
Q3
(D) BURST LENGTH = 8
COMMAND
AP
Q6
ACT
t
RP
Q2
Q3
Q4
Q5
Q7
NOTES:
READ
1.
2.
3.
shows the Read with Auto Precharge command.
shows internal precharge start timing.
shows the Bank Activate command.
AP
ACT
4. When the Auto Precharge command is asserted, the period to internal precharge start from the Bank Activate command
must satisfy t
(min).
RAS
Figure 17. Auto Precharge Timing (Read Cycle)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
37
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3. CAS LATENCY = 3
(A) BURST LENGTH = 1
COMMAND
READ
AP
ACT
t
RP
Q0
DQ
(B) BURST LENGTH = 2
COMMAND
READ
READ
AP
Q0
ACT
t
RP
Q1
Q1
DQ
DQ
(C) BURST LENGTH = 4
COMMAND
AP
Q2
ACT
t
RP
Q3
Q3
Q0
Q0
(D) BURST LENGTH = 8
COMMAND
READ
AP
Q6
ACT
t
RP
Q1
Q2
Q4
Q5
Q7
DQ
NOTES:
READ
AP
1.
2.
3.
shows the Read with Auto Precharge command.
shows internal precharge start timing.
shows the Bank Activate command.
ACT
4. When the Auto Precharge command is asserted, the period to internal precharge start from the Bank Activate command
must satisfy t (min).
RAS
Figure 17. Auto Precharge Timing (Read Cycle) (continued)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
38
0
1
2
3
4
5
6
7
8
9
10
11
12
13
1. CAS LATENCY = 1
(A) BURST LENGTH = 1
COMMAND
WRITE
AP
ACT
t
t
WR
RP
DQ
D0
(B) BURST LENGTH = 2
COMMAND
WRITE
t
AP
ACT
t
WR
RP
D0
D1
D1
DQ
DQ
(C) BURST LENGTH = 4
COMMAND
WRITE
D0
AP
ACT
t
t
WR
RP
D2
D2
D3
(D) BURST LENGTH = 8
COMMAND
WRITE
D0
AP
ACT
t
t
RP
WR
D7
D1
AP
D3
D4
D5
D6
DQ
DQ
2. CAS LATENCY = 2
(A) BURST LENGTH = 1
COMMAND
ACT
WRITE
t
t
RP
WR
D0
(B) BURST LENGTH = 2
COMMAND
WRITE
t
AP
ACT
AP
t
RP
WR
D0
D1
D1
D1
DQ
DQ
DQ
(C) BURST LENGTH = 4
COMMAND
ACT
WRITE
D0
t
t
RP
WR
D2
D3
D3
(D) BURST LENGTH = 8
COMMAND
WRITE
D0
AP
ACT
t
t
WR
RP
D2
D4
D5
D6
D7
NOTES:
WRITE
AP
1.
2.
3.
shows the Write with Auto Precharge command.
shows internal precharge start timing.
shows the Bank Activate command.
ACT
4. When the Auto Precharge command is asserted, the period to internal precharge start from the Bank Activate command
must satisfy t
(min).
RAS
Figure 18. Auto Precharge Timing (Write Cycle)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
39
0
1
2
3
4
5
6
7
8
9
10
11
12
13
3. CAS LATENCY = 3
(A) BURST LENGTH = 1
COMMAND
WRITE
D0
AP
ACT
t
t
RP
WR
DQ
(B) BURST LENGTH = 2
COMMAND
WRITE
D0
AP
ACT
t
t
RP
WR
DQ
DQ
D1
(C) BURST LENGTH = 4
COMMAND
AP
WRITE
D0
ACT
t
t
RP
WR
D1
D1
D2
D2
D3
D3
(D) BURST LENGTH = 8
COMMAND
WRITE
D0
AP
ACT
t
t
RP
WR
D4
D5
D6
D7
DQ
NOTES:
WRITE
AP
1.
2.
3.
shows the Write with Auto Precharge command.
shows internal precharge start timing.
shows the Bank Activate command.
ACT
4. When the Auto Precharge command is asserted, the period to internal precharge start from the Bank Activate command
must satisfy t (min).
RAS
Figure 18. Auto Precharge Timing (Write Cycle) (continued)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
40
BURST LENGTH = 4
1. CAS LATENCY = 1
(A) COMMAND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
READ WRITE
DQM
DQ
D0
D1
D2
D3
WRITE
READ
(B) COMMAND
DQM
DQ
D0
D1
D2
D3
Q0
2. CAS LATENCY = 2
(A) COMMAND
WRITE
D0
READ
DQM
DQ
D1
D2
D3
(B) COMMAND
READ
WRITE
DQM
DQ
D1
D2
D3
D0
3. CAS LATENCY = 3
(A) COMMAND
READ WRITE
DQM
DQ
D0
D1
D2
D3
READ
(B) COMMAND
WRITE
DQM
DQ
D0
D1
D2
D3
NOTE: The output data must be masked by DQM to avoid I/O contention.
Figure 19. Timing Chart of Read to Write Cycle
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
41
BURST LENGTH = 4
1. CAS LATENCY = 1
(A) COMMAND
0
1
2
3
4
5
6
7
8
9
10
11
12
13
WRITE READ
DQM
DQ
D0
Q0
Q1
Q2
Q3
WRITE
READ
(B) COMMAND
DQM
DQ
D1
Q0
Q1
D0
Q2
Q3
2. CAS LATENCY = 2
(A) COMMAND
WRITE READ
DQM
DQ
D0
Q0
Q1
Q2
Q3
(B) COMMAND
WRITE
READ
DQM
DQ
D1
D0
Q0
Q1
Q2
Q3
3. CAS LATENCY = 3
(A) COMMAND
WRITE READ
DQM
DQ
D0
Q0
Q1
Q2
Q3
READ
(B) COMMAND
WRITE
DQM
DQ
D0
D1
Q0
Q1
Q2
Q3
Figure 20. Timing Chart of Write to Read Cycle
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
42
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BURST LENGTH = 8
1. READ CYCLE
A. CAS LATENCY = 1
COMMAND
READ
BST
Q4
Q0
Q1
Q2
Q1
Q0
Q3
Q2
Q1
DQ
B. CAS LATENCY = 2
COMMAND
READ
READ
BST
Q3
Q0
Q4
DQ
C. CAS LATENCY = 3
COMMAND
BST
Q2
DQ
Q3
Q4
2. WRITE CYCLE
COMMAND
WRITE
D0
BST
D4
D1
D2
D3
DQ
NOTES:
1.
BST
shows the Burst Stop command.
2. Burst Stop command is effective in full page cycle.
Figure 21. Timing Chart of Burst Stop Cycle (Burst Stop Command)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
43
BURST LENGTH = 8
1. READ CYCLE
0
1
2
3
4
5
6
7
8
9
10
11
12
A. CAS LATENCY = 1
COMMAND
READ
PRCG
Q4
Q0
Q1
Q0
Q2
Q3
DQ
B. CAS LATENCY = 2
COMMAND
PRCG
Q3
READ
READ
Q1
Q0
Q2
Q1
Q4
Q3
DQ
C. CAS LATENCY = 3
COMMAND
PRCG
Q2
DQ
2. WRITE CYCLE
A. CAS LATENCY = 1
COMMAND
WRITE
PRCG
t
WR
DQM
DQ
D4
D1
D2
D3
D0
B. CAS LATENCY = 2
COMMAND
WRITE
PRCG
PRCG
t
WR
DQM
DQ
D4
D0
D1
D2
D3
C. CAS LATENCY = 3
COMMAND
WRITE
t
WR
DQM
DQ
D0
D1
D2
D3
Figure 22. Timing Chart of Burst Stop Cycle (Precharge Command)
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
44
ORDERING INFORMATION
(Order by Full Part Number)
x4, x8 DEVICE NUMBERS
MC 16Sxx4T3BTN XX
X
Motorola Memory Prefix
Shipping Method (R = Tape and Reel,
T = Trays)
Part Number (xx: 04 for x4, 08 for x8)
Speed (10 = 10 ns, 12 = 12 ns)
Full Part Numbers — MC16S044T3BTN10T
MC16S044T3BTN12T
MC16S044T3BTN10R
MC16S044T3BTN12R
MC16S084T3BTN10T
MC16S084T3BTN12T
MC16S084T3BTN10R
MC16S084T3BTN12R
x16 DEVICE NUMBERS
M1
16S163AST
XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel,
Blank = Trays)
Speed (10 = 10 ns, 12 = 12 ns)
Full Part Numbers — M116S163AST10
M116S163AST12
M116S163AST10R
M116S163AST12R
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
45
PACKAGE DIMENSIONS
400 MIL
THIN SMALL OUTLINE
CASE 924B–01
H
VIEW A
B
44
23
4X
0.13
H
A2
E
E1
L
A
A
VIEW A
E /2
ROTATED 90 CLOCKWISE
2X 22 TIPS
0.2
1
22
A1
A
C
B
NOTES:
A
D
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSIONS SHALL
NOT ALLOW THE b DIMENSION TO EXCEED 0.53.
44X
c
0.1
C
MILLIMETERS
DIM
A
A1
A2
b
c
D
e
E
MIN
–––
0.90
0.05
0.23
0.13
MAX
1.20
1.10
0.20
0.40
0.20
SEATING
PLANE
b
4X e /2
M
0.2
C A
C
42X
e
SECTION A–A
18.41 BSC
44 PLACES
0.80 BSC
11.76 BSC
10.16 BSC
0.40
0
E1
L
0.60
10
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
46
400 MIL
THIN SMALL OUTLINE
CASE 985C–01
VIEW A
B
50
26
E1
A A
1
25
D
A
A
25X E
M
0.2 (0.800)
C B
C
0.1 (0.004)
C
A2
L
SEATING
PLANE
48X e
C
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 (0.006) PER SIDE.
4. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.48
(0.019).
R (R1)
R (R2)
MILLIMETERS
INCHES
DIM
A
A1
A2
b
MIN
–––
MAX
1.20
0.15
1.05
0.40
0.20
21.05
MIN
MAX
0.047
0.006
0.041
0.016
0.008
0.829
–––
0.002
0.037
0.009
0.005
0.821
c
0.05
0.95
0.24
0.12
20.85
c
D
A1
b
L
e
0.80 BSC
0.0315 BSC
M
E
E1
L
R1
R2
11.56
10.06
0.40
11.96
10.26
0.60
0.455
0.396
0.016
0.471
0.404
0.024
0.13 (0.005)
C A
VIEW A
ROTATED 90 CW
SECTION A–A
0.10 REF
0.10 REF
10
0.004 REF
0.004 REF
10
50 PLACES
0
0
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
MC16S044T3B•MC16S084T3B•M116S163AST
MOTOROLA DRAM
47
Mfax is a trademark of Motorola, Inc.
How to reach us:
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INTERNET: http://www.mot.com/SPS/
MC16S044T3B/D
◊
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