MAC7100CVF_技术文档

Freescale Semiconductor, Inc.

Advance Information

MAC7100EC/D

Rev. 0.1, 10/2003

MAC7100 Microcontroller

Family Hardware

Specifications

32-bit Embedded

This document provides electrical specifications, pin assignments, and package diagrams for

MAC7100 family of microcontroller devices. For functional characteristics of the family,

refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D).

Controller Division

This document contains the following topics:

Topic

Page

Section 1, “Overview”

1

2

Section 2, “Ordering Information”

Section 3, “Electrical Characteristics”

Section 4, “Device Pin Assignments”

Section 5, “Mechanical Information”

3

36

41

1 Overview

The MAC7100 Family of microcontrollers (MCUs) are members of a pin-compatible family

of 32-bit Flash-memory-based devices developed specifically for embedded automotive

applications. The pin-compatible family concept enables users to select between different

memory and peripheral options for scalable designs. All MAC7100 Family members are

composed of a 32-bit central processing unit (ARM7TDMI-S), up to 512Kbytes of embedded

Flash EEPROM for program storage, up to 32Kbytes of embedded Flash for data and/or

program storage, and up to 32Kbytes of RAM. The family is implemented with an enhanced

DMA (eDMA) controller to improve performance for transfers between memory and many of

the on-chip peripherals. The peripheral set includes asynchronous serial communications

interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I²C) bus

controllers, FlexCAN interfaces, an enhanced modular I/O subsystem (eMIOS), 10-bit

analog-to-digital converter (ATD) channels, general-purpose timers (PIT) and two

special-purpose timers (RTI and SWT). The peripherals share a large number of general

purpose input-output (GPIO) pins, all of which are bidirectional and available with interrupt

capability to trigger wake-up from low-power chip modes.

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to

suit operational requirements. The operating frequency of devices in the family is up to a

maximum of 50 MHz. The internal data paths between the CPU core, eDMA, memory and

peripherals are all 32 bits wide, further improving performance for 32-bit applications. The

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Ordering Information

MAC7111 and MAC7131 also offer a 16-bit wide external data bus with 22 address lines. The family of

devices is capable of operating over a junction temperature range of -40° C to 150° C.

Table 1 provides a comparison of members of the MAC7100 Family and the availability of peripheral

modules on the various devices.

Table 1. MAC7100 Family Device Derivatives

Module Options

MAC7101

MAC7111

MAC7121

MAC7131

MAC7141

Program Flash

Data Flash

512Kbytes

32Kbytes

SRAM

32Kbytes

External Bus

ATD Modules

CAN Modules

eSCI Modules

DSPI Modules

I²C Modules

eMIOS Module

No

2

Yes

1

No

1

Yes

2

No

1

4

2

4

2

1

16 channels,

16-bit

16 channels,

16-bit

16 channels,

16-bit

16 channels,

16-bit

16 channels,

16-bit

Timer Module

10 channels,

24-bit

10 channels,

24-bit

10 channels,

24-bit

10 channels,

24-bit

10 channels,

24-bit

GPIO Pins (max.)

Package

111

84

127

71

144 LQFP

112 LQFP

208 MAP BGA

100 LQFP

2 Ordering Information

M AC 7 1 0 1 C PV 50 xx

MC Status

Core Code

Core Number

Temperature Option

C = –40° C to 85° C

V = –40° C to 105° C

M = –40° C to 125° C

Generation / Family

Package Option

Device Number

Package Option

FU = 100 QFP

PV = 112 / 144 LQFP

VF = 208 MAP BGA

Temperature Range

Package Identifier

Speed (MHz)

Optional Package Identifiers

Figure 1. Order Part Number Example

2

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ElectricalCharacteristics

3 Electrical Characteristics

This section contains electrical information for MAC7100 Family microcontrollers. The information is

preliminary and subject to change without notice.

MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any

voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done

to verify operation at intermediate supply voltage levels.

3.1 Parameter Classification

The electrical parameters shown in this appendix are derived by various methods. To provide a better

understanding to the designer, the following classification is used. Parameters are tagged accordingly in in

the column labeled “C” of the parametric tables, as appropriate.

Table 2. Parametric Value Classification

P

C

Parameters guaranteed during production testing on each individual device.

Parameters derived by the design characterization and by measuring a statistically relevant

sample size across process variations.

T

Parameters derived by design characterization on a small sample size from typical devices

under typical conditions (unless otherwise noted). All values shown in the typical column

are within this classification, even if not so tagged.

D

Parameters derived mainly from simulations.

3.2 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not

guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device.

MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or

electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if

unused inputs are tied to an appropriate logic voltage level (for example, either V_SS5 or V_DD5).

Table 3. Absolute Maximum Ratings

Num

Rating

Symbol

V_DD

Min

Max

Unit

A1

A2

A3

A4

A5

A6

A7

A8

A9

I/O, Regulator and Analog Supply Voltage

Digital Logic Supply Voltage ¹

PLL Supply Voltage ¹

5

–0.3

–6.5

–0.3

+6.0

+3.0

+6.5

+6.0

+0.3

+6.5

+6.0

V

V_DD2.5

V_DDPLL

ATD Supply Voltage

V_DDA

Analog Reference

V_RH,V_RL

Voltage difference V_DDX to V_DD

A

∆

VDDX

Voltage difference V_SSX to V_SS

Voltage difference V_RH– V_RL

Voltage difference V_DDA – V_RH

A

∆

VSSX

V_RH– V_RL

V_DDA – V_RH

V_IN

A10 Digital I/O Input Voltage

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

3

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

Table 3. Absolute Maximum Ratings (continued)

Num

Rating

Symbol

Min

Max

Unit

A11 XFC, EXTAL, XTAL inputs

V_ILV

–0.3

+3.0

V

A12 TEST input

V_TEST

+10.0

Instantaneous Maximum Current ²

A13

A14

A15

A16

Single pin limit for XFC, EXTAL, XTAL ³

Single pin limit for all digital I/O pins ⁴

Single pin limit for all analog input pins ⁴

I_DL

I_D

–25

+25

0

mA

°C

I_DA

I_DT

T_stg

–25

5

Single pin limit for TEST

–0.25

–65

A17 Storage Temperature Range

+155

1

2

The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The

absolute maximum ratings apply when the device is powered from an external source.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values using V_POSCLAMP= V_DDA + 0.3 V and V_NEGCLAMP= –0.3 V, then use the larger of the

calculated values.

These pins are internally clamped to V_SSPLL and V_DDPLL.

All I/O pins are internally clamped to V_SSX and V_DDX, V_SSR and V_DDR or V_SSA and V_DDA.

This pin is clamped low to V_SSX, but not clamped high, and must be tied low in applications.

3

4

5

3.3 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade

Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body

Model (HBM), the Machine Model (MM) and the Charge Device Model.

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification. Complete DC parametric and functional testing is performed per the applicable device

specification at room temperature followed by hot temperature, unless specified otherwise.

Table 4. ESD and Latch-up Test Conditions

Model

Description

Symbol

Value

Unit

Human Body

Series Resistance

R1

C

1500

100

Ohm

pF

Storage Capacitance

Number of Pulses per pin

positive

—

3

negative

3

Machine

Latch-up

Series Resistance

R1

C

0

Ohm

pF

Storage Capacitance

200

Number of Pulse per pin

positive

negative

—

3

Minimum input voltage limit

Maximum input voltage limit

–2.5

7.5

V

4

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ElectricalCharacteristics

Table 5. ESD and Latch-Up Protection Characteristics

Num

C

Rating

Symbol

Min

Max

Unit

B1

B2

B3

B4

C Human Body Model (HBM)

C Machine Model (MM)

V_HBM

V_MM

V_CDM

I_LAT

2000

200

—

V

C Charge Device Model (CDM)

500

V

C Latch-up Current at T_A= 125°C

mA

positive

negative

+100

–100

—

B5

C Latch-up Current at T_A= 27°C

I_LAT

mA

positive

negative

+200

–200

3.4 Operating Conditions

Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature

rating of the device (C, V, M) with respect to ambient temperature (T_A) and junction temperature (T_J). For

power dissipation calculations refer to Section 3.5, “Power Dissipation and Thermal Characteristics.”

Table 6. MAC7100 Family Device Operating Conditions

Num

Rating

Symbol

V_DD

_DD2.5

V_DDPLL

_VDDX

Min

Typ

Max

Unit

C1 I/O, Regulator and Analog Supply Voltage

C2 Digital Logic Supply Voltage ¹

C3 PLL Supply Voltage ¹

5

4.5

2.35

–0.1

0.5

5

2.5

0

5.5

2.75

0.1

16

V

C4 Voltage Difference V_DDX to V_DD

A

∆

V

C5 Voltage Difference V_SSX to V_SS

C6 Oscillator Frequency

C7 Bus Frequency

A

∆

_VSSX

f_osc

f_bus

T_J

0

V

—

MHz

°C

0.5

50

C8a MAC7100C Operating Junction Temperature Range

–40

110

2

C8b

C9a MAC7100V Operating Junction Temperature Range

Operating Ambient Temperature Range ²

T_A

T_J

–40

25

—

85

°C

130

2

C9b

C10a MAC7100M Operating Junction Temperature Range

Operating Ambient Temperature Range ²

T_A

T_J

–40

25

—

105

150

°C

2

C10b

Operating Ambient Temperature Range ²

T_A

–40

25

125

°C

1

The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The

absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source.

Please refer to Section 3.5, “Power Dissipation and Thermal Characteristics,” for more details about the relation

between ambient temperature T_Aand device junction temperature T_J.

2

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

5

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.4.1 5 V I/O Pins

The I/O pins operate at a nominal level of 5 V. This class of pins is comprised of the clocks, control and general

purpose/peripheral pins. The internal structure of these pins is identical; however, some functionality may be

disabled (for example, for analog inputs the output drivers, pull-up/down resistors are permanently disabled).

3.4.2 Oscillator Pins

The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5 V.

3.5 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum

operating junction temperature is not exceeded.

Note that the JEDEC specification reserves the symbol R

or θ_JA(Theta-JA) strictly for junction-to-

ambient thermal resistance on a 1s test board in natur^θa^Jl^Aconvection environment. R_θJMAor θ_JMA

(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for

junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic

name, θ_JA, will continue to be commonly used.

The average chip-junction temperature (T_J) in °C is obtained from:

T_J= T_A+ (Θ_JA

)

T_J= Junction Temperature ( C)

°

T_A= Ambient Temperature ( C)

°

P_D= Total Chip Power Dissipation (W)

Θ_JA= Package Thermal Resistance ( C/W)

°

The total power dissipation is calculated from:

P_D= P_INT+ P_IO

P_INT= Chip Internal Power Dissipation (W)

P_INT= (I_DD× V_DD) + (I_DDPLL × V_DDPLL) + (I_DDA × V_DDA)

Two cases for P_IO, with the internal voltage regulator enabled and disabled, must be considered:

1. Internal Voltage Regulator disabled:

2

P_IO

=

R_DSON⋅ (I_IO)

∑

i

P

_IOis the sum of all output currents on I/O ports associated with V_DDX and V_DDR.

V_OL

---------

(for outputs driven low)

R_DSON

=

I_OL

or

V_DD5 – V_OH

-------------------------------

I_OL

R_DSON

(for outputs driven high)

2. Internal voltage regulator enabled:

P_INT= (I_DDR × V_DDR) + (I_DDA × V_DDA)

I

_DDR is the current shown in Table 12 and not the overall current flowing into V_DDR, which

additionally contains the current flowing into the external loads with output high.

6

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ElectricalCharacteristics

3.5.1 Power Dissipation Simulation Details

1

Table 7. Thermal Resistance for 100 lead 14x14 mm LQFP, 0.5 mm Pitch

Rating

Value

44

34

37

29

18

7

Unit

Comments

Junction to Ambient (Natural Convection)

Junction to Ambient (@ 200 ft./min.)

Junction to Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

R

°C/W

1, 2

1, 3

4

θJA

R

θJMA

R

θJB

θJC

Junction to Case

R

5

Junction to Package Top

Natural Convection

Ψ

2

6

JT

1

100 LQFP, Case Outline: 983–02

1

Table 8. Thermal Resistance for 112 lead 20x20 mm LQFP, 0.65 mm Pitch

Rating

Value

42

34

35

30

22

7

Unit

Comments

Junction to Ambient (Natural Convection)

Junction to Ambient (@ 200 ft./min.)

Junction to Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

R

°C/W

1, 2

1, 3

4

θJA

R

θJMA

R

θJB

θJC

Junction to Case

R

5

Junction to Package Top

Natural Convection

Ψ

2

6

JT

1

112 LQFP, Case Outline: 987–01

1

Table 9. Thermal Resistance for 144 lead 20x20 mm LQFP, 0.5 mm Pitch

Rating

Value

42

34

35

30

22

7

Unit

°C/W

Comments

Junction to Ambient (Natural Convection)

Junction to Ambient (@ 200 ft./min.)

Junction to Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

R

1, 2

1, 3

4

θJA

R

θJMA

R

θJB

Junction to Case

R

θJC

5

Junction to Package Top

Natural Convection

Ψ

2

6

JT

1

144 LQFP, Case Outline: 918–03

1

Table 10. Thermal Resistance for 208 lead 17x17 mm MAP, 1.0 mm Pitch

Rating

Value

46

29

38

26

19

7

Unit

°C/W

Comments

Junction to Ambient (Natural Convection)

Junction to Ambient (@ 200 ft./min.)

Junction to Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

R

1, 2

1, 3

4

θJA

R

θJMA

R

θJB

θJC

Junction to Case

R

5

Junction to Package Top

Natural Convection

Ψ

2

6

JT

1

208 MAP BGA, Case Outline: 1159A-01

Comments:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board at the center lead. For fused lead packages, the adjacent lead is used.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC

JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

7

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

Table 11. Power Dissipation 1/8 Simulation Model Packaging Parameters

Component

Mold Compound

Leadframe (Copper)

Die Attach

Conductivity

0.9 W/m K

263 W/m K

1.7 W/m K

3.6 Power Supply

The MAC7100 Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports

and ATD. In the context of this section, V_DD5 is used for V_DDA, V_DDR or V_DDX; V_SS5 is used for V_SSA,

V_SSR or V_SSX unless otherwise noted. I_DD5 denotes the sum of the currents flowing into the V_DDA, V_DDX,

and V_DDR. V_DDis used for V_DD2.5, and V_DDPLL, V_SSis used for V_SS2.5 and V_SSPLL. I_DDis used for the

sum of the currents flowing into V_DD2.5 and V_DDPLL.

3.6.1 Current Injection

The power supply must maintain regulation within the V_DD5 or V_DD2.5 operating range during

instantaneous and operating maximum current conditions. If positive injection current (V > V_DD5) is

in

greater than I_DD5, the injection current may flow out of V_DD5 and could result in the external power supply

going out of regulation. It is important to ensure that the external V_DD5 load will shunt current greater than

the maximum injection current. The greatest risk will be when the MCU is consuming very little power (for

example, if no system clock is present, or if the clock rate is very low).

3.6.2 Power Supply Pins

The V_DDR – V_SSR pair supplies the internal voltage regulator. The V_DDA – V_SSA pair supplies the A/D

converter and the reference circuit of the internal voltage regulator. The V_DDX – V_SSX pair supplies the I/O

pins. V_DDPLL – V_SSPLL pair supplies the oscillator and PLL.

All V_DDX pins are internally connected by metal. All V_SSX pins are internally connected by metal. All

V_SS2.5 pins are internally connected by metal. V_DDA, V_DDX and V_DDR as well as V_SSA, V_SSX and V_SSR

are connected by anti-parallel diodes for ESD protection.

3.6.3 Supply Currents

All current measurements are without output loads. Unless otherwise noted the currents are measured in

single chip mode, internal voltage regulator enabled and at 40MHz bus frequency using a 4MHz oscillator

in low power mode. Production testing is performed using a square wave signal at the EXTAL input.

In expanded modes, the currents flowing in the system are highly dependent on the load at the address, data

and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be

given. A good estimate is to take the single chip currents and add the currents due to the external loads.

8

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ElectricalCharacteristics

Table 12. Supply Current Characteristics

Num

C

Rating

Symbol

I_DDR_core

Typ

Max

Unit

mA

1

D1a C Run Supply Current

–40° C ²

25° C ²

85° C ²

105° C ²

125° C ²

–40° C ²

25° C ²

—

1

Single Chip

—

1

—

1

—

1

—

1

D1b

D1c

C

I_DDR_reg

—

1

—

1

85° C ²

—

1

105° C ²

125° C ²

–40° C ²

25° C ²

85° C ²

105° C ²

125° C ²

—

1

—

1

I_DDR_pins

—

1

—

1

—

1

—

1

—

D2 C Doze Supply Current

Run ≥ Doze ≥ Pseudo Stop

1

D3a C Psuedo Stop Current

–40° C ²

25° C ²

85° C ²

105° C ²

125° C ²

–40° C ²

25° C ²

I_DDPS_core

—

µA

1

PLL on

—

1

—

1

—

1

—

1

D3b

D3c

C

I_DDPS_reg

I_DDPS_pins

I_DDS_core

I_DDS_reg

—

278 / 327 ³

—

1

85° C ²

—

1

105° C ²

125° C ²

–40° C ²

25° C ²

—

1

—

1

—

4 / 5 ³

—

1

85° C ²

—

1

105° C ²

125° C ²

–40° C ²

25° C ²

—

1

—

1

D4a C Stop Current

—

1

T_J= T_Aassumed

—

1

85° C ²

—

1

105° C ²

125° C ²

–40° C ²

25° C ²

—

1

—

1

D4b

D4c

C

—

1

68

—

1

85° C ²

—

1

105° C ²

125° C ²

–40° C ²

25° C ²

85° C ²

105° C ²

125° C ²

—

1

—

1

I_DDS_pins

—

1

4

—

1

—

1

—

1

—

1

2

3

At the time of publication, this value is yet to be determined, and will be supplied when device characterization is complete.

85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.

RTI disabled / enabled.

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

9

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.6.4 Voltage Regulator Characteristics

Table 13. VREG Operating Conditions

Num

C

Characteristic

Symbol

Min

Typical

Max

Unit

E1

E2

P Input Voltages

V_VDDRA

I_REG

2.97

—

5.5

V

P Regulator Current

Reduced Power Mode

Shutdown Mode

—

TBD

50

40

µA

E3

E4

P Output Voltage Core

V_DD

Full Performance Mode

Reduced Power Mode

Shutdown Mode

2.45

1.60

—

2.5

—

2.75

—

V

1

P Output Voltage PLL

V_DDPLL

Full Performance Mode

Reduced Power Mode ²

Reduced Power Mode ³

Shutdown Mode

2.35

2.00

1.60

—

2.5

2.75

—

V

1

—

E5

P Low Voltage Interrupt ⁴

Assert Level

V_LVIA

V_LVID

4.10

4.25

4.37

4.52

4.66

4.77

V

Deassert Level

E6

E7

P Low Voltage Reset ⁵

Assert Level

P Power On Reset ⁶

Assert Level

V_LVRA

2.25

2.35

—

V

V_PORA

V_PORD

0.97

—

2.05

V

Deassert Level

1

2

3

4

High Impedance Output.

Current I_DDPLL = 1mA (Low Power Oscillator).

Current I_DDPLL = 3mA (Standard Oscillator).

Monitors V A, active only in full performance mode. Indicated I/O and ATD performance degradation due to low supply

DD

voltage.

5

6

Monitors V_DD2.5, active only in full performance mode. Only POR is active in reduced performance mode.

Monitors V_DD2.5, active in all modes.

10

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ElectricalCharacteristics

3.6.5 Chip Power Up and Voltage Drops

The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)

handle chip power-up or drops of the supply voltage. Refer to Figure 2.

Voltage

V_DDA

V_LVID

V_LVIA

V_DD2.5

V_LVRD

V_LVRA

V_PORD

Time

LVI Disabled

due to LVR

LVI Enabled

LVI

POR

LVR

Note: Not to scale.

Figure 2. VREG Chip Power-up and Voltage Drops

3.6.6 Output Loads

The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC

load is allowed. Capacitive loads are specified in Table 14. Capacitors with X7R dielectricum are required.

Table 14. VREG Recommended Load Capacitances

Rating

Symbol

Min

Typ

Max

Unit

Load Capacitance on each V_DD2.5 pin

Load Capacitance on V_DDPLL pin

C_LVDD

200

90

440

220

12000

5000

nF

C_LVDDfcPLL

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

11

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.7 I/O Characteristics

This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All

parameters are not always applicable; for example, not all pins feature pull up/down resistances.

Table 15. 5 V I/O Characteristics

Conditions shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

F1a P Input High Voltage

V_IH

0.65 ×

—

V

V_DD5

F1b T Input High Voltage

F2a P Input Low Voltage

F2b T Input Low Voltage

F3 C Input Hysteresis

V_IH

V_IL

—

V_DD5 +

0.3

V

—

0.35 ×

V_DD

5

V_SS5 –

0.3

—

V_HYS

I_in

—

250

—

mV

1

F4

P

Input Leakage Current (pins in high impedance input mode)

V_in= V_DD5 or V_SS

TBD

µA

5

F5 P Output High Voltage (pins in output mode)

Partial Drive I = –2mA

V_OH

V_DD5 –

0.8

—

V

OH

= –10mA

Full Drive I

OH

F6 P Output Low Voltage (pins in output mode)

Partial Drive I = +2mA

V_OL

—

0.8

OL

= +10mA

Full Drive I

OL

F7 P Internal Pull Up Device Current,

tested at V_ILMax.

I_PUL

I_PUH

I_PDH

I_PDL

C_in

—

–10

—

–130

—

µA

F8 P Internal Pull Up Device Current,

tested at V_IHMin.

F9 P Internal Pull Down Device Current,

tested at V_IHMin.

130

—

F10 P Internal Pull Down Device Current,

tested at V_ILMax.

10

F11 D Input Capacitance

—

6

—

pF

F12 T Injection current ²

Single Pin limit

—

µA

I_ICS

I_ICP

–2.5

–25

2.5

25

Total Device Limit. Sum of all injected currents

F13 P Port Interrupt Input Pulse filtered ³

F14 P Port Interrupt Input Pulse passed ³

t_PULSE

—

3

µs

10

—

1

Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half

for each 8°C to 12°C in the temperature range from 50°C to 125°C.

Refer to Section 3.6.1, “Current Injection,” for more details

2

3

Parameter only applies in STOP or Pseudo STOP mode.

12

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table 16. 3.3 V I/O Characteristics

Conditions shown in Table 6, with V X = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.

DD

Num C

Rating

Symbol

Min

Typ

Max

Unit

G1a P Input High Voltage

V_IH

0.65 ×

—

V

V_DD5

G1b T Input High Voltage

G2a P Input Low Voltage

G2b T Input Low Voltage

G3 C Input Hysteresis

V_IH

V_IL

—

V_DD5 +

0.3

V

—

0.35 ×

V_DD

5

V_SS5 –

0.3

—

V_HYS

I_in

—

250

—

mV

1

G4

P

Input Leakage Current (pins in high impedance input mode)

V_in= V_DD5 or V_SS

TBD

µA

5

G5 P Output High Voltage (pins in output mode)

Partial Drive I = –0.75mA

V_OH

V_DD5 –

0.4

—

V

OH

= –4.5mA

Full Drive I

OH

G6 P Output Low Voltage (pins in output mode)

Partial Drive I = +0.9mA

V_OL

—

0.4

OL

= +5.5mA

Full Drive I

OL

G7 P Internal Pull Up Device Current,

tested at V_ILMax.

I_PUL

I_PUH

I_PDH

I_PDL

C_in

—

–6

—

6

—

–60

—

µA

G8 P Internal Pull Up Device Current,

tested at V_IHMin.

G9 P Internal Pull Down Device Current,

tested at V_IHMin.

60

—

G10 P Internal Pull Down Device Current,

tested at V_ILMax.

G11 D Input Capacitance

—

6

—

pF

G12 T Injection current ²

Single Pin limit

—

µA

I_ICS

I_ICP

–2.5

–25

2.5

25

Total Device Limit. Sum of all injected currents

G13 P Port Interrupt Input Pulse filtered ³

G14 P Port Interrupt Input Pulse passed ³

t_PULSE

—

3

µs

10

—

1

Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half

for each 8°C to 12°C in the temperature range from 50°C to 125°C.

Refer to Section 3.6.1, “Current Injection,” for more details

2

3

Parameter only applies in STOP or Pseudo STOP mode.

MOTOROLA

MAC7100 Microcontroller Family Hardware Specifications

13

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.8 Clock and Reset Generator Electrical

Characteristics

This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and

reset generator.

3.8.1 Oscillator Characteristics

The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce

oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce

oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET signal.

Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the

oscillation is checked for each start from either power on, STOP or oscillator fail. t

specifies the

CQOUT

maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is

not detected. The quality check also determines the minimum oscillator start-up time t . The device also

UPOSC

features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal

is below the Clock Monitor Assert Frequency f

.

CMFA

Table 17. Oscillator Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

H1a C Crystal oscillator range (loop controlled Pierce)

f_OSC

4.0

0.5

100

—

16

40

—

MHz

µA

ms

s

1, 2

H1b C Crystal oscillator range (full swing Pierce)

H2 P Startup Current

I_OSC

—

H3 C Oscillator start-up time (loop controlled Pierce)

H4 D Clock Quality check time-out

t_UPOSC

t_CQOUT

f_CMFA

f_EXT

TBD ³

—

50 ⁴

2.5

200

40

—

0.45

50

H5 P Clock Monitor Failure Assert Frequency

H6 P External square wave input frequency ²

H7 D External square wave pulse width low

H8 D External square wave pulse width high

H9 D External square wave rise time

H10 D External square wave fall time

100

—

KHz

MHz

ns

0.5

9.5

—

t_EXTL

t_EXTH

t_EXTR

t_EXTF

C_IN

—

ns

—

1

ns

—

1

ns

H11 D Input Capacitance (EXTAL, XTAL pins)

—

7

—

pF

H12 C EXTAL pin DC Operating Bias in loop controlled

mode

V_DCBIAS

—

TBD

—

V

1

2

3

4

Depending on the crystal; a damping series resistor might be necessary

XCLKS negated during reset

f_osc= 4 MHz, C = 22 pF.

Maximum value is for extreme cases using high Q, low frequency crystals

14

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.8.2 PLL Filter Characteristics

The oscillator provides the reference clock for the PLL. The voltage controlled oscillator (VCO) of the PLL

is also the system clock source in self clock mode. In order to operate reliably, care must be taken to select

proper values for external loop filter components.

V_DDPLL

C_S

C_P

Phase

Detector

VCO

K_V

R

f_REF

1

f_OSC

f_VCO

∆

K

φ

REFDV+1

f_CMP

Loop Divider

1

2

SYNR+1

Figure 3. Basic PLL Functional Diagram

The procedure described below can be used to calculate the resistance and capacitance values using typical

values for K₁, f₁and i_chfrom Table 18. First, the VCO Gain at the desired VCO output frequency is

approximated by:

(f₁– f_VCO

-------------------------

K₁⋅ 1V

)

K_V= K₁⋅ e

The phase detector relationship is given by:

K_Φ= – i_ch⋅ K_V

i_chis the current in tracking mode. The loop bandwidth f_Cshould be chosen to fulfill the Gardner’s stability

criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response.

2 ⋅ ζ ⋅ f_ref

π ⋅ (ζ + 1 + ζ²)

f_ref

→ f_C< ------------- ;(ζ = 0.9)

1

50









------

f_C< ----------------------------------------

4 ⋅ 50

And finally the frequency relationship is defined as

f_VCO

n = ----------- = 2 ⋅ (synr + 1)

f_ref

With the above inputs the resistance can be calculated as:

2 ⋅ π ⋅ n ⋅ f_C

R = ---------------------------

K_Φ

The capacitance C_Scan now be calculated as:

2 ⋅ ζ²

0.516

---------------------

C_S

=

≈ -------------;(ζ = 0.9)

π ⋅ f_C⋅ R

f_C⋅ R

The capacitance C_Pshould be chosen in the range of:

C_S÷ 20 ≤ C_P≤ C_S÷ 10

The stabilization delays shown in Table 18 are dependant on PLL operational settings and external

component selection (for example, crystal, XFC filter).

15

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.8.2.1 Jitter Information

The basic functionality of the PLL is shown in Figure 3. With each transition of the clock f , the deviation

cmp

from the reference clock f is measured and input voltage to the VCO is adjusted accordingly. The adjustment

ref

is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and

other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real

minimum and maximum clock periods as illustrated in Figure 4. It is important to note that the pre-scaler used

by timers and serial modules will eliminate the effect of PLL jitter to a large extent.

0

1

2

3

N–1

N

t_MIN1

t_NOM

t_MAX1

t_MIN(N)

t_MAX(N)

Figure 4. Jitter Definitions

The relative deviation of t_NOMis at its maximum for one clock period, and decreases towards zero for larger

number of clock periods (N). Thus, jitter is defined as:

t

_MAX(N)

t_MIN(N)







J(N) = max 1 – --------------------- , 1 – ---------------------



N ⋅ t_NOM

For N < 100, the following equation is a good fit for the maximum jitter:

j₁

J(N) = ------- + j₂

N

J(N)

0 1

5

10

15

20

N

Figure 5. Maximum Bus Clock Jitter Approximation

16

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.8.3 PLL Characteristics

Table 18. PLL Characteristics

Num C

Rating

Symbol

f_REF

Min

0.5

1

Typ

—

Max

16

Unit

MHz

J1

PLL reference frequency, crystal oscillator range ¹

J2 P Self Clock Mode frequency

J3 D VCO locking range

f_SCM

—

5.5

40

f_VCO

8

—

2

J4

D

Lock Detector transition from Acquisition to Tracking mode

|∆_trk

|∆_Lock

|∆_unl

|

3

—

4

%

2

J5 D Lock Detection

|

0

—

1.5

2.5

8

%

2

J6 D Un-Lock Detection

|

0.5

6

—

%

2

J7

D

Lock Detector transition from Tracking to Acquisition mode |∆_unt

|

—

%

J8 C PLLON Total Stabilization delay (Auto Mode) ³

J9 D PLLON Acquisition mode stabilization delay ³

J10 D PLLON Tracking mode stabilization delay ³

J11 D Charge pump current acquisition mode

J12 D Charge pump current tracking mode

J13 D Jitter fit VCO loop gain parameter

J14 D Jitter fit VCO loop frequency parameter

J15 C Jitter fit parameter 1

t_stab

t_acq

t_al

—

0.5 ⁴

0.3 ⁵

0.2 ⁵

38.5

3.5

–100

60

3 ⁵

1 ⁴

2 ⁴

—

ms

| i_ch

K₁

f₁

|

µA

—

µA

—

MHz/V

MHz

—

4

j₁

—

TBD

%

4

J16 C Jitter fit parameter 2

j₂

—

%

1

2

3

V_DDPLL at 2.5 V.

Percentage deviation from target frequency

PLL stabilization delay is highly dependent on operational requirement and external component values (for

example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical

configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.

f_REF= 4 MHz, f_SYS= 25 MHz (REFDV = 0x03, SYNR = 0x01), C_S= 4.7 nF, C_P= 470 pF, R_S= 10 KΩ.

f_REF= 4 MHz, f_SYS= 8 MHz (REFDV = 0x00, SYNR = 0x01), C_S= 33 nF, C_P= 3.3 nF, R_S= 2.7 KΩ.

4

5

3.8.4 Crystal Monitor Time-out

The time-out Table 19 shows the delay for the crystal monitor to trigger when the clock stops, either at the high

or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.

Table 19. Crystal Monitor Time-Outs

Min

Typ

Max

Unit

6

10

18.5

µs

3.8.5 Clock Quality Checker

The timing for the clock quality check is derived from the oscillator and the VCO frequency range in

Table 18. These numbers define the upper time limit for the individual check windows to complete.

Table 20. CRG Maximum Clock Quality Check Timings

Clock Check Windows

Value

Unit

Check Window

9.1 to 20.0

0.46 to 1.0

ms

s

Timeout Window

17

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.8.6 Startup

Table 21 summarizes several startup characteristics explained in this section. Refer to the MAC7100

Microcontroller Family Reference Manual (MAC7100RM/D) for a detailed description of the startup

behavior.

Table 21. CRG Startup Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

K1 T POR release level

K2 T POR assert level

V_PORR

V_PORA

PW_RSTL

n_RST

—

0.97

2

—

2.07

—

V

K3 D Reset input pulse width, minimum input time

K4 D Startup from Reset

—

t_osc

n_osc

ns

192

20

196

—

K5 D Interrupt pulse width, IRQ edge-sensitive mode

K6 D Wait recovery startup time

PW_IRQ

t_WRS

—

14

t_cyc

3.8.6.1 Power On and Low Voltage Reset (POR and LVR)

The release level V_PORRand the assert level V_PORAare derived from the V_DD2.5 supply. The assert level

V_LVRAis derived from the V_DD2.5 supply. They are also valid if the device is powered externally. After

releasing the POR or LVR reset, the oscillator and the clock quality check are started. If after a time t_CQOUT

no valid oscillation is detected, the MCU will start using the internal self-generated clock. The fastest startup

time possible is given by t_uposc(refer to Table 17).

3.8.6.2 SRAM Data Retention

The SRAM contents integrity is guaranteed if the PORF bit in the CRGFLG register is not set following a

reset operation.

3.8.6.3 External Reset

When external reset is asserted for a time greater than PW_RSTL, the CRG module generates an internal reset

and the CPU starts fetching the reset vector without doing a clock quality check, if there was stable

oscillation before reset.

3.8.6.4 Stop Recovery

The MCU can be returned to run mode from the stop mode by an external interrupt. A clock quality check

is performed in the same manner as for POR before releasing the clocks to the system.

3.8.6.5 Pseudo Stop and Doze Recovery

Recovery from pseudo stop and doze modes are essentially the same, since the oscillator is not stopped in

either mode. The controller is returned to run mode by internal or external interrupts or other wakeup events

in the system. After t_wrs, the CPU fetches an interrupt vector if the wakeup event was an interrupt, or

continues to execute code if the wakeup event was not an interrupt.

18

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.9 External Bus Timing Specifications

Table 22 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and

output delay with respect to the rising edge of a reference clock. The

reference clock is the CLKOUT output.

All other timing relationships can be derived from these values.

Table 22. External Bus Input Timing Specifications

Num

C

Rating ¹

Symbol Min Max Unit

L1

CLKOUT

t_CYC

23

—

ns

Control Inputs

L2a

L3a

Control input valid to CLKOUT high ²

CLKOUT high to control inputs invalid ²

t_CVCH

t_CHCII

13

0

—

ns

Data Inputs

L4

L5

Data input (DATA[15:0]) valid to CLKOUT high

CLKOUT high to data input (DATA[15:0]) invalid

t_DIVCH

t_CHDII

9

0

—

ns

1

2

Timing specifications have been indicated taking into account the full drive strength for the pads.

TA pins are being referred to as control inputs.

CLKOUT(45MHz)

Input Setup & Hold

Input Rise Time

Input Fall Time

CLKOUT

1.5 V

t_SETUP

Invalid

t_HOLD

1.5 V Valid 1.5 V

Invalid

t_RISE= 1.5 ns

V_H= V_IH

V_L= V_IL

t_FALL= 1.5 ns

V_H= V_IH

V_L= V_IL

L4

L5

Inputs

Figure 6. General Input Timing Requirements

19

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.9.1 Read and Write Bus Cycles

Table 23 lists processor bus output timings. Read/write bus timings listed in Table 23 are shown in Figure 7

and Figure 8.

Table 23. External Bus Output Timing Specifications

Num

C

Rating

Symbol

Min

Max

Unit

Control Outputs

1

L6a

L6b

CLKOUT high to chip selects valid

t_CHCV

t_CHBV

—

0.5t_CYC+ 10

ns

CLKOUT high to byte select (BS[1:0]) valid ²

L6c

CLKOUT high to output select (OE) valid ³

t_CHOV

—

0.5t_CYC+ 10

ns

L7a

L7b

CLKOUT high to control output (BS[1:0], OE) invalid

CLKOUT high to chip selects invalid

t_CHCOI0.5t_CYC+ 2

—

ns

t_CHCI

0.5t_CYC+ 2

Address and Attribute Outputs

L8

L9

CLKOUT high to address (ADDR[21:0]) and control

(R/W) valid

t_CHAV

—

2

10

—

ns

CLKOUT high to address (ADDR[21:0]) and control

(R/W) invalid

t_CHAI

Data Outputs

CLKOUT high to data output (DATA[15:0]) valid

CLKOUT high to data output (DATA[15:0]) invalid

L10

L11

L12

t_CHDOV

t_CHDOI

—

2

13

—

9

ns

CLKOUT high to data output (DATA[15:0]) high impedance t_CHDOZ

—

1

2

3

CSn transitions after the falling edge of CLKOUT.

BSn transitions after the falling edge of CLKOUT.

OE transitions after the falling edge of CLKOUT.

20

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

S0

S1

S2

S3

S4

S5

S0

S1

S2

S3

S4

S5

CLKOUT

CSn

L6a

L8

L6a

L7b

L8

L9

ADDR[21:0]

OE

L1

L6c

L7a

L8

L9

R/W

L6b

L7a

BS[1:0]

DATA[15:0]

TA (H)

L10

L4

L11

L12

L5

Figure 7. Read/Write (Internally Terminated) Bus Timing

21

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

S0

S1

S2

S3

S4

S5

S0

S1

CLKOUT

CSn

L6a

L8

L7b

L7a

L9

ADDR[21:0]

OE

L6c

R/W

L6b

BS[1:0]

DATA[15:0]

TA

L4

L5

L2a

L3a

Figure 8. Read Bus Cycle Terminated by TA

22

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.10 Analog-to-Digital Converter Characteristics

Table 24 and Table 25 show conditions under which the ATD operates. The following constraints exist to

obtain full-scale, full range results: V_SSA ≤ V_RL≤ V_IN≤ V_RH≤ V_DDA. This constraint exists because the

sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside

of this range it will effectively be clipped.

Table 24. ATD Operating Characteristics in 5 V Range

Conditions shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

M1 D Reference Potential

Low

High

V_RL

V_RH

V_SS

V_DDA ÷ 2

A

—

V

_DDA ÷ 2

V_DDA

V

M2 C Differential Reference Voltage ¹

M3 D ATD Clock Frequency

V_RH– V_RL

f_ATDCLK

4.50

0.5

5.00

—

5.25

2.0

V

MHz

M4 D ATD 10-bit Conversion PeriodClock Cycles ²

N_CONV10

14

7

—

28

14

Cycles

µs

@ 2.0MHz f_ATDCLKT_CONV10

M5 D ATD 8-bit Conversion PeriodClock Cycles ²

N_CONV8

12

6

—

26

13

Cycles

µs

@ 2.0MHz f_ATDCLKT_CONV8

M6 D Recovery Time (V_DDA = 5.0 V)

t_REC

—

20

µs

M7

M8

P

Reference Supply current 1 ATD module enabled

Reference Supply current 2 ATD modules enabled

I_REF

0.375

0.750

mA

1

2

Full accuracy is not guaranteed when differential voltage is less than 4.50 V

Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

Table 25. ATD Operating Characteristics in 3.3 V Range

Conditions shown in Table 6, with V_DDX = 3.3 V ±10% and a temperature maximum of +140°C unless otherwise noted.

Num C

Rating

Symbol

Min

Typ

Max

Unit

N1 D Reference Potential

Low

High

V_RL

V_RH

V_SS

V_DDA ÷ 2

A

—

V

_DDA ÷ 2

V_DDA

V

N2 C Differential Reference Voltage ¹

N3 D ATD Clock Frequency

V

_RH–V_RL

3.0

0.5

3.3

—

3.6

2.0

V

f_ATDCLK

MHz

N4 D ATD 10-bit Conversion PeriodClock Cycles ²

N_CONV10

14

7

—

28

14

Cycles

µs

Conv, Time at 2.0MHz ATD Clock f_ATDCLKT_CONV10

N5 D ATD 8-bit Conversion PeriodClock Cycles ²

N_CONV8

12

6

—

26

13

Cycles

µs

Conv, Time at 2.0MHz ATD Clock f_ATDCLKT_CONV8

N6 D Recovery Time (V_DDA=5.0 V)

t_REC

I_REF

—

20

µs

N7

N8

P

Reference Supply current 1 ATD module enabled

Reference Supply current 2 ATD modules enabled

0.375

0.250

mA

1

2

Full accuracy is not guaranteed when differential voltage is less than 3.0 V

Minimum time assumes final sample period of 2 ATD clocks; maximum time assumes final sample period of 16 ATD clocks.

3.10.1 Factors Influencing Accuracy

Three factors — source resistance, source capacitance and current injection — have an influence on the

accuracy of the ATD.

23

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.10.1.1 Source Resistance

Due to the input pin leakage current as specified in Table 15 in conjunction with the source resistance there

will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance R ,

S

results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or operating

conditions are less than the worst case, or leakage-induced errors are acceptable, larger values of source

resistance are allowed.

3.10.1.2 Source Capacitance

When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due

to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of

the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as,

C

≥

1024

×

(C

–

C

).

f

INS

INN

3.10.1.3 Current Injection

There are two cases to consider:

1. A current is injected into the channel being converted. The channel being stressed has conversion

values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than V_RHand 0x000 for values less

than V_RLunless the current is higher than specified as disruptive condition.

2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this

current is picked up by the channel (coupling ratio K), This additional current impacts the

accuracy of the conversion depending on the source resistance. The additional input voltage error

on the converted channel can be calculated as V_ERR= K × R_S× I_INJ, with I_INJbeing the sum of the

currents injected into the two pins adjacent to the converted channel.

Table 26. ATD Electrical Characteristics

Conditions are shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

P1 C Max input Source Resistance

R_S

—

1

KΩ

P2 T Total Input Capacitance

Non Sampling

C_INN

C_INS

—

10

22

pF

Sampling

P3 C Disruptive Analog Input Current

I_NA

K_p

K_n

–2.5

—

2.5

mA

A/A

P4 C Coupling Ratio positive current injection

P5 C Coupling Ratio negative current injection

TBD

—

24

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.10.2 ATD Accuracy

Table 27 and Table 28 specify the ATD conversion performance excluding any errors due to current

injection, input capacitance and source resistance.

Table 27. ATD Conversion Performance in 5 V Range

Conditions shown in Table 6 unless otherwise noted.

V_REF= V_RH– V_RL= 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV

f_ATDCLK= 2.0 MHz, 4.5 V ≤ V_DDA ≤ 5.5 V

Num C

Rating

Symbol

Min

Typ

Max

Unit

Q1 P 10-bit Resolution

LSB

DNL

INL

AE

—

–1

5

—

1

mV

Q2 P 10-bit Differential Nonlinearity

Q3 P 10-bit Integral Nonlinearity

Q4 P 10-bit Absolute Error ¹

Q5 P 8-bit Resolution

—

Counts

mV

–2.5

–3

±1.5

±2.0

20

2.5

3

LSB

DNL

INL

AE

—

Q6 P 8-bit Differential Nonlinearity

Q7 P 8-bit Integral Nonlinearity

Q8 P 8-bit Absolute Error ¹

–0.5

–1.0

–1.5

—

0.5

1.0

1.5

Counts

±0.5

±1.0

1

These values include the quantization error which is inherently 1/2 count for any A/D converter.

Table 28. ATD Conversion Performance in 3.3 V Range

Conditions shown in Table 6 unless otherwise noted.

V_REF= V_RH– V_RL= 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV

f_ATDCLK= 2.0 MHz, 4.5 V ≤ V_DDA ≤ 5.5 V

Num C

Rating

Symbol

Min

Typ

Max

Unit

R1 P 10-bit Resolution

LSB

DNL

INL

AE

—

3.25

—

1.5

3.5

5

mV

R2 P 10-bit Differential Nonlinearity

R3 P 10-bit Integral Nonlinearity

R4 P 10-bit Absolute Error ¹

R5 P 8-bit Resolution

–1.5

–3.5

–5

Counts

mV

±1.5

±2.0

13

LSB

DNL

INL

AE

—

R6 P 8-bit Differential Nonlinearity

R7 P 8-bit Integral Nonlinearity

R8 P 8-bit Absolute Error ¹

–0.5

–1.5

—

0.5

1.5

Counts

±1.0

1

These values include the quantization error which is inherently 1/2 count for any A/D converter.

For the following definitions see also Figure 8.

Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.

V_i– V_{i – 1}

DNL(i) = ----------------------- – 1

1 LSB

The Integral Non-Linearity (INL) is defined as the sum of all DNLs:

n

V_n– V₀

INL(n) =

DNL(i) = ------------------- – n

1 LSB

∑

i = 1

25

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

10-bit Absolute Error Boundary

0x3FF

8-bit Absolute Error Boundary

0x3FE

0x3FD

0x3FC

0x3FB

0x3FA

0x3F9

0x3F8

0x3F7

0x3F6

0x3F5

0x3F4

0x3F3

DNL

V_I–1

0xFF

0xFE

0xFD

2

LSB

V_I

9

8

7

6

5

4

3

2

1

0

Ideal Transfer Curve

10-bit Transfer Curve

1

8-bit Transfer Curve

V_IN

mV

0

10

20

30

40 50

5055 5065 5075 5085 5095 5105 5115

5060 5070 5080 5090 5100 5110 5120

5

15

25

35

Figure 9. ATD Accuracy Definitions

NOTE

Figure 8 shows only definitions, for specification values refer to Table 27.

26

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.10.3 ATD Electrical Specifications

Table 29 lists the DC electrical characteristics for the ATD module. Table 27 lists the analog-to-digital

conversion performance specifications.

1

Table 29. ATD Electrical Characteristics (Operating)

Num C

Rating

Reference Potential ²Low

Symbol

Min

Typ

Max

Unit

S1

S2

V_RL

V_RH

V_SSA

—

V_DDA ÷ 2

V_DDA

V

High

V_DDA ÷ 2

3

S3

S4

Voltage Difference V_RH– V_RL

Analog Input Voltage

V

_RH– V_RL

4.5

—

5.5

V

V_INDC

–0.3

V_DDA + 0.3

S5

S6

Digital Input

Voltage

High

Low

V_IH

V_IL

0.7 × V_DD

V_SSA – 0.3

A

—

V

_DDA + 0.3

V

0.2 × V_DDA

S7

S8

S9

Analog Supply

Current

Run

–40°C ⁴

25°C ⁴

85°C ⁴

105°C ⁴

125°C ⁴

–40°C ⁴

25°C ⁴

85°C ⁴

105°C ⁴

125°C ⁴

–40°C ⁴

I_DDA_run

—

TBD

17

TBD

250

mA

µA

mA

nA

—

Pseudo

Stop

I

A

—

DD pseudo_stop

—

TBD

17

—

Stop

I_DDA_stop

—

(low power) 25°C ⁴

85°C ⁴

—

TBD

200

—

105°C ⁴

125°C ⁴

—

S10

S11

S12

Reference Supply Current

Input Injection Current ⁵

Input Current, Off Channel ⁶

I_REF

I_INJ

—

2

I_OFF

–200

—

200

S13

S14

Total Input

Capacitance

Not Sampling

Sampling

C_INN

C_INS

—

10

15

pF

S15

S16

S17

Disruptive Analog Input Current ⁷

Coupling Ratio ⁸

I_NA

K

–3

—

3

10^–4

mA

A/A

Incremental Error due to injection current

±1

Counts

(All channels with 10k < Rs < 100k)⁹

S18

S19

Incremental Error due to injection current

—

±1

Counts

pF

9

(

Channel under test Rs=10k, I

=±3mA)

INJ

Incremental Capacitance during

Sampling ¹⁰

C_SAMP

5

1

2

All voltages referred to V_SSA, –40 to 125^oC, V_DDA = 5.0 V ±10% and 2.0 MHz conversion rate unless otherwise

noted. Refer to Table 6 for additional operating conditions.

To obtain full-scale, full-range results, V_SSA < V_RL< V_INDC< V_RH< V_DDA. Sample buffer amp cannot drive beyond

the power supply levels. If the input level goes outside of this range, it will effectively be clipped.

Full accuracy is not guaranteed when the differential reference voltage is less than 4.5 V.

85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.

The input injection current is specified to 1 count of error.

3

4

5

27

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

6

Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for

each 8 to 12 °C, in the ambient temperature range of 50 to 125 °C.

7

Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs

greater than V_RHand 0x000 for values less than V_RL. This assumes that V_DDA ≥ AV_RHand V_RL≥ V_SSA due to the

presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.

8

Coupling Ratio, K, is defined as the ratio of the output current, I_OUT, measured on the pin under test to the injection

current, I_INJ, when both adjacent pins are overstressed with the specified injection current. K = I_OUT÷ I_INJ. The input

voltage error on the channel under test is calculated as Verr = I_INJx K x R_S.

9

Total injection current is determined by the number of channels injecting (for example, 15), external injection voltage

(V_INJ– V_POSCLAMP, or V_INJ– V_NEGCLAMP), and the external source impedance, Rs, wherein all input channels have

the same values. To determine the error voltage on the converted channel, only the two adjacent channels are

expected to contribute to the error voltage: V_errj= (V_INJ– V_CLAMP) × K × 2.

10

For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, C_f≥ 1024 × C_SAMP. The

value of C_SAMPin the new design may be reduced, or increased slightly.

1

Table 30. ATD Performance Specifications

Num C

T1 D 10-bit Resolution

T2 D 10-bit Differential Nonlinearity ²

T3 D 10-bit Integral Nonlinearity ²

T4 D 10-bit Absolute Error ^{2, 3}

Rating

Symbol

LSB

DNL

INL

Min

—

Typ

5

Max

—

Unit

mV

–1

—

1

Counts

kΩ

–2

2

AE

–2.5

—

2.5

100

T5 D Max input Source Impedance ⁴

R_S

1

2

3

4

All voltages referred to V_SSA, V_DDA = 5.0 V±10%, ATD clock = 2.1 Mhz., –40 to 125 °C.

Note: 1 LSB = 1 Count (At V_REF= 5.12 V, one 8 bit count = 20 mV, one 10-bit count = 5 mV)

These values include quantization error which is inherently 1/2 count for any A/D converter.

This value is based on error attributed to the specified leakage value of TBD nA resulting in an error of less than 1/2

LSB (2.5 mV). If operating conditions are less than worst case or leakage-induced error is acceptable, larger values

of source resistance is allowable.

3.10.4 ATD Timing Specifications

Table 31. ATD Timing Specifications

Num C

Rating

Symbol

F_clk

Min

—

Typ

—

Max

25.0

2.0

28^*

14

Unit

MHz

Cycles^*

µsec

U1 D ATD Module Clock Frequency

U2 D ATD Conversion Clock Frequency

U3 D ATD 10-bit Conversion Period^*

F_atdclk

0.5

14^*

7

—

*

Clock Cycles N_CONV10

—

T_CONV10

Conv. Time

U4 D Stop Recovery Time (V_DDA = 5.0 V)

T_SR

—

100

µsec

Table 32. ATD External Trigger Timing Specifications

Num

C

Parameter

Symbol

Min

Max

Unit

V1

D ETRIG Minimum Period

T_PERIOD

—

1 sample +

1 conv. +

CYCLE

1 ATD clock

V2

V3

V4

D ETRIG Minimum Pulse Width

D ETRIG Level Recovery ¹

D Conversion Start Delay

t_PW

t_LR

2

1

—

2

SYS CLK

t_DLY

—

1

Time prior to end of conversion that the ETRIG pin must be deactivated so that another conversion sequence does

not start.

28

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

t_PW

t_PERIOD

Edge Sensitive

Falling Edge Active ETRIG

t_DLY

Coversion Activity

ADx

Max Frequency

t_PW

Level Sensitive

Low Active ETRIG

Sequence

ASCIF

Complete Flag

t_DLY

Coversion Activity

ADx

Max Frequency

Level Sensitive

Low Active ETRIG

t_LR

Sequence

ASCIF

Complete Flag

t_DLY

Coversion Activity

ADx

Figure 10. ATD External Trigger Timing Diagram

29

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.11 Serial Peripheral Interface Electrical

Specifications

3.11.1 Master Mode

Figure 11 and Figure 12 illustrate master mode timing. Timing values are shown in Table 33.

1

Table 33. SPI Master Mode Timing Characteristics

Conditions are shown in Table 6 unless otherwise noted, C_LOAD= 200pF on all outputs

Num C

W1a P Operating Frequency

Rating

Symbol

f_op

Min

DC

Typ

—

Max

1/4

Unit

f_bus

t_bus

t_sck

ns

W1b P SCK Period t_sck= 1/f_op

W2 D Enable Lead Time

t_sck

t_lead

t_lag

t_wsck

t_su

4

2048

—

1/2

W3 D Enable Lag Time

1/2

—

W4 D Clock (SCK) High or Low Time

W5 D Data Setup Time (Inputs)

W6 D Data Hold Time (Inputs)

W9 D Data Valid (after Enable Edge)

W10 D Data Hold Time (Outputs)

W11 D Rise Time Inputs and Outputs

W12 D Fall Time Inputs and Outputs

t_bus− 30

1024 t_bus

—

25

0

ns

t_hi

—

ns

t_v

—

0

25

ns

t_ho

—

ns

t_r

—

25

ns

t_f

25

ns

1

The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent

between the Master and the Slave timing shown in Table 34.

3.11.2 Slave Mode

Figure 13 and Figure 14 illustrate the slave mode timing. Timing values are shown in Table 34.

Table 34. SPI Slave Mode Timing Characteristics

Conditions are shown in Table 6 unless otherwise noted, CLOAD = 200pF on all outputs

Num C

Rating

Symbol

Min

Typ

Max

Unit

X1a P Operating Frequency

f_op

t_sck

t_lead

t_lag

t_wsck

t_su

t_hi

DC

—

1/4

2048

—

f_bus

t_bus

t_cyc

ns

X1b P SCK Period t_sck= 1/f_op

X2 D Enable Lead Time

4

1

X3 D Enable Lag Time

1

t_cyc− 30

25

—

X4 D Clock (SCK) High or Low Time

X5 D Data Setup Time (Inputs)

X6 D Data Hold Time (Inputs)

X7 D Slave Access Time

—

ns

25

—

ns

t_a

—

1

t_cyc

ns

X8 D Slave SIN Disable Time

X9 D Data Valid (after SCK Edge)

X10 D Data Hold Time (Outputs)

X11 D Rise Time Inputs and Outputs

X12 D Fall Time Inputs and Outputs

t_dis

t_v

t_ho

t_r

—

1

—

25

—

0

ns

—

25

ns

t_f

—

ns

30

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

PCSx

(OUTPUT)

W2

W11

W12

W1b

W3

SCK

(CPOL = 0)

(OUTPUT)

W4

SCK

(CPOL = 1)

(OUTPUT)

W5

W6

SIN

(INPUT)

MSB In ²

Bit 6 ... 1

LSB In

W9

W10

SOUT

(OUTPUT)

MSB Out ²

Bit 6 ... 1

LSB Out

¹If configured as output.

²LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 11. SPI Master Timing (CPHA = 0)

PCSx

(OUTPUT)

W2

W11

W12

W1b

W12

W11

W3

SCK

(CPOL = 0)

(OUTPUT)

W4

W5

W4

W6

SCK

(CPOL = 1)

(OUTPUT)

SIN

(INPUT)

MSB In ²

Bit 6 ... 1

LSB In

W9

W10

SOUT

(OUTPUT)

Port Data

Master MSB Out ²

Bit 6 ... 1

Master LSB Out

Port Data

¹If configured as output.

²LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 12. SPI Master Timing (CPHA =1)

31

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

SS

(INPUT)

X2

X11

X12

X1b

X12

X11

X3

SCK

(CPOL = 0)

(INPUT)

X4

SCK

(CPOL = 1)

(INPUT)

X7

X10

X8

X9

X10

SOUT

(OUTPUT)

Slave MSB Out

Bit 6 ... 1

Slave LSB Out

X5

X6

SIN

(INPUT)

MSB In

Bit 6 ... 1

LSB In

Figure 13. SPI Slave Timing (CPHA = 0)

SS

(INPUT)

X2

X11

X12

X1b

X12

X11

X3

SCK

(CPOL = 0)

(INPUT)

X4

SCK

(CPOL = 1)

(INPUT)

X9

X8

X7

X10

SOUT

(OUTPUT)

Slave MSB Out

Bit 6 ... 1

Slave LSB Out

LSB In

X5

X6

SIN

(INPUT)

MSB In

Bit 6 ... 1

Figure 14. SPI Slave Timing (CPHA =1)

32

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.12 FlexCAN Electrical Specifications

Table 35. FlexCAN Wake-up Pulse Characteristics

Conditions are shown in Table 6 unless otherwise noted

Num C

Rating

Symbol

Min

Typ

Max

Unit

Y1 P FlexCAN Wake-up dominant pulse filtered

Y2 P FlexCAN Wake-up dominant pulse passed

t_WUP

—

5

—

2

µs

—

3.13 Program Flash and Data Flash Timing

Characteristics

NOTE

Unless otherwise noted the abbreviation NVM (Non-Volatile Memory) is

used for both program Flash and data Flash.

3.13.1 NVM timing

The time base for all NVM program or erase operations is derived from the system clock divided by two

(Fsys/2). A minimum system frequency f_NVMfsysis required for performing program or erase operations.

The NVM modules do not have any means to monitor the frequency and will not prevent program or erase

operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM

modules at a lower frequency a full program or erase transition is not assured.

The Flash and Data Flash program and erase operations are timed using a clock derived from the system

frequency using the CFMCLKD register. The frequency of this clock must be set within the limits specified

as f_NVMOP. The minimum program and erase times shown in Table 36 are calculated for maximum f_NVMOP

and maximum f_bus. The maximum times are calculated for minimum f_NVMOPand a f_busof 2 MHz.

3.13.1.1 Single Word Programming

The programming time for single word programming is dependant on the bus frequency as a well as on the

frequency f_NVMOPand can be calculated according to the following formula.

1

f_bus

-----------------

--------

t_swpgm= 9 ⋅

+ 25 ⋅

f_NVMOP

3.13.1.2 Burst Programming

This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst

programming by keeping the command pipeline filled. The time to program a consecutive word can be

calculated as:

1

f_bus

-----------------

--------

t_bwpgm= 4 ⋅

+ 9 ⋅

f_NVMOP

The time to program a whole row is:

t_brpgm= t_swpgm+ 31 ⋅ t_bwpgm

Burst programming is more than 2 times faster than single word programming.

33

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.13.1.3 Sector Erase

Erasing a 4k byte Flash sector takes:

1

-----------------

t_era≈ 4000 ⋅

f_NVMOP

The setup time can be ignored for this operation.

3.13.1.4 Mass Erase

Erasing a NVM block takes:

1

-----------------

t_mass≈ 20000 ⋅

f_NVMOP

The setup time can be ignored for this operation.

3.13.1.5 Blank Check

The time it takes to perform a blank check on the Flash or Data Flash is dependant on the location of the

first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup

of the command.

t_check≈ location ⋅ t_cyc+ 10 ⋅ t_cyc

1

Table 36. NVM Timing Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

Z1 D System Clock/2

f_NVMfsys

0.5

1

—

50 ²

MHz

kHz

µs

Z2

D Bus frequency for Programming or Erase Operations f_NVMBUS

—

Z3 D Operating Frequency

f_NVMOP

t_swpgm

t_bwpgm

t_brpgm

t_era

150

200

Z4 P Single Word Programming Time

Z5 D Flash Burst Programming consecutive word

Z6 D Flash Burst Programming Time for 32 Words

Z7 P Sector Erase Time

46 ³

74.5 ⁴

31 ⁴

20.4 ³

678.4 ³

20 ⁵

µs

1035.5 ⁴

26.7 ⁴

133 ⁴

32778 ⁷

2058 ⁷

µs

ms

Z8 P Mass Erase Time

t_mass

100 ⁵

ms

6

Z9 D Blank Check Time Flash per block

Z10 D Blank Check Time Data Flash per block

t_check

11

t_cyc

11 ⁶

1

2

3

4

Conditions are shown in Table 6 unless otherwise noted

Restrictions for oscillator in crystal mode apply!

Minimum programming times are achieved under maximum NVM operating frequency f

and maximum bus frequency f

.

NVMOP

bus

Maximum erase and programming times are achieved under particular combinations of f_NVMOPand bus frequency

f_bus. Refer to formulae in Section 3.13.1.1, “Single Word Programming,” through Section 3.13.1.4, “Mass Erase,” for

more information.

5

6

7

Minimum erase times are achieved under maximum NVM operating frequency f_NVMOP

Minimum time, if first word in the array is not blank

Maximum time to complete check on an erased block

.

34

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

_{Electrical Characteristics}Freescale Semiconductor, Inc.

3.13.2 NVM Reliability

The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process

monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase

cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is

incremented every time a sector or mass erase event is executed.

Table 37. NVM Reliability Characteristics

Conditions shown in Table 6 unless otherwise noted.

Num

C

Rating

Min

Unit

Z10

Z11

C Program/Data Flash Program/Erase endurance (–40C to +125C)

C Program/Data Flash Data Retention Lifetime

10,000

15

Cycles

Years

NOTE

All values shown in Table 37 are target values and subject to

characterization.

For Flash cycling performance, each Program operation must be preceded

by an erase.

35

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Device Pin Assignments

4 Device Pin Assignments

The MAC7100 Family is available in 208-pin ball grid array (MAP BGA), 144-pin low profile quad flat

(LQFP), 112-pin LQFP, and 100-pin LQFP package options. The family of devices offer pin-compatible

packaged devices to assist with system development and accommodate a direct application enhancement

path. Refer to Table 1 for a comparison of the peripheral sets and package options for each device.

Most pins perform two or more functions, which is described in more detail in the MAC7100

Microcontroller Family Reference Manual (MAC7100RM/D). Figure 15, Figure 16, Figure 17, Figure 18,

and Figure 19 show the pin assignments for the various packages.

4.1 MAC7141PV Pin Assignments

CNTX_A / PG4

CNRX_A / PG5

CNTX_B / PG6

CNRX_B / PG7

PE9 / AN9_A

PE8 / AN8_A

PE7 / AN7_A

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PE6 / AN6_A / RDY'

PE5 / AN5_A / MSEO'

PE4 / AN4_A / MDO1'

PE3 / AN3_A / MDO0'

PE2 / AN2_A / EVTI'

PE1 / AN1_A / EVTO'

PE0 / AN0_A / MCKO'

PA7

V

X

SS

DD

N/C

/ PB0

SDA

SCL

SIN_A

/ PB1

/ PB2

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SOUT_A / PB3

SCK_A / PB4

/ PCS0_A / PB5

PCS1_A / PB6

PCS2_A / PB7

PA8

PA9

MAC7141

100 LQFP

SS_A

V

X

DD

SS

PCSS_A / PCS5_A / PB8

eMIOS15 / PF15

eMIOS14 / PF14

eMIOS13 / PF13

eMIOS12 / PF12

eMIOS11 / PF11

eMIOS10 / PF10

eMIOS9 / PF9

PD4 / IRQ

PD3 / XIRQ

CLKOUT

PB15 / SIN_B

PB14 / SOUT_B

PB13 / SCK_B

PB12 / PCS1_B

PB11 / PCS2_B

/ XCLKS

eMIOS8 / PF8

eMIOS7 / PF7

PB10 / PCS5_B / PCSS_B

PB9 / PCS0_B / SS_B

Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP

MAC7100 Microcontroller Family Hardware Specifications

36

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Device Pin Assignments

4.2 MAC7121PV Pin Assignments

CNTX_A / PG4

CNRX_A / PG5

CNTX_C / PG8

CNRX_C / PG9

CNTX_D / PG10

CNRX_D / PG11

CNTX_B / PG6

CNRX_B / PG7

PE9 / AN9_A

PE8 / AN8_A

PE7 / AN7_A

PE6 / AN6_A / RDY'

PE5 / AN5_A / MSEO'

PE4 / AN4_A / MDO1'

PE3 / AN3_A / MDO0'

PE2 / AN2_A / EVTI'

PE1 / AN1_A / EVTO'

PE0 / AN0_A / MCKO'

PA7

PA8

PA9

PA10

PA11

PA12

PD5

PC15

1

2

3

4

5

6

7

8

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

V

X

9

SS

V

X

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DD

SDA

/ PB0

SCL

SIN_A

/ PB1

/ PB2

SOUT_A / PB3

SCK_A / PB4

MAC7121

112 LQFP

SS_A

/ PCS0

/ PB5

PCS1_A / PB6

PCS2_A / PB7

PCSS_A / PCS5_A / PB8

V

X

DD

eMIOS15 / PF15

eMIOS14 / PF14

eMIOS13 / PF13

eMIOS12 / PF12

eMIOS11 / PF11

eMIOS10 / PF10

eMIOS9 / PF9

eMIOS8 / PF8

eMIOS7 / PF7

V

X

SS

PD4 / IRQ

PD3 / XIRQ

CLKOUT

/ XCLKS

PB15 / SIN_B

PB14 / SOUT_B

PB13 / SCK_B

PB12 / PCS1_B

PB11 / PCS2_B

Figure 16. Pin Assignments for MAC7121 in 112-pin LQFP

37

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Device Pin Assignments

4.3 MAC7101PV Pin Assignments

CNTX_A /PG4

CNRX_A /PG5

PH10 / AN10_B

PE9 / AN9_A

PH9 / AN9_B

PE8 / AN8_A

PH8 / AN8_B

PE7 / AN7_A

PH7 / AN7_B

PE6 / AN6_A / RDY'

PH6 / AN6_B

PE5 / AN5_A / MSEO'

PH5 / AN5_B

PE4 / AN4_A / MDO1'

PH4 / AN4_B

PE3 / AN3_A / MDO0'

PH3 / AN3_B

PE2 / AN2_A / EVTI'

PH2 / AN2_B

PE1 / AN1_A / EVTO'

PH1 / AN1_B

PE0 / AN0_A / MCKO'

PH0 / AN0_B

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

/

CNTX_C PG8

/

CNRX_C PG9

/

CNTX_D PG10

/

CNRX_D PG11

/

CNTX_B PG6

/

CNRX_B PG7

/PC0

/PC1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

/

PC2

PC3

V

DD

PB0

X

SS

V

X

/

SDA

SCL

SIN_A

PB1

PB2

/

SOUT_A PB3

MAC7101

144 LQFP

/

SCK_A

PB4

SS_A

PCS0_A PB5

/

PCS1_A PB6

/

PCS2_A PB7

/

V

PD15

X

SS

DD

PCSS_A PCS5_A PB8

/

eMIOS15 PF15

/

eMIOS14 PF14

/

PD14

PD13

PD4 / IRQ

PD3 / XIRQ

CLKOUT

eMIOS13 PF13

/

eMIOS12 PF12

/

PC4

/

PC5

/

/ XCLKS

PC6

/

V

X

SS

PC7

/

PB15 / SIN_B

eMIOS11 PF11

/

PB14 / SOUT_B

PB13 / SCK_B

PB12 / PCS1_B

PB11 / PCS2_B

eMIOS10 PF10

/

eMIOS9 PF9

/

eMIOS8 /PF8

eMIOS7 /PF7

PB10 / PCS5_B / PCSS_B

Figure 17. Pin Assignments for MAC7101 in 144-pin LQFP

38

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Device Pin Assignments

4.4 MAC7111PV Pin Assignments

CNTX_A / PG4

CNRX_A / PG5

CNTX_C / PG8

CNRX_C / PG9

CNTX_D / PG10

CNRX_D / PG11

CNTX_B / PG6

CNRX_B / PG7

ADDR0 / PC0

ADDR1 / PC1

ADDR2 / PC2

ADDR3 / PC3

PE9 / AN9_A

PE8 / AN8_A

PE7 / AN7_A

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

PE6 / AN6_A / RDY'

PE5 / AN5_A / MSEO'

PE4 / AN4_A / MDO1'

PE3 / AN3_A / MDO0'

PE2 / AN2_A / EVTI'

PE1 / AN1_A / EVTO'

PE0 / AN0_A / MCKO'

PA7 / DATA7

PA8 / DATA8

PA9 / DATA9

PA10 / DATA10

PA11 / DATA11

PA12 / DATA12

PD5 / ADDR16

PC15 / ADDR15

PC14 / ADDR14

PC13 / ADDR13

PC12 / ADDR12

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

V

/ PB0

/ PB1

X

SS

DD

X

SDA

SCL

SIN_A / PB2

SOUT_A / PB3

SCK_A / PB4

/ PCS0_A / PB5

PCS1_A / PB6

PCS2_A / PB7

MAC7111

144 LQFP

SS_A

V

X

DD

SS

PCSS_A / PCS5_A / PB8

eMIOS15/ PF15

eMIOS14/ PF14

eMIOS13/ PF13

eMIOS12/ PF12

ADDR4 / PC4

ADDR5 / PC5

ADDR6 / PC6

ADDR7 / PC7

eMIOS11/ PF11

eMIOS10/ PF10

eMIOS9 / PF9

eMIOS8 / PF8

eMIOS7 / PF7

PD15 / R/W

PD14 / CS0

PD13 / CS1

PD4 / IRQ

PD3 / XIRQ

CLKOUT

/ XCLKS

TA

PB15 / SIN_B

PB14 / SOUT_B

PB13 / SCK_B

PB12 / PCS1_B

PB11 / PCS2_B

PB10 / PCS5_B / PCSS_B

Figure 18. Pin Assignments for MAC7111 in 144-pin LQFP

39

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Device Pin Assignments

4.5 MAC7131VF Pin Assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

F

V_SS

X

V_SS

X

PG0 PG14 PA2

PG2 PG15 PA0

PA5 TCLK TDI

PE15 PE14 PH14 PE12 PH11

V_RL

V_RHV_DDA

V_SSX V_SS

X

PA4

PA3

TMS TDO

PD9 PH15 PE13 PH12 PE10 PH9 V_DD

A

PH8

PG5

PG3 V_SS

X

PG1

PA1

PA6 V_SS2.5 V_DD

X

PD6 PH13 PE11 V_DD

A

PE8

PE7

PH7

PH6

PH4

PH2

PE0

PG9

PG8

PG4 V_SS

X

V_SSX

V_SS2.5 V_SS2.5 PD10 PD8

PD7 V_SS

A

V_SS

A

PH10 PE9

PE6

PH5

PH3

PE1

PG6 PG11 PG10 V_SS

PE4

PE2

PH0

PA8

PE5

PE3

PH1

PA9

PC0

PB0

PB3

PB5

PB7

PG7

PC2

PB2

PB6

PC1 V_SS

PC3 V_SS

G

H

J

V_SS

X

V_SS

X

V_SS

X

V_SS

X

PB1 V_DD

X

PA7 PA10

PB4 V_SS

X

PD5 PA12 PA11 PC15

K

L

PB8 PF15 V_SS

PC13 PC12 PC14 V_DDX

PF14 PF13 PC4 V_SS

PD13 PD14 PD15 PD4

M

N

P

R

T

PF12 PC5

PC6 V_SS

V_SS

X

TA

PD3 CLKOUT

PF11 PF10 PC7 V_SS

V_SSR

V_SS2.5 V_SS2.5

V

PLL V_SSPLL V_SS

X

V_SS

X

PB11 PB14 PB15

SS

PF9

PF8 V_SS

X

PF5

PC8 PC10 V_DD

X

V_SS2.5 V_DD

R

V_DDX

PA15 PD11 PD12 V_SS

X

PB12 PB13

PF7 V_SS

X

PF6

PF3

PF2

PF1

PC9 PG12 PG13 V_SS

X

V_SSX

TEST PA13 PD1 PB10 V_SS

X

V_SS

X

V_SSX

PF4

PF0 PC11 RESET V_SSPLL XFC EXTAL XTAL PA14 PD0

PB9 V_SS

Figure 19. Pin Assignments for MAC7131 in 208-pin MAP BGA

40

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mechanical Information

5 Mechanical Information

5.1 100-Pin LQFP Package

L

60

41

61

40

B

P

-A-

-B-

L

V

B

-A-,-B-,-D-

DETAIL A

-D-

21

80

F

1

20

A

M

S

0.20

H A-B

D

0.05 A-B

J

N

S

M

S

0.20

C A-B

D

M

E

DETAIL C

M

S

0.20

C A-B

D

SECTION B-B

C

DATUM

PLANE

VIEW ROTATED 90

-H-

°

-C-

0.10

H

SEATING

PLANE

M

G

NOTES:

MILLIMETERS

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

DIM MIN MAX

A

B

C

D

E

F

13.90 14.10

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE

LEAD WHERE THE LEAD EXITS THE PLASTIC

BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B- AND -D- TO BE

2.15

0.22

2.00

0.22

2.45

0.38

2.40

0.33

U

T

G

H

J

0.65 BSC

DETERMINED AT DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE -C-.

DATUM

---

0.13

0.65

0.25

0.23

0.95

-H-

PLANE

R

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

K

L

M

N

P

12.35 REF

10

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B DO INCLUDE MOLD MISMATCH

AND ARE DETERMINED AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION. DAMBAR CANNOT

BE LOCATED ON THE LOWER RADIUS OR

THE FOOT.

5

°

0.13

0.17

0.325 BSC

K

Q

R

S

0

7

°

Q

°

W

0.13

0.30

16.95 17.45

X

T

U

V

W

X

0.13

0

---

DETAIL C

°

16.95 17.45

0.35

0.45

1.6 REF

Figure 20. 100-Pin LQFP Mechanical Dimensions (Case No. 983)

MAC7100 Microcontroller Family Hardware Specifications

41

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mechanical Information

5.2 112-Pin LQFP Package

4X

0.20 T L-M N

4X 28 TIPS

0.20 T L-M N

4X

P

J1

PIN 1

112

85

IDENT

C

1

84

L

VIEW Y

X

108X

G

X=L, M OR N

VIEW Y

V

B

L

M

AA

J

B1

V1

28

57

BASE

F

D

METAL

29

56

M

0.13

T L-M N

N

SECTION J1-J1

A1

S1

ROTATED 90 COUNTERCLOCKWISE

°

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

A

S

2. DIMENSIONS IN MILLIMETERS.

3. DATUMS L, MAND N TO BE DETERMINEDAT

SEATING PLANE, DATUM T.

4. DIMENSIONS S AND V TO BE DETERMINED

AT

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE. DIMENSIONS

A AND B INCLUDE MOLD MISMATCH.

6. DIMENSION D DOES NOT INCLUDE

C2

VIEW AB

0.10

θ2

C

0.050

112X

T

SEATING

PLANE

MILLIMETERS

DIM MIN MAX

θ3

A

A1

B

20.000 BSC

10.000 BSC

20.000 BSC

10.000 BSC

--- 1.600

T

B1

C

C1 0.050 0.150

C2 1.350 1.450

θ

D

E

F

G

J

0.270 0.370

0.450 0.750

0.270 0.330

0.650 BSC

0.090 0.170

0.500 REF

^RR2

K

P

0.325 BSC

R1 0.100 0.200

R2 0.100 0.200

0.25

R R1

S

S1

V

22.000 BSC

11.000 BSC

22.000 BSC

11.000 BSC

0.250 REF

1.000 REF

GAGE PLANE

V1

Y

Z

(K)

C1

θ1

AA 0.090 0.160

E

8 °

7 °

13 °

0 °

3 °

11 °

θ

θ1

θ2

θ3

(Y)

(Z)

VIEW AB

Figure 21. 112-Pin LQFP Mechanical Dimensions (Case No. 987)

42

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mechanical Information

5.3 144-Pin LQFP Package

0.20 T L-M N

4X

4X 36 TIPS

PIN 1

144

109

IDENT

1

108

4X

P

J1

L

M

C

L

V

B

X

X=L, M OR N

140X

G

B1

V1

VIEW Y

36

73

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

37

72

N

3. DATUMS L, M, N TO BE DETERMINED AT THE

SEATING PLANE, DATUM T.

A1

S1

4. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.

5. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

A

S

0.25 PER SIDE. DIMENSIONS

A

AND

B

DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE H.

6. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION.

ALLWABLE

DAMBAR

PROTRUSION SHALL NOT CAUSE THE

DIMENSION TO EXCEED 0.35.

D

VIEW AB

C

144X

MILLIMETERS

0.1 T

θ2

DIM MIN MAX

A

A1

B

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

SEATING

PLANE

B1

C

1.40

0.05

1.35

0.17

0.45

0.17

1.60

T

C1

C2

D

0.15

1.45

0.27

0.75

0.23

E

PLATING

F

G

0.50 BSC

J

C2

AA

F

J

0.09

0.20

0.05

K

0.50 REF

P

0.25 BSC

R2

R1

R2

S

0.13

0.20

θ

R1

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

0.25 REF

1.00 REF

S1

V

BASE

0.25

V1

Y

D

METAL

GAGE PLANE

Z

M

0.08

T L-M N

AA

θ

0.09

0.16

0

°

SECTION J1-J1

(K)

E

θ1

θ2

7

°

(ROTATED 90

144 PL

)

°

11

13

C1

θ 1

(Y)

VIEW AB

(Z)

Figure 22. 144-Pin LQFP Mechanical Dimensions (Case No. 918)

43

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mechanical Information

5.4 208-Pin MAP BGA Package

IDENTIFICATION IN THIS AREA

LASER MARK FOR PIN A1

M

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

K

2. INTERPRET DIMENSIONS AND TOLERANCES PER

ASME Y14.5M, 1994.

3. DIMENSION b IS MEASURED AT THE MAXIMUM

SOLDER BALL DIAMETER, PARALLEL TO DATUM

PLANE Z.

4. DATUM Z (SEATING PLANE) IS DEFINED BY THE

SPHERICAL CROWNS OF THE SOLDER BALLS.

5. PARALLELISM MEASEMENT SHALL EXCLUDE ANY

EFFECT OF MARK ON TOP SURFACE OF PACKAGE.

E

MILLIMETERS

DIM

A

A1

A2

b

MIN

---

0.40

1.00

0.50

MAX

2.00

0.60

1.30

0.70

M

X

D

X

4X

0.2

D

17.00 BSC

E

e

S

17.00 BSC

1.00 BSC

0.50 BSC

15X

e

METALIZED MARK FOR PIN A1

IDENTIFICATION IN THIS AREA

S

3

208X

b

A

B

C

D

E

F

M

0.3

0.1

X

Z

Y

Z

5

0.2

Z

G

H

J

A2

A

15X

e

K

L

M

N

P

R

T

A1

208X

Z

0.2

S

4

Z

16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

VIEW K

(ROTATED 90˚ CLOCKWISE)

VIEW M M

Figure 23. 208-Pin MAP BGA Mechanical Dimensions (Case No. 1159A-01)

44

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mechanical Information

THIS PAGE INTENTIONALLY LEFT BLANK

45

MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

HOW TO REACH US:

USA / EUROPE / Locations Not Listed:

Motorola Literature Distribution

P.O. Box 5405

Denver, Colorado 80217

1-800-521-6274 or 480-768-2130

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo, 106-8573 Japan

81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.

Silicon Harbour Centre

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

852-26668334

HOME PAGE:

http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software implementers to

use Motorola products. There are no express or implied copyright licenses granted hereunder to

design or fabricate any integrated circuits or integrated circuits based on the information in this

document.

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application

or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. Motorola does not

convey any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other

application in which the failure of the Motorola product could create a situation where personal

injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages,

and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.

All other product or service names are the property of their respective owners. Motorola, Inc. is

an Equal Opportunity/Affirmative Action Employer.

MAC7100EC/D, Rev. 0.1,