MC100EP223TC [MOTOROLA]
Low-Voltage 1:22 Differential PECL/HSTL Clock Driver; 低电压1:22差分PECL / HSTL时钟驱动器型号: | MC100EP223TC |
厂家: | MOTOROLA |
描述: | Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
文件: | 总8页 (文件大小:87K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC100EP223 is a low skew 1–to–22 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The selected signal is fanned out to 22 identical differential
outputs.
LOW–VOLTAGE
1:22 DIFFERENTIAL
PECL/HSTL CLOCK DRIVER
•
•
•
•
•
•
•
•
200ps Part–to–Part Skew
50ps Output–to–Output Skew
Differential Design
Open Emitter HSTL Compatible Outputs
3.3V V
CC
Both PECL and HSTL Inputs
75kΩ Input Pulldown Resistors
Thermally Enhanced 64 lead Exposed Pad LQFP
The EP223 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent t distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
TC SUFFIX
64–LEAD LQFP PACKAGE
CASE 840K–01
pd
The EP223 HSTL outputs are not realized in the conventional
manner. To minimize part–to–part and output–to–output skew, the HSTL
compatible output levels are generated with an open emitter
architecture. The outputs are pulled down with 50Ω to ground, rather
than the typical 50Ω to V
pullup of a “standard” HSTL output.
DDQ
Because the HSTL outputs are pulled to ground, the EP223 does not
utilize the V supply of the HSTL standard. The output levels are
DDQ
derived from V
.
CC
In the case of an asynchronous control, there is a chance of
generating a ‘runt’ clock pulse when the device is enabled/disabled. To
avoid this, the output enable (OE) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50Ω, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In
the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
03/01
REV 2
Motorola, Inc. 2001
MC100EP223
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCCO
Q6B
Q6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCCO
Q14
Q14B
Q15
Q5B
Q5
Q15B
Q16
Q4B
Q4
Q16B
Q17
Q3B
Q3
MC100EP223
Q17B
Q18
Q2B
Q2
Q18B
Q19
Q1B
Q1
Q19B
Q20
Q0B
Q0
Q20B
VCCO
VCCO
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Figure 1. 64–Lead Pinout (Top View)
CLK_SEL
PIN NAMES
Pins
HSTL_CLK
0
1
Function
Differential HSTL Inputs
HSTL_CLK
22
22
Q0 – Q21
Q0 – Q21
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB Differential PECL Inputs
Q0:21, Q0B:21B
CLK_SEL
OE
LVPECL_CLK
LVPECL_CLK
Differential HSTL Outputs
Active Clock Select Input
Output Enable
Ground
LEN
Q
D
OE
GND
VCCI
VCCO
Core VCC
I/O VCC
Figure 2. Logic Symbol
SIGNAL GROUPS
FUNCTION
OE
CLK_SEL
Q0:21, Q0B:21B
Level
Direction
Signal
0
0
1
1
0
1
0
1
Q = Low, QB = High
Q = Low, QB = High
HSTL_CLK, HSTL_CLKB
PECL_CLK, PECL_CLKB
HSTL
HSTL
LVPECL
LVCMOS/LVTTL
Input
Output
Input
HSTL_CLK, HSTL_CLKB
Q0:21, Q0B:21B
PECL_CLK, PECL_CLKB
CLK_SEL, OE
Input
MOTOROLA
2
TIMING SOLUTIONS
DL207 — Rev 0
MC100EP223
HSTL DC CHARACTERISTICS
0°C
25°C
85°C
Symbol
Characteristic
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
V
V
V
V
V
1.0
OH
OL
IH
0.4
1.6
V
V +0.1
–0.3
V
Input LOW Voltage
V –0.1
0.9
V
IL
Input Crossover Voltage
0.68
V
PECL DC CHARACTERISTICS
0°C
25°C
85°C
Symbol
Characteristic
Input HIGH Voltage (Note 1.)
Input LOW Voltage (Note 1.)
Input HIGH Current
Min
Typ
Max
2.420
1.825
150
Min
Typ
Max
2.420
1.825
150
Min
Typ
Max
2.420
1.825
150
Unit
V
V
V
2.135
1.490
2.135
1.490
2.135
1.490
IH
V
IL
I
IH
µA
1. These values are for V
CC
= 3.3V. Level specifications vary 1:1 with V
.
CC
AC CHARACTERISTICS (V
EE
= GND, V
=V
to V
)
CC(max)
CC
CC(min)
0°C
25°C
85°C
Symbol
Characteristic
Propagation Delay to Output
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
t
t
,
ns
PLH
PHL
IN (Differential)
1.0
1.0
1.0
t
Within–Device Skew
Part–to–Part Skew (Diff)
50
200
50
200
50
200
ps
skew
f
Maximum Input Frequency
250
250
250
MHz
mV
V
max
V
V
Minimum Input Swing PECL_CLK
CommonMode Range PECL_CLK
Output Rise/Fall Time (20–80%)
600
600
600
PP
CMR
t , t
r f
300
600
300
600
300
600
ps
Power Supply Characteristics
Symbol
Characteristic
Min
Typ
Max
Unit
V
V
CCI
Core V
CC
3.0
1.6
3.3
1.8
3.6
2.0
V
CCO
I/O V
CC
V
I
I
Power Supply Current
Power Supply Current
mA
mA
CC
EE
TIMING SOLUTIONS
DL207 — Rev 0
3
MOTOROLA
MC100EP223
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
Thermal Resistance
MC100EP223
a
b
c
d
Convection
LFPM
R
R
R
R
THJB
THJA
THJA
THJC
The MC100EP223 uses a thermally enhanced 64 lead
LQFP package. This package provides the low thermal
impedance that supports the power consumption of the
MC100EP223 high-speed bipolar integrated circuit and
eases the power management task for the system design. An
exposed pad at the bottom of the package establishes
thermal conductivity from the package to the printed circuit
board. In order to take advantage of the enhanced thermal
capabilitites of this package, it is recommended to solder the
exposed pad of the package to the printed circuit board. The
attachment process for exposed pad package is the same as
for any standard surface mount package. Vias are
recommended from the pad on the board down to an
appropriate plane in the board that is capable of distributing
the heat. In order to supply enough solder paste to fill those
vias and not starve the solder joints, it may be required to
stencil print solder paste onto the printed circuit pad. This pad
should match the dimensions of the exposed pad. The
dimensions of the exposed pad are shown on the package
outline in this specification. For thermal system analysis and
junction temperature calculation the thermal resistance
parameters of the package is provided:
°C/W
°C/W
°C/W
°C/W
Natural
100
57.1
50.0
46.9
43.4
38.6
24.9
21.3
20.0
18.7
16.9
200
15.8
9.7
400
800
a. Junction to ambient, single layer test board, per JESD51-6
b. Junction to ambient, four conductor layer test board (2S2P),
per JES51-6
c. Junction to case, per MIL-SPEC 883E, method 1012.1
d. Junction to board, four conductor layer test board (2S2P) per
JESD 51-8
It is recommended that users employ thermal modeling
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100EP223 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals.
MOTOROLA
4
TIMING SOLUTIONS
DL207 — Rev 0
MC100EP223
OUTLINE DIMENSIONS
TC SUFFIX
PLASTIC LQFP PACKAGE, EXPOSED PAD
CASE 840K–01
ISSUE O
4X
4X 16 TIPS
A2
0.2 H A–B D
0.2
C
A–B D
S
0.05
D
(S)
PIN 1
IDENTIFIER
64
49
R
Z1
1
48
0.25
GAGE PLANE
Z
A
B
R1
A1
L
E
E1
(L1)
VIEW AA
3X
E1/2
VIEW Y
E/2
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M–1994.
3. DATUMS A, B AND D TO BE DETERMINED AT DATUM
PLANE H.
16
33
17
32
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
D1/2
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN 0.08 mm.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSION 0.07 mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm
PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY
SIZE DIMENSIONS INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
D/2
D1
D
H
A
4X Z2
4X Z3
0.08 C
J
J
64X b
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM
THE LEAD TIP.
SEATING
PLANE
C
VIEW AA
M
0.08
C A–B D
MILLIMETERS
DIM MIN
MAX
1.60
0.15
1.45
0.27
0.23
0.20
0.16
X
A
A1
A2
b
b1
c
–––
0.05
1.35
0.17
0.17
0.09
0.09
12.00 BSC
10.00 BSC
0.50 BSC
X=A, B OR D
C
L
c1
D
AB
AB
e/2
D1
e
60X e
F
E
E1
L
12.00 BSC
10.00 BSC
BASE METAL
VIEW Y
0.45
0.75
L1
R1
R2
S
F
G
1.00 REF
8
b1
0.08
0.08
0.20
6.00
6.00
0
–––
–––
–––
7.00
7.00
7
G
8
c1
8
c
Z
Z1
Z2
Z3
0
11
11
–––
13
13
8
b
PLATING
SECTION AB–AB
ROTATED 90 CLOCKWISE
EXPOSED PAD
VIEW J–J
TIMING SOLUTIONS
DL207 — Rev 0
5
MOTOROLA
MC100EP223
NOTES
MOTOROLA
6
TIMING SOLUTIONS
DL207 — Rev 0
MC100EP223
NOTES
TIMING SOLUTIONS
DL207 — Rev 0
7
MOTOROLA
MC100EP223
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guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the
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and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
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◊
MC100EP223/D
DL207 — Rev 0
相关型号:
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