MC10111PD [MOTOROLA]
NOR Gate, ECL, PDIP16;
| 型号： | MC10111PD |
| 厂家： | 
MOTOROLA |
| 描述： | NOR Gate, ECL, PDIP16 栅 |
| 文件： | 总4页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC10111 is designed to drive up to three transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines from a single point makes the
MC10111 particularly useful in clock distribution applications where minimum
clock skew is desired. Three V
used.
pins are provided and each one should be
CC
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P
= 80 mW typ/gate (No Load)
= 2.4 ns typ (All Outputs Loaded)
D
t
pd
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
t , t = 2.2 ns typ (20%–80%)
r f
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
2
3
4
5
6
7
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CC2
CC1
OUT
OUT
OUT
OUT
OUT
OUT
12
13
14
A
A
9
10
11
A
IN
V
V
V
= PIN 1,15
= PIN 16
= PIN 8
CC1
CC2
EE
B
B
B
A
IN
IN
IN
IN
A
IN
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
Motorola, Inc. 1996
REV 6
MC10111
ELECTRICAL CHARACTERISTICS
Test Limits
+25°C
Typ
Pin
Under
Test
–30°C
+85°C
Characteristic
Power Supply Drain Current
Input Current
Symbol
Unit
mAdc
µAdc
µAdc
Min
Max
42
Min
Max
38
Min
Max
42
I
E
8
30
I
5, 6, 7
5, 6, 7
680
425
425
inH
I
0.5
0.5
0.3
inL
Output Voltage
Logic 1
V
2
3
4
–1.060
–1.060
–1.060
–0.890
–0.890
–0.890
–0.960
–0.960
–0.960
–0.810
–0.810
–0.810
–0.890
–0.890
–0.890
–0.700
–0.700
–0.700
Vdc
Vdc
Vdc
Vdc
ns
OH
Output Voltage
Logic 0
Logic 1
Logic 0
V
2
3
4
–1.890
–1.890
–1.890
–1.675
–1.675
–1.675
–1.850
–1.850
–1.850
–1.650
–1.650
–1.650
–1.825
–1.825
–1.825
–1.615
–1.615
–1.615
OL
Threshold Voltage
Threshold Voltage
V
OHA
2
3
4
–1.080
–1.080
–1.080
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
V
OLA
2
3
4
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.595
–1.595
–1.595
Switching Times (50Ω Load)
Propagation Delay
t
t
t
t
t
t
2
2
3
3
4
4
1.4
1.4
1.4
1.4
1.4
1.4
3.5
3.5
3.5
3.5
3.5
3.5
1.4
1.4
1.4
1.4
1.4
1.4
2.4
2.4
2.4
2.4
2.4
2.4
3.5
3.5
3.5
3.5
3.5
3.5
1.5
1.5
1.5
1.5
1.5
1.5
3.8
3.8
3.8
3.8
3.8
3.8
5+2–
5–2+
5+3–
5–3+
5+4–
5–4+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
t
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8
2+
3+
4+
t
t
t
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8
2–
3–
4–
3–45
MOTOROLA
MC10111
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
V
V
ILmin
V
V
V
EE
IHmax
IHAmin
ILAmax
–30°C
+25°C
+85°C
–0.890
–0.810
–0.700
–1.890
–1.850
–1.825
–1.205
–1.105
–1.035
–1.500
–1.475
–1.440
–5.2
–5.2
–5.2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Pin
Under
Test
(V
CC
)
Gnd
Characteristic
Power Supply Drain Current
Input Current
Symbol
V
V
ILmin
V
V
V
EE
IHmax
IHAmin
ILAmax
I
E
8
8
1, 15, 16
1, 15, 16
1, 15, 16
I
5, 6, 7
5, 6, 7
*
8
8
inH
I
*
inL
Output Voltage
Logic 1
Logic 0
V
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OH
Output Voltage
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OL
Threshold Voltage
Threshold Voltage
Logic 1
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OHA
Logic 0
V
2
3
4
5
6
7
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
OLA
Switching Times
(50Ω Load)
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t
t
t
t
t
t
2
2
3
3
4
4
5
5
5
5
5
5
2
2
3
3
4
4
8
8
8
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
1, 15, 16
5+2–
5–2+
5+3–
5–3+
5+4–
5–4+
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
t
t
t
2
3
4
5
5
5
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
2+
3+
4+
t
t
t
2
3
4
5
5
5
2
3
4
8
8
8
1, 15, 16
1, 15, 16
1, 15, 16
2–
3–
4–
* Individually test each input using the pin connections shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
MOTOROLA
3–46
MC10111
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
–A–
NOTES:
ISSUE V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
0.25 (0.010)
T B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
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MC10111/D
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