MC12206D [MOTOROLA]
MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer; MECL PLL元件串行输入锁相环频率合成器
| 型号： | MC12206D |
| 厂家： | 
MOTOROLA |
| 描述： | MECL PLL COMPONENTS Serial Input PLL Frequency Synthesizer |
| 文件： | 总12页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC12206 is a 2.0GHz Bipolar monolithic serial input phase locked
loop (PLL) synthesizer with pulse–swallow function. It is designed to
provide the high frequency local oscillator signal of an RF transceiver in
handheld communication applications.
MECL PLL COMPONENTS
Motorola’s advanced Bipolar MOSAIC V technology is utilized for
low power operation at a minimum supply voltage of 2.7V. The device is
designed for operation over 2.7 to 5.5V supply range for input frequencies
up to 2.0GHz with a typical current drain of 7.4mA. The low power
consumption makes the MC12206 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN or
personal communication services. A dual modulus prescaler is integrated
to provide either a 64/65 or 128/129 divide ratio.
Serial Input PLL
Frequency Synthesizer
For additional applications information, two InterActiveApNote
documents containing software (based on a Microsoft Excel
spreadsheet) and an Application Note are available. Please order
DK305/D and DK306/D from the Motorola Literature Distribution Center.
16
1
• Low Power Supply Current of 6.7mA Typical for I
and 0.7mA Typical
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
CC
for I
P
• Supply Voltage of 2.7 to 5.5V
• Dual Modulus Prescaler With Selectable Divide Ratios of 64/65 or
128/129
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a Binary 14–Bit
20
1
Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit Swallow Counter
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–03
and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First Stage of the Loop
Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of –40°C to +85°C
• Space Efficient Plastic Surface Mount SOIC or TSSOP Packages
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VDC
VDC
°C
V
V
Power Supply Voltage, Pin 4 (Pin 5 in 20–lead package)
Power Supply Voltage, Pin 3 (Pin 4 in 20–lead package)
Storage Temperature Range
–0.5 to +6.0
CC
V
to +6.0
P
CC
T
–65 to +150
stg
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.
1/97
REV 3
Motorola, Inc. 1997
MC12206
φ
R
φ
P
f
BISW FC
13 12
LE
11
DATA CLK
OUT
16
15
14
10
9
Pinout: 16–Lead Package (Top View)
1
2
3
4
5
6
7
8
OSCin OSCout
V
V
Do
GND
LD
f
P
CC
IN
φ
R
NC
19
φ
P
f
BISW
16
FC
15
LE
14
DATA
13
NC
12
CLK
11
OUT
20
18
17
Pinout: 20–Lead Package (Top View)
1
2
3
4
5
6
7
8
9
10
OSCin
NC OSCout
V
V
Do
GND
LD
NC
f
IN
P
CC
PIN NAMES
16–Lead Pkg 20–Lead Pkg
Pin
I/O
Function
Pin No.
Pin No.
OSCin
I
Oscillator input. A crystal is connected between OSCin and OSCout. An external
source can be AC coupled into this input
1
1
OSCout
O
Oscillator output. Pin should be left open if external source is used
2
3
3
4
V
P
—
Power supply for charge pumps (V should be greater than or equal to V ) V
CC P
P
provides power to the Do, BISW and φP outputs
V
CC
—
Power supply voltage input. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
4
5
Do
O
—
O
I
Internal charge pump output. Do remains on at all times
Ground
5
6
6
7
GND
LD
Lock detect, phase comparator output
7
8
f
IN
Prescaler input. The VCO signal is AC–coupled into this pin
Clock input. Rising edge of the clock shifts data into the shift registers
Binary serial data input
8
10
11
13
14
CLK
DATA
LE
I
9
I
10
11
I
Load enable input (with internal pull up resistor). When LE is HIGH or OPEN, data
stored in the shift register is transferred into the appropriate latch (depending on
the level of control bit). Also, when LE is HIGH or OPEN, the output of the second
internal charge pump is connected to the BISW pin
FC
I
Phase control select (with internal pull up resistor). When FC is LOW, the
characteristics of the phase comparator and charge pump are reversed. FC also
12
13
14
15
16
17
selects fp or fr on the f
pin
OUT
BISW
O
O
Analog switch output. When LE is HIGH or OPEN (“analog switch is ON”) the
output of the second charge pump is connected to the BISW pin. When LE is LOW,
BISW is high impedance
f
Phase comparator input signal. When FC is HIGH, f
=fr, programmable
OUT
OUT
reference divider output; when FC is LOW, f
=fp, programmable divider output
OUT
φP
φR
NC
O
O
Output for external charge pump. Standard CMOS output level
Output for external charge pump. Standard CMOS output level
No connect
15
16
—
18
20
—
2, 9, 12, 19
MOTOROLA
2
HIPERCOMM
BR1334 — Rev 4
MC12206
15–BIT SHIFT REGISTER
15
15–BIT LATCH
14
1
PROGRAMMABLE REFERENCE DIVIDER
OSCin
fr
LD
CRYSTAL
OSCILLATOR
14–BIT REFERENCE COUNTER
OSCout
φP
PHASE/FREQUENCY
DETECTOR
φR
CHARGE
PUMP 1
Do
FC
LE
LE
CONTROL
BIT
DATA
CHARGE
PUMP 2
DATA
BISW
18–BIT SHIFT REGISTER
7
11
DIVIDER
OUTPUT MUX
f
OUT
CLK
7–BIT
LATCH
11–BIT LATCH
11
7
PROGRAMMABLE DIVIDER
PRESCALER
f
IN
64/65 or 128/129
7–BIT
SWALLOW
A–COUNTER
11–BIT
PROGRAMMABLE
N–COUNTER
fp
CONTROL LOGIC
Figure 1. MC12206 Block Diagram
HIPERCOMM
BR1334 — Rev 4
3
MOTOROLA
MC12206
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit
programmable reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock
shifts one bit of serial data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred
into the latch when load enable pin is HIGH or OPEN.
Control bit:
“H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will
affect the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If
the control bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to
16383) and the prescaler divide ratio (SW=0 for ÷128/129, SW=1 for ÷64/65). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
S
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
C
W
14
13
12
11
10
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide
Ratio R
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
R
4
R
3
R
2
R
1
5
0
0
•
8
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
0
•
0
0
•
0
1
•
9
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PRESCALER SELECT BIT
Prescaler Divide Ratio P
128/129
SW
0
64/65
1
MOTOROLA
4
HIPERCOMM
BR1334 — Rev 4
MC12206
PROGRAMMABLE DIVIDER
19–bit serial data format for the programmable divider is shown below. If the control bit is LOW, data is transferred from the 18–bit
shift register into the 18–bit latch which specifies the swallow A–counter divide ratio (0 to 127) and the programmable N–counter
divide ratio (16 to 2047). An N–counter divide ratio less than 16 is prohibited.
For Control bit (C) = LOW:
MSB (FIRST BIT)
CONTROL BIT (LAST BIT)
LSB
N
N
N
N
N
N
N
N
N
N
9
N
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
C
18 17 16 15 14 13 12 11 10
SETTING BITS FOR
DIVIDE RATIO OF
SETTING BITS FOR
DIVIDE RATIO OF
PROGRAMMABLE N–COUNTER
SWALLOW A–COUNTER
DIVIDE RATIO OF PROGRAMMABLE N–COUNTER
DIVIDE RATIO OF SWALLOW A–COUNTER
Divide
Ratio N
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
Divide
Ratio A
A
7
A
6
A
5
A
4
A
3
A
2
A
1
8
0
1
•
16
17
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
0
•
0
0
•
0
0
•
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
127
1
1
1
1
1
1
1
DIVIDE RATIO SETTING
fvco = [(P•N)+A]•fosc ÷ R with A<N
fvco: Output frequency of external voltage controlled oscillator (VCO)
N:
A:
Preset divide ratio of binary 11–bit programmable counter (16 to 2047)
Preset divide ratio of binary 7–bit swallow counter (0 to 127, A<N)
fosc: Output frequency of the external frequency oscillator
R:
P:
Preset divide ratio of binary 14–bit programmable reference counter (8 to 16383)
Preset mode of dual modulus prescaler (64 or 128)
DATA
CLK
N18:MSB
(SW:MSB)
N17
N8
A7
A1
C = CONTROL BIT (LAST BIT)
(C = CONTROL BIT (LAST BIT))
(R14)
(R7)
(R6)
(R1)
LE
t (C
→LE)
s
t (D)
t (D)
t
t
EW
s
h
CW
NOTES:Programmable reference divider data shown in parenthesis. Data shifted into register on rising edge of CLK.
t (D) = Setup Time DATA to CLK
t (D)
≥
≥
≥
≥
≥
10ns
20ns
30ns
20ns
30ns
s
s
t (D) = Hold Time DATA to CLK
t (D)
h
CW
h
t
= CLK Pulse Width
= LE Pulse Width
t
CW
t
t
EW
EW
LE)
t (C
→
LE) = Setup Time CLK to LE
t (C→
s
s
Figure 2. Serial Data Input Timing
HIPERCOMM
5
MOTOROLA
BR1334 — Rev 4
MC12206
PHASE CHARACTERISTICS/VCO CHARACTERISTICS
The phase comparator in the MC12206 is a high speed digital phase frequency detector circuit. The circuit determines the “lead”
or “lag” phase relationship and time difference between the leading edges of the VCO (fp) signal and the reference (fr) input.
Since these edges occur only once per cycle, the detector has a range of ±2π radians. The phase comparator outputs are
standard CMOS rail–to–rail levels (V to GND for φP and V
load. These phase comparator outputs can be used along with an external charge pump to enhance the PLL characteristics.
to GND for φR), designed for up to 20MHz operation into a 15pF
P
CC
The operation of the phase comparator is shown in Figures 3 and 5. The phase characteristics of the phase comparator are
controlled by the FC pin. The polarity of the phase comparator outputs, φR and φP, as well as the charge pump output Do can be
reversed by switching the FC pin.
H
fr
L
H
fp
L
H
LD
L
Source
Do (FC = H)
BISW (LE = H or Open)
Z
Sink
H
φR (FC = H)
L
H
L
φP (FC = H)
Source
Do (FC = L)
Z
BISW (LE = H or Open)
Sink
H
L
φR (FC = L)
H
L
φP (FC = L)
NOTES: Do and BISW are current outputs.
Phase difference detection range: –2
π
to +2π
Spike difference depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
I
I
sink
source
4
4mA
4
Internal Charge Pump Gain
Figure 3. Phase/Frequency Detector, Internal Charge Pump and Lock Detect Waveforms
MOTOROLA
6
HIPERCOMM
BR1334 — Rev 4
MC12206
For FC = HIGH:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR
output will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φR indicates to the VCO to decrease in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φR output will remain in a LOW state while the φP
output pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φP indicates to the VCO to increase in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
When FC = LOW, the operation of the phase comparator is reversed from the above explanation.
For FC = LOW:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP
output will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φP indicates to the VCO to increase in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φP output will remain in a HIGH state while the φR
output pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition.
The signal on φR indicates to the VCO to decrease in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will
maintain the loop in its locked state.
The FC pin controls not only the phase characteristics, but also controls the f
test pin. The FC pin permits the user to monitor
OUT
output providing a test mode where the programming of the
either of the phase comparator input signals, fr or fp, at the f
OUT
dividers and the output of the counters can be checked. When FC is HIGH, f
= fr, the programmable reference divider output.
OUT
When FC is LOW, f
= fp, the programmable divider output.
OUT
Hence,
If VCO characteristics are like (1), FC should be set HIGH or OPEN.
If VCO characteristics are like (2), FC should be set LOW.
f
f
= fr
OUT
OUT
= fp
( 1 )
FC = HIGH or OPEN
FC = LOW
Do
φR
L
φP
L
f
Do
L
φR
H
L
φP
H
f
OUT
OUT
fp < fr
fp > fr
fp = fr
H
L
fr
fp
H
L
H
fr
fr
H
L
fp
fp
Z
H
Z
L
H
NOTES:Z = High impedance
When LE is HIGH or Open, BISW has the same
characteristics as Do.
( 2 )
VCO INPUT VOLTAGE
Figure 5. Phase Comparator, Internal Charge Pump, and
f
Characteristics
OUT
Figure 4. VCO Characteristics
HIPERCOMM
BR1334 — Rev 4
7
MOTOROLA
MC12206
UP
fr
0
1
φ
P
R
V
PHASE
FREQUENCY
DETECTOR
DOWN
φR
fp
0
1
LD
PHASE COMPARATOR
CHARGE
PUMP 1
Do
FC
LE
CHARGE
PUMP 2
BISW
Figure 6. Detailed Phase Comparator Block Diagram
LOCK DETECT
The Lock Detect (LD) output pin provides a LOW pulse when fr and fp are not equal in phase or frequency. The output is normally
HIGH. LD is designed to be the logical NORing of the phase frequency detector’s outputs UP and DOWN. See Figure 6. In typical
applications the output signal drives external circuitry which provides a steady LOW signal when the loop is locked. See Figure 9.
OSCILLATOR INPUT
For best operation, an external reference oscillator is recommended. The signal should be AC–coupled to the OSCin pin through
a coupling capacitor. In this case, no connection to OSCout is required. The magnitude of the AC–coupled signal must be
between 500 and 2200 mV peak–to–peak. To optimize the phase noise of the PLL when used in this mode, the input signal
amplitude should be closer to the upper specification limit. This maximizes the slew rate of the signal as it switches against the
internal voltage reference.
The device incorporates an on–chip reference oscillator/buffer so that an external parallel–resonant fundamental crystal can be
connected between OSCin and OSCout. External capacitor C1 and C2 as shown in Figure 10 are required to set the proper
crystal load capacitance and oscillator frequency. The values of the capacitors are dependent on the crystal chosen (up to a
maximum of 30 pF each including parasitic and stray capacitance).
DUAL INTERNAL CHARGE PUMPS (“ANALOG SWITCH”)
Due to the pure Bipolar nature of the MC12206 design, the “analog switch” function is implemented with dual internal charge
pumps. The loop filter time constant can be decreased by bypassing the first stage of the loop filter with the charge pump output
BISW as shown in Figure 7 below. This enables the VCO to lock in a shorter amount of time.
When LE is HIGH or OPEN (“analog switch is ON”), the output of the second internal charge pump is connected to the BISW pin,
and the Do output is ON. The charge pump 2 output on BISW is essentially equal to the charge pump 1 output on Do. When LE is
LOW, BISW is in a high impedance state and Do output is active.
Do
CHARGE
LPF–1
LPF–2
VCO
PUMP 1
BISW
CHARGE
PUMP 2
LE
Figure 7. “Analog Switch” Block Diagram
MOTOROLA
8
HIPERCOMM
BR1334 — Rev 4
MC12206
ELECTRICAL CHARACTERISTICS (V
= 2.7 to 5.5V; T = –40 to +85°C)
A
CC
Symbol
Parameter
Min
Typ
6.7
8.1
0.7
0.8
Max
10.5
12.5
1.1
Unit
Condition
I
Supply Current for V
mA
Note 1
Note 2
Note 3
Note 4
Note 5
CC
CC
I
Supply Current for V
mA
P
P
1.3
F
F
Operating Frequency
f
max
2000
MHz
IN
IN
f
min
500
20
IN
Operating Frequency (OSCin)
Input Sensitivity
12
MHz
MHz
Crystal Mode
External Reference Mode
OSC
40
V
V
V
V
f
IN
200
500
1000
2200
mV
IN
P–P
OSCin
mV
OSC
IH
P–P
Input HIGH Voltage
Input LOW Voltage
CLK, DATA, LE, FC
CLK, DATA, LE, FC
0.7V
CC
V
0.3V
CC
V
V
CC
V
CC
V
CC
= 5.5V
= 5.5V
= 5.5V
IL
I
I
I
Input HIGH Current (DATA and CLK)
Input LOW Current (DATA and CLK)
Input Current (OSCin)
1.0
2.0
µA
µA
µA
IH
–10
–5.0
IL
130
–310
OSCin = V
OSCin = V
OSC
CC
CC
– 2.2V
I
I
I
I
I
Input HIGH Current (LE and FC)
Input LOW Current (LE and FC)
Charge Pump Output Current
Do and BISW
1.0
–60
–2.0
+2.0
2.0
µA
µA
IH
–75
–2.6
+1.4
–15
IL
6
–1.4
+2.6
+15
mA
V
= V /2; V = 2.7V
Do P P
Source
6
V
BISW
= V /2; V = 2.7V
Sink
P
P
nA
0.5 < V
0.5 < V
< V – 0.5
DO P
Hi–Z
< V – 0.5
BISW
P
V
V
I
4.4
2.4
V
V
V
CC
V
CC
V
CC
V
CC
= 5.0V
= 3.0V
= 5.0V
= 3.0V
Output HIGH Voltage (LD, φR, φP, f
)
OH
OUT
0.4
0.4
V
Output LOW Voltage (LD, φR, φP, f
)
OL
OUT
V
–1.0
1.0
mA
mA
Output HIGH Current (LD, φR, φP, f
Output LOW Current (LD, φR, φP, f
)
OH
OUT
I
)
OL
OUT
1. V
2. V
= 3.3V, all outputs open.
= 5.5V, all outputs open.
4. V = 6.0V, all outputs open.
P
CC
CC
5. AC coupling, F measured with a 1000pF capacitor.
IN
3. V = 3.3V, all outputs open.
6. Sourcecurrent flows out of the pin and sink current flows into the pin.
P
V
P
V
CC
10k
Ω
Ω
12k
Ω
Ω
100kΩ
φP
33kΩ
LD
EXTERNAL CHARGE
PUMP OUTPUT
LOCK DETECT
OUTPUT
0.01µF
φR
12k
10kΩ
10k
Figure 8. Typical External Charge Pump Circuit
Figure 9. Typical Lock Detect Circuit
HIPERCOMM
BR1334 — Rev 4
9
MOTOROLA
MC12206
C1
1
2
3
16
15
14
13
12
11
10
9
φ
R
OSCin
LOW PASS
FILTER
(SEE FIGURE 11)
EXTERNAL
CHARGE PUMP
(SEE FIGURE 8)
VCO
φP
OSCout
C2
100pF
100pF
CHARGE PUMP SELECTION
(INTERNAL OR EXTERNAL)
V
P
FOUT
BISW
FC
V
P
0.1
µF
V
CC
4
V
CC
0.1
µF
MC12206
5
Do
6
7
8
LE
GND
LD
LOCK DETECT
CIRCUIT
(SEE FIGURE 9)
LOCK
DETECT
DATA
CLK
FROM
CONTROLLER
47kΩ
f
in
1000pF
47kΩ
C1, C2: Dependent on Crystal Oscillator
Figure 10. Typical Applications Example (16–Pin Package)
BISW
Do OR EXTERNAL
CHARGE PUMP
VCO
R
C
Figure 11. Typical Loop Filter
MOTOROLA
10
HIPERCOMM
BR1334 — Rev 4
MC12206
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
ISSUE J
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
12 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T
U
V
S
0.15 (0.006)
T U
13 CONTROLLING DIMENSION: MILLIMETER.
14 DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
15 DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
16 DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
17 TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
S
18 DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
HIPERCOMM
BR1334 — Rev 4
11
MOTOROLA
MC12206
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