MC13XX [MOTOROLA]
UNIVERSAL NARROWBAND FM RECEIVER INTEGRATED CIRCUIT; 通用窄带FM接收器集成电路
| 型号： | MC13XX |
| 厂家： | 
MOTOROLA |
| 描述： | UNIVERSAL NARROWBAND FM RECEIVER INTEGRATED CIRCUIT |
| 文件： | 总68页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC13110A/D
The MC13110A/B and MC13111A/B integrates several of the functions
required for a cordless telephone into a single integrated circuit. This
significantly reduces component count, board space requirements, external
adjustments, and lowers overall costs. It is designed for use in both the
handset and the base.
UNIVERSAL
NARROWBAND FM RECEIVER
INTEGRATED CIRCUIT
• MC13110A and MC13111A: Fully Programmable in all Power Modes
• MC13110B and MC13111B: MPU Clk Out and Second Local Oscillator
are “Always On”. There is No Inactive Mode
• Dual Conversion FM Receiver
– Complete Dual Conversion Receiver – Antenna Input to Audio Out
52
1
80 MHz Maximum Carrier Frequency
– RSSI Output
FB SUFFIX
PLASTIC PACKAGE
CASE 848B
– Carrier Detect Output with Programmable Threshold
– Comparator for Data Recovery
– Operates with Either a Quad Coil or Ceramic Discriminator
• Compander
(QFP–52)
– Expander Includes Mute, Digital Volume Control, Speaker Driver,
Programmable Low Pass Filter, and Gain Block
– Compressor Includes Mute, Programmable Low Pass Filter, Limiter,
and Gain Block
• MC13110A/B only: Frequency Inversion Scrambler
– Function Controlled via MPU Interface
– Programmable Carrier Modulation Frequency
• Dual Universal Programmable PLL
48
1
FTA SUFFIX
PLASTIC PACKAGE
CASE 932
(LQFP–48)
ORDERING INFORMATION
Tested Operating
– Supports New 25 Channel U.S. Standard with No External Switches
– Universal Design for Domestic and Foreign Cordless Telephone
Standards
Temperature Range
Device
Package
– Digitally Controlled Via a Serial Interface Port
– Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit
Programmable Counter and 2nd LO with 12–Bit Counter
QFP–52
MC13110AFB
MC13110AFTA
LQFP–48
QFP–52
LQFP–48
– Transmit Section Contains Phase Detector and 14–Bit Counter
– MPU Clock Outputs Eliminates Need for MPU Crystal
• Low Battery Detect
– Provides Two Levels of Monitoring with Separate Outputs
– Separate, Adjustable Trip Points
• 2.7 to 5.5 V Operation (15 µA Current Consumption in Inactive Mode)
MC13110BFB
MC13110BFTA
T
A
= – 40° to +85°C
QFP–52
LQFP–48
QFP–52
LQFP–48
MC13111AFB
MC13111AFTA
MC13111BFB
MC13111BFTA
• AN1575: Refer to this Application Note for a List of the “Worldwide
Cordless Telephone Frequencies
Simplified Block Diagram
Limiting IF
Amplifier
R
In
MPU Clock Out
2nd LO
x
2nd
1st
Mixer
Detector
Mixer
RSSI
RSSI
R
PD In
x
Carrier Detect Out
1st LO
2nd LO
Scrambler
Expander
Data Out
Low Battery
Detect
R
Phase
µ
P Serial
Interface
Low Battery
Indicator
x
R
PD Out
PD Out
x
Detector
R
Out
x
T
Phase
x
T
x
Detector
SPI
In
Scrambler
Compressor
T
Out
x
T
x
NOTE:
=
MC13110A/B Only
This device contains 8262 active transistors.
This document contains information on a new product. Specifications and information herein
Motorola, Inc. 1997
Rev 0
are subject to change without notice.
MC13110A/B MC13111A/B
PIN CONNECTIONS
QFP–52
IF Amp/
Limiter
Detector
1st Mix
2nd Mix
2nd LO
40
41
42
26
25
24
23
22
21
20
19
18
17
16
15
14
LO In
1
RSSI
RSSI
LPF
1st LO
VCO
Scrambler
1st LO
LO Out
1
Det Out
LPF
AALPF
R
Adjust
Gain
V
Ctrl
R Audio In
x
x
cap
4.129 kHz
R
x
Speaker
Amp
43
44
45
Gnd Audio
SA Out
SA In
V
Audio
CC
DA In
In
Bypass
Mute
2nd LO
Speaker
Mute
SC Filter
Clock
6 b Prog
SC Clk Ctr
÷2
Mic Amp
T
x
Expander
Scrambler
Modulating Clock
÷40
46
47
48
49
50
51
52
E Out
Amp Out
C In
Vol
Control
T
Gain
T
x
x
ALC
4.129 kHz
LPF
Limiter
Adjust
Mute
E
cap
LPF
E In
C Cap
Compressor
Bypass
C Cap
Scr Out
T Out
x
14 b Prog
Ctr
VB
Ref
2
1st LO
25
V
ref
R
Ref
2
BD2 Out
DA Out
x
2nd LO
Low Battery
Detect
Reg 2.5 V
14 b Prog
÷
Ref
1
12 b Prog
Ref Ctr
Ref
1
÷
4
1
Data
Amp
÷
T
Ctr
x
µ
P Serial
VB
BD1 Out
Interface
2nd LO
10.240
R
Phase
T Phase
x
Carrier
Detect
x
Prog
Clk Ctr
Detect
Detect
NOTE:
LQFP–48
=
MC13110A/B Only
IF Amp/
Limiter
Detector
1st Mix
2nd Mix
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
Q Coil
LO In
1
RSSI
2nd LO
1st LO
VCO
Scrambler
LPF
1st LO
Gain
Det Out
LO Out
1
LPF
AALPF
R
R
Audio In
x
V
Ctrl
x
cap
4.129 kHz
Adjust
R
x
V
Audio
Gnd Audio
SA Out
SA In
Speaker
Amp
CC
DA In
In
Bypass
Mute
2nd LO
SC Filter
Clock
6 b Prog
SC Clk Ctr
Speaker
Mute
÷2
Mic Amp
T
x
Expander
Scrambler
÷40
Modulating Clock
Amp Out
C In
E Out
Vol
Control
T
Gain
T
Mute
x
x
ALC
4.129 kHz
LPF
Limiter
Adjust
E
cap
LPF
C Cap
E In
Scr Out
VB
Compressor
Bypass
C Cap
T
Out
x
14 b Prog
Ctr
VB
1st LO
25
V
V
Audio
ref
R
CC
BD Out
DA Out
2nd LO
x
Data
Amp
Reg 2.5 V
14 b Prog
Programmable
Low Battery
Detect
÷
12 b Prog
Ref Ctr
LO In
2
÷
4
÷1
T
Ctr
x
µ
P Serial
Interface
2nd LO
10.240
R
Phase
Detect
T Phase
x
x
Carrier
Detect
Prog
Clk Ctr
Detect
2
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
MAXIMUM RATINGS
Characteristic
Symbol
Value
–0.5 to +6.0
–65 to +150
70
Unit
Vdc
°C
Power Supply Voltage
Junction Temperature
V
CC
T
J
Maximum Power Dissipation, T = 25°C
P
D
mW
A
NOTES: 1. Devices should not be operated at these limits. The “Recommended Operating Conditions”
provide for actual device operation.
2. ESD data available upon request.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
2.7
–40
–
Typ
3.6
–
Max
5.5
85
Unit
Vdc
°C
V
Supply Voltage
V
CC
Operating Ambient Temperature
Input Voltage Low (Data, Clk, EN)
Input Voltage High (Data, Clk, EN)
T
A
V
IL
–
0.3
–
V
IH
PLL V
ref
–
–
V
0.3
Bandgap Reference Voltage
V
B
–
1.5
–
V
NOTE: 3. All limits are not necessarily functional concurrently.
DC ELECTRICAL CHARACTERISTICS (V
Test Circuit Figure 1.)
= 3.6 V, T = 25°C, unless otherwise specified, IP3 = 0;
CC
A
Characteristic
Symbol
Figure
Min
Typ
Max
Unit
Static Current
1
Active Mode
Receive Mode
Standby Mode
Inactive Mode [Note 4]
ACT I
5.5
3.1
–
8.5
4.1
465
15
10.5
5.3
560
30
mA
mA
µA
CC
R I
x CC
STD I
CC
INACT I
–
µA
CC
Current Increase When IP3 = 1
(Active and Receive Modes)
I
1
–
1.4
1.8
mA
IP3
NOTE: 4. MC13110B/MC13111B versions have no inactive mode.
3
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
FM RECEIVER (f
RF
= 46.77 MHz [USA Ch 21], f
dev
= ±3.0 kHz, f
= 1.0 kHz, V = 1.2 V)
cap ctrl
mod
Input Sensitivity (for 12 dB SINAD at Det Out
Using C–Message Weighting Filter)
68, 69
Mix
In /In
1
Det Out
V
SIN
µVrms
dBm
1
2
–
–
2.2
–100
–
–
50 Ω Termination, Generator Referred
Single–Ended, Matched Input, Generator
Referred
–
–
0.4
–115
–
–
Differential, Matched Input, Generator Referred
–
–
0.4
–115
–
–
First and Second Mixer Voltage Gain Total
1
–
1
1
1
–
Mix
In or In
1
Mix Out MX
24
29
–
dB
dB
1
2
gainT
(V = 1.0 mVrms, with CF and CF Load)
in
1
2
2
2
2
2
2
2
Isolation of First Mixer Output and Second Mixer
Input (V = 1.0 mVrms, with CFI Removed)
Mix
In or In
1
Mix In
2
Mix–Iso
THD
–
60
–
1
in
Total Harmonic Distortion (V = 3.16 mVrms)
Mix
In or In
1
Det Out
Det Out
Det Out
Det Out
–
1.4
112
48
2.0
150
–
%
in
1
Recovered Audio (V = 3.16 mVrms)
in
Mix
In or In
1
AFO
80
30
–
mVrms
dB
1
AM Rejection Ratio (V = 3.16 mVrms, 30% AM,
in
@ 1.0 kHz)
Mix
In or In
1
AMR
SNR
1
Signal to Noise Ratio (V = 3.16 mVrms,
in
No Modulation)
Mix
In or In
1
48
–
dB
1
FIRST MIXER (No Modulation, f = USA Ch21, 46.77 MHz, 50 Ω Termination at Inputs)
in
Input Impedance
Single–Ended
–
Mix
In or In
1
kΩ
pF
1
16
16
R
C
–
–
1.6
3.7
–
–
2
PS1
PS1
Differential
Mix
1
In /In
R
C
–
–
1.6
1.8
–
–
1
2
PD1
PD1
Output Impedance
14
–
Mix Out
R
C
Out
Out
–
–
300
3.7
–
–
Ω
pF
1
P1
P1
Voltage Conversion Gain
(V = 1.0 mVrms, with CF Filter as Load)
in
17, 18
Mix
In or In
1
Mix Out MX
–
12
–
dB
1
1
gain1
1
2
2
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set to 0
Mix
In or In
1
Mix Out
V
O
Mix
mVrms
dBm
1
1
1
19, 21
20, 21
1 dB
–
–
20
–21
–
–
IP3 Bit Set to 1
–
–
56
–12
–
–
Third Order Intercept (Input Referred) [Note 5]
IP3 Bit Set to 0
Mix
In or In
1
Mix Out
TOI
mVrms
dBm
1
1
mix1
19, 21
20, 21
22
–
–
64
–11
–
–
2
IP3 Bit Set to 1
–
–
178
–2.0
–
–
–3.0 dB IF Bandwidth
Mix In
Mix Out Mix BW
–
13
–
MHz
1
1
1
1
or In
2
NOTE: 5. Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
4
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
SECOND MIXER (No Modulation, f = 10.7 MHz, 50 Ω Termination at Inputs)
in
Input Impedance
24
Mix In
2
Mix In
R
C
In
In
–
–
2.8
3.6
–
–
kΩ
pF
2
P2
P2
Output Impedance
Voltage Conversion Gain
24
–
Mix Out
R
C
Out
Out
–
–
1.5
6.1
–
–
kΩ
pF
2
P2
P2
26, 27
Mix In
Mix Out MX
–
20
–
dB
2
2
gain2
(V = 1.0 mVrms, with CF Filter as Load)
in
2
1.0 dB Voltage Compression Level (Input Referred)
IP3 Bit Set 0
Mix In
Mix Out
V
O
2
1 dB
mVrms
dBm
2
2
28, 30
29, 30
Mix
–
–
32
–17
–
–
IP3 Bit Set 1
–
–
45
–14
–
–
Third Order Intercept (Input Referred) [Note 6]
IP3 Bit Set 0
Mix In
Mix Out
TOI
mix2
mVrms
dBm
2
2
28, 30
29, 30
31
–
–
136
–4.3
–
–
IP3 Bit Set 1
–
–
158
–3.0
–
–
–3.0 dB IF Bandwidth
Mix In
Mix Out Mix BW
–
2.5
–
MHz
2
2
2
LIMITER/DEMODULATOR (f = 455 kHz, f
= ±3.0 kHz, f
mod
= 1.0 kHz)
Lim In
in
dev
Input Impedance
49
Lim In
R
C
–
–
1.5
16
–
–
kΩ
pF
PLim
PLim
Detector Output Impedance
IF –3.0 dB Limiting Sensitivity
Demodulator Bandwidth
–
1
–
–
Det Out
Det Out
Det Out
R
–
–
–
1.1
71
20
–
100
–
kΩ
µVrms
kHz
O
Lim In
Lim In
IF Sens
BW
RSSI/CARRIER DETECT (No Modulation)
RSSI Output Dynamic Range
56
56
Mix In
RSSI
RSSI
RSSI
–
–
80
–
–
dB
1
DC Voltage Range
Mix In
DC RSSI
0.2 to
1.5
Vdc
1
Carrier Detect Threshold
CD Threshold Adjust = (10100)
(Threshold Relative to Mix In Level)
57
Mix In
1
CD Out
V
–
–
15
–
µVrms
T
1
Hysteresis, CD = (10100)
(Threshold Relative to Mix In Level)
57
1
Mix1 In
RSSI
RSSI
–
CD Out
CD Out
CD Out
–
Hys
2.0
3.6
–
–
dB
V
1
Output High Voltage
CD = (00000), RSSI = 0.2 V
V
OH
V
–
CC
0.1
Output Low Voltage
CD = (11111), RSSI = 0.9 V
1
V
OL
–
–
–
0.02
0.4
–
V
Carrier Detect Threshold Adjustment Range
(Programmable through MPU Interface)
126
126
V
–20 to
11
dB
–
T
Range
Carrier Detect Threshold – Number of
Programmable Levels
–
–
V
Tn
32
–
NOTE: 6. Third order intercept calculated for input levels 10 dB below 1.0 dB compression point.
5
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
R
AUDIO PATH (f = 1.0 kHz, Active Mode, scrambler bypassed)
in
x
Absolute Gain (V = –20 dBV)
in
1, 72
R Audio In
x
SA Out
E Out
G
–4.0
0
4.0
dB
dB
Gain Tracking
1, 76
E In
G
t
(Referenced to E Out for V = –20 dBV)
in
V
in
V
in
= –30 dBV
= –40 dBV
–21
–42
–20
–40
–19
–38
Total Harmonic Distortion (V = –20 dBV)
in
1, 76
76
R Audio In
SA Out
–
THD
–
–
–
0.7
–11.5
0
1.0
–
%
x
Maximum Input Voltage (V
= 2.7 V)
R Audio In
x
dBV
dBV
CC
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
output voltage)
1
E In
E Out
V
Omax
–2.0
–
Input Impedance
–
–
–
1
1
1
R Audio In
x
–
Z
–
–
600
7.5
–
–
kΩ
ms
ms
dB
in
E In
Attack Time
E In
E Out
E Out
E Out
E Out
Scr Out
t
a
–
3.0
13.5
–90
–
E
= 0.5 µF, R = 40 k (See Appendix B)
filt
cap
Release Time
= 0.5 µF, R = 40 k (See Appendix B)
E In
C In
t
–
–
–
r
E
cap
filt
Compressor to Expander Crosstalk
= –10 dBV, V = AC Gnd
C
–70
–60
3.979
T
V
in
(E In)
R Muting (∆ Gain)
R Audio In
x
M
e
–
–84
dB
x
in
V
= –20 dBV, R Gain Adj = (01111)
x
R High Frequency Corner
R Audio In
x
R
f
3.779
3.879
0.4
kHz
x
x ch
R Path, V R Audio In = –20 dBV
x
x
Low Pass Filter Passband Ripple (V = –20 dBV)
in
1, 73
125
R Audio In
x
Scr Out
Scr Out
Ripple
–
–
0.6
–
dB
dB
R Gain Adjust Range (Programmable through
x
MPU Interface)
R Audio In
x
R
–9.0 to
10
x
Range
R Gain Adjust Steps – Number of
x
125
70
R Audio In
Scr Out
R n
x
–
20
–
dB
x
Programmable Levels
Audio Path Noise, C–Message Weighting
(Input AC–Grounded)
R Audio In
x
Scr Out
E Out
SA Out
EN
–
–
–85
<–95
<–95
–
–
dBV
Volume Control Adjust Range
123
123
E In
E In
E Out
E Out
V
–
–
–14 to
16
–
–
dB
–
cnRange
Volume Control – Number of Programmable
Levels
V
cn
16
SPEAKER AMP/SP MUTE (Active Mode)
Maximum Output Swing
1, 79
SA In
SA In
SA Out
SA Out
V
Vpp
dB
Omax
R
L
R
L
R
L
= No Load, V = 3.4 Vpp
2.8
2.0
–
3.2
2.6
3.4
–
–
–
in
= 130 Ω, V = 2.8 Vpp
in
= 620 Ω, V = 4.0 Vpp
in
Speaker Amp Muting
1
M
sp
–
–92
–60
V
in
= –20 dBV, R = 130 Ω
L
6
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
DATA AMP COMPARATOR
Figure
Symbol
Min
Typ
Max
Unit
Hysteresis
1
–
DA In
DA In
DA Out
DA Out
Hys
30
–
42
50
–
mV
V
Threshold Voltage
V
T
V
–
CC
0.7
Input Impedance
1
–
1
–
–
DA In
DA Out
DA Out
Z
200
–
250
100
3.6
280
–
kΩ
kΩ
V
I
Output Impedance
Output High Voltage
Z
O
DA In
V
OH
V
CC
0.1
–
–
V
= V
– 1.0 V, I
= 0 mA
= 0 mA
in
Output Low Voltage
= V – 0.4 V, I
OL
CC
OH
1
–
DA In
DA In
DA Out
DA Out
V
OL
–
0.1
10
0.4
–
V
V
in
CC
Maximum Frequency
F
–
kHz
max
MIC AMP (f = 1.0 kHz, External resistors set to gain of 1, Active Mode)
in
Open Loop Gain
–
–
–
T In
Amp Out
Amp Out
Amp Out
AVOL
GBW
–
–
–
100,000
100
–
–
–
V/V
kHz
Vpp
x
Gain Bandwidth
T In
x
Maximum Output Swing (R = 10 kΩ)
T In
x
V
Omax
3.2
L
T
x
AUDIO PATH (f = 1.0 kHz, T Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
in
x
Absolute Gain (V = –10 dBV)
in
1, 83
T In
T Out
G
–4.0
0
4.0
dB
dB
x
x
Gain Tracking
1, 87
T In
x
T Out
x
G
t
(Referenced to T Out for V = –10 dBV)
x
in
V
in
V
in
= –30 dBV
= –40 dBV
–11
–17
–10
–15
–9.0
–13
Total Harmonic Distortion (V = –10 dBV)
in
1, 87
1
T In
T Out
THD
–
0.8
0
1.8
–
%
x
x
Maximum Output Voltage (Increase input voltage
until output voltage THD = 5.0%, then measure
T In
x
T Out
x
V
Omax
–2.0
dBV
output voltage. T Gain Adjust = 8 dB)
x
Input Impedance
–
–
–
C In
Z
–
–
10
–
–
kΩ
in
Attack Time (C
Appendix B))
= 0.5 µF, R = 40 k (See
filt
C In
T Out
x
t
a
3.0
ms
cap
Release Time (C
Appendix B))
= 0.5 µF, R = 40 k (See
filt
–
1
1
C In
E In
T Out
t
r
–
–
–
13.5
–60
–88
–
ms
dB
cap
x
Expander to Compressor Crosstalk (V = –20 dBV,
in
Speaker Amp No Load, V
T Out
x
C
–40
–60
T
= AC Gnd)
(C In)
T Muting (V – 10 dBV)
x in
T In
x
T Out
x
M
c
dB
ALC Output Level (ALC enabled)
1, 87,
90
T In
x
T Out
x
ALC
out
dBV
V
in
V
in
= –10 dBV
= –2.5 dBV
–15
–13
–13
–11
–8.0
–6.0
ALC Slope (ALC enabled)
1
T In
x
T Out
Slope
DR
0.1
0.25
0.4
dB/dB
x
V
in
V
in
= –10 dBv
= –2.5 dBv
ALC Input Dynamic Range
–
1
1
C In
T Out
x
–
–16 to
–2.5
–
–
dBV
dBV
kHz
Limiter Output Level (V = –2.5 dBV,
in
Limiter enabled)
T In
x
T Out
x
V
lim
–10
3.6
–8.0
T High Frequency Corner [Note 7]
T In
x
T Out
x
T f
x c
3.7
3.8
x
(VT In = –10 dBV, Mic Amp = Unity Gain)
x
NOTE: 7. The filter specification is based on a 10.24 MHz 2nd LO, and a switched–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
7
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
Figure
Symbol
Min
Typ
Max
Unit
T
x
AUDIO PATH (f = 1.0 kHz, T Gain Adj = (01111); ALC, Limiter, and Mutes Disabled; Active Mode, scrambler bypassed)
in
x
Low Pass Filter Passband Ripple (V = –10 dBV)
in
1, 84
T In
x
T Out
Ripple
–
–
–
0.7
1.2
dB
dB
dB
x
Maximum Compressor Gain (V = –70 dBV)
in
–
C In
C In
T Out
x
AV
23
–
max
T Gain Adjust Range (Programmable through
x
MPU Interface)
125
T Out
x
T Range
x
–9.0 to
10
–
T Gain Adjust Steps – Number of Programmable
x
Levels
125
C In
T Out
x
T n
x
–
20
–
–
R
AND T SCRAMBLER (2nd LO = 10.24 MHz, T Gain Adj = (01111), R Gain Adj = (01111), Volume Control = (0 dB Default Levels),
x x x
x
SCF Clock Divider = 31. Total is divide by 62 for SCF clock frequency of 165.16 kHz)
R High Frequency Corner (Note 8)
–
–
R Audio In
Scr Out
R f
x ch
3.55
3.65
3.75
kHz
kHz
x
x
R Path, f = 479 Hz, V R Audio In = –20 dBV
x
x
T High Frequency Corner (Note 8)
x
T In
x
T Out
x
T f
x ch
3.829
3.879
3.929
T Path, f = 300 Hz, V T In = –10 dBV,
x
x
Mic Amp = Unity Gain
Absolute Gain
AV
dB
dB
–
–
R Audio In
x
E Out
T Out
x
–4.0
–4.0
0.4
–1.0
4.0
4.0
R : V = –20 dBV
x
in
T In
x
T : V = –10 dBV, Limiter disabled
in
x
Pass Band Ripple
R + T Path – 1.0 µF from T Out to
–
C In
E Out
Ripple
–
1.9
2.5
x
x
x
R Audio In, f = low corner frequency to
x
in
high corner frequency
Scrambler Modulation Frequency
f
4.119
4.129
4.139
kHz
ms
mod
–
–
R Audio In
x
E Out
T Out
x
R : 100 mV (–20 dBV)
x
T : 316 mV (–10 dBV)
x
C In
Group Delay
–
–
–
C In
C In
C In
E Out
E Out
E Out
GD
GD
–
–
–
1.0
4.0
–
–
–
R + T Path – 1.0 µF from T Out to
x
x
x
R Audio In, f = 1.0 kHz
in
in
frequency
x
f
= low corner frequency to high corner
Carrier Breakthrough
R + T Path – 1.0 µF from T Out to
CBT
BBT
–60
dB
dB
x
x
x
R Audio In
x
Baseband Breakthrough
–
C In
E Out
–
–50
–
R + T Path – 1.0 µF from T Out to
x
x
x
R Audio In,
x
f
= 1.0 kHz, f
= 3.192 kHz
in
meas
LOW BATTERY DETECT
Average Threshold
Voltage Before Electronic Adjustment
(V _Adj = (0111))
ref
1, 131
1
Ref
Ref
BD Out
BD Out
2
VT
i
1.38
1.48
1.5
1.58
V
V
1
2
1
Average Threshold
Voltage After Electronic Adjustment
(V _Adj = (adjusted value))
ref
Ref
Ref
BD Out
VT
f
1.475
1.525
1
2
1
BD Out
2
Hysteresis
–
1
1
Ref
Ref
BD Out
Hys
–
4.0
–
–
50
–
mV
nA
V
1
2
1
BD Out
2
Input Current (V = 1.0 and 2.0 V)
in
–
Ref
Ref
I
in
–50
1
2
Output High Voltage (V = 2.0 V)
in
Ref
Ref
BD Out
V
OH
V
–
3.6
1
2
1
CC
0.1
BD Out
2
NOTE: 8. The filter specification is based on a 10.24 MHz 2nd LO, and a switch–capacitor (SC) filter counter divider ratio of 31. If other 2nd LO frequencies
and/or SC filter counter divider ratios are used, the filter corner frequency will be proportional to the resulting SC filter clock frequency.
8
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
ELECTRICAL CHARACTERISTICS (continued) (V
Test Circuit Figure 1.)
= 3.6 V, V = 1.5 V, T = 25°C, Active or R Mode, unless otherwise specified;
CC
B
A
x
Input
Pin
Measure
Pin
Characteristic
LOW BATTERY DETECT
Figure
Symbol
Min
Typ
Max
Unit
Output Low Voltage (V = 1.0 V)
in
1
Ref
Ref
BD Out
V
OL
–
0.2
0.4
V
1
2
1
BD Out
2
BATTERY DETECT INTERNAL THRESHOLD
After Electronic Adjustment of V Voltage
B
1, 128
V
CC
Audio
BD Out
V
2
BD Select = (111)
BD Select = (110)
BD Select = (101)
BD Select = (100)
BD Select = (011)
BD Select = (010)
BD Select = (001)
IBS
IBS
IBS
IBS
IBS
IBS
IBS
3.381
3.298
3.217
3.134
2.970
2.886
2.802
3.455
3.370
3.287
3.202
3.034
2.948
2.862
3.529
3.442
3.357
3.270
3.098
3.010
2.922
7
6
5
4
3
2
1
PLL PHASE DETECTOR
Output Source Current
–
–
–
R
T PD
x
PD
I
–
–
1.0
1.0
–
–
mA
mA
x
OH
(V
PD
= Gnd + 0.5 V to PLL V
– 0.5 V)
ref
Output Sink Current
(V = Gnd + 0.5 V to PLL V – 0.5 V)
–
R
T PD
x
PD
I
OL
x
PD ref
PLL LOOP CHARACTERISTICS
Maximum 2nd LO Frequency
(No Crystal)
–
–
–
LO In
2
–
f
f
–
–
–
12
12
80
–
–
–
MHz
MHz
MHz
2ext
Maximum 2nd LO Frequency
(With Crystal)
–
–
LO In
2
2ext
LO Out
2
Maximum T VCO (Input Frequency),
T
x
VCO
f
txmax
x
V
in
= 200 mVpp
PLL VOLTAGE REGULATOR
Regulated Output Level (I = 0 mA, after V
L
1
–
PLL V
V
O
2.4
2.5
2.6
V
ref
ref
Adjustment)
Line Regulation (I = 0 mA, V
= 3.0 to 5.5 V)
1
1
V
Audio
PLL V
PLL V
V
Line
–
11.8
–1.4
40
–
mV
mV
L
CC
CC
ref
Reg
Load Regulation (I = 1.0 mA)
V
Audio
V
–20
L
CC
ref
Reg
Load
MICROPROCESSOR SERIAL INTERFACE
Input Current Low (V = 0.3 V, Standby Mode)
1
1
–
–
–
–
Data,
Clk, EN
I
–5.0
0.4
1.6
1.0
2.0
8.0
–
5.0
–
µA
µA
V
in
IL
Input Current High (V = 3.3 V, Standby Mode)
in
–
–
Data,
Clk, EN
I
IH
–
–
–
–
Hysteresis Voltage
Data,
Clk, EN
V
hys
Maximum Clock Frequency
Input Capacitance
Data,
EN, Clk
–
–
–
–
MHz
pF
Data,
Clk, EN
C
–
in
EN to Clk Setup Time
Data to Clk Setup Time
Hold Time
106
105
105
106
–
–
–
–
–
–
–
EN, Clk
Data, Clk
Data, Clk
EN, Clk
EN, Clk
–
t
–
–
–
–
–
–
200
100
90
–
–
–
–
–
–
ns
ns
ns
ns
ns
µs
suEC
t
suDC
t
h
Recovery Time
t
90
rec
Input Pulse Width
t
w
100
100
MPU Interface Power–Up Delay (90% of PLL V
to Data,Clk, EN)
108
t
puMPU
ref
9
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
C o i l
O u t
C D
Q
L i m O u t
C l k O u t
C l k
C C
R F
V
2
L i m C
L i m C
L i m I n
E N
1
D a t a
x
V C T O
G n d P L L
S G n d R F
2
x
I n M i x
P D T
2
r e f
O u t M i x
V
P L L
x
G n d R F
P D R
1
a g
V
O u t M i x
2
1
2
I n M i x
O u t L O
1
1
2
I n
M i x
I n L O
10
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION
Pin
LQFP–48
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
48
1
1
2
LO In
These pins form the PLL reference oscillator when
connected to an external parallel–resonant crystal
(10.24 MHz typical). The reference oscillator is
2
PLL
LO Out
2
V
ref
also the second Local Oscillator (LO ) for the RF
2
receiver. “LO In” may also serve as an input for
2
PLL
100
1
2
PLL
V
an externally generated reference signal which is
typically ac–coupled.
ref
V
ref
LO
In
When the IC is set to the inactive mode, LO In is
2
100
2
internally pulled low to disable the oscillator. The
LO
Out
2
input capacitance to ground at each pin (LO In/
2
LO Out) is 3.0 pF.
2
2
3
V
ag
V
is the internal reference voltage for the
ag
V
CC
Audio
PLL
switched capacitor filter section. This pin must be
decoupled with a 0.1 µF capacitor.
V
ref
3
V
ag
30 k
3
5
4
4
6
5
R PD
x
This pin is a tri–state voltage output of the R and
x
PLL
PLL
(Output)
T Phase Detector. It is either “high”, “low”, or “high
x
V
ref
V
ref
impedance,” depending on the phase difference of
the phase detector input signals. During lock, very
narrow pulses with a frequency equal to the
4, 6
15
reference frequency are present. This pin drives
the external R and T PLL loop filters. R and T
x
T PD
x
(Output)
R
T
PD,
PD
x
x
x
x
x
PD outputs can sink or source 1.0 mA.
PLL V
ref
PLL V is a PLL voltage regulator output pin. An
ref
internal voltage regulator provides a stable power
V
CC
Audio
supply voltage for the R and T PLL’s and can
x
x
also be used as a regulated supply voltage for
other IC’s. It can source up to 1.0 mA externally.
Proper supply filtering is a must on this pin. PLL
5
V
is pulled up to V audio for the standby and
ref
inactive modes (Note 1).
CC
PLL V
ref
132 k
6
7
7
8
Gnd PLL
VCO
Ground pin for digital PLL section of IC.
T
T VCO is the transmit divide counter input which
x
x
(Input)
is driven by an ac–coupled external transmit loop
VCO. The minimum signal level is 200 mVpp @
60.0 MHz. This pin also functions as the test mode
input for the counter tests.
PLL
V
PLL
ref
V
ref
1.0 k
8
TX VCO
11
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
8
9
10
9
10
11
Data
EN
Clk
Microprocessor serial interface input pins are for
programming various counters and control
functions. The switching thresholds are referenced
V
CC
Audio
PLL
V
ref
(Input)
to PLL V and Gnd PLL. The inputs operate up to
ref
240
1.0
9, 10, 11
V
CC
. These pins have 1.0 µA internal pull–down
currents.
Data, EN, Clk
µA
11
12
Clk Out
(Output)
The microprocessor clock output is derived from
the 2nd LO crystal oscillator and a programmable
divider with divide ratios of 2 to 312.5. It can be
used to drive a microprocessor and thereby
reduce the number of crystals required in the
system design. The driver has an internal resistor
in series with the output which can be combined
with an external capacitor to form a low pass filter
to reduce radiated noise on the PCB. This output
also functions as the output for the counter test
modes.
V
CC
Audio
V
CC
Audio
12
Clk Out
1.0 k
1) For the MC13110A/B and MC13111A/B the Clk
Out can be disabled via the MPU interface.
2) For the MC13110B and MC13111B this output is
always active (on) (Note 2).
12
13
CD Out
(I/O)
Dual function pin;
V
CC
Audio
PLL
1) Carrier detect output (open collector with
external 100 kΩ pull–up resistor.
V
ref
240
13
2) Hardware interrupt input which can be used to
“wake–up” from the Inactive Mode.
Hardware
Interrupt
CD Out
CD
Comparator
–
14
16
15
BD Out
Low battery detect output #1 is an open collector
with external pull–up resistor.
1
V
Audio
CC
14, 16
14
13
BD Out
2
(Output)
Low battery detect output #2 is an open collector
with external pull–up resistor.
BD Out
1
BD Out
2
DA Out
(Output)
Data amplifier output (open collector with internal
100 kΩ pull–up resistor).
V
CC
V
CC
Audio
Audio
100 k
15
DA Out
15
17
T Out
x
(Output)
T Out is the T path audio output. Internally this
x x
V
CC
pin has a low–pass filter circuitry with –3 dB
Audio
bandwidth of 4.0 kHz. T gain and mute are
x
programmable through the MPU interface. This pin
is sensitive to load capacitance.
17
T
Out
x
V
B
12
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
16
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
18
C Cap
C Cap is the compressor rectifier filter capacitor
pin. It is recommended that an external filter
audio be used. A practical
capacitor range is 0.1 to 1.0 µF. 0.47 µF is the
V
V
CC
Audio
CC
Audio
capacitor to V
CC
40 k
18
recommended value.
C Cap
17
19
C In
(Input)
C In is the compressor input. This pin is internally
biased and has an input impedance of 12.5 k. C In
must be ac–coupled.
V
Audio
CC
12.5 k
19
C In
V
B
18
19
20
21
Amp Out
(Output)
Microphone amplifier output. The gain is set with
external resistors. The feedback resistor should be
less than 200 kΩ.
V
Audio
V
CC
CC
Audio
21
In
20
T In
x
(Input)
T In is the T path input to the microphone
x x
amplifier (Mic Amp). An external resistor is
T
x
Amp Out
connected to this pin to set the Mic Amp gain and
input impedance. T In must be ac–coupled, too.
x
V
B
V
20
22
DA In
(Input)
The data amplifier input (DA In) resistance is
250 kΩ and must be ac–coupled. Hysteresis is
internally provided.
CC
Audio
V
Audio
CC
250 k
250 k
22
DA In
21
22
23
24
V
Audio
V
audio is the supply for the audio section. It is
CC
CC
necessary to adequately filter this pin.
R Audio In
x
The R audio input resistance is 600 kΩ and must
be ac–coupled.
x
V
CC
Audio
(Input)
600 k
24
Audio In
R
x
V
B
23
25
Det Out
(Output)
Det Out is the audio output from the FM detector.
This pin is dc–coupled from the FM detector and
has an output impedance of 1100 Ω.
V
CC
V
Audio
CC
RF
240
25
Det Out
30 µA
13
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
30
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
26
RSSI
RSSI is the receive signal strength indicator. This
pin must be filtered through a capacitor to ground.
The capacitance value range should be 0.01 to
0.1 µF. This is also the input to the Carrier Detect
comparator. An external R to ground shifts the
RSSI voltage.
V
CC
RF
V
V
CC
RF
CC
Audio
26
RSSI
186 k
24
27
Q Coil
A quad coil or ceramic discriminator connects this
pin as part of the FM demodulator circuit.
V
CC
RF
V
CC
RF
DC–couple this pin to V
RF through the quad
CC
coil or the external resistor.
27
Q Coil
26
25
29
28
V
RF
V
supply for RF receiver section (1st LO, mixer,
CC
CC
limiter, demodulator). Proper supply filtering is
needed on this pin too.
Lim Out
A quad coil or ceramic discriminator are connected
to these pins as part of the FM demodulator circuit.
A coupling capacitor connects this pin to the quad
coil or ceramic discriminator as part of the FM
demodulator circuit. This pin can drive coupling
capacitors up to 47 pF with no deterioration in
performance.
V
V
V
CC CC CC
RF RF RF
V
CC
RF
53.5 k
31
28
Lim C
1
32
27
28
30
31
Lim C
Lim C
Lim Out
IF amplifier/limiter capacitor pins. These
decoupling capacitors should be 0.1 µF. They
determine the IF limiter gain and low frequency
bandwidth.
2
1
Lim In
30
1.5 k
52 k
Lim C
2
29
–
32
33
34
Lim In
(Input)
Signal input for IF amplifier/limiter. Signals should
be ac–coupled to this pin. The input impedance is
1.5 kΩ at 455 kHz.
SGnd RF
This pin is not connected internally but should be
grounded to reduce potential coupling between
pins.
31
Mix In
2
(Input)
Mix In is the second mixer input. Signals are to be
2
ac–coupled to this pin, which is biased internally to
V
CC
RF
V
CC
V
RF. The input impedance is
CC
RF
2.8 kΩ at 455 kHz. The input impedance can be
3.0 k
reduced by connecting an external resistor to
34
Mix In
V
CC
RF.
2
14
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
32
35
Mix Out
2
(Output)
Mix Out is the second mixer output. The second
2
V
CC
RF
V
mixer has a 3 dB bandwidth of 2.5 MHz and an
output impedance of 1.5 kΩ. The output current
drive is 50 µA.
CC
RF
1.2 k
35
Mix Out
2
33
34
36
37
Gnd RF
Ground pin for RF section of the IC.
Mix Out
1
(Output)
The first mixer has a 3 dB IF bandwidth of 13 MHz
and an output impedance of 300 Ω. The output
current drive is 300 µA and can be programmed
for 1.0 mA.
V
CC
RF
V
CC
RF
200
37
Mix Out
1
35
36
38
39
Mix In
1 2
Signals should be ac–coupled to this pin, which is
V
ref
(Input)
biased internally to V
and differential input impedance are about 1.6 and
– 1.6 V. The single–ended
CC
20 k
V
RF
V
1.8 kΩ at 46 MHz, respectively.
CC
CC
RF
950
950
38, 39
Mix In
1
1
(Input)
Mix In ,
1
1
2
1
Mix In
37
38
40
41
LO In
Tank Elements, an internal varactor and capacitor
matrix for 1st LO multivibrator oscillator are
connected to these pins. The oscillator is useable
up to 80 MHz.
1
LO Out
1
40
41
LO
Out
LO
In
1
1
39
42
V
cap
Ctrl
V
Ctrl is the 1st LO varactor control pin. The
cap
voltage at this pin is referenced to Gnd Audio and
varies the capacitance between LO In and
V
RF
CC
1
LO Out. An increase in voltage will decrease
2
capacitance.
55 k
42
V
cap
Ctrl
40
41
43
44
Gnd Audio
Ground for audio section of the IC.
SA Out
(Output)
The speaker amplifier gain is set with an external
feedback resistor. It should be less than 200 kΩ.
The speaker amplifier can be muted through the
MPU interface.
V
V
CC
Audio
CC
Audio
45
SA In
44
SA Out
42
45
SA In
(Input)
An external resistor is connected to the speaker
amplifier input (SA In). This will set the gain and
input impedance and must be ac–coupled.
V
B
15
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PIN FUNCTION DESCRIPTION (continued)
Pin
LQFP–48
43
Symbol/
Type
QFP–52
Equivalent Internal Circuit (52 Pin QFP)
Description
V
46
E Out
(Output)
The output level of the expander output is
determined by the volume control. Volume control
is programmable through the MPU interface.
CC
Audio
46
E Out
V
B
44
47
E Cap
E Cap is the expander rectifier filter capacitor pin.
V
V
Audio
CC
Audio
CC
Connect an external filter capacitor between V
CC
audio and E Cap. The recommended capacitance
range is 0.1 to 1.0 µF. 0.47 µF is the suggested
value.
40 k
47
E Cap
V
Audio
45
48
E In
(Input)
The expander input pin is internally biased and has
input impedance of 30 kΩ.
CC
30 k
48
E In
V
B
V
CC
46
49
Scr Out
(Output)
Scr Out is the R audio output. An internal low
x
pass filter has a –3 dB bandwidth of 4.0 kHz.
Audio
49
Scr Out
V
B
V
Audio
–
–
50
51
52
Ref
2
Reference voltage input for Low Battery Detect #2.
Reference voltage input for Low Battery Detect #1.
CC
50, 51
Ref , Ref
1
Ref
2
1
V
47
V
B
V is the internal half supply analog ground
B
reference. This pin must be filtered with a
CC
Audio
V
CC
Audio
capacitor to ground. A typical capacitor range of
0.5 to 10 µF is desired to reduce crosstalk and
noise. It is important to keep this capacitor value
240
52
V
equal to the PLL V capacitor due to logic timing
ref
B
(Note 9).
NOTE: 9. A capacitor range of 0.5 to 10 µF is recommended. The capacitor value should be the same used on the V pin (Pin 52). An additional high
B
quality parallel capacitor of 0.01 µF is essential to filter out spikes originating from the PLL logic circuitry.
16
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
DEVICE DESCRIPTION AND APPLICATION INFORMATION
The following text, graphics, tables and schematics are
battery detect output, and vice versa for V
Audio set to a
CC
low level. For the 52 pin package option, the Ref 1 and Ref 2
pins need to be tied to V when used in the programmable
provided to the user as a source of valuable technical
information about the Universal Cordless Telephone IC. This
information originates from thorough evaluation of the device
performance for the US and French applications. This data
was obtained by using units from typical wafer lots. It is
important to note that the forgoing data and information was
from a limited number of units. By no means is the user to
assume that the data following is a guaranteed parametric.
Only the minimum and maximum limits identified in the
electrical characteristics tables found earlier in this spec are
guaranteed.
CC
mode. It is essential to keep the external reference pins
above Gnd to prevent any possible power–on reset to be
activated.
When considering the non–programmable mode (bits set
to <000>) for the 52 pin package, the Ref 1 and Ref 2 pins
become the comparators reference. An internal switch is
activated when the non–programmable mode is chosen
connecting Ref 1 and Ref 2. Here, two external precision
resistor dividers are used to set independent thresholds for
two battery detect hysteresis comparators. The voltages on
Ref 1 and Ref 2 are again compared to the internally
generated 1.5 V reference voltage (VB).
The Low Battery Detect threshold tolerance can be
improved by adjusting a trim–pot in the external resistor
divider (user designed). The initial tolerance of the internal
reference voltage (VB) is ±6.0%. Alternately, the tolerance of
the internal reference voltage can be improved to ±1.5%
through MPU serial interface programming (refer to the Serial
Interface section, Figure 131). The internal reference can be
measured directly at the “VB” pin. During final test of the
telephone, the VB internal reference voltage is measured.
Then, the internal reference voltage value is adjusted
electronically through the MPU serial interface to achieve the
desired accuracy level. The voltage reference register value
should be stored in ROM during final test so that it can be
reloaded each time the combo IC is powered up. The Low
Battery Detect outputs are open collector. The battery detect
levels will depend on the accuracy of the VB voltage. Figure
12 indicates that the VB voltage is fairly flat over temperature.
General Circuit Description
The MC13110A/B and MC13111A/B are a low power dual
conversion narrowband FM receiver designed for
applications up to 80 MHz carrier frequency. This device is
primarily designated to be used for the 49 MHz cordless
phone (CT–0), but has other applications such as low data
rate narrowband data links and as a backend device for 900
MHz systems where baseband analog processing is
required. This device contains a first and second mixer,
limiter, demodulator, extended range receive signal strength
(RSSI), receive and transmit baseband processing, dual
programmable PLL, low battery detect, and serial interface
for microprocessor control. The FM receiver can also be
used with either a quadrature coil or ceramic resonator.
Refer to the Pin Function Description table for the simplified
internal circuit schematic and description of this device.
DC Current and Battery Detect
Figures 3 through 6 are the current consumption for
Inactive, Standby, Receive, and Active modes versus supply
voltages. Figures 7 and 8 show the typical behavior of current
consumption in relation to temperature. The relationship of
additional current draw due to IP3 bit set to <1> and supply
voltage are shown in Figures 9 and 10.
For the Low Battery Detect, the user has the option to
operate the IC in the programmable or non–programmable
modes. Note that the 48 pin package can only be used in the
programmable mode. Figure 128 describes this operation
(refer to the Serial Interface section under Clock Divider
Register).
Figure 2. Internal Low Battery Detect Levels
(with VB = 1.5 V)
Battery
Detect
Select
Ramping
Up
Ramping
Down
(V)
Average
(V)
Hysteresis
(mV)
(V)
0
1
2
3
4
5
6
7
–
–
–
–
2.867
2.953
3.039
3.207
3.291
3.375
3.461
2.861
2.947
3.031
3.199
3.285
3.367
3.453
2.864
2.950
3.035
3.204
3.288
3.371
3.457
4.0
6.0
8.0
8.0
6.0
8.0
8.0
In the programmable mode several different internal
threshold levels are available (Figure 2). The bits are set
through the SCF Clock Divider Register as shown in Figures
108 and 126. The reference for the internal divider network is
V
Audio. The voltages on the internal divider network are
compared to the Internal Reference Voltage, VB, generated
by an internal source. Since the internal comparator used is
CC
NOTE: 10. Battery Detect Select 0 is the non–programmable operating
mode.
non–inverting, a high at V
Audio will yield a high at the
CC
17
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
DC CURRENT
Figure 4. Current versus Supply
Voltage Standby Mode, MCU
Clock Output – On at 2.048 MHz
Figure 3. Current versus Supply
Voltage Inactive Mode
40
35
30
25
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
MCU Clock Out On
20
15
10
5.0
0
MCU Clock Out Off
0.1
0
2.7
3.1
3.5
V
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
V
3.9
4.3
4.7
5.1
5.5
, SUPPLY VOLTAGE (V)
, SUPPLY VOLTAGE (V)
CC
CC
Figure 6. Current versus Supply Voltage
Active Mode
Figure 5. Current versus Supply
Voltage Receive Mode
5.0
4.9
4.8
4.7
4.6
8.0
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7.0
MCU Clock Out On
MCU Clock Out On
MCU Clock Out Off
4.5
4.4
4.3
4.2
4.1
4.0
MCU Clock Out Off
2.7
3.1
3.5
V
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
V
3.9
4.3
4.7
5.1
5.5
, SUPPLY VOLTAGE (V)
, SUPPLY VOLTAGE (V)
CC
CC
Figure 7. Current versus
Temperature Normalized to 25°C
Figure 8. Current versus
Temperature Normalized to 25°C
15
10
6.0
4.0
Receive
°
°
2.0
0
Active
5.0
0
–2.0
–4.0
–6.0
–8.0
–10
–12
Standby
–5.0
–10
Inactive
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
T , TEMPERATURE ( C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
T , TEMPERATURE ( C)
°
°
A
A
18
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
DC CURRENT
Figure 10. Additional IP3
Supply Current Consumption versus
Figure 9. Additional Supply Current Consumption
versus Supply Voltage, IP3 = <1>
Temperature Normalized to 25°C
10
5
1.50
°
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
1.32
1.30
0
Receive/Active
Receive/Active
–5
–10
–15
–20
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
T , TEMPERATURE ( C)
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
, SUPPLY VOLTAGES (V)
V
°
CC
A
Figure 11. Current Standby
Figure 12. VB Voltage versus Temperature
Mode versus MCU Clock Output
Normalized to 1.5 V at 25°C
800
750
700
650
600
550
500
450
400
350
300
1.5075
1.5050
1.5025
1.5000
1.4975
1.4950
1.4925
10 pF load
No load
MCU clock off
1.0
10
100
1000
–20 –10
0
10
20
30
40
50
C)
60
70
80
90
MCU CLK OUT DIVIDE VALUE
T , TEMPERATURE (
°
A
19
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
FIRST AND SECOND MIXER
Mixer Description
Figure 14. First Mixer Output Impedance
The 1st and 2nd mixers are similar in design. Both are
double balanced to suppress the LO and the input
frequencies to give only the sum and difference frequencies
at the mixer output. Typically the LO is suppressed better
than –50 dB for the first mixer and better than –40 dB for the
second mixer. The gain of the 1st mixer has a –3.0 dB corner
at approximately 13 MHz and is used at a 10.7 MHz IF. It has
an output impedance of 300 Ω and matches to a typical
10.7 MHz ceramic filter with a source and load impedance of
330 Ω. A series resistor may be used to raise the impedance
for use with crystal filters. They typically have an input
impedance much greater than 330 Ω.
Unit
Output Impedance
304 Ω // 3.7 pF
B IP3 = <0> (Set Low)
B IP3 = <1> (Set High)
300 Ω // 4.0 pF
Figures 13, 14, and 16 represent the input and output
impedance for the first mixer. Notice that the input
single–ended and differential impedances are basically the
same. The output impedance as described in Figure 14 will
be used to match to a ceramic or crystal filter’s input
impedance. A typical ceramic filter input impedance is 330 Ω
while crystal filter input impedance is usually 1500 Ω. Exact
impedance matching to ceramic filters are not critical,
however, more attention needs to be given to the filter
characteristics of a crystal filter. Crystal filters are much
narrower. It is important to accurately match to these filters to
guaranty a reasonable response.
First Mixer
Figures 17 through 20 show the first mixer transfer curves
for the voltage conversion gain, output level, and
intermodulation. Notice that there is approximately 10 dB
linearity improvement when the “IP3 Increase” bit is set to
<1>. The “IP3 Increase” bit is a programmable bit as shown in
To find the IF bandwidth response of the first mixer refer to
Figure 22. The –3.0 dB bandwidth point is approximately 13
MHz. Figure 15 is a summary of the first mixer feedthrough
parameters.
the Serial Programmable Interface section under the R
Counter Latch Register. The IP3 = <1> option will increase
the supply current demand by 1.3 mA.
x
Figure 15. First Mixer Feedthrough Parameters
Figure 13. First Mixer Input and Output Impedance
Schematic
Parameter
1st LO Feedthrough @ Mix In
(dBm)
–70.0
–55.5
–61.0
1
1
1st Mixer
1st LO Feedthrough @ Mix Out
1
RF Feedthrough @ Mix Out with –30 dBm
1
Mix In
Mix Out
1
1
R
C
C
R
PO
PI
PI
PO
Figure 16. First Mixer Input Impedance over Input Frequency
US Center Channels
France Center Channels
49 MHz
46 MHz
41 MHz
26 MHz
Unit
Single–Ended
Differential
1550 Ω // 3.7 pF
1600 Ω // 1.8 pF
1560 Ω // 3.7 pF
1610 Ω // 1.8 pF
1570 Ω // 3.8 pF
1670 Ω // 1.8 pF
1650 Ω // 3.7 pF
1710 Ω // 1.8 pF
Note: 11. Single–Ended data is from measured results. Differential data is from simulated results.
20
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
FIRST MIXER
Figure 17. First Mixer Voltage Conversion
Gain, IP3_bit = 0
Figure 18. First Mixer Voltage Conversion
Gain, IP3_bit = 1
14
12
10
14
12
10
V
= 3.6 V
V
= 3.6 V
CC
IF = 10.695 MHz, 330
CC
IF = 10.695 MHz, 330
Ω
Ω
8.0
6.0
4.0
2.0
8.0
6.0
–40
–40
–35
–30
–25
–20
–15
–10
–35
–30
–25
–20
–15
–10
Mix In, MIXER INPUT LEVEL (dBm)
Mix In, MIXER INPUT LEVEL (dBm)
1
1
Figure 19. First Mixer Output Level and
Intermodulation, IP3_bit = 0
Figure 20. First Mixer Output Level and
Intermodulation, IP3_bit = 1
0
–20
–40
0
Fundamental Level
–20
–40
Fundamental Level
3rd Order
Intermodulation
3rd Order
Intermodulation
–60
–80
–60
–80
V
= 3.6 V
V
= 3.6 V
CC
IF = 10.695 MHz, 330
CC
IF = 10.695 MHz, 330
Ω
Ω
–100
–100
–40
–35
–30
–25
–20
–15
–10
–40
–35
–30
–25
–20
–15
–10
Mix In, MIXER INPUT LEVEL (dBm)
Mix In, MIXER INPUT LEVEL (dBm)
1
1
Figure 21. First Mixer Compression versus
Supply Voltage
Figure 22. First IF Bandwidth
–10
–12
–14
–16
–18
15
10
IP3_bit = 1
5.0
0
IF = 10.695 MHz, 330
Ω
V
R
= 3.6 V
CC
L
= 330
Ω
–5.0
–10
–15
LO = 36.075 MHz
IP3_bit = 0
–20
–22
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
1.0
10
f, IF FREQUENCY (MHz)
100
V
Audio, AUDIO SUPPLY VOLTAGE (V)
CC
21
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Second Mixer
The 2nd mixer input impedance is typically 2.8 kΩ. It
requires an external 360 Ω parallel resistor for use with a
standard 330 Ω, 10.7 MHz ceramic filter. The second mixer
output impedance is 1.5 kΩ making it suitable to match
standard 455 kHz ceramic filters.
The IF bandwidth response of the second mixer is shown
in Figure 31. The –3.0 dB corner is 2.5 MHz. The feedthrough
parameters are summarized in Figure 25.
Figures 26 through 29 represents the second mixer
transfer characteristics for the voltage conversion gain,
output level, and intermodulation. There is a slight
improvement in gain when the “IP3 bit” is set to <1> for the
second mixer. (Note: This is the same programmable bit
discussed earlier in the section.)
Figure 23. Second Mixer Input and Output
Impedance Schematic
Figure 25. Second Mixer Feedthrough Parameters
Parameter
2nd LO Feedthrough @ Mix Out
(dBm)
–42.9
–61.7
2nd Mixer
2
IF Feedthrough @ Mix Out with –30 dBm
2
Mix In
Mix Out
2
2
R
C
C
R
PO
PI
PI
PO
Figure 24. Second Mixer Input and Output
Impedances
Output
Input Impedance
// C
Impedance
// C
R
R
Unit
PI
PI
PO
PO
IP3 = <0> (Set Low)
IP3 = <1> (Set High)
2817 Ω // 3.6 pF
2817 Ω // 3.6 pF
1493 Ω // 6.1 pF
1435 Ω // 6.2 pF
22
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
SECOND MIXER
Figure 27. Second Mixer Conversion Gain,
Figure 26. Second Mixer Conversion Gain,
IP3_bit = 0
IP3_bit = 1
22
20
18
16
14
22
20
18
16
V
= 3.6 V
V
= 3.6 V
CC
CC
IF = 455 kHz
= 1500 Ω
IF = 455 kHz
R
= 1500
Ω
R
L
L
12
14
–40
–40
–35
–30
–25
–20
–15
–10
–35
–30
–25
–20
–15
–10
Mix In, MIXER INPUT LEVEL (dBm)
Mix In, MIXER INPUT LEVEL (dBm)
2
2
Figure 28. Second Mixer Output Level and
Intermodulation, IP3_bit = 0
Figure 29. Second Mixer Output Level and
Intermodulation, IP3_bit = 1
10
–10
–30
10
–10
–30
Fundamental Level
Fundamental Level
3rd Order
Intermodulation
3rd Order
Intermodulation
–50
–70
–90
–50
–70
–90
V
= 3.6 V
V
= 3.6 V
CC
IF = 455 kHz
= 1500
CC
IF = 455 kHz
= 1500 Ω
R
Ω
R
L
L
–40
–35
–30
–25
–20
–15
–10
–40
–35
–30
–25
–20
–15
–10
Mix In, MIXER INPUT LEVEL (dBm)
Mix In, MIXER INPUT LEVEL (dBm)
2
2
Figure 30. Second Mixer Compression
versus Supply Voltage
Figure 31. Second IF Bandwidth
–10
–12
–14
–16
–18
25
20
15
IP3_bit = 1
IP3_bit = 0
10
5.0
0
IF = 455 kHz
V
= 3.6 V
R = 1500 Ω
CC
L
–20
–22
R
= 1500
Ω
L
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
0.1
1.0
10
V
Audio, AUDIO SUPPLY VOLTAGE (V)
f, IF FREQUENCY (MHz)
CC
23
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
First Local Oscillator
To select the proper L
and C we can do the following
ext
ext
analysis. From Figure 34 it is observed that an inductor will
have a significant affect on first LO performance, especially
over frequency. The overall minimum Q required for first LO
to function as it relates to the LO frequency is also given in
Figure 34.
Choose an inductor value, say 470 nH. From Figure 34,
the minimum operating Q is approximately 25. From the
following equation:
The 1st LO is a multi–vibrator oscillator. The tank circuit is
composed of a parallel external capacitance and inductance,
internal programmable capacitor matrix, and internal
varactor. The local oscillator requires a voltage controlled
input to the internal varactor and an external loop filter driven
by on–board phase–lock control loop (PLL). The 1st LO
internal component values have a tolerance of ±15%. A
typical dc bias level on the LO Input and LO Output is 0.45
Vdc. The temperature coefficient of the varactor is
+0.08%/°C. The curve in Figure 33 is the varactor control
voltage range as it relates to varactor capacitance. It
represents the expected internal capacitance for a given
Q Coil = R /X Coil
p
where: R = parallel equivalent impedance (Figure 35).
p
C
can be determined as follows:
1
ext
f
control voltage (V
MC13111A/B. Figure 32 shows a representative schematic of
the first LO function.
Ctrl) of the MC13110A/B and
cap
LO
2
L
C
ext ext
= external inductance, C
where: L
= external
ext
ext
Figure 32. First Local Oscillator Schematic
capacitance.
Figure 34 clearly indicates that for lower coil values, higher
quality factors (Q) are required for the first LO to function
properly. Also, lower LO frequencies need higher Q’s. In
Figure 35 the internal programmable capacitor selection
relative to the first LO frequency and the parallel impedance
is shown. This information will help the user to decide what
V
Ctrl
cap
Varactor
LO In
1
Programmable
Internal
Capacitor
C
ext
inductor (L ) to choose for best performance in terms of Q.
ext
L
1st LO
ext
Varactor
Refer to the Auxiliary Register in the Serial Interface
Section for further discussion on LO programmability.
LO Out
1
24
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
FIRST LOCAL OSCILLATOR
Figure 34. First LO Minimum Required Overall
Q Value versus Inductor Value
Figure 33. First LO Varicap Capacitance
versus Control Voltage
120
100
80
60
40
20
0
15
14
13
30 MHz
12
40 MHz
11
10
50 MHz
9.0
8.0
7.0
100
1000
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
LO INDUCTOR VALUE (nH)
V
, CONTROL VOLTAGE (V)
capCtrl
Figure 35. Representative Parallel Impedance
versus Capacitor Select
Figure 36. Varicap Value at V = 1.0 V
CV
Over Temperature
100
11
10.6
10.2
9.8
30 MHz
40 MHz
50 MHz
9.4
10
9.8
0
2
1
5
6
7
4
3
8
9
10 11 12 13 14 15
–20
0
25
55
70
C)
85
C –C , CAPACITANCE SELECT
T , AMBIENT TEMPERATURE (
°
1
15
A
Figure 37. Control Voltage versus
Figure 38. Control Voltage versus
Channel Number, U.S. Handset Application
Channel Number, U.S. Baseset Application
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
1.8
1.7
1.6
1.5
1.4
Cap 11
Cap 8
Cap 10
Cap 6
Cap 3
1.3
1.2
1.1
1.0
0.9
Cap 9
Cap 4
0.8
1
3
5
7
9
11
13
15 17
19
21 23
25
1
3
5
7
9
11
13
15 17
19
21 23
25
CH1–CH25, U.S. HANDSET CHANNEL APPLICATION
CH1–CH25, U.S. BASESET CHANNEL APPLICATION
25
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Second Local Oscillator
Figure 41 shows a typical gain/phase response of the
second local oscillator. Load capacitance (C ), equivalent
L
The 2nd LO is a CMOS oscillator. It is used as the PLL
reference oscillator and local oscillator for the second
frequency conversion in the RF receiver. It is designed to
utilize an external parallel resonant crystal. See schematic in
Figure 39.
series resistance (ESR), and even supply voltage will have
and affect on the 2nd LO response as shown in Figures 45
and 46. Except for the standby mode open loop gain is fairly
constant as supply voltage increases from 2.5 V. This is due
to the regulated voltage of 2.5 V on PLL V . From the graphs
ref
it can seen that optimum performance is achieved when C1
equals C2 (C1/C2 = 1).
Figure 39. Second Local Oscillator Schematic
2nd LO
Figure 46 represents the ESR versus crystal load
capacitance for the 2nd LO. This relationship was defined by
using a 6.0 dB minimum loop gain margin at 3.6 V. This is
considered the minimum gain margin to guarantee oscillator
start–up.
Oscillator start–up is also significantly affected by the
crystal load capacitance selection. In Figures 42 and 43 the
relationship between crystal load capacitance, supply
voltage, and external load capacitance ratio (C2/C1), can be
seen. The lower the load capacitance the better the
performance.
R
C
C
R
PO
PI
PI
PO
Gm
LO In
LO Out
2
2
Xtal
Given the desired crystal load capacitance, C1 and C2
can be determined from Figure 47. It is also interesting to
point out that current consumption increases when C1 ≠ C2,
as shown in Figure 44.
Be careful not to overdrive the crystal. This could cause a
noise problem. An external series resistor on the crystal
output can be added to reduce the drive level, if necessary.
C
C
2
1
Figure 40. Second Local Oscillator
Input and Output Impedance
Input Impedance (R // C
)
11.6 kΩ // 2.9 pF
9.6 kΩ // 2.7 pF
PI
PI
Output Impedance (R
PO
// C
)
PO
SECOND LOCAL OSCILLATOR
Figure 41. Second LO Gain/Phase @ –10 dBm
Figure 42. Start–Up Time versus Capacitor
Ratio, Inactive to R Mode
x
15
10
6.0
5.0
4.0
90
10.24 MHz Crystal
67.5
C
R
= 10 pF
L
S
= 20
Ω
Gain
10.24 MHz Crystal
5.0
0
45
C
R
= 10 pF
L
S
= 20
Ω
22.5
0
V
= 2.3 V
C1 = C2 = 15 pF
CC
–5.0
–10
–15
3.0
V
V
V
= 2.7 V
= 3.6 V
= 5.0 V
CC
CC
CC
–22.5
–45
2.0
1.0
0
Phase
–20
–25
–67.5
–90
10.235
10.24
f, FREQUENCY (MHz)
10.245
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CAPACITOR RATIO (C2:C1)
26
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
SECOND LOCAL OSCILLATOR
Figure 43. Start–Up Time versus Capacitor
Ratio, Inactive to R Mode
Figure 44. Second LO Current Consumption
versus Capacitor Ratio
x
30
25
20
800
700
13
12
11
10.24 MHz Crystal
Standby Current with Clk_Out
Running at 2.048 MHz
C
R
= 24 pF
L
S
V
V
V
V
= 2.3 V
= 2.7 V
= 3.6 V
= 5.0 V
CC
CC
CC
CC
= 16
Ω
600
500
400
300
15
10
Standby Current
with Clk_Out Off
200
100
0
10
10.24 MHz Crystal
5.0
0
C
R
= 10 pF
Oscillator Level
3.0 3.5 4.0
L
S
= 20
Ω
9.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.5
1.0
1.5
2.0
2.5
CAPACITOR RATIO (C2:C1)
CAPACITOR RATIO (C2:C1)
Figure 46. Maximum Allowable
Equivalent Series Resistance (ESR)
versus Crystal Load Capacitance
Figure 45. Maximum Open Loop Gain
versus Capacitor Ratio
20
16
12
8.0
4.0
0
1000
V
= 2.7, 3.6, 5.0 V
CC
V
= 2.3 V
CC
100
10
10.24 MHz Crystal
C
R
R
= 10 pF
L
S
x
= 20
Ω
Mode
Curve Valid for f
in the Range of 10 MHz to 12 MHz
osc
16
0
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
12
14
18
20
22
24
26
28
30
32
CAPACITOR RATIO (C2:C1)
CRYSTAL LOAD CAPACITANCE (pF)
Figure 47. Optimum Value for C1 and C2
versus Equivalent Required Parallel
Capacitance of the Crystal
70
60
50
40
30
20
10
C1 = C2
0
0
5.0
10
15
20
25
30
35
REQUIRED PARALLEL CRYSTAL LOAD CAPACITANCE (pF)
27
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
IF Limiter and Demodulator
the IF bandpass Q is approximately 23; the loaded Q of the
quadrature tank is chosen slightly lower at 15.
The limiting IF amplifier typically has about 110 dB of gain;
the frequency response starts rolling off at 1.0 MHz.
Decoupling capacitors should be placed close to Pins 31 and
32 to ensure low noise and stable operation. The IF input
impedance is 1.5 kΩ. This is a suitable match to 455 kHz
ceramic filters.
Example:
Let the total external C = 180 pF. (Note: the capacitance is
the typical capacitance for the quad coil.) Since the external
capacitance is much greater than the internal device and
PCB parasitic capacitance, the parasitic capacitance may be
neglected.
Figure 48. IF Limiter Schematic
Limiter Stage
Rewrite equation (2) and solve for L:
2
2
)
L = (0.159) /(C f
c
L = 678 µH ; Thus, a standard value is chosen:
L = 680 µH (surface mount inductor)
Lim In
Lim Out
The value of the total damping resistor to obtain the
required loaded Q of 15 can be calculated from equation (1):
R
C
PI
PI
R = Q(2π f L)
T
R = 15(2π)(0.455)(680) = 29.5 kΩ
T
Figure 49. Limiter Input Impedance
The internal resistance, R at the quadrature tank Pin 27
int
Input Impedance
(R
Input Impedance
(C
is approximately 100 kΩ and is considered in determining the
)
PI
)
Unit
PI
external resistance, R
which is calculated from:
ext
Lim In
1538 Ω
15.7 pF
R
ext
R
ext
R
ext
= ((R )(R ))/(R – R )
int int
T
T
= 41.8 kΩ;Thus, choose a standard value:
= 39 kΩ
Figure 50. Quadrature Detector
Demodulator Schematic
In Figure 50, the R
ext
is chosen to be 22.1 kΩ. An
adjustable quadrature coil is selected. This tank circuit
represents one popular network used to match to the
455 kHz carrier frequency. The output of the detector is
represented as a “S–curve” as shown in Figure 52. The goal
is to tune the inductor in the area that is most linear on the
“S–curve” (minimum distortion) to optimize the performance
in terms of dc output level. The slope of the curve can also be
C
28
10 p
Lim Out
Q Coil
1
R
Toko Q Coil
7MCS–8128Z
ext
22.1 k
adjusted by choosing higher or lower values of R
. This will
ext
have an affect on the audio output level and bandwidth. As
is increased the detector output slope will decrease.
R
ext
The quadrature detector is coupled to the IF with an
external capacitor between Pins 27 and 28. Thus, the
recovered signal level output is increased for a given
bandwidth by increasing the capacitor. The external
quadrature component may be either a LCR resonant circuit,
which may be adjustable, or a ceramic resonator which is
usually fixed tuned. (More on ceramic resonators later.)
The bandwidth performance of the detector is controlled
by the loaded Q of the LC tank circuit (Figure 50). The
following equation defines the components which set the
detector circuit’s bandwidth:
The maximum audio output swing and distortion will be
reduced and the bandwidth increased. Of course, just the
opposite is true for smaller R
.
ext
A ceramic discriminator is recommended for the
quadrature circuit in applications where fixed tuning is
desired. The ceramic discriminator and a 5.6 kΩ resistor are
placed from Pin 27 to V
. A 22 pF capacitor is placed from
CC
Pin 28 to 27 to properly drive the discriminator. MuRata Erie
has designed a resonator for this part (CDBM455C48 for
USA & A/P regions and CDBM450C48 for Europe). This
resonator has been designed specifically for the
MC13110/111 family. Figure 51 shows the schematic used to
generate the “S–curve” and waveform shown in Figure 54
and 55.
(1) R = Q X ,
T
L
where R is the equivalent shunt resistance across the LC
T
tank. X is the reactance of the quadrature inductor at the IF
L
frequency (X = 2π f L).
L
The 455 kHz IF center frequency is calculated by:
1/2
(2) f = [2π (L Cp) ] – 1
c
where L is the parallel tank inductor. Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a detector at 455
kHz and a specific loaded Q:
The loaded Q of the quadrature detector is chosen
somewhat less than the Q of the IF bandpass for margin. For
an IF frequency of 455 kHz and an IF bandpass of 20 kHz,
28
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
(CDBM455C48 US; CDBM450C48 France)
Figure 51. Ceramic Resonator Demodulator
Schematic with Murata CDBM450C48
The “S–curve” for the ceramic discriminator shown in
Figure 54 is centered around 450 kHz. It is for the French
application. The same resonator is also used for the US
application and is centered around 455 kHz. Clearly, the
“S–curves” for the resonator and quad coil have very similar
limiter outputs. As discussed previously, the slope of the
“S–curve” centered around the center frequency can be
C
28
390 p
Lim Out
Q Coil
1
Ceramic Resonator
Murata
CDBM450C34
R
ext
2.7 k
controlled by the parallel resistor, R . Distortion, bandwidth,
ext
and audio output level will be affected.
IF LIMITER AND DEMODULATION
Figure 52. S–Curve of Limiter
Discriminator with Quadrature Coil
Figure 53. Typical Limiter Output
Waveform with Quadrature Coil
800
2.2
f = 455 kHz
Toko 7MCS–8128Z
1.8
1.4
1.0
0.6
Vpp
= 344 mV
typ
600
1.0
400
200
0.2
0
425
435
445
455
465
475
485
Lim In, INPUT FREQUENCY (kHz)
t, TIME (ms)
Figure 54. S–Curve of Limiter
Discriminator with Ceramic Resonator
Figure 55. Typical Limiter Output
Waveform with Ceramic Resonator
800
1.7
1.6
1.5
1.4
1.3
1.2
f = 450 kHz
Murata CDBM450C48
Vpp
= 370 mV
typ
600
1.0
400
200
1.1
1.0
0.9
0.8
0.7
0.6
0
440 442 444
446 448 450
452 454 456 458 460
Lim In, INPUT FREQUENCY (kHz)
t, TIME (ms)
29
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
RSSI and Carrier Detect
the RSSI pin to ground in parallel with the capacitor. From
Figure 57, the affect of an external resistor at RSSI on the
carrier detect level can be noticed. Since there is hysteresis
in the carrier detect comparator, one trip level can be found
when the input signal is increased while the another one can
be found when the signal is decreased.
Figure 58 represents the RSSI ripple in relation to the RF
input for different filtering capacitors at RSSI. Clearly, the
higher the capacitor, the less the ripple. However, at low
carrier detect thresholds, the ripple might supersede the
hysteresis of the carrier detect. The carrier detect output may
appear to be unstable. Using a large capacitor will help to
stabilize the RSSI level, but RSSI charge time will be
affected. Figure 59 shows this relationship.
The Received Signal Strength Indicator (RSSI) indicates
the strength of the IF level. The output is proportional to the
logarithm of the IF input signal magnitude. RSSI dynamic
range is typically 80 dB. A 187 kΩ resistor to ground is
provided internally to the IC. This internal resistor converts
the RSSI current to a voltage level at the “RSSI” pin. To
improve the RSSI accuracy over temperature an internal
compensated reference is used. Figure 56 shows the RSSI
versus RF input. The slope of the curve is 16.5 mV/dB.
The Carrier Detect Output (CD Out) is an open–collector
transistor output. An external pull–up resistor of 100 kΩ will
be required to bias this device. To form a carrier detect filter a
capacitor needs to be connected from the RSSI pin to
ground. The carrier detect threshold is programmable
through the MPU interface (see “Carrier Detect Threshold
Programming” in the serial interface section). The range can
be scaled by connecting additional external resistance from
The user must decide on a compromise between the RSSI
ripple and RSSI start–up time. Choose a 0.01 µf capacitor as
a starting point. For low carrier detect threshold settings, a
0.047 µf capacitor is recommended.
RSSI AND CARRIER DETECT
Figure 56. Typical RSSI Voltage
Level versus RF Input
Figure 57. Carrier Detect Threshold versus
External RSSI Resistor
0
1.6
1.4
–10
–20
–30
–40
–50
–60
–70
–80
–90
Limiter Input
1.2
1.0
0.8
0.6
Increasing Signal
Decreasing Signal
Increasing Signal
0.4
0.2
0
Mixer 1
Input
Decreasing Signal
–120
–100
–80
–60
–40
–20
0
100
1000
Mix In, RF INPUT (dBm)
R
, LOAD RESISTANCE (kΩ)
1
RSSI
Figure 58. RSSI Ripple versus RF Input Level for
Different RSSI Capacitors
Figure 59. RSSI Charge Time
versus Capacitor Value
11
10
35
30
25
20
15
10
5.0
0
10 nF
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
22 nF
33 nF
47 nF
100 nF
–120
–110
–100
–90
–80
–70
–60
0.01 0.02 0.03
0.04 0.05 0.06 0.07
0.08 0.09 0.10
µF)
Mix In, RF INPUT (dBm)
C
, LOAD CAPACITANCE (
1
RSSI
30
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
RF System Performance
The exact impedance looking into the RF In1 pin is
displayed in the following table along with the sensitivity
levels.
The sensitivity of the IC is typically 0.4 µVrms matched
(single ended or differential) with no preamp. To achieve
suitable system performance, a preamp and passive
duplexer may be used. In production final test, each section
of the IC is separately tested to guarantee its system
performance in the specific application. The preamp and
duplexer (differential, matched input) yields typically
–115 dBm @ 12 dB SINAD sensitivity performance under full
duplex operation. See Figure 45 and 48.
The duplexer is important to achieve full duplex operation
without significant “de–sensing” of the receiver by the
transmitter. The combination of the duplexer and preamp
circuit should attenuate the transmitter power to the receiver
by over 60 dB. This will improve the receiver system noise
figure without giving up too much IMD performance.
The duplexer may be a two piece unit offered by Shimida,
Sansui, or Toko products (designed for 25 channel CT–0
cordless phone). The duplexer frequency response at the
receiver port has a notch at the transmitter frequency band of
about 35 to 40 dB with a 2.0 to 3.0 dB insertion loss at the
receiver frequency band.
Figure 61. 12 dB SINAD Sensitivity Levels, US
Handset Application Channel 21
Input
Sensitivity
(dBm)
Impedance
(dBm)
Differential matched
Single–ended match
Single–ended 50 Ω
–115.3
–114.8
–100.1
50.2 ± 0.1j
50.2 ± 0.1j
50.2 ± 0.1j
The graphs in Figures 64 to 69 are performance results
based on Evaluation Board Schematic (Figure 138). This
evaluation board did not use a duplexer or preamp stage.
Figure 62 is a summary of the RF performance and Figure 63
contains the French RF Performance Summary.
Figure 62. RF Performance Summary
for US Applications
The preamp circuit utilizes a tuned transformer at the
output side of the amplifier. This transformer is designed to
bandpass filter at the receiver input frequency while rejecting
the transmitter frequency. The tuned preamp also improves
the noise performance by reducing the bandwidth of the pass
band and by reducing the second stage contribution of the
1st mixer. The preamp is biased such that it yields suitable
noise figure and gain.
MC13110A/MC13111A (fdev = 3.0 kHz, fmod = 1.0 kHz, 50 Ω)
Parameter
Handset
Baseset
Unit
Sensitivity at
12 dB SINAD
–100.1
–100.1
dBm
Recovered Audio
SINAD @ –30 dBm
THD @ –30 dBm
S/N @ –30 dBm
AMRR @ –30 dBm
RSSI range
132
41.8
0.8
132
41.4
0.8
mVrms
dB
The following matching networks have been used to
obtain 12 dB SINAD sensitivity numbers:
%
78.2
73.4
>80
78.5
72.2
>80
dB
dB
Figure 60. Matching Input Networks
dB
Differential Match
360
Figure 63. RF Performance Summary
for US French Applications
RF In
1
Mix In
1
1
MC13110A/MC13111A (fdev = 1.5 kHz, fmod = 1.0 kHz, 50 Ω)
39
1:5
15
Parameter
Handset
Baseset
Unit
Mix In
1
2
Sensitivity at
12 dB SINAD
–91
–90.8
dBm
Single–ended Match
680
Recovered Audio
SINAD @ –30 dBm
THD @ –30 dBm
S/N @ –30 dBm
AMRR @ –30 dBm
RSSI range
89.8
42.1
0.8
90
mVrms
dB
44.3
0.8
RF In
1
Mix In
1
1
%
39
1:5
15
75.7
56
75.1
84.7
>80
dB
Mix In
1
2
dB
0.01
>80
dB
Single–ended 50
Ω
Mix In
1
RF In
1
1
49.9
Ω
Mix In
1
2
0.01
31
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
RF SYSTEM PERFORMANCE
Figure 65. Typical Performance Parameters
Figure 64. Typical Receiver Performance
Over U.S. Handset Channel Frequencies
Parameters U.S. Handset Application Channel 21
138
137
85
80
80
1.7
S/N
70
60
50
40
30
1.5
S/N
75
70
136
135
1.3
1.1
0.9
0.7
0.5
AMRR
RSSI
65
134
60
55
50
45
40
35
133
132
131
130
129
128
SA Out Level
SINAD
20
10
0
SINAD
0.3
0.1
1
3
5
7
9
11 13
15
17
19 21 23 25
–120
–100
–80
–60
–40
–20
0
Mix In, RF INPUT (dBm)
U.S. HANDSET CHANNEL NUMBER
1
Figure 66. Typical Performance Parameters
Over U.S. Baseset Channel Frequencies
Figure 67. Typical Receiver Performance for
US Handset Application Channel 21
138
137
85
80
–10
–30
–50
–70
S/N
S+N+D
N+D
75
70
136
135
AMRR
65
60
55
50
45
40
35
134
133
132
131
130
129
128
SA Out Level
SINAD
AMR
N
–90
–110
–120
1
3
5
7
9
11 13
15
17
19 21 23 25
–100
–80
–60
–40
–20
0
U.S. BASESET CHANNEL NUMBER
Mix In , FIRST MIXER INPUT (dBm)
1
1
Figure 69. 12 dB SINAD Sensitivity Over
US Baseset Application Channels
Figure 68. 12 dB SINAD Sensitivity Over
US Handset Application Channels
–96
–96
–97
–97
–98
–98
–99
–99
–100
–101
–102
–100
–101
–102
1
5
9
13
17
21
25
1
5
9
13
17
21
25
US CHANNEL NUMBERS
US CHANNEL NUMBERS
32
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Receive Audio Path
enabled. However, assuming a nominal output level of –20
dBV (100 mVrms) at the 0 dB gain setting, the noise floor is
more than 56 dB below the audio signal. However, the noise
data at E Out and SA Out is much more improved.
The R Audio signal path begins at “Rx Audio In” and goes
through the IC to “E Out”. The “R Audio In”, “Scr Out”, and
x
“E In” pins are all ac–coupled. This signal path consists of
x
filters; programmable R gain adjust, R mute, and volume
x
x
Speaker Amp
control, and finally the expander. The typical maximum
output voltage at “E Out” should be approximately 0 dBV @
THD = 5.0% .
Figures 71 to 73 represent the receive audio path filter
response. The filter response attenuation is very sharp above
3900 Hz, which is the cutoff frequency. Inband (audio),
out–of–band, and ripple characteristics are also shown in
these graphs.
The Speaker Amp is an inverting rail–to–rail operational
amplifier. The noninverting input is connected to the internal
VB reference. External resistors and capacitors are used to
set the gain and frequency response. The “SA In” input pin
must be ac–coupled. The typical output voltage at “SA Out” is
2.6 V
with a 130 Ω load. The speaker amp response is
pp
shown in Figures 79 and 80.
Data Amp Comparator
The group delay (Figure 75) has a peak around 6.5 kHz.
This spike is formed by rapid change in the phase at the
frequency. In practice this does not cause a problem since
the signal is attenuated by at least 50 dB.
The output capability at “Scr Out” and “E Out” are shown in
Figures 76, 77, and 78. The results were obtained by
increasing the input level for 2.0% distortion at the outputs.
The data amp comparator is an inverting hysteresis
comparator. Its open collector output has an internal 100 kΩ
pull–up resistor. A band pass filter is connected between the
“Det Out” pin and the “DA In” pin with component values as
shown in the Application Circuit schematic. The “DA In” input
signal needs to be ac–coupled, too.
In Figure 70, noise data for the R audio path is shown.
x
At Scr Out, the noise level clearly rises when the scrambler is
Figure 70. R Path Noise Data
x
Receive
Scrambler
Receive Gain
(dB)
Volume
SCR_Out
(dBV)
E_Out
(dBV)
SA_Out
(dBV)
(dB)
muted
–14
0
off/on
muted
–9.0
0
< –95
–92
–85
–76
–85
–77
–66
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
< –95
off
off
off
1.0
–9.0
0
16
on (MC13110A/B)
on (MC13110A/B)
on (MC13110A/B)
–14
0
10
16
33
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
R AUDIO
x
Figure 71. R Audio Wideband Frequency Response
10
Figure 72. R Audio Inband Frequency Response
x
5.0
x
–5.0
–15
–25
–35
–45
–55
–10
–30
–50
–70
–110
R
Audio In
R
Audio In
x
x
–90
to Scr Out
= –20 dBV
to Scr Out
= –20 dBV
V
V
in
in
100
1000
10000
100000
1000000
100
1000
10000
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 73. R Audio Ripple Response
Figure 74. R Audio Inband Phase Response
x
x
0.5
0.3
0.1
180
135
90
45
0
–0.1
–0.3
–0.5
–45
–90
–135
–180
R Audio In
x
R
Audio In
x
to Scr Out
= –20 dBV
to Scr Out
V = –20 dBV
V
in
in
100
1000
10000
100
1000
10000
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 75. R Audio Inband Group Delay
x
Figure 76. R Audio Expander Response
x
28
24
20
16
12
8.0
4.0
10
1.0
0.1
0
5.0
–5.0
–15
–25
–35
–45
–55
–65
R
Audio In
x
to Scr Out
= –20 dBV
V
in
Expander Transfer
Distortion
0
0
100
1000
10000
–40
–20
E , INPUT VOLTAGE LEVEL (dBV)
in
–15
–10
–5.0
–35
–30
–25
f, FREQUENCY (Hz)
34
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
R AUDIO
x
Figure 77. R Audio Maximum Output Voltage
x
Figure 78. R Audio Maximum Output Voltage
x
versus Gain Control Setting
versus Volume Setting
–4.0
–6.0
–8.0
–10
–12
–14
–16
–18
–20
1.4
1.2
1.0
0.8
0.6
V
= 3.6 V
V
= 3.6 V
CC
THD = 2%
CC
THD = 2%
0.4
0.2
0
–9.0 –7.0
–5.0 –3.0
–1.0
1.0
3.0
5.0
7.0
9.0
–14
–10
–6.0
R PROGRAMMABLE VOLUME LEVEL SETTING
x
–2.0
2.0
6.0
10
14
R
PROGRAMMABLE GAIN CONTROL SETTING
x
Figure 79. R Audio Speaker Amplifier Drive
x
Figure 80. R Audio Speaker Amplifier Distortion
x
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5.0
0
No Load
130
Ω
620
130
Ω
Ω
620
Ω
No Load
0
0.4
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
SA In, INPUT VOLTAGE LEVEL (dBV)
SA In, INPUT VOLTAGE LEVEL (dBV)
35
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Transmit Audio Path
The limiter begins to clip the output signal at this level and
distortion is rapidly rising. Similarly, Figure 68 (ALC and
Limiter Off) shows to compressor transfer curve extending all
the way up to the maximum output. Finally, Figure 90 through
This portion of the audio path goes from “C In” to “T Out”.
x
The “C In” pin will be ac–coupled. The audio transmit signal
path includes automatic level control (ALC) (also referred to
93 show the T Out signal versus several combinations of
x
as the Compressor), T mute, limiter, filters, and T gain
x
x
ALC and Limiter selected.
adjust. The ALC provides “soft” limiting to the output signal
swing as the input voltage slowly increases. With this
technique the gain is slightly lowered to help reduce distortion
of the audio signal. The limiter section provides hard limiting
due to rapidly changing signal levels, or transients. This is
Figure 81 is the noise data measured for the
MC13110A/13111A. This data is for 0 dB gain setting and –20
dBV (100 mVrms) audio levels.
Figure 81. T Path Noise Data
x
accomplished by clipping the signal peaks. The ALC, T
mute, and limiter functions can be enabled or disabled via the
x
Transmit
Scrambler
Transmit
Gain
Amp_Out
(dBV)
T _Out
x
(dBV)
MPU serial interface. The T gain adjust can also be remotely
x
(dB)
controlled to set different desired signal levels. The typical
off/on
muted
–9.0
0
muted
< –95
< –95
< –95
< –95
< –95
–< –95
< –95
–83
–74
–64
–82
–73
–63
maximum output voltage at “T Out” should be approximately
x
0 dBV @ THD = 5.0%.
off
Figures 82 to 86 represent the transmit audio path filter
response. The filter response attenuation, again, is very
definite above 3800 Hz. This is the filter cutoff frequency.
Inband (audio), wideband, and ripple characteristics are also
shown in these graphs.
The compressor transfer characteristics, shown in
Figure 87, has three different slopes. A typical compressor
slope can be found between –55 and –15 dBV. Here the
slope is 2.0. At an input level above –15 dBV the automatic
level control (ALC) function is activated and prevents hard
clipping of the output. The slope below –55 dBV input level is
one. This is where the compressor curve ends. Above 5.0
dBV the output actually begins to decrease and distort. This
is due to supply voltage limitations.
off
off
10
on (MC13110A)
on (MC13110A)
on (MC13110A)
–9.0
0
10
Mic Amp
Like the Speaker Amp the Mic Amp is also an inverting
rail–to–rail operational amplifier. The noninverting input
terminal is connected to the internal VB reference. External
resistors and capacitors are used to set the gain and
frequency response. The “T In” input is ac–coupled.
x
In Figure 88 the ALC function is off. Here the compressor
curve continues to increase above –15 dBV up to –4.0 dBV.
36
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
T AUDIO
x
Figure 82. T Audio Wideband Frequency Response
10
Figure 83. T Audio Inband Frequency Response
x
5.0
x
0
–5.0
–15
–25
–35
–45
–55
–10
–20
–30
–40
–50
–60
–70
–80
C In to T Out
x
in
C In to T Out
x
V
= –10 dBV
V
= –10 dBV
–90
in
–100
100
1000
10000
100000
1000000
100
1000
10000
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 84. T Audio Ripple Response
Figure 85. T Audio Inband Phase Response
x
x
0.3
0.2
180
135
90
0.1
0
45
–0.1
–0.2
–0.3
–0.4
0
–45
–90
–0.5
–0.6
–0.7
C In to T Out
x
C In to T Out
x
–135
–180
V
= –10 dBV
V
= –10 dBV
in
in
100
1000
10000
100
1000
f, FREQUENCY (Hz)
10000
f, FREQUENCY (Hz)
Figure 86. T Audio Inband Group Delay
Figure 87. T Audio Compressor Response
x
x
10
0
–5.0
–10
–15
–20
–25
–30
–35
–40
4.0
ALC On,
Limiter On or Off
C In to T Out
x
3.0
2.0
V
= –10 dBV
in
1.0
Compressor
0.1
0
Distortion
1.0
0
100
–60
–50
–40
–30
–20
–10
0
1000
10000
10
f, FREQUENCY (Hz)
C In, INPUT VOLTAGE LEVEL (dBV)
37
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
T AUDIO
x
Figure 88. T Audio Compressor Response
x
Figure 89. T Audio Compressor Response
x
0
0
4.0
3.0
2.0
4.0
3.0
2.0
ALC Off,
Limiter On
ALC Off,
Limiter Off
–5.0
–10
–15
–20
–25
–30
–35
–40
–5.0
–10
–15
–20
–25
–30
–35
–40
Compressor Transfer
Compressor Transfer
1.0
0
1.0
0
Distortion
Distortion
–60
–50
–40
–30
–20
–10
0
10
–60
–50
–40
–30
–20
–10
0
10
C In, INPUT VOLTAGE LEVEL (dBV)
C In, INPUT VOLTAGE LEVEL (dBV)
Figure 90. T Audio Maximum Output Voltage
x
Figure 91. T Output Audio Response
x
versus Gain Control Setting
0
–4.0
–8.0
–12
–16
–20
V
= 3.6 V
Limiter and ALC Off
CC
A
B
C
A: ALC Off, Limiter Off
B: ALC Off, Limiter On
C: ALC On, Limiter On or Off
200 mV/Div
500 s/Div
µ
–7.0 –5.0
–3.0
–1.0
1.0
3.0
5.0
7.0
9.0
–9.0
T
PROGRAMMABLE GAIN CONTROL SETTING
t, TIME (µs)
x
Figure 92. T Output Audio Response
Figure 93. T Audio Output Response
x
x
Limiter On and ALC Off
Limiter On and ALC On
200 mV/Div
500 s/Div
200 mV/Div
500 s/Div
µ
µ
t, TIME (µs)
t, TIME (µs)
38
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
PLL SYNTHESIZER SECTION
PLL Frequency Synthesizer General Description
Figure 95 shows a simplified block diagram of the
programmable universal dual phase locked loop (PLL)
designed into the MC13110A/B and MC13111A/B IC. This
dual PLL is fully programmable through the MCU serial
interface and supports most country channel frequencies
including USA (25 ch), Spain, Australia, Korea, New Zealand,
U.K., Netherlands, France, and China (see channel frequency
tables in AN1575, “Worldwide Cordless Telephone
Frequencies”).
microprocessor. The maximum input and output levels for
these pins is V . Figure 94 shows a simplified schematic of
CC
the I/O pins.
Figure 94. PLL I/O Pin Simplified Schematics
PLL V
ref
V
Audio
PLL V
ref
V
Audio
CC
(2.7 to 5.5 V)
CC
(2.7 to 5.5 V)
(2.5 V)
(2.5 V)
I/O
In
Out
The 2nd local oscillator and reference divider provide the
reference frequency signal for the R and T PLL loops. The
x
x
2.0
µA
programmed divider value for the reference divider is
selected based on the crystal frequency and the desired R
LO In, LO Out,
Data, Clk and EN Pins
Clk Out Pin
2
2
x
R
PD, T PD and
x
x
and T reference frequency values. For the U.K., additional
x
T
VCO Pins
x
divide by 25 and divide by 4 blocks are provided to allow for
generation of the 1.0 kHz and 6.2 kHz reference frequencies.
PLL Loop Control Voltage Range
The control voltage for the T and R loop filters is set by
the phase detector outputs which drive the external loop
filters. The phase detectors are best considered to have a
current mode type output. The output can have three states;
ground, high impedance, and positive supply, which in this
The 14–bit R counter is programmed for the desired first
x
x
x
local oscillator frequency. The 14–bit T counter is
x
programmed for the desired transmit channel frequency. All
counters power–up to a set default state for USA channel #21
using a 10.24 MHz reference frequency crystal (see power–up
default latch register state in the Serial Programmable
Interface section).
case is the voltage at “PLL V ”. When the loop is locked the
ref
phase detector outputs are at high impedance. An exception
of this state is for narrow current pulses, referenced to either
the positive or negative supply rails. If the loop voltages get
within 0.5 V of either rail the linear current output starts to
degrade. The phase detector current source was not
designed to operate at the supply rails. VCO tuning range will
also be limited by this voltage range
To extend the sensitivity of the 1st LO for U.S. 25 channel
operation, internal fixed capacitors can be connected to the
tank circuit through microprocessor programmable control.
When designing the external PLL loop filters, it is
recommended that the T and R phase detectors be
x
x
considered as current drive type outputs. The loop filter
control voltage must be 0.5 V away from either the positive or
negative supply rail.
The maximum loop control voltage is the “PLL V ” voltage
which is 2.5 V. If a higher loop control voltage range is
ref
desired, the “PLL V ” pin can be pulled to a higher voltage.
ref
PLL I/O Pin Configurations
It can be tied directly to the V
voltage (with suitable filter
CC
The 2nd LO, R and T PLL’s, and MPU serial interface are
x
x
capacitors connected close to each pin). When this is done,
the internal voltage regulator is automatically disabled. This
is commonly used in the telephone base set where an
external 5.0 V regulated voltage is available. It is important to
powered by the internal voltage regulator at the “PLL V ” pin.
ref
The “PLL V ” pin is the output of a voltage regulator which is
ref
powered from the “V
CC
Audio” power supply pin. It is regulated
by an internal bandgap voltage reference. Therefore, the
maximum input and output levels for most of the PLL I/O pins
remember, that if “PLL V ” is tied to V
regulated voltage, the PLL loop parameters and lock–up time
will vary with supply voltage variation. The phase detector
and V is not a
ref
CC
CC
(LO2 In, LO2 Out, R PD, T PD, T VCO) is the regulated
x
x
x
voltage at the “PLL V ” pin. The ESD protection diodes on
ref
gain constant, K , will not be affected if the “PLL V ” is tied
pd ref
these pins are also connected to “PLL V ”.
ref
to V
CC.
Internal level shift buffers are provided for the pins (Data,
Clk, EN, Clk Out) which connect directly to the
Figure 95. Dual PLL Simplified Block Diagram
T
VCO
PD
x
14–b Programmable
T
VCO
x
T
Counter
x
8
T
x
T
Phase
U.K. Base
T
x
LP Loop Filter
LP Loop Filter
Detector
(Current
Output)
Ref
x
6
LO In
2
12–b
÷
25
4
U.K. Handset
U.K. Base
R
4
PD
1
Programmable
Reference
Counter
x
÷
LO Out
2
R
Phase
R
Ref
x
x
÷1
Detector
(Current
Output)
V
Ctrl
cap
2
U.K. Handset
42
LO In
1
14–b Programmable
Counter
40
LO Out
Programmable
Internal Capacitor
1st LO
R
x
1
41
39
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Loop Filter Characteristics
second order slope (–40 dB/dec) creating a phase of –180
degrees at the lower and higher frequencies. The filter
characteristic needs to be determined such that it is adding a
pole and a zero around the 0 dB point to guarantee sufficient
phase margin in this design (Qp in Figure 98).
Lets consider the following discussion on loop filters. The
fundamental loop characteristics, such as capture range,
loop bandwidth, lock–up time, and transient response are
controlled externally by loop filtering.
Figure 96 is the general model for a Phase Lock Loop
(PLL).
Figure 98. Bode Plot of Gain and
Phase in Open Loop Condition
0
Figure 96. PLL Model
Open Loop Gain
Phase
Detector (K
Filter
VCO
(K )
fi
fo
)
(K )
pd
f
o
0
–90
Divider
(K )
n
Where:
Phase
K
= Phase Detector Gain Constant
pd
K = Loop Filter Transfer Function
Q
p
f
K = VCO Gain Constant
o
K = Divide Ratio (1/N)
n
w
–180
p
fi = Input frequency
The open loop gain including the filter response can be
expressed as:
fo = Output frequency
fo/N = Feedback frequency divided by N
K
K (1 jw(R2C2))
o
From control theory the loop transfer function can be
represented as follows:
pd
A
openloop
(1)
R2C1C2
jwK jw 1
jw
A = K K K K Open loop gain
n
pd
f o n
C1 C2
K
can be either expressed as being 2.5 V/4.0 π or
pd
The two time constants creating the pole and the zero in
the Bode plot can now be defined as:
1.0 mA/2.0 π for the CT–0 circuits. More details about
performance of different type PLL loops, refer to Motorola
application note AN535.
The loop filter can take the form of a simple low pass filter.
A current output, type 2 filter will be used in this discussion
since it has the advantage of improved step response,
velocity, and acceleration.
R2C1C2
T1
T2
R2C2
(2)
C1 C2
By substituting equation (2) into (1), it follows:
The type 2 low pass filter discussed here is represented as
follows:
K
K T1
o
pd
1
1
jwT2
jwT1
A
(3)
openloop
2
w C1K T2
n
Figure 97. Loop Filter
with Additional Integrating Element
The phase margin (phase + 180) is thus determined by:
From
Phase
Detector
(
)
(
)
Q
arctan wT2 –arctan wT1
(4)
To VCO
p
At w=w , the derivative of the phase margin may be set to
zero in order to assure maximum phase margin occurs at w
(see also Figure 98). This provides an expression for w :
R2
C2
p
p
p
C1
dQ
p
dw
From Figure 97, capacitor C1 forms an additional
integrator, providing the type 2 response, and filters the
discrete current steps from the phase detector output. The
function of the additional components R2 and C2 is to create
a pole and a zero (together with C1) around the 0 dB point of
the open loop gain. This will create sufficient phase margin
for stable loop operation.
In Figure 98, the open loop gain and the phase is
displayed in the form of a Bode plot. Since there are two
integrating functions in the loop, originating from the loopfilter
and the VCO gain, the open loop gain response follows a
T2
T1
(5)
0
–
2
2
(
)
(
)
wT1
1
wT2
1
1
w
w
p
(6)
(7)
T2T1
Or rewritten:
1
2
T1
w
T2
p
40
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
By substituting into equation (4), solve for T2:
(11)
(12)
T2
T1
C2
C1
1
Q
p
tan
T2
C2
2
4
R2
(8)
T2
w
p
The VCO gain is dependent on the selection of the
external inductor and the frequency required. The free
running frequency of the VCO is determined by:
By choosing a value for w and Q , T1 and T2 can be
calculated. The choice of Q determines the stability of the
p
p
p
loop. In general, choosing a phase margin of 45 degrees is a
good choice to start calculations. Choosing lower phase
margins will provide somewhat faster lock–times, but also
generate higher overshoots on the control line to the VCO.
This will present a less stable system. Larger values of phase
margin provide a more stable system, but also increase
lock–times. The practical range for phase margin is 30
degrees up to 70 degrees.
1
f
(13)
2
LC
T
In which L represents the external inductor value and C
T
represents the total capacitance (including internal
capacitance) in parallel with the inductor. The VCO gain can
be easily calculated via the internal varicap transfer curve
shown below.
The selection of w is strongly related to the desired
p
lock–time. Since it is quite complicated to accurately
calculate lock time, a good first order approach is:
Figure 99. Varicap Capacitance
versus Control Voltage
15
(9)
3
p
T_lock
w
14
13
Equation (9) only provides an order of magnitude for lock
time. It does not clearly define what the exact frequency
difference is from the desired frequency and it does not show
the effect of phase margin. It assumes, however, that the
phase detector steps up to the desired control voltage
without hesitation. In practice, such step response approach
is not really valid. The two input frequencies are not locked.
Their phase maybe momentarily zero and force the phase
detector into a high impedance mode. Hence, the lock times
may be found to be somewhat higher.
12
11
10
9.0
8.0
7.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
In general, w should be chosen far below the reference
p
frequency in order for the filter to provide sufficient
attenuation at that frequency. In some applications, the
reference frequency might represent the spacing between
channels. Any feedthrough to the VCO that shows up as a
spur might affect adjacent channel rejection. In theory, with
the loop in lock, there is no signal coming from the phase
detector. But in practice leakage currents will be supplied to
both the VCO and the phase detector. The external
capacitors may show some leakage, too. Hence, the lower
As can be derived from Figure 99, the varicap capacitance
changes 1.3 pF over the voltage range from 1.0 V to 2.0 V:
1.3 pF
V
(14)
Cvar
Combining (13) with (14) the VCO gain can be determined
by:
w , the better the reference frequency is filtered, but the
p
longer it takes for the loop to lock.
1
jw
1
1
As shown in Figure 98, the open loop gain at w is 1 (or
0 dB), and thus the absolute value of the complex open loop
gain as shown in equation (3) solves C1:
p
K
o
Cvar
2
Cvar
2
2
L C
2
L C
T
T
(15)
2
Although the basic loopfilter previously described provides
adequate performance for most applications, an extra pole
may be added for additional reference frequency filtering.
Given that the channel spacing in a CT–0 telephone set is
based on the reference frequency, and any feedthrough to
K
K T1
1
1
w T2
p
o
pd
2
C1
(10)
2
w K T2
n
w T1
p
With C1 known, and equation (2) solve C2 and R2:
41
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
the first LO may effect parameters like adjacent channel
rejection and intermodulation. Figure 100 shows a loopfilter
architecture incorporating an additional pole.
Figure 100. Loop Filter
with Additional Integrating Element
From
Phase
Detector
To VCO
R3
R2
C2
C1
C3
For the additional pole formed by R3 and C3 to be efficient,
the cut–off frequency must be much lower than the reference
frequency. However, it must also be higher than w in order
p
not to compromise phase margin too much. The following
equations were derived in a similar manner as for the basic
filter previously described.
Similarly, it can be shown:
K
K
o
pd
1
1
jwT2
jwT1
A
–
(16)
(17)
openloop
In which:
2
2
(
)
K w C1 C2 C3 – w C1C2C3R2R3
n
(
)
(
)
C1 C2 T2
C1C2 T3
2
T1
C1 C2 C3 w C1T2T3
(18)
(19)
T2
R2C2
T3
R3C3
From T1 it can be derived that:
2
(
)
T1 T2 C3 C1 T2 T3 T1 w T1T2T3
C2
(20)
(21)
T3 T1
In analogy with (10), by forcing the loopgain to 1 (0 dB) at
w , we obtain:
p
2
K
K
1
1
w T2
o
2
p
pd
K w
(
)
C1 T1 T2
C2T3 C3T2
2
n p
w T1
p
Solving for C1:
2
2
K
K T1
1
1
w T2
p
o
pd
(
)
(
)
(
)
T3 T1
T2 T1 T3C3
T3 T1 T2C3
2
w
K
p
n
w T1
p
C1
(22)
(23)
2
(
)
(
)
T3 T1 T2
T3 T1 T3
T2 T3 T1
w
T1T2T3 T3
p
By selecting w via (9), the additional time constant
p
expressed as T3, can be set to:
1
Kw
T3
p
42
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
The K–factor shown determines how far the additional
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
pole frequency will be separated from w . Selecting too small
p
of a K–factor, the equations may provide negative
capacitance or resistor values. Too large of a K–factor may
not provide the maximum attenuation.
feedthrough at w will not be directly disastrous but still, the
p
additional pole may be added in the loopfilter design for
added safety.
By selecting R3 to be 100 kΩ, C3 becomes known and C1
and C2 can be solved from the equations. By using equations
(8) and (7), time constants T2 and T1 can be derived by
selecting a phase margin. Finally, R2 follows from T2 and C2.
The following pages, the loopfilter components are
determined for both handset and baseset the US application
based on the equations described. Choose K to be
In an application, w is chosen to be 20 times less than the
p
reference frequency of 5.0 kHz and the phase margin has
been set to 45 degrees. This provides a lock time according
to (9) of about 2.0 ms (order of magnitude). With the adjacent
channels spaced at least 15 kHz away, reference
feedthrough at w will not be directly disastrous but still, the
p
approximately five times w (5.0w ).
additional pole may be added in the loopfilter design for
added safety.
p
p
In an application, w is chosen to be 20 times less than the
p
reference frequency of 5.0 kHz and the phase margin has
Figure 101. Open Loop Response Handset US
with Selected Values
Figure 102. Open Loop Response Baseset US
with Selected Values
100 k
100 k
From
From
Phase
Detector
To VCO
Phase
Detector
To VCO
22 k
18 k
.082
6800
.068
1000
8200
1000
80
40
80
60
40
20
80
40
80
60
40
20
Loop
Gain
Loop
Gain
0
0
Phase
Margin
Phase
Margin
–40
–40
–80
0
–80
0
100
1000
10000
100000
1000000
100
1000
10000
f, FREQUENCY (Hz)
100000
1000000
f, FREQUENCY (Hz)
Figure 103. Handset US
Figure 104. Baseset US
Conditions
Conditions
L = 470 uH
F
ref
= 5.0 kHz
L = 470 uH
F
ref
= 5.0 kHz
RF = 46.77 MHz
VCO center = 36.075 MHz
Q
w
= 45 degrees
= w / 20 radians
ref
RF = 49.83 MHz
VCO center = 39.135 MHz
Q
w
= 45 degrees
= w / 20 radians
ref
p
p
p
p
Results
Equations Select
Results
Equations Select
K
K
= 159.2 uA/rad
K
= 159.2 uA/rad
pd
pd
= 3.56 Mrad/V
(14), (15)
(8)
(7)
K
VCO
= 4.54 Mrad/V
(14), (15)
(8)
(7)
VCO
T2 = 1540 µs
T1 = 264 µs
T3 = 91 µs
T2 = 1540 µs
T1 = 264 µs
T3 = 91 µs
with K = 7
with K = 7
C1 = 7.6 nF
(21)
(20)
(18)
choose:
(19)
C1 = 6.8 nF
C2 = 68 nF
R2 = 22 kΩ
R3 = 100 kΩ
C1 = 9.1 nF
(21)
(20)
(18)
choose:
(19)
C1 = 8.2 nF
C2 = 82 nF
R2 = 18 kΩ
R3 = 100 kΩ
C3 = 1 nf
C2 = 70.9 nF
R2 = 21.7 kΩ
R3 = 100 kΩ
C3 = 909.5 pF
C2 = 83.5 nF
R2 = 18.4 kΩ
R3 = 100 kΩ
C3 = 909.5 pF
C3 = 1 nf
43
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
SERIAL PROGRAMMABLE INTERFACE
Microprocessor Serial Interface
The state of the “EN” pin when clocking data into the shift
register determines whether the data is latched into the
address register or a data register. Figure 107 shows the
address and data programming diagrams. In the data
programming mode, there must not be any clock transitions
when “EN” is high. The clock can be in a high state (default
high) or a low state (default low) but must not have any
transitions during the “EN” high state. The convention in
these figures is that latch bits to the left are loaded into the
shift register first. A minimum of four “Clk” rising edge
transition must occur before a negative “EN” transition will
latch data or an address into a register.
The Data, Clock, and Enable (“Data”, “Clk”, and “EN”
respectively) pins provide a MPU serial interface for
programming the reference counters, the transmit and
receive channel divide counters, the switched capacitor filter
clock counter, and various other control functions. The “Data”
and “Clk” pins are used to load data into the MC13111A/B
shift register (Figure 109). Figure 105 shows the timing
required on the “Data” and “Clk” pins. Data is clocked into the
shift register on positive clock transitions.
Figure 105. Data and Clock Timing Requirement
t
t
f
r
Figure 107. Microprocessor Interface
Programming Mode Diagrams
90%
10%
Data,
Clk, EN
Data
MSB
8–Bit Address
LSB
Latch
Latch
50%
EN
Address Register Programming Mode
Data
t
suDC
MSB
16–Bit Data
Latch
LSB
Data
t
h
EN
50%
Data Register Programming Mode
Clk
The MPU serial interface is fully operational within 100 µs
after the power supply has reached its minimum level during
power–up (see Figure 108). The MPU Interface shift
registers and data latches are operational in all four power
After data is loaded into the shift register, the data is
latched into the appropriate latch register using the “EN” pin.
This is done in two steps. First, an 8–bit address is loaded
into the shift register and latched into the 8–bit address latch
register. Then, up to 16–bits of data is loaded into the shift
register and latched into the data latch register. It is specified
by the address that was previously loaded. Figure 106 shows
the timing required on the EN pin. Latching occurs on the
negative EN transition.
saving modes; Inactive, Standby, R , and Active Modes.
x
Data can be loaded into the shift registers and latched into
the latch registers in any of the operating modes.
Figure 108. Microprocessor Serial
Interface Power–Up Delay
Figure 106. Enable Timing Requirement
2.7 V
50%
50%
Last
Clock
First
Clock
t
puMPU
V
CC
Clk
t
t
suEC
rec
Data,
Clk, EN
50%
50%
Previous Data Latched
EN
44
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Data Registers
Figure 109 shows the data latch registers and addresses
which are used to select each of each registers. Latch bits to
the left (MSB) are loaded into the shift register first. The LSB
bit must always be the last bit loaded into the shift register.
Bits proceeding the register must be “0’s” as shown.
R mode with all mutes active. The reference counter is set to
x
generate a 5.0 kHz reference frequency from a 10.24 MHz
crystal. The switched capacitor filter clock counter is set
properly for operation with a 10.24 MHz crystal. The T and R
x
x
counter registers are set for USA handset channel frequency,
number 21 (Channel 6 for previous FCC 10 Channel Band).
Figure 110 shows the initial power–up states for all latch
registers.
Power–Up Defaults for Data Registers
When the IC is first powered up, all latch registers are
initialized to a defined state. The device is initially placed in the
Figure 109. Microprocessor Interface Data Latch Registers
Latch Address
1. (00000001)
0
0
0
MSB
MSB
14–b T Counter
LSB
LSB
x
T
Counter Latch
x
x
IP3
Increase
14–b R Counter
2. (00000010)
3. (00000011)
x
R
Counter Latch
U.K.
HS
Select
U.K.
BS
Select
MSB
12–b Reference Counter
LSB
0
0
0
0
0
Reference Counter Latch
ALC
Disable
Limiter
Disable
Clk
Disable
MPU
Clk 1
MPU
Clk 0
Stdby
Mode
R
Mode
T
Mute
R
x
SP
Mute
MPU
Clk 2
x
x
MSB
4–b Vol Control
LSB
LSB
4. (00000100)
5. (00000101)
6. (00000110)
Mute
Mode Control Latch
5–b T Gain Control
5–b R Gain Control
5–b CD Threshold Control
MSB
LSB
MSB
MSB
LSB
LSB
x
x
Gain Control Latch
6–b Switched
Capacitor Filter
Clock Counter Latch
3–b Low Battery
4–b Voltage
Reference Adjust
T
Sbl
R Sbl
x
x
MSB
MSB
0
LSB
MSB
Detect Threshold Select
Bypass
Bypass
SCF Clock Dividers Latch (MC13110A/B only)
6–b Switched
Capacitor Filter
Clock Counter Latch
3–b Low Battery
4–b Voltage
Reference Adjust
6. (00000110)
7. (00000111)
0
0
LSB
0
0
MSB
LSB
Detect Threshold Select
SCF Clock Dividers Latch (MC13111A/B only)
0
0
0
0
0
0
0
3–b Test Mode
4–b 1st LO Capacitor Selection
Auxillary Latch
45
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 110. Latch Register Power–Up Defaults
MSB
LSB
15
–
14
–
13
1
12
0
11
0
10
1
9
1
0
0
1
0
1
8
0
0
0
0
1
1
7
1
0
0
1
1
0
6
1
0
0
1
1
0
5
1
1
0
1
1
0
4
0
0
0
0
1
1
3
1
1
0
1
0
1
2
1
1
0
1
1
1
1
1
1
0
1
0
1
0
0
1
0
1
0
1
Register
Count
9966
7215
2048
N/A
T
x
R
–
–
0
1
1
1
x
Ref
Mode
Gain
–
–
0
0
1
0
–
0
0
0
0
1
N/A
–
0
1
1
1
1
SCF
31
–
0
0
0
0
1
(MC13110A/B)
SCF
(MC13111A/B)
31
–
0
0
0
0
1
1
1
–
–
0
1
1
0
1
0
1
0
1
0
Aux
N/A
–
–
–
–
–
–
–
–
–
0
0
0
NOTE: 12. Bits 6 and 7 in the SCF latch register are ”Don’t Cares” for the MC13111A/B since this part does not have a scrambler.
T and R Counter Registers
In this case, set “U.K. Base Select” and “U.K. Handset
Select” bits to “0”. Then the fixed divider is set to “1” and the
T and R reference frequencies will be equal to the crystal
oscillator frequency divided by the programmable reference
counter value.
x
x
The 14 bit T and R counter registers are used to select
x
x
the transmit and receive channel frequencies. In the R
x
x
x
counter there is an “IP3 Increase” bit that allows the ability to
trade off increased receiver mixer performance versus
reduced power consumption. With “IP3 increase” = <1>,
there is about a 10 dB improvement in 1 dB compression and
3rd order intercept for both the 1st and 2nd mixers. However,
there is also an increase in power supply current of 1.3 mA.
The power–up default for the MC13111A/B is “IP3 Increase”
= <0>. The register bits are shown in Figure 111.
The U.K. is a special case which requires a different
reference frequency value for T and R . For U.K. base
x
x
operation, set “U.K. Base Select” to “1”. For U.K. handset
operation, set “U.K. Handset Select” to “1”. The Netherlands
is also a special case. A 2.5 kHz reference frequency is used
for both the T and R reference and the total divider value
x
x
required is 4096. This is larger than the maximum divide
value available from the 12–bit reference divider (4095). In
this case, set “U.K. Base Select” to “1” and set “U.K. Handset
Reference Counter Register
Reference Counter
Figure 113 shows how the reference frequencies for the
Select” to “1”. This will give a fixed divide by 4 for both the T
and R reference. Then set the reference divider to 1024 to
x
x
R and T loops are generated. All countries except the U.K.
x
x
require that the T and R reference frequencies be identical.
x
x
get a total divider of 4096.
Figure 111. R and T Counter Register Latch Bits
x
x
0
0
0
MSB
MSB
14–b T Counter
LSB
LSB
x
T
Counter Latch
x
IP3
Increase
14–b R Counter
x
R
Counter Latch
x
Figure 112. Reference Counter Register
U.K.
Handset
Select
U.K.
Base
Select
0
0
MSB
12–b Ref Counter
LSB
46
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 113. Reference Counter Register Programming Mode
U.K. Base
T
Reference Frequency
x
LO In
2
÷ 25
÷ 4.0
÷1.0
U.K. Handset
U.K. Base
12–b
Programmable
Reference
Counter
LO
2
R
Reference Frequency
x
LO Out
2
U.K. Handset
U.K. Handset
U.K. Base
Select
T
Divider
Value
R Divider
x
x
Select
Value
Application
0
0
1
1
0
1
0
1
1
25
4
1
4
25
4
All but U.K. and Netherlands
U.K. Base Set
U.K. Hand Set
Netherlands Base and Hand Set
4
Figure 114. Reference Frequency and Divider Values
MC13110A/B
MC13111A/B
Reference
U.K. Base/
Handset
Divider
SC Filter
Clock
Divider
SC Filter
Clock
Frequency
Scrambler
Modulation
Divider
Scrambler
Modulation
Frequency
Crystal
Frequency
Divider
Value
Reference
Frequency
10.24 MHz
10.24 MHz
11.15 MHz
12.00 MHz
11.15 MHz
11.15 MHz
11.15 MHz
2048
1024
2230
2400
1784
446
1
4
5.0 kHz
5.0 kHz
5.0 kHz
5.0 kHz
6.25 kHz
6.25 kHz
1.0 kHz
31
31
34
36
34
34
34
165.16 kHz
165.16 kHz
163.97 kHz
166.67 kHz
163.97 kHz
163.97 kHz
163.97 kHz
40
40
40
40
40
40
40
4.129 kHz
4.129 kHz
4.099 kHz
4.167 kHz
4.099 kHz
4.099 kHz
4.099 kHz
1
1
1
4
446
25
Figure 115. Mode Control Register
ALC
Disable
MPU
Clk 2
Limiter
Disable Disable
Clk
MPU
Clk 1
MPU
Clk 0
4–b Volume
Control
Stdby
Mode
R
Mode
T
Mute
R
x
SP
Mute
x
x
0
Mute
Reference Frequency Selection
The “LO In” and “LO Out” pins form a reference oscillator
set by the Mode Control Register. Operation of the Control
Register is explained in Figures 115 through 119.
2
2
when connected to an external parallel–resonant crystal. The
reference oscillator is also the second local oscillator for the
RF Receiver. Figure 114 shows the relationship between
different crystal frequencies and reference frequencies for
Figure 116. Mute and Disable Control Bit Descriptions
ALC Disable
1
0
Automatic Level Control Disabled
Normal Operation
cordless phone applications in various countries. “LO In”
2
T Limiter Disable
x
1
0
T Limiter Disabled
x
may also serve as an input for an externally generated
reference signal which is ac–coupled. The switched
capacitor filter 6–bit programmable counter must be
programmed for the crystal frequency that is selected since
this clock is derived from the crystal frequency and must be
held constant regardless of the crystal that is selected. The
actual switched capacitor clock divider ratio is twice the
programmed divider ratio due to the a fixed divide by 2.0 after
the programmable counter. The scrambler mixer modulation
frequency is the switched capacitor clock divided by 40 for
the MC13110A/B.
Normal Operation
Clock Disable
(MC13110A/111A)
1
0
MPU Clock Output Disabled
Normal Operation
Clock Disable
(MC13110B/111B)
1
0
Don’t Care
Normal Operation
T Mute
x
1
0
Transmit Channel Muted
Normal Operation
R Mute
x
1
0
Receive Channel Muted
Normal Operation
SP Mute
1
0
Speaker Amp Muted
Normal Operation
Mode Control Register
The power saving modes; mutes, disables, volume
control, and microprocessor clock output frequency are all
47
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Power Saving Operating Modes
Figure 118. Circuit Blocks Powered
During Power Saving Modes
When the MC13110A/B or MC13111A/B are used in a
handset, it is important to conserve power in order to prolong
battery life. There are five modes of operation for the
MC13110A/MC13111A
MC13110B/MC13111B
MC13110A/MC13111A; Active, R , Standby, Interrupt, and
x
Inactive. The MC13110B/MC13111B has three modes of
operation. They are Active, R , and Standby. In the Active
mode, all circuit blocks are powered. In the R mode, all
x
Active
R
Standby Inactive
1, 2
x
Circuit Blocks
x
1
X
“PLL V ” Regulated
ref
Voltage
X
X
X
circuitry is powered down except for those circuit sections
needed to receive a transmission from the base. In the
Standby and Interrupt Modes, all circuitry is powered down
except for the circuitry needed to provide the clock output for
the microprocessor. In the Inactive Mode, all circuitry is
powered down except the MPU serial interface. Latch
memory is maintained in all modes. All mode functions are
the same for the MC13110B/MC13111B, except that there is
no Inactive mode. With the B” version the MPU Clock is
always running so that there can never be a register reset if
the memory is disturbed. Figure 118 shows the control
register bit values for selection of each power saving mode
and Figure 118 shows the circuit blocks which are powered in
each of these operating modes.
2
X
MPU Serial Interface
2nd LO Oscillator
MPU Clock Output
X
X
X
X
X
X
X
X
X
X
X
RF Receiver and 1st LO
VCO
R PLL
x
X
X
X
X
X
X
X
X
X
X
Carrier Detect
Data Amp
Low Battery Detect
T PLL
x
R and T Audio Paths
x
x
NOTES: 15. In Standby and Inactive Modes, “PLL V ” remains powered
ref
Figure 117. Power Saving Mode Selection
but is not regulated. It will fluctuate with V
.
CC
“CD Out/
Hardware
Interrupt” Pin
Power
Saving
Mode
16. There is no Inactive mode for MC13110B/MC13111B.
Power Saving Application – Option 1 (MC13110B and
MC13111B Only)
Stdby Mode Bit
R
Mode Bit
x
MC13110A/MC13111A
When the handset is in standby, power can be reduced by
entering a “low power” mode and periodically switching to
“sniff” mode to check for incoming calls. Figure 119. shows
an application where the “Clk Out” pin provides the clock for
the MPU. In this application, the 2nd LO and MPU clock run
continuously. The MPU maintains control at all times and sets
the timing for transitions into the “sniff” mode. Power is saved
in the low power mode by putting the MC13110B/MC13111B
into its “Standby” mode. Only the 2nd LO and MPU clock
divider are active. By programming the MPU clock divider to
a large divide value of 20, 80, or 312.5 this will reduce the
MPU clock frequency and save power in the MPU.
0
0
1
1
0
1
0
1
X
X
X
Active
R
x
Standby
Inactive
1 or High
Impedance
1
1
0
Interrupt
MC13110B/MC13111B [Note 14]
0
0
1
1
0
1
X
1
X
X
X
0
Active
R
x
Standby
Interrupt
NOTES: 13. “X” is a don’t care
14. MPU Clock Out is ”Always On”
48
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
An external timing circuit should be used to initiate the
turn–on sequence. The “CD Out” pin has a dual function. In
Power Saving Application – Option 2 (MC13110A and
MC13111A Only)
the Active and R modes it performs the carrier detect
x
In some handset applications it may be desirable to power
down all circuitry including the microprocessor (MPU). First
put the MC13110A/MC13111A into the Inactive mode. This
turns off the MPU Clock Output (see Figure 120) and
disables the microprocessor. Once a command is given to
switch the IC into an “Inactive” mode, the MPU Clock output
will remain active for a minimum of one reference counter
cycle (about 200 µs) and up to a maximum of two reference
counter cycles (about 400 µs). This is performed in order to
give the MPU adequate time to power down.
function. In the Standby and Inactive modes the carrier
detect circuit is disabled and the “CD Out” pin is in a “High”
state, because of an external pull–up resistor. In the Inactive
mode, the “CD Out” pin is the input for the hardware interrupt
function. When the “CD Out” pin is pulled “low”, by the
external timing circuit, the IC switches from the Inactive to the
Interrupt mode. Thereby turning on the MPU Clock Output.
The MPU can then resume control of the IC. The “CD Out”
pin must remain low until the MPU changes the operating
mode from Interrupt to Standby, Active, or R modes.
x
Figure 119. Power Saving Application – Option 1
MC13110B
MC13111B
Clk Out
Clk In
Microprocessor
Timer
SPI Port
SPI Port
MPU Clk
Divider
LO Out
2
LO In
2
“Low Power”
“Sniff”
Mode
Standby Mode
R
Mode
x
MPU Timer
MPU
Clock
Out
32.8, 128 or 512 kHz
4.0 MHz
49
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 120. Power Saving Application – Option 2 (MC13110A/MC13111A Only)
MC13110A/
MC13111A
Clk Out
Clk In
SPI Port
Interrupt
Microprocessor
SPI Port
MPU Clk
Divider
LO Out
2
LO In
2
V
CC
CD Out/
HW Interrupt
External Timer
Mode
Active/R
Inactive
MPU Initiates
Interrupt
Standby/R /Active
x
x
MPU Initiates
Mode Change
Inactive Mode
EN
External Timer
Pulls Pin Low
CD Out Low
CD Out/Hardware Interrupt
Timer Output
Disabled
CD Turns Off
MPU Clock Out
Delay after MPU selects Inactive Mode to when CD turns off.
“MPU Clock Out” remains active for a minimum of one count of reference
counter after “CD Out/Hardware Interrupt” pin goes high
MPU “Clk Out” Divider Programming
The “Clk Out” signal is derived from the second local
oscillator. It can be used to drive a microprocessor (MPU) clock
input. This will eliminate the need for a separate crystal to drive
the MPU, thus reducing system cost. Figure 121 shows the
relationship between the second LO crystal frequency and the
clock output for each divide value. Figure 122 shows the “Clk
Out” register bit values. With a 10.24 MHz crystal, the divide by
312.5 gives the same clock frequency as a clock crystal and
allows the MPU to display the time on a LCD display without
additional external components.
Figure 121. Clock Output Values
Clock Output Divider
Crystal
Frequency
2
2.5
3
4
5
20
80
312.5
10.24 MHz
11.15 MHz
12.00 MHz
5.120 MHz
5.575 MHz
6.000 MHz
4.096 MHz
4.460 MHz
4.800 MHz
3.413 MHz
3.717 MHz
4.000 MHz
2.560 MHz
2.788 MHz
3.000 MHz
2.048 MHz
2.230 MHz
2.400 MHz
512 kHz
557 kHz
600 kHz
128 kHz
139 kHz
150 kHz
32.768 kHz
35.680 kHz
38.400 kHz
50
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
transition between one clock divider value and another is
Figure 122. Clock Output Divider
“smooth” (i.e. there will be no narrow clock pulses to disturb
the MPU).
MPU Clk
Bit #2
MPU Clk
Bit #1
MPU Clk
Bit #0
Clk Out
Divider Value
MPU “Clk Out” Radiated Noise on Circuit Board
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
The clock line running between the MC13110A/B or
MC13111A/B and the microprocessor has the potential to
radiate noise. Problems in the system can occur, especially if
the clock is a square wave digital signal with large high
frequency harmonics. In order to minimize the radiated noise,
a 1000 Ω resistor is included on–chip in series with the “Clk
Out” output driver. A small capacitor or inductor with a
capacitor can be connected to the “Clk Out” line on the PCB
to form a one or two pole low pass filter. This filter should
significantly reduce noise radiated by attenuating the high
frequency harmonics on the signal line. The filter can also be
used to attenuate the signal level so that it is only as large as
required by the MPU clock input. To further reduce radiated
noise, the PCB signal trace length should be kept to a
minimum.
4
5
2.5
20
80
312.5
MPU “Clk Out” Power–Up Default Divider Value
The power–up default divider value is “divide by 5”. This
provides a MPU clock of about 2.0 MHz after initial
power–up. The reason for choosing a relatively low clock
frequency at initial power–up is because some
microprocessors operate using a 3.0 V power supply and
have a maximum clock frequency of 2.0 MHz. After initial
power–up, the MPU can change the clock divider value and
set the clock to the desired operating frequency. Special care
was taken in the design of the clock divider to insure that the
Volume Control Programming
The volume control adjustable gain block can be
programmed in 2 dB gain steps from –14 dB to +16 dB. The
power–up default value for the MC13110A/B and
MC13111A/B is 0 dB. (see Figure 123)
Figure 123. Volume Control
Volume Control
Bit #3
Volume Control
Bit #2
Volume Control
Volume Control
Volume
Control #
Gain/Attenuation
Amount
Bit #1
Bit #0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–14 dB
–12 dB
–10 dB
–8 dB
–6 dB
–4 dB
–2 dB
0 dB
2
3
4
5
6
7
8
2 dB
9
4 dB
10
11
12
13
14
15
6 dB
8 dB
10 dB
12 dB
14 dB
16 dB
51
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Gain Control Register
The gain control register contains bits which control the T
Voltage Gain, R Voltage Gain, and Carrier Detect threshold.
x
Operation of these latch bits are explained in Figures 124,
125 and 126.
than the nominal power–up default, is desired, it can be
programmed through the MPU interface. Alternately, these
programmable gain blocks can be used during final test of the
telephone to electronically adjust for gain tolerances in the
x
telephone system (see Figure 125). In this case, the T and
x
T and R Gain Programming
x
x
R gain register values should be stored in ROM during final
x
test so that they can be reloaded each time the IC is powered
up.
The T and R audio signal paths each have a
x
x
programmable gain block. If a T or R voltage gain, other
x
x
Figure 124. Gain Control Latch Bits
0
5–b T Gain Control
x
5–b R Gain Control
5–b CD Threshold Control
x
Figure 125. T and R Gain Control
x
x
Gain Control
Bit #4
Gain Control
Gain Control
Bit #2
Gain Control
Bit #1
Gain Control
Bit #0
Gain
Control #
Gain/Attenuation
Bit #3
Amount
–9 dB
–9 dB
–8 dB
–7 dB
–6 dB
–5 dB
–4 dB
–3 dB
–2 dB
–1 dB
0 dB
–
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
–
–
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
–
–
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
–
–
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
–
–
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–
<6
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
>25
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
7 dB
8 dB
9 dB
10 dB
10 dB
52
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Carrier Detect Threshold Programming
The “CD Out” pin gives an indication to the microprocessor
if a carrier signal is present on the selected channel. The
nominal value and tolerance of the carrier detect threshold is
given in the carrier detect specification section of this
document. If a different carrier detect threshold value is
desired, it can be programmed through the MPU interface as
shown in Figure 126 below. Alternately, the carrier detect
threshold can be electronically adjusted during final test of
the telephone to reduce the tolerance of the carrier detect
threshold. This is done by measuring the threshold and then
by adjusting the threshold through the MPU interface. In this
case, it is necessary to store the carrier detect register value
in ROM so that the CD register can be reloaded each time the
combo IC is powered up. If a preamp is used before the first
mixer it may be desirable to scale the carrier detect range by
connecting an external resistor from the “RSSI” pin to
ground. The internal resistor is 187 kΩ.
Figure 126. Carrier Detect Threshold Control
CD
Bit #4
CD
Bit #3
CD
Bit #2
CD
Bit #1
CD
Bit #0
CD
Control #
Carrier Detect
Threshold
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
–20 dB
–19 dB
–18 dB
–17 dB
–16 dB
–15 dB
–14 dB
–13 dB
–12 dB
–11 dB
–10 dB
–9 dB
–8 dB
–7 dB
–6 dB
–5 dB
–4 dB
–3 dB
–2 dB
–1 dB
0 dB
0
1
0
2
0
3
1
4
1
5
1
6
1
7
0
8
0
9
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
1
1
1
0
0
0
0
1
1
1 dB
1
2 dB
1
3 dB
0
4 dB
0
5 dB
0
6 dB
0
7 dB
1
8 dB
1
9 dB
1
10 dB
11 dB
1
53
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Clock Divider/Voltage Adjust Register
This register controls the divider value for the
programmable switched capacitor filter clock divider, the low
battery detect threshold select, the voltage reference adjust,
and the scrambler bypass mode (MC13110A/B only).
The non–programmable threshold mode is only available in
the 52 QFP package. In this mode, there are two low battery
detect comparators and the threshold values are set by
external resistor dividers which are connected to the REF1
and REF2 pins. In the programmable threshold mode,
several different threshold levels may be selected through
the “Low Battery Detect Threshold Register” as shown in Figure
128. The power–on default value for this register is <0,0,0> and
is the non–programmable mode. Figure 130 shows equivalent
schematics for the programmable and non–programmable
operating modes.
Operation is explained in Figures 127 through 134. The T
and R Audio bits are don’t cares for either the MC13111A or
x
x
the MC13111B device. However, for the MC13110A/B, these
bits are defined. Figure 129 describes the operation. Note the
power–up default bit is set to <0>, which is the scrambler
bypass mode.
Low Battery Detect
The low battery detect circuit can be operated in
programmable and non–programmable threshold modes.
Figure 127. Clock Divider/Voltage Adjust Latch Bits
3–b Low Battery
Detect Threshold Select
4–b Voltage
Reference Adjust
T
Sbl
R
Sbl
6–b Switched
Capacitor Filter Clock Counter Latch
x
x
0
0
MSB
LSB
MSB
LSB
LSB
Bypass
Bypass
(MC13110A/B)
3–b Low Battery
Detect Threshold Select
4–b Voltage
Reference Adjust
6–b Switched
Capacitor Filter Clock Counter Latch
MSB
LSB
0
0
MSB
(MC13111A/B)
Figure 128. Low Battery Detect Threshold Selection
Low Battery
Low Battery
Low Battery
Detect
Nominal Low
Battery Detect
Threshold Value (V)
Detect
Detect
Threshold
Select Bit #2
Threshold
Select Bit #1
Threshold
Select Bit #0
Select #
Operating Mode
Non–Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
N/A
2.850
2.938
3.025
3.200
3.288
3.375
3.463
NOTE: 17. Nominal Threshold Value is before electronic adjustment.
Figure 129. MC13110A/B Bypass Mode Bit Description
(MC13110A/B Only)
T Scrambler
x
1
T Scrambler Post–Mixer LPF and Mixer Bypassed
x
Bypass
0
1
Normal Operation with T Scrambler
x
R Scrambler
x
R Scrambler Post–Mixer LPF and Mixer Bypassed
x
Bypass
0
Normal Operation R Scrambler
x
54
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 130. Low Battery Detect Equivalent Schematics
Ref2
BD2 Out
50
16
Ref 1
BD1 Out
51
14
VB
V
ref
52
Non–Programmable Threshold Mode: 52–QFP Package
V
Audio
V
Audio
CC
CC
21
23
BD Out
14
BD2 Out
16
VB
47
VB
52
V
V
ref
ref
Programmable Threshold Mode: 48–LQFP Package
Programmable Threshold Mode: 52–QFP Package
55
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Voltage Reference Adjustment
An internal 1.5 V bandgap voltage reference provides the
voltage reference for the “BD Out” and “BD Out” low battery
Switched Capacitor Filter Clock Programming
A block diagram of the switched capacitor filter clock
divider is show in Figure 132. There is a fixed divide by 2 after
the programmable divider. The switched capacitor filter clock
value is given by the following equation;
1
2
detect circuits, the “PLL V ” voltage regulator, the “V ”
ref
B
reference, and all internal analog ground references. The
initial tolerance of the bandgap voltage reference is ±6%. The
tolerance of the internal reference voltage can be improved to
±1.5% through MPU serial interface programming. During
final test of the telephone, the battery detect threshold is
measured. Then, the internal reference voltage value is
adjusted electronically through the MPU serial interface to
achieve the desired accuracy level. The voltage reference
register value should be stored in ROM during final test so
that it can be reloaded each time the MC13110A/B or
MC13111A/B is powered up (see Figure 131).
(SCF Clock) = F(2nd LO) / (SCF Divider Value * 2).
The scrambler modulation clock frequency (SMCF) is
proportional to the SCF clock. The following equation defines
its value:
SMCF = (SCF Clock)/40
The SCF divider should be set to a value which brings the
SCF Clock as close to 165.16 kHz as possible. This is based
on the 2nd LO frequency which is chosen in Figure 114.
Figure 131. Bandgap Voltage Reference Adjustment
Figure 132. SCF Clock Divider Circuit
V
Adj.
V
Adj.
V
Adj.
V
Adj.
V
Adj.
#
V
ref
Adj.
ref
ref
ref
ref
ref
Bit #3
Bit #2
Bit #1
Bit #0
Amount
–9.0%
–7.8%
–6.6%
–5.4%
–4.2%
–3.0%
–1.8%
–0.6%
+0.6 %
+1.8 %
+3.0 %
+4.2 %
+5.4 %
+6.6 %
+7.8 %
+9.0 %
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LO In
2
SCF
Clock
6–b
Divide
By 2.0
2nd LO
Crystal
Programmable
SCF Clock Counter
2
3
LO Out
2
4
5
Divide
By 40
MC13110A/B
only
6
Scrambler
Modulation
Clock
7
8
9
Corner Frequency Programming for MC13110A/B and
MC13111A/B
10
11
12
13
14
15
Four different corner frequencies may be selected by
programming the SCF Clock divider as shown in Figures 133
and 134. It is important to note, that all filter corner
frequencies will change proportionately with the SCF Clock
Frequency and Scrambler Modulation Frequency. The
power–up default SCF Clock divider value is 31.
Figure 133. Corner Frequency Programming for 10.240 MHz 2nd LO
MC13110A/B
MC13111A/B
Scrambler
Total
Divide
Value
R
Upper
T
Upper
Scrambler
Lower Corner
Frequency (Hz) Frequency (kHz)
Scrambler
Upper Corner
Modulation
Frequency
(Clk/40) (kHz)
x
x
SCF Clock
Divider
SCF Clock
Freq. (kHz)
Corner
Corner
Frequency (kHz) Frequency (kHz)
29
30
31
32
58
60
62
64
176.55
170.67
165.16
160.00
4.147
4.008
3.879
3.758
3.955
3.823
3.700
3.584
4.414
4.267
4.129
4.000
267.2
258.3
250.0
242.2
3.902
3.772
3.650
3.536
NOTE: 18. All filter corner frequencies have a tolerance of ±3%.
19. R and T Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
x
x
56
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 134. Corner Frequency Programming for 11.15 MHz 2nd LO
MC13110A/B
MC13111A/B
Scrambler
Total
Divide
Value
R
Upper
T
Upper
Scrambler
Lower Corner
Frequency (Hz)
Scrambler
Upper Corner
Frequency (kHz)
Modulation
Frequency
(Clk/40) (kHz)
x
x
SCF Clock
Divider
SCF Clock
Freq. (kHz)
Corner
Corner
Frequency (kHz) Frequency (kHz)
32
33
34
35
64
66
68
70
174.22
168.94
163.97
159.29
4.092
3.968
3.851
3.741
3.903
3.785
3.673
3.568
4.355
4.223
4.099
3.982
263.7
255.7
248.2
241.1
3.850
3.733
3.624
3.520
NOTES: 20. All filter corner frequencies have a tolerance of ±3%.
21.
R
and T Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass
x
x
Figure 135. Auxiliary Register Latch Bits
4–b 1st LO Capacitor
Selection
0
0
0
0
0
0
0
0
0
MSB 3–b Test Mode LSB
MSB
LSB
Figure 136. Digital Test Mode Description
Counter Under Test or
Test Mode Option
“T
V
”
CO
x
Input Signal
>200 mVpp
0 to 2.5 V
0 to 2.5 V
0 to 2.5 V
0 to 2.5 V
N/A
TM #
TM 2 TM 1 TM 0
“Clk Out” Output Expected
0
1
2
3
4
5
6
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Normal Operation
R Counter
–
Input Frequency/R Counter Value
x
x
T Counter
x
Input Frequency/T Counter Value
x
Reference Counter + Divide by 4/25
SC Counter
Input Frequency/Reference Counter Value * 100
Input Frequency/SC Counter Value * 2
ALC Gain = 10 Option
ALC Gain = 25 Option
N/A
N/A
N/A
Auxiliary Register
range is not large enough to accommodate this large
frequency span. An internal capacitor with 15 programmable
capacitor values can be used to cover the 25 channel
frequency span without the need to add external capacitors
and switches. The programmable internal capacitor can also
be used to eliminate the need to use an external variable
capacitor to adjust the 1st LO center frequency during
telephone assembly. Figure 32 shows the schematic of the
1st LO tank circuit. Figure 137 shows the register control bit
values.
The internal programmable capacitor is composed of a
matrix bank of capacitors that are switched in as desired.
Programmable capacitor values between about 0 and 16 pF
can be selected in steps of approximately 1.1 pF. The internal
parallel resistance values in the table can be used to
calculate the quality factor (Q) of the oscillator if the Q of the
external inductor is known. The temperature coefficient of the
varactor is 0.08%/°C. The temperature coefficient of the
internal programmable capacitor is negligible. Tolerance on
the varactor and programmable capacitor values is ±15%.
The auxiliary register contains a 4–bit First LO Capacitor
Selection latch and a 3–bit Test Mode latch. Operation of
these latch bits are explained in Figures 135, 136 and 137.
Test Modes
Test modes are be selected through the 3–bit Test Mode
Register. In test mode, the “T VCO” input pin is multiplexed
x
to the input of the counter under test. The output of the
counter under test is multiplexed to the “Clk Out” output pin
so that each counter can be individually tested. Make sure
test mode bits are set to “0’s” for normal operation. Test
mode operation is described in Figure 136. During normal
operation, the “T VCO” input can be a minimum of 200 mVpp
x
at 80 MHz and should be AC coupled. Input signals should be
standard logic levels of 0 to 2.5 V and a maximum frequency of
16 MHz.
First Local Oscillator Programmable Capacitor Selection
There is a very large frequency difference between the
minimum and maximum channel frequencies in the 25
Channel U.S. standard. The internal varactor adjustment
57
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Figure 137. First Local Oscillator Internal Capacitor Selection
Equivalent
Internal
Parallel
Equivalent
Internal
Parallel
Internal
Programmable
Capacitor
1st LO
Cap.
Bit 3
1st LO
Cap.
Bit 2
1st LO
Cap.
Bit 1
1st LO
Cap.
Bit 0
1st LO
Cap.
Select
Varactor
Value over
0.3 to 2.5 V (pF)
Resistance
at 40 MHz (kΩ)
Resistance
at 51 MHz (kΩ)
Value (pF)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.0
0.6
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
9.7 to 5.8
1200
79.3
131
736
48.8
80.8
19.3
20.8
41
2
1.7
3
2.8
31.4
33.8
66.6
49.9
40.7
27.1
21.6
20.5
18.6
17.2
15.8
15.3
14.2
4
3.9
5
4.9
6
6.0
30.7
25.1
16.7
13.3
12.6
11.5
10.6
9.7
7
7.1
8
8.2
9
9.4
10
11
12
13
14
15
10.5
11.6
12.7
13.8
14.9
16.0
9.4
8.7
58
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
OTHER APPLICATIONS INFORMATION
The “PLL V ” pin is the internal supply voltage for the R
PCB Board Lay–Out Considerations
ref
x
and T PLL’s. It is regulated to a nominal 2.5 V. The “V
x
The ideal printed circuit board (PCB) lay out would be
double–sided with a full ground plane on one side. The
ground plane would be divided into separate sections to
prevent any audio signal from feeding into the first local
oscillator via the ground plane. Leaded components, can
likewise, be inserted on the ground plane side to improve
shielding and isolation from the circuit side of the PCB. The
opposite side of the PCB is typically the circuit side. It has the
interconnect traces and surface mount components. In cases
where cost allows, it may be beneficial to use multi–layer
boards to further improve isolation of components and
sensitive sections (i.e. RF and audio). For the CT–0 band, it
is also permissible to use single–sided PC layouts, but with
continuous full ground fill in and around the components.
The proper placement of certain components specified in
the application circuit may be very critical. In a lay–out
design, these components should be placed before the other
less critical components are inserted. It is also imperative
that all RF paths be kept as short as possible. Finally, the
MC13110A/B and MC13111A/B ground pins should be tied to
CC
Audio” pin is the supply voltage for the internal voltage
regulator. Two capacitors with 10 µF and 0.01 µF values must
be connected to the “PLL V ” pin to filter and stabilize this
ref
regulated voltage. The “PLL V ” pin may be used to power
ref
other IC’s as long as the total external load current does not
exceed 1.0 mA. The tolerance of the regulated voltage is
initially ±8.0%, but is improved to ±4.0% after the internal
Bandgap voltage reference is adjusted electronically through
the MPU serial interface. The voltage regulator is turned off in
the Standby and Inactive modes to reduce current drain. In
these modes, the “PLL V f” pin is internally connected to the
re
“V
Audio” pin (i.e., the power supply voltage is maintained
but is now unregulated).
CC
It is important to note that the momentary drop in voltage
below 2.5 V during this transition may affect initial PLL lock
times and also may trigger the reset. To prevent this, the PLL
V
capacitor described above should be kept the same or
larger than the VB capacitor, say 10 µf as shown in the
ref
evaluation and application diagrams.
ground at the pins and V
decoupling to ground as close to the IC as possible. In mixed
mode systems where digital and RF/Analog circuitry are
pins should have adequate
CC
DC Coupling
Choosing the right coupling capacitors for the compander
is also critical. The coupling capacitors will have an affect on
the audio distortion, especially at lower audio frequencies. A
useful capacitor range for the compander timing capacitors is
0.1 µf to 1.0 µf. It is advised to keep the compander
capacitors the same value in both the handset and baseset
applications.
All other dc coupling capacitors in the audio section will
form high pass filters. The designer should choose the
overall cut off frequency (–3.0 dB) to be around 200 Hz.
Designing for lower cut off frequencies may add unnecessary
cost and capacitor size to the design, while selecting too high
of a cut off frequency may affect audio quality. It is not
necessary or advised to design each audio coupling
capacitors for the same cut off frequency. Design for the
overall system cut off frequency. (Note: Do not expect the
application, evaluation, nor production test schematics to
necessarily be the correct capacitor selections.) The goals of
these boards may be different than the systems approach a
designer must consider.
present, the V
and V buses need to be ac–decoupled
CC
EE
and isolated from each other. The design must also take
great caution to avoid interference with low level analog
circuits. The receiver can be particularly susceptible to
interference as they respond to signals of only a few
microvolts. Again, be sure to keep the dc supply lines for the
digital and analog portions separate. Avoid ground paths
carrying common digital and analog currents, as well.
Component Selection
The evaluation circuit schematics specify particular
components that were used to achieve the results shown in
the typical curves and tables, but alternate components
should give similar results. The MC13110A/B and
MC13111A /B IC are capable of matching the sensitivity, IMD,
adjacent channel rejection, and other performance criteria of
a multi–chip analog cordless telephone system. For the most
part, the same external components are used as in the
multi–chip solution.
For the supply pins (V
Audio and V
RF) choose a 10
CC
CC
VB and PLL V
ref
µf in parallel with a high quality 0.01 µf capacitor. Separation
of the these two supply planes is essential, too. This is to
prevent interference between the RF and audio sections. It is
always a good design practice to add additional coupling on
each supply plane to ground as well.
The IF limiter capacitors are recommended to be 0.1 µf.
Smaller values lower the gain of the limiter stage. The
–3.0 dB limiting sensitivity and SINAD may be adversely
affected.
VB is an internally generated bandgap voltage. It functions
as an ac reference point for the operational amplifiers in the
audio section as well as for the battery detect circuitry. This
pin needs to be sufficiently filtered to reduce noise and
prevent crosstalk between R audio to T audio signal paths.
x
x
A practical capacitor range to choose that will minimize
crosstalk and noise relative to start up time is 0.5 µf to 10 µf.
The start time for a 0.5 µf capacitor is approximately 5.0 ms,
while a 10µf capacitor is about 10 ms.
59
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX A
60
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX A
Figure 139. Evaluation Board Bill of Materials for U.S. and French Application
USA Application Handset
French Application Base
RF
RF Crystal
RF Ceramic
(50 Ω)
(50 Ω)
(50 Ω)
Comp. Number
RF Matched
RF Matched
INPUT MATCHING
T1
n.m.
Toko 1:5
n.m.
n.m.
Toko 1:5
292GNS–765A0
292GNS–765A0
C38
C39
0.01
0.01
n.m.
n.m.
0.01
0.01
0.01
0.01
n.m.
n.m.
10.7 MHz FILTER
F1
Ceramic
Ceramic
Crystal
1.2 k
Ceramic
Ceramic
R37
R34
0
0
0
0
360
360
3.01 k
360
360
450 kHz FILTER
F2
4 Element
Murata E
4 Element
Murata E
4 Element
Murata G
4 Element
Murata G
4 Element
Murata G
DEMODULATOR
L1
Q Coil Toko
7MCS–8128Z
Q Coil Toko
7MCS–8128Z
Ceramic Murata
CDBM 450C34
Ceramic Murata
CDBM 450C34
Ceramic Murata
CDBM 450C34
R28
C28
22.1 k
10 p
22.1 k
10 p
2.7 k
2.7 k
2.7 k
390 p
390 p
390 p
OSCILLATOR
Xtal
10.24
10.24
11.15
11.15
11.15
C1 = 10 p
C1 = 10 p
C1 = 18 p
C1 = 18 p
C1 = 18 p
C2
C1
18 p
18 p
33 p
33 p
33 p
5–25 p
5–25 p
15 p + 5–25 p
15 p + 5–25 p
15 p + 5–25 p
FIRST LO
L2
0.47
0.47
0.22
0.22
0.22
Toko T1370
Toko T1370
Toko T1368
Toko T1368
Toko T1368
C40 HS/BS
HS: 27 pF
BS: 22 pF
HS: 27 pF
BS: 22 pF
BS: 100 p
HS: 68 pF
BS: 100 p
HS: 68 pF
BS: 100 p
HS: 68 pF
LOOP FILTER HANDSET/BASESET
R4a
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
R4b
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
HS: 0
BS: 0
C4
HS: 6800
BS: 8200
HS: 6800
BS: 8200
HS: 8600
BS: 6800
HS: 8600
BS: 6800
HS: 8600
BS: 6800
R42a
R42b
C42a
C42b
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 100 k
BS: 100 k
HS: 22 k
BS: 18 k
HS: 22 k
BS: 18 k
HS: 18 k
BS: 22 k
HS: 18 k
BS: 22 k
HS: 18 k
BS: 22 k
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 1000
BS: 1000
HS: 0.068
BS: 0.082
HS: 0.068
BS: 0.082
HS: 0.082
BS: 0.068
HS: 0.082
BS: 0.068
HS: 0.082
BS: 0.068
61
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX B
APPLICATIONS CIRCUIT
C 3 0
6 8 0 0
8 1 2 8 Z
T 2
0 . 1 0
1 0 k
R 2 0
0 . 1 0
C 7 4
C 7 3
C 1 9
0 . 1
62
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX B
Figure 140. Basic Cordless Telephone Transceiver Application Circuit (continued)
V
CC
+
C56
0.1
C57
2.2
µ
F
Batt1
L6
56
µ
H
Gnd
VR
x
V+
V–
V
–RF
CC
CC
C55
0.22
+
C54
10
C53
0.01
µ
F
Gnd
V
–A
+
C58
10
Gnd
µ
F
Gnd
C59
180
C49
T VT
x
2.0
L4
0.22
T
x
Audio
µ
H
1
2
C48
120
2109
VR2
R54
U5
100 k
C46
36
C47
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Variable
Reactance
Output
RF Osc
RF Osc
R53
68 k
C37
6800
36
C60
Decoupling
T VCO
x
0.1
µ
F
R50
Modulator
Input
RF
Output
V
CC
R46
220 k
C45
10
R51
1.5 k
Gnd
Mic Amp
Output
Tr 2
Base
C38
8.0
R49 100
110 k
R45
110
Mic Amp
Input
Tr 2
Emitter
R37
22 k
R47
75 k
C44
Tr 2
Collector
Gnd
0.22
L5
µ
H
C50
0.022
4700
Tr 1
Emitter
V
CC
C43
51
R39
110 k
Tr 1
Base
Tr 1
Collector
R44
110
T
Data
x
C40
P1
S1
S2
C51
C52
0.022
T3
10
Cx
P2
P3
C41
51
7.5
R41
27 k
51
Ω
R43
110
T RF–In
x
13630
R42
91 k
0.022
63
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
APPENDIX C – MEASUREMENT OF COMPANDER ATTACK/DECAY TIME
This measurement definition is based on EIA/CCITT
Expander Attack
recommendations.
For a 6.0 dB step up at the input, attack time is defined as
the time for the output to settle to 0.57X of the final steady
state value.
Compressor Attack Time
For a 12 dB step up at the input, attack time is defined as
the time for the output to settle to 1.5X of the final steady state
value.
Expander Decay
For a 6.0 dB step down at the input, decay time is defined
as the time for the output to settle to 1.5X of the final steady
state value.
Compressor Decay Time
For a 12 dB step down at the input, decay time is defined
as the time for the input to settle to 0.75X of the final steady
state value.
6.0 dB
Input
12 dB
0 mV
Input
0 mV
Attack Time
Decay Time
Attack Time
Decay Time
0.57X Final Value
1.5X Final Value
1.5X Final Value
Output
Output
0 mV
0.75X Final Value
0 mV
64
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
OUTLINE DIMENSIONS
FB SUFFIX
PLASTIC PACKAGE
CASE 848B–04
(QFP–52)
ISSUE C
B
B
L
39
27
26
40
–A–, –B–, –D–
DETAIL A
DETAIL A
–B–
–A–
L
F
J
N
14
13
52
1
BASE METAL
D
–D–
M
S
S
B
0.02 (0.008)
C
A–B
D
M
S
S
S
0.20 (0.008)
H
A–B
D
D
SECTION B–B
0.05 (0.002) A–B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
V
M
S
0.20 (0.008)
C
A–B
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.
DETAIL C
M
C
E
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
DATUM
–H–
PLANE
0.10 (0.004)
H
SEATING
PLANE
–C–
M
G
MILLIMETERS
INCHES
DIM
A
B
C
D
E
MIN
9.90
9.90
2.10
0.22
2.00
0.22
MAX
10.10
10.10
2.45
0.38
2.10
MIN
MAX
0.398
0.398
0.096
0.015
0.083
0.013
0.390
0.390
0.083
0.009
0.079
0.009
U
F
0.33
G
H
J
K
L
0.65 BSC
0.026 BSC
–––
0.13
0.65
0.25
0.23
0.95
–––
0.005
0.026
0.010
0.009
0.037
R
Q
7.80 REF
0.307 REF
M
N
Q
R
S
T
U
V
5
0.13
0
0.13
12.95
0.13
0
12.95
0.35
1.6 REF
10
0.17
7
0.30
13.45
–––
–––
13.45
0.45
5
0.005
0
0.005
0.510
0.005
0
0.510
0.014
0.063 REF
10
0.007
7
0.012
0.530
–––
–––
0.530
0.018
K
T
W
X
DETAIL C
W
X
65
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
OUTLINE DIMENSIONS
FTA SUFFIX
PLASTIC PACKAGE
CASE 932–02
(LQFP–48)
ISSUE D
4X
NOTES:
0.200 (0.008) AB T–U
Z
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2
3
CONTROLLING DIMENSION: MILLIMETER.
DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL Y
P
9
A
A1
48
37
4
5
6
DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
1
36
DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014).
–T–
B1
–U–
V1
B
V
7
AE
AE
8
9
MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
12
25
MILLIMETERS
MIN MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
13
24
DIM
A
A1
B
B1
C
D
E
F
G
H
J
–Z–
S1
–T–, –U–, –Z–
1.400
1.600
0.270
1.450
0.230
0.055
0.063
0.011
0.057
0.009
S
0.170
1.350
0.170
0.007
0.053
0.007
DETAIL Y
4X
0.200 (0.008) AC T–U
Z
0.500 BASIC
0.020 BASIC
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
K
M
N
P
12 REF
12 REF
0.080 (0.003) AC
0.090
0.160
0.004
0.006
G
0.250 BASIC
0.010 BASIC
Q
R
S
S1
V
V1
W
X
1
5
1
5
0.150
9.000 BSC
0.250
0.006
0.354 BSC
0.010
–AB–
–AC–
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
AD
M
BASE METAL
TOP & BOTTOM
R
N
GAUGE PLANE
J
0.250 (0.010)
E
C
H
F
D
M
S
S
0.080 (0.003)
AC T–U
Z
SECTION AE–AE
W
Q
K
DETAIL AD
X
66
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
67
MOTOROLA ANALOG IC DEVICE DATA
MC13110A/B MC13111A/B
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