MC14029BCLD [MOTOROLA]
Binary Counter, 4000/14000/40000 Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDIP16, 620-09;
| 型号： | MC14029BCLD |
| 厂家： | 
MOTOROLA |
| 描述： | Binary Counter, 4000/14000/40000 Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDIP16, 620-09 计数器 |
| 文件： | 总8页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14029B Binary/Decade up/down counter is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. The counter consists of type D flip–flop stages with a
gating structure to provide toggle flip–flop capability. The counter can be
used in either Binary or BCD operation. This complementary MOS counter
finds primary use in up/down and difference counting and frequency
synthesizer applications where low power dissipation and/or high noise
immunity is desired. It is also useful in A/D and D/A conversion and for
magnitude and sign generation.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
•
•
Asynchronous Preset Enable Operation
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin for Pin Replacement for CD4029B
T
A
= – 55° to 125°C for all packages.
•
PIN ASSIGNMENT
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
PE
Q3
P3
P0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
CLK
Q2
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
l , l
P2
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
C
P1
in
Q0
out
Q1
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
C
U/D
B/D
T
stg
– 65 to + 150
260
V
T
L
Lead Temperature (8–Second Soldering)
C
SS
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
Preset
Enable
Carry In
Up/Down
Action
No Count
Count Up
Count Down
Preset
1
X
1
0
X
0
0
0
1
0
0
X
X = Don’t Care
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (0.58 µA/kHz) f + I
= (1.20 µA/kHz) f + I
= (1.70 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.001.
SS
T
L
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MOTOROLA CMOS LOGIC DATA
MC14029B
121
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
All Types
Typ #
Characteristic
Output Rise and Fall Time
Symbol
V
Unit
Min
Max
DD
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
L
TLH THL
, t
TLH THL
= (0.55 ns/pF) C + 9.5 ns
L
Propagation Delay Time
Clk to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
= (0.5 ns/pF) C + 75 ns
L
5.0
10
15
—
—
—
200
100
90
400
200
180
PLH PHL
L
L
, t
PLH PHL
, t
PLH PHL
Clk to C
t
t
t
t
t
,
ns
ns
ns
ns
out
, t
, t
PLH
= (1.7 ns/pF) C + 230 ns
L
t
5.0
10
15
—
—
—
250
130
85
500
260
190
PLH PHL
PHL
t
t
= (0.66 ns/pF) C + 97 ns
PLH PHL
PLH PHL
L
, t
= (0.5 ns/pF) C + 75 ns
L
C
to C
out
,
in
PLH
t
t
t
, t
, t
, t
= (1.7 ns/pF) C + 95 ns
L
t
5.0
10
15
—
—
—
175
50
50
360
120
100
PLH PHL
PLH PHL
PLH PHL
PHL
= (0.66 ns/pF) C + 47 ns
L
= (0.5 ns/pF) C + 35 ns
L
PE to Q
t
,
PLH
, t
, t
, t
= (1.7 ns/pF) C + 230 ns
L
t
5.0
10
15
—
—
—
235
100
80
470
200
160
PLH PHL
PHL
t
t
= (0.66 ns/pF) C + 97 ns
PLH PHL
PLH PHL
L
= (0.5 ns/pF) C + 75 ns
L
PE to C
t
,
out
, t
PLH
= (1. 7 ns/pF) C + 465 ns
L
t
5.0
10
15
—
—
—
320
145
105
640
290
210
PLH PHL
PHL
t
t
, t
, t
= (0.66 ns/pF) C + 192 ns
PLH PHL
PLH PHL
L
= (0.5 ns/pF) C + 125 ns
L
Clock Pulse Width
t
5.0
10
15
180
80
60
90
40
30
—
—
—
ns
MHz
ns
W(cl)
Clock Pulse Frequency
f
cl
5.0
10
15
—
—
—
4.0
8.0
10
2.0
4.0
5.0
Preset Removal Time
The Preset Signal must be low prior to a positive–going
transition of the clock.
t
t
5.0
10
15
160
80
60
80
40
30
—
—
—
rem
Clock Rise and Fall Time
5.0
10
1 5
—
—
—
—
—
—
15
5
4
µs
r(cl)
f(cl)
t
Carry In Setup Time
t
su
5.0
10
15
150
60
40
75
30
20
—
—
—
ns
Up/Down Setup Time
5.0
10
15
340
140
100
170
70
50
—
—
—
ns
Binary/Decade Setup Time
Preset Enable Pulse Width
5.0
10
15
320
140
100
160
70
50
—
—
—
ns
t
W
5.0
10
15
130
70
50
65
35
25
—
—
—
ns
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14029B
122
MOTOROLA CMOS LOGIC DATA
V
DD
0.01 µF
CERAMIC
I
500 pF
D
PE
Q0
Q1
Q2
C
in
B/D
U/D
CLK
P0
PULSE
GENERATOR
C
L
C
L
P1
P2
P3
Q3
out
C
L
C
C
L
C
L
20 ns
20 ns
V
V
DD
90%
50%
CLK
10%
SS
VARIABLE
WIDTH
Figure 1. Power Dissipation Test Circuit and Waveform
V
DD
PE
Q0
Q1
Q2
PROGRAMMABLE
PULSE
GENERATOR
C
in
B/D
U/D
CLK
C
L
P0
P1
P2
C
Q3
L
C
L
P3
C
C
L
out
C
L
V
SS
t
W
t
t
rem
su
1/f
cl
CARRY IN OR
UP/DOWN
OR BINARY/DECADE
V
DD
50%
V
V
SS
DD
CLOCK
50%
V
V
SS
DD
t
W
PRESET ENABLE
V
SS
20 ns
t
C
ONLY
TLH
90%
out
V
V
OH
90%
10%
Q0 OR CARRY OUT
10%
OL
t
PLH
t
t
t
PLH
THL
PHL
Figure 2. Switching Time Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14029B
123
TIMING DIAGRAM
CLOCK
CARRY IN
UP/DOWN
BINARY/DECADE
PE
P0
P1
P2
P3
Q0
Q1
Q2
Q3
CARRY OUT
COUNT
0
1
2
3
4
5
6
7
8
9
8
7
6
5
4
3
2
1
0
0
9
6
7
0
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
C
U/D
B/D
C
C
U/D
B/D
C
C
U/D
B/D
C
out
in
out
in
out
in
MC14029B
MSD
MC14029B
LSD
MC14029B
PE
PE
PE
OUTPUT
P3 P2 P1 P0 CLK
P3 P2 P1 P0 CLK
P3 P2 P1 P0 CLK
V
V
V V
DD DD
DD
DD
“1”
“2”
“3”
INPUT
CLOCK
CLOCK
C
(LSD)
out 1
C
out 2
C
(MSD)
out 3
PE
COUNT
* t
W
900 ns @ V = 5 V
DD
Figure 3. Divide by N BCD Down Counter and Timing Diagram
(Shown for N = 123)
MC14029B
124
MOTOROLA CMOS LOGIC DATA
LOGIC DIAGRAM
MOTOROLA CMOS LOGIC DATA
MC14029B
125
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14029B
126
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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are registered
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MC14029B/D
◊
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