MC141547P2_技术文档

MOTOROLA

SEMICONDUCTOR TECHICAL DATA

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MC141547P2

Advanced Monitor On-Screen

Display II - 16

CMOS

P SUFFIX

PLASTIC PACKAGE

This is a high performance HCMOS device designed to interface with a mi-

crocontroller unit to allow colored symbols or characters to be displayed on a

color monitor. Its on-chip PLL allows both multisystem operation and self gen-

eration of system timing. It also minimizes the MCU’s burden through its built-in

display and control bytes RAM. By storing a full screen of data and control

information, this device has a capability to carry out ‘screen-refresh’ without any

MCU supervision.

ORDERING INFORMATION

MC141547P2 Plastic Dip

Since there is no clearance between characters, special graphics oriented

characters can be generated by combining two or more character blocks. There

are two different resolutions that users can choose. By changing the number of

dots per horizontal line to 384 (CGA) or 768 (SVGA), smaller characters with

higher resolution can be easily achieved.

Special functions such as character bordering or shadowing, multi-level win-

dows, intensity control for windows, double height and double width, and pro-

grammable vertical length of character are also incorporated. Furthermore, nei-

ther massive information update nor extremely high data transmission rate are

expected for normal on- screen display operation and serial protocols are imple-

mented in lieu of any parallel formats to achieve the minimum pin count.

Moreover, the font matrix is improved from 10 by 16 to high resolution font

matrix, 12 by 18, in this version. In order to maintain the constant menu height

in the different display modes, one special register, controlling the row to row

spacing, is implemented to avoid the nonuniform extension of BRM algorithm

in character height adjustment.

PIN ASSIGNMENT

V

1

2

3

4

16

15

14

13

V

SS(A)

VCO

SS

R

G

B

RP

DD(A)

HFLB

5

12 FBKG

INT/Cout

VFLB

6

7

8

11

10

SS

SDA(MOSI)

9

SCL(SCK)

V

DD

•

Two Resolutions: 384 (CGA) or 768 (SVGA) Dots per Line

12 x 18 Dot Matrix Character

MaximumHorizontalFrequencyis120KHz(92.2MHz DotClockat768mode)

Four Fully Programmable Background Windows with Intensity Control

Row to Row Spacing Register to Manipulate the Constant Menu Height

Programmable Height of Character to Meet Multi-Sync Requirement

Smooth Menu Movement by Real Time Programming of H/V Delay Registers

Fully Programmable Character Array of 15 Rows by 30 Columns

Internal PLL Generates a Wide-Ranged System Clock

Programmable Vertical and Horizontal Positioning for Display Center

128 Characters and Graphic Symbols ROM (Mask ROM is Optional)

Character by Character Color Selection

A Maximum of Four Selectable Colors per Row

Double Character Height and Double Character Width

Character Bordering or Shadowing

M_BUS (IIC) Interface with Address $7A (SPI Bus is Mask Option)

REV 1.2

2/98

BLOCK DIAGRAM

7

8

6

HORD

VERD

CH

DISPLAY

MEMORY

OSD_EN

SHADOW

BSEN

CONTROL

X32B

REGISTERS

VPOL

HPOL

7

DATA

8

SDA(MOSI)

SCL(SCK)

and DATA

DATA RECEIVER

MBUS/SPI

8

6

MANAGEMENT

54

15

9

ADR

WADDR

SS

ADDRC

9

WCOLOUR

and

CONTROL

RFG

RDATA

Z

8

32

MCLK

BUS ARBITRATION

LOGIC

32

Y

13

CCOLOURS

and SELECT

ROW

BUFFER

NROW

CHS

R

VPOL

4

CWS

10

VERTICAL

CONTROL

CIRCUIT

VFLB

CRADDR

8

CHS

VERD

8

6

CH

CHARACTER ROM(240 + 16)

12 X 18 MATRIX

4

LP

12X3

3

2

HORD

7

RP

CHAR

HORIZONTAL

CONTROL

and PLL

VCO

PWM_CLK

CWS

5

HFLB

BSEN

CCLK

SC

10 BITS SHIFT

REGISTERS

SHADOW

HPOL

54

X32B

VDD(A)

VSS(A)

CCOLOURS

and SELECT

4

1

BACKGROUND

GENERATOR

W

3

13

COLOUR ENCODER

15

WCOLOUR

and CONTROL

VDD

VSS

9

16

11

15

13 12

14

MC141547P2

2

MOTOROLA

ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V

SS

This device contains protection circuitry to guard

against damage due to high static voltages or

electric fields. However, precautions must be

taken to avoid applications of any voltage higher

than maximum rated voltages to this high-imped-

Symbol

Characteristic

Value

– 0.3 to + 7.0

– 0.3 to

Unit

V

Supply Voltage

DD

V

Input Voltage

V

in

SS

V

ance circuit. For proper operation, V and V

in out

+ 0.3

DD

25

0 to 85

– 65 to + 150

should be constrained to the range V

≤ (V

SS in

Id

Ta

Current Drain per Pin Excluding V

and V

mA

DD

SS

or V ) ≤ V

out

.

DD

Unused inputs must always be tied to an appro-

Operating Temperature Range

Storage Temperature Range

°C

priate logic voltage level (e.g., either V

or

T

SS

stg

V

). Unused outputs must be left open.

DD

NOTE: Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics

tables or Pin Description section.

AC ELECTRICAL CHARACTERISTICS (V /V

= 5.0 V, V /V

SS SS(A)

= 0 V, T = 25C,

A

DD DD(A)

Voltage Referenced to V

)

SS

Symbol

Characteristic

Min

Typ

Max

Unit

Output Signal (R, G, B, FBKG and INT/Cout) C

= 30 pF

load

t

—

6

ns

r

Rise Time

Fall Time

t

f

F

HFLB Input Frequency

15K

—

120K

Hz

HFLB

90%

10%

tr

tf

Figure 1. Switching Characteristics

MOTOROLA

MC141547P2

3

DC CHARACTERISTICS V /V

DD DD(A)

= 5.0 V ± 10%, V /V

SS SS(A)

= 0 V, T = 25°C, Voltage Referenced to V

SS

A

Symbol

Characteristic

Min

– 0.8

DD

Typ

Max

Unit

V

High Level Output Voltage

= – 5 mA

V

—

V

OH

I

out

V

Low Level Output Voltage

—

V

+ 0.4

SS

V

OL

I

= 5 mA

out

Digital Input Voltage (Not Including SDA and SCL)

V

Logic Low

Logic High

—

0.3 V

—

V

IL

DD

0.7 V

V

DD

IH

Input Voltage of Pin SDA and SCL in SPI Mode

Logic Low

Logic High

V

—

0.3 V

—

V

IL

0.7 V

V

IH

Input Voltage of Pin SDA and SCL in M_BUS Mode

Logic Low

Logic High

V

—

0.3 V

—

V

IL

0.7 V

V

IH

I

High-Z Leakage Current (R, G, B and FBKG)

– 10

—

+ 10

µA

II

I

Input Current (Not Including RP, VCO, R, G, B, FBKG and INT)

– 10

—

+ 10

+ 20

µA

I

Supply Current (No Load on Any Output)

mA

DD

SDA (MOSI) (Pin 7)

PIN DESCRIPTION

Data and control message are being transmitted to this

chip from a host MCU, via one of the two serial bus systems.

With either protocol, this wire is configurated as a uni-direc-

tional data line. (Detailed description of these two protocols

will be discussed in the M_BUS and SPI sections).

VSS(A) (Pin 1)

This pin provides the signal ground to the PLL circuitry. An-

alog ground for PLL is separated from digital ground for opti-

mal performance.

SCL (SCK) (Pin 8)

A separate synchronizing clock input from the transmitter

is required for either protocol. Data is read at the rising edge

of each clock signal.

VCO (Pin 2)

A dc control voltage input to regulate an internal oscillator

frequency. See the Application Diagram for the application val-

ues used.

V

(Pin 9)

DD

This is the power pin for the digital logic of the chip.

RP (Pin 3)

VFLB (Pin 10)

An external RC network is used to bias an internal VCO to

resonate at the specific dot frequency. The maximum voltage

at Pin 3 should not exceed 3.5 V at any condition. See the

Application Diagram for the application values used.

Similar to Pin 5, this pin inputs a negative polarity of verti-

cal synchronize signal to synchronize the vertical control cir-

cuit.

V

(Pin 4)

INT/ Cout (Pin 11)

DD(A)

A positive 5 V dc supply for PLL circuitry. Analog power for

This is a multiplexed pin. When the Cout bit is cleared

after power on or by the MCU, this pin is INT and this output

pin is used to indicate the color intensity. If the associated

window intensity control bits are set, this pin will output a

logic high while displaying the specified windows. Otherwise,

it will keep in low state. Only the windows have the color

intensity selection and all displayed characters or symbols

are all high intensity. It means that INT pin must be driven

high while displaying the characters or symbols.

PLL is separated from digital power for optimal performance.

HFLB (Pin 5)

This pin inputs a negative polarity horizontal synchronize

signal pulse to phase lock into an internal system clock gener-

ated by the on-chip VCO circuit.

SS (Pin 6)

This input pin is part of the SPI system. An active low signal

generated by the master device enables this slave device to

accept data. Pull high to terminate the SPI communication. If

M_BUS is employed as the serial interface, this pin should be

Please refer to the timing figure for detail timing chart.

Thus, 16-color selection is achievable by combining this

intensity pin with R/G/B outputs for windows’ color control.

On the other hand, this color intensity information could be

tied to either V

or V .

DD

SS

MC141547P2

4

MOTOROLA

reflected on the R/G/B pins by asserting tri-state instead of

logic high if 3_S bit is set to 1. Refer to the “REGISTERS” for

more information.

terface, the link can be terminated if change on display is not

required.

The bottom half of the Block Diagram constitutes the heart

of this entire system. It performs all the AMOSD II functions

such as programmable vertical length (from 16 lines to 63

lines), display clock generation (which is phase locked to the

incoming horizontal sync signal at Pin 5 HFLB), bordering or

shadowing, and multiple windowing.

If the Cout bit is set to 1 via M_BUS or SPI, this pin is

changed to a mode-dependent clock output with 50/50 duty

cycle and synchronous with the input horizontal synchroniza-

tion signal at Pin 5. The frequency is dependent on the mode

in which the AMOSD II is currently running. The exact fre-

quencies in the different resolution modes are described be-

low.

COMMUNICATION PROTOCOLS

BUS Operation

The operating clock for M_Bus or SPI bus derives from

system dot clock. Internal PLL is using to generate the dot

clock base on the HFLB input frequency where the dot clock

is equal to 384/768xHFLB in 384/768 modes respectively. In

order to have stable operation of M_Bus or SPI bus in the

OSD and meet below specifications, HFLB(15k-120k) must

be presented and the PLL locks to HFLB properly. Refer to

Application Diagram for PLL bias circuit.

Resolution

Frequency

Duty Cycle

32 x H

f

384 dots/line

768 dots/line

50/50

64 x H

f

NOTE: H is the frequency of the input H sync. on Pin 5.

f

Typically, this clock is fed into an external pulse width mod-

ulation module as its clock source. Because of the synchro-

nization between Cout clock and H sync, a better perfor-

mance on the external PWM controlled functions can be

achieved.

M_BUS Serial Communication

This is a two-wire serial communication link that is fully

compatible with the IIC bus system. It consists of SDA bidi-

rectional data line and SCL clock input line. Data is sent from

a transmitter (master), to a receiver (slave) via the SDA line,

and is synchronized with a transmitter clock on the SCL line

at the receiving end. The maximum data rate is limited to

100 kbps.The default chip address is $7A. Please refer to the

IIC-Bus specification for detail timing requirement.

FBKG (Pin 12)

This pin will output a logic high while displaying characters

or windows when FBKGC bit in frame control register is 0,

and output a logic high only while displaying characters

when FBKGC bit is 1. It is defaulted to high impedance state

after power on, or when there is no output. An external 10 kΩ

resistor pulled low is recommended to avoid level toggling

caused by hand effect when there is no output.

Operating Procedure

Figure 2 shows the M_BUS transmission format. The mas-

ter initiates a transmission routine by generating a START

condition, followed by a slave address byte. Once the ad-

dress is properly identified, the slave will respond with an

ACKNOWLEDGE signal by pulling the SDA line LOW during

the ninth SCL clock. Each data byte which then follows must

be eight bits long, plus the ACKNOWLEDGE bit, to make up

nine bits together. Appropriate row and column address in-

formation and display data can be downloaded sequentially

in one of the three transmission formats described in DATA

TRANSMISSION FORMATS SECTION. In the cases of no

ACKNOWLEDGE or completion of data transfer, the master

will generate a STOP condition to terminate the transmission

routine. Note that the OSD_EN bit must be set after all the

display information has been sent in order to activate the

AMOSD II circuitry of MC141547P2, so that the received in-

formation can then be displayed.

B,G,R (Pin 13, 14, 15)

AMOSD II color outputs in TTL level to the host monitor.

These three outputs are in high impedance if 3_S bit is set

and the color intensity is low. Otherwise, they are active high

push-pull outputs. See “REGISTERS” for more information.

These pins are in high impedance state after power on.

V

(Pin 16)

SS

This is the ground pin for the digital logic of the chip.

SYSTEM DESCRIPTION

MC141547P2 is a full screen memory architecture. Re-

fresh is done by the built-in circuitry after a screenful of dis-

play data has been loaded in through the serial bus. Only

changes to the display data need to be input afterward.

Serial data, which includes screen mapping address, dis-

play information, and control messages, are being transmit-

ted via one of the two serial buses: M_BUS or SPI (mask

option). These two sets of buses are multiplexed onto a sin-

gle set of wires. Standard parts offer M_BUS transmission.

Data is first received and saved in the MEMORY MAN-

AGEMENT CIRCUIT in the Block Diagram. Meanwhile, the

AMOSD II is continuously retrieving the data and putting it

into a ROW BUFFER for display and refreshing, row after

row. During this storing and retrieving cycle, a BUS ARBI-

TRATION LOGIC will patrol the internal traffic, to make sure

that no crashes occur between the slower serial bus receiver

and fast ‘screen-refresh’ circuitry. After the full screen display

data is received through one of the serial communication in-

DATA BYTES

CHIP ADDRESS

SDA

ACK

SCL

1

2–7

8

9

STOP CONDITION

START CONDITION

Figure 2. M_BUS Format

MOTOROLA

MC141547P2

5

Serial Peripheral Interface (SPI)

tween format (a), (b) and (c), the sixth bit of the column ad-

dress is set to ‘1’ which represents format (c), and a ‘0’ for

format (a) or (b). There is some limitation on using mix-for-

mats during a single transmission. It is permissible to change

the format from (a) to (b), or from (a) to (c), or from (b) to (a),

but not from (c) back to (a) or (b).

Similar to M_BUS communication, SPI requires separate

clock (SCK) and data (MOSI) lines. In addition, a SS SLAVE

SELECT pin is controlled by the master transmitter to initiate

the receiver.

Operating Procedure

To initiate SPI transmission, pull SS pin low by the master

device to enable MC141547P2 to accept data. The SS input

line must be a logic low prior to occurrence of SCK and re-

main low until and after the last (eighth) SCK cycle. After all

data has been sent, the SS pin is then pulled high by master

to terminate the transmission. Data bit is sent from master to

OSD’s internal latch during rising edge of SCK and then

transmit to internal register during falling edge. Therefore,

last falling edge of CLK is needed for proper transmission of

last byte data. No slave address is needed for SPI. Hence,

row and column address information and display data (the

data transmission formats are the same as in M_BUS mode

described in the previous section) can be sent immediately

after the SPI is initiated.

row addr

col addr

info

Figure 4. Data Packet

BIT

FORMAT

ADDRESS

7

1

0

6

5

4

3

2

1

0

a, b, c

a, b

c

ROW

X

0

1

X

D

X

COLUMN

X: don’t care

D: valid data

Figure 5. Row & Column Address Bit Patterns

MEMORY MANAGEMENT

SS

Internal RAM are addressed with row and column (coln)

number in sequence. The space between row 0 and coln 0

to row 14 and coln 29 are called Display registers, with each

contains a character ROM address corresponding to display

location on monitor screen. Every data row associate with

two control registers, which locate at coln 30 and 31 of their

respective rows, to control the characters display format of

that row. In addition, three window control registers for each

of three windows together with six frame control registers

occupy the first 15 columns of row 15 space. The PWM reg-

isters are located from column 20 to 31.

MOSI

MSB

LSB

last byte

first byte

SCK

Figure 3. SPI Protocol

DATA TRANSMISSION FORMATS

After the proper identification by the receiving device, data

train of arbitrary length is transmitted from the master. There

are three transmission formats from (a) to (c) as stated below.

The data train in each sequence consists of row address (R),

column address (C), and display information (I), as shown in

Figure 4. In format (a), display information data must be pre-

ceded with the corresponding row address and column ad-

dress. This format is particularly suitable for updating small

amounts of data between different rows. However, if the cur-

rent information byte has the same row address as the one

before, format (b) is recommended. For a full screen pattern

change which requires a massive information update, or dur-

ing power up situation, most of the row and column address-

es on either (a) or (b) format will appear to be redundant. A

more efficient data transmission format (c) should be applied.

This sends the RAM starting row and column addresses

once only, and then treats all subsequent data as display in-

formation. The row and column addresses will be automati-

cally incremented internally for each display information data

from the starting location.

User should handle the internal RAM address location

with care especially for those rows with double length alpha-

numeric symbols. For example, if row n is destined to be

double height on the memory map, the data displayed on

screen row n and n+1 will be represented by the data con-

tained in the memory address of row n only. The data of next

row n+1 on the memory map will appear on the screen of

n+2 and n+3 row space and so on. Hence, it is not neces-

sary to throw in a row of blank data to compensate for the

double row action. User needs to take care of excessive row

of data in memory in order to avoid over running the limited

number of row space on the screen.

There is difference for rows with double width alphanu-

meric symbols. Only the data contained in the even num-

bered columns of memory map will be shown, the odd

numbered columns will be ignored and not disclosed.

The data transmission formats are:

(a) R – > C– > I –> R – > C – > I – > . . . . . . . . .

(b) R – > C – > I – > C – > I – > C – > I. . . . . . .

(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .

To differentiate the row and column addresses when trans-

ferring data from master, the MSB (Most Significant Bit) is set

as in Figure 5: ‘1’ to represent row, while ‘0’ for column ad-

dress. Furthermore, to distinguish the column address be-

MC141547P2

6

MOTOROLA

Bit 7-2 Color 3 and 4 are defined by R3, G3, B3, and R4,

G4, B4 respectively.

COLUMN

0

27 28 29 30 31

0

.

Table 1. The Character/Window Color Selection

R

0

1

G

0

1

0

1

B

0

1

0

1

0

1

0

1

DISPLAY REGISTERS

Black

Blue

Green

Cyan

14

15

0

1112

19 20

31

Red

FRAME CRTL REG

PWM CRTL REG

WINDOW 1 ~ WINDOW 4

Magenta

Yellow

White

WINDOW/FRAME/PWM CONTROL REGISTERS

Figure 6. Memory Map

REGISTERS

Display Register

Window 1 Registers

Row 15 Coln 0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

CCS0

ROW START ADDR

LSB

ROW END ADDR

ROW 15

COLN 0

LSB

MSB

CRADDR

Bit 7 CCS0 - This bit defines a specific character color out of

the two preset colors. Color 1 is selected if this bit is cleared,

and color 2 otherwise.

Row 15 Coln 1

7

6

5

4

3

2

1

0

COL START ADDR

ROW 15

COLN 1

Bit 6-0 CRADDR - This seven bits address the 128 charac-

ters or symbols resided in the character ROM.

W_INT

WEN

CCS1

MSB

LSB

Bit 2

WEN - It enables the background window 1 gen-

Row Control Registers

Coln 30

eration if this bit is set.

Bit 1

CCS1 - This additional color select bit provides

the characters resided within window 1 with two extra color

selections, making a total of four selection for that row

7

6

5

4

3

2

1

0

Bit 0

W_INT - This additional color related bit provides

R1

G1

B1

R2

G2

B2

CHS CWS

COLN 30

the color intensity selection for window 1. If this bit is 0, INT

pin will go low while displaying window 1. The default value

is 1 to indicate high intensity.Video pre-amplifier or external

R/G/B switch can make use of INT pin for windows’s color

intensity control.

Bit 7-2 Color 1 is determined by R1, G1, B1 and color 2 by

R2, G2, B2. Refer to Table 1 for color selection.

Bit 1 CHS - It determines the height of a display symbol.

When this bit is set, the symbol is displayed in double height.

Bit 0 CWS - Similar to bit 1, character is displayed in double

width, if this bit is set.

Row 15 Coln 2

7

6

5

4

3

2

1

0

Coln 31

ROW 15

COLN 2 MSB

COL END ADDR

R

G

B

LSB

7

6

5

4

3

2

1

0

Bit 2-0 R, G and B - Controls the color of window 1. Refer

to Table 1 for color selection. Window 1 Registers occupy

Column 0-2 of Row 15, Window 2 from Column 3-5, Window

3 from 6-8 and Window 4 from 9-11. Window 1 has the high-

est priority, and Window 4 the least. If window over-lapping

occurs, the higher priority window will cover the lower one,

R3

G3

B3

R4

G4

B4

COLN 31

MOTOROLA

MC141547P2

7

and the higher priority color will take over on the overlap win-

dow area. If the start address is greater than the end

address, this window will not be displayed.

Row 15 Coln 7

7

6

5

4

3

2

1

0

ROW 15

COLN 7

COL START ADDR

W_INT

WEN

CCS1

MSB

LSB

Window 2 Registers

Row 15 Coln 3

Bit 2

WEN - It enables the background window 3 gen-

eration if this bit is set.

Bit 1

CCS1 - This additional color select bit provides

7

6

5

4

3

2

1

0

the characters resided within window 3 with two extra color

selections, making a total of four selection for that row

ROW START ADDR

ROW END ADDR

ROW 15

COLN 3

MSB

LSB

Bit 0

W_INT - This additional color related bit provides

the color intensity selection for window 3. If this bit is 0, INT

pin will go low while displaying window 3.The default value

is 1 to indicate high intensity. Video pre-amplifier or external

R/G/B switch can make use of INT pin for windows’s color

intensity control.

Row 15 Coln 4

7

6

5

4

3

2

1

0

ROW 15

COLN 4

COL START ADDR

WEN

CCS1 W_INT

Row 15 Coln 8

MSB

LSB

7

6

5

4

3

2

1

0

ROW 15

COLN 8

COL END ADDR

MSB

Bit 2

WEN - It enables the background window 2 gen-

R

G

B

LSB

eration if this bit is set.

Bit 1

CCS1 - This additional color select bit provides

Bit 2-0 R, G and B - Controls the color of window 3.

Refer to Table 1 for color selection. Window 1 Registers

occupy Column 0-2 of Row 15, Window 2 from Column 3-5,

Window 3 from 6-8 and Window 4 from 9-11. Window 1 has

the highest priority, and Window 4 the least. If window over-

lapping occurs, the higher priority window will cover the

lower one, and the higher priority color will take over on the

overlap window area. If the start address is greater than the

end address, this window will not be displayed.

the characters resided within window 2 with two extra color

selections, making a total of four selection for that row

Bit 0

W_INT - This additional color related bit provides

the color intensity selection for window 2. If this bit is 0, INT

pin will go low while displaying window 2. The default value

is 1 to indicate high intensity.Video pre-amplifier or external

R/G/B switch can make use of INT pin for windows’s color

intensity control.

Row 15 Coln 5

Window 4 Registers

Row 15 Coln 9

7

6

5

4

3

2

1

0

ROW 15

COLN 5

COL END ADDR

R

G

B

MSB

LSB

7

6

5

4

3

2

1

0

Bit 2-0 R, G and B - Controls the color of window 2.

Refer to Table 1 for color selection. Window 1 Registers

occupy Column 0-2 of Row 15, Window 2 from Column 3-5,

Window 3 from 6-8 and Window 4 from 9-11. Window 1 has

the highest priority, and Window 4 the least. If window over-

lapping occurs, the higher priority window will cover the

lower one, and the higher priority color will take over on the

overlap window area. If the start address is greater than the

end address, this window will not be displayed.

ROW START ADDR

ROW END ADDR

ROW 15

COLN 9

MSB

LSB

LSB MSB

Row 15 Coln 10

7

6

5

4

3

2

1

0

ROW 15

COLN 10

COL START ADDR

W_INT

WEN

CCS1

MSB

LSB

Bit 2

WEN - It enables the background window 4 gen-

eration if this bit is set.

Bit 1

CCS1 - This additional color select bit provides

Window 3 Registers

Row 15 Coln 6

the characters resided within window 4 with two extra color

selections, making a total of four selection for that row

Bit 0

W_INT - This additional color related bit provides

the color intensity selection for window 4. If this bit is 0, INT

pin will go low while displaying window 4.The default value

is 1 to indicate high intensity. Video pre-amplifier or external

R/G/B switch can make use of INT pin for windows’s color

intensity control.

7

6

5

4

3

2

1

0

ROW START ADDR

ROW END ADDR

ROW 15

COLN 6

MSB

LSB

LSB MSB

MC141547P2

8

MOTOROLA

Row 15 Coln 11

CHARACTER ENLARGEMENT

7

6

5

4

3

2

1

0

3 lines

ROW 15

COLN 11

COL END ADDR

MSB

R

G

B

LSB

2 lines

1 line

Bit 2-0 R, G and B - Controls the color of window 4.

Refer to Table 1 for color selection. Window 1 Registers

occupy Column 0-2 of Row 15, Window 2 from Column 3-5,

Window 3 from 6-8 and Window 4 from 9-11. Window 1 has

the highest priority, and Window 4 the least. If window over-

lapping occurs, the higher priority window will cover the

lower one, and the higher priority color will take over on the

overlap window area. If the start address is greater than the

end address, this window will not be displayed.

CH lines

(48~63)

CH lines

(32~47)

(16~31)

3 lines

2 lines

1 line

16<CH<32

32<CH<48

48<CH<64

0

1

Frame Control Registers

2

3

4

5

Frame Control Register Row 15 Coln 12

6

7

8

7

6

5

4

3

2

1

0

18 lines

(1+16+1)

9

24 lines

VERTD

10

11

12

13

14

15

16

17

COLN 12

LSB

(1+22+1)

MSB

Bit 7-0 VERTD - These 8 bits define the vertical starting

position. Total 256 steps, with an increment of four horizontal

lines per step for each field. Its value can’t be zero anytime.

The default value of it is 4.

Built-in font

(12x18 matrix)

when CH=16

Display character

when CH=22

Frame Control Register Row 15 Coln 13

7

6

5

4

3

2

1

0

HORD

COLN 13

MSB

LSB

38 lines

27 lines

(2+34+2)

(1+25+1)

Bit 6-0 HORD - Horizontal starting position for character

display. 7 bits give a total of 128 steps and each increment

represents five dots movement shift to the right on the moni-

tor screen. Its value cannot be zero anytime. The default

value of it is 15.

Display character

when CH=25

Display character

when CH=34

Frame Control Register Coln 14

6

5

4

3

2

1

0

7

COLN 14

CH5 CH4 CH3 CH2 CH1 CH0

Figure 7. Variable Character Height

Figure 7 illustrates the enlargement algorithm for top and

bottom lines and how this chip expand the built-in character

font to the desired height.

Bit 5-0 CH5-CH0 - This six bits will determine the dis-

played character height. AMOSD II adopts 12 by 18 font

matrix and the middle 16 lines, line 2 to line 17, are

expanded by BRM algorithm. The top line and bottom line

will be duplicated dependent on the value of CH. No any line

is duplicated for top and bottom if CH is less than 32. One

extra duplicated line will be inserted for top and bottom if CH

is larger or equal to 32 and less than 48. Two extra dupli-

cated lines will be inserted for top and bottom if CH is larger

or equal to 48. Setting a value below 16 will not have a pre-

dictable result. Display character line number is equal to C1

x (18 + C2) where C1 = 1, 2 or 3 defined by CH5-CH4 and

C2 = 0-15 defined by CH3-CH0 (BRM).

In this approach, the actual character height in unit of the

scan line can be calculated from the following simple equa-

tion:

H = CH + N

Where H is the expanded character height in unit of

lines

CH is the number defined by CH5 ~ CH0

N is a variable dependent on the value of CH

N = 2 when 16<CH<32

N = 4 when 32<CH<48

N = 6 when 48<CH<64

MOTOROLA

MC141547P2

9

Bit 2

TRIC - Tri-state Control. This bit is used to control

Frame Control Register Row 15 Coln 15

the driving state of output pins, R, G, B and FBKG when the

OSD is disabled. After power on, this bit is reset and R, G, B

and FBKG are in high impedance state while OSD being dis-

abled. If it is set by MCU, these four output pins will drive low

while OSD being in disabled state. Basically, the setting is

dependent on the requirement of the external application cir-

cuit.

6

5

4

3

2

1

0

7

ROW 15

COLN 15

OSD_EN BSEN SHADOW

X32B 3_S

FBKGC

Bit 7

is set.

OSD_EN - OSD circuit is activated when this bit

BSEN - It enables the character bordering or

Bit 3

HF - High Frequency Bit. If the incoming H sync

signal is higher than 60 KHz, set this bit to 1 for better perfor-

mance. This bit controls gain of internal VCO so that PLL can

work for whole range from 15KHz to 120KHz.

Bit 6

shadowing function when this bit is set.

Bit 5

SHADOW - Character with black-edge shadow-

ing is selected if this bit is set, otherwise bordering prevails.

Bit 1

HPOL - This bit selects the polarity of the incoming

horizontal sync signal (HFLB). If it is negative polarity, clear

this bit. Otherwise, set this bit to 1 to represent the positive H

sync signal. After power on, this bit is cleared.

Bit 3

X32B - It determines the number of dots per hor-

izontal line. There are 384 dots per horizontal line if bit

X32B is clear and this is also the default power on state.

Otherwise, 768 dots per horizontal sync line when bit X32B

is set to 1. Please refer to the Table 2 for details.

Bit 0

VPOL - This bit selects the polarity of the incoming

vertical sync signal (VFLB). If it is negative polarity, clear this

bit. Otherwise, set this bit to 1 to represent the positive V

sync signal. After power on, this bit is cleared.

Table 2. Resolution Setting

Row 15 Col 18 to Col 19

(X32B)

0

1

7

6

5

4

3

2

1

0

Dots / Line

Resolution

384

CGA

768

SVGA

ROW 15

COLN 18

7

6

5

4

3

2

1

0

ROW 15

COLN 19

Bit 2

3_S - By setting this bit to 1, R/G/B could output

Cout

high impedance state if the intensity attribute of windows is

set to 0. It means the corresponding R/G/B output will go

high impedance instead of driving-high while displaying the

low intensity windows which can be implemented by simple

external circuit. After power on, this bit is reset and the R/G/

B are push-pull outputs initially.

Bit 7 Cout – When this bit is set to 1,INT/Cout pin will be

switched to a clock output which is synchronous to the H sync

and used as an external PWM (pulse width modulation) clock

source. Refer to the pin description of INT/Cout for more infor-

mation. After power on, the default value is 0.

Bit 0

FBKGC - It determines the configuration of

FBKG output pin. When it is clear. FBKG pin outputs high

during displaying characters or windows. Otherwise, FBKG

pin outputs high only during displaying characters.

Frame Control Register Row 15 Coln 16

7

6

5

4

3

2

1

0

RSPACE

COLN 16

LSB

MSB

Bit 4-0 RSPACE - These 5 bits define the row to row

spacing in unit of horizontal scan line. It means extra N

lines, defined by this 5-bit value, will be appended for each

display row. Because of the nonuniform expansion of BRM

used by character height control, this register is usually

used to maintain the constant OSD menu height for differ-

ent display modes instead of adjusting the character height.

The default value of it is 0. It means there is no any extra

line inserted between row and row after power on.

Frame Control Register Row 15 Coln 17

6

5

4

3

2

1

0

7

ROW 15

COLN 17

HF

TRIC HPOL VPOL

MC141547P2

10

MOTOROLA

Frame Format and Timing

Figure 10 illustrates the relative positions of all display

characters on the screen relative to the leading edge of hori-

zontal and vertical flyback signals. The shaded area indi-

cates the area not interfered by the display characters.

Notice that there are two components in the equations stated

in Figure 10 for horizontal and vertical delays: fixed delays

from the leading edge of HFLB and VFLB signals, regard-

less of the values of HORD and VERTD: (47 dots + phase

detection pulse width) and one H scan line for horizontal and

vertical delays, respectively; variable delays determined by

the values of HORD and VERTD. Please refer to Frame

Control Registers COLN 9 and 10 for the definitions of

VERTD and HORD. Phase detection pulse width is a func-

tion of external charge-up resistor, which is the 1M Ohm

resistor in series with 5.6KOhm to VCO pin in the Application

Diagram. Dot frequency is determined by the equation: H

Freq. x 384 if the bit X32B is clear and H Freq. x 768 if bit

X32B is set to 1. For example, dot frequency is 12.288MHz if

H freq is 32 KHz while bit X32B is 0. If X32B is 1, the dot fre-

quency will be 24.576MHz (double of the original one).

vertical delay =

VERTD x 4 + 1 H scan lines

variable number of Hscan lines

VFLB

When double character width is selected for a row, only

the even-numbered characters will be displayed, as shown

in row 2. Notice that the total number of horizontal scan lines

in the display frame is variable, depending on the chosen

character height of each row. Care should be taken while

configurated each row character height so that the last hori-

zontal scan line in the display frame always comes out

before the leading edge of VFLB of next frame to avoid

wrapping display characters of the last few rows in current

frame into next frame. The number of display dots in a hori-

zontal scan line is always fixed at 360, regardless of row

character width and the setting of bit X32B.

Although there are 30 character display registers that can

be programmed for each row, not every programmed char-

acter can be shown on the screen in 384 dots resolution.

Usually, only 24 characters can be shown in this resolution

at most. This is induced by the retrace time that is required

to retrace the H scan line. In other resolution, 768 dots, 30

characters can be displayed on the screen totally if the hori-

zontal delay register is set properly.

. . . . . .

Figure 11 illustrates the timing of all output signals as a

function of window and fast blanking features. Line 3 of all

three characters are used to illustrate the timing signals. The

shaded area depicts the window area. Both the left hand

side and right hand side characters are embodied in a win-

dow with only one difference: FBKGC bit. The middle char-

acter does not have a window as its background. Timing of

signal FBKG depends on the configuration of FBKGC bit.

The configuration of FBKGC bits affects only FBKG signal

timing. Waveform ‘R, G or B’, which is the actual waveform

at R, G, or B pin, is the logical OR of waveform ‘character R,

G or B’ and waveform ‘window R, G or B’. ‘character R, G, or

B’ and ‘window R, G, or B’ are internal signals for illustration

purpose only.

Figure 10. Timing of Output Signals

MC141547P2

12

MOTOROLA

0

1

0

1

2

3

4

3

5

6

7

8

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

17

Bordering

Shadowing

Figure 12. Character Bordering and Shadowing

Figure 11. Display Frame Format

A software called AMOSD II FONT EDITOR in IBM PC

environment was written for MC141547P2 editing purposes.

It generates a set of S-Record or Binary record for the

desired display patterns to be masked onto the character

ROM of the MC141547P2.

In order to have better character display within windows,

we suggest you to place your designed character font in the

centre of the 12x18 matrix, and let its spaces be equally

located in the four sides of the matrix. The character $00 is

pre-defined for blank character, the character $FF is pre-

defined for full-filled character.

In order to avoid submersion of displayed symbols or

characters into a background of comparable colors, a fea-

ture of bordering which encircles all four sides, or shadowing

which encircles only the right and bottom sides of an individ-

ual display character is provided. Figure 12 shows how a

character is being jacketed differently. To make sure that a

character is bordered or shadowed correctly, at least one dot

blank should be reserved on each side of the character font.

MOTOROLA

MC141547P2

13

FONT

Icon Combination

MC141547P2 contains 128 character ROM. The user can

create an on-screen menu based on those characters and

icons. Refer to Table 3 for icon combinations. Address $00

and $7F are predefined characters. They cannot be modified

in any AMOSD II.

Table 3. Combination Map

ICON

ROM ADDRESS(HEX)

ARABIC NUMERALS

ALPHABET

01-0A

0B-26

EUROPEAN

27-41

SYMBOLS

42-61, 7E

C5-EE

GEOMETRY

ROM CONTENT

Figures 13 – 14 show the ROM content of MC141547P2.

Mask ROM is optional for custom parts.

MC141547P2

14

MOTOROLA

00

08

10

18

20

28

30

38

01

09

11

19

21

29

31

39

02

03

0B

13

1B

23

2B

33

3B

04

0C

14

1C

24

2C

34

3C

05

06

0E

16

1E

26

2E

36

3E

07

0F

17

1F

27

2F

37

3F

0A

12

0D

15

1A

22

1D

25

2A

32

2D

35

3A

3D

Figure 13. ROM Address ($00 – $3F)

MOTOROLA

MC141547P2

15

40

48

50

58

60

68

70

78

41

49

51

59

61

69

71

79

42

43

4B

53

5B

63

6B

73

7B

44

4C

54

5C

64

6C

74

7C

45

46

4E

56

5E

66

6E

76

7E

47

4F

57

5F

67

6F

77

7F

4A

52

4D

55

5A

62

5D

65

6A

72

6D

75

7A

7D

Figure 14. ROM Address ($40 – $7F)

MC141547P2

16

MOTOROLA

•

DC supply path for Pin 4 (V ) should be separated

DD(A)

DESIGN CONSIDERATIONS

Distortion

from other switching devices.

LC filter should be connected between Pin 17 and Pin 4.

Refer to the values used in the Application Diagram.

Biasing and filter networks should be connected to Pin 2

and Pin 3. Refer to the recommended networks in the Ap-

plication Diagram.

Two small capacitors can be added between Pin1-Pin2

and Pin3-Pin4 to filter VCO noise if necessarry. Values

should be small enough to avoid picture unlocking

caused by temperature variation.

Motorola’s MC141547P2 has a built-in PLL for multisys-

tems application. Pin 2 voltage is a dc basing for the internal

VCO in the PLL. When the input frequency (HFLB) in Pin 5

becomes higher, the VCO voltage will increase accordingly.

The built-in PLL then has a higher locked frequency output.

The frequency should be equal to 384/768 x HFLB (depends

on resolution). It is the dot-clock in each horizontal line.

•

Display distortion is caused by noise in Pin 2. Positive

noise makes VCO run faster than normal. The corresponding

scan line will be shorter accordingly. In contrast, negative

noise causes the scan line to be longer. The net result will be

distortion on the display, especially on the right hand side with

window turn on.

Jittering and Unlocking

Most display jittering and unlocking is caused by HFLB in Pin

5. Care must be taken if the HFLB signal comes from the

flyback transformer. A short path and shielded cable are rec-

ommended for a clean signal. Buffer is needed for both HFLB

and VFLB inputs. Refer to the value used in the Application

Diagram.

In order to have distortion-free display, the following recom-

mendations should be considered.

Note:The bead core added between V

and V can

SS(A)

SS

•

Only analog part grounds (Pin 2 to Pin 4) can be connect-

ed to Pin 1(V )). V and other grounds should con-

also enhance the OSD stability in high frequency HFLB oper-

ation .

SS(A

SS

nect to PCB common ground. Then the V

SS(A)

and V

SS

grounds can be connected by a bead core. Please refer to

the application diagram.(NOTE: Vss(A) and Vss are con-

nected internally.)

Display Dancing

Most display dancing is caused by interference of the se-

rial bus. It can be avoided by adding resistors in the bus in

series.

V

CC

ANALOG PLATE

100 µH

5.6µH

Bead core added to remove distortion

and enhance OSD stability at high frequenc

* Small capacitors added

100 µF

to filter VCO

noise (optional).

0.1 µF

V

and V

SS

are connected internally

SS(A)

1

9

V

DD

SS(A)

0.1

V

10

0.022 µF

CC

560

5.6 k

2

16

15

14

13

12

11

10

240

R

V

100

VCO

SS

1.8 k

1 k

0.22µF

3

4

240

G

R

RP

V

1M

B

G

B

100

DD(A)

5

6

HFLB

SS

MPS2369

Vcc

470

AMOSD -16

10K

FBKG

10 k

INT

10K

7

8

HFLB

INT

SDA(MOSI)

SCL(SCK)

Buffer

ANALOG

VFLB

470

DIGITAL GROUND

Vcc

IIC(SPI) BUS

VFLB

DIGITAL GROUND - COMMON

Buffer

MOTOROLA

MC141547P2

17


型号：	MC141547P2
厂家：	MOTOROLA
描述：	ON-SCREEN DISPLAY IC, PDIP16, PLASTIC, DIP-16 监视器光电二极管商用集成电路
文件：	总17页 (文件大小：322K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC141547P2 [MOTOROLA]

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