MC14194BCLDS [MOTOROLA]
4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, 620-09;型号: | MC14194BCLDS |
厂家: | MOTOROLA |
描述: | 4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, 620-09 移位寄存器 |
文件: | 总6页 (文件大小:113K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14194B is a 4–bit static shift register capable of operating in the
parallel load, serial shift left, serial shift right, or hold mode. The
asynchronous Reset input, when at a low level, overrides all other inputs,
resets all stages, and forces all outputs low. When Reset is at a logic 1 level,
the two mode control inputs, S0 and S1, control the operating mode as
shown in the truth table. Both serial and parallel operation are triggered on
the positive–going transition of the Clock input. The Parallel Data, Data Shift,
and mode control inputs must be stable for the specified setup and hold
times before and after the positive–going Clock transition.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
•
•
•
•
Synchronous Right/Left Serial Operation
Synchronous Parallel Load
Asynchronous Hold (Do Nothing) Mode
Functional Pin for Pin Equivalent of LS194
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
T = – 55° to 125°C for all packages.
A
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
3
4
6
5
D
D
D
D
P3
P0
P1
P2
S1 10
S0
9
2
DSR
7
DSL
V
V
= PIN 16
= PIN 8
DD
SS
D Q
D
C
Q
D Q
D Q
C
C
C
R
R
R
R
CLOCK 11
RESET
1
Q0
15
Q1
14
Q2
13
Q3
12
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (0.95 µA/kHz) f + I
= (1.90 µA/kHz) f + I
= (2.90 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
DD
– V ) in volts, f in kHz is input frequency, and k = 0.002.
SS
T
L
PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
R
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
DSR
Q0
Q1
Q2
Q3
C
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
D
D
D
D
P0
P1
P2
P3
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
DSL
S1
S0
V
SS
MOTOROLA CMOS LOGIC DATA
MC14194B
285
TRUTH TABLE
Inputs
(Reset = 1)
Outputs
(@ t
)
n+1
Operating
Mode
S1
0
S0
0
DSR
X
DSL
X
D
Q0
Q0
Q1
Q1
0
Q1
Q2
Q2
Q3
Q3
Q1
Q1
0
Q3
Q3
0
P0–3
Hold
X
Q1
Q2
Q2
Q0
Q0
0
1
0
X
0
X
X
X
X
0
Shift Left
1
0
X
1
1
0
1
0
X
Q2
Q2
0
Shift Right
0
1
1
X
1
1
1
X
X
0
Parallel
1
1
X
X
1
1
1
1
1
X = Don’t Care
t
= State after the next positive–going transition of the clock.
n+1
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
Characteristic
Output Rise and Fall Time
Symbol
, t
Min
Typ #
Max
Unit
t
ns
TLH THL
t
t
t
, t
= (1.35 ns/pF) C + 32 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.6 ns/pF) C + 20 ns
L
TLH THL
, t
TLH THL
= (0.4 ns/pF) C + 20 ns
L
Propagation Delay Time
Clock to Q
t
,t
ns
ns
PLH PHL
t
t
t
, t
= (0.9 ns/pF) C + 230 ns
= (0.36 ns/pF) C + 92 ns
L
= (0.26 ns/pF) C + 72 ns
5.0
10
15
—
—
—
275
110
85
550
220
170
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
t
Reset to Q
PHL
5.0
10
15
—
—
—
350
140
110
700
280
220
t
t
t
= (0.9 ns/pF) C + 305 ns
L
PHL
PHL
PHL
= (0.36 ns/pF) C + 122 ns
L
= (0.26 ns/pF) C + 97 ns
L
Clock Pulse Width
t
t
5.0
10
15
280
110
85
140
55
40
—
—
—
ns
ns
WH
Reset Pulse Width
5.0
10
15
180
70
50
90
35
26
—
—
—
WH
Clock Pulse Frequency
(Shift Right or Left Mode)
f
5.0
10
15
—
—
—
3.6
9.0
12
1.8
4.5
6.0
MHz
µs
cl
Clock Pulse Rise and Fall Time
t
, t
5.0
10
15
—
—
—
—
—
—
15
5
4
TLH THL
Setup Time
t
su
ns
Data to Clock
5.0
10
15
10
20
40
– 8.0
0
9.0
—
—
—
Mode Control (S) to Clock
5.0
10
15
200
75
55
100
36
27
—
—
—
ns
ns
Hold Time
t
h
Data to Clock
5.0
10
15
180
50
35
90
25
10
—
—
—
Mode Control (S) to Clock
Reset Removal Time
5.0
10
15
0
0
0
– 40
– 27
– 20
—
—
—
ns
ns
t
5.0
10
15
300
110
80
150
55
40
—
—
—
rem
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14194B
286
MOTOROLA CMOS LOGIC DATA
Parallel Load
Serial Load
V
V
DD
16
DD
16
3
15
14
3
4
5
15
14
D
Q0
D
Q0
P0
P0
4
5
C
C
C
C
L
L
D
D
D
D
D
D
P1
P2
P3
P1
P2
P3
Q1
Q2
Q1
Q2
Q3
6
11
2
6
11
2
L
L
CLOCK
CLOCK
PULSE
PULSE
GENERATOR
13
12
13
12
GENERATOR
DSR
DSL
DSR
DSL
7
7
C
C
C
C
L
L
9
10
9
10
S0
S1
R
S0
S1
R
Q3
V
L
L
8
SS
1
1
8
V
SS
NOTE: Interchange DSR with DSL and S0 with
S1 for testing shift left.
20 ns
DPn
DSR
DSL
20 ns
V
V
DD
90%
50%
10%
SS
t
t
h
h
t
t
su
su
V
V
DD
CLOCK
50%
SS
t
1/f
cl
WH(cl)
t
t
PLH
PHL
V
V
OH
90%
50%
10%
Q
n
OL
t
t
THL
TLH
t
PHL
t
rem
V
V
DD
50%
RESET
SS
t
WL
Figure 1. Switching Time Test Circuits and Waveforms
V
DD
16
3
15
14
D
Q0
P0
4
5
C
C
D
D
D
L
P1
P2
P3
Q1
Q2
Q3
6
11
2
20 ns
CLOCK
20 ns
10%
L
V
DD
CLOCK
DSR
DSL
PULSE
GENERATOR
90%
50%
13
12
V
V
SS
DD
7
1/f
C
C
L
9
10
DSR
S0
S1
R
V
V
SS
OH
Q
n
L
V
OL
1
8
V
SS
I
500 µF
D
Figure 2. Dynamic Power Dissipation Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14194B
287
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14194B
288
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered
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MC14194B/D
◊
相关型号:
MC14194BCPD
4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, 648-08
MOTOROLA
MC14194BCPDS
4000/14000/40000 SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, 648-06
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