MC14506UBCPD [MOTOROLA]
4000/14000/40000 SERIES, DUAL 4-INPUT AND-OR-INVERT GATE, PDIP16, PLASTIC, DIP-16;
| 型号： | MC14506UBCPD |
| 厂家： | 
MOTOROLA |
| 描述： | 4000/14000/40000 SERIES, DUAL 4-INPUT AND-OR-INVERT GATE, PDIP16, PLASTIC, DIP-16 栅 |
| 文件： | 总7页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14506UB is an expandable AND–OR–INVERT gate with inhibit
and 3–state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
•
•
•
•
•
3–State Output
Separate Inhibit Line
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
I , I
in out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
operation, V and V
should be constrained
in
out
to the range V
(V or V
in out
)
V
DD
.
T
stg
– 65 to + 150
260
SS
Unused inputs must always be tied to an
appropriatelogic voltage level (e.g., either V
T
L
Lead Temperature (8–Second Soldering)
C
SS
or V ). Unused outputs must be left open.
DD
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
A B C D
E
Inhibit Disable
Z
LOGIC DIAGRAM
0
0
0
X
0
X
X
0
0
0
X
0
0
X
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
A
B
C
D
E
1
2
3
4
5
A
A
A
A
A
X
15 Z
X
1
X
X
0
1
X
X
X
X
1
0
X
1
1
X
X
0
0
X
X
X
0
0
0
0
1
0
0
0
A
X
X
V
V
= PIN 16
= PIN 8
DD
SS
INH
6
X
X
X
X
X
X
X
X
X
X
1
X
0
1
0
High
Impedance
3–STATE
OUTPUT DISABLE
DIS 14
X = Don’t Care
E
D
13
12
7
Z
B
B
B
C
11
10
B
B
B
A
9
Z = (AB + CD + E + I)
B
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
T
I
T
I
T
= (0.6 µA/kHz) f + I
= (1.1 µA/kHz) f + I
= (1.7 µA/kHz) f + I
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
Three–State Leakage Current
I
15
—
± 0.1
—
± 0.0001
± 0.1
—
± 3.0
µAdc
TL
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
– V ) in volts, f in kHz is input frequency, and k = 0.002.
SS
T
L
DD
PIN ASSIGNMENT
A
B
C
D
E
1
2
16
15
V
A
A
A
A
A
DD
Z
A
3
4
5
6
7
8
14
13
12
11
10
9
DISABLE
E
B
D
C
B
B
B
B
INH
Z
B
A
B
V
SS
MC14506UB
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
, t
V
Min
Typ #
Max
Unit
DD
Output Rise and Fall Time
t
ns
TLH THL
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
L
TLH THL
, t
TLH THL
= (0.55 ns/pF) C + 9.5 ns
L
Data Propagation Delay Time
t
ns
PLH
t
t
t
= (1.7 ns/pF) C + 210 ns
5.0
10
15
—
—
—
295
110
75
580
225
180
PLH
PLH
PLH
L
= (0.66 ns/pF) C + 77 ns
L
= (0.5 ns/pF) C + 50 ns
L
t
t
t
= (1.7 ns/pF) C + 185 ns
t
t
5.0
10
15
—
—
—
270
95
65
480
175
140
ns
ns
PHL
PHL
PHL
L
PHL
= (0.66 ns/pF) C + 62 ns
L
= (0.5 ns/pF) C + 40 ns
L
Expand Propagation Delay Time
PLH
t
t
t
= (1.7 ns/pF) C + 95 ns
5.0
10
15
—
—
—
180
75
50
430
160
125
PLH
PLH
PLH
L
= (0.66 ns/pF) C + 42 ns
L
= (0.5 ns/pF) C + 25 ns
L
t
t
t
= (1.7 ns/pF) C + 115 ns
t
t
5.0
10
15
—
—
—
200
80
55
330
110
90
ns
ns
PHL
PHL
PHL
L
PHL
= (0.66 ns/pF) C + 47 ns
L
= (0.5 ns/pF) C + 30 ns
L
Inhibit Propagation Delay Time
PLH
t
t
t
= (1.7 ns/pF) C + 135 ns
5.0
10
15
—
—
—
220
100
65
500
225
160
PLH
PLH
PLH
L
= (0.66 ns/pF) C + 67 ns
L
= (0.5 ns/pF) C + 40 ns
L
t
t
t
= (1.7 ns/pF) C + 145 ns
t
5.0
10
15
—
—
—
230
95
60
400
175
150
ns
ns
PHL
PHL
PHL
L
PHL
= (0.66 ns/pF) C + 62 ns
L
= (0.5 ns/pF) C + 35 ns
L
3–State Propagation Delay Time
“1” to High Impedance
t
t
PHZ
5.0
10
15
—
—
—
60
45
35
150
110
90
“0” to High Impedance
High Impedance to “1”
High Impedance to “0”
t
5.0
10
15
—
—
—
90
55
40
225
140
100
ns
ns
ns
PLZ
5.0
10
15
—
—
—
110
50
40
300
125
100
PZH
t
5.0
10
15
—
—
—
170
70
50
425
175
125
PZL
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
16
14
12
16
14
12
a
b
c
T = + 125°C
A
V
= 15 Vdc
V
= 15 Vdc
DD
a
DD
T
= + 25°C
b
a
A
c
b
T
= – 55°C
A
c
10 Vdc
10 Vdc
10
8.0
6.0
10
8.0
6.0
a
b
a
b
UNUSED INPUTS
CONNECTED TO
V
c
c
A AND B CONNECTED TO V
in
ENABLE INPUT CONNECTED TO
SS
5.0 Vdc
5.0 Vdc
a
b
V
. OTHER INPUTS CONNECTED
a
b
DD
TO V
4.0
2.0
0
4.0
2.0
0
a T = + 125
°C
.
SS
A
c
c
b T = + 25°C
A
c T = – 55°C
A
0
2.0
4.0
6.0
8.0
10
12
14
16
0
2.0
4.0
6.0
V , INPUT VOLTAGE (Vdc)
in
8.0
10
12
14
16
V
, INPUT VOLTAGE (Vdc)
in
(a) Expand Inputs
(b) Data Inputs
Figure 1. Typical Voltage Transfer Characteristics
MOTOROLA CMOS LOGIC DATA
MC14506UB
3
V
V
DD
16
DD
16
V
V
OL
OH
INH
Z
INH
Z
A
A
A
B
A
B
A
A
A
A
I
I
OL
OH
C
C
A
A
A
A
A
A
D
E
D
E
EXTERNAL
POWER
EXTERNAL
POWER
SUPPLY
A
A
B
B
B
B
B
B
SUPPLY
C
C
B
B
B
B
B
B
D
E
D
E
DIS
Z
DIS
Z
B
B
8
V
SS
8
V
SS
Figure 2. Typical Output Source
Characteristics Test Circuit
Figure 3. Typical Output Sink
Characteristics Test Circuit
0.01
µF
CERAMIC
V
DD
16
Z
V
DD
16
Z
INH
V
A
DD
A
B
C
D
A
A
A
INH
A
A
B
A
A
PULSE
GENERATOR
B
A
A
E
A
B
I
A
B
B
C
TL
A
D
50% DUTY CYCLE
A
A
E
A
B
C
D
B
B
B
B
B
E
C
B
DIS
Z
B
D
E
B
B
8
V
SS
DIS
Z
B
C
C
L
L
8
V
SS
500 µF
I
DD
Figure 4. 3–State Leakage Current
Test Circuit
Figure 5. Typical Power Dissipation
Test Circuit
MC14506UB
4
MOTOROLA CMOS LOGIC DATA
V
DD
16
INH
Z
A
A
20 ns
20 ns
A
B
A
A
A
PULSE
GENERATOR
C
D
E
V
V
DD
90%
50%
10%
INPUT
A
SS
A
B
B
B
t
t
PLH
V
PHL
90%
50%
10%
C
OH
B
B
B
D
E
DIS
OUTPUT
V
OL
Z
B
t
t
TLH
THL
C
C
L
L
8
V
SS
Figure 6. Switching Time Test Circuit and Waveforms
(Data Inputs)
V
V
V
DD
DD
16
Z
out
INH
A
A
20 ns
A
20 ns
B
A
C
90%
50%
10%
DISABLE
INPUT
L
1 k
C
D
A
A
A
B
B
B
A
S1
A
B
E
A
B
S2
t
PZL
t
PLZ
V
OH
90%
C
D
E
≈
2.5 V @ V
= 5 V,
B
B
10%
DD
10 V AND 15 V
t
OUTPUT
PHZ
90%
≈
≈
≈
2 V @ V
6 V @ V
10 V @ V
=
5 V
DD
DD
DD
B
t
PZH
PULSE
GENERATOR
= 10 V
= 15 V
DIS
Z
B
10%
V
OL
8
V
SS
* To test other side of circuit connect to this output and
change switch (S1) to other expand input (E).
SWITCH POSITIONS
TEST
S1
A
S2
A
t
PLZ
t
t
B
B
PHZ
t
A
A
PZL
B
B
PZH
Figure 7. Switching Time Test Circuit and Waveforms
(For 3–State Output)
MOTOROLA CMOS LOGIC DATA
MC14506UB
5
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J 16 PL
G
0.300 BSC
7.62 BSC
M
S
0.25 (0.010)
T B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14506UB
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC14506UB/D
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相关型号：
MC14506UBDR2
AND-OR-Invert Gate, 4000/14000/40000 Series, 2-Func, 4-Input, CMOS, PDSO16, SOIC-16
MOTOROLA
MC145073DWR2
ADC, Delta-Sigma, 16-Bit, 1 Func, 2 Channel, Serial Access, CMOS, PDSO24, SOG-24
MOTOROLA
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