MC14516BCL [MOTOROLA]
Binary Up/Down Counter; 二进制加/减计数器
| 型号： | MC14516BCL |
| 厂家： | 
MOTOROLA |
| 描述： | Binary Up/Down Counter |
| 文件： | 总10页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC14516B synchronous up/down binary counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure.
L SUFFIX
CERAMIC
CASE 620
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the
reset (R) pin.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
T
A
= – 55° to 125°C for all packages.
Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
Single Pin Reset
BLOCK DIAGRAM
•
•
•
Asynchronous Preset Enable Operation
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky Load Over the Rated Temperature Range
PE
1
6
Q0
Q1
Q2
Q3
CARRY IN
RESET
UP/DOWN
CLOCK
P0
5
9
11
14
2
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
10
15
4
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
– 0.5 to + 18.0
DD
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
P1
12
13
3
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P2
CARRY
OUT
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
P3
7
T
stg
– 65 to + 150
260
T
L
Lead Temperature (8–Second Soldering)
C
V
V
= PIN 16
= PIN 8
DD
SS
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
TRUTH TABLE
Preset
Enable
Carry In
Up/Down
Reset
Clock
Action
No Count
Count Up
Count Down
Preset
1
X
1
0
0
0
1
X
0
0
0
0
1
X
operation, V and V
should be constrained
in
out
0
to the range V
(V or V
in out
)
V
DD
.
SS
0
0
Unused inputs must always be tied to an
appropriatelogic voltage level (e.g., either V
X
X
X
X
X
SS
or V ). Unused outputs must be left open.
DD
X
Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (0.58 µA/kHz) f + I
= (1.20 µA/kHz) f + I
= (1.70 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
– V ) in volts, f in kHz is input frequency, and k = 0.001.
SS
T
L
DD
PIN ASSIGNMENT
PE
1
2
16
15
V
DD
Q3
P3
C
3
4
5
6
7
8
14
13
12
11
10
9
Q2
P2
P1
Q1
U/D
R
P0
CARRY IN
Q0
CARRY OUT
V
SS
MC14516B
394
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
All Types
Typ #
Characteristic
Output Rise and Fall Time
Symbol
V
Unit
Min
Max
DD
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
L
TLH THL
, t
TLH THL
= (0.55 ns/pF) C + 9.5 ns
L
Propagation Delay Time
Clock to Q
t
t
,
ns
PLH
PHL
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
L
= (0.5 ns/pF) C + 75 ns
L
5.0
10
15
—
—
—
315
130
100
630
260
200
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Clock to Carry Out
t
t
t
t
,
ns
ns
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
L
= (0.5 ns/pF) C + 75 ns
L
t
5.0
10
15
—
—
—
315
130
100
630
260
200
PLH PHL
L
PHL
, t
PLH PHL
, t
PLH PHL
Carry In to Carry Out
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 230 ns
= (0.66 ns/pF) C + 97 ns
L
= (0.5 ns/pF) C + 75 ns
t
5.0
10
15
—
—
—
180
80
60
360
160
120
PLH PHL
L
PHL
, t
PLH PHL
, t
PLH PHL
L
,
Preset or Reset to Q
PLH
t
5.0
10
15
—
—
—
315
130
100
630
360
200
t
t
t
, t = (1.7 ns/pF) C + 230 ns
PHL
PLH PHL L
, t
= (0.66 ns/pF) C + 97 ns
L
PLH PHL
, t
PLH PHL
= (0.5 ns/pF) C + 75 ns
L
,
Preset or Reset to Carry Out
PLH
t
5.0
10
15
—
—
—
550
225
150
1100
450
300
t
t
t
, t = (1.7 ns/pF) C + 465 ns
PHL
PLH PHL L
, t
= (0.66 ns/pF) C + 192 ns
L
PLH PHL
, t
PLH PHL
= (0.5 ns/pF) C + 125 ns
L
Reset Pulse Width
Clock Pulse Width
Clock Pulse Frequency
t
5.0
10
15
380
200
160
190
100
80
—
—
—
ns
ns
w
t
5.0
10
15
350
170
140
200
100
75
—
—
—
WH
f
cl
5.0
10
15
—
—
—
3.0
6.0
8.0
1.5
3.0
4.0
MHz
ns
Preset or Reset Removal Time
t
5.0
10
15
650
230
180
325
115
90
—
—
rem
The Preset or Reset signal must be low prior to a
positive–going transition of the clock.
Clock Rise and Fall Time
t
t
,
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
TLH
THL
Setup Time
t
su
5.0
10
15
260
120
100
130
60
50
—
—
—
ns
Carry In to Clock
Hold Time
t
h
5.0
10
15
0
20
20
– 60
– 20
0
—
—
—
ns
Clock to Carry In
Setup Time
t
su
5.0
10
15
500
200
150
250
100
75
—
—
—
ns
Up/Down to Clock
Hold Time
t
h
5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
—
—
—
ns
Clock to Up/Down
Setup Time
Pn to PE
t
su
5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
—
—
—
ns
Hold Time
PE to Pn
t
h
5.0
10
15
480
420
420
240
210
210
—
—
—
ns
Preset Enable Pulse Width
t
5.0
10
15
200
100
80
100
50
40
—
—
—
ns
WH
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14516B
395
V
DD
500 pF
I
D
0.01
µF
CERAMIC
PE
Q0
CARRY IN
20 ns
20 ns
CLOCK
R
Q1
Q2
Q3
V
DD
90%
UP/DOWN
CLOCK
P0
C
L
50%
PULSE
GENERATOR
10%
V
SS
VARIABLE
WIDTH
C
L
P1
C
L
P2
CARRY
OUT
P3
C
L
C
L
Figure 1. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
P0
4
Q0
6
P1 Q1
12 11
P2
13
Q2
14
P3
3
Q3
2
RESET
9
1
PRESET
ENABLE
CLOCK 15
P
P
P
P
PE
C
Q
PE
C
Q
Q
PE
C
Q
PE
C
Q
CARRY OUT
7
T
Q
T
T
Q
T
Q
CARRY IN
5
UP/DOWN 10
TOGGLE FLIP–FLOP
FLIP–FLOP FUNCTIONAL TRUTH TABLE
Preset
PARALLEL IN
Enable
Clock
T
X
0
Q
n+1
Parallel In
P
PE
C
Q
Q
1
X
0
Q
Q
Q
n
n
n
T
0
1
0
X
X = Don’t Care
MC14516B
396
MOTOROLA CMOS LOGIC DATA
t
t
rem
su
1
t
f
h
cl
CARRY IN OR
UP/DOWN
V
DD
50%
V
V
SS
DD
50%
CLOCK
V
V
SS
DD
t
w(H)
t
w(H)
PRESET ENABLE
V
SS
t
t
TLH
CARRY OUT ONLY
Q
OR CARRY OUT
V
V
0
OH
90%
10%
90%
10%
OL
t
PHL
t
THL
t
PLH
PLH
t
rem
V
V
DD
50%
RESET
SS
t
w
Figure 2. Switching Time Waveforms
PIN DESCRIPTIONS
INPUTS
synchronous output is active low and may also be used to
indicate terminal count.
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active–low input is used when
Cascading stages. Carry In is usually connected to Carry
Out of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or decrem-
ented, depending on the direction of count, on the positive
transition of this input.
CONTROLS
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out–
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count, high
for up count, low for down count.
OUTPUTS
SUPPLY PINS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0 correspond-
ing to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
V
, Negative Supply Voltage, (Pin 8) — This pin is
SS
usually connected to ground.
, Positive Supply Voltage, (Pin 16) — This pin is
V
DD
connected to a positive supply voltage ranging from 3.0 volts
to 18.0 volts.
MOTOROLA CMOS LOGIC DATA
MC14516B
397
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q0
Q5
Q1
Q6
Q2
Q7
Q3
PRESET
ENABLE
0 = COUNT
PE
PE
1 = PRESET
TERMINAL COUNT
INDICATOR
C
C
out
C
out
C
in
in
L.S.D.
MC14516B
M.S.D.
MC14516B
CLOCK
CLOCK
1 = UP
U/D
U/D
0 = DOWN
R
R
P0
P1
P2
P3
P0
P1
P2
P3
P7
P0
P1
P2
P3
P4
P5
P6
+V
+V
DD
DD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK
RESET
RESISTORS = 10 k
+V
DD
OPEN = COUNT
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit(M.S.D.)isdisabledwhileC ishigh. WhenthecountoftheL.S.D. reaches0(countdownmode)orreaches15(count
in
goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
up mode), C
out
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
MC14516B
398
MOTOROLA CMOS LOGIC DATA
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER
MOTOROLA CMOS LOGIC DATA
MC14516B
399
f
out
BUFFER
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q0
Q5
Q1
Q6
Q2
Q7
Q3
PE
PE
C
C
out
C
out
C
in
in
L.S.D.
MC14516B
M.S.D.
MC14516B
CLOCK
CLOCK
U/D
U/D
R
R
P0
P1
P2
P3
P3
P0
P1
P2
P3
P7
P0
P1
P2
P4
P5
P6
+V
+V
DD
DD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
CLOCK (f
)
RESISTORS = 10 k
in
f
n
RESET
in
f
=
out
+V
DD
OPEN = COUNT
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
Figure 4. Programmable Cascaded Frequency Divider
MC14516B
400
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14516B
401
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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are registered
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MC14516B/D
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