MC14519BCPD [MOTOROLA]
4000/14000/40000 SERIES, QUAD 2-INPUT XNOR GATE, PDIP16, PLASTIC, DIP-16;
| 型号： | MC14519BCPD |
| 厂家： | 
MOTOROLA |
| 描述： | 4000/14000/40000 SERIES, QUAD 2-INPUT XNOR GATE, PDIP16, PLASTIC, DIP-16 |
| 文件： | 总6页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14519B is constructed with MOS P–channel and N–channel
enhancement mode devices in a monolithic structure. These complementary
MOS logic gates find primary use where low power dissipation and/or high
noise immunity is desired.
P SUFFIX
PLASTIC
CASE 648
This device provides three functions in one package; a 4–Bit AND/OR
Selector, a Quad 2–Channel Data Selector, or a Quad Exclusive NOR Gate.
D SUFFIX
SOIC
CASE 751B
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Plug–in Replacement for CD4019 in Most Applications
ORDERING INFORMATION
•
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
LOGIC DIAGRAM
T
A
= – 55° to 125°C for all packages.
A
B
9
CONTROL
INPUTS
14
TRUTH TABLE
10 Z0
11 Z1
12 Z2
13 Z3
Control Inputs
Output
X0
Y0
6
7
A
B
Z
n
0
0
1
1
0
1
0
1
0
Y
X
n
n
X1
Y1
4
5
x
Y
n
n
DATA
INPUTS
NOTE: X
Y means X
n
n
n
X2
Y2
2
3
(Exclusive–NOR) Y
n
X3 15
Y3
1
V
V
= PIN 16
= PIN 8
DD
SS
REV 3
1/94
Motorola, Inc. 1995
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
PIN ASSIGNMENT
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
Y3
X2
Y2
X1
Y1
X0
Y0
1
2
16
15
V
DD
X3
B
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
3
4
5
6
7
8
14
13
12
11
10
9
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
Z3
Z2
Z1
Z0
A
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
T
stg
– 65 to + 150
260
T
L
Lead Temperature (8–Second Soldering)
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
V
SS
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
T
I
T
I
T
= (1.2 µA/kHz) f + I
= (2.4 µA/kHz) f + I
= (3.6 µA/kHz) f + I
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
– V ) in volts, f in kHz is input frequency, and k = 0.004.
SS
T
L
DD
MC14519B
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
V
DD
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
TLH THL
, t
TLH THL
L
Propagation Delay Time
t
t
,
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 165 ns
= (0.66 ns/pF) C + 82
= (0.5 ns/pF) C + 65 ns
L
5.0
10
15
—
—
—
250
115
90
500
225
165
PLH PHL
L
L
PHL
, t
PLH PHL
, t
PLH PHL
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
+V
DD
Z0
Z1
V
DD
A
B
PULSE
GENERATOR
V
in
C
C
C
L
L
L
20 ns
20 ns
X0
Y0
V
DD
90%
10%
50% DUTY CYCLE
X1
Y1
V
in
V
SS
X2
Z2
Z3
Y2
X3
Y3
V
SS
C
L
I
SS
500 µF
Figure 1. Dynamic Power Dissipation Test Circuit and Waveform
V
DD
20 ns
INPUT
20 ns
V
V
DD
DD
PULSE
GENERATOR
A
B
Z0
90%
50%
10%
C
C
L
V
V
SS
X0
Y0
X1
Y1
X2
Y2
X3
Y3
t
t
PLH
PHL
Z1
Z2
Z3
OH
L
90%
50%
10%
OUTPUTS
OUTPUT
V
OL
C
C
L
t
THL
t
TLH
t
t
PLH
PHL
V
V
OH
V
SS
L
OUTPUT
50%
OL
Figure 2. Switching Time Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14519B
3
TYPICAL CIRCUIT APPLICATIONS
DATA REGISTER SELECTION COMPARISON
MC14015B
DUAL 4–BIT REGISTER
DATA A
CLOCK A
RESET A
DATA B
CLOCK B
RESET B
4–BIT REGISTER A
Q1 Q2 Q3 Q4
4–BIT REGISTER B
Q1 Q2 Q3 Q4
X0
A
X1
X2
X3
MC14519B
AND/OR SELECT/EXCL NOR
Z1 Z2
Y0
Y1
Y2
Y3
Z3
CONTROL A
CONTROL B
B
Z0
INVERT
MC14070B
QUAD
EXCLUSIVE OR
Q0
Q1
Q2
Q3
CONVERSION TABLE
Output
Operation Code
Function
A
B
INV
Q0
Q1
Q2
Q3
0
0
1
1
0
0
0
0
0
1
0
1
0
1
X0
X0
0
1
X1
X1
0
1
X2
X2
0
1
X3
X3
Inhibit, all zeros
Inhibit, all ones
Control A
Control A and Invert
0
0
1
1
1
1
1
1
0
1
0
1
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Control B
Control B and Invert
Exclusive NOR
Exclusive OR
X0
X0
Y0
Y0
X1
X1
Y1
Y1
X2
X2
Y2
Y2
X3
X3
Y3
Y3
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautionsmust be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V and V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
be left open.
should be constrained to the range V
≤ (V or V ) ≤ V
.
in out
SS
in
out
DD
or V ). Unused outputs must
SS
DD
MC14519B
MOTOROLA CMOS LOGIC DATA
4
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14519B
5
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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are registered
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MC14519B/D
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