MC145202F1R2 [MOTOROLA]
PLL FREQUENCY SYNTHESIZER, 2000MHz, PDSO20, PLASTIC, SO-20;
| 型号： | MC145202F1R2 |
| 厂家： | 
MOTOROLA |
| 描述： | PLL FREQUENCY SYNTHESIZER, 2000MHz, PDSO20, PLASTIC, SO-20 光电二极管 |
| 文件： | 总22页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC145202–1 is recommended for new designs and has improved
suppression of reference sideband spurs. The counters are programmed via
a synchronous serial port which is SPI compatible. The serial port is
byte-oriented to facilitate control via an MCU. Due to the innovative
BitGrabber Plus registers, the MC145202–1 may be cascaded with other
peripherals featuring BitGrabber Plus without requiring leading dummy bits
or address bits in the serial data stream. In addition, BitGrabber Plus
peripherals may be cascaded with existing BitGrabber peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor
tied from the Rx pin to ground. This current can be varied via the serial port.
PLL FREQUENCY
SYNTHESIZER
SEMICONDUCTOR
TECHNICAL DATA
Slew–rate control is provided by a special driver designed for the REF
out
pin. This minimizes interference caused by REF
.
20
out
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external
crystal and a programmable reference output. The R, A, and N counters are
fully programmable. The C register (configuration register) allows the part to
be configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from
being loaded into the counters, on–board circuitry synchronizes the update
of the A register if the A or N counters are loading. Similarly, an update of the
R register is synchronized if the R counter is loading.
1
F SUFFIX
PLASTIC PACKAGE
CASE 751J
(SO–20)
The double–buffered R register allows new divide ratios to be presented
to the three counters (R, A, and N) simultaneously.
PIN CONNECTIONS
• Maximum Operating Frequency: 2000 MHz @ – 10 dBm
• Operating Supply Current: 4 mA Nominal at 3.0 V
REF
1
2
20
19
REF
in
out
LD
D
in
• Operating Supply Voltage Range (V , V , V
Pins): 2.7 to 5.5 V
DD CC PD
φ
3
18 CLK
17 ENB
16
R
• Current Source/Sink Phase Detector Output:
4
φ
V
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V
V
PD
5
Output A
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
15
14
6
PD
Output B
out
Gnd
Rx
Serial Port
7
V
DD
• R Counter Division Range: 1 and 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
8
13 Test 2
9
12
11
V
CC
Test 1
f
in
10
f
in
• Output A Pin, When Configured as Data Out, Permits Cascading of
(Top View)
Devices
• Two General–Purpose Digital Outputs:
Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
EVALUATION KIT
• Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
The P/N MC145202–1EVK, which contains
hardware and software, is available.
• See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for
Offset Reference PLLs for Fine Resolution or Fast Hopping
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
MC145202F1
T
A
= –40 to 85°C
SO–20
MC145202–1
4.2–146
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
BLOCK DIAGRAM
Data Out
20
1
f
REF
in
R
OSC or
4–Stage
Divider
16
13–Stage R Counter
13
Select
Logic
Output A
Port
f
V
(Configurable)
REF
out
3
Double–buffered
BitGrabber R Register
16 Bits
2
Lock Detector
And Control
LD
Rx
18
19
8
6
CLK
Shift
Register
And
Control
Logic
BitGrabber C Register
8 Bits
Phase/Frequency
Detector A And Control
D
in
PD
out
24
Standby
POR
Logic
3
4
17
φ
φ
V
R
Phase/Frequency
Detector B And Control
ENB
2
BitGrabber A Register
24 Bits
Output B
(Open–
Drain
6
12
15
Internal
Control
4
Output)
6–Stage
A Counter
12–Stage
N Counter
11
10
f
in
64/65
Prescaler
Modulus
Control
Logic
Input
AMP
13
9
Test 2
Test 1
f
in
Supply Connections:
Pin 12 = V (V+ To Input AMP and 64/65 Prescaler)
CC
Pin 5 = V (V+ To Phase/Frequency Detectors A and B)
This device contains 7,278 active transistors.
PD
Pin 14 = V (V+ To Balance Of Circuit)
DD
Pin 7 = Gnd (Common Ground)
MC145202–1
4.2–147
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
MAXIMUM RATINGS* (Voltages Referenced to Gnd, unless otherwise stated)
Parameter
DC Supply Voltage (Pins 12 and 14)
DC Supply Voltage (Pin 5)
Symbol
, V
Value
Unit
V
This device contains protection circuitry
to guard against damage due to high static
voltagesorelectricfields. However,precau-
tions must be taken to avoid applications of
any voltage higher than maximum rated
voltages to this high–impedance circuit.
V
–0.5 to 6.0
CC DD
V
PD
V
DD
– 0.5 to 6.0
V
DC Input Voltage
V
in
–0.5 to V
–0.5 to V
+ 0.5
+ 0.5
V
DD
DC Output Voltage (except Output B, PD
,
V
out
V
out
DD
φ , φ )
R
V
DC Output Voltage (Output B, PD , φ , φ )
V
out
–0.5 to V
+ 0.5
V
out
R
V
PD
DC Input Current, per Pin (Includes V
)
I , I
±10
mA
mA
mA
mW
°C
PD
in PD
DC Output Current, per Pin
I
±20
±30
300
out
DD
DC Supply Current, V
and Gnd Pins
I
DD
Power Dissipation, per Package
Storage Temperature
P
D
T
stg
–65 to 150
260
Lead Temperature, 1 mm from Case for 10
Seconds
T
L
°C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.
2. ESD (electrostatic discharge) immunity meets Human Body Model (HBM) ≤2000 V and
Machine Model (MM) ≤200 V. Additional ESD data available upon request.
ELECTRICAL CHARACTERISTICS
(V
DD
= V
= 2.7 to 5.5 V, Voltages Referenced to Gnd, unless otherwise stated; V = 2.7 to 5.5 V, T = –40 to 85°C)
CC
PD A
Guaranteed
Limit
Parameter
Maximum Low–Level Input Voltage
(D , CLK, ENB)
in
Test Condition
Symbol
Unit
V
IL
0.3 x V
V
DD
DD
Minimum High–Level Input Voltage
(D , CLK, ENB)
in
V
IH
0.7 x V
V
mV
Minimum Hysteresis Voltage (CLK, ENB)
V
DD
V
DD
= 2.7 V
= 4.5 V
V
Hys
100
250
Maximum Low–Level Output Voltage
(REF , Output A)
out
I
= 20 µA, Device in Reference Mode
V
0.1
V
out
OL
OH
OL
OL
OL
OL
Minimum High–Level Output Voltage
(REF , Output A)
out
I
= – 20 µA, Device in Reference Mode
V
V
– 0.1
V
out
DD
Minimum Low–Level Output Current
(REF , LD)
out
V
= 0.3 V
= 0.3 V
= 0.4 V
I
I
I
I
0.36
mA
out
Minimum Low–Level Output Current
V
0.36
1.0
mA
out
(φ , φ )
R
V
Minimum Low–Level Output Current
(Output A)
V
V
mA
out
DD
= 4.5 V
Minimum Low–Level Output Current
(Output B)
V
= 0.4 V
1.0
mA
out
Minimum High–Level Output Current
(REF , LD)
out
V
= V
= V
= V
– 0.3 V
– 0.3 V
– 0.4 V
I
I
I
–0.36
–0.36
–0.6
mA
out
DD
PD
DD
OH
OH
OH
Minimum High–Level Output Current
V
out
mA
(φ , φ )
R
V
Minimum High–Level Output Current
(Output A Only)
V
mA
out
V
DD
= 4.5 V
(continued)
MC145202–1
4.2–148
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
ELECTRICAL CHARACTERISTICS (continued)
Guaranteed
Limit
Parameter
Test Condition
Symbol
Unit
Maximum Input Leakage Current
V
V
= V
= V
or Gnd, Device in XTAL Mode
I
±1.0
µA
in
DD
DD
in
(D , CLK, ENB, REF )
in
in
Maximum Input Current
(REF )
in
or Gnd, Device in Reference Mode
I
in
±100
µA
in
Maximum Output Leakage Current (PD
)
V
= V
or Gnd, Output in Floating State
I
OZ
±130
±1
nA
µA
µA
out
out
PD
PD
(Output B)
Maximum Standby Supply Current
V
out
= V
or Gnd, Output in High–Impedance State
V
in
= V
or Gnd; Outputs Open; Device in Standby Mode,
I
STBY
30
DD
(V + V Pins)
Shut–Down Crystal Mode or REF –Static–Low Reference
DD
PD
out
per Figure 21
Mode; Output B Controlling V
CC
Bit C6 = High Which Selects Phase Detector A,
PD = Open, PD = Static State, Bit C4 = Low Which is
Maximum Phase Detector
Quiescent Current (V
I
750
30
µA
PD
Pin)
PD
out
out
not Standby, I = 170 µA, V
= 5.5 V
PD
Rx
Bit C6 = Low Which Selects Phase Detector B, φ and
R
φ
= Open, φ and φ = Static Low or High, Bit
R V
V
C4 = Low Which is not Standby
Total Operating Supply Current
(V + V + V Pins)
f
= 2.0 GHz; REF = 13 MHz @ 1 V
;
I
T
[Note]
mA
in
in pp
Output A = Inactive and No Connect; V
REF , φ , φ , PD , LD = No Connect;
D , ENB, CLK = V
(Bit C6 = Low)
= V ,
CC
DD
PD
CC
DD
out
V
R
out
DD
or Gnd, Phase Detector B Selected
in
NOTE: The nominal values are: 4 mA at V
= V
= V
= 3.0 V; 6 mA at V
DD
= V
= V
= 5.0 V. These are not guaranteed limits.
PD
DD
CC
PD
CC
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PD
out
(I
out
≤ 1 mA @ V
= 2.7 V and I
≤ 1.7mA @ V
≥ 4.5 V, V
= V
= 2.7 to 5.5 V, Voltages Referenced to Gnd)
DD
out
DD
DD
CC
Guaranteed
Limit
Parameter
Test Condition
V
PD
Unit
Maximum Source Current Variation (Part–to–Part)
Maximum Sink–vs–Source Mismatch [Note 3]
Output Voltage Range [Note 3]
V
= 0.5 x V
= 0.5 x V
2.7
4.5
5.5
2.7
4.5
5.5
2.7
4.5
5.5
±15
%
out
PD
±15
±15
V
out
11
%
V
PD
11
11
I
I
I
Variation ≤ 15%
Variation ≤ 20%
Variation ≤ 22%
0.5 to 2.2
0.5 to 3.7
0.5 to 4.7
out
out
out
NOTES: 1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within –40 to 85°C.
MC145202–1
4.2–149
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
AC INTERFACE CHARACTERISTICS
(V
DD
= V
= 2.7 to 5.5 V, T = – 40 to + 85°C, C = 25 pF, Input t = t = 10 ns; V = 2.7 to 5.5 V)
CC
A
L
r
f
PD
Figure
No.
Guaranteed
Limit
Parameter
Serial Data Clock Frequency (Note: Refer to Clock t below)
Symbol
Unit
MHz
ns
1
f
dc to 4.0
100
w
clk
Maximum Propagation Delay, CLK to Output A (Selected as Data Out)
Maximum Propagation Delay, ENB to Output A (Selected as Port)
Maximum Propagation Delay, ENB to Output B
1, 5
t
t
, t
PLH PHL
2, 5
, t
150
ns
PLH PHL
2, 6
t
, t
150
ns
PZL PLZ
Maximum Output Transition Time, Output A and Output B; t
only, on Output B
THL
1, 5, 6
t
, t
50
ns
TLH THL
Maximum Input Capacitance – D , ENB, CLK
in
C
10
pF
in
TIMING REQUIREMENTS
(V
DD
= V
= 2.7 to 5.5 V, T = – 40 to + 85°C, Input t = t = 10 ns, unless otherwise indicated)
CC A r f
Figure
No.
Guaranteed
Limit
Parameter
Minimum Setup and Hold Times, D vs CLK
Symbol
Unit
ns
3
4
4
1
1
t , t
su
50
100
in
h
Minimum Setup, Hold and Recovery Times, ENB vs CLK
Minimum Pulse Width, ENB
t
, t , t
ns
su
h
rec
t
[Note]
125
cycles
ns
w
w
Minimum Pulse Width, CLK
t
Maximum Input Rise and Fall Times, CLK
t , t
r f
100
µs
NOTE: The minimum limit is 3 REF cycles or 195 f cycles, whichever is greater.
in in
MC145202–1
4.2–150
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
t
t
r
f
V
DD
V
50%
DD
90%
50%
10%
ENB
CLK
Gnd
Gnd
t
t
PHL
PLH
t
w
t
w
1/f
clk
Output A
Output B
50%
t
t
PHL
PLH
t
t
PZL
PLZ
90%
50%
10%
Output A
(Data Out)
50%
10%
t
t
THL
TLH
Figure 3.
Figure 4.
t
w
t
w
V
DD
Valid
ENB
CLK
50%
V
DD
Gnd
50%
t
D
in
t
su
t
h
Gnd
t
rec
V
DD
t
su
h
V
DD
50%
First
CLK
50%
CLK
Last
CLK
Gnd
Gnd
Figure 5.
Figure 6.
+V
PD
Test Point
C
Test Point
7.5 kΩ
Device
Under
Test
Device
Under
Test
*
*
C
L
L
* Includes all probe and fixture capacitance.
* Includes all probe and fixture capacitance.
MC145202–1
4.2–151
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
LOOP SPECIFICATIONS (V
= V
= 2.7 to 5.5 V unless otherwise indicated, T = –40 to 85°C)
DD
CC
A
Guaranteed
Operating
Range
Fig.
No.
Parameter
Test Condition
Symbol
Unit
dBm*
MHz
Min
Max
Input Sensitivity Range, f
500 MHz ≤ f ≤ 2000 MHz
7
P
– 10
4
in
in
in
Input Frequency, REF Externally Driven in
in
V
in
≥ 400 mVpp
2.7 ≤ V
4.5 ≤ V
< 4.5 V
≤ 5.5 V
8
f
1.5
1.5
20
30
DD
DD
ref
Reference Mode
Crystal Frequency, Crystal Mode
C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray
Capacitance
9
f
2
15
MHz
XTAL
Output Frequency, REF
out
C
= 20 pF, V
out
≥ 1 V
10, 12
f
out
dc
dc
10
2
MHz
MHz
L
pp
Operating Frequency of the Phase Detectors
Output Pulse Width (φ , φ , and LD)
f
φ
f
R
in Phase with f , C = 20 pF, φ and φ
11, 12
t
w
R
V
V
L
R
V
active for LD measurement, **
= 2.7 to 5.5 V
V
PD
V
V
V
= 2.7 V
= 4.5 V
= 5.5 V
40
18
14
120
60
50
ns
DD
DD
DD
Output Transition Times (LD, φ , and φ )
C
= 20 pF, V
= 2.7 V,
= 2.7 V
11, 12
t ,
TLH
THL
—
80
7
ns
V
R
L
PD
V
DD
= V
t
CC
Input Capacitance, REF
C
—
pF
in
in
*Power level at the input to the dc block.
**When PD
is active, LD minimum pulse width is approximately 5 ns.
out
Figure 7. Test Circuit
Figure 8. Test Circuit — Reference Mode
Sine Wave
Generator
DC
Block
Test
Point
50 Ω PAD
0.01 µF
Output A
Device
Under
Test
Test
Point
f
Sine Wave
Generator
in
REF
Output A
in
(f )
V
50 Ω
(f )
R
Device
Under
Test
V
in
f
in
50 Ω
Test
Point
V
Gnd
V
DD
REF
out
CC
V
CC
Gnd V
V+
DD
V+
NOTE: Alternately, the 50 Ω pad may be a T network.
Figure 9. Test Circuit — Crystal Mode
Figure 10. Switching Waveform
1/f REF
out
Test
Point
REF
in
Output A
C1
C2
REF
out
(f )
R
50%
Device Under
Test
REF
out
V
Gnd V
CC
DD
V+
Figure 12. Test Circuit
Test Point
Device
Under
Test
Figure 11. Switching Waveform
*
C
L
t
w
90%
10%
Output
50%
* Includes all probe and fixture capacitance.
t
t
TLH
THL
MC145202–1
4.2–152
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
Figure 13. Normalized Input Impedance at f — Series Format (R + jx)
in
f
(PIN 11)
in
SOG PACKAGE
4
4
1
1
3
3
2
2
3 V
5 V
Table 1. Input Impedence at f — Series Format (R + jx), V
in
= 3 V
CC
Frequency
(GHz)
Resistance
Reactance
Capacitance/
Inductance
(Ω)
(Ω)
Marker
1
2
3
4
0.5
1
11.4
12.4
19.8
18.1
–168
–59.4
–34.9
9.43
1.9 pF
2.68 pF
3.04 pF
751 pH
1.5
2
Table 2. Input Impedence at f — Series Format (R + jx), V
in
= 5 V
CC
Frequency
(GHz)
Resistance
Reactance
Capacitance/
Inductance
(Ω)
(Ω)
Marker
1
2
3
4
0.5
1
11.8
11.5
22.2
18.4
–175
–64.4
–36.5
1.14
1.82 pF
2.47 pF
2.91 pF
90.4 pH
1.5
2
MC145202–1
4.2–153
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
PIN DESCRIPTIONS
CLK
DIGITAL INTERFACE PINS
Serial Data Clock Input (Pin 18)
Low–to–high transitions on CLK shift bits available at the
pin, while high–to–low transitions shift bits from Output A
D
in
Serial Data Input (Pin 19)
D
in
(when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A
register. See Table 3 and Figures 14, 15, and 16. The number
of clocks required for cascaded devices is shown in Figures
23 through 25.
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 3). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
CAUTION
CLK typically switches near 50% of V
and has a
DD
Schmitt–triggered input buffer. Slow CLK rise and fall times
The value programmed for the N counter must be
greater than or equal to the value of the A counter.
are allowed. See the last paragraph of D
information.
for more
in
The 13 least significant bits (LSBs) of the R register are
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not
double–buffered and have an immediate effect after a 16–bit
transfer.) The second buffer of the R register contains the 13
bits for the R counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24–bit transfer). This allows presenting new values to the R,
A, and N counters simultaneously. If this is not required, then
the 16–bit transfer may be followed by pulsing ENB low with
no signal on the CLK pin. This is an alternate method of
transferring data to the second buffer of the R register (see
Figure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber Plus registers. Therefore, all bits
in the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V. The formats are
shown in Figures 14, 15, and 16.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
Gnd (with ENB being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK
being a don’t care) during power–up. Floating,
toggling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
Afterthesetwoaccesses, thetwocascadedchips
perform normally.
ENB
Active Low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an
inactive high state, shifting is inhibited and the port is held in
the initialized state. To transfer data to the device, ENB
(which must start inactive high) is taken low, a serial transfer
D
typically switches near 50% of V
to maximize noise
in
DD
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
is made via D and CLK, and ENB is taken back high. The
in
low–to–high transition on ENB transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 3.
the resistor are worst–case I
maximum tolerable power consumption, and maximum data
rate.
of the driving device,
OL
Transitions on ENB must not be attempted while CLK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and CLK is low.
Table 3. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
This input is also Schmitt–triggered and switches near
Number
of Clocks
Accessed
Register
Bit
50% of V , thereby minimizing the chance of loading
DD
Nomenclature
erroneous data into the registers. See the last paragraph of
D
for more information.
in
For POR information, see the note for the CLK pin.
8
16
24
C Register
R Register
A Register
Not Allowed
See Figures
22 – 25
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
Other Values ≤ 32
Values > 32
MC145202–1
4.2–154
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
Output A
crystal. Frequency–setting capacitors of appropriate values,
Configurable Digital Output (Pin 16)
as recommended by the crystal supplier, are connected from
each of the two pins to ground (up to a maximum of 30 pF
each, including stray capacitance). An external resistor of
1 MΩ to 15 MΩ is connected directly across the pins to
ensure linear operation of the amplifier. The required
connections for the components are shown in Figure 9.
To turn on the oscillator, bits R15, R14, and R13 must have
an octal value of one (001 in binary, respectively). This is the
active–crystal mode shown in Figure 16. In this mode, the
crystal oscillator runs and the R Counter divides the crystal
frequency, unless the part is in standby. If the part is placed in
standby via the C register, the oscillator runs, but the R
counter is stopped. However, if bits R15 to R13 have a value
of 0, the oscillator is stopped, which saves additional power.
This is the shut–down crystal mode (shown in Figure 16) and
can be engaged whether in standby or not.
Output A is selectable as f , f , Data Out, or Port. Bits A22
R V
and A23 in the A register control the selection; see Figure 15.
If A23 = A22 = high, Output A is configured as f . This
signal is the buffered output of the 13–stage R counter. The
R
f
R
signal appears as normally low and pulses high. The f
R
signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits R0–R12 in the R register. Also,
direct access to the phase detectors via the REF pin is
allowed by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate is
in
2 MHz. Therefore, the frequency of f should not exceed
R
2 MHz.
If A23 = high and A22 = low, Output A is configured as f .
This signal is the buffered output of the 12–stage N counter.
V
In the reference mode, REF (Pin 20) accepts a signal
in
The f signal appears as normally low and pulses high. The
V
from an external reference oscillator, such as a TCXO. A
f
V
signal can be used to verify the operation of the prescaler,
signal swinging from at least the V to V levels listed in the
IL IH
A counter, and N counter. The divide ratio between the f
in
Electrical Characteristics table may be directly coupled to the
pin. If the signal is less than this level, ac coupling must be
used as shown in Figure 8. Due to an on–board resistor
which is engaged in the reference modes, an external biasing
input and the f signal is N × 64 + A. N is the divide ratio of the
V
N counter and A is the divide ratio of the A counter. These
ratios are determined by bits loaded into the A register. See
Figure 15. The maximum frequency at which the phase
resistor tied between REF and REF
With the reference mode, the REF
the output of a divider. As an example, if bits R15, R14, and
is not required.
pin is configured as
in
out
out
detectors operate is 2 MHz. Therefore, the frequency of f
should not exceed 2 MHz.
V
If A23 = low and A22 = high, Output A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, Output A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, Output A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port bit
(C1) of the C register is low, and high when the Port bit is
high.
R13 have an octal value of seven, the frequency at REF
is
out
the REF frequency divided by 16. In addition, Figure 16
in
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REF
pin is listed
in the Loop Specifications table for an output swing of 1 V
out
pp
and 20 pF loads. Therefore, for higher REF frequencies, the
in
one–to–one ratio may not be used for this magnitude of
signal swing and loading requirements. Likewise, for REF
frequencies above two times the highest rated frequency, the
ratio must be more than two.
in
Output B
The output has a special on–board driver that has
slew–rate control. This feature minimizes interference in the
application.
Open–Drain Digital Output (Pin 15)
This signal is a general–purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (C0) of the C register is low. When the Out B bit
is high, Output B assumes the high–impedance state. Output
B may be pulled up through an external resistor or active
circuitry to any voltage less than or equal to the potential of
If REF
is unused, an octal value of two should be used
out
for R15, R14, and R13 and the REF
pin should be floated.
out
A value of two allows REF to be functional while disabling
REF , which minimizes dynamic power consumption.
in
out
the V
pin is 5.5 V.
pin. Note: the maximum voltage allowed on the V
PD
PD
LOOP PINS
Upon power–up, power–on reset circuitry forces Output B
to a low level.
f
and f
in
in
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These
pins feed the on–board RF amplifier which drives the 64/65
prescaler. These inputs may be fed differentially. However,
they are usually used in a single–ended configuration (shown
in Figure 7). Note that f is driven while f must be tied to
REFERENCE PINS
REF and REF
in
out
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–resonant
in
in
ground via a capacitor.
Motorola does not recommend driving f while terminating
in
f
in
because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
MC145202–1
4.2–155
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
PD
feature. Note that when disabled or in standby, φ and φ are
out
R V
Single–Ended Phase/Frequency Detector Output (Pin 6)
forced to their rest condition (high state).
The φ and φ output signal swing is approximately from
R
PD
V
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a
linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
POL bit (C7) in the C register = low (see Figure 14)
Frequency of f > f or Phase of f Leading f
current–sinking pulses from a floating state
Frequency of f < f or Phase of f Lagging f
current–sourcing pulses from a floating state
Frequency and Phase of f = f : essentially a floating
state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of f > f or Phase of f Leading f
current–sourcing pulses from a floating state
Frequency of f < f or Phase of f Lagging f
Gnd to V
.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (f and f of the
R
V
same phase and frequency). The output pulses low when f
V
:
:
V
R
V
R
R
and f are out of phase or different frequencies. LD is the
R
logical ANDing of φ and φ (see Figure 17).
R
V
V
R
V
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip
initialization circuitry disables LD to a static low logic level to
prevent a false “lock” signal. If unused, LD should be disabled
and left open.
V
R
:
:
V
R
V
R
R
The LD output signal swing is approximately from Gnd to
V
.
DD
V
R
V
current–sinking pulses from a floating state
Frequency and Phase of f = f : essentially a floating
state; voltage at pin determined by loop filter
Rx
V
R
External Resistor (Pin 8)
A resistor tied between this pin and Gnd, in conjunction
with bits in the C register, determines the amount of current
This output can be enabled, disabled, and inverted via the
C register. If desired, PD
high–impedance state by utilization of the disable feature in
the C register (bit C6). This is a patented feature. Similarly,
can be forced to the
out
that the PD
pin sinks and sources. When bits C2 and C3
out
are both set high, the maximum current is obtained at PD
;
out
see Tables 4 and 5 for other current values. The
PD
is forced to the high–impedance state when the device
out
is put into standby (STBY bit C4 = high).
The PD circuit is powered by V . The phase detector
recommended value for Rx is 3.9 kΩ (preliminary). A value of
3.9 kΩ provides current at the PD
pin of approximately 1
out
= 3 V and approximately 1.7 mA @ V
out
PD
gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PD current divided by 2π.
mA @ V
= 5 V in
DD
DD
the 100% current mode. Note that V , not V , is a factor in
DD PD
out
and φ (Pins 3 and 4)
determining the current.
φ
When the φ and φ outputs are used, the Rx pin may be
R
V
R
V
Double–Ended Phase/Frequency Detector Outputs
floated.
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized by
a linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
Figure 17.
Table 4. PD
Current*, C1 = Low with
out
Output A not Selected as “Port”;
Also, Default Mode When Output A
Selected as “Port”
Bit C3
Bit C2
PD
Current*
out
0
0
1
1
0
1
0
1
70%
80%
90%
POL bit (C7) in the C register = low (see Figure 14)
Frequency of f > f or Phase of f Leading f : φ
=
=
V
R
V
R
V
100%
negative pulses, φ = essentially high
R
Frequency of f < f or Phase of f Lagging f : φ
V
R
R
V
R
V
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
essentially high, φ = negative pulses
Frequency and Phase of f = f : φ and φ remain
essentially high, except for a small minimum time period
when both pulse low in phase
V
R
V
R
Table 5. PD
Current*, C1 = High with
Output A not Selected as “Port”
out
POL bit (C7) = high
Frequency of f > f or Phase of f Leading f : φ
=
=
Bit C3
Bit C2
PD
Current*
V
R
V
R
R
out
negative pulses, φ = essentially high
V
0
0
1
1
0
1
0
1
25%
50%
75%
Frequency of f < f or Phase of f Lagging f : φ
V
R
V
V
R
R
essentially high, φ = negative pulses
Frequency and Phase of f = f : φ and φ remain
essentially high, except for a small minimum time period
when both pulse low in phase
V
R
V
R
100%
* At the time the data sheet was printed, only the 100%
current mode was guaranteed. The reduced current
modes were for experimentation only.
These outputs can be enabled, disabled, and
interchanged via C register bits C6 or C4. This is a patented
MC145202–1
4.2–156
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
TEST POINT PINS
For optimum performance, V should be bypassed to
DD
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
Test 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
V
CC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65
prescaler. The voltage range is 2.7 to 5.5 V with respect to
CAUTION
the Gnd pin. In standby mode, the V
pin still draws a few
CC
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
milliamps from the power supply. This current drain can be
eliminated with the use of transistor Q1 as shown in
Figure 21.
For optimum performance, V
should be bypassed to
Test 2
CC
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
Prescaler Output (Pin 13)
This pin may be used to access the on–board 64/65
prescaler output.
CAUTION
V
PD
This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin may be more or less
than the potential applied to the V
and V
pins. The
DD
is 2.7 to 5.5 V with respect to the Gnd
CC
voltage range for V
pin.
PD
POWER SUPPLY PINS
V
For optimum performance, V
should be bypassed to
DD
PD
Positive Power Supply (Pin 14)
Gnd using a low–inductance capacitor mounted very close to
these pins. Lead lengths on the capacitor should be
minimized.
This pin supplies power to the main CMOS digital portion
of the device. Also, this pin, in conjunction with the Rx
resistor, determines the internal reference current for the
PD
the Gnd pin.
Gnd
Ground (Pin 7)
pin. The voltage range is 2.7 to 5.5 V with respect to
out
Common ground.
MC145202–1
4.2–157
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
Figure 14. C Register Access and Format
(8 Clock Cycles are Used)
ENB
CLK
NOTE
1
2
3
4
5
6
7
8
MSB
C7
LSB
C0
C6
C5
C4
C3
C2
C1
D
in
NOTE: At this point, the new byte is transferred to the C register and stored. No other
registers are affected.
C7 – POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PD
out
and interchanges the φ function with φ as depicted in Figure 17. Also see the phase detector output
R
V
pin descriptions for more information. This bit is cleared low at power up.
C6 – PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PD ) and disables phase/frequency detector B by forcing φ and φ
out
R
V
to the static high state. When cleared low, phase/frequency detector B is enabled (φ and φ ) and
R
V
phase/frequency detector A is disabled with PD
cleared low at power up.
forced to the high–impedance state. This bit is
out
C5 – LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.
C4 – STBY: When set, places the CMOS section of device, which is powered by the V
and V
pins, in the
DD
PD
standby mode for reduced power consumption: PD
is forced to the high–impedance state, φ and
out
R
φ
are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
V
off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REF
= static low is selected, the internal feedback resistor is disconnected and the input is inhibited
out
when in standby; in addition, the REF input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
in
When C4 is reset low, the part is taken out of standby in two steps. First, the REF (only in one
in
mode) resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any f and
R
f
V
signals are inhibited from toggling the phase/frequency detectors and lock detector. Second, when
the first f pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
V
At this point, the f and f pulses are enabled to the phase and lock detectors. (Patented feature.)
R
V
C3, C2 – I2, I1: Controls the PD
out
source/sink current per Tables 4 and 5. With both bits high, the maximum current
is available. Also, see C1 bit description.
C1 – Port: When the Output A pin is selected as “Port” via bits A22 and A23, C1 determines the state of Output
A. When C1 is set high, Output A is forced high; C1 low forces Output A low. When Output A is
not selected as “Port,” C1 controls whether the PD
5.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when Output A is
selected as “Port.” The Port bit is not affected by the standby mode.
step size is 10% or 25%. (See Tables 4 and
out
C0 – Out B: Determines the state of Output B. When C0 is set high, Output B is high–impedance; C0 low forces
Output B low. The Out B bit is not affected by the standby mode. This bit is cleared low at power
up.
MC145202–1
4.2–158
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
Figure 15. A Register Access and Format
(24 Clock Cycles are Used)
ENB
CLK
Note 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSB
LSB
D
in
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
÷
÷
÷
÷
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Not Allowed
0
0
0
0
.
.
.
0
1
2
3
.
.
.
A COUNTER =
A COUNTER =
A COUNTER =
A COUNTER =
0
1
2
3
1
1
Not Allowed
Not Allowed
Both Bits
Must Be
Not Allowed
Not Allowed
High
Port
Data Out
f V
÷
÷
÷
0
0
1
1
0
1
0
1
N COUNTER =
N COUNTER =
N COUNTER =
5
6
7
÷
3
3
E
F
A COUNTER = 62
A COUNTER = ÷63
f R
.
.
.
.
.
.
.
.
.
4
4
0
1
Not Allowed
Not Allowed
.
.
.
.
.
.
Binary
Value
Output A
Function
(Note 1)
F
F
F
F
E
F
N COUNTER = ÷4094
N COUNTER = 4095
÷
F
F
Not Allowed
Hexadecimal Value
For N Counter
Hexadecimal Value
For A Counter
NOTES:
1. A power-on initialize circuit forces the Output A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register’s second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.
MC145202–1
Figure 16. R Register Access and Format
(16 Clock Cycles are Used)
ENB
CLK
Note
4
Note
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MSB
R15
LSB
R0
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D
in
0
1
2
Crystal Mode, Shut Down
Crystal Mode, Active
0
0
0
0
0
0
0
0
0
·
0
0
0
0
0
0
0
0
0
·
0
0
Not Allowed
R COUNTER = ÷ 1 (Note 6)
Not Allowed
Not Allowed
Not Allowed
R COUNTER = ÷5
R COUNTER = ÷6
R COUNTER = ÷7
R COUNTER = ÷8
0
0
0
0
0
0
0
0
·
1
2
3
4
5
6
7
8
·
Reference Mode, REF Enabled and REF
in
out
Static Low
3
4
5
6
7
Reference Mode, REF = REF (Buffered)
out in
Reference Mode, REF = REF /2
out in
Reference Mode, REF = REF /4
out in
Reference Mode, REF = REF /8 (Note 3)
out in
Reference Mode, REF = REF /16
out in
·
·
·
·
·
·
·
·
Octal Value
1
1
F
F
F
F
E
F
R COUNTER = ÷8190
R COUNTER = ÷8191
Binary Value
Hexadecimal Value
NOTES:
1
2
3
4
Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
A power–on initialize circuit forces a default REF to REF
ratio of eight.
in
out
At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12
are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet
and retains the previous ratio loaded. The C and A registers are not affected.
5
6
Optional load pulse. At this point, bits R0 – R12 are transferred to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A
registers are not affected. The first buffer of the R register is not affected. Also, see Note 3 of Figure 15 for an alternate method of loading
the second buffer in the R register.
Allows direct access to reference input of phase/frequency detectors.
MC145202–1
4.2–160
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
Figure 17. Phase/Frequency Detectors and Lock
Detector Output Waveforms
f
R
Reference
REF ÷ R
V
H
in
V
L
f
V
Feedback
V
H
f
in
÷ (N x 64 + A)
V
L
*
Sourcing Current
Float
PD
out
Sinking Current
V
H
φ
R
V
L
V
H
φ
V
V
L
V
H
V
L
LD
V = High voltage level
H
V = Low voltage level
L
*At this point, when both f and f are in phase, the output source and sink circuits are turned on for a short interval.
R
V
NOTE: The PD either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output is in the floating condition and
out
the voltage at that pin is determined by the low–pass filter capacitor. PD , φ , and φ are shown with the polarity bit (POL) = low; see Figure 14 for POL.
out
R
V
MC145202–1
4.2–161
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
DESIGN CONSIDERATIONS
Crystal Oscillator Considerations
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
The following options may be considered to provide a
reference frequency to Motorola’s CMOS frequency
synthesizers.
frequency (f ) at Output A as a function of supply voltage.
R
Use of a Hybrid Crystal Oscillator
(REF
is not used because loading impacts the oscillator.)
out
Commercially available temperature–compensated
crystal oscillators (TCXOs) or crystal–controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of CMOS logic levels at the output may be
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in
frequency or becomes unstable with an increase in supply
voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start–up time is
proportional to the value of R1.
direct or dc coupled to REF . If the oscillator does not have
in
CMOS logic levels on the outputs, capacitive or ac coupling
to REF may be used (see Figure 8).
in
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 2).
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications. The reference signal is usually ac
Figure 18. Pierce Crystal Oscillator Circuit
Frequency Synthesizer
coupled to REF (see Figure 8). For large amplitude signals
in
(standard CMOS logic levels), dc coupling may be used.
Use of the On–Chip Oscillator Circuitry
REF
in
REF
out
R
f
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference
source frequency. A fundamental mode crystal, parallel
resonant at the desired operating frequency, should be
connected as shown in Figure 18.
R1*
C1
C2
The crystal should be specified for a loading capacitance
* May be needed in certain cases. See text.
(C ) which does not exceed approximately 20 pF when used
at the highest operating frequencies listed in the Loop
L
Specifications table. Assuming R1 = 0 Ω, the shunt load
capacitance (C ) presented across the crystal can be
L
estimated to be:
Figure 19. Parasitic Capacitances of the
Amplifier and C
stray
C C
in out
C1 • C2
C1 + C2
C =
L
+ C + C
+
stray
a
C
a
C
+ C
in
out
REF
in
REF
out
where
C
in
C
out
C
= 5 pF (see Figure 19)
= 6 pF (see Figure 19)
in
C
out
C = 1 pF (see Figure 19)
C
stray
a
C1 and C2 = external capacitors (see Figure 18)
C
= the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
stray
Figure 20. Equivalent Crystal Networks
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
C
S
R
S
L
S
1
2
1
2
REF
and REF
pins to minimize distortion, stray
in
out
capacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
C
O
appropriate stray value to the values for C and C . For this
in out
X
e
R
e
approach, the term C
becomes 0 in the above expression
2
stray
1
for C .
L
Power is dissipated in the effective series resistance of the
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
crystal, R , in Figure 20. The maximum drive level specified
e
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
MC145202–1
4.2–162
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
RECOMMENDED READING
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May 1966.
Technical Note TN–24, Statek Corp.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June 1969.
Table 6. Partial List of Crystal
Manufacturers
CTS Corp.
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend
one supplier over another and in no
way suggests that this is a complete
listing of crystal manufacturers.
MC145202–1
4.2–163
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
K K
φ VCO
NC
PD
out
(A)
VCO
ω
=
n
R
C
ω RC
K K
C
R
2
n
φ VCO
ζ =
=
N
2
1 + sRC
sC
Z(s) =
NOTE:
For(A),usingK inampsperradianwiththefilter’simpedancetransferfunction,Z(s),maintainsunitsofvoltsperradianforthedetector/filter
φ
combination.AdditionalsidebandfilteringcanbeaccomplishedbyaddingacapacitorC′ acrossR. Thecornerω =1/RC′ shouldbechosen
c
such that ω is not significantly affected.
n
R
2
K K
φ VCO
(B)
ω
=
n
NCR
R
C
1
1
φ
R
–
ω R C
n 2
2
A
VCO
φ
ζ =
+
V
R
1
R
2
Assuming Gain A is very large, then:
R sC + 1
2
C
F(s) =
R sC
1
NOTE:
For(B),R isfrequentlysplitintotwoseriesresistors;eachresistorisequaltoR dividedby2.AcapacitorC isthenplacedfromthemidpoint
1
1
C
to ground to further filter the error pulses. The value of C should be such that the corner frequency of this network does not significantly
C
affect ω .
n
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K
φ
K
φ
(Phase Detector Gain) = I
(Phase Detector Gain) = V /2π volts per radian for φ and φ
/2π amps per radian for PD
PDout
PD
out
R
V
2π∆f
VCO
K
VCO
(VCO Transfer Function) =
radians per volt
∆V
VCO
For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ω ≈ (2πf /50) where f
R
n
R
is the frequency at the phase detector input. Larger ω values result in faster loop lock times and, for similar sideband filtering, higher f –related
n
R
VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate f –related VCO sidebands. This additional
R
filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1253, An Improved PLL Design Method Without ω and ζ, Motorola Semiconductor Products, Inc., 1995.
n
MC145202–1
4.2–164
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
MC145202–1
Figure 21. Example Application
Threshold
Detector
+3 V
MCU
20
1
2
REF
LD
REF
in
out
19
18
D
in
Integrator
3
φ
R
CLK
ENB
17
16
4
φ
V
5
General–purpose
Digital Output
+ 3 V
V
PD
Output A
Output B
6
15
14
Low–pass
Filter
PD
out
+3 V
7
V
DD
Gnd
Rx
8
13
12
11
NC
Q1
Test 2
Note 2
9
V
CC
NC
Test 1
10
f
in
f
in
1000 pF
UHF
VCO
UHF Output
Buffer
NOTES:
1
When used, the φ and φ outputs are fed to an external combiner/loop filter. See the Phase–
R V
Locked Loop — Low–Pass Filter Design (Page 4.2–142) for additional information.
Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, Output B. If the standby
feature is not needed, tie Pin 12 directly to the power supply.
2
3
4
Foroptimumperformance,bypasstheV , V , andV
pacitors.
pinstoGndwithlow–inductanceca-
PD
CC DD
TheR counter is programmed for a divide value = REF /f . Typically, f is the tuning resolution
in
R
R
required for the VCO. Also, the VCO frequency divided by f = N = N x 64 + A; this determines
R
T
the values (N, A) that must be programmed into the N and A counters, respectively.
Figure 22. Cascading Two Devices
Device #1
(MC145193 or MC145202–1)
Device #2
(MC145193 or MC145202–1)
Output A
(Data Out)
Output A
(Data Out)
D
in
CLK
ENB
D
in
CLK
ENB
CMOS
MCU
Optional
NOTE: See related Figures 23, 24, and 25.
MC145202–1
4.2–165
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA
Figure 23. Accessing the C Registers of
Two Cascaded MC145193 or MC145202–1 Devices
ENB
CLK
1
2
7
8
9
10
15
16
17
18
23
24
25
26
31
32
C7
C6
C0
X
X
X
X
X
X
C7
C6
C0
D
in
C Register Bits of Device #2
in Figure 22
C Register Bits of Device #1
in Figure 22
*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.
Figure 24. Accessing the A Registers of
Two Cascaded MC145193 or MC145202–1 Devices
ENB
1
2
7
8
9
15
16
17
23
24
25
31
32
38
39
40
47
48
A0
CLK
D
in
A23
A22
A16
A15
A8
A7
A0
A23
A16
A9
A8
A Register bits of Device #2
in Figure 22
A Register Bits of Device #1
in Figure 22
* At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the
13 LSBs in each of the first buffers of the R registers are transferred to the respective R register’s second buffer. Thus, the
R, N, and A counter can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.
Figure 25. Accessing the R Registers of Two Cascaded
MC145193 or MC145202–1 Devices
ENB
CLK
Note 1 Note 2
1
2
7
8
9
15
16
17
23
24
25
31
32
33
39
40
D
in
R15
R14
R8
R7
R0
X
X
R15
R8
R7
R0
R Register Bits of Device #2
in Figure 22
R Register Bits of Device #1
in Figure 22
Notes Applicable to Each Device:
1. At this point, bits R13, R14 and R15 are stored and sent to the ‘‘OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register. Therfore, the R counter divide is not altered yet and
retains the previous ratio loaded. The C and A registers are not affected.
2. Optional load pulse. At this point, the bits R0 through R12 are transfered to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A registers
are not affected. The first buffer of the R register is not affected. Also, see note of Figure 24 for an alternate method of loading the second
buffer in the R register.
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