MC14529B [MOTOROLA]
3.3 VOLT ONLY DRIVER / RECEIVER WITH AN INTEGRATED STANDBY MODE; 3.3伏只驱动器/接收器，集成待机模式
| 型号： | MC14529B |
| 厂家： | 
MOTOROLA |
| 描述： | 3.3 VOLT ONLY DRIVER / RECEIVER WITH AN INTEGRATED STANDBY MODE |
| 文件： | 总8页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14529B analog data selector is a dual 4–channel or single
8–channel device depending on the input coding. The device is suitable for
digital as well as analog application, including various one–of–four and
one–of–eight data selector functions. Since the device has bidirectional
analog characteristics it can also be used as a dual binary to 1–of–4 or a
binary to 1–of–8 decoder.
P SUFFIX
PLASTIC
CASE 648
•
•
•
•
•
Data Paths Are Bidirectional
3–State Outputs
Linear “On” Resistance
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range.
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
ORDERING INFORMATION
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
T
A
= – 55° to 125°C for all packages.
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
BLOCK DIAGRAM
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
3–STATE OUTPUT ENABLE
STROBE X 1
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
6
A
7
2
3
B
TRUTH TABLE (X = Don’t Care)
X0
X1
9
Z
ST
ST
B
A
Z
W
X
Y
4
5
X2
X3
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
X0
X1
X2
X3
Y0
Y1
Y2
Y3
Dual 4–Channel Mode
2 Outputs
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X0
X1
X2
X3
14
13
12
11
Y0
Y1
10
W
Single 8–Channel Mode
1 Output
(Z and W tied together)
Y2
Y3
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
Y0
Y1
Y2
Y3
STROBE Y 15
V
V
= PIN 16
= PIN 8
DD
SS
0
0
X
X
High
Impedance
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS
– 55 C
25 C
Typ #
125 C
Characteristic
Symbol
V
DD
Test Conditions
Min
Max
Min
Max
Min
Max
Unit
SUPPLY REQUIREMENTS (Voltages Referenced to V
)
EE
– 3.0 ≥ V ≥
SS
Power Supply Voltage
Range
V
DD
—
V
V
3.0
18
3.0
—
18
3.0
18
V
DD
EE
Quiescent Current Per
Package
I
5.0
10
15
Control Inputs: V
=
—
—
—
1.0
1.0
2.0
—
—
—
0.005
0.010
0.015
1.0
1.0
2.0
—
—
—
60
60
120
µA
DD
in
V
or V
DD
,
SS
Switch I/O: V
SS
V
I/O
V
, and
500 mV**
DD
∆V
switch
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
5.0
10
15
T
= 25 C only (The
(0.07 µA/kHz) f + I
Typical (0.20 µA/kHz) f + I
(0.36 µA/kHz) f + I
µA
D(AV)
A
DD
DD
DD
channel component,
(V – V )/R , is
not included.)
in out on
CONTROL INPUTS — INHIBIT, A, B (Voltages Referenced to V
)
SS
Low–Level Input Voltage
V
5.0
10
15
R
= per spec,
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
V
IL
IH
in
on
= per spec
I
off
High–Level Input Voltage
V
5.0
10
15
R
= per spec,
on
= per spec
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
I
off
Input Leakage Current
Input Capacitance
I
15
—
V
in
= 0 or V
DD
—
—
± 0.1
—
—
±0.00001 ±0.1
—
—
±1.0
µA
C
—
5.0
7.5
—
pF
in
SWITCHES IN/OUT AND COMMONS OUT/IN — W, Z (Voltages Referenced to V
)
EE
Recommended Peak–to–
Peak Voltage Into or
Out of the Switch
V
—
—
Channel On or Off
Channel On
0
0
V
0
0
—
V
0
0
V
V
I/O
DD
DD
DD
p–p
mV
Recommended Static or
Dynamic Voltage
Across the Switch**
(Figure 5)
∆V
switch
600
—
600
300
Output Offset Voltage
ON Resistance
V
—
V
= 0 V, No Load
—
—
—
10
—
—
—
µV
OO
in
R
10
15
∆V
V
500 mV**,
IL IH
—
—
400
240
—
—
120
80
480
270
—
—
560
350
Ω
on
switch
= V or V
in
(Control), and V
0 to V
DD
=
in
(Switch)
∆ON Resistance Between
Any Two Channels
∆R
10
15
—
—
—
—
—
—
15
10
—
—
—
—
—
—
Ω
on
in the Same Package
Off–Channel Leakage
Current (Figure 10)
I
off
15
V
= V or V
± 100
—
± 0.05
± 100
—
±1000
nA
in IL IH
(Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O
C
C
C
—
—
Inhibit = V
—
—
—
—
—
—
8.0
20
—
—
—
—
—
—
pF
pF
pF
I/O
O/I
I/O
DD
DD
Capacitance, Common O/I
Inhibit = V
Capacitance, Feedthrough
(Channel Off)
—
—
Pins Not Adjacent
Pins Adjacent
—
—
—
—
—
—
0.15
0.47
—
—
—
—
—
—
#Data labelled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
** For voltage drops across the switch (∆V ) > 600 mV ( > 300 mV at high temperature), excessive V current may be drawn; i.e. the
switch DD
currentout of the switch may contain both V andswitchinputcomponents. ThereliabilityofthedevicewillbeunaffectedunlesstheMaximum
DD
Ratings are exceeded. (See first page of this data sheet.)
MC14529B
2
MOTOROLA CMOS LOGIC DATA
SWTCHING CHARACTERISTICS (T = 25 C)
A
Characteristic
Figure
Symbol
, t
PLH PHL
V
V
Min
Typ #
Max
Unit
SS
DD
V
in
to V
out
L
Propagation Delay Time
7
t
0.0
0.0
0.0
0.0
0.0
5.0
10
15
—
—
—
20
10
8.0
40
20
15
ns
(C = 50 pF, R = 1.0 kΩ)
L
Propagation Delay Time, Control to
Output, V = V or V
8
t
t
, t
,
5.0
10
15
—
—
—
140
70
50
400
160
120
ns
mV
PLZ PZL
, t
in DD SS
PHZ PZH
(C = 50 pF, R = 1.0 kΩ)
L
L
Crosstalk, Control to Output
9
—
5.0
10
15
—
—
—
5.0
5.0
5.0
—
—
(C = 50 pF, R = 1.0 kΩ
L
out
L
R
= 10 kΩ)
Control Input Pulse Frequency
10
f
in
5.0
10
15
—
—
—
5.0
10
12
2.5
6.2
8.3
MHz
(C = 50 pF, R = 1.0 kΩ)
L
L
Noise Voltage
(f = 100 Hz)
11, 12
—
5.0
10
15
—
—
—
24
25
30
—
—
—
nV/
√cycle
5.0
10
15
—
—
—
12
12
15
—
—
—
Sine Wave Distortion
—
—
—
– 5.0
5.0
—
0.36
—
%
(V = 1.77 Vdc RMS
in
Centered @ 0.0 Vdc,
R
= 10 kΩ, f = 1.0 kHz)
L
Off–Channel Leakage Current
I
off
nA
(V = + 5.0 Vdc, V
= – 5.0 Vdc)
= + 5.0 Vdc)
= – 7.5 Vdc)
= + 7.5 Vdc)
out
– 5.0
– 5.0
– 7.5
– 7.5
5.0
5.0
7.5
7.5
—
—
—
—
± 0.001
± 0.001
± 0.0015
± 0.0015
± 125
± 125
± 250
± 250
in out
(V = – 5.0 Vdc, V
in out
(V = + 7.5 Vdc, V
in out
(V = – 7.5 Vdc, V
in
Insertion Loss
13
—
– 5.0
5.0
dB
(V = 1.77 Vdc
in
RMS centered @ 0.0 Vdc,
f = 1.0 MHz)
I
= 20 Log (V /V )
loss
10 out in
(R = 1.0 kΩ)
—
—
—
—
2.0
0.8
0.25
0.01
—
—
—
—
L
(R = 10 kΩ)
L
(R = 100 kΩ)
L
(R = 1.0 MΩ)
L
Bandwidth (– 3 dB)
—
—
BW
– 5.0
5.0
5.0
MHz
MHz
(V = 1.77 Vdc
in
RMS centered @ 0.0 Vdc)
(R = 1.0 kΩ)
—
—
—
—
35
28
27
26
—
—
—
—
L
L
(R = 10 kΩ)
(R = 100 kΩ)
L
(R = 1.0 MΩ)
L
Feedthrough and Crosstalk
20 Log (V /V ) = – 50 dB
—
– 5.0
10 out in
(R = 1.0 kΩ)
—
—
—
—
850
100
12
—
—
—
—
L
(R = 10 kΩ)
L
(R = 100 kΩ)
L
(R = 1.0 MΩ)
1.5
L
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14529B
3
V
DD
ST
ST
A
X
Y
I
S
V
N
1 k
B
Z
W
X3
Y3
V
SS
Pins 2, 3, 4, 12, 13 and 14 are left open.
OUT
V
V
V
V
: V is raised from V
SS
until V = V .
IL
IL
IL
C
C
: at V = V : I = ± 10 µA with V = V , V
= V
DD
C
IL
S
in
SS out
V
SS
V
: V = V , V
= V .
SS
IL in
DD out
DD
V
IH
V
IH
: When V = V to V , the switch is ON and the R
IH DD ON
C
V
= 0.0 V
V
in
SS
: specifications are met.
Figure 1. Output Voltage
Test Circuit
Figure 2. Noise Immunity
Test Circuit
V
DD
ST = ST = V
X
Y
DD
I
D
V
OUT
OUT
DD
R
10 k
L
PULSE
GENERATOR
V
SS
V
DD
f
A0, A1
c
V
V
in
SS
P
= V x I
DD
D
D
V
in
Figure 3. Quiescent Power Dissipation
Test Circuit
Figure 4. R
Characteristics
ON
Test Circuit
TYPICAL R
ON
versus INPUT VOLTAGE
250
200
150
100
250
V
V
= 5 V
= –5 V
V
V
= 10 V
= 0 V
DD
SS
DD
SS
200
150
100
50
V
V
= 15 V
= 0 V
DD
SS
V
V
= 7.5 V
= –7.5 V
DD
SS
50
0
0
–10
–5
0
5
10
0
5
10
15
20
25
V
, INPUT VOLTAGE (Vdc)
V
, INPUT VOLTAGE (Vdc)
in
in
Figure 5.
Figure 6.
MC14529B
4
MOTOROLA CMOS LOGIC DATA
V
OUT
V
out
V
ST , ST
X Y
SS
R
C
C
R
L
L
L
L
DD
V
in
V
V
in
90%
10%
X
20 ns
t
V
V
DD
ST , ST
20 ns
20 ns
50%
X
Y
V
V
DD
SS
V
90%
PZH
t
PHZ
50%
V
V
90%
10%
in
DD
SS
V
in
SS
V
10%
t
out
V
t
t
x
PLH
PHL
t
PLZ
PZL
50%
V
V
V
V
V
out
90%
in
x
SS
DD
V
10%
out
Figure 7. Propagation Delay Test Circuit
and Waveforms
Figure 8. Turn–On Delay Time Test Circuit
and Waveforms
V
X, Y
SS
INPUT
V
Feedthrough
OUT
CONTROL
LOGIC
50 pF
OUT
V
A OR B
10 k
R
L
V
DD
R
L
V
SS
DD
V
in
+2.5 Vdc
1 k
V
0.0 Vdc
in
X, Y INPUT
–2.5 Vdc
Figure 9. Crosstalk Test Circuit
Figure 10. Frequency Response Test Circuit
35
30
V
= 15 Vdc
DD
10 Vdc
5.0 Vdc
25
20
15
10
5.0
0
OUT
QUAN–TECH
MODEL
2283
OR EQUIV
V
V
DD
SS
IN
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
Figure 11. Noise Voltage Test Circuit
Figure 12. Typical Noise Characteristics
MOTOROLA CMOS LOGIC DATA
MC14529B
5
2.0
0
PIN ASSIGNMENT
R
= 1 M AND 100 k
L
ST
1
2
16
15
V
X
DD
ST
10 k
X0
X1
X2
X3
A
Y
–2.0
–4.0
3
4
5
6
7
8
14
13
12
11
10
9
Y0
Y1
Y2
Y3
W
1.0 k
–3.0 dB (R = 1.0 M
L
–6.0
–8.0
–3.0 dB (R = 10 k
L
–3.0 dB (R = 1.0 k
L
B
V
Z
–10
–12
SS
10 k
100 k
1.0 M
, INPUT FREQUENCY (Hz)
10 M
100 M
f
in
Figure 13. Typical Insertion Loss/Bandwidth
Characteristics
LOGIC DIAGRAM
B
A
ST
ST
X
Y
7
6
15
1
2
X0
3
4
X1
X2
X3
Y0
9
Z
5
14
13
12
11
Y1
Y2
Y3
10
W
V
V
= PIN 16
= PIN 8
DD
SS
MC14529B
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14529B
7
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
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trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
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MC14529B/D
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