MC14536 [MOTOROLA]
Programmable Timer; 可编程定时器
| 型号： | MC14536 |
| 厂家： | 
MOTOROLA |
| 描述： | Programmable Timer |
| 文件： | 总13页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14536B programmable timer is a 24–stage binary ripple counter
with 16 stages selectable by a binary code. Provisions for an on–chip RC
oscillator or an external clock are provided. An on–chip monostable circuit
incorporating a pulse–type output has been included. By selecting the
appropriate counter stage in conjunction with the appropriate input clock
frequency, a variety of timing can be achieved.
P SUFFIX
PLASTIC
CASE 648
0
24
•
•
•
•
•
•
•
•
24 Flip–Flop Stages — Will Count From 2 to 2
Last 16 Stages Selectable By Four–Bit Select Code
8–Bypass Input Allows Bypassing of First Eight Stages
Set and Reset Inputs
DW SUFFIX
SOIC
CASE 751G
Clock Inhibit and Oscillator Inhibit Inputs
On–Chip RC Oscillator Provisions
On–Chip Monostable Output Provisions
ORDERING INFORMATION
Clock Conditioning Circuit Permits Operation With Very Long Rise and
Fall Times
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
•
•
•
Test Mode Allows Fast Test Sequence
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
– 0.5 to + 18.0
DD
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
BLOCK DIAGRAM
CLOCK INH.
7
RESET SET 8 BYPASS
2
1
6
OSC. INHIBIT 14
STAGES 9 THRU 24
STAGES
1 THRU 8
IN
1
Q
9
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
4
OUT
5
A
B
C
9
10
11
OUT
2
1
DECODER
D
12
V
V
= PIN 16
= PIN 8
DD
SS
DECODE
OUT
MONOSTABLE
MULTIVIBRATOR
MONO–IN 15
13
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
OH
(V
OH
(V
OH
(V
OH
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Pins 4 & 5
5.0
5.0
10
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.25
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
15
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Pin 13
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
mAdc
OH
OH
OH
OH
15
– 3.4
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
Sink
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
OL
Input Current
I
15
—
—
—
±0.1
—
—
±0.00001
±0.1
—
—
±1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (1.50 µA/kHz) f + I
= (2.30 µA/kHz) f + I
= (3.55 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
– V ) in volts, f in kHz is input frequency, and k = 0.003.
SS
T
L
DD
MC14536B
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
V
DD
Min
Typ #
Max
Unit
Output Rise and Fall Time (Pin 13)
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.75 ns/pF) C + 12.5 ns
L
TLH THL
, t
TLH THL
= (0.55 ns/pF) C + 9.5 ns
L
Propagation Delay Time
Clock to Q1, 8–Bypass (Pin 6) High
t
,
ns
PLH
t
PHL
t
t
t
, t
= (1.7 ns/pF) C + 1715 ns
= (0.66 ns/pF) C + 617 ns
L
= (0.5 ns/pF) C + 425 ns
5.0
10
15
—
—
—
1800
650
450
3600
1300
1000
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
Clock to Q1, 8–Bypass (Pin 6) Low
t
t
,
µs
µs
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 3715 ns
5.0
10
15
—
—
—
3.8
1.5
1.1
7.6
3.0
2.3
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 1467 ns
PLH PHL
L
, t
PLH PHL
= (0.5 ns/pF) C + 1075 ns
L
Clock to Q16
t
t
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 6915 ns
5.0
10
15
—
—
—
7.0
3.0
2.2
14
6.0
4.5
PHL PLH
L
PHL
, t
= (0.66 ns/pF) C + 2967 ns
PHL PLH
L
, t
PHL PLH
= (0.5 ns/pF) C + 2175 ns
L
Reset to Q
t
n
PHL
t
t
t
= (1.7 ns/pF) C + 1415 ns
5.0
10
15
—
—
—
1500
600
450
3000
1200
900
PHL
PHL
PHL
L
= (0.66 ns/pF) C + 567 ns
L
= (0.5 ns/pF) C + 425 ns
L
Clock Pulse Width
t
5.0
10
15
600
200
170
300
100
85
—
—
—
ns
MHz
—
WH
Clock Pulse Frequency
(50% Duty Cycle)
f
cl
5.0
10
15
—
—
—
1.2
3.0
5.0
0.4
1.5
2.0
Clock Rise and Fall Time
Reset Pulse Width
t
t
,
5.0
10
15
TLH
THL
No Limit
t
5.0
10
15
1000
400
300
500
200
150
—
—
—
ns
WH
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PIN ASSIGNMENT
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
SET
RESET
1
2
16
15
V
DD
MONO IN
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
IN 1
3
4
5
6
7
8
14
13
12
11
10
9
OSC INH
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
OUT 1
DECODE
SS DD
OUT 2
D
C
B
A
8–BYPASS
CLOCK INH
V
SS
MOTOROLA CMOS LOGIC DATA
MC14536B
3
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) — A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock transition
OSC INHIBIT (Pin 14) — A high level on this pin stops the
RC oscillator which allows for very low–power standby op-
eration. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO–IN (Pin 15) — Used as the timing pin for the on–
chip monostable multivibrator. If the Mono–In input is con-
on IN causes Decode Out to go low. The counter’s flip–flop
stages begin counting on the second negative clock transi-
nected to V
, the monostable circuit is disabled, and
1
SS
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono–In and V
ternal capacitance will determine the minimum output pulse
widths. With the addition of an external capacitor to V , the
pulse width range may be extended. For reliable operation
the resistor value should be limited to the range of 5 kΩ to
100 kΩ and the capacitor value should be limited to a maxi-
mum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
tion of IN . When Set is high, the on–chip RC oscillator is
1
disabled. This allows for very low–power standby operation.
RESET (Pin 2) — A high on Reset asynchronously forces
Decode Out to a low level; all 24 flip–flop stages are also
reset to a low level. Like the Set input, Reset disables the
on–chip RC oscillator for standby operation.
. This resistor and the device’s in-
DD
SS
IN (Pin 3) — The device’s internal counters advance on
1
the negative–going edge of this input. IN may be used as an
1
external clock input or used in conjunction with OUT and
1
OUT to form an RC oscillator. When an external clock is
2
used, both OUT and OUT may be left unconnected or
1
2
used to drive 1 LSTTL or several CMOS loads.
OUTPUTS
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially be-
comes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) — A high on this input discon-
nects the first counter stage from the clocking source. This
holds the present count and inhibits further counting. How-
ever, the clocking source may continue to run. Therefore,
when Clock Inhibit is brought low, no oscillator start–up time
is required. When Clock Inhibit is low, the counter will start
counting on the occurrence of the first negative edge of the
OUT , OUT (Pin 4, 5) — Outputs used in conjunction with
1
2
IN to form an RC oscillator. These outputs are buffered and
1
0
may be used for 2 frequency division of an external clock.
DECODE OUT (Pin 13) — Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip–flop stages
into three 8–stage sections to facilitate a fast test sequence.
The test mode is enabled when 8–Bypass, Set and Reset
are at a high level. (See Figure 8.)
clocking source at IN .
1
MC14536B
4
MOTOROLA CMOS LOGIC DATA
TRUTH TABLES
Input
Input
Stage Selected
for Decode Out
Stage Selected
for Decode Out
8–Bypass
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8–Bypass
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION TABLE
Clock
Inh
OSC
Inh
Decode
Out
In
1
Set
Reset
Out 1
Out 2
0
0
0
0
No
Change
0
0
0
0
Advance to
next state
X
1
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
0
X
X
—
—
No
Change
X
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
No
Change
X
No
Change
Advance to
next state
X = Don’t Care
MOTOROLA CMOS LOGIC DATA
MC14536B
5
LOGIC DIAGRAM
MC14536B
6
MOTOROLA CMOS LOGIC DATA
TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 11 In Application)
8.0
4.0
100
V
= 10 V
DD
V
= 15 V
DD
50
f AS A FUNCTION
OF R
TC
(C = 1000 pF)
20
10
0
(R
≈
2R )
TC
S
10 V
5.0
–4.0
f AS A FUNCTION
OF C
2.0
1.0
0.5
–8.0
–12
–16
(R
= 56 k
Ω)
TC
5.0 V
(R = 120 k)
S
0.2
0.1
R
= 56 k
Ω,
R
R
= 0, f = 10.15 kHz @ V
= 10 V, T = 25°C
A
DD
TC
C = 1000 pF
S
S
DD
, f = 7.8 kHz @ V
= 120 k
Ω
= 10 V, T = 25°C
A
–55 –25
0
25
50
75
100
125
1.0 k
10 k
100 k
1.0 M
0.1
R
, RESISTANCE (OHMS)
TC
0.001
C, CAPACITANCE (
* Device Only.
T , AMBIENT TEMPERATURE (°C)*
A
0.0001
0.01
F)
µ
Figure 1. RC Oscillator Stability
Figure 2. RC Oscillator Frequency as a
Function of R
and C
TC
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 10 In Application)
100
100
FORMULA FOR CALCULATING t IN
MICROSECONDS IS AS FOLLOWS:
FORMULA FOR CALCULATING t IN
MICROSECONDS IS AS FOLLOWS:
W
W
t
= 0.00247 R
WHERE R IS IN k
•
C
Ω
0.85
t
= 0.00247 R • C 0.85
WHERE R IS IN kΩ, C IN pF.
X
W
X
X
W X X
, C IN pF.
X
10
10
R
= 100 k
Ω
Ω
X
R
= 100 k
Ω
Ω
X
50 k
50 k
1.0
0.1
1.0
0.1
10 k
5 k
Ω
Ω
10 k
Ω
Ω
T
V
= 25
°
C
T = 25°C
A
DD
A
5 k
= 5 V
V
= 10 V
DD
1.0
10
100
1000
1.0
10
100
1000
C
, EXTERNAL CAPACITANCE (pF)
C , EXTERNAL CAPACITANCE (pF)
X
X
Figure 3. Typical C versus Pulse Width
Figure 4. Typical C versus Pulse Width
X
X
@ V
= 5.0 V
@ V
= 10 V
DD
DD
100
FORMULA FOR CALCULATING t IN
W
MICROSECONDS IS AS FOLLOWS:
t
= 0.00247 R • C 0.85
W
X X
WHERE R IS IN kΩ, C IN pF.
X
10
R
= 100 k
Ω
Ω
X
50 k
1.0
0.1
10 k
5 k
Ω
Ω
T
= 25°C
= 15 V
A
V
DD
1.0
10
100
1000
C
, EXTERNAL CAPACITANCE (pF)
X
Figure 5. Typical C versus Pulse Width
X
DD
@ V
= 15 V
MOTOROLA CMOS LOGIC DATA
MC14536B
7
V
DD
0.01 µF
CERAMIC
I
500 µF
D
SET
20 ns
20 ns
IN
RESET OUT 1
8–BYPASS
C
L
V
DD
50%
1
PULSE
IN
1
C INH
GENERATOR
t
t
WH
WL
SET
OUT 1
OUT
2
MONO IN
RESET
90%
10%
50%
t
OUT
t
OSC INH
C
L
8–BYPASS
PULSE
GENERATOR
A
B
IN
1
PHL
PLH
t
t
THL
C INH
MONO IN
OSC INH
A
TLH
C
D
DECODE
OUT
OUT
2
C
L
V
SS
B
C
D
DECODE
OUT
20 ns
20 ns
C
L
V
90%
10%
SS
50%
50%
DUTY CYCLE
Figure 6. Power Dissipation Test
Circuit and Waveform
Figure 7. Switching Time Test Circuit and Waveforms
V
FUNCTIONAL TEST SEQUENCE
DD
SET
Test function (Figure 8) has been included for the reduc-
tion of test time required to exercise all 24 counter stages.
This test function divides the counter into three 8–stage
sections and 255 counts are loaded in each of the 8–stage
sections in parallel. All flip–flops are now at a “1”. The count-
er is now returned to the normal 24–stages in series configu-
RESET OUT 1
PULSE
8–BYPASS
GENERATOR
IN
1
C INH
MONO IN
OSC INH
A
OUT
2
ration. One more pulse is entered into In which will cause
1
the counter to ripple from an all “1” state to an all “0” state.
B
C
D
DECODE
OUT
V
SS
Figure 8. Functional Test Circuit
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
Decade Out
Q1 thru Q24
In
Set
0
Reset
8–Bypass
1
All 24 stages are in Reset mode.
1
1
0
1
1
1
1
1
1
0
0
0
1
Counter is in three 8 stage sections in parallel mode.
First “1” to “0” transition of clock.
1
1
0
—
—
—
1
1
1
255 “1” to “0” transitions are clocked in the counter.
0
0
1
0
1
0
1
0
1
1
The 255 “1” to “0” transition.
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
0
0
0
0
0
0
1
0
In Switches to a “1”.
1
Counter Ripples from an all “1” state to an all “0” state.
MC14536B
8
MOTOROLA CMOS LOGIC DATA
+V
16
V
6
9
DD
8–BYPASS
4
5
A
OUT 1
OUT 2
10
11
12
2
B
C
D
RESET
OSC INH
MONO–IN
SET
14
15
1
PULSE
GEN.
7
CLOCK INH
3
13
DECODE OUT
IN
1
PULSE
GEN.
V
SS
8
CLOCK
IN
1
SET
CLOCK INH
DECODE OUT
POWER UP
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
n
A, B, C, and D inputs, and the clock input period. A 2 frequency division (where n = the
0
number of stages selected from the truth table) is obtainable at Decode Out. A 2 –divided
output of IN can be obtained at OUT and OUT .
1
1
2
Figure 9. Time Interval Configuration Using an External Clock, Set,
and Clock Inhibit Functions
(Divide–by–2 Configured)
MOTOROLA CMOS LOGIC DATA
MC14536B
9
+V
16
V
6
9
DD
8–BYPASS
R
4
5
X
A
OUT 1
OUT 2
10
11
12
2
B
C
D
PULSE
GEN.
RESET
SET
1
7
CLOCK INH
MONO–IN
CLOCK INH
15
14
3
13
DECODE OUT
IN
1
CLOCK
V
SS
8
C
X
IN
1
RESET
*t ≈ .00247 • R • C 0.85
w
X
X
t
R
C
in µsec
w
DECODE OUT
in kΩ
X
X
in pF
*t
w
POWER UP
NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset
n
input low enables the chip’s internal counters. After Reset goes low, the 2 /2 negative transition of the clock input causes
Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of the
n
output is dependent on the external timing components. The second and all subsequent pulses occur at 2 x (the clock
period) intervals where n = the number of stages selected from the truth table.
Figure 10. Time Interval Configuration Using an External Clock, Reset,
and Output Monostable to Achieve a Pulse Output
(Divide–by–4 Configured)
MC14536B
10
MOTOROLA CMOS LOGIC DATA
+V
R
R
S
16
V
6
9
DD
8–BYPASS
4
5
A
OUT 1
OUT 2
10
11
12
2
C
B
C
TC
D
PULSE
GEN.
RESET
SET
14
15
CLOCK INH
MONO–IN
CLOCK INH
1
7
3
13
DECODE OUT
IN
1
V
SS
8
RESET
OUT 1
OUT 2
1
f
osc
2.3R
C
tc
DECODE OUT
tc
≥ R
R
s
= Hz
F
R
C
t
w
= Ohms
= FARADS
POWER UP
NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is deter-
mined by the external R and C components. When power is first applied to the device, Decode Out
initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator is
disabled.Thisputsthedeviceinalow–currentstandbycondition.TherisingedgeoftheResetpulse
will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,
the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low
n
for 2 /2 of the oscillator’s period. After the part times out, the output again goes high.
Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and
Reset Input to Initiate Time Interval
(Divide–by–2 Configured)
MOTOROLA CMOS LOGIC DATA
MC14536B
11
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MC14536B
12
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B–
8X P
0.010 (0.25)
M
M
B
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
1
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
16X D
M
S
S
0.010 (0.25)
T
A
B
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
M
SEATING
14X G
K
PLANE
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
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