MC145443BDW [MOTOROLA]
Single-Chip 300-Baud Modem; 单芯片300波特率的调制解调器
| 型号： | MC145443BDW |
| 厂家： | 
MOTOROLA |
| 描述： | Single-Chip 300-Baud Modem |
| 文件： | 总12页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC145442B/D
SEMICONDUCTOR TECHNICAL DATA
The MC145442B and MC145443B silicon–gate CMOS single–chip low–
speed modems contain a complete frequency shift keying (FSK) modulator,
demodulator, and filter. These devices are compatible with CCITT V.21
(MC145442B) and Bell 103 (MC145443B) specifications. Both devices provide
full–duplex or half–duplex 300–baud data communication over a pair of
telephone lines. They also include a carrier detect circuit for the demodulator
section and a duplexer circuit for direct operation on a telephone line through a
simple transformer.
P SUFFIX
PLASTIC DIP
CASE 738
20
1
DW SUFFIX
SOG PACKAGE
CASE 751D
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MC145442B Compatible with CCITT V.21
MC145443B Compatible with Bell 103
Low–Band and High–Band Band–Pass Filters On–Chip
Simplex, Half–Duplex, and Full–Duplex Operation
Originate and Answer Mode
Analog Loopback Configuration for Self Test
Hybrid Network Function On–Chip
Carrier Detect Circuit On–Chip
Adjustable Transmit Level and CD Delay Timing
On–Chip Crystal Oscillator (3.579 MHz)
Single +5 V Power Supply Operation
Internal Mid–Supply Generator
Power–Down Mode
Pin Compatible with MM74HC943
20
1
ORDERING INFORMATION
MC145442BP
MC145443BP
Plastic DIP
Plastic DIP
MC145442BDW
MC145443BDW
SOG Package
SOG Package
PIN ASSIGNMENT
DSI
LB
1
2
20 TLA
19
V
AG
Capable of Driving –9 dBm into a 600 Ω Load
CD
3
4
18 Exl
CDT
17 TxA
RxD
5
6
7
8
9
16 RxA1
15 RxA2
14 SQT
13 MODE
V
DD
CDA
X
out
X
in
12
V
SS
FB 10
11 TxD
REV 1
9/00
Motorola,Inc.2000
BLOCK DIAGRAM
4
7
CDT
CDA
LOW–BAND
15
16
BPF
RxA2
RxA1
3
CARRIER
DETECT
CD
–
AAF
S/H
+
5
AC AMP
RxD
DEMOD
*
HIGH–BAND
BPF
10
1
FB
DSI
SMOOTHING
FILTER
2
17
18
–
LB
TxA
ExI
13
MODE
CONTROL
+
MODE
14
11
20
SQT
TxD
TLA
MODULATOR
ANALOG
GROUND
19
6
INTERNAL
V
AG
V
AG
GENERATOR
8
9
V
DD
X
out
X
in
SAMPLING CLOCK: 77.82 kHz
SAMPLING CLOCK: 19.46 kHz
CLOCK
DIVIDER
OSCILLATOR
12
V
SS
* Refer to the FB pin description.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
)
SS
This device contains circuitry to protect the
Rating
Symbol
Value
Unit
V
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normalprecautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
Supply Voltage
V
DD
–0.5 to 7.0
DC Input Voltage
V
in
–0.5 to V
+ 0.5
V
DD
DC Output Voltage
V
out
–0.5 to V
+ 0.5
V
DD
proper operation it is recommended that V and
in
Clamp Diode Current, per Pin
DC Output Current, per Pin
Power Dissipation
I , I
IK OK
±20
mA
mA
mW
°C
°C
V
V
be constrained to the range V
≤ (V or
SS in
out
I
±28
) ≤ V ).
out
out
DD
Unused inputs must always be tied to an
P
D
500
appropriate logic voltage level (e.g., either V
or V ).
DD
SS
Operating Temperature Range
Storage Temperature Range
T
A
–40 to 85
T
stg
–65 to 150
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Min
4.5
0
Max
Unit
V
V
DD
5.5
DC Input or Output Voltage
Input Rise or Fall Time
Crystal Frequency*
V , V
in out
V
DD
V
t , t
r f
—
500
5.0
ns
f
3.2
MHz
crystal
* Changing the crystal frequency from 3.579 MHz will change the output frequencies. The
change in output frequency will be proportional to the change in crystal frequency.
MC145442B•MC145443B
MOTOROLA
2
DC ELECTRICAL CHARACTERISTICS (V
Characteristic
= 5.0 V ±10%, T = –40° to 85°C)
DD
A
Symbol
Min
– 0.8
DD
Typ
Max
Unit
High–Level Input Voltage
LB
V
IH
V
—
—
—
—
V
X , TxD, Mode, SQT
in
3.15
Low–Level Input Voltage
High–Level Output Voltage
LB
V
—
—
—
—
0.8
1.1
V
V
IL
X , TxD, Mode, SQT
in
V
OH
I
I
I
= 20 µA
= 2 mA
= 20 µA
CD, RxD
CD, RxD
V
– 0.1
—
—
—
—
—
OH
OH
OH
DD
3.7
—
X
V
– 0.05
out
DD
Low–Level Output Voltage
V
OL
V
I
I
I
= 20 µA
= 2 mA
= 20 µA
CD, RxD
CD, RxD
—
—
—
—
—
0.05
0.1
0.4
—
OL
OL
OL
X
out
Input Current
LB, TxD, Mode, SQT
I
in
—
—
—
—
—
10
—
—
±1.0
±12
±20
±10
µA
RxA1, RxA2 (0°
RxA1, RxA2 (–40°
T
A
T
A
85°C)
< 0°C)
X
in
Quiesent Supply Current (X or f
in
= 3.579 MHz)
I
—
—
7
10
mA
µA
pF
crystal
DD
Power–Down Supply Current
Input Capacitance
200
300
X
C
—
—
10
—
—
10
in
in
All Other Inputs
V
Output Voltage (I = ±10 µA)
V
2.4
1.1
10
2.5
1.2
20
2.6
1.3
30
V
V
AG
O
AG
CDA Output Voltage (I = ±10 µA)
V
CDA
O
Line Driver Feedback Resistor
R
kΩ
f
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 5.0 V ±10%, T = –40° to 85°C, Crystal Frequency = 3.579 MHz ±0.1%; See Figure 1)
A
Characteristic
Min
Typ
Max
Unit
TRANSMITTER
Power Output on TxA
dBm
–13
–10
–12
–9
–11
–8
R
R
= 1.2 kΩ, R
= 1.2 kΩ, R
= ∞
L
L
TLA
TLA
= 5.5 kΩ
Second Harmonic Power
= 1.2 kΩ
—
– 56
—
dBm
R
L
RECEIVE FILTER AND HYBRID
Hybrid Input Impedance RxA1, RxA2
FB Output Impedance
40
—
50
16
—
—
—
—
kΩ
kΩ
Adjacent Channel Rejection
DEMODULATOR
–48
dBm
Receive Carrier Amplitude
Dynamic Range
–48
—
—
36
100
5
–12
—
dBm
dB
Bit Jitter (S/N = 30 dB, Input = –38 dBm, Bit Rate = 300 baud)
Bit Bias
—
—
µs
—
—
%
Carrier Detect Threshold
(CDA = 1.2 V or CDA grounded through a 0.1 µF capacitor)
On to Off
Off to On
—
—
–44
–47
—
—
dBm
MOTOROLA
MC145442B•MC145443B
3
3.579 MHz ± 0.1%
Table 1. Bell 103 and CCITT V.21
Frequency Characteristics
Originate Mode
Answer Mode
8
9
R
X
TLA
X
out
in
TxD
Data
Bell 103 (MC145443B)
Transmit
Receive
Transmit
Receive
11
20
17
15
TLA
TxA
RxA2
D
in
V
DD
Space
Mark
1070 Hz
1270 Hz
2025 Hz
2225 Hz
2025 Hz
2225 Hz
1070 Hz
1270 Hz
MC145442B
MC145443B
600 Ω
600 Ω
CCITT V.21 (MC145442B)
16
5
RxA1
CDT
4
RxD
FB
10
D
out
Space
Mark
1180 Hz
980 Hz
1850 Hz
1650 Hz
1850 Hz
1650 Hz
1180 Hz
980 Hz
TEST
OUTPUT
0.1 µF
TEST
INPUT
0.1 µF
NOTE: Actual frequencies may be ±5 Hz assuming 3.579545 MHz
crystal is used.
C
CDT
C
FB
MAXIMUM LEVEL OF OUT–OF–BAND ENERGY
RELATIVE TO THE TRANSMIT CARRIER LEVEL INTO 600 Ω (kHz)
Figure 1. AC Characteristics Evaluation Circuit
0
2
3.4 4
16
64
256
PIN DESCRIPTIONS
0
V
DD
–20
–25
Positive Power Supply (Pin 6)
This pin is normally tied to 5.0 V.
15 dB/OCTAVE
V
SS
Negative Power Supply (Pin 12)
–55
–60
This pin is normally tied to 0 V.
V
Figure 2. Out–of–Band Energy
AG
Analog Ground (Pin 19)
ExI
External Input (Pin 18)
Analog ground is internally biased to (V
pin must be decoupled by a capacitor from V
– V )/2. This
SS
AG
DD
to V
and a
SS
The external input is the non–inverting input to the line
driver. It is provided to combine an auxiliary audio signal or
speech signal to the phone line using the line driver. This pin
capacitor from V
to V . Analog ground is the common
AG
DD
bias line used in the switched capacitor filters, limiter, and
slicer in the demodulation circuitry.
should be connected to V
if not used. The average level
to maintain proper operation. (See
AG
must be the same as V
AG
TLA
Applications Information.)
Transmit Level Adjust (Pin 20)
DSI
This pin is used to adjust the transmit level. Transmit level
adjustment range is typically from –12 dBm to –9 dBm. (See
Applications Information.)
Driver Summing Input (Pin 1)
The driver summing input may be used to connect an ex-
ternal signal, such as a DTMF dialer, to the phone line. A
TxD
series resistor, R
A (see Applications Information and Figure 6). When ap-
V
, is needed to define the voltage gain
DSI
Transmit Data (Pin 11)
plying a signal to the DSI pin, the modulator should be
squelched by bringing SQT (pin 14) to a logic high level. The
Binary information is input to the transmit data pin. Data
entered for transmission is modulated using FSK techniques.
A logic high input level represents a mark and a logic low
represents a space (see Table 1).
voltage gain, A , is calculated by the formula A = –R /R
V
V
f
DSI
DSI
(where R ≈ 20 kΩ). For example, a 20 kΩ resistor for R
f
will provide unity gain (A = –20 kΩ/20 kΩ = –1). This pin
V
must be left open if not used.
TxA
Transmit Carrier (Pin 17)
RxD
Receive Data (Pin 6)
This is the output of the line driver amplifier. The transmit
carrier is the digitally synthesized sine wave output of the
modulator derived from a crystal oscillator reference. When a
3.579 MHz crystal is used the frequency outputs shown in
Table 1 apply. (See Applications Information.)
The receive data output pin presents the digital binary data
resulting from the demodulation of the receive carrier. If no
carrier is present, CD high, the receive data output (RxD) is
clamped high.
MC145442B•MC145443B
MOTOROLA
4
RxA2, RxA1
Receive Carrier (Pins 15, 16)
by CDT, pin 4). This pin is held at the logic low level until the
signal falls below the maximum threshold level for longer
than the turn off time. (See Applications Information and
Figure 5.)
The receive carrier is the FSK input to the demodulator
through the receive band–pass filter. RxA1 is the non–invert-
ing input and RxA2 is the inverting input of the receive hybrid
(duplexer) operational amplifier.
CDA
Carrier Detect Adjust (Pin 7)
An external voltage may be applied to this pin to adjust the
carrier detect threshold. The threshold hysteresis is internally
fixed at 3 dB (see Applications Information).
LB
Analog Loopback (Pin 2)
When a high level is applied to this pin (SQT must be low),
the analog loopback test is enabled. The analog loopback
test connects the TxA pin to the RxA2 pin and the RxA1 to
analog ground. In loopback, the demodulator frequencies
are switched to the modulation frequencies for the selected
mode. (See Tables 1 and 2 and Figures 4c and 4d.)
X
, X
out in
Crystal Oscillator (Pins 8, 9)
A crystal reference oscillator is formed when a 3.579 MHz
crystal is connected between these two pins. X
(pin 8) is
out
the output of the oscillator circuit, and X (pin 9) is the input
in
When LB is connected to analog ground (V ), the modu-
AG
to the oscillator circuit. When using an external clock, apply
lator generates an echo cancellation tone of 2100 Hz for
MC145442B CCITT V.21 and 2225 Hz for MC145443B Bell
103 systems. For normal operation, this pin should be at a
logic low level (V ).
The power–down mode is enabled when both LB and SQT
are connected to a logic high level (see Table 2).
the clock to the X (pin 9) pin and leave X
internal 10 MΩ resistor and internal capacitors, typically
(pin 8) open. An
in
out
10 pF on X and 16 pF on X , allow the crystal to be con-
in out
SS
nected without any other external components. Printed cir-
cuit board layout should keep external stray capacitance to a
minimum.
Table 2. Functional Table
FB
MODE
Pin 13
SQT
LB
Filter Bias (Pin 10)
Pin 14
Pin 2
Operating Mode
Originate Mode
Answer Mode
This is the negative input to the ac amplifier. In normal op-
eration, this pin is connected to analog ground through a
0.1 µF bypass capacitor in order to cancel the input offset
voltage of the limiter. It has a nominal input impedance of
16 kΩ (see Figure 3).
1
0
0
0
0
0
1
1
1
0
0
X
X
X
X
X
V
(V /2) Echo Tone
AG DD
1
0
Analog Loopback
Squelch Mode
SQT
Transmit Squelch (Pin 14)
V
(V /2) Squelch Mode
AG DD
When this input pin is at a logic high level, the modulator is
disabled. The line driver remains active if LB is at a logic low
level (see Table 2).
1
Power Down
When both LB and SQT are connected to a logic high level
(see Table 2), the entire chip is in a power down state and all
circuitry except the crystal oscillator is disabled. Total power
supply current decreases from 10 mA (max) to 300 µA
(max).
MODE
Mode (Pin 13)
This input selects the pair of transmit and frequencies
used during modulation and demodulation. When a logic
high level is placed on this input, originate (Bell) or channel 1
(CCITT) is selected. When a low level is placed on this input,
answer (Bell) or channel 2 (CCITT) is selected. (See
Tables 1 and 2 and Figure 4.)
FROM
TO
BAND–PASS
FILTER
+
–
CARRIER DETECT CIRCUIT
AND DEMODULATOR
CDT
Carrier Detect Timing (Pin 4)
490 kΩ
A capacitor on this pin to V
SS
carrier must be present before CD goes low (see Applica-
tions Information for the capacitor values).
sets the amount of time the
16 kΩ
10
FB
CD
Carrier Detect Output (Pin 3)
0.1 µF
This output is used to indicate when a carrier has been
sensed by the carrier detect circuit. This output goes to a
logic low level when a valid signal above the maximum
threshold level (defined by CDA, pin 7) is maintained on the
input to the hybrid circuit longer then the response (defined
Figure 3. AC Amplifier Circuit
MOTOROLA
MC145442B•MC145443B
5
In the answer or channel 2 mode, a logic low level is
placed on MODE (pin 13) and on LB (pin 2). In this mode, the
data follows the same path except the FSK signal is routed to
the high–band band–pass filter and the sample–and–hold
signal is routed through the low–band band–pass filter (see
Figure 4b).
In the analog loopback originate or channel 1 mode, a logic
high level is placed on MODE (pin 13) and on LB (pin 2). This
mode is used for a self check of the modulator, demodulator,
and low–band pass–band filter circuit. The modulator side is
configured exactly like the originate mode above except the
line driver output (TxA, pin 17) is switched to the negative in-
put of the hybrid op–amp. The RxA2 input pin is open in this
mode and the non–inverting input of the hybrid circuit is con-
GENERAL DESCRIPTION
The MC145442B and MC145443B are full–duplex low–
speed modems. They provide a 300–baud FSK signal for bi-
directional data transmission over the telephone network.
They can be operated in one of four basic configurations as
determined by the state of MODE (pin 13) and LB (pin 2).
The normal (non–loopback) and self test (loopback) modes
in both answer and originate modes will be discussed.
For an originate or channel 1 mode, a logic high level is
placed on MODE (pin 13) and a logic low level is placed on
LB (pin 2). In this mode, transmit data is input on TxD, where
it is converted to a FSK signal and routed through a low–
band band–pass filter. The filtered output signal is then buff-
ered by the Tx op–amp line driver, which is capable of driving
–9 dBm onto a 600 Ω line. The receive signal is connected
through a hybrid duplexer circuit on pins 15 and 16, RxA2
and RxA1. The signal then passes through the anti–aliasing
filter, the sample–and–hold circuit, is switched into the high–
band band–pass filter, and then switched into the ac amplifier
circuit. The output of the ac amplifier circuit is routed to the
demodulator circuit and demodulated. The resulting digital
data is then output through RxD (pin 5). The carrier detect
circuit receives its signal from the output of the ac amplifier
circuit and goes low when the incoming signal is detected
(see Figure 4a).
nected to V . The sample–and–hold output bypasses the
AG
filter so that the demodulator receives the modulated Tx data
(see Figure 4c). This test checks all internal device compo-
nents except the high–band band–pass filter, which can be
checked in the answer or channel 2 mode test.
In the analog loopback or channel 2 mode, a logic low level
is placed on MODE (pin 13) and a logic high level on LB
(pin 2). This mode is used for a self check of the modulator,
demodulator, and high–band pass–band filter circuit. This
configuration is exactly like the originate loopback mode
above, except the signal is routed through the high–band
pass–band filter (see Figure 4d).
MC145442B•MC145443B
MOTOROLA
6
15
16
RxA2
RxA1
CARRIER
DETECT
3
CD
–
AC
AMP
LOW–BAND
BPF
AAF
S/H
+
5
1
DEMOD
RxD
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
TxD
–
MODULATOR
17
18
TxA
Exl
+
(a) Originate/Channel 1 Mode (MODE = High, LB = Low)
15
16
RxA2
RxA1
CARRIER
DETECT
3
CD
–
AC
AMP
LOW–BAND
BPF
AAF
S/H
+
5
1
DEMOD
RxD
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
TxD
MODULATOR
–
17
18
TxA
Exl
+
(b) Answer/Channel 2 Mode (MODE = Low, LB = Low)
15
16
RxA2
RxA1
CARRIER
DETECT
3
CD
–
AC
AMP
AAF
S/H
+
LOW–BAND
BPF
5
1
DEMOD
RxD
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
–
TxD
MODULATOR
17
18
TxA
Exl
+
(c) Originate/Channel 1 Mode and Analog Loopback State (MODE = High, LB = Low)
15
16
RxA2
RxA1
CARRIER
DETECT
3
CD
–
AC
AMP
AAF
S/H
+
LOW–BAND
BPF
5
1
RxD
DSI
DEMOD
11
HIGH–BAND
BPF
SMOOTHING
FILTER
MODULATOR
–
TxD
17
18
TxA
Exl
+
(d) Answer/Channel 2 Mode and Analog Loopback State (MODE = Low, LB = Low)
Figure 4. Basic Operating Modes
MOTOROLA
MC145442B•MC145443B
7
(pin 20) to V
DD
(pin 6). Table 3 shows the R
the corresponding power output for a 600 Ω load. The volt-
values and
APPLICATIONS INFORMATION
TLA
CARRIER DETECT TIMING ADJUSTMENT
age at TxA is twice the value of that at ring and tip because
TxA feeds the signal through a 600 Ω resistor R to a 600 Ω
line transformer (see Figure 7). When choosing resistor
Tx
The value of a capacitor, C
CDT
at CDT (pin 4) determines
how long a received modem signal must be present above
the minimum threshold level before CD (pin 3) goes low. The
R
TLA
, keep in mind that –9 dBm is the maximum output level
allowed from a modem onto the telephone line (in the U.S.).
In addition, keep in mind that maximizing the power output
from the modem optimizes the signal–to–noise ratio, improv-
ing accurate data transmission.
C
capacitor also determines how long the CD pin stays
CDT
low after the received modem signal goes below the mini-
mum threshold. The CD pin is used to distinguish a strong
modem signal from random noise. The following equations
show the relationship between t
, the time in seconds re-
CDL
Table 3. Transmit Level Adjust
Output Transmit Level
quired for CD to go low; t
for CD to go high; and C
, the time in seconds required
CDH
, the capacitor value in µF.
CDT
(Typical into 600 Ω)
R
Valid signal to CD response time: t
≈ 6.4 × C
CDT
TLA
CDL
Invalid signal to CD off time:
t
≈ 0.54 × C
CDT
–12 dBm
–11 dBm
–10 dBm
–9 dBm
∞
CDH
19.8 kΩ
9.2 kΩ
5.5 kΩ
Example: t
t
≈ 6.4 × 0.1 µF ≈ 0.64 seconds
≈ 0.54 × 0.1 µF ≈ 0.054 seconds
CDL
CDH
CARRIER DETECT THRESHOLD ADJUSTMENT
THE LINE DRIVER
The carrier detect threshold is set by internal resistors to
activate CD with a typical –44 dBm (into 600 Ω) signal and
deactivate CD with a typical –47 dBm signal applied to the
input of the hybrid circuit. The carrier detect threshold level
can be adjusted by applying an external voltage on CDA
(pin 7). The following equations may be used to find the CDA
voltage required for a given threshold voltage. (V and V
The line driver is a power amplifier used for driving a tele-
phone line. Both the inverting and noninverting input to the
line driver are available for transmitting externally generated
tones.
Exl (pin 18) is the noninverting input to the line driver and
gives a fixed gain of 2 (R = 50 kΩ). The average signal level
must be the same as V
pin should be connected to V
AG
The driver summing input (DSI, pin 1) may be used to con-
nect an external signal, such as a DTMF dialer, to the phone
line. When applying a signal to the DSI pin, the modulator
should be squelched by bringing SQT (pin 14) to a logic high
level. DSI must be left open if not used.
on
off
are in Vrms.)
i
to maintain proper operation. This
if not used.
V
CDA
V
CDA
= 244 × V
on
= 345 × V
off
AG
Example (Internally Set)
V
V
= 4.9 mV ≈ –44 dBm: V
= 3.5 mV ≈ –47 dBm: V
= 244 × 4.9 mV = 1.2 V
= 345 × 3.5 mV = 1.2 V
on
CDA
CDA
off
In addition, the DSI pin is the inverting side of the line driv-
Example (Externally Set)
er and allows adjustable gain with a series resistor R
(see
DSI
V
V
= 7.7 mV ≈ –40 dBm: V
= 5.4 mV ≈ –43 dBm: V
= 244 × 7.7 mV = 1.9 V
= 345 × 5.4 mV = 1.9 V
on
CDA
CDA
Figure 6). The voltage gain, A , is determined by the
V
off
equation:
The CDA pin has an approximate Thevenin equivalent
voltage of 1.2 V and an output impedance of 100 kΩ. When
using the internal 1.2 V reference, a 0.1 µF capacitor should
R
f
A = –
V
R
DSI
be connected between this pin and V
(see Figure 5).
SS
where R ≈ 20 kΩ.
f
TRANSMIT LEVEL ADJUSTMENT
Example: A resistor value of 20 kΩ for RDSI will provide
unity gain.
The power output at TxA (pin 17) is determined by the
value of resistor R that is connected between TLA
A = – (20 kΩ/20 kΩ) = –1 .
V
TLA
MC145442B•MC145443B
MOTOROLA
8
V
DD
ac
AMP
AUTO–NULLED
COMPARATOR
HYBRID
16
7
6 ms
3
RxA1
CDA
RETRIGGERABLE
ONE–SHOT
CD
V
ref
V
CDA
≈ 1.2 V
SAMPLING
CLOCK
THRESHOLD
CONTROL
4
CDT
C
CDA
0.1 µF
C
CDT
0.1 µF
Figure 5. Carrier Detect Circuit
MODULATOR
OUTPUT
R = R
0
f
R
0
DSI
1
R
DSI
R
f
TxA
17
ExI
18
–
+
R
i
V
AG
19
Figure 6. Line Driver Using the DSI Input
MOTOROLA
MC145442B•MC145443B
9
+5 V
0.1 µF
0.1 µF
0.1 µF
17
19
6
EIA–232–D
DB–25
CONNECTOR
9
8
V
V
CC
V
DD
DD
1
X
in
20
20
1
C1+
3.58
MHz
C1+
C1–
TLA
C
DSI
3
R
DSI
R
TLA
18
10
6
DTMF
C1–
DI2
X
out
DSI
TxA
RxA2
INPUT
8
11
17
15
20 kΩ
MMBZ15VDLT1 X 3
0.1 µF
CD
TxD
RxD
Tx2
Rx1
Tx1
15
13
R
DO1
DI1
Tx
2
3
600 Ω
+
10 µF
10 Ω
16
10 kΩ
10 kΩ
TIP
RxA1
MC145442B/3B
MC145407
SQT
LB
8
*
TxEN
STBY
RING
18
10
19
Exl
V
DD
C
FB
7
9
Rx2
Rx3
7
10 kΩ
FB
V
0.1 µF
0.1 µF
0.1 µF
MODE
AG
V
CDT
4
GND
12
CDA
7
GND
SS
2
4
C
C
CDA
0.1 µF
CDT
0.1 µF
* Line Protection Circuit.
Figure 7. Typical MC145442B/MC145443B Applications Circuit
MC145442B•MC145443B
MOTOROLA
10
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 738–03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
DIM MIN MAX
1.010 1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
G
J
K
L
M
N
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
6.10
3.81
0.39
1.27 BSC
1.27
2.54 BSC
0.21
2.80
7.62 BSC
6.60
4.57
0.55
-T-
SEATING
PLANE
K
M
1.77
E
N
0.38
3.55
G
F
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0°
15°
0°
0.51
15°
1.01
0.020 0.040
M
M
0.25 (0.010)
T A
DW SUFFIX
SOG PACKAGE
CASE 751D–05
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
T
0.25
A
B
e
1.27 BSC
H
h
L
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
SEATING
PLANE
18X e
A1
C
T
MOTOROLA
MC145442B•MC145443B
11
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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