MC145480DW_技术文档

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SEMICONDUCTOR TECHNICAL DATA

The MC145480 is a general purpose per channel PCM Codec–Filter with pin

selectable Mu–Law or A–Law companding, and is offered in 20–pin DIP, SOG,

and SSOP packages. This device performs the voice digitization and

reconstruction as well as the band limiting and smoothing required for PCM

systems. This device is designed to operate in both synchronous and

asynchronous applications and contains an on–chip precision reference

voltage.

This device has an input operational amplifier whose output is the input to the

encoder section. The encoder section immediately low–pass filters the analog

signal with an active R–C filter to eliminate very high frequency noise from being

modulated down to the passband by the switched capacitor filter. From the

active R–C filter, the analog signal is converted to a differential signal. From this

point, all analog signal processing is done differentially. This allows processing

of an analog signal that is twice the amplitude allowed by a single–ended

design, which reduces the significance of noise to both the inverted and

non–inverted signal paths. Another advantage of this differential design is that

noise injected via the power supplies is a common–mode signal that is

cancelled when the inverted and non–inverted signals are recombined. This

dramatically improves the power supply rejection ratio.

P SUFFIX

PLASTIC DIP

CASE 738

20

1

DW SUFFIX

SOG PACKAGE

CASE 751D

1

VF SUFFIX

SSOP

CASE 940C

20

1

ORDERING INFORMATION

MC145480P

Plastic DIP

MC145480DW SOG Package

MC145480VF SSOP

After the differential converter, a differential switched capacitor filter band–

passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized

by the differential compressing A/D converter.

The decoder accepts PCM data and expands it using a differential D/A

converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X

compensated by a differential switched capacitor filter. The signal is then filtered

by an active R–C filter to eliminate the out–of–band energy of the switched

capacitor filter.

The MC145480 PCM Codec–Filter accepts a variety of clock formats,

including Short Frame Sync, Long Frame Sync, IDL, and GCI timing

environments. This device also maintains compatibility with Motorola’s family of

Telecommunication products, including the MC14LC5472 U–Interface Trans-

ceiver, MC145474/75 S/T–Interface Transceiver, MC145532 ADPCM Trans-

coder, MC145422/26 UDLT–1, MC145421/25 UDLT–2, and MC3419/MC33120

SLIC.

PIN ASSIGNMENT

RO+

RO–

1

2

20

19

V

AG

TI+

PI

3

4

18

17

TI–

TG

PO–

PO+

5

6

16

15

Mu/A

V

SS

DD

FSR

DR

7

14

13

12

11

FST

8

DT

The MC145480 PCM Codec–Filter utilizes CMOS due to its reliable

low–power performance and proven capability for complex analog/digital VLSI

functions.

BCLKR

PDI

9

BCLKT

MCLK

10

•

Single 5 V Power Supply

Typical Power Dissipation of 23 mW, Power–Down of 0.01 mW

Fully–Differential Analog Circuit Design for Lowest Noise

Transmit Band–Pass and Receive Low–Pass Filters On–Chip

Active R–C Pre–Filtering and Post–Filtering

Mu–Law and A–Law Companding by Pin Selection

On–Chip Precision Reference Voltage (1.575 V)

Push–Pull 300 Ω Power Drivers with External Gain Adjust

MC145536EVK is the Evaluation Kit that Also Includes the MC145532

ADPCM Transcoder

REV 2

9/95

Motorola, Inc. 1995

MOTOROLA

MC145480

1

RECEIVE

SHIFT

REGISTER

DR

RO +

RO –

DAC

FREQ

PI

FSR

–

+

PO –

BCLKR

Mu/A

PDI

SHARED

DAC

SEQUENCE

AND

– 1

PO +

CONTROL

MCLK

BCLKT

V

DD

1.575 V

REF

V

SS

2.4 V

REFERENCE

1

V

AG

FST

TG

TI –

TI +

–

+

ADC

FREQ

TRANSMIT

SHIFT

DT

REGISTER

Figure 1. MC145480 PCM Codec–Filter Block Diagram

which increment. When the chord bits increment, the step

bits double their voltage weighting. This results in an effec-

tive resolution of six bits (sign + chord + four step bits) across

a 42 dB dynamic range (seven chords above 0, by 6 dB per

chord).

DEVICE DESCRIPTION

A PCM Codec–Filter is used for digitizing and reconstruct-

ing the human voice. These devices are used primarily for

the telephone network to facilitate voice switching and trans-

mission. Once the voice is digitized, it may be switched by

digital switching methods or transmitted long distance (T1,

microwave, satellites, etc.) without degradation. The name

codec is an acronym from ‘‘COder’’ for the analog–to–digital

converter (ADC) used to digitize voice, and ‘‘DECoder’’ for

the digital–to–analog converter (DAC) used for reconstruct-

ing voice. A codec is a single device that does both the ADC

and DAC conversions.

To digitize intelligible voice requires a signal–to–distortion

ratio of about 30 dB over a dynamic range of about 40 dB.

This may be accomplished with a linear 13–bit ADC and

DAC, but will far exceed the required signal–to–distortion

ratio at larger amplitudes than 40 dB below the peak ampli-

tude. This excess performance is at the expense of data per

sample. Two methods of data reduction are implemented by

compressing the 13–bit linear scheme to companded

pseudo–logarithmic 8–bit schemes. The two companding

schemes are: Mu–255 Law, primarily in North America and

Japan; and A–Law, primarily used in Europe. These com-

panding schemes are accepted world wide. These compand-

ing schemes follow a segmented or ‘‘piecewise–linear’’ curve

formatted as sign bit, three chord bits, and four step bits. For

a given chord, all sixteen of the steps have the same voltage

weighting. As the voltage of the analog input increases, the

four step bits increment and carry to the three chord bits

In a sampling environment, Nyquist theory says that to

properly sample a continuous signal, it must be sampled at a

frequency higher than twice the signal’s highest frequency

component. Voice contains spectral energy above 3 kHz, but

its absence is not detrimental to intelligibility. To reduce the

digital data rate, which is proportional to the sampling rate, a

sample rate of 8 kHz was adopted, consistent with a band-

width of 3 kHz. This sampling requires a low–pass filter to

limit the high frequency energy above 3 kHz from distorting

the in–band signal. The telephone line is also subject to

50/60 Hz power line coupling, which must be attenuated

from the signal by a high–pass filter before the analog–to–

digital converter.

The digital–to–analog conversion process reconstructs a

staircase version of the desired in–band signal, which has

spectral images of the in–band signal modulated about the

sample frequency and its harmonics. These spectral images

are called aliasing components, which need to be attenuated

to obtain the desired signal. The low–pass filter used to at-

tenuate these aliasing components is typically called a re-

construction or smoothing filter.

The MC145480 PCM Codec–Filter has the codec, both

presampling and reconstruction filters, a precision voltage

reference on–chip, and requires no external components.

MC145480

2

MOTOROLA

place this amplifier’s output (TG) into a high–impedance

state, thus allowing the TG pin to serve as a high–impedance

input to the transmit filter.

PIN DESCRIPTIONS

POWER SUPPLY

V

DD

TI–

Positive Power Supply (Pin 6)

Transmit Analog Input (Inverting) (Pin 18)

This is the most positive power supply and is typically con-

This is the inverting input of the transmit gain setting op-

erational amplifier. Gain setting resistors are usually con-

nected from this pin to TG and from this pin to the analog

signal source. The common mode range of the TI+ and TI–

nected to + 5 V. This pin should be decoupled to V

0.1 µF ceramic capacitor.

with a

SS

V

SS

Negative Power Supply (Pin 15)

pins is from 1.2 V to V

Connecting both TI+ and TI– pins to V

– 2 V. This is an FET gate input.

will place this ampli-

DD

This is the most negative power supply and is typically

connected to 0 V.

fier’s output (TG) into a high–impedance state, thus allowing

the TG pin to serve as a high–impedance input to the trans-

mit filter.

V

AG

Analog Ground Output (Pin 20)

TG

This output pin provides a mid–supply analog ground reg-

Transmit Gain (Pin 17)

ulated to 2.4 V. This pin should be decoupled to V

0.01 µF to 0.1 µF ceramic capacitor. All analog signal pro-

with a

SS

This is the output of the transmit gain setting operational

amplifier and the input to the transmit band–pass filter. This

op amp is capable of driving a 2 kΩ load. Connecting both

cessing within this device is referenced to this pin. If the au-

dio signals to be processed are referenced to V , then

special precautions must be utilized to avoid noise between

SS

TI+ and TI– pins to V

into a high–impedance state, thus allowing the TG pin to

serve as a high–impedance input to the transmit filter. All sig-

will place this amplifier’s output (TG)

DD

V

and the V

pin. Refer to the applications information in

pin becomes

SS

AG

this document for more information. The V

high impedance when this device is in the powered down

mode.

AG

nals at this pin are referenced to the V

impedance when the device is in the powered down mode.

pin. This pin is high

AG

CONTROL

RO+

Receive Analog Output (Non–Inverting) (Pin 1)

Mu/A

Mu/A Law Select (Pin 16)

This is the non–inverting output of the receive smoothing

filter from the digital–to–analog converter. This output is

capable of driving a 2 kΩ load to 1.575 V peak referenced to

This pin controls the compression for the encoder and the

expansion for the decoder. Mu–Law companding is selected

when this pin is connected to V

the V

pin. This pin is high impedance when the device is in

and A–Law companding is

AG

DD

the powered down mode.

selected when this pin is connected to V

.

SS

RO–

PDI

Receive Analog Output (Inverting) (Pin 2)

Power–Down Input (Pin 10)

This pin puts the device into a low power dissipation mode

when a logic 0 is applied. When this device is powered down,

all of the clocks are gated off and all bias currents are turned

This is the inverting output of the receive smoothing filter

from the digital–to–analog converter. This output is capable

of driving a 2 kΩ load to 1.575 V peak referenced to the V

AG

off, which causes RO+, RO–, PO–, PO+, TG, V , and DT to

pin. This pin is high impedance when the device is in the

powered down mode.

AG

become high impedance. The device will operate normally

when a logic 1 is applied to this pin. The device goes through

a power–up sequence when this pin is taken to a logic 1

state, which prevents the DT PCM output from going low im-

pedance for at least two FST cycles. The filters must settle

out before the DT PCM output or the RO+ or RO– receive

analog outputs will represent a valid analog signal.

PI

Power Amplifier Input (Pin 3)

This is the inverting input to the PO– amplifier. The non–

inverting input to the PO– amplifier is internally tied to the

V

pin. The PI and PO– pins are used with external resis-

AG

tors in an inverting op amp gain circuit to set the gain of the

PO+ and PO– push–pull power amplifier outputs. Connect-

ANALOG INTERFACE

ing PI to V

will power down the power driver amplifiers and

TI+

DD

the PO+ and PO– outputs will be high impedance.

Transmit Analog Input (Non–Inverting) (Pin 19)

This is the non–inverting input of the transmit input gain

setting operational amplifier. This pin accommodates a differ-

ential to single–ended circuit for the input gain setting op

PO–

Power Amplifier Output (Inverting) (Pin 4)

amp. This allows input signals that are referenced to the V

This is the inverting power amplifier output, which is used

to provide a feedback signal to the PI pin to set the gain of

the push–pull power amplifier outputs. This pin is capable of

driving a 300 Ω load to PO+. The PO+ and PO– outputs are

differential (push–pull) and capable of driving a 300 Ω load to

3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage

SS

pin with minimum noise.

pin to be level shifted to the V

This pin may be connected to the V

AG

pin for an inverting

AG

amplifier configuration if the input signal is already refer-

enced to the V pin. The common mode range of the TI+

AG

and TI– pins is from 1.2 V, to V

gate input. Connecting both TI+ and TI– pins to V

minus 2 V. This is an FET

DD

will

and signal reference of this output is the V

pin. The V

DD

AG

MOTOROLA

MC145480

3

pin cannot source or sink as much current as this pin, and

therefore low impedance loads must be between PO+ and

FSR

Frame Sync, Receive (Pin 7)

PO–. Connecting PI to V

will power down the power driver

DD

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts an 8 kHz clock, which synchronizes

the input of the serial PCM data at the DR pin. FSR can be

asynchronous to FST in the Long Frame Sync or Short

Frame Sync modes. When an ISDN mode (IDL or GCI) has

been selected with BCLKR, this pin selects either B1 (logic 0)

or B2 (logic 1) as the active data channel.

amplifiers and the PO+ and PO– outputs will be high imped-

ance. This pin is also high impedance when the device is

powered down by the PDI pin.

PO+

Power Amplifier Output (Non–Inverting) (Pin 5)

This is the non–inverting power amplifier output, which is

an inverted version of the signal at PO–. This pin is capable

BCLKR

Bit Clock, Receive (Pin 9)

of driving a 300 Ω load to PO–. Connecting PI to V

will

DD

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts any bit clock frequency from 64 to

4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,

and DR become IDL Interface compatible. When this pin is

held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-

face compatible.

power down the power driver amplifiers and the PO+ and

PO– outputs will be high impedance. This pin is also high im-

pedance when the device is powered down by the PDI pin.

See PI and PO– for more information.

DIGITAL INTERFACE

DR

MCLK

Master Clock (Pin 11)

Data, Receive (Pin 8)

This pin is the PCM data input, and when in a Long Frame

Sync or Short Frame Sync mode is controlled by FSR and

BCLKR. When in the IDL or GCI mode, this data transfer is

controlled by FST and BCLKT. FSR and BCLKR select the

B channel and ISDN mode, respectively.

This is the master clock input pin. The clock signal applied

to this pin is used to generate the internal 256 kHz clock and

sequencing signals for the switched–capacitor filters, ADC,

and DAC. The internal prescaler logic compares the clock on

this pin to the clock at FST (8 kHz) and will automatically

accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For

MCLK frequencies of 256 and 512 kHz, MCLK must be syn-

chronous and approximately rising edge aligned to FST. For

optimum performance at frequencies of 1.536 MHz and

higher, MCLK should be synchronous and approximately ris-

ing edge aligned to the rising edge of FST. In many ap-

plications, MCLK may be tied to the BCLKT pin.

FUNCTIONAL DESCRIPTION

ANALOG INTERFACE AND SIGNAL PATH

The transmit portion of this device includes a low–noise,

three–terminal op amp capable of driving a 2 kΩ load. This

op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its

output is TG (Pin 17). This op amp is intended to be confi-

gured in an inverting gain circuit. The analog signal may be

applied directly to the TG pin if this transmit op amp is inde-

pendently powered down by connecting the TI+ and TI–

FST

Frame Sync, Transmit (Pin 14)

inputs to the V

power supply. The TG pin becomes high

DD

This pin accepts an 8 kHz clock that synchronizes the out-

put of the serial PCM data at the DT pin. This input is com-

patible with various standards including IDL, Long Frame

Sync, Short Frame Sync, and GCI formats. If both FST and

FSR are held low for several 8 kHz frames, the device will

power down.

impedance when the transmit op amp is powered down. The

TG pin is internally connected to a 3–pole anti–aliasing pre–

filter. This pre–filter incorporates a 2–pole Butterworth active

low–pass filter, followed by a single passive pole. This pre–

filter is followed by a single–ended to differential converter

that is clocked at 512 kHz. All subsequent analog processing

utilizes fully–differential circuitry. The next section is a fully–

differential, 5–pole switched–capacitor low–pass filter with a

3.4 kHz frequency cutoff. After this filter is a 3–pole

switched–capacitor high–pass filter having a cutoff fre-

quency of about 200 Hz. This high–pass stage has a trans-

mission zero at dc that eliminates any dc coming from the

analog input or from accumulated op amp offsets in the pre-

ceding filter stages. The last stage of the high–pass filter is

an autozeroed sample and hold amplifier.

BCLKT

Bit Clock, Transmit (Pin 12)

This pin controls the transfer rate of transmit PCM data. In

the IDL and GCI modes it also controls the transfer rate of

the receive PCM data. This pin can accept any bit clock fre-

quency from 64 to 4096 kHz for Long Frame Sync and Short

Frame Sync timing. This pin can accept clock frequencies

from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz

to 6.176 MHz for GCI timing mode.

One bandgap voltage reference generator and digital–to–

analog converter (DAC) are shared by the transmit and re-

ceive sections. The autozeroed, switched–capacitor

bandgap reference generates precise positive and negative

reference voltages that are virtually independent of tempera-

ture and power supply voltage. A binary–weighted capacitor

array (CDAC) forms the chords of the companding structure,

while a resistor string (RDAC) implements the linear steps

within each chord. The encode process uses the DAC, the

voltage reference, and a frame–by–frame autozeroed

DT

Data, Transmit (Pin 13)

This pin is controlled by FST and BCLKT and is high im-

pedance except when outputting PCM data. When operating

in the IDL or GCI mode, data is output in either the B1 or B2

channel as selected by FSR. This pin is high impedance

when the device is in the powered down mode.

MC145480

4

MOTOROLA

comparator to implement a successive–approximation con-

version algorithm. All of the analog circuitry involved in the

data conversion (the voltage reference, RDAC, CDAC, and

comparator) are implemented with a differential architecture.

The receive section includes the DAC described above, a

sample and hold amplifier, a 5–pole, 3400 Hz switched ca-

pacitor low–pass filter with sinX/X correction, and a 2–pole

active smoothing filter to reduce the spectral components of

the switched capacitor filter. The output of the smoothing fil-

ter is buffered by an amplifier, which is output at the RO+ and

RO– pins. These outputs are capable of driving a 4 kΩ load

must be present. The DT output will remain in a high–imped-

ance state for at least two FST pulses after power–up.

MASTER CLOCK

Since this codec–filter design has a single DAC architec-

ture, the MCLK pin is used as the master clock for all analog

signal processing including analog–to–digital conversion,

digital–to–analog conversion, and for transmit and receive fil-

tering functions of this device. The clock frequency applied to

the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,

1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-

vice has a prescaler that automatically determines the proper

divide ratio to use for the MCLK input, which achieves the re-

quired 256 kHz internal sequencing clock. The clocking re-

quirements of the MCLK input are independent of the PCM

data transfer mode (i.e., Long Frame Sync, Short Frame

Sync, IDL mode, or GCI mode).

differentially or a 2 kΩ load to the V

pin. The MC145480

AG

also has a pair of power amplifiers that are connected in a

push–pull configuration. The PI pin is the inverting input to

the PO– power amplifier. The non–inverting input is internally

tied to the V

pin. This allows this amplifier to be used in an

AG

inverting gain circuit with two external resistors. The PO+

amplifier has a gain of minus one, and is internally con-

nected to the PO– output. This complete power amplifier cir-

cuit is a differential (push–pull) amplifier with adjustable gain

that is capable of driving a 300 Ω load to +12 dBm. The

power amplifier may be powered down independently of the

DIGITAL I/O

The MC145480 is pin selectable for Mu–Law or A–Law.

Table 1 shows the 8–bit data word format for positive and

negative zero and full scale for both companding schemes

(see Tables 3 and 4 at the end of this document for a com-

plete PCM word conversion table). Table NO TAG shows the

series of eight PCM words for both Mu–Law and A–Law that

correspond to a digital milliwatt. The digital mW is the 1 kHz

calibration signal reconstructed by the DAC that defines the

absolute gain or 0 dBm0 Transmission Level Point (TLP) of

the DAC. The 0 dBm0 level for Mu–Law is 3.17 dB below the

maximum level for an unclipped tone signal. The 0 dBm0

level for A–Law is 3.14 dB below the maximum level for an

unclipped tone signal. The timing for the PCM data transfer is

independent of the companding scheme selected. Refer to

Figure NO TAG for a summary and comparison of the four

PCM data interface modes of this device.

rest of the chip by connecting the PI pin to V

.

DD

POWER–DOWN

There are two methods of putting this device into a low

power consumption mode, which makes the device nonfunc-

tional and consumes virtually no power. PDI is the power–

down input pin which, when taken low, powers down the

device. Another way to power the device down is to hold both

the FST and FSR pins low. When the chip is powered down,

the V , TG, RO+, RO–, PO+, PO–, and DT outputs are high

AG

impedance. To return the chip to the power–up state, PDI

must be high and either the FST or the FSR frame sync pulse

Table 1. PCM Codes for Zero and Full Scale

Mu–Law

A–Law

Chord Bits

0 1 0

Level

+ Full Scale

+ Zero

Sign Bit

Chord Bits

0 0 0

Step Bits

0 0 0 0

1 1 1 1

0 0 0 0

Sign Bit

Step Bits

1 0 1 0

0 1 0 1

1 0 1 0

1

0

1

0

1 1 1

1 0 1

– Zero

1 1 1

1 0 1

– Full Scale

0 0 0

0 1 0

Table 2. PCM Codes for Digital mW

Mu–Law

A–Law

Chord Bits

0 1 1

Phase

π/8

Sign Bit

Chord Bits

0 0 1

Step Bits

1 1 1 0

1 0 1 1

1 1 1 0

1 0 1 1

1 1 1 0

Sign Bit

Step Bits

0 1 0 0

0 0 0 1

0 1 0 0

0 0 0 1

0 1 0 0

0

1

0

1

3π/8

0 0 0

0 1 0

5π/8

0 0 0

0 1 0

7π/8

0 0 1

0 1 1

9π/8

0 0 1

0 1 1

11π/8

13π/8

15π/8

0 0 0

0 1 0

0 0 0

0 1 0

0 0 1

0 1 1

MOTOROLA

MC145480

5

FST (FSR)

BCLKT (BCLKR)

DT

1

2

3

4

5

6

7

8

DR

DON’T CARE

8

DON’T CARE

Figure NO TAGa. Long Frame Sync (Transmit and Receive Have Individual

Clocking)

FST (FSR)

BCLKT (BCLKR)

DT

DR

1

2

3

4

5

6

7

8

DON’T CARE

8

DON’T CARE

Figure NO TAGb. Short Frame Sync (Transmit and Receive Have Individual

Clocking)

IDL SYNC (FST)

IDL CLOCK (BCLKT)

IDL TX (DT)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

DON’T

CARE

DON’T

CARE

IDL RX (DR)

DON’T CARE

8

B1–CHANNEL (FSR = 0)

B2–CHANNEL (FSR = 1)

Figure NO TAGc. IDL Interface — BCLKR = 1 (Transmit and Receive Have Common

Clocking)

FSC (FST)

DCL (BCLKT)

D

(DT)

(DR)

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

out

DON’T

CARE

D

8

DON’T CARE

in

B1–CHANNEL (FSR = 0)

B2–CHANNEL (FSR = 1)

Figure NO TAGd. GCI Interface — BCLKR = 0 (Transmit and Receive Have Common

Clocking)

Figure 2. Digital Timing Modes for the PCM Data Interface

MC145480

6

MOTOROLA

Long Frame Sync

able’’ is used for two specific synchronizing functions. The

first is to synchronize the PCM data word transfer, and the

second is to control the internal analog–to–digital and digital–

to–analog conversions. The term ‘‘Sync’’ refers to the func-

tion of synchronizing the PCM data word onto or off of the

multiplexed serial PCM data bus, which is also known as a

PCM highway. The term ‘‘Short’’ comes from the duration of

the frame sync measured in PCM data clock cycles. Short

Frame Sync timing occurs when the frame sync is used as a

‘‘pre–synchronization’’ pulse that is used to tell the internal

logic to clock out the PCM data word under complete control

of the data clock. The Short Frame Sync is held high for one

falling data clock edge. The device outputs the PCM data

word beginning with the following rising edge of the data

clock. This results in the PCM output going low impedance

with the rising edge of the transmit data clock, and remaining

low impedance until the middle of the LSB (seven and a half

PCM data clock cycles).

Long Frame Sync is the industry name for one type of

clocking format that controls the transfer of the PCM data

words. (Refer to Figure NO TAGa.) The ‘‘Frame Sync’’ or

‘‘Enable’’ is used for two specific synchronizing functions.

The first is to synchronize the PCM data word transfer, and

the second is to control the internal analog–to–digital and

digital–to–analog conversions. The term ‘‘Sync’’ refers to the

function of synchronizing the PCM data word onto or off of

the multiplexed serial PCM data bus, which is also known as

a PCM highway. The term ‘‘Long’’ comes from the duration of

the frame sync measured in PCM data clock cycles. Long

Frame Sync timing occurs when the frame sync is used di-

rectly as the PCM data output driver enable. This results in

the PCM output going low impedance with the rising edge of

the transmit frame sync, and remaining low impedance for

the duration of the transmit frame sync.

The implementation of Long Frame Sync has maintained

compatibility and been optimized for external clocking sim-

plicity. This optimization includes the PCM data output going

low impedance with the logical AND of the transmit frame

sync (FST) with the transmit data bit clock (BCLKT). The op-

timization also includes the PCM data output (DT) remaining

low impedance until the middle of the LSB (seven and a half

PCM data clock cycles) or until the FST pin is taken low,

whichever occurs last. This requires the frame sync to be

approximately rising edge aligned with the initiation of the

PCM data word transfer, but the frame sync does not have a

precise timing requirement for the end of the PCM data word

transfer. The device recognizes Long Frame Sync clocking

when the frame sync is held high for two consecutive falling

edges of the transmit data clock. The transmit logic decides

on each frame sync whether it should interpret the next

frame sync pulse as a Long or a Short Frame Sync. This de-

cision is used for receive circuitry also. The device is de-

signed to prevent PCM bus contention by not allowing the

PCM data output to go low impedance for at least two frame

sync cycles after power is applied or when coming out of the

powered down mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit PCM data word. Thus the

PCM digital switch needs to be able to generate only one

type of frame sync for use by both transmit and receive sec-

tions of the device.

The logical AND of the receive frame sync with the receive

data clock tells the device to start latching the 8–bit serial

word into the receive data input on the falling edges of the

receive data clock. The internal receive logic counts the re-

ceive data clock cycles and transfers the PCM data word to

the digital–to–analog converter sequencer on the ninth data

clock rising edge.

The device recognizes Short Frame Sync clocking when

the frame sync is held high for one and only one falling edge

of the transmit data clock. The transmit logic decides on each

frame sync whether it should interpret the next frame sync

pulse as a Long or a Short Frame Sync. This decision is used

for receive circuitry also. The device is designed to prevent

PCM bus contention by not allowing the PCM data output to

go low impedance for at least two frame sync cycles after

power is applied or when coming out of the powered down

mode.

The receive side of the device is designed to accept the

same frame sync and data clock as the transmit side and to

be able to latch its own transmit PCM data word. Thus the

PCM digital switch needs to be able to generate only one

type of frame sync for use by both transmit and receive sec-

tions of the device.

The falling edge of the receive data clock latching a high

logic level at the receive frame sync input tells the device to

start latching the 8–bit serial word into the receive data input

on the following eight falling edges of the receive data clock.

The internal receive logic counts the receive data clock

cycles and transfers the PCM data word to the digital–to–

analog converter sequencer on the rising data clock edge af-

ter the LSB has been latched into the device.

This device is compatible with four digital interface modes.

To ensure that this device does not reprogram itself for a dif-

ferent timing mode, the BCLKR pin must change logic state

no less than every 125 µs. The minimum PCM data bit clock

frequency of 64 kHz satisfies this requirement.

Interchip Digital Link (IDL)

The Interchip Digital Link (IDL) Interface is one of two

standard synchronous 2B+D ISDN timing interface modes

with which this device is compatible. In the IDL mode, the de-

vice can communicate in either of the two 64 kbps B chan-

nels (refer to Figure NO TAGc for sample timing). The IDL

mode is selected when the BCLKR pin is held high for two or

more FST (IDL SYNC) rising edges. The digital pins that con-

trol the transmit and receive PCM word transfers are repro-

grammed to accommodate this mode. The pins affected are

FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of

four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),

and IDL RX (DR). The IDL interface mode provides access to

both the transmit and receive PCM data words with common

control clocks of IDL Sync and IDL Clock. In this mode, the

This device is compatible with four digital interface modes.

To ensure that this device does not reprogram itself for a dif-

ferent timing mode, the BCLKR pin must change logic state

no less than every 125 µs. The minimum PCM data bit clock

frequency of 64 kHz satisfies this requirement.

Short Frame Sync

Short Frame Sync is the industry name for the type of

clocking format that controls the transfer of the PCM data

words (refer to Figure NO TAGb). The ‘‘Frame Sync’’ or ‘‘En-

MOTOROLA

MC145480

7

FSR pin controls whether the B1 channel or the B2 channel

is used for both transmit and receive PCM data word trans-

fers. When the FSR pin is low, the transmit and receive PCM

words are transferred in the B1 channel, and for FSR high

the B2 channel is selected. The start of the B2 channel is ten

IDL CLK cycles after the start of the B1 channel.

The IDL SYNC (FST, Pin 14) is the input for the IDL frame

synchronization signal. The signal at this pin is nominally

high for one cycle of the IDL Clock signal and is rising edge

aligned with the IDL Clock signal. (Refer to Figure 4 and the

IDL Timing specifications for more details.) This event identi-

fies the beginning of the IDL frame. The frequency of the IDL

Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST)

should be aligned approximately with the rising edge of

MCLK. MCLK must be one of the clock frequencies specified

in the Digital Switching Characteristics table, and is typically

tied to IDL CLK (BCLKT).

The IDL CLK (BCLKT, Pin 12) is the input for the PCM

data clock. All IDL PCM transfers and data control sequenc-

ing are controlled by this clock following the IDL SYNC. This

pin accepts an IDL data clock frequency of 256 kHz to 4.096

MHz.

The IDL TX (DT, Pin 13) is the output for the transmit PCM

data word. Data bits are output for the B1 channel on se-

quential rising edges of the IDL CLK signal beginning after

the IDL SYNC pulse. If the B2 channel is selected, then the

PCM word transfer starts on the eleventh IDL CLK rising

edge after the IDL SYNC pulse. The IDL TX pin will remain

low impedance for the duration of the PCM word until the

LSB after the falling edge of IDL CLK. The IDL TX pin will re-

main in a high impedance state when not outputting PCM

data or when a valid IDL Sync signal is missing.

The FSC (FST, Pin 14) is the input for the GCI frame syn-

chronization signal. The signal at this pin is nominally rising

edge aligned with the DCL clock signal. (Refer to Figure 6

and the GCI Timing specifications for more details.) This

event identifies the beginning of the GCI frame. The frequen-

cy of the FSC synchronization signal is 8 kHz. The rising

edge of the FSC (FST) should be aligned approximately with

the rising edge of MCLK. MCLK must be one of the clock fre-

quencies specified in the Digital Switching Characteristics

table, and is typically tied to DCL (BCLKT).

The DCL (BCLKT, Pin 12) is the input for the clock that

controls the PCM data transfers. The clock applied at the

DCL input is twice the actual PCM data rate. The GCI frame

begins with the logical AND of the FSC with the DCL. This

event initiates the PCM data word transfers for both transmit

and receive. This pin accepts a GCI data clock frequency of

512 kHz to 6.176 MHz for PCM data rates of 256 kHz to

3.088 MHz.

The GCI D

(DT, Pin 13) is the output for the transmit

out

PCM data word. Data bits are output for the B1 channel on

alternate rising edges of the DCL clock signal, beginning with

the FSC pulse. If the B2 channel is selected, then the PCM

word transfer starts on the seventeenth DCL rising edge after

the FSC rising edge. The D

for 15–1/2 DCL clock cycles. The D

pin will remain low impedance

pin becomes high

out

impedance after the second falling edge of the DCL clock

during the LSB of the PCM word. The D pin will remain in

out

a high–impedance state when not outputting PCM data or

when a valid FSC signal is missing.

The D (DR, Pin 8) is the input for the receive PCM data

in

word. Data bits are latched in for the B1 channel on alternate

rising edges of the DCL clock signal, beginning with the se-

cond DCL clock after the rising edge of the FSC pulse. If the

B2 channel is selected then the PCM word is latched in start-

ing on the eighteenth DCL rising edge after the FSC rising

edge.

The IDL RX (DR, Pin 8) is the input for the receive PCM

data word. Data bits are input for the B1 channel on sequen-

tial falling edges of the IDL CLK signal beginning after the

IDL SYNC pulse. If the B2 channel is selected, then the PCM

word is latched in starting on the eleventh IDL CLK falling

edge after the IDL SYNC pulse.

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

The MC145480 is manufactured using high–speed CMOS

VLSI technology to implement the complex analog signal

processing functions of a PCM Codec–Filter. The fully–differ-

ential analog circuit design techniques used for this device

result in superior performance for the switched capacitor fil-

ters, the analog–to–digital converter (ADC) and the digital–

to–analog converter (DAC). Special attention was given to

the design of this device to reduce the sensitivities of noise,

including power supply rejection and susceptibility to radio

frequency noise. This special attention to design includes a

fifth order low–pass filter, followed by a third order high–pass

filter whose output is converted to a digital signal with greater

than 75 dB of dynamic range, all operating on a single 5 V

power supply. This results in a Mu–Law LSB size for small

audio signals of about 386 µV. The typical idle channel noise

level of this device is less than one LSB. In addition to the

dynamic range of the codec–filter function of this device, the

input gain–setting op amp has the capability of greater than

35 dB of gain intended for an electret microphone interface.

This device was designed for ease of implementation, but

due to the large dynamic range and the noisy nature of the

environment for this device (digital switches, radio tele-

phones, DSP front–end, etc.) special care must be taken to

assure optimum analog transmission performance.

General Circuit Interface (GCI)

The General Circuit Interface (GCI) is the second of two

standard synchronous 2B+D ISDN timing interface modes

with which this device is compatible. In the GCI mode, the

device can communicate in either of the two 64 kbps B–

channels. (Refer to Figure 2d for sample timing.) The GCI

mode is selected when the BCLKR pin is held low for two or

more FST (FSC) rising edges. The digital pins that control

the transmit and receive PCM word transfers are repro-

grammed to accommodate this mode. The pins affected are

FST, FSR, BCLKT, DT, and DR. The GCI Interface consists

of four pins: FSC (FST), DCL (BCLKT), D

(DT), and D

out

in

(DR). The GCI interface mode provides access to both the

transmit and receive PCM data words with common control

clocks of FSC (frame synchronization clock) and DCL (data

clock). In this mode, the FSR pin controls whether the B1

channel or the B2 channel is used for both transmit and re-

ceive PCM data word transfers. When the FSR pin is low, the

transmit and receive PCM words are transferred in the B1

channel, and for FSR high the B2 channel is selected. The

start of the B2 channel is 16 DCL cycles after the start of the

B1 channel.

MC145480

8

MOTOROLA

PC BOARD MOUNTING

resulting from the high speed digital current spikes. The

magnitude of digitally induced voltage spikes may be

hundreds of times larger than the analog signal the

device is required to digitize.

It is recommended that the device be soldered to the PC

board for optimum noise performance. If the device is to be

used in a socket, it should be placed in a low parasitic pin

inductance (generally, low–profile) socket.

7. Use a short, wide, low inductance trace to connect the

V

power supply pin to the 5 V power supply.

DD

Depending on the application, a double–sided PCB with

bypass capacitors to the V ground plane, as

POWER SUPPLY, GROUND, AND NOISE

CONSIDERATIONS

V

DD

SS

described above, may complete the low impedance

coupling for the power supply. For a multilayer PC board

This device is intended to be used in switching applica-

tions which often require plugging the PC board into a rack

with power applied. This is known as ‘‘hot–rack insertion.’’ In

these applications care should be taken to limit the voltage

with a power plane, connecting all of the V

pins to the

DD

power plane would be the optimal power distribution

method. The integrated circuit layout and packaging

on any pin from going positive of the V

pins, or negative of

DD

pins. One method is to extend the ground and power

considerations for the 5 V V

power circuit are

ground circuit.

DD

essentially the same as for the V

the V

SS

contacts of the PCB connector. The device has input protec-

tion on all pins and may source or sink a limited amount of

current without damage. Current limiting may be accom-

plished by series resistors between the signal pins and the

connector contacts.

8. The V

AG

pin is the reference for all analog signal

processing. In some applications the audio signal to be

digitized may be referenced to the V ground. To

SS

reduce the susceptibility to noise at the input of the ADC

section, the three–terminal op amp may be used in a

differential to single–ended circuit to provide level

The most important considerations for PCB layout deal

with noise. This includes noise on the power supply, noise

generated by the digital circuitry on the device, and cross

coupling digital or radio frequency signals into the audio sig-

nals of this device. The best way to prevent noise is to:

1. Keep digital signals as far away from audio signals as

possible.

conversion from the V

ground to the V ground with

SS

AG

noise cancellation. The op amp may be used for more

than35dBofgaininmicrophoneinterfacecircuits, which

will require a compact layout with minimum trace lengths

as well as isolation from noise sources. It is recom-

mended that the layout be as symmetrical as possible to

avoid any imbalances which would reduce the noise

cancelling benefits of this differential op amp circuit.

Refer to the application schematics for examples of this

circuitry.

2. Keep radio frequency signals as far away from the audio

signals as possible.

3. Use short, low inductance traces for the audio circuitry

to reduce inductive, capacitive, and radio frequency

noise sensitivities.

If possible, reference audio signals to the V

pin. Handset receivers and tele-

AG

4. Use short, low inductance traces for digital and RF

circuitry to reduce inductive, capacitive, and radio

frequency radiated noise.

instead of to the V

SS

phone line interface circuits using transformers may be

audio signal referenced completely to the V pin. Re-

AG

fer to the application schematics for examples of this

circuitry. The V pin cannot be used for ESD or line

5. Bypass capacitors should be connected from the V

DD

and V

AG

pins to V with minimal trace length. Ceramic

SS

AG

monolithic capacitors of about 0.1 µF are acceptable to

decouple the device from its own noise. The V

protection.

DD

9. For applications using multiple MC145480 PCM Codec–

capacitor helps supply the instantaneous currents of the

digital circuitry in addition to decoupling the noise which

may be generated by other sections of the device or

other circuitry on the power supply. The V

capacitor helps to reduce the impedance of the V

Filters, the V pins cannot be tied together. The V

AG AG

pins are capable of sourcing and sinking current and will

each be driving the node, which will result in large

contention currents, crosstalk susceptibilities, and in-

creased noise.

decoupling

AG

to V

at frequencies above the bandwidth of the V

SS

AG

generator, which reduces the susceptibility to RF noise.

6. Use a short, wide, low inductance trace to connect the

10. The MC145480 is fabricated with advanced high–speed

CMOS technology that is capable of responding to noise

pulses on the clock pins of 1 ns or less. It should be noted

that noise pulses of such short duration may not be seen

with oscilloscopes that have less bandwidth than

600 MHz. The most often encountered sources of clock

noise spikes are inductive or capacitive coupling of

high–speed logic signals, and ground bounce. The best

solution for addressing clock spikes from coupling is to

separate the traces and use short low inductance PC

board traces. To address ground bounce problems, all

integrated circuits should have high frequency bypass

capacitors directly across their power supply pins, with

low inductance traces for ground and power supply. A

less than optimum solution may be to limit the bandwidth

of the trace by adding series resistance and/or capaci-

tance at the input pin.

V

groundpintothepowersupplyground.TheV pin

SS

is the digital ground and the most negative power supply

pin for the analog circuitry. All analog signal processing

is referenced to the V

circuitry will probably be powered by this same ground,

care must be taken to minimize high frequency noise in

pin, but because digital and RF

AG

the V

trace. Depending on the application, a double–

sided PCB with a V ground plane connecting all of the

SS

digital and analog V

pins together would be a good

SS

grounding method. A multilayer PC board with a ground

plane connecting all of the digital and analog V pins

SS

together would be the optimal ground configuration.

These methods will result in the lowest resistance and

the lowest inductance in the ground circuit. This is

important to reduce voltage spikes in the ground circuit

MOTOROLA

MC145480

9

MAXIMUM RATINGS (Voltages Referenced to V

Rating

Pin)

SS

Symbol

Value

Unit

V

DC Supply Voltage

V

DD

– 0.5 to 6

Voltage on Any Analog Input or Output Pin

Voltage on Any Digital Input or Output Pin

Operating Temperature Range

Storage Temperature Range

V

– 0.3 to V

+ 0.3

V

SS

DD

V

SS

DD

T

– 40 to + 85

– 85 to +150

°C

A

T

stg

POWER SUPPLY (T = – 40 to + 85°C)

A

Characteristics

Min

Typ

Max

Unit

V

DC Supply Voltage

4.75

5.0

5.25

Active Power Dissipation

(No Load, PI ≥ V

(No Load, PI ≤ V

– 0.5 V)

– 1.5 V)

—

23

25

33

35

mW

DD

Power–Down Dissipation (V for Logic Levels Must be ≥ 3.0 V)

IH

PDI = V

FST and FSR = V , PDI = V

SS

—

0.01

0.1

0.5

1.0

mW

SS

DD

DIGITAL LEVELS (V

= + 5 V ± 5%, V = 0 V, T = – 40 to + 85°C)

SS A

DD

Characteristics

Symbol

Min

—

Max

0.6

—

Unit

V

Input Low Voltage

Input High Voltage

V

IL

V

IH

2.2

—

V

Output Low Voltage (DT Pin, I = 2.5 mA)

OL

V

OL

0.4

—

V

Output High Voltage (DT Pin, I

OH

= – 2.5 mA)

V

I

V

– 0.5

V

OH

DD

Input Low Current (V

SS

≤ V ≤ V

in DD

)

I

IL

– 10

—

+ 10

10

µA

pF

Input High Current (V

SS

≤ V ≤ V )

in DD

IH

Output Current in High Impedance State (V

SS

≤ DT ≤ V

DD

)

I

OZ

Input Capacitance of Digital Pins (Except DT)

Input Capacitance of DT Pin when High–Z

C

in

C

—

15

out

MC145480

10

MOTOROLA

ANALOG ELECTRICAL CHARACTERISTICS (V

= + 5 V ± 5%, V = 0 V, T = – 40 to + 85°C)

SS A

DD

Characteristics

Min

—

1.2

—

0

Typ

Max

± 1.0

—

Unit

mA

MΩ

pF

Input Current

TI+, TI–

± 0.1

1.0

—

AC Input Impedance to V

AG

(1 kHz)

Input Capacitance

10

Input Offset Voltage of TG Op Amp

Input Common Mode Voltage Range

Input Common Mode Rejection Ratio

—

± 5

mV

V

– 2.0

DD

60

3000

95

—

dB

Gain Bandwidth Product (10 kHz) of TG Op Amp (R ≥ 10 kΩ)

kHz

dB

L

DC Open Loop Gain of TG Op Amp (R ≥ 10 kΩ)

—

L

Equivalent Input Noise (C–Message) Between TI+ and TI– at TG

Output Load Capacitance for TG Op Amp

Output Voltage Range for TG

– 30

—

dBrnC

pF

100

V

(R = 10 kΩ to V

AG

)

0.5

1.0

—

V

DD

V

DD

– 0.5

– 1.0

L

(R = 2 kΩ to V

)

L

AG

Output Current (0.5 V ≤ V

≤ V

DD

– 0.5 V)

TG, RO+, RO–

TG, RO+, and RO–

RO+ or RO–

± 1.0

2

—

mA

kΩ

Ω

out

Output Load Resistance to V

AG

—

Output Impedance (0 to 3.4 kHz)

Output Load Capacitance

—

1

RO+ or RO–

0

—

500

± 25

2.6

—

pF

DC Output Offset Voltage of RO+ or RO– Referenced to V

AG

—

mV

V

Output Voltage Referenced to V

(No Load)

Output Current with ± 25 mV Change in Output Voltage

2.2

± 2.0

2.4

± 10

AG

SS

V

AG

mA

dBC

Power Supply Rejection Ratio

(0 to 100 kHz @100 mVrms Applied to V

Transmit

Receive

50

80

75

—

,

DD

C–Message Weighting, All Analog Signals

Referenced to V Pin)

AG

Power Drivers PI, PO+, PO–

Input Current (V

AG

– 0.5 V ≤ PI ≤ V

AG

+ 0.5 V)

PI

—

10

± 0.05

—

± 1.0

—

mA

MΩ

mV

mA

Ω

Input Resistance (V

AG

– 0.5 V ≤ PI ≤ V + 0.5 V)

AG

Input Offset Voltage

Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–)

Output Current (V + 0.7 V ≤ PO+ or PO– ≤ V – 0.7 V)

—

± 20

± 50

—

± 10

—

SS DD

PO+ or PO– Output Resistance (Inverted Unity Gain for PO–)

Gain Bandwidth Product (10 kHz, Open Loop for PO–)

1

—

1000

—

kHz

pF

Load Capacitance (PO+ or PO– to V , or PO+ to PO–)

AG

0

1000

+ 0.2

—

Gain of PO+ Relative to PO– (R = 300 Ω, + 3 dBm0, 1 kHz)

– 0.2

45

0

dB

L

Total Signal to Distortion at PO+ and PO– with a 300 Ω Differential Load

60

dBC

dB

Power Supply Rejection Ratio

(0 to 25 kHz @ 100 mVrms Applied to V

0 to 4 kHz

4 to 25 kHz

40

—

55

40

—

.

DD

PO– Connected to PI. Differential or Measured

Referenced to V Pin.)

AG

MOTOROLA

MC145480

11

ANALOG TRANSMISSION PERFORMANCE

(V

DD

= + 5 V ± 5%, V

= 0 V, All Analog Signals Referenced to V , 0 dBm0 = 0.775 Vrms = + 0 dBm @ 600 Ω, FST = FSR = 8 kHz,

SS

AG

BCLKT = MCLK = 2.048 MHz Synchronous Operation, T = – 40 to + 85°C, Unless Otherwise Noted)

A

End–to–End

A/D

D/A

Characteristics

Units

dB

Min

Max

Min

Max

Min

Max

Absolute Gain (0 dBm0 @ 1.02 kHz, T = 25°C, V

= 5.0 V)

—

– 0.25 + 0.25 – 0.25 + 0.25

A

DD

Absolute Gain Variation with Temperature

0 to + 70°C

– 40 to + 85°C

—

± 0.03

± 0.05

—

± 0.03

± 0.05

dB

Absolute Gain Variation with Power Supply (T = 25°C)

—

± 0.03

—

± 0.04

dB

A

Gain vs Level Tone (Mu–Law, Relative to – 10 dBm0, 1.02 kHz)

+ 3 to – 40 dBm0 @ 0 to + 85°C

—

– 0.25 + 0.25 – 0.20 + 0.20

– 0.25 + 0.25 – 0.25 + 0.25

– 0.8

– 1.3

+ 3 to – 40 dBm0 @ – 40 to 0°C

– 40 to – 50 dBm0 @ 0 to + 85°C

– 40 to – 50 dBm0 @ – 40 to 0°C

– 50 to – 55 dBm0 @ 0 to + 85°C

– 50 to – 55 dBm0 @ – 40 to 0°C

+ 0.8

+ 1.3

– 0.5

– 0.9

– 1.0

– 1.8

+ 0.5

+ 0.9

+ 1.0

+ 1.8

Gain vs Level Pseudo Noise, CCITT G.712

(A–Law, Relative to – 10 dBm0)

– 10 to – 40 dBm0

– 40 to – 50 dBm0

– 50 to – 55 dBm0

—

– 0.25 + 0.25 – 0.25 + 0.25

– 0.60 + 0.30 – 0.30 + 0.30

– 1.00 + 0.45 – 0.45 + 0.45

dB

Total Distortion, 1.02 kHz Tone (Mu–Law, C–Message Weighting)

dBC

+ 3 dBm0

—

34

36

30

28.5

25

—

34

36

30

28.5

25

—

0 to – 30 dBm0

– 40 dBm0 @ 0 to + 85°C

– 40 dBm0 @ – 40 to 0°C

– 45 dBm0

Total Distortion, Pseudo Noise, CCITT G.714 (A–Law)

– 3 dBm0

– 6 to – 27 dBm0

—

30.0

35.0

34.0

28.5

28.0

13.5

—

30.0

36.0

34.5

29.5

28.5

14.5

—

dB

– 34 dBm0

– 40 dBm0 @ 0 to + 85°C

– 40 dBm0 @ – 40 to 0°C

– 55 dBm0

Idle Channel Noise (For End–to–End and A/D, See Note 1)

(Mu–Law, C–Message Weighted)

(A–Law, Psophometric Weighted)

—

18

– 68

—

11

– 78

dBrnc0

dBm0p

Frequency Response (Relative to 1.02 kHz @ 0 dBm0)

15 Hz

50 Hz

60 Hz

—

– 40

– 30

– 26

– 0.4

– 0.5

0

dB

200 Hz

300 to 3000 Hz

3300 Hz

– 1.0

– 0.20 + 0.15 – 0.15 + 0.15

– 0.35 + 0.15 – 0.35 + 0.15

– 0.8

—

3400 Hz

4000 Hz

0

– 14

– 32

– 0.8

—

0

– 14

30

4600 Hz to 100 kHz

—

In–Band Spurious (1.02 kHz @ 0 dBm0, Transmit and Receive)

300 to 3000 Hz

dB

—

– 48

—

– 48

—

– 48

Out–of–Band Spurious at RO+ (300 to 3400 Hz @ 0 dBm0 in)

4600 to 7600 Hz

7600 to 8400 Hz

8400 to 100,000 Hz

—

– 30

– 40

– 30

—

– 30

– 40

– 30

Idle Channel Noise Selective (8 kHz, Input = V , 30 Hz Bandwidth)

AG

—

– 70

—

– 70

205

dBm0

µs

Absolute Delay (1600 Hz)

315

Group Delay Referenced to 1600 Hz

500 to 600 Hz

600 to 800 Hz

—

210

130

70

35

70

– 40

– 30

—

85

µs

800 to 1000 Hz

1000 to 1600 Hz

1600 to 2600 Hz

2600 to 2800 Hz

2800 to 3000 Hz

95

145

—

110

175

Crosstalk of 1020 Hz @ 0 dBm0 from A/D or D/A (Note 2)

—

– 75

—

– 70

dB

Intermodulation Distortion of Two Frequencies of Amplitudes

(– 4 to – 21 dBm0 from the Range 300 to 3400 Hz)

—

– 41

—

– 41

—

– 41

NOTES:

1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.

2. Selectively measured while stimulated with 2667 Hz @ – 50 dBm0.

MC145480

12

MOTOROLA

DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC

(V

DD

= + 5 V ± 5%, V

= 0 V, All Digital Signals Referenced to V , T = – 40 to + 85°C, C = 150 pF, Unless Otherwise Noted)

SS

A

L

Ref.

No.

Characteristics

Min

Typ

Max

Unit

1

Master Clock Frequency for MCLK

—

256

512

—

kHz

1536

1544

2048

2560

4096

1

2

MCLK Duty Cycle for 256 kHz Operation

45

50

—

50

64

50

20

80

0

—

55

—

%

ns

kHz

ns

Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)

Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)

Rise Time for All Digital Signals

3

—

4

50

—

5

Fall Time for All Digital Signals

6

Setup Time from MCLK Low to FST High

7

Setup Time from FST High to MCLK Low

—

8

Bit Clock Data Rate for BCLKT or BCLKR

4096

—

9

Minimum Pulse Width High for BCLKT or BCLKR

Minimum Pulse Width Low for BCLKT or BCLKR

Hold Time from BCLKT (BCLKR) Low to FST (FSR) High

Setup Time for FST (FSR) High to BCLKT (BCLKR) Low

Setup Time from DR Valid to BCLKR Low

10

11

12

13

14

—

Hold Time from BCLKR Low to DR Invalid

50

—

LONG FRAME SPECIFIC TIMING

15

16

17

18

Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low

Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data

Delay Time from BCLKT High to DT for Valid Chord and Step Bit Data

50

—

10

—

60

ns

Delay Time from the Later of the 8th BCLKT Falling Edge, or the Falling Edge

of FST to DT Output High Impedance

19

Minimum Pulse Width Low for FST or FSR

50

—

ns

SHORT FRAME SPECIFIC TIMING

20

21

22

23

Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low

Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low

Delay Time from BCLKT High to DT Data Valid

50

10

—

60

ns

Delay Time from the 8th BCLKT Low to DT Output High Impedance

MOTOROLA

MC145480

13

1

7

4

3

5

6

2

MCLK

8

1

2

3

4

5

6

7

8

9

BCLKT

12

9

11

15

10

FST

DT

16

18

17

18

16

MSB

CH1

CH2

CH3

ST1

ST2

ST3

LSB

8

1

2

3

4

5

6

7

8

9

BCLKR

FSR

11

15

9

12

10

14

13

MSB

CH1

CH2

CH3

ST1

ST2

ST3

LSB

DR

Figure 3. Long Frame Sync Timing

MC145480

14

MOTOROLA

1

7

4

3

5

6

2

MCLK

12

8

1

2

3

4

5

6

7

8

9

BCLKT

FST

9

20

21

10

11

23

22

MSB

CH1

CH2

CH3

ST1

ST2

ST3

LSB

DT

8

1

2

3

4

5

6

7

8

9

BCLKR

20

9

21

10

11

12

FSR

DR

14

13

MSB

CH1

CH2

CH3

ST1

ST2

ST3

LSB

Figure 4. Short Frame Sync Timing

MOTOROLA

MC145480

15

DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE

(V

DD

= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 5 and Note 1)

A L

Ref.

No.

31

32

33

34

35

36

37

38

39

40

41

Characteristics

Min

Max

Unit

Time Between Successive IDL Syncs

Note 2

Hold Time of IDL SYNC After Falling Edge of IDL CLK

Setup Time of IDL SYNC Before Falling Edge IDL CLK

IDL Clock Frequency

20

60

256

50

20

75

10

—

ns

kHz

ns

4096

—

IDL Clock Pulse Width High

IDL Clock Pulse Width Low

—

Data Valid on IDL RX Before Falling Edge of IDL CLK

Data Valid on IDL RX After Falling Edge of IDL CLK

Falling Edge of IDL CLK to High–Z on IDL TX

Rising Edge of IDL CLK to Low–Z and Data Valid on IDL TX

Rising Edge of IDL CLK to Data Valid on IDL TX

—

50

60

50

NOTES:

1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.

2. In IDL mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words

are accessed during the B2 channel as shown in Figure 5. IDL accesses must occur at a rate of 8 kHz (125 µs interval).

31

IDLE SYNC

(FST)

32

33

32

34

35

IDL CLOCK

(BCLKT)

1

2

3

4

5

6

7

8

9

10

39

11

12

13

14

15

16

17

18

19

1

2

36

41

39

40

41

40

IDL TX

(DT)

MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB

38

MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB

38

37

IDL RX

(DR)

MSB CH1 CH2 CH3 ST1 ST2 ST3 LSB

Figure 5. IDL Interface Timing

MC145480

16

MOTOROLA

DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE

(V

DD

= 5.0 V ± 5%, T = – 40 to + 85°C, C = 150 pF, See Figure 6 and Note 1)

A L

Ref.

No.

42

43

44

45

46

47

48

49

50

51

52

53

Characteristics

Min

Max

Unit

Time Between Successive FSC Pulses

DCL Clock Frequency

Note 2

512

50

20

60

—

6176

—

kHz

ns

DCL Clock Pulse Width High

DCL Clock Pulse Width Low

—

Hold Time of FSC After Falling Edge of DCL

Setup Time of FSC to DCL Falling Edge

Rising Edge of DCL (After Rising Edge of FSC) to Low Impedance and Valid Data of D

—

60

50

—

out

Rising Edge of FSC (While DCL is High) to Low Impedance and Valid Data of D

out

—

Rising Edge of DCL to Valid Data on D

out

—

Second DCL Falling Edge During LSB to High Impedance of D

out

10

20

—

Setup Time of D Before Rising Edge of DCL

in

Hold Time of D After DCL Rising Edge

in

60

NOTES:

1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.

2. In GCI mode, both transmit and receive 8–bit PCM words are accessed during the B1 channel, or both transmit and receive 8–bit PCM words

are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (125 µs interval).

42

FSC

(FST)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

DCL

(BCLKT)

51

50

48

51

49

MSB CH1

53

CH2

CH3 ST1

ST2

ST3 LSB

MSB CH1

CH2

CH3

ST1

53

ST2

ST3 LSB

D

(DT)

(DR)

out

52

CH2

MSB CH1

CH3

ST1

ST3

LSB

MSB CH1

ST1

ST2

ST3

LSB

D

in

46

FSC

(FST)

46

47

43

44

DCL

(BCLKT)

5

1

2

3

4

49

45

48

D

(DT)

(DR)

MSB

CH1

out

52

53

D

MSB

CH1

in

Figure 6. GCI Interface Timing

MOTOROLA

MC145480

17

0.1

µ

F

+

–

1

2

20

19

18

17

16

15

14

13

12

11

RO+

RO–

PI

V

10 k

Ω

AG

AUDIO OUT

ANALOG IN

1.0

µ

F

10 k

Ω

TI+

TI–

3

10 kΩ

10 k

Ω

4

PO–

PO+

TG

µ

5

Mu/A

+ 5 V

6

V

+ 5 V

DD

SS

7

FSR

DR

FST

DT

8 kHz

0.1 µF

8

PCM OUT

2.048 MHz

9

BCLKR

PDI

BCLKT

MCLK

10

PCM IN

Figure 7. MC145480 Test Circuit with Differential Input and Output

AUDIO OUT

0.1 µF

1

2

20

19

18

17

16

15

14

13

12

11

R

≥

2 kΩ

RO+

RO–

PI

10 kΩ

V

L

AG

1.0

µ

F

10 kΩ

TI+

TI–

10 k

Ω

3

68 µF

AUDIO OUT

10 kΩ

ANALOG IN

+

4

PO–

PO+

TG

R

≥

150

Ω

L

µ

5

Mu/A

+ 5 V

10 k

Ω

6

V

+ 5 V

DD

SS

7

FSR

DR

FST

DT

8 kHz

0.1 µF

8

PCM OUT

2.048 MHz

9

BCLKR

PDI

BCLKT

MCLK

10

PCM IN

Figure 8. MC145480 Test Circuit with Input and Output Referenced to V

SS

MC145480

18

MOTOROLA

2.048 MHz

18 pF

10 MΩ

+ 5 V

2.048 MHz

(BCLKT, BCLKR, MCLK)

300

Ω

V

R

OSC IN

OSC

OUT 1 OUT 2

OSC

CC

8 kHz

(FST, FSR)

MC74HC4060

Q4

0.1 µF

GND

Q8

+ 5 V

V

CC

J

Q

J

Q

1/2 MC74HC73

K

Q

K

Q

GND

R

+ 5 V

8 kHz

256

1

2

3

4

5

6

7

8

9

2.048 MHz

Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz

+5 V

1 k

Ω

SIDETONE

0.1

µF

68 µF

1 kΩ

420 pF

20

19

18

17

16

15

14

13

12

11

1

2

RO+

RO–

V

AG

75 k

Ω

0.1

µ

F

1 k

Ω

TI+

MIC

1 kΩ

3

4

PI

TI–

TG

0.1

µ

PO–

PO+

75 kΩ

REC

5

+ 5 V

Mu/A

420 pF

6

V

+ 5 V

DD

SS

7

IDL SYNC – 8 kHz

IDL TX

FSR

DR

FST

DT

0.1 µF

8

+ 5 V

9

BCLKT

BCLKR

PDI

IDL CLOCK – 2.048 MHz

10

MCLK

IDL RX

B1 – 0 V

B2 – + 5 V

Figure 10. MC145480 Analog Interface to Handset with IDL Clocking

MOTOROLA

MC145480

19

1.0

µF

10 kΩ

1

2

20

19

18

17

16

15

14

13

12

11

RO+

RO–

PI

V

AG

10 k

Ω

TI+

TI–

R0 = 600

Ω

TIP

R0

10 kΩ

3

0.1 µF

10 kΩ

4

PO–

PO+

TG

N = 1

5

Mu/A

+ 5 V

RING

6

V

+ 5 V

DD

SS

7

FSR

DR

FST

DT

FSC – 8 kHz

0.1 µF

8

D

out

9

BCLKR

PDI

BCLKT

MCLK

DCL – 4.096 MHz

10

D

in

B1 – 0 V

B2 – + 5 V

Figure 11. MC145480 Transformer Interface to 600 Ω Telephone Line with GCI Clocking

1.0 µF

10 kΩ

R0 = 600

Ω

TIP

20

19

18

17

16

15

14

13

12

11

1

2

RO+

RO–

PI

V

AG

10 k

Ω

TI+

TI–

N = 0.5

1/4 R0

10 kΩ

3

0.1 µF

20 kΩ

4

PO–

PO+

TG

N = 0.5

5

– 48 V

Mu/A

+ 5 V

6

+ 5 V

N = 0.5

V

SS

DD

7

8 kHz

FSR

DR

FST

DT

RING

0.1 µF

8

PCM OUT

2.048 MHz

9

BCLKR

PDI

BCLKT

MCLK

10

PCM IN

Figure 12. MC145480 Step–Up Transformer Interface to 600 Ω Telephone Line

MC145480

20

MOTOROLA

Table 3. Mu–Law Encode–Decode Characteristics

Normalized

Digital Code

Encode

Decision

Levels

Normalized

Decode

Levels

1

2

3

4

5

6

7

8

Chord

Number

of Steps

Step

Size

Sign

Chord Chord Chord Step

Step Step

Step

8159

7903

4319

4063

2143

2015

1055

991

511

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8031

4191

2079

1023

495

231

99

8

16

256

7

6

5

4

3

2

1

16

128

64

32

16

8

479

239

223

103

95

4

35

33

31

15

1

2

1

3

1

0

1

0

1

2

0

NOTES:

1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.

2. Digital code includes inversion of all magnitude bits.

MOTOROLA

MC145480

21

Table 4. A–Law Encode–Decode Characteristics

Normalized

Digital Code

Encode

Decision

Levels

Normalized

Decode

Levels

1

2

3

4

5

6

7

8

Chord

Number

of Steps

Step

Size

Sign

Chord Chord Chord Step

Step Step

Step

4096

3968

2176

2048

1088

1024

544

512

272

256

136

128

68

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4032

2112

1056

528

264

132

66

7

16

128

6

5

4

3

2

16

32

64

32

16

8

4

64

1

2

1

0

NOTES:

1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.

2. Digital code includes inversion of all even numbered bits.

MC145480

22

MOTOROLA

PACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP

CASE 738–03

-A-

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

20

1

11

10

B

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

C

L

INCHES

MILLIMETERS

DIM

A

B

C

D

E

F

G

J

K

L

M

N

MIN

MAX

1.070

0.260

0.180

0.022

MIN

25.66

6.10

3.81

0.39

1.27 BSC

1.27

2.54 BSC

0.21

MAX

27.17

6.60

4.57

0.55

1.010

0.240

0.150

0.015

0.050 BSC

0.050

0.100 BSC

0.008

0.110

-T-

SEATING

PLANE

K

M

0.070

1.77

E

N

0.015

0.140

0.38

3.55

G

F

J 20 PL

2.80

0.300 BSC

15

0.040

7.62 BSC

15

0.51 1.01

D 20 PL

M

0.25 (0.010)

T

B

0°

°

0°

°

0.020

M

0.25 (0.010)

T

A

DW SUFFIX

SOG PACKAGE

CASE 751D–04

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

20

11

4. MAXIMUM MOLD PROTRUSION 0.150

(0.006) PER SIDE.

10X P

–B–

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

M

0.010 (0.25)

B

1

10

MILLIMETERS

INCHES

20X D

DIM

A

B

C

D

MIN

12.65

7.40

2.35

0.35

0.50

MAX

12.95

7.60

2.65

0.49

0.90

MIN

MAX

0.510

0.299

0.104

0.019

0.035

J

0.499

0.292

0.093

0.014

0.020

M

S

0.010 (0.25)

T

A

B

F

G

J

K

M

P

R

1.27 BSC

0.050 BSC

0.25

0.10

0

0.32

0.25

7

0.010

0.004

0

0.012

0.009

7

R X 45

10.05

0.25

10.55

0.75

0.395

0.010

0.415

0.029

C

SEATING

PLANE

–T–

M

18X G

K

MOTOROLA

MC145480

23

VF SUFFIX

SSOP

CASE 940C–03

20X K REF

0.12 (0.005)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

M

S

T

U

V

Y14.5M, 1982.

0.25 (0.010)

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.15 (0.006) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION/INTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13 (0.005)

TOTAL IN EXCESS OF K DIMENSION AT

MAXIMUM MATERIAL CONDITION. DAMBAR

INTRUSION SHALL NOT REDUCE DIMENSION

K BY MORE THAN 0.07 (0.002) AT LEAST

MATERIAL CONDITION.

N

20

11

10

L/2

M

B

N

L

F

PIN 1

IDENT

1

DETAIL E

–U–

A

–V–

K

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE –W–.

M

S

J

0.20 (0.008)

T U

J1

MILLIMETERS

INCHES

K1

DIM

A

B

C

D

F

G

H

J

J1

K

MIN

7.07

5.20

1.73

0.05

0.63

MAX

7.33

5.38

1.99

0.21

0.95

MIN

MAX

0.288

0.212

0.078

0.008

0.037

0.278

0.205

0.068

0.002

0.024

SECTION N–N

–W–

C

0.65 BSC

0.026 BSC

0.076 (0.003)

0.59

0.09

0.25

7.65

0

0.75

0.20

0.16

0.38

0.33

7.90

8

0.023

0.003

0.010

0.301

0

0.030

0.008

0.006

0.015

0.013

0.311

8

SEATING

PLANE

–T–

D

G

DETAIL E

H

K1

L

M

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different

applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does

not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE: Motorola Literature Distribution;

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447

6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609

INTERNET: http://Design–NET.com

HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MC145480/D

◊

MC145480

24

MOTOROLA


型号：	MC145480DW
厂家：	MOTOROLA
描述：	5 V PCM Codec-Filter 5 V PCM编解码器，过滤器解码器过滤器编解码器电信集成电路电信电路光电二极管 PC
文件：	总24页 (文件大小：417K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC145480DW [MOTOROLA]

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