MC145574AEGR2 [MOTOROLA]
DATACOM, DIGITAL SLIC, PDSO28, 0.600 INCH, PLASTIC, SOIC-28;
| 型号： | MC145574AEGR2 |
| 厂家： | 
MOTOROLA |
| 描述： | DATACOM, DIGITAL SLIC, PDSO28, 0.600 INCH, PLASTIC, SOIC-28 光电二极管 |
| 文件： | 总167页 (文件大小：671K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC145574/D
REV 6
MC145574
ISDN S/T-Interface Transceiver
Coming through loud and clear.
m
This page intentionally left blank.
MC145574
ISDN S/T-Interface Transceiver
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Motorola, Inc. 1999
MC145574 TABLE OF CONTENTS
MC145574 ISDN S/T-INTERFACE TRANSCEIVER
SECTION 1
INTRODUCTION
1.1
1.2
1.3
1.4
1.5
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORGANIZATION OF DATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1–1
1–2
1–3
1–3
SECTION 2
WIRING CONFIGURATIONS
2.1
2.2
2.3
2.4
2.5
2.6
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POINT–TO–POINT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SHORT PASSIVE BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTENDED PASSIVE BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BRANCHED PASSIVE BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT1 STAR MODE OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1
2–1
2–2
2–2
2–3
2–3
SECTION 3
ACTIVATION/DEACTIVATION OF S/T TRANSCEIVER
3.1
3.2
3.3
3.4
3.5
3.6
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMISSION STATES FOR NT MODE S/T TRANSCEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMISSION STATES FOR TE MODE S/T TRANSCEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVATION OF S/T LOOP BY NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVATION OF S/T LOOP BY TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACTIVATION PROCEDURES IGNORED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–1
3–1
3–1
3–2
3–2
3.7
3.7.1
3.7.2
FRAME SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2
3–2
3–2
3.8
ACTIVATION INDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR1(2) — ERROR INDICATION (EI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEACTIVATION PROCEDURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2
3–2
3–3
3.9
3.10
3.11
3.11.1
3.11.2
INITIAL STATE OF B1 AND B2 CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3
3–3
3–3
3.12
ADDITIONAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M and N Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Echo Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Indication of Transmit and Receive States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3
3–3
3–3
3–4
3–4
3–4
3.12.1
3.12.2
3.12.3
3.12.4
3.12.5
MOTOROLA
MC145574
Contents–i
MC145574 TABLE OF CONTENTS
SECTION 4
THE INTERCHIP DIGITAL LINK
4.1
4.2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1
4–1
4.3
IDL2 STANDARD MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT IDL2 Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT IDL2 Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE IDL2 Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE IDL2 Master Free Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE IDL2 Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Relationship of the NT Transmit Signal with Respect to FSC/FSR . . . . . . . . . . . . . . . . . . . .
Phase Relationship of the TE Transmit Signal with Respect to FSC/FSR, When in the IDL2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of Multiple MC145574s in TE Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Independent Tx/Rx Frame Syncs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timeslot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short and Long Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSEN Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL2 Waveform Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2
4–2
4–3
4–3
4–3
4–3
4–4
4–4
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.6.1
4.3.6.2
4–4
4–4
4–4
4–4
4–8
4–9
4–9
4–9
4.3.6.3
4.3.6.4
4.3.6.5
4.3.6.6
4.3.6.7
4.3.6.8
4.3.6.9
SECTION 5
SERIAL CONTROL PORT
5.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1
5.2
SCP TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Nibble Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Nibble Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Byte Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Byte Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Merged Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1
5–1
5–2
5–3
5–4
5–5
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCPCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6
5–6
5–6
5–6
5–7
5–7
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.4
SCP HIGH–IMPEDANCE DIGITAL OUTPUT MODE (SCP HIDOM) . . . . . . . . . . . . . . . . . . . . . . . .
5–7
5.5
5.5.1
5.5.2
ADDITIONAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Independent of Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7
5–7
5–7
SECTION 6
GENERAL CIRCUIT INTERFACE
6.1
6.2
6.3
6.4
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCI FRAME STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLING THE GCI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCI INDIRECT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1
6–1
6–1
6–4
6.5
6.5.1
GCI DIRECT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6
6–6
Contents–ii
MC145574
MOTOROLA
MC145574 TABLE OF CONTENTS
SECTION 6 (continued)
6.5.2
6.6
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2B+D CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6
6–7
6.7
6.7.1
M AND A/E CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7
6–8
6.8
MONITOR CHANNEL MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Monitor Channel Response Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Monitor Channel Status Indication Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Accessible Monitor Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
SCP/GCI Register Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
6.9
COMMAND INDICATE CHANNEL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
GCI ACTIVATION AND DEACTIVATION TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
6.10
SECTION 7
PIN DESCRIPTIONS
7.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RxN, RxP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE/NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T_IN/TFSC/TCLK/FIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1
7–1
7–1
7–2
7–2
7–2
7–2
7–2
7–2
7–3
7–3
7–3
7–3
7–3
7–3
7–3
7–3
7–3
7–3
7–4
7–4
7–4
7–4
7–4
7–4
7–4
7–4
V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SG/DGRANT/ANDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DREQUEST/ANDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS/ECHO_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSC/FSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.2.24
7.2.25
7.2.26
D
D
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
in
out
SCP Tx/S0/M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Rx/S1/M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCPCLK/S2/M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCPEN/GCIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSEN/FST/BCL/LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ/IND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
DD
V
DD
V
DD
3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TxN, TxP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
ADDITIONAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP HIDOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–5
7–5
7–5
7–5
7.3.1
7.3.2
7.3.3
MOTOROLA
MC145574
Contents–iii
MC145574 TABLE OF CONTENTS
SECTION 8
NIBBLE REGISTER MAP DEFINITION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1
8–2
8–3
8–3
8–4
8–5
8–6
8–7
8–8
SECTION 9
BYTE REGISTER MAP DEFINITION
9.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–1
9–3
9–3
9–3
9–3
9–4
9–5
9–5
9–6
9–8
9–8
9–9
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
BR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
BR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
BR13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
BR14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
BR15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13
SECTION 10
OVERLAY REGISTER MAP DEFINITION
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
OR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
OR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
OR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
OR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4
OR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5
OR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6
OR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7
OR15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7
Contents–iv
MC145574
MOTOROLA
MC145574 TABLE OF CONTENTS
SECTION 11
D CHANNEL OPERATION
11.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
11.2
IDL2 D CHANNEL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Gaining Access to the D Channel in the TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Setting the Class for TE Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
Generation of an Interrupt in the TE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
Gaining Access to the D Channel in the NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
GCI D Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
SECTION 12
MULTIFRAMING
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1
ACTIVATION/DETECTION OF MULTIFRAMING IN THE MC145574 . . . . . . . . . . . . . . . . . . . . . . . 12–1
WRITING S CHANNEL DATA TO AN NT–CONFIGURED MC145574 . . . . . . . . . . . . . . . . . . . . . . 12–1
MULTIFRAME INTERRUPTS IN AN NT–CONFIGURED MC145574 . . . . . . . . . . . . . . . . . . . . . . . 12–2
READING Q CHANNEL DATA FROM AN NT–CONFIGURED MC145574 . . . . . . . . . . . . . . . . . . . 12–3
WRITING Q CHANNEL DATA TO A TE–CONFIGURED MC145574 . . . . . . . . . . . . . . . . . . . . . . . . 12–3
MULTIFRAME INTERRUPTS IN A TE–CONFIGURED MC145574 . . . . . . . . . . . . . . . . . . . . . . . . . 12–3
READING S SUBCHANNEL DATA FROM A TE–CONFIGURED MC145574 . . . . . . . . . . . . . . . . 12–3
MULTIFRAMING IN GCI MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3
SECTION 13
DEVICE CONFIGURATIONS
13.1
NT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
NT Fixed or Adaptive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
NT Master or Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
NT1 Star and NT Terminal Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
13.1.1
13.1.2
13.1.3
13.1.3.1 NT1 Star Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
13.1.3.2 NT Terminal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
13.2
13.2.1
13.2.2
TE CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
TE Master Mode (TEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5
TE Slave Mode (TES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5
SECTION 14
CLOCK INTERFACE
SECTION 15
INTERRUPTS
15.1
15.2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1
IRQ7 NR3(0) — NT : D CHANNEL COLLISION
TE : NOT APPLICABLE
NR4(0) — ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1
15.3
15.4
IRQ1 NR3(1) — TE: D CHANNEL COLLISION
NT: NOT APPLICABLE
NR4(1) — ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1
IRQ2 NR3(2) — MULTIFRAME RECEPTION
NR4(2) — ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1
MOTOROLA
MC145574
Contents–v
MC145574 TABLE OF CONTENTS
SECTION 15 (continued)
15.5
15.6
IRQ3 NR3(3) — CHANGE IN Rx INFO STATE
NR4(3) — ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2
IRQ6 NR3(1) — NT: FAR–END CODE VIOLATION (FECV) DETECTION
TE: NOT APPLICABLE
NR4(1) — ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2
15.7
GCI MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2
SECTION 16
TRANSMISSION LINE INTERFACE CIRCUITRY
16.1
16.2
16.3
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1
TRANSMIT LINE INTERFACE CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1
RECEIVE LINE INTERFACE CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1
16.4
ADDITIONAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3
Sources of Line Interface Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3
Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3
Protection Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3
16.4.1
16.4.2
16.4.3
SECTION 17
POWER MODE OPERATION
17.1
POWER SUPPLY STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1
17.2
POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1
Transmit Power–Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1
Absolute Minimum Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–2
Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–2
17.2.1
17.2.2
17.2.3
17.2.4
SECTION 18
ELECTRICAL SPECIFICATIONS
18.1
18.2
18.3
18.4
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1
DIGITAL DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–1
ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–2
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–2
18.5
18.5.1
18.5.2
IDL2 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–3
IDL2 Master Timing, 8– and 10–Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–3
IDL2 Slave Timing, 8– and 10–Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–4
18.6
18.7
18.8
18.9
GCI TIMING FOR MASTER AND SLAVE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–6
SCP TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–8
NT1 STAR MODE TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
D CHANNEL TIMING CHARACTERISTICS (IDL2 MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
Contents–vi
MC145574
MOTOROLA
MC145574 TABLE OF CONTENTS
SECTION 19
MECHANICAL DATA
19.1
19.2
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–1
PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–2
SECTION 20
F57J4 MASK SET DIFFERENCES
20.1
FUNCTIONAL DIFFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1
Differences in Section 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1
Differences in Section 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1
Differences in Section 13.1.3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20–1
20.1.1
20.1.2
20.1.3
APPENDIX A
MC145574EVK ISDN S/T–INTERFACE TRANSCEIVER EVALUATION KIT
A.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1
A.2
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2
A–2
A–2
A–2
A.2.1
A.2.2
A.2.3
A.3
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3
APPENDIX B
GLOSSARY OF TERMS AND ABBREVIATIONS
MOTOROLA
MC145574
Contents–vii
MC145574 LIST OF FIGURES
Figure 1–1.
Figure 2–1.
Figure 2–2.
Figure 2–3.
Figure 2–4.
Figure 4–1.
Figure 4–2.
Figure 4–3.
Figure 4–4.
Figure 4–5.
Figure 4–6.
Figure 4–7.
Figure 4–8.
Figure 5–1.
Figure 5–2.
Figure 5–3.
Figure 5–4.
Figure 5–5.
Figure 5–6.
Figure 5–7.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Point–to–Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Passive Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Passive Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branched Passive Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Relationship of NT Transmit Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two–Baud Turnaround in TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Relationship of TE Transmit Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Architecture of an NT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3
2–1
2–2
2–2
2–3
4–5
4–6
4–7
4–8
Standard IDL2 10–Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Standard IDL2 8–Bit Mode with Long Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10
Standard IDL2 8–Bit Slave Mode with Independent Frame Syncs . . . . . . . . . . . . . . . . . . . . . 4–10
Timeslot Operation with Independent Slave Frame Syncs, TSEN . . . . . . . . . . . . . . . . . . . . . . 4–11
Serial Control Port Nibble Register Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Port Nibble Register Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Port Byte Register Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Port Byte Register Read Operation Double 8–Bit Transaction . . . . . . . . . . . .
Serial Control Port Byte Register Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Byte Register Write Operation Double 8–Bit Transaction . . . . . . . . . . . . . . . .
Merged Serial Control Port Nibble Register Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2
5–2
5–3
5–4
5–4
5–5
5–5
6–2
6–3
6–4
6–9
Figure 6–1. a. Relative Channel Positions (GCI Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–1. b. Relative Channel Positions (GCI Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6–2.
Figure 6–3.
Figure 6–4.
Figure 6–5.
Figure 6–6.
Figure 7–1.
Figure 11–1.
Figure 13–1.
Figure 13–2.
Figure 13–3.
Figure 14–1.
Figure 14–2.
Figure 16–1.
Figure 16–2.
Figure 18–1.
Figure 18–2.
Figure 18–3.
Figure 18–4.
Figure 18–5.
Figure 18–6.
Figure 18–7.
Figure 19–1.
Figure 19–2.
Figure A–1.
Figure A–2.
GCI Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Channel Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation from TE End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Deactivation from NT End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Activation from NT End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1
SCIT Terminal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4
NT Family Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1
NT1 Star Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3
NT2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6
Typical Crystal Oscillator Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1
Connection with External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1
Transmit Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–2
Receive Line Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–2
IDL2 Master Timing, 8– and 10–Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–3
IDL2 Slave Timing, 8– and 10–Bit Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–5
GCI Timing For Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–7
SCP Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–8
NT1 Star Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
D Channel Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
D Channel Grant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–9
MC145574DW Pin Assignment (SOIC 28–Pin Package, Case 751F) . . . . . . . . . . . . . . . . . . 19–1
MC145574PB Pin Assignment (TQFP 32–Pin Package, Case 873A) . . . . . . . . . . . . . . . . . . 19–1
Motorola Silicon Applications and the MC145574EVK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1
A–3
Contents–viii
MC145574
MOTOROLA
MC145574 LIST OF TABLES
Table 3–1.
Table 3–2.
Table 4–1.
Table 6–1.
Table 6–2.
Table 6–3.
Table 6–4.
Table 6–5.
Table 6–6.
Table 6–7.
Table 6–8.
Table 6–9.
Table 8–1.
Table 8–2.
Table 8–3.
Table 9–1.
Table 9–2.
Table 9–3.
Table 9–4.
Table 9–5.
Table 9–6.
Table 10–1.
Table 10–2.
Table 10–3.
Table 10–4.
Table 11–1.
Table 11–2.
Table 11–3.
Table 12–1.
Table 12–2.
Table 12–3.
Table 13–1.
Table 13–2.
NT Mode Transmission States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TE Mode Transmission States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL2 Clock Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLK1, CLK0 GCI Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCI Timeslot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M2, M1, and M0 Pins in GCI NT Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M2, M1, and M0 Pins in GCI TE Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–1
4–2
6–4
6–5
6–6
6–7
Monitor Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Monitor Channel Response Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
Monitor Channel Status Indication Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
C/I Channel Commands and Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
GCI C/I Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
SCP Nibble Register Map for NT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCP Nibble Register Map for TE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nibble Register Initialization After Any Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Register Map for NT Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Register Map for TE Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Byte Register Initialization After Any Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDL2 Clock Speed Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1
8–1
8–2
9–1
9–2
9–2
9–8
BR11(5), BR11(4) Rx INFO State Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
BR11(3), BR11(2) Tx INFO State Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11
Overlay Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1
Overlay Register Initialization After Any Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2
S(2:0) GCI Timeslot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3
S(2:0) GCI Timeslot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4
Channel SCP Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
D Channel Operation Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1
MC145574 Class Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2
S Channel Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
Multiframe Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2
TE Multiframe Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3
Pin Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2
Pin Operations for Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4
MOTOROLA
MC145574
Contents–ix
Contents–x
MC145574
MOTOROLA
1
INTRODUCTION
1.1 INTRODUCTION
The MC145574 is Motorola’s second generation S/T transceiver and is a follow–up to the
MC145474/75 transceiver.
The MC145574 provides the improved interfacing capabilities and reduced power consumption re-
quired by today’s ISDN applications, while maintaining the functionality and extended range perfor-
mance of the MC145474/75.
The MC145574 provides an economical VLSI layer 1 interface for the transportation of two 64 kbps
B channels and one 16 kbps D channel between the network termination (NT) and terminal equipment
applications (TEs). The MC145574 conforms to CCITT I.430, ETSI ETS 300012, and ANSI T1.605
specifications.
The MC145574 provides the modulation/line drive and demodulation/line receive functions required
of the interface. In addition, the MC145574 provides the activation/deactivation, error monitoring, fram-
ing, bit, and octet timing. The MC145574 provides the control signals for the interface to the layer 2
devices. Complete multiframe capability is provided.
The MC145574 features the interchip digital link (IDL2) for the exchange of the 2B+D channel informa-
tion between ISDN components and systems. The MC145574 provides an industry standard serial
control port (SCP) to program the operation of the transceiver. As an alternative to the IDL2+SCP
combination, a general circuit interface (GCI) is provided.
The MC145574 is not pin compatible with the MC145474/75, but it does have a compatible register
set. However, to make full use of the additional MC145574 features, software enhancements are re-
quired.
1.2 ORGANIZATION OF DATA SHEET
This data sheet is comprised of 20 sections. Section 1 is an introduction, serving to outline the features,
package types, and pin assignments of the MC145574. Section 2 describes the various wiring configu-
rations which are applicable to the MC145574, and the operational distances as recommended by
CCITT I.430, ETSI ETS 300012, and ANSI T1.605. Section 3 addresses the activation and deactivation
procedures of the MC145574.
The MC145574 incorporates the IDL2. This is a four–wire interface used for full–duplex communication
between ICs on the board level. Two 64 kbps B channels and one 16 kbps D channel are transmitted
and received over this interface. Section 4 is a detailed description of the IDL2.
The MC145574 incorporates an SCP interface. The SCP is a four–wire interface conforming to an
industry standard multi–drop serial link. The SCP is compatible with Motorola’s serial peripheral inter-
face (SPI). The SCP makes use of seven nibble registers, 16 byte registers and 10 overlay registers.
Section 5 is a description of the SCP. A per bit description of the nibble, byte, and overlay registers
is provided in Sections 8, 9, and 10, respectively. When the MC145574 is configured as a TE, it is
equipped with five interrupt modes. When configured as an NT, it is equipped with four interrupt modes.
Section 15 describes these interrupts.
The MC145574 also features a GCI interface. This is a standard four–wire interface which allows full–
duplex transmission of two 64 kbps B channels and one 16 kbps D channel, multiplexed with control
and maintenance information channels. Section 6 is a description of the GCI.
MOTOROLA
MC145574
1–1
Section 7 contains pin descriptions of the MC145574. The pin descriptions differentiate between the
device configured for NT mode or TE mode of operation, and GCI and IDL2+SCP.
As mentioned previously, the MC145574 is used for the transmission of two 64 kbps B channels and
one 16 kbps D channel. Access to the B channels is determined by the network. The TEs gain access
to the D channel in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605 recommenda-
tions. A description of the D channel operation is contained in Section 11.
In addition to the 2B+D channels, the S/T transceiver has a multiframing capability. Multiframing is
a layer 1 signalling channel for use between the NT and the TE(s). The multiframing operation is de-
scribed in Section 12.
The MC145574 can be configured in several different operating modes depending on the application.
Section 13 describes all the possible configurations, whether in the NT or TE mode.
Section 16 describes how to interface the MC145574 to the S/T bus. Section 17 describes the various
power modes of operation. Section 18 contains electrical specifications, and Section 19 contains me-
chanical data relevant to the MC145574. Section 20 describes the differences between this data book
and the F57J4 mask version of the MC145574.
1.3 FEATURES
The features of the MC145574 are described below.
• Conforms to CCITT I.430, ETSI ETS 300012, and ANSI T1.605 Specifications
• Register Compatible With the First Generation MC145474/75
• Exceeds Q.502 Jitter Requirements for TE Slave Applications
• Pin Selectable NT or TE Modes of Operation
• Incorporates the IDL2, With Timeslot Assigner
• Industry Standard Microprocessor SCP
• GCI Interface
• Uses 2.5:1 Transformers for Transmit and Receive
• Exceeds the Recommended Range of Operation in All Configurations
• Complete Multiframing Capability Supported (SC1 – SC5 and Q Channel)
• Optional B Channel Idle, Invert, or Exchange
• Supports Full Range of S/T and IDL2 Loopbacks
• Supports Transmit Power–Down, Listening, and Absolute Minimum Power Modes
• Supports Crystal or External Clock Input Mode
• NT Star and NT Terminal Modes Supported
• Low Power Consumption
• Compatible with 3 V Devices
1–2
MC145574
MOTOROLA
1.4 BLOCK DIAGRAM
TxP TxN
DGRANT DREQUEST
RxP RxN
Rx
CORE
BLOCK
ISET
Tx
3 V REG
D CHANNEL
CONTROL
DEMODULATOR AND
TIMING RECOVERY
ACT/DEACT
LOGIC
MODULATOR
S AND Q
HANDLER
2B+D
2B+D
SCP CONTROL AND STATUS
EXTALOUT
XTALIN
CLK
LOGIC
SYSTEM BLOCK
VOLTAGE
REG
V
DD
IDL2 + SCP + GCI
INTERFACE
CONTROL AND DATA INTERFACE SIGNALS
Figure 1–1. Block Diagram
1.5 PACKAGING
The MC145574 comes in the following packages:
28–Pin, 600 mil Wide, Plastic SOIC
32–Pin, 700 mil Square, TQFP
The pin assignments for the MC145574 are described in Section 7. Package dimensions are in
Section 19.
MOTOROLA
MC145574
1–3
1–4
MC145574
MOTOROLA
2
WIRING CONFIGURATIONS
2.1 INTRODUCTION
The MC145574 ISDN S/T transceiver conforms to CCITT I.430, ETSI ETS 300012, and ANSI T1.605
specifications. It is a layer 1 transceiver designed for use at the ISDN S and T reference points. It
is designed for both point–to–point and multipoint operation. The S/T transceiver is designed for use
in either the network terminating (NT) mode or in the terminal endpoint (TE) applications. Two 64 kpbs
B channels and one 16 kbps D channel are transmitted in a full–duplex fashion across the interface.
Sections 2.2 through 2.6 contain suggested wiring configurations for use. These configurations are
deemed to be the most common but by no means the only wiring configurations. Section 16 specifies
the recommended circuitry for interfacing the MC145574 to the S/T bus. Note that when operating
in the TE mode, only one TE has the 100 Ω termination resistors in the transmit and receive paths.
Figures 2–1 through 2–4 illustrate where to connect the termination resistors for the described loop
configurations.
A description of the most commonly used loop configurations is as described below.
2.2 POINT-TO-POINT OPERATION
In the point–to–point mode of operation, one NT communicates with one TE. As such, 100 Ω termina-
tion resistors must be connected across the transmit and receive paths of both the NT and TE transceiv-
ers. Figure 2–1 illustrates this wiring configuration.
When using the MC145574 in this configuration, the NT must be in adaptive timing. This is accom-
plished by holding the FIX pin low; i.e., connecting it to V . Refer to Section 6 for a more detailed
SS
description of this pin function. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specify that the
S/T transceiver must be able to operate up to a distance of 1 km in the point–to–point mode. This
is the distance D1 as shown in Figure 2–1.
<
>
NT
D1
TE
TxP
RxP
TR
TR
TR
TR
TxN
RxN
MC145574
MC145574
RxP
TxP
RxN
TxN
Figure 2–1. Point–to–Point
MOTOROLA
MC145574
2–1
2.3 SHORT PASSIVE BUS OPERATION
The short passive bus is intended for use when up to eight TEs are required to communicate with
one NT. The TEs can be distributed at any point along the passive bus, the only requirement being
that the termination resistors be located at the end of the passive bus. Figure 2–2 illustrates this wiring
configuration. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specify a maximum operational dis-
tance from the NT of 200 meters. This corresponds to the distance D2 as shown in Figure 2–2.
<
>
D2
NT
TxP
TR
TR
TR
TR
TxN
MC145574
RxP
RxN
TxP TxN RxP RxN
TxP TxN RxP RxN
TxP TxN RxP RxN
MC145574
MC145574
MC145574
TE
TE
TE
Figure 2–2. Short Passive Bus
2.4 EXTENDED PASSIVE BUS OPERATION
A wiring configuration whereby the TEs are restricted to a grouping at the far end of the cable, distant
from the NT, is shown as the “Extended Passive Bus.” This configuration is shown in Figure 2–3. The
termination resistors are to be positioned as shown in Figure 2–3.
<
>
D4
NT
TxP
TR
TR
TR
TR
TxN
MC145574
RxP
RxN
TxP TxN RxP RxN
TxP TxN RxP RxN
MC145574
MC145574
TE
TE
<
>
D3
Figure 2–3. Extended Passive Bus
MC145574
2–2
MOTOROLA
The essence of this configuration is that a restriction is placed on the distance between the TEs. The
distance, D3 (as shown in Figure 2–3), corresponds to the maximum distance between the grouping
of TEs. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specify a distance of 25 – 50 meters for
the separation between the TEs, and a distance of 500 meters for the total length. These distances
correspond to the distances D3 and D4 as shown in Figure 2–3.
Note that the “NT configured” MC145574 should be placed in the adaptive timing mode for this configu-
ration. This is achieved by holding the FIX pin low.
2.5 BRANCHED PASSIVE BUS OPERATION
A wiring configuration which has somewhat similar characteristics to those of the “extended passive
bus” is known as the “branched passive bus” and is shown in Figure 2–4. In this configuration the
branching occurs at the end of the bus. The branching occurs after a distance D1 from the NT. The
distance D5 corresponds to the maximum separation between the TEs.
<
><
>
TE
D5
D1
NT
RxP
TxP
TR
TR
TR
TR
RxN
TxN
MC145574
MC145574
TxP
RxP
TxN
RxN
TxP TxN RxP RxN
MC145574
TE
Figure 2–4. Branched Passive Bus
2.6 NT1 STAR MODE OF OPERATION
A wiring configuration which may be used to support multiple T interfaces is known as the “NT1 Star
mode of operation.” This mode of operation is supported by the MC145574. This mode is described
in Section 11. Note that the NT1 Star mode contains multiple NTs. Each of these NTs can be connected
to either a passive bus (short, extended, or branched) or to a single TE.
MOTOROLA
MC145574
2–3
2–4
MC145574
MOTOROLA
3
ACTIVATION/DEACTIVATION OF S/T TRANSCEIVER
3.1 INTRODUCTION
CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define five information states for the S/T transceiver.
When the NT is in the fully operational state, it transmits INFO 4. When the TE is in the fully operational
state, it transmits INFO 3. INFO 1 is transmitted by the TE when it wants to wake up the NT. INFO 2
is transmitted by the NT when it wants to wake up the TE, or in response to the TE’s transmitted
INFO 1. These states cause unique patterns of symbols to be transmitted over the S/T–interface.
Only when the S/T loop is in the fully activated state are the 2B+D channels of data transmitted over
the interface.
3.2 TRANSMISSION STATES FOR NT MODE S/T TRANSCEIVER
When configured as an NT, an S/T transceiver can be in any of the following transmission states shown
in Table 3–1.
Table 3–1. NT Mode Transmission States
Information State
INFO 0
Description
The NT transmits 1s in every bit position. This corresponds to no signal being transmitted.
INFO 2
The NT sets its B1, B2, D, and E channels to 0. The A bit is set to 0. (See Sections 3.12.1 and
3.12.2.)
INFO 4
INFO 4 corresponds to frames containing operational data on the B1, B2, D, and E channels.
The A bit is set to 1.
3.3
TRANSMISSION STATES FOR TE MODE S/T TRANSCEIVER
When configured as a TE, an S/T transceiver can be in any of the following transmission states shown
in Table 3–2.
Table 3–2. TE Mode Transmission States
Information State
INFO 0
Description
The TE transmits 1s in every bit position. This corresponds to no signal being transmitted.
INFO 1
The TE transmits a continuous signal with the following pattern: positive 0, negative 0, six 1s.
This signal is asynchronous to the NT.
INFO 3
INFO 3 corresponds to frames containing operational data on the B1, B2, and D channels. If
INFO 4 or INFO 2 is being received, INFO 3 will be synchronized to it.
3.4 ACTIVATION OF S/T LOOP BY NT
The NT activates the loop by transmitting INFO 2 to the TE(s). This is accomplished in the MC145574
by setting NR2(3) to a 1 (see Section 3.12.3). Note that this bit is internally reset to 0 after the internal
activation state machine has recognized its active transition.
The TE on receiving INFO 2 synchronizes to it and transmits back INFO 3 to the NT. The NT, on
receiving INFO 3 from the TE, responds with INFO 4, thus activating the loop.
MOTOROLA
MC145574
3–1
3.5 ACTIVATION OF S/T LOOP BYTE
The TE activates an inactive loop by transmitting INFO 1 to the NT. This is accomplished in the
MC145574 by setting NR2(3) to a 1. Note that this bit is internally reset to 0 after the internal activation
state machine has recognized its active transition.
The NT, upon detecting INFO 1 from the TE, responds with INFO 2. The TE, upon receiving a signal
from the NT, ceases transmission of INFO 1, reverting to transmitting INFO 0. After synchronizing
to the received signal and having fully verified that it is INFO 2, the TE responds with INFO 3, thus
activating the loop.
3.6
ACTIVATION PROCEDURES IGNORED
The MC145574 has the capability of being forced into the highest transmission state. This is accom-
plished by setting BR7(7) to a 1. Thus when this bit is set in the NT, it forces the NT to transmit INFO 4.
Correspondingly, in the TE, setting this bit to 1 forces the TE to transmit INFO 3.
Note that CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications allow a TE to be activated
by reception of INFO 4, without having to go through the intermediate handshaking. This is to allow
for the situation where a TE is connected to an already active loop.
However, an NT can not be activated by a TE sending it INFO 3, without going through the intermediate
INFO 1, INFO 2, INFO 3, and INFO 4 states.
This “Activation Procedures Ignored” feature is provided for test purposes, allowing the NT to forcibly
activate the TE(s). In the TE, the forced transmission of INFO 3 enables verification of the TEs opera-
tion.
3.7 FRAME SYNC
3.7.1
NT Mode
When the S/T transceiver in the NT mode is receiving INFO 3 from the TE(s) and has achieved frame
synchronization, it sets the FSYNC status bit NR1(0) high.
3.7.2
TE Mode
When the TE is receiving either INFO 2 or INFO 4 from the NT, and has achieved frame synchronization,
the MC145574 internally sets the SCP nibble bit, NR1(0). NR1(0) performs this function in both the
NT and TE modes, for the MC145574.
3.8
ACTIVATION INDICATION
NR1(3), the activation indication bit, is used to signify that the loop is fully active. When the MC145574
is configured as an NT, this corresponds to the NT transmitting INFO 4 and receiving INFO 3. When
the MC145574 is configured as a TE, this corresponds to it transmitting INFO 3 and receiving INFO 4.
When the loop is in the fully active state, NR1(3) is internally set high.
3.9
NR1(2) Ċ ERROR INDICATION (EI)
NR1(2) is set by the MC145574 S/T transceiver to indicate an error condition has been detected by
the activation state machine of the transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. The low–to–high level transition of the EI bit corresponds to the EI1 error indication
reporting, while the high–to–low level transition of the EI bit corresponds to the EI2 error indication
reporting recovery. Note that NR1(2) is a read only bit.
3–2
MC145574
MOTOROLA
3.10 DEACTIVATION PROCEDURES
CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications dictate that only an NT can deactivate
the S/T loop. Intuitively, this has to be the case because in a passive bus if one TE sends INFO 0,
seeking to deactivate the loop, the other TE’s INFO 3 simply overrides it.
An NT transmits INFO 0 to the TE(s) when it wishes to deactivate the S/T loop. This is done by setting
NR2(2) (Deactivation Request) to a 1. Note that this bit is internally reset to 0 after the internal activation
state machine has recognized its active transition.
3.11 INITIAL STATE OF B1 AND B2 CHANNELS
3.11.1 NT
When the MC145574 is configured as an NT, NR5(3:2) corresponds to “IDLE B1 channel on S/T loop”,
and “IDLE B2 channel on S/T loop”, respectively. The device comes out of a hardware or software
reset with these two bits reset to 0. Thus, the NT comes out of reset with the B1 and B2 channels
enabled. When the NT is transmitting INFO 4, data on the B1 and B2 IDL2 timeslots will be modulated
onto the S/T loop. Setting either of these nibble bits in the NT mode will idle the corresponding B
channel on the S/T loop. Note that putting a B channel in the idle mode affects only the transmitted
B channel. The demodulated B data is still transmitted out on IDL2 Tx, in accordance with the IDL2
specification.
3.11.2 TE
When the MC145574 is configured as a TE, NR5(3:2) corresponds to “ENABLE B1 channel on S/T
loop,” and “ENABLE B2 channel on S/T loop,” respectively. The device comes out of a hardware or
software reset with these two bits reset to 0. Thus, the TE comes out of reset with the B1 and B2
channels disabled. When the TE is transmitting INFO 3, data on the B1 and B2 IDL2 timeslots is not
modulated onto the S/T loop. Setting either of these bits enables the modulation of the corresponding
B channel onto the S/T loop.
Note that although the TE comes out of reset with both B channels in the idle mode, this only affects
the modulation path. Demodulated data is still transmitted on D
.
out
3.12 ADDITIONAL NOTES
3.12.1 M and N Parameters
For conformance qualification procedures, it is often necessary to state the values of M and N, where:
M is the number of successive good S0 frames for frame synchronization, and
N is the number of successive bad S0 frames for frame loss.
For the MC145574, M = 5 and N = 3.
3.12.2 Echo Channel
The NT demodulates the 2B+D data received from the TE(s). In addition to passing this data onto
the network, the NT echoes the D channel data back to the TE(s) using the echo channel. This echo
channel is monitored by the TEs and used in the D channel contention algorithm. For a detailed descrip-
tion, refer to Section 11.
MOTOROLA
MC145574
3–3
3.12.3
A Bit
An S/T frame consists of 48 bauds. In the NT to TE direction, one of these bauds is for the A bit.
The A bit is set to 1 when the S/T loop is in the fully activated state and is set to 0 at all other times.
Thus, when the NT is transmitting INFO 2, the A bit is set to 0. When the NT is transmitting INFO 4,
the A bit is set to 1.
3.12.4 SCP Nomenclature
There are seven nibble registers, 16 byte registers, and 10 overlay registers in the MC145574. These
registers are accessed by means of the SCP. NR1(2) refers to nibble register 1, bit 2. Likewise, BR3(4)
refers to byte register 3, bit 4, and OR5(6) refers to overlay register 5, bit 6.
The overlay registers are a second bank of registers available when the overlay register control bit
BR15(7) is set to logic 1.
3.12.5 SCP Indication of Transmit and Receive States
Note that there are two SCP bits, BR11(5:4), used to signify what INFO state the MC145574 is receiv-
ing. In addition to this, BR11(3:2) are used to signify what INFO state the MC145574 is transmitting.
Refer to Tables 9–2 and 9–3 for a detailed description of these bits.
3–4
MC145574
MOTOROLA
4
THE INTERCHIP DIGITAL LINK
4.1 INTRODUCTION
The Interchip Digital Link (IDL2) of the MC145574 is backwards compatible with the IDL of the
MC145474/75 S/T transceiver of first generation. In addition to the standard operating mode, this en-
hanced interface features new modes that are programmable through the SCP.
The IDL2 is a four–wire interface used for full–duplex communication between ICs on the board level.
The interface consists of a transmit path, a receive path, an associated clock, and a sync signal. These
signals are known as D , D , DCL, andFSC, respectively. Theclockdeterminestherateofexchange
out in
of data in both the transmit and receive directions, and the sync signal controls when this exchange
is to take place. Three channels of data are exchanged every 8 kHz. These channels consist of two
64 kbps B channels and one 16 kbps D channel used for full–duplex communication between the
NT and TE.
There are two modes of operation for an IDL2 device: IDL2 master and IDL2 slave. If an IDL2 device
is configured as an IDL2 master, then FSC and DCL are outputs from the device. Conversely, if an
IDL2 device is configured as an IDL2 slave, then FSC and DCL are inputs to the device. Ordinarily
the MC145574 should be configured as an IDL2 slave when acting as an NT, and as an IDL2 master
when acting as a TE. The exception to this rule is the option to configure the NT as an IDL2 master.
The TE configured MC145574 also features the new option of operating in the IDL2 slave mode. These
operation modes are described in Section 4.3.
4.2 SIGNAL DESCRIPTION
There are six pins associated with the IDL2 interface.
FSC/FSR
This pin is normally FSC and is an input/output pin to which all serial interface events are synchronized.
This pin is periodic at 8 kHz. In the master mode, the pin is an output and is either derived from the
S/T frame or from the XTAL. In the slave mode, this pin is an input.
FSC can be reconfigured through the SCP to be FSR. In this mode, the IDL2 operates with two indepen-
dent frame syncs, one for the Tx direction (FST) and one for the Rx direction (FSR). FSR is bidirectional,
the direction depending on whether the IDL2 is a master or a slave. See Register OR7 description.
DCL
This is an input/output pin that provides the clock to the serial interface. In the master mode, this pin
is an output. In the slave mode, this pin is an input. The clock is continuous and the edges are synchro-
nous with the frame sync.
When DCL is an output, the clock rate can be programmed through the SCP to be 2.56 MHz,
2.048 MHz, 1.536 MHz, or 512 kHz. When DCL is an input, the clock rate can be between 512 kHz
and 4096 kHz (DCL should be a multiple of FSC.) Selection of the clock frequency is accomplished
in the same manner as used in MC145474, through the bits BR7(2) and BR13(5). See Table 4–1
for IDL2 clock speeds.
MOTOROLA
MC145574
4–1
Table 4–1. IDL2 Clock Speeds
BR13(5)
BR7(2)
DCL
0
0
1
1
0
1
0
1
2.56 MHz
2.048 MHz
1.536 MHz
512 kHz
D
in
This pin is always an input. Data to be output on the S/T–interface is input on this pin.
D
out
This pin is a three–state output. Data received on the S/T–interface is output on this pin during pro-
grammed timeslots and is high impedance at all other times.
TSEN/FST
This pin is normally three–state, but it can be reconfigured through the SCP to be used as TSEN
or FST. See Register OR7 description.
TSEN is an open drain output. TSEN can be used to enable an external bus driver and pulses low
when data is being output on the D
driver in applications where the D
wire–OR’d with other devices and share the same driver.
pin. This signal can be used to control a high drive bus/backplane
data is going off–board. Since TSEN is open drain, it can be
out
out
This pin can also be reconfigured through the SCP to be used as FST. In this mode, the IDL2 interface
operates with two independent frame syncs, one for the Tx direction (FST) and one for the Rx direction
(FSR). FST is bidirectional, the direction depending on whether the IDL2 is a master or a slave.
TFSC/TCLK/T_IN/FIX
This pin is the FIX input in NT modes, but in the TE slave mode it is reconfigured to be used as TFSC
and outputs an 8 kHz signal that is synchronized to the incoming S/T–interface frames. The TFSC
can be used in NT2 applications where the TE slave mode is utilized. The TFSC can be used to synchro-
nize the TE slaves to the network. Alternatively, this pin can output TCLK, selected via the SCP. TCLK
is a clock whose frequency can be chosen via the SCP, which is also synchronized to the received
S/T–interface. TCLK can be used as an alternative to TFSC in the NT2 slave–slave mode. Refer to
the slave–slave mode section for further details on TFSC and TCLK. See Register OR7 description.
In the NT Terminal mode (NTTERM), this pin is T_IN. See the section on NT Terminal mode. See
description for Register OR8.
4.3 IDL2 STANDARD MODE
4.3.1
NT IDL2 Slave
This is the normal mode of operation for the MC145574, when active as an NT. In this mode FSC
and DCL are inputs to the device, and the outgoing S/T frame is synchronized to the IDL2 frame sync.
Typically the MC145574, when configured as an NT, is situated on a line card or an NT1 box. As
an IDL2 slave, this allows the S/T chip to derive its timing from the backplane or from the
MC14LC5472/MC145572 U–chips. As mentioned previously, FSC must be 8 kHz, while DCL can be
input to the device with any frequency from 512 kHz to 4.096 MHz.
When the MC145574 is configured as an NT, then BR7(3) determines whether the NT is acting as
an IDL2 master or as an IDL2 slave. When BR7(3) is a 0, the MC145574, when acting as an NT,
is behaving as an IDL2 slave. Conversely, when BR7(3) or OR8(3) is set to a 1, or when pulling high
the M/S pin, the chip acting as an NT behaves as an IDL2 timing master.
4–2
MC145574
MOTOROLA
4.3.2
NT IDL2 Master
As mentioned previously, the normal configuration for the MC145574, when configured as an NT, is
as an IDL2 slave. However, in order to facilitate testing of the environment in which the MC145574
resides, the capability exists to configure the chip as an NT IDL2 master. In this mode of operation,
the chip outputs FSC and DCL. These signals are divided down from the 15.36 MHz crystal input
XTALIN and hence are synchronous with it. The NT IDL2 master mode also finds use in testing PC–
based local area networks or in passive bus configurations. In these environments, it may be required
to configure one of the TEs to act as an NT. The NT IDL2 master enables the user to do this. Writing
a 1 to BR7(3) or OR8(3), or pulling high the M/S pin, puts the NT into the IDL2 master mode. Note
that a software or a hardware reset reconfigures the NT as an IDL2 slave.
When the MC145574 is acting as an NT IDL2 master, the DCL can be programmed to output one
of four frequencies. The DCL rate is determined by BR7(2) and BR13(5). In the NT IDL2 master mode,
the DCL is obtained by dividing down from the 15.36 MHz crystal. Application of a software or a hard-
ware reset will reset BR7(2) and BR13(5) to 0. Note that these bits have no application when the
MC145574 is an NT IDL2 slave.
4.3.3
TE IDL2 Master
This is the normal mode of operation for the MC145574 when active as an NT. In this mode, the
MC145574 derives its timing from the inbound data from the NT. When the TE is receiving either INFO 2
or INFO 4 from the NT, it adaptively phase–locks onto it. The TE sets the FSYNC bit (NR1(0)) high
when this frame synchronization has been achieved. When this occurs, the TE outputs FSC, DCL,
and D
synchronous with the inbound INFO 2 or INFO 4. If the TE is receiving INFO 2, it outputs
“idle 1s” on D in the B1, B2, and D channel timeslots. If the TE is receiving INFO 4, it outputs valid
out
out
data in these timeslots.
Note that when the TE has reached its fully active state, it internally sets the activate indication bit
(NR1(3)). (The active state for a TE is when it is receiving INFO 4 from the NT, has phase–locked
onto it, and is transmitting back INFO 3 to the NT.) In the TE IDL2 master mode, BR7(2) and BR7(3)
determine the output DCL rate. See description of BR7 bits 1 and 2 in Section 9.9.
4.3.4
TE IDL2 Master Free Run
The capability exists in the MC145574 to configure the chip as a TE operating in the IDL2 master
free run mode. This is done by setting BR7(3) to a 1. In this mode, the TE sends out a DCL and FSC
regardless of the state of the frame synchronization bit (NR1(0)). If NR1(0) is low, then FSC and DCL
are derived from the crystal in the same way as in the NT IDL2 master mode. Upon achieving frame
synchronization (i.e., the TE is receiving either INFO 2 or INFO 4 from the NT, has phase–locked
onto it, and has set NR1(0)), FSC and DCL will become synchronous to the inbound INFO 2 or
INFO 4 from the NT. The TE IDL2 master mode has the capability of providing four clock rates:
2.56 MHz, 2.048 MHz, 1.536 MHz, and 512 kHz.
4.3.5
TE IDL2 Slave
The TE slave–slave mode should be selected when the device is to be used on the T–interface of
an NT2. In this mode, the IDL2 is in the slave mode, and D channel data is continuously transmitted/re-
ceived to/from the T–interface. The D channel access algorithm is disabled in this mode.
In this mode, the frame sync and serial clock are inputs. The IDL2 circuitry incorporates buffering
to accommodate any phase relationship between the frame sync and the received S/T frame. The
buffering is able to absorb low–frequency wander between the IDL2 frame sync and the S/T frame.
The wander absorption capability exceeds the requirement of Q.502, which defines wander as 18 µs
peak–to–peak at frequencies below 10 Hz over a 24–hour period.
MOTOROLA
MC145574
4–3
4.3.6
Additional Notes
4.3.6.1
Phase Relationship of the NT Transmit Signal with Respect to FSC/FSR
The MC145574 operating as an NT behaves as an IDL2 slave, FSC/FSR and DCL being inputs to
the device. FSC/FSR is a single positive polarity pulse, one DCL cycle in duration, and is periodic
at an 8 kHz rate. The MC145574 operating as an NT uses FSC/FSR to correctly position its outbound
waveform. Thus, the FSC/FSR input to the NT and the NT’s outbound INFO 2 or INFO 4 are synchro-
nous. The phase relationship of these signals is shown in Figure 4–1 with a “close–up shot” included.
4.3.6.2
Phase Relationship of the TE Transmit Signal with Respect to FSC/FSR, When in
the IDL2 Master Mode
The MC145574 operating as a TE behaves as an IDL2 master; FSC/FSR and DCL are outputs from
the device. The TE derives its timing from the inbound INFO 2 or INFO 4 from the NT. There is a
two–baud turnaround in the TE in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605
specifications; i.e., the time between the TE’s received “F bit” and its transmitted “F bit” is equivalent
to two bauds. This is indicated in Figure 4–2. The TE outputs FSC/FSR, DCL, and D
achieved frame synchronization. The phase relationship of the TE’s transmitted INFO 3 and FSC/FSR
is as shown in Figure 4–3 with a “close–up shot” included.
when it has
out
4.3.6.3
Operation of Multiple MC145574s in TE Slave Mode
When the MC145574 is configured for TE slave mode in NT2 applications, the T_IN/TFSC/TCLK/FIX
pin defaults to the TFSC function. As TFSC, this pin outputs an 8 kHz frame sync that is synchronized
to recovered timing from the network.
In TE slave mode, the T_IN/TFSC/TCLK/FIX pin function can be changed to TCLK, which outputs
a network synchronized high frequency clock. This is done by setting OR7(5) to a 1. The clock frequen-
cy of TCLK is selected in the same manner as programming the DCL clock in IDL2 master mode.
Elasticbuffers are included in TE slave mode to allow the MC145574 to operate with any phase relation-
ship between the IDL2 frame sync and the network. This buffer also allows the frame sync to wander
with respect to the network, up to 60 µs peak–to–peak. This exceeds the requirements of Q.502, which
states that wander up to 18 µs peak–to–peak may arise over a 24–hour period.
An example architecture of an NT2 is shown in Figure 4–4. The TFSC or TCLK signal supplied by
the TE is used to synchronize the entire NT2 to the network. The TFSC/TCLK pins can be wire OR’d
together and connected to V
via a pull–up resistor. Each TE looks at the TFSC/TCLK pin during
DD
its programmed B1 channel timeslot. If there is no signal present and the TE is activated, it outputs
a synchronized signal on TFSC/TCLK. It is important for all TEs to have their B and D channels config-
ured using the timeslot assigner, and no two devices can share a timeslot.
4.3.6.4
Independent Tx/Rx Frame Syncs
Via the SCP, two pins (FST and FSR) are available to handle the transmit and receive frames indepen-
dently on the IDL2 interface. These pins must operate synchronously with the DCL clock. Operation
of FST and FSR is dependent on the master or slave mode. Separate frame syncs are enabled by
setting OR7(4) to a 1.
In the slave mode, FST and FSR may assume any relationship with respect to each other.
In the master mode, both FST and FSR are operational and locked together in time. Long frame format
can not be used with independent Tx/Rx frame syncs.
4.3.6.5
Timeslot Assignment
The MC145574 contains a timeslot assigner. The timeslot immediately following the FSC/FSR/FST
signal is timeslot zero. Timeslots are available up to the maximum DCL rate of 4096 kHz. The timeslots
are programmed through a group of control registers in the overlay register map. Up to 256 start times
may be defined, corresponding to each 2–bit boundary defined by DCL.
4–4
MC145574
MOTOROLA
FSC/FSR
125 µs
B1
B2
B1
B2
F
L
2
E
D A F
N
E
D M
E
D S
E D L F L
A
NT TRANSMIT
(INFO 4)
1
3 4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2
250 µs
FSC/FSR
DCL
B1
32
B1
33
B1
34
E
NT TRANSMIT
(INFO 4)
35
B1
B2
B1
B2
F
L
E
D A F
N
E
D M
E
D S
E D L F L
A
TE RECEIVED
SIGNAL
(INFO 4)
B1
B2
B1
B2
D L
F
L
L
D L F
L
L
D L
L D L
L D L F L
A
TE TRANSMITTED
SIGNAL
(INFO 3)
2 BAUD TURNAROUND –10.4 µs
FSC/FSR
125 µs
B1
B2
B1
B2
F
L
2
L D L F
L
L D L
L
D L
L D L F L
A
TE TRANSMIT
(INFO 3)
1
3 4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 2
250 µs
FSC/FSR
DCL
B1
32
B1
33
B1
34
L
TE TRANSMIT
(INFO 3)
35
NT
NT
NT
TE
TE
TE
TFSC
CLK
FSC SOURCE
SELECTOR
CLK
S
S
S
T
T
T
SYNC
SYNC
DATA
SYNC AND CLOCK
GENERATOR
DATA
TSA CONTROLLER
TFSC
CLK
CLK
SYNC
DATA
SYNC
DATA
CONTROL
BUS
TFSC
CLK
CLK
SYNC
CLK
FRAME SYNC
SYNC
DATA
DATA
NT
TFSC TE
CLK
CLK
S
T
SYNC
DATA
SYNC
DATA
SUBSCRIBER
LINES
S–INTERFACE
TRUNK LINES
TO CENTRAL OFFICE(S)
T–INTERFACE
Figure 4–4. Example Architecture of an NT2
Independent timeslot assignment is available for the B1, B2, and D channels in both the transmit and
receive directions. B1, B2, and D timeslots may be enabled separately. When a timeslot is enabled,
the IDL2 automatically enters timeslot mode. If any one channel’s timeslot is not enabled, data trans-
mitted by the framer for that channel will be filled with all ones, and the channel will not be present
on D
.
out
With a DCL rate of 4096 kHz, it is possible to allocate 1 of 256 possible timeslots to each data channel.
It is important that the software selects a timeslot consistent with the DCL rate. When a clock rate
of 2048 kHz is being used, only 128 timeslots are available. If a timeslot out with the available range
is chosen, then no data transfer occurs for that timeslot.
The default values assigned to the B1, B2, and D channels are 00H, 04H, and 08H. These values
provide an IDL2 8–bit output format as default.
The IDL2 10–bit mode is not available when the timeslot assigner has been enabled.
CAUTION
Do not program overlapping timeslots even if a timeslot has not been enabled. The transmit
and receive timeslot for a given B1, B2, or D channel can be the same.
4.3.6.6
Short and Long Framing
In master timing mode, the default state is to supply a one–clock–wide FSC/FSR/FST frame sync.
However, an option is provided to change this to long frame. The length of the long frame pulse is
always 8–bit clocks, regardless of whether an 8– or 10–bit format is selected. In the slave mode, the
MC145574 will automatically adjust to whichever framing method is supplied. If the frame sync is two
or more clocks wide, the MC145574 assumes a long frame format.
A long frame format cannot be used in timeslot assignment mode.
4–8
MC145574
MOTOROLA
4.3.6.7
TSEN Signal
The TSEN signal is enabled via the SCP. See description for OR7 bits 1 and 0. This pin then becomes
an open drain output that pulls low when data is being output from D . This signal can then be used
out
to enable an external driver in applications where the IDL2 data goes off–board, such as PBXs, channel
banks, etc.
4.3.6.8
Miscellaneous
Clock Options
In the slave mode, the IDL2 interface accepts any clock from 512 kHz to 4096 kHz in 8 kHz increments.
In the master mode, the DCL has four frequency options, programmable through the SCP. The clock
rate can be either 2.56 MHz, 2.048 MHz, 1.536 MHz, or 512 kHz. The default selection is 2.56 MHz.
B Channel Exchange
An option is provided to exchange the B1 and B2 channels inside the IDL2. This exchange operates
simultaneously in both Tx and Rx directions.
B1 and B2 Blocking
Options are provided to independently block or force the B1 and B2 channels to all ones in both the
transmit and receive directions.
B1 and B2 Inversion
Options are provided to independently invert the B1 and B2 channels in both the transmit and receive
directions.
B1, B2, and D Loopbacks
Options are provided to make an individual loopback on each B1, B2, or D channel.
4.3.6.9
IDL2 Waveform Diagrams
The relative timing relationships of the IDL2 signals are shown in Figures 4–5 through 4–8.
MOTOROLA
MC145574
4–9
FSC/FSR
DCL
B1 B1 B1 B1 B1 B1 B1 B1
D
D
B2 B2 B2 B2 B2 B2 B2 B2
D
D
D
in
D
out
B1 B1 B1 B1 B1 B1 B1 B1
B2 B2 B2 B2 B2 B2 B2 B2
Figure 4–5. Standard IDL2 10–Bit Mode
FSC/FSR
DCL
D
in
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2
D
D
D
D
D
out
Figure 4–6. Standard IDL2 8–Bit Mode with Long Frame Sync
FSC/FSR
DCL
D
in
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2
D
D
FST
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2
D
D
D
out
Figure 4–7. Standard IDL2 8–Bit Slave Mode with Independent Frame Syncs
4–10
MC145574
MOTOROLA
Figure 4–8. Timeslot Operation with Independent Slave Frame Syncs, TSEN
MOTOROLA
MC145574
4–11
4–12
MC145574
MOTOROLA
5
SERIAL CONTROL PORT
5.1 INTRODUCTION
The MC145574 is equipped with a serial control port (SCP). This SCP is used by external devices
(such as an MC145488 DDLC or 68302) to communicate with the S/T transceiver. The SCP is an
industry standard serial control port and is compatible with Motorola’s SPI, which is used on several
single–chip MCUs.
The SCP is a five–wire bus with control and status bits, with data being passed to and from the S/T
transceiver in a full–duplex fashion.
The SCP interface consists of a transmit path, a receive path, an associated clock, an enable signal,
and an interrupt indicate. These signals are known as SCP Tx, SCP Rx, SCPCLK, SCPEN, and IRQ.
The clock determines the rate of exchange of data in both the transmit and receive directions, the
enable signal governs when this exchange is to take place, and the interrupt signal indicates that
an interrupt condition exists and a read operation of the interrupt status register (NR3) is required.
The operation/configuration of the S/T transceiver is programmed by setting the state of the control
bits within the S/T transceiver. The control, status, and data information reside in eight 4–bit–wide
nibble registers, sixteen 8–bit–wide byte registers, and sixteen 8–bit–wide overlay registers. The nibble
registers are accessed via an 8–bit SCP bus transaction. The 16–byte–wide registers are accessed
by first writing to a pointer register within the eight 4–bit–wide nibble registers. This pointer register
(NR(7)) then contains the address of the byte wide register to be read from or written to on the following
SCP transaction. Thus, an SCP byte access is in essence a 16–bit operation. Note that this 16–bit
operation can take place by means of two 8–bit accesses or a single 16–bit access.
5.2 SCP TRANSACTIONS
There are six types of SCP transactions.
1. SCP Nibble Register Read
2. SCP Nibble Register Write
3. SCP Byte Register Read
4. SCP Byte Register Write
5. SCP Merged Read
6. SCP Merged Write
The following sections contain a discussion on each type of SCP transaction.
5.2.1 SCP Nibble Register Read
A nibble register read is an 8–bit SCP transaction. Figure 5–1 illustrates this process. To initiate an
SCP nibble register read, the SCPEN pin is brought low. Following this, a read/write (R/W) bit, followed
by three primary address bits (A0 – A2 = 0 to 6), are shifted (MSB first) into an intermediate buffer
register on the first four rising edges of SCPCLK, following the high–to–low transition of SCPEN. If
a read operation is to be performed, then R/W should be a 1. The three address bits clocked in after
the R/W bit select which nibble register is to be read. The contents of this nibble register are shifted
out on SCP Tx on the subsequent four falling edges of SCPCLK; i.e., the four falling edges of SCPCLK
after the rising edge of SCPCLK, which clocked in the last address bit (LSB). SCPEN should be brought
MOTOROLA
MC145574
5–1
back high after the transaction, before another rising edge of SCPCLK is encountered. Note that
SCP Rx is ignored during the time that SCP Tx is being driven. Also note that SCP Tx comes out
of high impedance only when it is transmitting data.
SCPEN
DON’T CARE
DON’T CARE
SCPCLK
SCP Rx
SCP Tx
R/W A2 A1 A0
D3 D2 D1 D0
HIGH IMPEDANCE
Figure 5–1. Serial Control Port Nibble Register Read Operation
5.2.2 SCP Nibble Register Write
A nibble register write is an 8–bit SCP transaction. Figure 5–2 illustrates this process. To initiate an
SCP nibble register write, the SCPEN pin must be brought low. Following this, an R/W bit followed
by three primary address bits are shifted (MSB first) into an intermediate buffer register on the first
four rising edges of SCPCLK following the high–to–low transition of SCPEN. If a write operation is
to be performed, then R/W should be a 0. The three address bits, clocked in after the R/W bit, select
the nibble register to be written to. The data shifted in on the next four rising edges of SCPCLK is
then written to the selected register. Throughout this whole operation the SCP Tx pin remains in high–
impedance state. Note that if a selected register or bit in a selected register is “read only”, then a
write operation has no effect.
SCPEN
SCPCLK
SCP Rx
R/W A2 A1 A0 D3 D2 D1 D0
DON’T CARE
DON’T CARE
SCP Tx
HIGH IMPEDANCE
NOTES:
1. R/W = 0 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
4. A2, A1, A0 = 0 to 6.
Figure 5–2. Serial Control Port Nibble Register Write Operation
5–2
MC145574
MOTOROLA
5.2.3
SCP Byte Register Read
A byte register read is a 16–bit SCP transaction. Figure 5–3 illustrates this process. To initiate an
SCP byte register read, the SCPEN is brought low. Following this, an R/W bit is shifted in from SCP
Rx on the next rising edge of SCPCLK. This bit determines the operation to be performed; read or
write.
SCPEN
SCPCLK
DON’T CARE
DON’T CARE
SCP Rx
R/W
A3 A2 A1 A0
HIGH
IMPEDANCE
SCP Tx
D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
NOTES:
1. R/W = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
Figure 5–3. Serial Control Port Byte Register Read Operation
If R/W is a 1, then a read operation is selected. Conversely, if R/W is a 0, then a write operation is
selected. The next three bits shifted in from SCP Rx on the three subsequent rising edges of
SCPCLK are primary address bits (A0 – A2 = 7), as mentioned previously. With all three bits equal
to 1, nibble register 7 (NR7) is selected. This is a pointer register, the selection of which informs the
device that a byte operation is to be performed. When NR7 is selected, the following four bits shifted
in from SCP Rx on the following four rising edges of SCPCLK are automatically written to NR7. These
four bits are the address bits for the byte operation. In a read operation, the next eight falling edges
of SCPCLK shift out the data from the selected byte register on SCP Tx.
As mentioned previously, an SCP byte access is a 16–bit transaction. This can take place in one 16–bit
exchange or two 8–bit exchanges. If the transaction is performed in two 8–bit exchanges, the SCPEN
should be returned high after the first eight bits have been shifted into the part.
When SCPEN comes low again, the MSB of the selected byte presents itself on SCP Tx. The following
seven falling edges of SCPCLK shift out the remaining seven bits of the byte register. Note that the
order in which data is written into the part and read out of the part is independent of whether the byte
access is done in one 16–bit exchange or in two 8–bit exchanges. Figure 5–4 illustrates this process.
MOTOROLA
MC145574
5–3
SCPEN
SCPCLK
DON’T CARE
DON’T CARE
SCP Rx
SCP Tx
R/W
A3 A2 A1 A0
HIGH
IMPEDANCE
HIGH IMPEDANCE
D7 D6 D5 D4 D3 D2 D1 D0
Figure 5–4. Serial Control Port Byte Register Read Operation Double 8–Bit Transaction
5.2.4 SCP Byte Register Write
A byte register write is also a 16–bit SCP transaction. Figure 5–5 illustrates this process. To initiate
an SCP byte register write, the SCPEN must be brought low. As before, the next bit determines whether
the operation is to be read or write. If the first bit is a 0, then a write operation is selected. Again the
next three bits read in from SCP Rx on the subsequent three rising edges of SCPCLK must all be
1 in order to select the pointer nibble register (NR7). The following four bits shifted in are automatically
written into NR7. As in an SCP byte register read, these bits are the address bits for the selected
byte register operation. The next eight rising edges of SCPCLK shift in the data from the SCP Rx.
This data is then stored in the selected byte register. Throughout this operation SCP Tx is in a high–im-
pedance state. Note that if the selected byte is “read only”, then this operation has no effect.
SCPEN
SCPCLK
SCP Rx DON’T CARE
DON’T CARE
R/W
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
SCP Tx
NOTES:
1. R/W = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
Figure 5–5. Serial Control Port Byte Register Write Operation
As mentioned previously, an SCP byte access is a 16–bit transaction. This can take place in one 16–bit
exchange or two 8–bit exchanges. If the transaction is performed in two 8–bit exchanges, then SCPEN
should be returned high after the first eight bits have been shifted into the part.
5–4
MC145574
MOTOROLA
When SCPEN comes low again, the next eight rising edges of SCPCLK shift data in from
SCP Rx. This data is then stored in the selected byte. Figure 5–6 illustrates this process.
SCPEN
SCPCLK
DON’T CARE
DON’T CARE
DON’T CARE
SCP Rx
SCP Tx
R/W
A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
HIGH IMPEDANCE
Figure 5–6. Serial Control Byte Register Write Operation Double 8–Bit Transaction
5.2.5 SCP Merged Read/Write
Merged operations are accomplished by not taking SCPEN high between separate SCP instructions.
The SCP bytes/nibbles are strung together in a continuous bit stream and can be a mux or read/write
command. The device is able to extract the separate instructions and provide the appropriate response.
The SCPEN signal goes low at the start of the bit stream and goes high again at the end.
Figure 5–7 illustrates this process with two consecutive nibble register read operations. The merged
instructions can be a free mix of nibble/byte/read/write operations.
SCPEN
SCPCLK
SCP Rx
R/W A2 A1 A0
HIGH IMPEDANCE
R/W A2 A1
A0
DON’T CARE
DON’T CARE
DON’T CARE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SCP Tx
D3 D2 D1 D0
D3 D2 D1 D0
NOTES:
1. R/W = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
Figure 5–7. Merged Serial Control Port Nibble Register Read Operation
MOTOROLA
MC145574
5–5
5.3 SIGNAL DESCRIPTION
There are five signals which constitute the SCP bus.
1. SCP Tx
2. SCP Rx
3. SCPCLK
4. SCPEN
5. IRQ
A description of each signal follows.
5.3.1
SCP Tx
SCP Tx is used to output control, status, and data information from the MC145574 S/T transceiver.
The data is output in either 4–bit nibble or 8–bit byte groupings. The data is output in 4–bit nibble
groupings during a nibble register read and in 8–bit byte groupings during a byte register read. Data
is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
In a nibble register read transaction, the fourth rising edge of SCPCLK after SCPEN goes low shifts
the LSB of the 3–bit nibble address into the MC145574. The following falling edge of SCPCLK shifts
out the first bit of the selected nibble register (MSB) and takes SCP Tx out of the high–impedance
state. The next three falling edges of SCPCLK shift out the other three bits of the selected nibble
register. When the last bit (LSB) has been shifted out, SCPEN should be returned high. This action
returns SCP Tx to a high–impedance state.
In a byte register read transaction, the eighth rising edge of SCPCLK after SCPEN goes low shifts
in the LSB of the 4–bit byte address. The following falling edge of SCPCLK (provided SCPEN is still
low) shifts out the first bit (MSB) of the selected byte register and takes SCP Tx out of high impedance.
The next seven falling edges of SCPCLK shift out the remaining seven bits of the selected byte register.
When the last bit (LSB) has been shifted out, SCPEN should be returned high. This action returns
SCP Tx to a high–impedance state.
5.3.2
SCP Rx
SCP Rx is used to input control, status, and data information to the S/T transceiver. Data is shifted
into the device on rising edges of SCPCLK. The format for the input of data is as follows: the first
bit is the R/W bit (1 = read, 0 = write). This bit selects the operation to be performed on the selected
registers within the MC145574 S/T transceiver. The next three bits address one of eight specific nibble
registers within the MC145574 S/T transceiver on which the read or write operation is to be performed.
The address bits are shifted in MSB first. The last four bits are either the data bits (MSB first) that
are to be written to the S/T transceiver nibble register (NR0 through NR6), or are four additional address
bits (if NR7 had been addressed). These address bits select one of the 16–byte–wide registers (which
are accessed during the next eight cycles of the SCPCLK or a second 8–bit access). SCP Rx is ignored
when data is being shifted out on SCP Tx, or when SCPEN is high.
5.3.3
SCPCLK
This is an input to the device used for controlling the rate of transfer of data into and out of the SCP.
Data is shifted into the part from SCP Rx on rising edges of SCPCLK. Data is shifted out of the part
on SCP Tx on falling edges of SCPCLK. SCPCLK can be any frequency up to 4.096 MHz.
An SCP transaction takes place when SCPEN is brought low. Note that SCPCLK is ignored when
SCPEN is high; i.e., it may be continuous or it can operate in the burst mode.
5–6
MC145574
MOTOROLA
5.3.4
SCPEN
This signal, when held low, selects the SCP for the transfer of control, status, and data information
into and out of the MC145574 S/T transceiver. SCPEN should be held low for 8 or 16 periods of the
SCPCLK signal, in order for information to be transferred into or out of the MC145574 S/T transceiver.
The phase relationship of SCPEN, with respect to SCPCLK, is as shown in Figures 5–1 through 5–6
inclusive.
The transition of SCPEN going high will abort any SCP operation in progress, and will force the SCP Tx
pin into the high–impedance state.
5.3.5
IRQ
IRQ is an open drain output to the device used for indicating that an interrupt condition exists. This
pin is normally pulled high by an external resistor. When this pin goes low, it indicates a read operation
of the interrupt status register (NR3) is required.
5.4 SCP HIGH-IMPEDANCE DIGITAL OUTPUT MODE (SCP HIDOM)
The MC145574 S/T transceiver has the capability of forcing all output pins of the MC145574 (both
analog and digital) to the high–impedance state. This feature, known as the “Serial Control Port High–
Impedance Digital Output Mode”, or SCP HIDOM, is provided to allow “in circuit” testing of other circuits
or devices resident on the same PCB, without requiring the removal of the MC145574.
The SCP HIDOM mode is entered by holding SCPEN low for a minimum of 33 consecutive rising
edges of SCPCLK while SCP Rx is high. After entering this mode, if SCPEN goes high or if SCP Rx
goes low, the device will exit the SCP HIDOM mode and return to normal operation.
5.5 ADDITIONAL NOTES
5.5.1 SCP Independent of Crystal
The MC145574 S/T transceiver operates with a 15.36 MHz crystal frequency. Details of the crystal
circuit can be found in Section 7. The SCP operates independently of the 15.36 MHz crystal; i.e.,
the SCP can be accessed in the presence or absence of the 15.36 MHz input.
5.5.2 SCP Slave
The SCP in the MC145574 always operates in the SCP slave mode. The SCP slave mode is defined
as having SCPCLK and SCPEN as inputs to the device. Thus, any device which communicates with
the MC145574 via the SCP must be able to operate in the SCP master mode where SCPCLK and
SCPEN are outputs. Note that the MC145488 dual data link controller (DDLC) and 68302 operate
in the SCP master mode.
MOTOROLA
MC145574
5–7
5–8
MC145574
MOTOROLA
6
GENERAL CIRCUIT INTERFACE
6.1 OVERVIEW
The MC145574 is able to work with a General Circuit Interface port (GCI). The GCI is a standard
four–wire interface between devices for the subscriber access in ISDN and analog environments. The
principle use in these applications is to control the subscriber line interface circuitry.
The following are some of the benefits of the General Circuit Interface.
• Operation and Maintenance Features
• Activation and Deactivation Facilities (via a Control Indication (C/I) Channel)
• Well–Defined Transmission Protocols to Ensure Correct Information Transfer Between GCI Com-
patible Devices
• Point–to–Point and Multipoint Communication Links
• Multiplexed Mode of Operation Where up to Eight GCI Channels can be Combined to Form a
Single Data Stream
The GCI interface consists of a transmit path, a receive path, an associated clock, and a frame sync
signal. These signals are known as D , D , DCL, and FSC.
out in
The clock determines the rate of exchange of data in both the transmit and receive directions. The
frame sync signal indicates when this exchange will start.
6.2 GCI FRAME STRUCTURE
In a GCI channel, information is in a 4–byte time–division based structure with a repetition rate of
8 kHz. The four bytes are B1 and B2 channels, a monitor (M) channel, and a C/I channel.
The two independent B channels are used to carry subscriber voice and data information. The M chan-
nel is used for operation and maintenance facilities. The C/I channel is further subdivided into two
bits for the D channel information, four bits for the control/indication (C/I) channel, and two bits for
the A and E channels that are used to control the transfer of information on the Monitor channel.
Figure 6–1 shows the relative positions of these channels.
6.3
ENABLING THE GCI MODES
GCI modes can be enabled via two different methods, depending on the application requirements.
1. The GCI mode can be enabled through the GCI control register present in the SCP. This is called
indirect mode. See descriptions for OR6(2) and OR5.
2. Alternatively, if the SCP port is not required or available, then the GCI mode can be enabled at
hardware reset. This is called direct mode. This is done by connecting SCPEN/GCIEN to V
during reset.
SS
MOTOROLA
MC145574
6–1
125 µs
BASIC GCI CHANNEL
DCL = 512 kHz
FSC
DCL
FSC = 8 kHz
D
/D = 256 kbps
out in
B1 B1 B1 B1 B1 B1 B1 B1
B1 B1 B1 B1 B1 B1 B1 B1
B2
M
M
D D
C/I
C/I
A E
A E
D
out
B2
D D
D
in
IF S(2:0) = 3
FSC
DCL
D
D
out
in
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
125 µs
8 CHANNEL GCI MULTIPLEX
DCL = 4096 kHz /D = 256 kbps/CH
D
FigurFeSC6=–81k.Hz
out in
Figure 6–1a. Relative Channel Positions (GCI Slave Mode)
6–2
MC145574
MOTOROLA
125 µs
BASIC GCI CHANNEL
DCL = 512 kHz
FSC = 8 kHz
D
/D = 256 kbps
out in
FSC
DCL
IF M(2:0) = 7
B1 B1 B1 B1 B1 B1 B1 B1
B1 B1 B1 B1 B1 B1 B1 B1
B2
M
M
D D
C/I
C/I
A E
A E
D
out
B2
D D
D
in
FSC
DCL
IF M(2:0) = 4
D
D
out
in
S/G
CH0
CH1
CH2
125 µs
3 CHANNEL GCI MULTIPLEX
DCL = 1536 kHz /D = 256 kbps/CH
FSC = 8 kHz
D
out in
FSC
DCL
IF M(2:0) = 0
D
D
out
in
CH0
CH1
CH2
CH3
125 µs
4 CHANNEL GCI MULTIPLEX
DCL = 2048 kHz /D = 256 kbps/CH
FSC = 8 kHz
D
out in
Figure 6–1b. Relative Channel Positions (GCI Master Mode)
MOTOROLA
MC145574
6–3
6.4 GCI INDIRECT MODE
When control of the SCP interface is available, a pseudo GCI mode can be activated through the
GCI control register. In the indirect mode, the SCP interface operates as normal and the IDL2 interface
operates in a GCI type 2B+D data format mode. This means that the 2B+D data is assembled in a
pseudo GCI frame for transmission, but the C/I, monitor, and A/E fields are high impedance. For recep-
tion, data is recognized in the B and D channels but is ignored in the C/I, M, and A/E channels. The
SCP interface is available as normal.
125 µs
BASIC GCI CHANNEL IN INDIRECT MODE
FSC
DCL
FSC = 8 kHz
DCL = 512 kHz
D
/D = 256 kbps
out in
B1
B1
B2
D D
D
out
B2
D D
D
in
Figure 6–2. GCI Indirect Mode
The following GCI control bits are located in the overlay register set, in OR5 and OR6.
GCI_IND EN, OR6(b2)
At reset, this bit is set to a logic zero; the inactive state (i.e., normal IDL2 mode). When set to a logic
one, the IDL2 port is reconfigured to have the same 2B+D data format as a GCI interface. When GCI
indirect mode is inactive, OR5(2:0) and OR6(1:0) bits are disabled.
CLK(1:0), OR6(b1, b0)
In master mode, these two bits control the output clock frequency of GCI_DCL. CLK(1:0)=0 is the
default state.
Table 6–1. CLK1, CLK0
GCI Clock Selection
CLK1
CLK0
OR6(b1)
OR6(b0)
GCI_DCL
2.048 MHz
2.048 MHz
1.536 MHz
512 kHz
0
0
1
1
0
1
0
1
6–4
MC145574
MOTOROLA
S(2:0), OR5(b2, b1, b0)
These three bits select the GCI timeslot that the device will use. S(2:0)=0 is the default state, timeslot 0.
The timeslot selected must be compatible with the DCL clock rate being used (i.e., if the clock rate
is 2048 kHz, only the first four timeslots are available).
Table 6–2. GCI Timeslot Assignment
S2
S1
S0
OR5(b2)
OR5(b1)
OR5(b0)
Timeslot
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
FSC
This is an input/output pin to which all serial interface events are synchronized. This pin is periodic
at 8 kHz/125 µs. In the master mode, the pin is an output and is either derived from the S/T frame
or from XTAL. In the slave mode, the pin is an input.
DCL
This is an input/output pin that provides the clock to the serial interface. In the master mode, this pin
is an output; and in the slave mode, it is an input. The clock is continuous and is synchronous with
the frame sync. The clock rate for GCI is double the bit rate (i.e., two clocks per data bit).
When programmed as an input, the clock rate can be any multiple of 16 kHz between 512 and
4096 kHz.
When programmed as an output, the clock rate can be selected via the SCP GCI control register
to be either 2048, 1536, or 512 kHz.
D
in
This pin is always an input. Data to be output on the S/T–interface is input on this pin during the pro-
grammed timeslots. This pin is also the input for the monitor and C/I channels of the GCI frame.
D
out
This pin is an open drain output and requires an external pull–up resistor. This output can be wire–OR’d
with other GCI devices. Data received on the S/T–interface is output on this pin during the programmed
timeslot and is high impedance at all other times. This pin is also the output for the monitor and C/I
channels of the GCI frame.
MOTOROLA
MC145574
6–5
6.5 GCI DIRECT MODE
The alternative GCI mode is direct mode. This mode should be used when a fully–compliant GCI
is required. In this mode, the SCP interface is not available.
In a GCI direct mode the monitor, C/I, and A/E channels are fully active and compatible with the GCI
standards.
To enter a GCI direct mode, the SCPEN/GCIEN pin should be tied to V
and a reset applied to the
SS
device. The GCI direct mode is selected on the rising edge of RESET. The GCIEN pin must be tied
to V at all times when GCI direct mode is the required mode of operation. The GCIEN pin is continu-
SS
ously sampled internally. A “zero–to–one” transition on GCIEN will cause the MC145574 to exit from
a GCI direct mode into IDL/SCP mode.
In GCI direct mode, the IRQ function is not required and is internally disabled.
On entering GCI direct mode, the pins of the MC145574 are redefined as follows.
SCPEN changes to GCIEN (an input).
FST changes to BCL (an output).
SCPCLK changes to S2 (an input) in slave mode, and M2 (an input) in master mode.
SCP Rx changes to S1 (an input) in slave mode, and M1 (an input) in master mode.
SCP Tx changes to S0 (an input) in slave mode, and M0 (an input) in master mode.
DGRANT changes to SG (an output) in TE master mode.
BCL is enabled in both the slave and master mode. BCL is an output clock which is the DCL
clock divided by two. BCL is synchronous with FSC and can be used by non–GCI devices which
require a locked bit frequency clock to access the B and D channel slots (i.e., codec).
6.5.1
Slave Mode
In the slave mode, DCL and FSC are inputs. DCL can be any frequency between 512 kHz and
4.096 MHz. In the slave mode, S2, S1, and S0 pins control the timeslot in which the device operates.
In the NT slave mode, it is possible to select both NT1 Star and NT Terminal modes via the Monitor
channel. The associated pins used in the default IDL2 mode are enabled and operate in the same
manner.
In the TE slave mode, the TFSC/TCLK pin is enabled and it is possible to select the TCLK and its
frequency via the Monitor channel.
6.5.2
Master Mode
In the master mode, DCL and FSC are outputs. The M2, M1, and M0 pins control mode selection
in master mode; however, these modes are defined differently for the NT and TE master.
Table 6–3. M2, M1, and M0 Pins in GCI NT Master Mode
M2
M1
M0
GCI NT Master Mode
0
0
0
DCL = 2.048 MHz, Channel 0
DCL = 2.048 MHz, Channel 1
DCL = 2.048 MHz, Channel 2
DCL = 2.048 MHz, Channel 3
DCL = 1.536 MHz, Channel 0
DCL = 1.536 MHz, Channel 1
DCL = 1.536 MHz, Channel 2
DCL = 512 kHz, Channel 0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
6–6
MC145574
MOTOROLA
In the GCI NT master mode, it is possible to select both NT1 Star and NT Terminal modes via the
Monitor channel. The associated pins used in the default IDL2 mode are enabled and operate in the
same manner.
Table 6–4. M2, M1, and M0 Pins in GCI TE Master Mode
M2
M1
M0
GCI TE Master Mode
DCL = 2.048 MHz
Reserved
0
0
0
0
0
1
0
1
0
Reserved
0
1
1
Reserved
1
0
0
DCL = 1.536 MHz, Terminal Mode
Reserved
1
0
1
1
1
0
Reserved
1
1
1
DCL = 512 kHz
In the GCI TE master mode, only three modes of operation are available.
When M(2:0) = 4, terminal mode is selected. In this mode, the MC145574 always operates in channel 0,
and D channel availability is indicated in two ways:
1. If pin SG = 1, then the D channel is currently idle and available for access. If pin SG = 0, then
the D channel on the passive bus is being used by another TE device.
If the SG pin toggles during the time when the device is using the D channel, then a collision
has occurred and the device stops its D channel access. SG indicates stop/go for D channel
access.
2. In parallel with the SG pin, this signal is also output from the device in bit 4 of the C/I channel
of CH2. This is compatible with the SCIT bus specification and is also compatible with the
MC68302. This is enabled via the Monitor channel in register OR7(6).
When M(2:0) = 7, only one GCI channel is available, and D channel availability is indicated by
the SG pin only.
The D channel access circuitry can be disabled by writing to a control register via the Monitor
channel, BR7(6). When this is done, it is assumed that the device is not operating in a passive
bus application and has sole use of the D channel. When disabled, the SG pin and bit always
equal one, and the GCI D channel data flows transparently to the S/T loop interface.
6.6
2B+D CHANNELS
In the activated state, GCI transparently transmits the information in the B and D channels in the NT
and TE slave modes. In TE master mode, D channel flow control is operational and access to the
D channel must be requested. Refer to the section on GCI D channel operation for further details.
6.7 M AND A/E CHANNELS
The GCI M (or Monitor) channel is intended to be used for the transfer of operation and maintenance
information between management and layer 1 entities. For the MC145574, this means that the Monitor
channel is used to access the internal registers defined for the SCP mode of operation. The A/E channel
is used to control the transfer of the information on the Monitor channel by providing a handshake
facility.
MOTOROLA
MC145574
6–7
6.7.1
Monitor Channel Operation
The Monitor channel is used to access the internal registers of the MC145574. All Monitor channel
messages are two bytes in length. Each byte is sent twice to permit the receiving GCI device to verify
data integrity. In ISDN applications, the Monitor channel is used for access to the S interface mainte-
nance messages. The entire register set of the MC145574 can be accessed via the Monitor channel.
The A and E bits in the GCI channel are used to control and acknowledge Monitor channel transfers
between the MC145574 and another GCI device. When the Monitor channel is inactive, the A and
E bit times from D
are both high impedance. The A and E bits are active when they are driven
out
to V
during their respective bit times. Pull–up resistors are required on D and D . The E bit indi-
SS
in out
cates the transmission of a new Monitor channel byte. The A bit from the opposite direction is used
to acknowledge the Monitor channel byte transfer.
An idle Monitor channel is indicated by both A and E bits being inactive for two consecutive GCI frames.
The A and E bits are high impedance when inactive. The Monitor channel data is $FF.
The originating GCI device transmits a byte onto the Monitor channel after receiving the A and E bits
equal to 1 for at least two consecutive GCI frames. The originating GCI device also sets its outgoing
E bit to 0 in the same GCI frame as the byte that is transmitted. The transmitted byte is repeated
for at least two GCI frames, or is repeated in subsequent GCI frames until the MC145574 acknowledges
receiving two consecutive GCI frames containing the same byte.
Once the MC145574 acknowledges the first byte, the sending device sets E to high impedance and
transmits the first frame of the second byte. Then the second byte is repeated with the E bit low until
it is acknowledged. See Figure 6–3 for details of Monitor channel procedure.
The destination GCI device verifies that it has received the first byte by setting the A bit to 0 towards
the originating GCI device for at least two GCI frames. Successive bytes are acknowledged by the
receiving device setting A to high impedance on the first instance of the next byte followed by A being
cleared to 0 when the second instance of the bit is received.
If the GCI device does not receive the same Monitor channel byte in two consecutive GCI frames,
it indicates this by leaving A = 0 until two consecutive identical bytes are received. The last byte of
the sequence is indicated by the originating GCI device setting its E bit to 1 for two successive GCI
frames.
6.8
MONITOR CHANNEL MESSAGES
The MC145574 supports three basic types of Monitor channel messages. The first group of messages
are commands that read or write the internal register set of the MC145574. See Sections 8, 9, and
10 for the complete description of the MC145574 register set. The second group of messages are
responses from the MC145574. These responses are transmitted by the MC145574 after it receives
a register read or write command over the Monitor channel. The third type of Monitor channel message
is the Status Indication Message. When enabled, this message indicates a change in interrupt status
register NR3.
6–8
MC145574
MOTOROLA
FSC
125 µs
NULL
E
BYTE1
E
BYTE1
E
BYTE2
E
BYTE2
E
NULL
E
NULL
E
NULL
E
D
in
B1 B2 M
B1 B2 M
B1 B2 M
B1 B2 M
B1 B2 M
B1 B2 M
B1 B2 M
B1 B2 M
A
A
A
A
A
A
A
A
D
out
6.8.1
Monitor Channel Commands
A GCI device transmits Monitor channel commands to a receiving MC145574 to access its internal
register set. The receiving MC145574 then transmits a Monitor channel response message onto the
Monitor channel for commands that request data to be read from an internal register. Commands
that write data to an internal MC145574 register are accepted and acted upon, but the MC145574
does not issue a response message. The Monitor channel commands are given in Table 6–5.
The MC145574 acknowledges all messages it receives over the Monitor channel. If an invalid message
is received, the MC145574 acknowledges it but does not take any action.
Table 6–5. Monitor Channel Commands
MSB
Byte 1
LSB
MSB
Byte 2
LSB
7
6
0
0
0
0
0
5
0
0
1
1
0
4
0
1
0
1
0
3
ba3
ba3
0
2
1
0
7
6
d6
X
5
d5
X
4
3
d3
X
2
d2
X
1
0
d0
X
Comment
Byte Write
0
0
0
0
1
ba2
ba2
na2
na2
0
ba1
ba1
na1
na1
0
ba0
ba0
na0
na0
0
d7
X
d4
X
d1
X
Byte Read
d3
X
d2
X
d1
X
d0
X
X
X
X
X
Nibble Write
Nibble Read
ID Command
0
X
X
X
X
0
X
X
X
X
X
X
X
X
6.8.2
Monitor Channel Response Messages
The Monitor channel response messages are transmitted onto the GCI Monitor channel by the
MC145574 in response to a register read command. The Monitor channel response messages are
given in Table 6–6.
Table 6–6. Monitor Channel Response Messages
MSB
Byte 1
LSB
MSB
Byte 2
LSB
7
6
0
0
1
5
0
1
0
4
1
1
0
3
ba3
0
2
1
0
7
6
d6
d2
x
5
d5
d1
x
4
3
d3
x
2
d2
x
1
0
d0
x
Comment
Byte Read
0
0
0
ba2
na2
0
ba1
na1
0
ba0
na0
0
d7
d3
x
d4
d0
x
d1
x
Nibble Read
ID Response
0
x
x
x
x
6.8.3
Monitor Channel Status Indication Messages
This message is automatically transmitted onto the GCI Monitor channel by the MC145574 when a
status change has occurred within the device. This message is analogous to the interrupt in SCP
mode. The Monitor channel status indication message is given in Table 6–7.
The status indication message is in effect a read of the interrupt status register NR3. By default, this
indication message is disabled. The indication message must be first enabled by writing to the Monitor
channel register NR4.
Table 6–7. Monitor Channel Status Indication Messages
MSB
Byte 1
LSB
MSB
Byte 2
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Comment
0
0
1
1
0
0
1
1
d3
d2
d1
d0
x
x
x
x
NR3 Read
6–10
MC145574
MOTOROLA
6.8.4
Accessible Monitor Channel Registers
The following register maps indicate the internal SCP registers that are accessible via the Monitor
channel. Items that are in bold print indicate functions that are different to those of the SCP version.
See Sections 8, 9, and 10 for initial register values after a reset.
(3)
(2)
(1)
Not Applicable
Multiframing Detection
(0)
NR1
NT
TE
Activation Indication
Activation Indication
Error Indication
Frame Sync
Frame Sync
Error Indication
NR2
NR3
Transmit Power Down
Return to Normal
IRQ7 NT Term. D Ch. Coll.
Not Applicable
NT
TE
NT
TE
NT
TE
IRQ3 ∆ Rx Info
IRQ3 ∆ Rx Info
IRQ3 Enable
IRQ2 Multiframe Reception IRQ6 FECV Detect
IRQ2 Multiframe Reception IRQ1 D Channel Collision
NR4
NR5
NR6
IRQ2 Enable
IRQ6 Enable
IRQ7 Enable
IRQ3 Enable
IRQ2 Enable
IRQ1 Enable
Not Applicable
Idle B1 Channel
Enable B1 Channel
Idle B2 Channel
Enable B2 Channel
Invert B1 Channel
Invert B1 Channel
Invert B2 Channel
Invert B2 Channel
Swap B1 and B2
2B+D GCI Transparent
Loopback
(7)
SC1.1
Q.1
(6)
SC1.2
Q.2
(5)
SC1.3
Q.3
(4)
(3)
(2)
(1)
(0)
BR2
BR3
NT
TE
NT
SC1.4
Q.4
Q.1
Q.2
Q.3
Q.4
Q Qual
Int. Every
Multiframe
TE
SC1.1
SC1.2
SC1.3
SC1.4
Not
Applicable
Int. Every
Multiframe
BR4
BR5
BR6
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
B1 S/T
Loopback
Transparent
B1 S/T
Loopback
Non–
B2 S/T
Loopback
Transparent
B2 S/T
Loopback
Non–
GCI B1
Loopback
Transparent
GCI B1
Loopback
Non–
GCI B2
Loopback
Transparent
GCI B2
Loopback
Non–
Transparent
Transparent
Transparent
Transparent
BR7
NT
TE
Activation
Procedures
Disabled
Active Only
NT Enable
Enable
Multiframing
Invert E
Channel
LAPD Polarity Activation
Control
Timer #2
Expired
Activation
Procedures
Disabled
D Channel
Procedures
Ignored
Map E to D
GCI
Free Run
LAPD Polarity
Control
BR9
BR10
BR11
NT
TE
NT
TE
TXSC2.1
RXSC2.1
TXSC4.1
RXSC4.1
TXSC2.2
RXSC2.2
TXSC4.2
RXSC4.2
TXSC2.3
RXSC2.3
TXSC4.3
RXSC4.3
TXSC2.4
RXSC2.4
TXSC4.4
RXSC4.4
TXSC3.1
RXSC3.1
TXSC5.1
RXSC5.1
TXSC3.2
RXSC3.2
TXSC5.2
RXSC5.2
TXSC3.3
RXSC3.3
TXSC5.3
RXSC5.3
TXSC3.4
RXSC3.4
TXSC5.4
RXSC5.4
Rx INFO
State B1
Rx INFO
State B0
Tx INFO
State B1
Tx INFO
State B0
Ext. S/T
Loopback
Transmit 96 kHz
Test Signal
BR12
BR13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Mute B1
Reserved
Reserved
Reserved
NT
TE
NT1 Star
Mode
Mute B2
on GCI Tx
Force Echo
on GCI Tx Channel to 0
Mute B2
on GCI Tx
Mute B1
on GCI Tx
Force
GCI Tx
BR14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MOTOROLA
MC145574
6–11
(7)
(6)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR15
Overlay
Register
Enabled
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
(7)
(5)
(4)
(3)
(2)
(1)
(0)
OR6
OR7
OR8
OR9
TSA B1
Enable
TSA B2
Enable
TSA D
Enable
D
Open
Drain
GCI Indirect
Mode Enable
CLK1
CLK0
out
Disable 3 V
Regulator
Enable
S/G Bit
Enable
TCLK
Enable BCL
Disable XTAL
FIX Enable
NT Terminal
Mode Enable
Sleep
Disable
NT
TE
Force INFO 2
Transmission
T3F8 Enable T3F6 Disable
Rev 1 Rev 0
OR15
Overlay
Register
Enable
Rev 5
Rev 4
Rev 3
Rev 2
All these registers are detailed in the following sections of this document: Section 8 for the nibble
registers, Section 9 for the byte registers, and Section 10 for the overlay registers.
6.8.5
SCP/GCI Register Differences
When configured for GCI direct mode of operation, the following register bits have different functionality
from SCP mode.
OR7(6)
Enable S/G Bit
This bit can be enabled only in GCI 1.536 MHz clock mode. This bit provides the availability of the
D channel on the S/T loop. “1” = Stop (no availability of the D channel) and “0” = Go (availability of
the D channel). Refer to Section 11.
OR8(0)
Sleep Disable
In GCI mode, the sleep mode is enabled by default. It can be disabled by writing to the register bit
(i.e., by writing a logic 1). This is opposite to operation of these bits in the SCP mode.
6.9
COMMAND INDICATE CHANNEL OPERATION
The command/indication (C/I) is intended to manage layer 1 procedures such as activation and deac-
tivation of the line, test loop control, and other additional control functions. C/I codes are four bits
in length and must be received for two consecutive GCI frames before they are acted upon.
The C/I channel bits are numbered bit 4 through bit 1, with bit 4 being the most significant bit. The
C/I channel command bits are transmitted starting with bit 4.
The command channel (COM) is an input to the device in the C/I channel of the GCI frame on the
D
pin.
in
The indicate channel (IND) is an output from the device in the GCI channel of the GCI frame on the
pin.
D
out
In both the COM and IND cases, the four–bit word is continually input or output until superceded by
another C/I channel word.
The command and indicate words used by the MC145574 device are defined in Table 6–8. This table
is fully compatible with the industry standard GCI specification.
6–12
MC145574
MOTOROLA
Table 6–8. C/I Channel Commands and Indications
TE Master
TE Slave
NT
NT Terminal
C/I
Code
Indication
Command
Indication Command Indication Command Indication
Command
DR
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DR
—
TIM
RES
—
DR
—
—
RES
—
—
—
DR
RES
—
—
—
RES
—
—
—
—
—
—
—
—
—
—
—
—
—
RSY
—
—
RSY
—
—
RSY
—
—
RSY
—
—
—
—
—
—
—
T1/T3EXP
—
—
T1/T3EXP
—
—
T1/T3EXP
—
—
T1/T3EXP
—
—
—
—
—
AR
—
AR8
AR10
ARL
AREOM
—
AR
—
AR
AR
—
AR
AR
—
AR8
AR10
ARL
AREOM
AI
AR
AR
—
—
ARL
AR
—
ARL
AR
—
—
—
—
—
AI8
AI10
—
AI
—
AI
AI
AI8
AI10
—
—
—
—
—
—
—
—
—
—
—
AIL
DC
AIL
DC
DI
DC
DI
DI
DI
DC
Table 6–9 lists the GCI C/I codes used, with all the codes coming from the GCI specification except
for T1/T3EXP and AREOM.
Table 6–9. GCI C/I Codes
Command/Indication
Abbreviation
AI
Activation Indication
Activation Indication Priority 1
Activation Indication Priority 2
Activation Indication Local Test Loop
Activation Request
AI8
AI10
AIL
AR
Activation Request Priority 1
Activation Request Priority 2
Activation Request Local Test Loop
Activation Request, End of Message
Deactivation Confirmation
Deactivation Indication
AR8
AR10
ARL
AREOM
DC
DI
Deactivation Request
DR
Reset
RES
RSY
TIM
Resynchronization (Loss of Framing)
Timing Request
Activation Timer Expired — Force Deactivation
T1/T3EXP
MOTOROLA
MC145574
6–13
6.10 GCI ACTIVATION AND DEACTIVATION TIMING DIAGRAMS
The following diagrams (Figures 6–4 through 6–6) indicate the flow of the activation/deactivation proce-
dure and are not intended to be exhaustive in all the possible permutations.
TEM
NTS
INFO 0
INFO 0
I
Rx
Tx
DC
DI
Tx
Rx
C
I
DC
DI
C
START
CLOCKS
D = 0
in
C
C
INFO 1
START
CLOCKS
Rx
I
I
AR8, AR10
Tx
D
out = 0
AR
INFO 2
INFO 3
AR
I
I
Rx
Tx
Tx
Rx
C
I
AR
AI
INFO 4
AI8, AI10
AI
Rx
Tx
C
Figure 6–4. Activation from TE End
6–14
MC145574
MOTOROLA
TEM
NTS
INFO 4
INFO 3
I
Rx
Tx
AI
AI
AI
Tx
Rx
C
I
C
AR8, AR10
INFO 0
INFO 0
DR
I
I
Rx
Tx
Tx
Rx
DR
DI
C
I
DI
DC
C
DC
Figure 6–5. Deactivation from NT End
TEM
NTS
INFO 0
INFO 0
I
Rx
Tx
Tx
Rx
C
I
DC
DI
DC
DI
C
INFO 2
INFO 3
I
Rx
Tx
Tx
Rx
C
I
AR
AI
AR
INFO 4
AI
AI
I
Rx
Tx
C
Figure 6–6. Activation from NT End
MOTOROLA
MC145574
6–15
6–16
MC145574
MOTOROLA
7
PIN DESCRIPTIONS
7.1 INTRODUCTION
The Motorola MC145574 ISDN S/T transceiver is available in a 28–pin SOIC and a 32–pin TQFP
package (see Figure 7–1).
28–LEAD SOIC
32–LEAD TQFP
ISET
RxN
RxP
1
2
3
4
5
28 RESET
27 TxP
32 31 30 29 28 27 26 25
26 TxN
25 XTAL
24 EXTAL
TE/NT
M/S
T_IN/TSFC/TCLK/FIX
1
2
3
4
5
6
7
8
24 XTAL
23 EXTAL
22
21
20
TE/NT
M/S
V 5
DD
V
V
DD
I/O
SS
SG/DGRANT/ANDOUT
DREQUEST/ANDIN
CLASS/ECHO_IN
FSC/FSR
V 3
DD
T_IN/TFSC/TCLK/FIX
6
7
8
9
23
22
21
V 5
DD
19 IRQ/IND
18 TSEN/FSX/BCL/LBA
V
SS
V
DD
I/O
17 SCPEN/GCIEN
9 10 11 12 13 14 15 16
SG/DGRANT/ANDOUT
DREQUEST/ANDIN
V 3
DD
20 IRQ/IND
CLASS/ECHO_IN 10
FSC/FSR 11
DCL 12
19 TSEN/FST/BCL/LBA
18 SCPEN/GCIEN
17 SCPCLK/S2/M2
16 SCPRx/S1/M1
15 SCPTx/S0/M0
D
13
14
in
D
out
Figure 7–1. Pin Assignments
7.2 PIN DESCRIPTIONS
The following pin descriptions are not intended to be exhaustive but merely indicate the operational
modes of the pins. For complete operational details please refer to the appropriate sections of this
document.
7.2.1 ISET
In both the NT and TE modes of operation, a current programming reference resistor of value
30 kΩ accurate to 5% should be connected between this pin and V . This resistor provides biasing
SS
and programs the current limit for the TxP and TxN driver circuit. Note that this resistor is not user
programmable and must be 30 kΩ for CCITT 1.430, ETSI ETS 300012, and ANSI T1.605 compatibility.
7.2.2 RxN, RxP
These two pins form the differential receiver for the S/T–interface. They are connected to the S/T
loop via a transformer. For further information, refer to Section 16.
MOTOROLA
MC145574
7–1
7.2.3
TE/NT
This pin allows the external selection of NT or TE mode. When this pin is held low, the NT mode
is selected; and when it is held high, the TE mode is selected. This pin is OR’d with an SCP register
bit, enabling TE/NT selection to be made in the software. This pin must be tied low to allow software
selection of TE or NT mode.
7.2.4 M/S
This pin allows the external selection of master or slave timing mode for the IDL2/GCI interface. This
pin functions in both NT and TE modes. When this pin is held low, the slave mode is selected; and
when it is held high, the master mode is selected. In the slave mode FSC/DCL are inputs; in the master
mode FSC/DCL are outputs.
This pin is OR’d with an SCP register bit, enabling master/slave selection to be made in the software.
This pin must be tied low to allow software selection of master or slave mode.
7.2.5 T_IN/TFSC/TCLK/FIX
This pin performs four functions dependent on the mode of operation. In all NT modes, except NT
Terminal mode, this pin is the FIX input and enables the device to differentiate between fixed and
adaptive timing modes. When this pin is held low, adaptive timing is selected, and when it is held
high fixed timing is selected. This pin is OR’d with an SCP register bit, enabling fixed/adaptive selection
to be made in the software.
In the NT Terminal mode, this pin is the T_IN input; T_IN is an IDL2 input port that accepts B1, B2,
and D channel data. Refer to the NT Terminal section for further details. In the NT Terminal mode,
the FIX function is controlled via an SCP register bit.
In the TE slave mode, this pin outputs TFSC. TFSC is an 8 kHz frame clock that is synchronized
to the received S/T–interface and can be used as the synchronization source in the NT2 slave–slave
mode.
Alternatively, this pin can output TCLK, selected via the SCP. TCLK is a clock, whose frequency can
be chosen via the SCP, which is synchronized to the received S/T–interface. TCLK can be used as
an alternative to TFSC in NT2 slave–slave mode.
In the TE master mode, this pin has no function and is a high–impedance output.
7.2.6
V
SS
This is the most negative power supply and digital logic ground. It is normally 0 V.
7.2.7 SG/DGRANT/ANDOUT
This pin performs three functions dependent on the mode of operation. In the NT1 Star mode, it is
the ANDOUT output function for use in NT1 Star applications. In the TE master and NT Terminal modes,
this pin is the DGRANT output function used for gaining D channel access. In the GCI TE master
mode, this pin is SG and indicates stop/go access to the D channel.
7.2.8
DREQUEST/ANDIN
This pin performs two functions dependent on the mode of operation. In the NT1 Star mode, it is the
ANDIN input function for use in NT1 Star applications. In the TE master and NT Terminal modes,
this pin is the DREQUEST input used for requesting D channel access. In all other modes, this input
has no defined function and should be tied to V
.
SS
7–2
MC145574
MOTOROLA
7.2.9
CLASS/ECHO_IN
This pin performs two functions dependent on the mode of operation. In the NT1 Star mode, it is the
ECHO_IN input function for use in NT1 Star applications. In the TE master mode, this pin is the class
input used to determine the D channel access class. In all other modes, this input has no defined
function and should be tied to V
.
SS
7.2.10 FSC/FSR
This pin is bidirectional; the direction depending on whether the device is to be a timing master or
a slave to the IDL2/GCI interfaces. In either case, this pin should be driven with or it generates an
8 kHz frame sync signal. This pin is also the frame sync signal for the IDL2 receive direction (FSR)
when independent frame syncs have been enabled via the SCP interface.
7.2.11 DCL
This pin is the clock pin for the IDL2/GCI interfaces and is either an input or an output depending
on whether the interface is operating as a slave or a master.
7.2.12
7.2.13
D
in
This pin is the data input pin for the GCI and IDL2 interfaces.
D
out
This pin is the data output pin for the GCI and IDL2 interfaces.
7.2.14 SCP Tx/S0/M0
This pin has three functions. It is the data output pin (SCP Tx) in SCP mode, a timeslot select input
pin (S0) in GCI slave mode, and a mode select pin (M0) in GCI master mode.
7.2.15 SCP Rx/S1/M1
This pin has three functions. It is the data input pin (SCP Rx) in SCP mode, a timeslot select input
pin (S1) in GCI slave mode, and a mode select pin (M1) in GCI master mode.
7.2.16 SCPCLK/S2/M2
This pin has three functions. It is the clock input pin (SCPCLK) in SCP mode, a timeslot select input
pin (S2) in GCI slave mode, and a mode select pin (M2) in GCI master mode.
7.2.17 SCPEN/GCIEN
This pin has two functions. It is the SCP enable input pin (SCPEN) in SCP mode, and the GCI enable
input pin (GCIEN) in GCI mode. Refer to the section on GCI for details on how the device enters
GCI mode.
7.2.18 TSEN/FST/BCL/LBA
This pin is initially high impedance, but can be programmed to have three separate functions. When
the TSEN signal is enabled via the SCP, this pin becomes an open drain output that pulls low when
data is being output from D . This signal can then be used to enable an external driver in applications
out
where the IDL2 2B+D data goes off–board (PBXs, etc.).
MOTOROLA
MC145574
7–3
In IDL2 mode, this pin can also be used as the 8 kHz frame sync (FST) for the transmit path. In this
mode, the pin is bidirectional, the direction depending on whether the device is an IDL2 master or
slave. FST only operates when dual frame sync mode has been enabled via the SCP.
In GCI mode, this pin can be an output clock (BCL). BCL is a bit rate clock that is half the frequency
of the DCL clock and is synchronous with FSC. This clock can be used as the data clock for standard
devices such as a codec. BCL must be enabled via the GCI Monitor channel.
Loopback active (LBA) is the default function for both the IDL2 and GCI modes. This pin is initially
an output. The LBA pin is normally low but when a loopback is activated within the device, this pin
will transition to a high during the time that the loopback is enabled. This pin can be redefined by
writing to internal registers within the device.
7.2.19 IRQ/IND
This pin is an open drain output that pulls low when the device wants to inform the microprocessor
that a status change has occurred. This pin returns to high impedance after clearing the interrupt condi-
tion via the SCP.
In GCI mode, this pin is GCI_IND. It is an open drain output and is driven low to indicate that GCI
mode is enabled.
7.2.20
7.2.21
V
3
DD
This pin is the 3 V regulated supply output used to power the internal digital circuitry. This pin requires
an external smoothing capacitor to be connected to ground (100 nF).
V
I/O
DD
This is the positive supply pin for the output drivers. This pin should be connected to V 5, if 5 V
DD
drivers are required; or the 3 V regulator output, V 3, if 3 V drivers are required. For further informa-
DD
tion, refer to the section on Power Supply Strategy.
7.2.22
V
5
DD
This is the positive supply pin and is normally 5 V ± 5%. It should have a capacitor of 100 nF connected
to ground. For further information, refer to the section on Power Supply Strategy.
7.2.23 EXTAL
This pin is an output and should be connected to the 15.36 MHz crystal using the circuit defined in
Section 14.
7.2.24 XTAL
This pin is an output and should be connected to the 15.36 MHz crystal using the circuit defined in
Section 14, or alternatively it can be driven by an external 15.36 MHz clock source.
7.2.25 TxN, TxP
These two pins form a differential output driver that will connect to the S/T–interface via a transformer.
For further information, refer to Section 16.
7.2.26 RESET
This pin is always an input and is the reset pin for the device. It is active low. When this pin is held
low, a hardware reset is applied and the device is held in the deactivated state. At the initial application
7–4
MC145574
MOTOROLA
of power, the MC145574 should be reset. This pin is a Schmitt–trigger input and could have an external
RC circuit connected to perform the power–on reset function.
7.3 ADDITIONAL NOTES
7.3.1
Input Levels
The MC145574 S/T transceiver is always TTL/CMOS level compatible on all digital input pins.
7.3.2
7.3.3
Output Levels
The MC145574 is always CMOS level compatible on all digital output pins.
SCP HIDOM
The MC145574 S/T transceiver has the capability of forcing all outputs (both analog and digital) to
the high–impedance state. This feature, known as the “serial control port high–impedance digital output
mode” is provided to allow “in–circuit” testing of other circuits or devices resident on the same PCB
without requiring the removal of the MC145574.
The SCP HIDOM mode is entered by holding SCPEN low for a minimum of 33 consecutive rising
edges of the SCPCLK while SCP Rx is high. If SCPEN goes high or if SCP Rx goes low, the device
exits the SCP HIDOM mode and returns to normal operation.
MOTOROLA
MC145574
7–5
7–6
MC145574
MOTOROLA
8
NIBBLE REGISTER MAP DEFINITION
8.1 INTRODUCTION
There are seven nibble registers (NR0 through NR6) in the MC145574. Control and status information
reside in these nibble registers, which are accessed via the SCP. For a detailed description of access
procedures, refer to Section 5. The nomenclature used in this data sheet is such that NR2(3) refers
to nibble register 2, bit 3.
The MC145574 nibble register map is compatible to the MC145474/475 nibble register map, the only
modification being the removal of bits NR6(2) and NR6(1), related to the IDL A/M FIFOs and the addi-
tion of bits (NR2(0), NR3(0), and NR4(0) for NT mode only).
Table 8–1. SCP Nibble Register Map for NT Operation
(3)
(2)
(1)
(0)
NR0
NR1
NR2
Software Reset
Transmit Power Down
Error Indication
Absolute Minimum Power Return to Normal
Activation Indication
Activation Request
Not Applicable
Frame Sync
Deactivation Request
Activation Timer T1
Expired
NT Terminal Class
NR3
Change in Rx Info
State IRQ3
Multiframe Reception
IRQ2
IRQ6 FECV Detection
D Channel Collision IRQ7
NT Terminal Mode
NR4
NR5
NR6
Enable IRQ3
Enable IRQ2
Enable IRQ6
Enable IRQ7
Idle B1 Channel
2B+D IDL2 Loopback
Idle B2 Channel
Invert B1 Channel
Invert B2 Channel
Swap B1 and B2
Table 8–2. SCP Nibble Register Map for TE Operation
(3)
(2)
(1)
(0)
NR0
NR1
NR2
Software Reset
Transmit Power–Down
Error Indication
Not Applicable
Absolute Minimum Power Return to Normal
Activation Indication
Activation Request
Multiframing Detection
Frame Sync
Class
Activation Timer T3
Expired
NR3
Change in Rx Info
State IRQ3
Multiframe Reception
IRQ2
D Channel Collision IRQ1 Not Applicable
NR4
NR5
NR6
Enable IRQ3
Enable IRQ2
Enable IRQ1
Not Applicable
Enable B1 Channel
2B+D IDL2 Loopback
Enable B2 Channel
Invert B1 Channel
Invert B2 Channel
Swap B1 and B2
MOTOROLA
MC145574
8–1
Table 8–3. Nibble Register Initialization After Any Reset
IDL TE
IDL NT
GCI TE
GCI NT
NR0
NR1
NR2
NR3
NR4
NR5
NR6
0
0
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0
0
0
0
0
NOTE: All values in hexadecimal unless shown otherwise.
8.2 NR0
This register is a read/write register and can be reset by a hardware reset. A per–bit description of
nibble register 0 (NR0) follows.
b3
b2
b1
b0
NR0
Software Reset
Transmit Power–Down
Absolute Minimum
Power
Return to Normal
rw
rw
rw
rw
NR0(3) — Software Reset
When NR0(3) is 0, the MC145574 functions normally. When this bit is set to 1, a software reset is
applied to the internal circuits of the S/T transceiver. The effect of the software reset is the equivalent
of holding the external reset input low (hardware reset), except that NR0(3:0) is not reset. Thus, when
this bit is set, all internal registers (except NR0) are returned to their initial state. Application of either
a hardware or software reset has the effect of re–initializing all the internal registers; it does not prevent
access to the SCP. Note that NR0(3) is a read/write bit.
NR0(2) — Transmit Power–Down
When NR0(2) is 0, the S/T transceiver functions normally. When NR0(2) is set to 1, the S/T transceiver
enters a power conservation mode. In this mode the transmit section of the transceiver is held in the
INFO 0 state and IDL2 Tx is held in the “idle 1s” condition. When NR0(2) = 1, the receive circuitry
of the transceiver is still functional, allowing an interrupt to be generated in the event of a change
in state of the received signal. Note that NR0(2) is a read/write bit. This bit has no effect on the operation
of the SCP. If BR13(1) is set, the S/T transceiver outputs data on D
.
out
NR0(1) — Absolute Minimum Power
When this bit is 0, the MC145574 functions normally. When this bit is set to 1, the chip enters a power
conservation mode. In this mode a software reset is applied to the chip, all circuits are initialized, all
clocking of the device is blocked, and the nonessential bias to the analog functions of the transceiver
are removed such that the device consumes the absolute minimum amount of power. The transmit
section of the chip is held in the INFO 0 state and IDL2 Tx is held in the “idle 1s” condition. Note
that NR0(1) is a read/write bit. This bit has no effect on the operation of the SCP. In this mode, only
the SCP can operate.
NR0(0) — Return to Normal
When this bit is 0, the MC145574 functions normally. When this bit is 1, the following bits are reset:
BR11(0) 96 kHz Test Signal
BR11(1) External S/T Loopback
BR6(7:0)
Note that NR0(0) is a read/write bit.
8–2
MC145574
MOTOROLA
8.3
NR1
This register is a read only register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 1 (NR1) follows.
b3
b2
b1
b0
NR1
Activation Indication
Error Indication
NT: Not Applicable
TE: Multiframing
Detection
Frame Sync
ro
ro
ro
ro
NR1(3) — Activation Indication (AI)
This bit is set by the MC145574 when the loop is fully activated. Thus, when the MC145574 is config-
ured as an NT, this bit is set when it is transmitting INFO 4 and receiving INFO 3. Conversely, when
the MC145574 is configured as a TE, this bit is set when it is transmitting INFO 3 and receiving INFO
4. Note that NR1(3) is a read only bit.
NR1(2) — Error Indication (EI)
NR1(2) is set by the MC145574 S/T transceiver to indicate an error condition has been detected by
the activation state machine of the transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. The low–to–high level transition of the EI bit corresponds to the EI1 error indication
reporting, while the high–to–low level transition of the EI bit corresponds to the EI2 error indication
reporting recovery. Note that NR1(2) is a read only bit.
NR1(1) — NT: Not Applicable
TE: Multiframing Detection (MD)
In the TE mode of operation, this bit is set by the MC145574 S/T transceiver whenever it detects
multiframing from the NT. This bit will be set low if multiframing synchronization is lost and will return
high when synchronization is re–acquired. This bit applies only to TE–configured devices. Note that
NR1(1) is a read only bit.
NR1(0) — Frame Sync (FS)
NR1(0) is set high by the MC145574 S/T transceiver when frame synchronization is achieved. NR1(0)
is reset by the MC145574 whenever frame synchronization is lost. Note that NR1(0) is a read only
bit.
8.4 NR2
This register is a read/write register and can be cleared by application of either a hardware or software
reset. A per–bit description of nibble register 2 (NR2) is as follows.
b3
b2
b1
b0
NR2
Activation Request
NT: Deactivate Request
TE: Not Applicable
rw
Activation Timer
Expired
NT: NT Terminal Class
TE: Class
rw
rw
rw
NR2(3) — Activation Request (AR)
When NR2(3) is set to 1, an activation request input is passed to the activate state machine within
the MC145574 S/T transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
If the transceiver is in the idle state (i.e., transmitting and receiving INFO 0) and is configured as an
NT, then AR causes INFO 2 to be sent out on the transmit side of the S/T–interface. Alternatively,
if the chip is configured as a TE and is in the idle state, then writing a 1 to NR2(3) causes INFO 1
to be sent out. Note that this bit will be returned low by the MC145574 S/T transceiver after its active
MOTOROLA
MC145574
8–3
transition (low–to–high) has been recognized by the activation/deactivation state machine of the trans-
ceiver. This action indicates that the requested action has been recognized. Note that NR2(3) is a
read/write bit.
NR2(2) — NT: Deactivate Request DR
TE: Not Applicable
When NR2(2) is set to 1, a deactivate request input is passed to the activation state machine within
the MC145574 S/T transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
The deactivate request input is used to initiate deactivation of the transmission loop. Note that this
bit will be returned low by the MC145574 S/T transceiver after its active transition (low–to–high) has
been recognized by the activation/deactivation state machine of the transceiver. This action indicates
that the requested action has been recognized and deactivation is proceeding. Note that NR2(2) is
a read/write bit.
NR2(1) — Activation Timer Expired Input
NT: Timer #1
TE: Timer #3
When NR2(1) is set to 1, an activation timer expired input is passed to the activation state machine
of the MC145574 S/T transceiver. If the transceiver is configured as an NT, this bit corresponds to
the Timer #1 expire input. If the transceiver is configured as a TE, this bit corresponds to the Timer
#3 expire input. These timers correspond to the activation timers outlined in CCITT I.430, ETSI ETS
300012, and ANSI T1.605. The timer expire input informs the activation/deactivation state machine
that sufficient time has elapsed since the request to activate the loop and that attempts to do so should
be abandoned. This bit is normally set by the controlling device and is automatically cleared when
the MC145574 has deactivated the loop. This bit can be reset by hardware or a software reset. Note
that NR2(1) is a read/write bit.
NR2(0) — NT : NT Terminal Class
TE : Class
When the MC145574 is configured for TE mode, this bit sets the class for D channel operation. When
this bit is 0, the chip is set for class 1 operation. Alternatively, when this bit is 1, the chip is configured
for class 2 operation. Class 1 and class 2 operations are as per CCITT I.430, ETSI ETS 300012,
and ANSI T1.605 (i.e., class 1 is the higher class, used for signalling information, and class 2 is the
lower class). The class can also be chosen externally by means of the CLASS/ECHO_IN pin. In this
case, the class is chosen by the logical ‘OR’ of the external pin and NR2(0). NR2(0) can be reset
by a hardware or a software reset. Refer to Section 11 for a detailed description of the D channel.
Note that NR2(0) is a read/write bit.
In the NT Terminal mode, this bit sets the class for D channel operation idle in the TE mode.
8.5 NR3
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 3 (NR3) follows.
b3
b2
b1
b0
NR3
Change in RX INFO
State IRQ3
Multiframe Reception
IRQ2
NT: IRQ6 FECV
Detection
TE: D Channel Collision
NT: IRQ7 NT Terminal
D Channel Collision
TE: Not Applicable
IRQ1
rw
rw
rw
rw
NR3(3) — Change in Rx INFO State IRQ3
The interrupt request condition IRQ3 is generated whenever a change occurs in the received informa-
tion state of the transceiver. In the NT mode, this corresponds to a change in the receiving INFO 0,
8–4
MC145574
MOTOROLA
INFO 1, INFO 3, or INFO X state. Alternatively, in the TE mode, this corresponds to a change in the
receiving INFO 0, INFO 2, INFO 4, or INFO X state. Thus, when a change occurs in one of these
states, the MC145574 internally sets this bit. An external interrupt will occur if “Enable IRQ3” (NR4(3))
is set. IRQ3 can be cleared by writing a 0 to NR3(3). This bit is reset by a software or a hardware
reset.
Note that the transmission states for the NT (INFO 0, INFO 2, and INFO 4) and for the TE (INFO 0,
INFO 1, and INFO 3) are as defined in Section 3. INFO X is defined as any transmission state other
than those states. An example of such a state would be when the MC145574 is programmed to transmit
a 96 kHz test tone (BR11(0) = 1). Note that NR3(3) is a read/write bit.
An INFO X state interrupt is generated only when receive INFO X state has persisted for > 8 ms.
This avoids spurious interrupts during transient INFO X changes seen during activation but allows
indication of prolonged INFO X conditions.
NR3(2) — Multiframe Reception IRQ2
This bit is for multiframe detection indication. Multiframing is initiated by the NT by setting BR7(5).
A multiframe is 20 basic frames or 5 ms in duration. If this interrupt is enabled by setting NR4(2) and
if multiframing is in progress, then an interrupt will be generated on multiframe boundaries; i.e., every
5 ms. Alternatively, an NT–configured MC145574 can be programmed to generate an interrupt only
in the event of a new Q channel nibble having been received. Similarly, a TE–configured MC145574
can be programmed to generate an interrupt only in the event of a new SC1 subchannel having been
received. Refer to Section 12 for a detailed description of these features.
A mutiframing interrupt is cleared by reading BR3. Reading BR3 will clear the interrupt in both the
NT and TE modes of operation, regardless of whether the MC145574 is configured to generate an
interrupt in the event of a new nibble or every multiframe. Note that NR3(2) is a read only bit.
NR3(1)
NT: IRQ6 FECV Detection — The IRQ6 status bit is set when the NT has detected a far–end code
violation. See Section 15.6 for more details.
TE: D Channel Collision IRQ1 — NR3(1) is an interrupt bit used to indicate to external devices
that a collision has occurred on the D channel. A D channel collision is considered to have occurred
when the TE is transmitting on the D channel (both DREQUEST and DGRANT being high), and the
received E echo bit from the NT does not match the previously modulated D bit. The interrupt condition
is cleared by writing a 0 to NR3(1). This bit is maskable by means of NR4(1). Note that NR3(1) is
a read/write bit.
NR3(0) — NT: D Channel Collision IRQ7 NT Terminal Mode
TE: Not Applicable
NR3(0) is an interrupt bit used to indicate to external devices that a collision has occurred on the
D channel. A D channel collision is considered to have occurred when the NT is transmitting on the
IDL2 Tx D channel via the T_IN input pin (both DREQUEST and DGRANT being high), and the trans-
mitted E echo bit to the TE does not match the previously input T_IN bit. The interrupt condition is
cleared by writing a 0 to NR3(0). This bit is maskable by means of NR4(0). Note that NR3(0) is a
read/write bit.
8.6
NR4
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 4 (NR4) follows.
b3
b2
b1
b0
NR4
Enable IRQ3
Enable IRQ2
NT: Enable IRQ6
TE: Enable IRQ1
NT: Enable IRQ7
TE: Not Applicable
rw
rw
rw
rw
MOTOROLA
MC145574
8–5
NR4(3) — Enable IRQ3
NR4(3) is an interrupt mask bit for IRQ3. When this bit is set high and IRQ3 is pending (i.e., NR3(3)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to NR3(3).
When the interrupt mask bit NR4(3) is a 0, NR3(3) cannot cause an interrupt to the external device.
This bit can be reset by either a software or hardware reset. Note that NR4(3) is a read/write bit.
NR4(2) — Enable IRQ2
NR4(2) is an interrupt mask bit for IRQ2. When this bit is set high and IRQ2 is pending (i.e., NR3(2)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by reading BR3. When the
interrupt mask bit (NR4(2)) is a 0, NR3(2) cannot cause an interrupt to the external device. This bit
can be reset by either a software or a hardware reset. Note that NR4(2) is a read/write bit.
NR4(1) — NT: Enable IRQ6
TE: Enable IRQ1
NR4(1) is an interrupt mask bit for IRQ1 or IRQ6. When this bit is set high and IRQ1 is pending (i.e.,
NR3(1) having been internally set to a 1), an interrupt is given to an external device by holding the
IRQ* pin low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to
NR3(1). When the interrupt mask bit NR4(1) is a 0, NR3(1) cannot cause an interrupt to the external
device. This bit can be reset by either a software or a hardware reset. Note that NR4(1) is a read/write
bit.
NR4(0) — NT: Enable IRQ7
TE: Not Applicable
NR4(0) is an interrupt mask bit for IRQ7. When this bit is set high and IRQ7 is pending (i.e., NR3(0)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to NR3(0).
When the interrupt mask bit NR4(0) is a 0, NR3(0) cannot cause an interrupt to the external device.
This bit can be reset by either a software or a hardware reset. Note that NR4(0) is a read/write bit.
8.7 NR5
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 5 (NR5) follows.
b3
b2
b1
b0
NR5
NT: Idle B1 Channel
NT: Idle B2 Channel
Invert B1 Channel
Invert B2 Channel
TE: Enable B1 Channel
TE: Enable B2 Channel
rw
rw
rw
rw
NR5(3)
NT: Idle B1 Channel — In the NT mode, NR5(3) functions as a B1 channel idle bit. When NR5(3)
is 0, the MC145574 functions normally where data received in the B1 channel timeslot via the IDL2
is modulated onto the S/T–interface in the B1 channel timeslot. When NR5(3) is 1, data input on the
IDL2 Rx pin in the B1 channel timeslot is ignored, and the “idle 1s” condition exists on the B1 channel
timeslot on the S/T–interface. Note that the default condition (i.e., after power–up or after a reset)
for NR5(3) is 0, thereby allowing the data received via the IDL2 interface to be modulated onto the
transmission loop. Note that NR5(3) is a read/write bit in the NT mode.
TE: Enable B1 Channel — In the TE mode of operation, NR5(3) functions as a B1 channel enable
bit. In the TE mode B1 channel data is forced to the “idle 1s” condition on the S/T transmission loop
when NR5(3) is 0. When NR5(3) is 1 (enabled), B1 channel data input via the IDL2 interface is modu-
lated and transmitted onto the S/T transmission loop in the B1 channel timeslot. The default condition
(i.e., after power–up or after a reset) for TE mode devices forces the B1 channel bits to the “idle 1s”
condition. This is to avoid B channel interference until the B channels are assigned by the network.
8–6
MC145574
MOTOROLA
This function may be used in multidrop configurations or in applications where the output B channel
transmission must be held in the “idle 1s” condition. Note that NR5(3) is a read/write bit in the TE
mode.
NR5(2)
NT: Idle B2 Channel — In the NT mode, NR5(2) functions as a B2 channel idle bit. When NR5(2)
is 0, the MC145574 functions normally, where data received in the B2 channel timeslot via the IDL2
is modulated onto the S/T transmission loop in the B2 channel timeslot. When NR5(2) is 1, data input
on the IDL2 Rx pin in the B2 channel timeslot is ignored, and the “idle 1s” condition exists on the
B2 channel timeslot on the S/T transmission loop. Note that the default condition (i.e., after power–up
or after a reset) for NR5(2) is 0, thereby allowing the data received via the IDL2 interface to be modu-
lated onto the transmission loop. Note that NR5(2) is a read/write bit in the NT mode.
TE: Enable B2 Channel — In the TE mode of operation, NR5(2) functions as a B2 channel enable
bit. In the TE mode B2 channel data is forced to the “idle 1s” condition on the S/T transmission loop
when NR5(2) is 0. When NR5(2) is 1 (enabled), B2 channel data input via the IDL2 interface is modu-
lated and transmitted onto the S/T transmission loop in the B2 channel timeslot. The default condition
(i.e., after power–up or after a reset) for TE mode devices forces the B2 channel bits to the “idle 1s”
condition. This is to avoid B channel interference until the B channels are assigned by the network.
This function may be used in multidrop configurations or in applications where the output B channel
transmission must be held in the “idle 1s” condition. Note that NR5(2) is a read/write bit in the TE
mode.
NR5(1) — Invert B1 Channel
When NR5(1) is 0, the B1 channel data received via the IDL2 interface is transmitted normally on
the transmission loop. When NR5(1) is set to 1, the B1 channel data received via the IDL2 interface
is inverted before entering the modulator portion of the MC145574 S/T transceiver, prior to transmission
on the S/T loop in the B1 timeslot. The selected B1 channel data received via the transmission loop
is also inverted before being output on the IDL2 Tx pin when this function is invoked. This feature
is useful in applications where it is required to use inverted data. Note that NR5(1) is a read/write
bit.
NR5(0) — Invert B2 Channel
When NR5(0) is 0, the B2 channel data received via the IDL2 interface is transmitted normally on
the transmission loop. When NR5(0) is set, the B2 channel data received via the IDL2 interface is
inverted before entering the modulator portion of the MC145574 S/T transceiver prior to transmission
on the S/T loop in the B2 timeslot. The selected B2 channel data received via the transmission loop
is also inverted before being output on the IDL2 Tx pin when this function is invoked. This feature
is useful in applications where inverted data is required. Note that NR5(0) is a read/write bit.
8.8
NR6
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 6 (NR6) is as follows.
b3
b2
b1
b0
NR6
2B+D IDL2 Loopback
Swap B1 and B2
rw
rw
NR6(3) – 2B+D IDL2 Loopback
When NR6(3) is 0, the MC145574 S/T transceiver functions normally. When NR6(3) is set to 1, the
B1, B2, and D channel data input on the IDL2 Rx input pin are buffered and returned to the IDL2
Tx output pin on the next IDL2 cycle. The output B1, B2, and D channel data is passed unchanged
to the modulator portion of the transceiver and transmitted onto the S/T loop (i.e., the loopback is
transparent). Note that NR6(3) is a read/write bit.
MOTOROLA
MC145574
8–7
NR6(0) – Swap B1 and B2
When NR6(0) is 0, the timeslot assigned positions of the B1 and B2 channel data input and output
via the IDL2 interface functions normally. When NR6(0) is set to 1, the timeslot positions of the B1
and B2 channels are reversed; i.e., data entering the device on IDL2 Rx in the B1 timeslot is modulated
onto the B2 timeslot, on the S/T loop. Data demodulated from the B2 timeslot from the S/T loop is
output on IDL2 Tx in the B1 timeslot. The situation is analogous for B2 data entering the device on
IDL2 Rx. This feature is useful in applications where a particular device (such as a codec filter) is
hard–wired to a particular IDL2 timeslot and needs to gain access to the opposite B channel timeslot.
NR6(0) has no effect during a 2B+D IDL2 loopback. Note that NR6(0) is a read/write bit.
NOTE: When NR6(0) is set, the B channel used on the IDL bus must be enabled before being output
on the S/T loop. For example, if data entering the device on D in the B1 channel is modulated onto
in
the B2 channel on the S/T loop, then NR5(3) has to be set. On the MC145474/75, this is done differently.
For the same example, NR5(2) is set instead of NR5(3).
8.9
NR7
NR7 is a pointer register used when accessing a 16–byte–wide register. This pointer register will con-
tain the address of the byte–wide register to be read from or written to, on the following SCP transaction.
This nibble register is not shown on the register map, as it is not programmable.
8–8
MC145574
MOTOROLA
9
BYTE REGISTER MAP DESCRIPTION
9.1 INTRODUCTION
There are 16 byte registers (BR0 through BR15) in the MC145574. Control, status, and maintenance
information reside in these byte registers, which are accessed via the SCP. For a detailed description
of access procedures, refer to Section 5. The nomenclature used in this data sheet is such that BR2(3)
refers to byte register 2, bit 3.
The byte register map is fully compatible with the byte register map of the MC145474, with the exception
of:
1. The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
has no effect, and reading them returns FFH.
2. TheTTLinputlevelbitBR13(6)hasbeenremoved. ThedigitalinputsareCMOSandTTLcompatible.
Writing to this bit has no effect, and reading it returns 0 or 1 depending on what value, if any, has been
written.
3. The only addition to the byte register map is the bit BR15(0), used for enabling the overlay registers.
Table 9–1. Byte Register Map for NT Mode of Operation
(7)
SC1.1
Q.1
(6)
SC1.2
Q.2
(5)
SC1.3
Q.3
(4)
SC1.4
Q.4
(3)
(2)
(1)
(0)
BR2
BR3
Q Qual
Interrupt
Every
Multiframe
BR4
BR5
BR6
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
B1 S/T
Loopback
Transparent
B1 S/T
Loopback
Non–
B2 S/T
Loopback
Transparent
B2 S/T
Loopback
Non–
IDL2 B1
Loopback
Transparent
IDL2 B1
Loopback
Non–
IDL2 B2
Loopback
Transparent
IDL2 B2
Loopback
Non–
Transparent
Transparent
Transparent
Transparent
BR7
Activation
Procedures
Disabled
Active Only
NT Enable
Enable
Multiframing
Invert E
Channel
IDL2 Master
Mode
IDL2 Clock
Speed (LSB)
LAPD
Polarity
Control
Activation
Timer #2
Expired
BR9
BR10
BR11
TXSC2.1
TXSC4.1
TXSC2.2
TXSC4.2
TXSC2.3
TXSC4.3
TXSC2.4
TXSC4.4
TXSC3.1
TXSC5.1
TXSC3.2
TXSC5.2
TXSC3.3
TXSC5.3
TXSC3.4
TXSC5.4
Do Not React Do Not React
to INFO 1
Rx INFO
State B1
Rx INFO
State B0
Tx INFO
State B1
Tx INFO
State B0
External S/T
Loopback
Transmit
96 kHz
to INFO 3
Test Signal
BR12
BR13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NT1 Star
Mode
IDL2 Clock
Speed (MSB)
Mute B2
on IDL2 Tx
Mute B1
on IDL2 Tx
Force Echo
Channel
to Zero
Not
Applicable
BR14
BR15
Reserved
Reserved
Reserved
Rev 5
Reserved
Rev 4
Reserved
Rev 3
Reserved
Rev 2
Reserved
Rev 1
Reserved
Rev 0
Overlay
Register
Enabled
MOTOROLA
MC145574
9–1
Table 9–2. Byte Register Map for TE Mode of Operation
(7)
Q.1
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR2
BR3
Q.2
Q.3
Q.4
SC1.1
SC1.2
SC1.3
SC1.4
Not
Applicable
Interrupt
Every
Multiframe
BR4
BR5
BR6
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
B1 S/T
Loopback
Transparent
B1 S/T
Loopback
Non–
B2 S/T
Loopback
Transparent
B2 S/T
Loopback
Non–
IDL2 B1
Loopback
Transparent
IDL2 B1
Loopback
Non–
IDL2 B2
Loopback
Transparent
IDL2 B2
Loopback
Non–
Transparent
Transparent
Transparent
Transparent
BR7
Activation
Procedures
Disabled
D Channel
Procedures
Ignored
Not
Applicable
Map E
to D
IDL2
Free Run
IDL2 Clock
Speed (LSB)
LAPD
Polarity
Control
BR9
BR10
BR11
RXSC2.1
RXSC4.1
RXSC2.2
RXSC4.2
RXSC2.3
RXSC4.3
RXSC2.4
RXSC4.4
RXSC3.1
RXSC5.1
RXSC3.2
RXSC5.2
RXSC3.3
RXSC5.3
RXSC3.4
RXSC5.4
Not
Applicable
Not
Applicable
Rx INFO
State B1
Rx INFO
State B0
Tx INFO
State B1
Tx INFO
State B0
External S/T
Loopback
Transmit
96 kHz
Test Signal
BR12
BR13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Not
IDL2 Clock
Mute B2
Mute B1
Not
Force
Applicable
Speed (MSB)
on IDL2 Tx
on IDL2 Tx
Applicable
IDL2 Tx
BR14
BR15
Reserved
Reserved
Reserved
Rev 5
Reserved
Rev 4
Reserved
Rev 3
Reserved
Rev 2
Reserved
Rev 1
Reserved
Rev 0
Overlay
Register
Enabled
Table 9–3. Byte Register Initialization After Any Reset
IDL TE
IDL NT
GCI TE
GCI NT
BR0
FF
FF
FF
FF
BR1
BR2
FF
FF
FF
FF
F0
00
F0
00
BR3
00
F0
00
F0
BR4
00
00
00
00
BR5
00
00
00
00
BR6
00
00
00
00
BR7
00
00
00
00
BR8
00
00
00
00
BR9
00
00
00
00
BR10
BR11
BR12
BR13
BR14
BR15
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00XX XXXX
00XX XXXX
00XX XXXX
00XX XXXX
NOTES:
1. All values in hexadecimal unless shown otherwise.
2. BR15 and OR15 are the same register.
3. BR0, BR1, and BR8 are reserved registers. Do not use.
9–2
MC145574
MOTOROLA
9.2 BR0
The functions that were related to the IDL2 M FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
9.3
BR1
The functions that were related to the IDL2 A FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
9.4 BR2
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR2
NT: SC1.1
TE: Q.1
NT: SC1.2
TE: Q.2
NT: SC1.3
TE: Q.3
NT: SC1.4
TE: Q.4
BR2(7:4)
NT: Subchannel 1 (SC1) to S/T Loop — BR2(7:4) are used for multiframing. In the NT mode of opera-
tion, these four bits correspond to subchannel 1 for transmission to the TE(s). Multiframing is initiated
by the NT by setting BR7(5). When multiframing is enabled, the NT will transmit the bits in BR2(7:4)
as subchannel 1, in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. BR2(7:4),
is internally polled at the start of every multiframe (this occurs every 5 ms and the device can be pro-
grammed to give an interrupt at the start of every multiframe), and its contents are interpreted as
subchannel 1. If multiframing is enabled and the contents of BR2(7:4) have not been updated, then
the subchannel is re–transmitted as is. BR2(7:4) can be updated any time between the 5 ms interrupts.
BR2(7:4) are read/write bits. Application of either a software or hardware reset resets these bits to
all 0s. Note that BR2(7) is the MSB of SC1 and BR2(4) is the LSB. Refer to Section 10 for a more
detailed description of this feature.
TE: Q Nibble to S/T Loop — BR2(7:4) are used for multiframing. In the TE mode of operation these
four bits correspond to the Q channel data for transmission to the NT. When multiframing is enabled,
the TE will transmit the bits in BR2(7:4), as Q channel data, in accordance with CCITT I.430, ETSI
ETS 300012, and ANSI T1.605. BR2(7:4) is internally polled at the start of every multiframe (this occurs
every 5 ms and the device can be programmed to give an interrupt at the start of every multiframe),
and its contents are interpreted as Q channel data. If multiframing is enabled and the contents of
BR2(7:4) have not been updated then the Q channel is re–transmitted as is. BR2(7:4) can be updated
any time between the 5 ms interrupts. BR2(7:4) are read/write bits. Application of either a software
or hardware reset sets these bits to all 1s. Note that BR2(7) is the MSB of the Q channel and BR2(4)
is the LSB. Refer to Section 10 for a more detailed description of this feature.
9.5 BR3
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR3
NT: Q.1
TE: SC1.1
NT: Q.2
TE: SC1.2
NT: Q.3
TE: SC1.3
NT: Q.4
TE: SC1.4
NT: Q Qual
TE: Not
Interrupt
Every
Applicable
Multiframe
BR3(7:4)
NT: Q Nibble from S/T Loop — BR3(7:4) are used in the multiframing mode of operation. When
the device is configured as an NT and multiframing has been enabled, these bits correspond to the
received Q channel nibble from the TE(s). These bits are updated once every multiframe. The NT–con-
figured device can give an interrupt once every multiframe (see BR3(2) and NR4(2)) or every time
a new Q channel nibble is received. BR3(7:4) are read only bits. Application of either a hardware
MOTOROLA
MC145574
9–3
or software reset sets these bits to all 1s. Note that BR3(7) is the MSB of the received Q channel
nibble, and BR3(4) is the LSB. Refer to Section 12 for a more detailed description of this feature.
Reading BR3 clears the multiframe interrupt.
TE: SC1 FROM S/T LOOP — BR3(7:4) are used in the multiframing mode of operation. When the
device is configured as a TE and multiframing has been enabled, these bits correspond to the received
subchannel 1 nibble from the NT. These bits are updated once every multiframe. The TE–configured
device can give an interrupt once every multiframe, or every time a new subchannel nibble (SC1)
is received (see BR3(2) and NR4(2)). BR3(7:4) are read only bits. Application of either a hardware
or software reset resets these bits to all 0s. Note that BR3(7) is the MSB of the received SC1 subchannel
nibble and BR3(4) is the LSB. Refer to Section 12 for a more detailed description of this feature.
BR3(3) — NT: Q Bit Quality Indicate
TE: Not Applicable
In the NT mode, this bit corresponds to the Q bit quality indication. When multiframing has been initiated
by the NT, the TE(s) will respond by sending Q data once every five frames. This Q data will be trans-
mitted in the Fa bit position. During the other four frames (i.e., when the TE(s) are not transmitting
Q data), the Fa bit should be a 0. BR3(3) being high indicates that the Fa bits in the frames where
multiframing data was not being transmitted were 0s. This bit is a read only bit and is reset to 0 by
application of either a hardware or software reset.
BR3(2)
NT: Interrupt Every Multiframe — Programming of BR3(2) dictates whether an interrupt will be given
every multiframe (assuming multiframing has been enabled and IRQ2 enable, NR4(2), has been set),
or only on the receipt of a new Q channel nibble from the TE(s). When BR3(2) is 1, an interrupt is
given every multiframe. When BR3(2) is 0, an interrupt is given only on the receipt of a new Q channel
nibble. Refer to Section 12 for a more detailed description. BR3(2) is a read/write bit and is reset
to 0 by application of either a hardware or software reset.
TE: Interrupt Every Multiframe — Programming of BR3(2) dictates whether an interrupt will be given
every multiframe (assuming multiframing has been enabled and IRQ2 enable, NR4(2), has been set),
or only on the receipt of a new SC1 subchannel nibble from the NT. When BR3(2) is 1, an interrupt
is given every multiframe. When BR3(2) is 0, an interrupt is given only on the receipt of a new SC1
subchannel nibble. Refer to Section 12 for a more detailed description. BR3(2) is a read/write bit and
is reset to 0 by application of either a hardware or software reset.
9.6
BR4
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR4
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
Recommendation CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications state that there
must be two AMI violations in every S/T frame. The F bit is the first violation and the succeeding violation
must occur within 13 or 14 bauds, depending on the configuration of the transceiver as either an NT
or TE. BR4(7:0) is the output of an 8–bit binary counter. This counter counts the number of frames
which do not contain the correct number of AMI violations. Note that in multiframing, it is possible
to have a frame which does not contain the correct number of violations (Fa = 1, B1 = 1). The
MC145574, when in multiframe mode, does not count these frames. Thus, this counter is a “frame
error” counter, counting the number of frames which do not contain the correct number of AMI viola-
tions. BR4(7:0) only counts frames not containing the correct number of AMI violations after FSYNC
has been achieved, and ceases counting whenever FSYNC is lost.
BR4(7:0) is applicable to both NT and TE modes of operation. It is a read/write register, thereby allowing
the user to program the counter to a predetermined value. The counter is initialized to “100” by a
hardware/software reset. Note that the counter, upon reaching a value of “FF”, will not roll over; i.e.,
it will remain at “FF” until the user rewrites a starting value. Note that BR4(7) is the MSB of the counter
and BR4(0) is the LSB.
9–4
MC145574
MOTOROLA
9.7 BR5
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR5
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
BR5(7:0) is the output of an 8–bit binary counter. This counter counts the number of unbalanced frames.
A frame in which the total number of positive pulses is different from the total number of negative
pulses constitutes an unbalanced frame. BR5(7:0) is applicable to both NT and TE modes of operation.
It is a read/write register, thereby allowing the user to program the counter to a predetermined value.
The counter is initialized to “100” by a hardware/software reset. Note that the counter, upon reaching
a value of “FF”, will not roll over; i.e., it will remain at “FF” until the user rewrites a starting value.
Note that BR5(7) is the MSB of the counter and BR5(0) is the LSB.
9.8
BR6
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
B1 S/T
Loopback
Transparent
BR6
B1 S/T
Loopback
Non–
B2 S/T
B2 S/T
Loopback
Non–
IDL2 B1
IDL2 B1
Loopback
Non–
IDL2 B2
IDL2 B2
Loopback
Non–
Loopback
Loopback
Loopback
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
BR6(7) — B1 S/T Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B1 S/T Loopback Transparent
Mode”. In this mode, data entering the device from RxP/PxN in the B1 timeslot is demodulated and
remodulated back out on TxP/TxN in the B1 timeslot. The demodulated B1 data continues to present
itself on IDL2 Tx in the B1 timeslot (hence, the term “transparent”). Data entering the part from IDL2
Rx in the B1 timeslot is ignored. This bit is reset to 0 by either a software reset, a hardware reset,
or in the “return to normal” mode (NR0(0) = 1).
BR6(6) — B1 S/T Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0 the device functions normally. When this bit is 1, the device enters a “B1 S/T Loopback Non–Trans-
parent Mode”. In this mode, data entering the device from RxP/RxN in the B1 timeslot is demodulated
and remodulated back out on TxP/TxN in the B1 timeslot. Data entering the part from IDL2 Rx in
the B1 timeslot is ignored. IDL2 Tx ignores the demodulated B1 data, presenting in its stead the “idle
1s” condition in the IDL2 Rx B1 timeslot (hence, the term “non–transparent”). This bit is reset to 0
by either a software reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(5) — B2 S/T Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B2 S/T Loopback Transparent
Mode”. In this mode, data entering the device from RxP/RxN in the B2 timeslot is demodulated and
remodulated back out on TxP/TxN in the B2 timeslot. The demodulated B2 data continues to present
itself on IDL2 Tx in the B2 timeslot (hence, the term “transparent”). Data entering the part from IDL2
Rx in the B2 timeslot is ignored. This bit is reset to 0 by either a software reset, a hardware reset,
or in the “return to normal” mode (NR0(0) = 1).
BR6(4) — B2 S/T Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B2 S/T Loopback Non–Trans-
parent Mode”. In this mode, data entering the device from RxP/RxN in the B2 timeslot is demodulated
and remodulated back out of TxP/TxN in the B2 timeslot. Data entering the part from IDL2 Rx in the
MOTOROLA
MC145574
9–5
B2 timeslot is ignored. IDL2 Tx ignores the demodulated B2 data, presenting in its stead the “idle
1s” condition in the IDL2 Rx B2 timeslot (hence, the term “non–transparent”). This bit is reset to 0
by either a software reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(3) — IDL2 B1 Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B1 timeslot
at D and transmits it onto the D
B1 timeslot is also transmitted onto the S/T–interface. This bit is reset to 0 by either a software reset,
a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
pin during the B1 timeslot. Data entering the D pin during the
in out
in
BR6(2) — IDL2 B1 Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B1 channel
timeslot at D and transmits it onto the D
pin during the B1 timeslot. Data entering the D pin during
in
out
in
the B1 timeslot is not transmitted onto the S/T–interface. Instead, the MC145574 transmits idle 1s
onto the B1 channel bits of the S/T–interface. This bit is reset to 0 by either a software reset, a hardware
reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(1) — IDL2 B2 Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B2 channel
timeslot at D and transmits it onto the D
the B2 timeslot is also transmitted onto the S/T–interface. This bit is reset to 0 by either a software
reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
pin during the B2 timeslot. Data entering the D pin during
in
out
in
BR6(0) — IDL2 B2 Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B2 channel
timeslot at D and transmits it onto the D
pin during the B2 timeslot. Data entering the D pin during
in
out
in
the B2 timeslot is not transmitted onto the S/T–interface. Instead, the MC145574 transmits idle 1s
onto the B2 channel bits of the S/T–interface. This bit is reset to 0 by either a software reset, a hardware
reset, or in the “return to normal” mode (NR0(0) = 1).
9.9
BR7
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR7
Activation
Procedures
Disabled
NT: Active
Only NT
Enable
NT: Enable NT: Invert E
NT: IDL2
Master
Mode
TE: IDL2
Free Run
IDL2 Clock
Speed
(LSB)
LAPD
Polarity
Control
NT:
Multi–
framing
TE: Not
Channel
TE: Map E
To IDL2
Activation
Timer #2
Expired
TE: Not
Applicable
TE: D
Channel
Procedures
Ignored
Applicable
BR7(7) — Activation Procedures Disabled
This bit a read/write bit and is applicable to both NT and TE modes of operation. When this bit is
0, the MC145574 functions normally. When this bit is set to 1, the transmit section of the transceiver
is forced into the highest information state. Thus, if the device is operating as NT, INFO 4 is forced
out on the transmit side of the device. INFO 4 is forced out regardless of what is being received on
RxP/RxN. If the device is operating as a TE, the transceiver transmits INFO 3 on TxP/TxN.
9–6
MC145574
MOTOROLA
Note that if activation procedures are disabled as a TE, causing INFO 3 to be transmitted, then this
state may or may not be commensurate with receiving INFO 0 from the NT. In the event that INFO 0
is being received, the transmitted INFO 3 is transmitted asynchronously. If either INFO 2 or INFO 4
are subsequently received, then the TE’s INFO 3 aligns itself to the received signal in accordance
with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. Note also that a TE wakes up if it receives
either INFO 2 or INFO 4 from the NT. However, an NT transmitting INFO 0 will not wake up to the
reception of INFO 3 from the TE. For an NT to be woken up by a TE, it must first receive INFO 1
from the TE and then proceed to go through the subsequent handshaking. BR7(7) is reset to 0 by
application of either a hardware or software reset.
BR7(6) — NT: Active Only NT Enable
TE: D Channel Procedures Ignored
When the MC145574 is configured as a TE, this bit is used to enable/disable D channel contention
procedures in accordance with the CCITT I.430, ETSI ETS 300012, and ANSI T1.605. When this
bit is 0, the D channel procedures are adhered to as per the DREQUEST, DGRANT, and CLASS pin
descriptions. When this bit is 1, the D channel procedures are ignored, allowing the data present in
the D channel on IDL2 Rx to be modulated regardless of the status of DREQUEST and DGRANT.
BR7(6) = 1 causes the TE to disregard the demodulated E echo bits. The TE’s D data will be modulated
regardless. This bit is a read/write bit and is reset to 0 by application of either a software or a hardware
reset. When configured as an NT, this bit enables the “active only NT” mode. In this mode, the NT
is restricted to the G2 or G3 state; i.e., the device is either activated or attempting to activate. The
device is never allowed to fully deactivate.
BR7(5) — NT: Enable Multiframing
TE: Not Applicable
When the MC145574 is configured as an NT, this bit is used to enable/disable multiframing in accor-
dance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. When this bit is 0, multiframing is dis-
abled. In this mode the M, Fa, and S bauds transmitted from the NT will be binary 0. When this bit
is 1, multiframing is enabled. In this mode, the M, Fa, and S bauds will adhere to the multiframing
coding rules as outlined in CCITT I.430 and ANSI T1.605. Since the TE cannot initiate multiframing,
this bit has no application in this mode. This bit is a read/write bit and is reset to 0 by application
of either a software or a hardware reset.
BR7(4)
NT: Invert Echo Channel — When the MC145574 is configured as an NT, this bit is used to determine
the polarity of the transmitted echo channel from the NT to the TE. When this bit is a 0, the transmitted
E bit is the same as the previously demodulated D bit from the TE(s). When this bit is 1, the transmitted
E bit is the logical inverse of the previously demodulated D bit. This bit is a read/write bit and is reset
to 0 by application of either a software or hardware reset.
TE: Map E Bits to IDL2 — With the MC145574 configured as a TE and this bit a 0, the TE outputs
the demodulated D channel data in the D timeslot on the IDL2 Tx. When this bit is set to 1, the TE
outputs the demodulated E channel in the D timeslot on IDL2 Tx, neglecting the demodulated D channel
data. This bit is a read/write bit and is reset to 0 by application of either a software or a hardware
reset.
BR7(3)
NT: IDL2 Master Mode — With the MC145574 configured as an NT, this bit determines whether the
device operates in IDL2 slave or IDL2 master mode. When this bit is 0, the NT operates in the IDL2
slave mode, where IDL2 SYNC and IDL2 CLK are inputs to the device. When this bit is 1, the NT
operates in the NT IDL2 master mode, where IDL2 SYNC and IDL2 CLK are outputs from the device.
This bit is a read/write bit OR’d with the M/S pin and is reset to 0 by application of either a software
or hardware reset.
TE: IDL2 Free Run — When the MC145574 is configured as a TE and the loop is active, the device
will output IDL2 SYNC and IDL2 CLK synchronous to the inbound data from the NT. When the loop
is inactive and this bit is 0, the TE does not output IDL2 SYNC or IDL2 CLK. If this bit is 1, the TE
outputs IDL2 SYNC and IDL2 CLK regardless of the status of the loop. If the loop is inactive, these
MOTOROLA
MC145574
9–7
signals will be free–running (derived from the crystal). If the loop is active, these signals will be synchro-
nous to the inbound data. This bit is a read/write bit and is reset to 0 by application of either a software
or a hardware reset.
BR7(2) — IDL2 Clock Speed (LSB)
This bit is a read/write bit and is applicable to both NT and TE modes of operation. BR7(2), in conjunc-
tion with BR13(5), determines the IDL2 CLK frequency when operating in the IDL2 master mode.
BR7(2) is the LSB and BR13(5) is the MSB. The code corresponding to each IDL2 clock frequency
is shown in Table 9–4.
Table 9–4. IDL2 Clock Speed Codes
IDL2 CLK
BR13(5)
BR7(2)
Rate
Duty Cycle
50%
0
0
1
1
0
1
0
1
2.56 MHz
2.048 MHz
1.536 MHz
512 kHz
53.3%
50%
50%
Application of either a hardware or a software reset will reset this bit to 0. Refer to Section 4 for a
more detailed description of this feature.
BR7(1) — NT: LAPD Polarity Control (NT Terminal Mode)
TE: LAPD Polarity Control
When the MC145574 is configured as a TE or an NT (Terminal Mode), this bit performs the “LAPD
Polarity Control” function. When this bit is 0, the active state of DREQUEST and DGRANT signals
is defined to be the logic 1 or high state. When this bit is 1, the active state of these signals is defined
to be the logic 0 or low state. This bit is a read/write bit and is reset to 0 by application of either a
hardware or software reset.
BR7(0) — NT: Activation Timer #2 Expired
TE: Not Applicable
When the MC145574 is configured as an NT, this bit performs the “Activation Timer #2 Expired” func-
tion. When this bit is 0, the NT–configured S/T transceiver uses a value of 50 ms for the Timer #2
value outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605 (i.e., the device unambiguously
detects INFO 1). When this bit is 1, a value of 100 ms is used for the value of Timer #2. This bit is
a read/write bit and is reset to 0 by application of either a hardware or software reset.
9.10 BR8
The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
will have no effect, and reading them will return 00H or any value that has been written to them. (No
register shown.)
9.11 BR9
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR9
NT:
NT:
NT:
NT:
NT:
NT:
NT:
NT:
TXSC2.1
TE:
TXSC2.2
TE:
TXSC2.3
TE:
TXSC2.4
TE:
TXSC3.1
TE:
TXSC3.2
TE:
TXSC3.3
TE:
TXSC3.4
TE:
RXSC2.1
RXSC2.2
RXSC2.3
RXSC2.4
RXSC3.1
RXSC3.2
RXSC3.3
RXSC3.4
9–8
MC145574
MOTOROLA
BR9(7:4)
NT: SC2 to Loop — BR9(7:4) is used for multiframing. In the NT mode of operation, these four bits
correspond to subchannel 2 for transmission to the TE(s). Multiframing is initiated by the NT by setting
BR7(5). When multiframing is enabled, the NT will transmit the bits in BR9(7:4) as subchannel 2, in
accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. BR9(7:4), are internally polled
at the start of every multiframe (this occurs every 5 ms and the device can be programmed to give
an interrupt at the start of every multiframe), and the contents are interpreted as subchannel 2. If
multiframing is enabled and the contents of BR9(7:4) have not been updated, the subchannel is re–
transmitted as is. BR9(7:4) can be updated any time between the 5 ms interrupts. In the NT mode
of operation, BR9(7:4) are write only bits. These bits are reset to 0 by application of either a software
or hardware reset. Note that BR9(7) is the MSB of SC2 and BR9(4) is the LSB. Refer to Section 10
for a detailed description of the multiframe procedure.
TE: SC2 from Loop — BR9(7:4) are used in the multiframing mode of operation. When the device
is configured as a TE and multiframing has been enabled, these bits correspond to the received sub-
channel 2 nibble from the NT. These bits are updated once every multiframe. BR9(7:4) are read only
bits and are reset to 0 by application of either a software or hardware reset. Note that BR9(7) is the
MSB of SC2 and BR9(4) is the LSB. Refer to Section 10 for a detailed description of the multiframe
procedure.
BR9(3:0)
NT: SC3 to Loop — BR9(3:0) is used for multiframing. In the NT mode of operation, these four bits
correspond to subchannel 3 for transmission to the TE(s). When multiframing is enabled, the NT will
transmit the bits in BR9(3:0) as subchannel 3, in accordance with CCITT I.430, ETSI ETS 300012,
and ANSI T1.605. BR9(3:0) are internally polled at the start of every multiframe (this occurs every
5 ms and the device can be programmed to give an interrupt at the start of every multiframe), and
the contents are interpreted as subchannel 3. If multiframing is enabled and the contents of BR9(3:0)
have not been updated, the subchannel is re–transmitted as is. BR9(3:0) can be updated any time
between the 5 ms interrupts. In the NT mode of operation, BR9(3:0) are write only bits. These bits
are reset to 0 by application of either a software or hardware reset. Note that BR9(3) is the MSB of
SC3 and BR9(0) is the LSB. Refer to Section 12 for a detailed description of the multiframe procedure.
TE : SC3 from Loop — BR9(3:0) are used in the multiframing mode of operation. When the device
is configured as a TE and multiframing has been enabled, these bits correspond to the received sub-
channel 3 nibble from the NT. These bits are updated once every multiframe. BR9(3:0) are read only
bits and are reset to 0 by application of either a software or hardware reset. Note that BR9(3) is the
MSB of SC2 and BR9(0) is the LSB. Refer to Section 10 for a detailed description of the multiframe
procedure.
9.12 BR10
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR10
NT:
NT:
NT:
NT:
NT:
NT:
NT:
NT:
TXSC4.1
TE:
TXSC4.2
TE:
TXSC4.3
TE:
TXSC4.4
TE:
TXSC5.1
TE:
TXSC5.2
TE:
TXSC5.3
TE:
TXSC5.4
TE:
RXSC4.1
RXSC4.2
RXSC4.3
RXSC4.4
RXSC5.1
RXSC5.2
RXSC5.3
RXSC5.4
BR10(7:4)
NT: SC4 to Loop — BR10(7:4) are used for multiframing. In the NT mode of operation, these four
bits correspond to subchannel 4 for transmission to the TE(s). When multiframing is enabled, the NT
will transmit the bits in BR10(7:4) as subchannel 4, in accordance with CCITT I.430, ETSI ETS 300012,
and ANSI T1.605. BR10(7:4) are internally polled at the start of every multiframe (this occurs every
5 ms and the device can be programmed to give an interrupt at the start of every multiframe), and
the contents are interpreted as subchannel 4. If multiframing is enabled and the contents of BR10(7:4)
have not been updated, the subchannel is re–transmitted as is. BR10(7:4) can be updated any time
between the 5 ms interrupts. In the NT mode of operation, BR10(7:4) are write only bits. These bits
MOTOROLA
MC145574
9–9
are reset to 0 by application of either a software or hardware reset. Note that BR10(7) is the MSB
of SC4 and BR10(4) is the LSB. Refer to Section 10 multiframing for a detailed description of the
multiframing procedure.
TE: SC4 from Loop — BR10(7:4) are used in the multiframing mode of operation. When the device
is configured as a TE and multiframing has been enabled, these bits correspond to the received sub-
channel 4 nibble from the NT. These bits are updated once every multiframe. BR10(7:4) are read
only bits and are reset to 0 by either a software or hardware reset. Note that BR10(7) is the MSB
of SC4 and BR10(4) is the LSB. Refer to Section 10 for a detailed description of multiframe procedures.
BR10(3:0)
NT: SC5 to Loop — BR10(3:0) are used for multiframing. In the NT mode of operation, these four
bits correspond to subchannel 5 for transmission to the TE(s). When multiframing is enabled, the NT
will transmit the bits in BR10(3:0) as subchannel 5, in accordance with CCITT I.430, ETSI ETS 300012,
and ANSI T1.605. BR10(3:0) is internally polled at the start of every multiframe (this occurs every
5 ms and the device can be programmed via NR4(2) to give an interrupt at the start of every multiframe),
and the contents are interpreted as subchannel 5. If multiframing is enabled and the contents of
BR10(3:0) have not been updated, the subchannel is re–transmitted as is. BR10(3:0) can be updated
any time between the 5 ms interrupts. In the NT mode of operation, BR10(3:0) are write only bits.
These bits are reset to 0 by application of either a software or hardware reset. Note that BR10(3)
is the MSB of SC5 and BR10(0) is the LSB. Refer to Section 10 for a detailed description of the multi-
frame procedure.
TE: SC5 from Loop — BR10(3:0) are used in the multiframing mode of operation. When the device
is configured as a TE and multiframing has been enabled, these bits correspond to the received sub-
channel 5 nibble from the NT. These bits are updated once very multiframe. BR10(3:0) are read only
bits and are reset to 0 by either a software or hardware reset. Note that BR10(3) is the MSB of SC5
and BR10(0) is the LSB. Refer to Section 10 for a detailed description of the multiframe procedure.
9.13 BR11
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR11
NT: Do Not NT: Do Not
Rx INFO
State B1
Rx INFO
State B0
Tx INFO
State B1
Tx INFO
State B0
External
S/T
Loopback
Transmit
96 kHz
Test Signal
React To
INFO 1
React To
INFO 3
TE: Not
TE: Not
Applicable
Applicable
9.13.1 BR11(7) — NT: Do Not React to INFO 1
TE: Not Applicable
This bit is only applicable to the NT mode of operation. When this bit is 0, the part functions normally.
When this bit is 1, the NT will not react to INFO 1 from the TE. (Note, however, that the NT will give
an interrupt indicating a change in received information state.) Only when the NT resets this bit to
0 will it react to INFO 1. This feature is used in the NT in applications where it is necessary to delay
activation of the S/T loop until the U link has reached its active state. This bit is a read/write bit and
is reset to 0 by application of either a hardware or software reset.
BR11(6) — NT: Do Not React to INFO 3
TE: Not Applicable
This bit is only applicable to the NT mode of operation. When this bit is 0, the part functions normally.
When this bit is 1, the NT will not react to INFO 3 from the TE (this INFO 3 from the TE being the
response of the TE to INFO 2 from the NT). Only when the NT resets this bit to 0 will it react to INFO
3. In the meantime, the NT will continue to transmit INFO 2. This feature is used in the NT in applications
where it is necessary to delay activation of the S/T loop until the U link has reached its active state.
This bit is a read/write bit and is reset to 0 by application of either a hardware or software reset.
9–10
MC145574
MOTOROLA
BR11(5), BR11(4) — Rx INFO State B1 and B0
These bits are read/write bits and are applicable to both NT and TE modes of operation. The MC145574
internally sets these bits to indicate the status of the received signal; i.e., it is INFO 0, 1, 2, 3, 4, or
X, where INFO X is none of the above. An example of INFO X would be when it is receiving the 96 kHz
test signal. Another example of INFO X would be where the transceiver is not receiving INFO 0, but
it has not yet determined whether it is INFO 1, 2, 3, or 4.
The codes corresponding to the different states are shown in Table 9–5.
Table 9–5. BR11(5), BR11(4) Rx INFO State Codes
BR11(5)
BR11(4)
Receive Information State
0
0
1
1
0
1
0
1
INFO 0
INFO LOW
INFO HIGH
INFO X
NOTE: When configured as an NT, receiving INFO LOW corresponds to receiving INFO 1, and receiv-
ing INFO HIGH corresponds to receiving INFO 3. Conversely, when the device is operating as a TE,
receiving INFO LOW corresponds to receiving INFO 2, and receiving INFO HIGH corresponds to re-
ceiving INFO 4. The device internally sets these bits, and this internal write overrides any external
write. These bits are reset to 0 by application of either a hardware or software reset.
BR11(3), BR11(2) — Tx INFO State B1 and B0
These bits are read/write bits and are applicable to both NT and TE modes of operation. The MC145574
internally sets these bits to indicate the status of the transmitted signal; i.e., is it INFO 0, 1, 2, 3, 4,
or X where INFO X is none of the above. An example of INFO X would be when it is transmitting
the 96 kHz test signal. The codes corresponding to the different states is shown in Table 9–6.
Table 9–6. BR11(3), BR11(2) Tx INFO State Codes
BR11(3)
BR11(2)
Transmit Information State
0
0
1
1
0
1
0
1
INFO 0
INFO LOW
INFO HIGH
INFO X
NOTE: When configured as an NT, transmitting INFO LOW corresponds to transmitting INFO 2, and
transmitting INFO HIGH corresponds to transmitting INFO 4. Conversely, when the device is operating
as a TE, transmitting INFO LOW corresponds to transmitting INFO 1, and transmitting INFO HIGH
corresponds to transmitting INFO 3. The device internally sets these bits, and this internal write over-
rides any external write. These bits are reset to 0 by application of either a hardware or software reset.
BR11(1) — External S/T Loopback
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the MC145574 functions normally. If the transmit pair is shorted to the receive pair while this
bit is 1, the device will perform an external or “analog” loopback. In an analog loopback, the device
demodulates its own transmitted data. The transceiver should have its activation procedures disabled
(BR7(7) = 1) and be configured for the IDL2 master mode (BR7(3) = 1). This feature is useful for
test purposes. In external loopback, the B1 and B2 channels are looped back. In the NT mode, the
D channel is also looped back. The D channel is not looped back in the TE mode. Application of a
hardware or software reset will reset this bit to 0.
MOTOROLA
MC145574
9–11
BR11(0) — Transmit 96 kHz Test Signal
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the MC145574 functions normally. When this bit is 1, the device transmits a 96 kHz square wave
test signal on TxP/TxN. This test signal can be used for test purposes. This 96 kHz test signal qualifies
as a “Transmit INFO X” state. Correspondingly, the MC145574 receiving the 96 kHz test signal will
be in the “Receive INFO X” state. Application of a hardware or software reset will reset this bit to 0.
9.14 BR12
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte register 12 is reserved for Motorola use only.
9.15 BR13
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR13
NT: NT1
Star Mode
TE: Not
Reserved
IDL2 Clock Mute B2 on Mute B1 on
NT: Force
Echo
Channel to
Zero
NT: Not
Applicable
TE: Force
IDL2 Tx
Reserved
Speed
(MSB)
IDL2 Tx
IDL2 Tx
Applicable
TE: Not
Applicable
BR13(7) — NT: NT1 Star Mode
TE: Not Applicable
This bit is a read/write bit and is only applicable to the NT mode of operation. When this bit is 0, the
device functions normally. When this bit is 1, the device is configured for NT1 Star mode operation.
Refer to Section 11 for a detailed description of this mode. This bit is reset to 0 by application of either
a hardware or software reset.
BR13(6)
This bit has no function and is reserved for Motorola use only.
BR13(5) — IDL2 Clock Speed (MSB)
This bit is a read/write bit and is applicable to both NT and TE modes of operation. BR13(5), in conjunc-
tion with BR7(2), determines the IDL2 CLK frequency when operating in the IDL2 master mode. BR7(2)
is the LSB and BR13(5) is the MSB. The code corresponding to each IDL2 clock frequency is as shown
in the description for BR7(2). Application of either a hardware or a software reset will reset this bit
to 0. See Table 9–3.
BR13(4) — Mute B2 on IDL2
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the data transmitted on the B2 channel on IDL2
Tx will be forced to the “idle 1s” condition. This feature is primarily used in the NT1 Star mode operation.
Refer to Section 11 for a detailed description of this mode. Application of a hardware or software reset
resets this bit to 0.
BR13(3) — Mute B1 on IDL2
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the data transmitted on the B1 channel on IDL2
Tx will be forced to the “idle 1s” condition. This feature is primarily used in the NT1 Star mode operation.
9–12
MC145574
MOTOROLA
Refer to Section 11 for a detailed description of this mode. Application of a hardware or software reset
resets this bit to 0.
BR13(2) — NT: Force Echo Channel to Zero
TE: Not Applicable
This bit is a read/write bit and is only applicable to the NT mode of operation. When the MC145574
is configured as an NT and this bit is 0, the device functions normally. When this bit is 1, the NT forces
the transmitted E bits to be 0. This feature is used for test purposes when the NT wishes tocommunicate
to the TEs on the passive bus that they should disengage from the D channel. Application of either
a hardware or a software reset resets this bit to 0.
BR13(1) —NT: Not Applicable
TE: Force IDL2 Tx
This bit is a read/write bit and is only applicable to the TE mode of operation. When the MC145574
is configured as a TE and this bit is 0, the device functions normally. When this bit is 1, data is presented
on IDL2 Tx in the special case where the TE is synchronized to INFO 4 incoming from the NT but
its transmitter is not fully active (i.e., not transmitting INFO 3). This feature is useful when the MC145574
is in the transmit power down mode (NR0(2) = 1) and it is desired to continue to process data from
the NT. This bit has no effect when the device is fully active (transmitting INFO 3 and receiving INFO 4).
When BR13(1) = 0 and the device is not fully active, “idle 1s” will be presented on IDL2 Tx. Application
of either a hardware or a software reset resets this bit to 0.
BR13(0)
This bit is reserved.
9.16 BR14
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte register 14 is a read/write register. It is reserved for Motorola use only.
9.17 BR15
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR15
Overlay
Register
Enabled
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
BR15(7) — Overlay Register Enabled
When the device is initialized, this bit is a logic 0. When set to a logic 0, operation of the MC145574
register map is identical to that of the MC145474. When set to a logic 1, a second set overlay register
is enabled. The overlay register map allows access to the TSA registers required by the IDL2 and
also to a GCI control register.
BR15(5:0) — Device Revision Identification, Rev (5:0)
The Rev (5:0) bits indicate the revision status of the device. These bits are read only and can only
be modified by altering the device mask. Rev (5:0) is set to 11H for G20R1 mask set and to 03H
for F57J4 mask set. See Section 20 for F57J4 mask set differences.
MOTOROLA
MC145574
9–13
9–14
MC145574
MOTOROLA
10
OVERLAY REGISTER MAP DEFINITION
10.1 INTRODUCTION
There are eleven overlay registers (OR0 through OR9 and OR15) in the MC145574. The overlay regis-
ters are a second bank of registers available when the overlay register control bit BR15(7) is set to
a logic 1. These overlay registers are in the IDL2 TSA mode used to assign the timeslot used by each
channel (B1, B2, and D) for transmission and reception; OR0 through OR5, OR6, OR7, and OR8
are control registers used in the GCI indirect mode, and OR15 gives the revision number of the S/T
chip.
Table 10–1. Overlay Register Map
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR0
OR1
OR2
OR3
OR4
OR5
OR5
OR6
D
D
B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
D Channel Timeslot Bits (7:0) (IDL2 Mode)
B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
in
in
D
in
D
D
out
out
D
D Channel Timeslot Bits (7:0) (IDL2 Mode)
out
Time Slot Assignment for GCI Mode
S2
S1
S0
TSA B1
Enable
TSA B2
Enable
TSA D
Enable
D
Open
out
Drain
GCI Indirect
Mode Enable
CLK1
CLK0
OR7
Disable
3 V
Regulator
Enable
S/G Bit
Enable
TCLK
Dual Frame
Syncs
Long
Frame
8/10 Bit
Select
TSEN B1/B2
Enable,
BCL Enable
TSEN
D Channel
Enable
OR8
OR9
Reserved
Disable XTAL
TE Mode
Enable
Master Mode
Enable
FIX Enable
NT Terminal
Mode Enable
Sleep
Enable
Force
INFO 2
T3F8
Enable
T3F6
Disable
Transmission
OR15
Overlay
Register
Enable
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
MOTOROLA
MC145574
10–1
Table 10–2. Overlay Register Initialization After Any Reset
IDL TE
IDL NT
GCI TE
GCI NT
OR0
OR1
00
00
00
00
04
04
00
00
OR2
08
08
00
00
OR3
00
00
00
00
OR4
04
04
00
00
OR5
08
08
00
00
OR6
00
00
00
00
OR7
00
00
00
00
00
00
00
01
OR8
OR15
NOTES:
00XX XXXX
00XX XXXX
00XX XXXX
00XX XXXX
1. All values in hexadecimal unless shown otherwise.
2. BR15 and OR15 are the same register.
10.2 OR0
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR0
D
B1 Channel Timeslot Bits (7:0)
in
OR0(7:0) — Tx B1 Channel Timeslot
This register allows the B1 channel timeslot input to the D pin to be allocated 1 of 256 start points,
in
corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or 10 CLKs
wide. The default value for OR0 is 00H.
10.3 OR1
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR1
D
in
B2 Channel Timeslot Bits (7:0)
OR1(7:0) — Tx B2 Channel Timeslot
This register allows the B2 channel timeslot input to the D pin to be allocated 1 of 256 start points,
in
corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or 10 CLKs
wide. The default value for OR1 is 04H.
10.4 OR2
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR2
D
in
D Channel Timeslot Bits (7:0)
OR2(7:0) — Tx D Channel Timeslot
This register allows the D channel timeslot input to the D pin to be allocated 1 of 256 start points,
in
corresponding to each 2–bit boundary defined by the CLK. The default value for OR2 is 08H.
10–2
MC145574
MOTOROLA
10.5 OR3
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR3
D
out
B1 Channel Timeslot Bits (7:0)
OR3(7:0) — Rx B1 Channel Timeslot
This register allows the B1 channel timeslot output from the D
points, corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or
10 CLKs wide. The default value for OR3 is 00H.
pin to be allocated 1 of 256 start
out
10.6 OR4
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR4
D
out
B2 Channel Timeslot Bits (7:0)
OR4(7:0) — Rx B2 Channel Timeslot
This register allows the B2 channel timeslot output from the D
points, corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or
10 CLKs wide. The default value for OR4 is 04H.
pin to be allocated 1 of 256 start
out
10.7 OR5
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR5
OR5
D
D Channel Timeslot Bits (7:0)
out
(GCI Indirect Mode)
S2
S1
S0
OR5(7:0) — Rx D Channel Timeslot
This register allows the D channel timeslot output from the D
corresponding to each 2–bit boundary defined by the CLK. The default value for OR5 is 08H.
pin to be allocated 1 of 256 start points,
out
OR5(2:0) — GCI Timeslot, S(2:0)
In GCI indirect mode, control of the GCI timeslot is available through the S(2:0) bits. S(2:0)=0H is
the initialized state, timeslot 0. The timeslot selected must be compatible with the GCI DCL clock rate
being used; i.e., if the clock rate is 2048 kHz, only the first four timeslots are available. Bits 7:3 must
be programmed as 0.
Table 10–3. S(2:0) GCI Timeslot
Assignment
S2
S1
S0
Timeslot
0
0
0
0
1
2
3
4
5
6
7
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOTOROLA
MC145574
10–3
10.8 OR6
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR6
TSA B1
Enable
TSA B2
Enable
TSA D
Channel
Enable
D
GCI
Indirect
Mode
CLK1
CLK0
out
Open Drain
Enable
OR6(7) — Control Register, TSA B1 Enable
This bit is used to enable the B1 channel in IDL2 timeslot mode. The B1 timeslot is defined through
the OR0 and OR3 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA B1 enable is a 0, then the B1 channel
is not present on D , and the transmit data on the S/T interface is forced to all 1s and D
impedance.
is high
out
out
OR6(6) — Control Register, TSA B2 Enable
This bit is used to enable the B2 channel in IDL2 timeslot mode. The B2 timeslot is defined through
OR1 and OR4 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all chan-
nels enter timeslot mode. If in timeslot mode and TSA B2 enable is a 0, then the B2 channel is not
presentonD ,andthetransmitdataontheS/Tinterfaceisforcedtoall1sandD
ishighimpedance.
out
out
OR6(5) — Control Register, TSA D Channel Enable
This bit is used to enable the D channel in IDL2 timeslot mode. The D timeslot is defined through
the OR2 and OR5 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA D enable is a 0, then the D channel is
not present on D , and the transmit data on the S/T interface is forced to all 1s and D
impedance.
is high
out
out
OR6(3) — Control Register, D
out
Open Drain
When operating in NT Terminal mode, this bit configures the D
a 1. When this bit is set to a 0, the D
out
pin as an open drain when set to
pin goes high impedance between B and D channels.
out
OR6(2) — Control Register, GCI Indirect Mode Enable
When the device is initialized, this bit is a logic 0, the inactive state; i.e., normal IDL2 mode. When
set to a logic 1, the IDL2 port is reconfigured to behave like a GCI frame. This is called GCI indirect
mode. When GCI indirect mode has been enabled, the GCI timeslot can be selected through the S(2:0)
bits in OR5.
OR6(1:0) — Control Register, CLK(1:0)
In GCI indirect mode, these two bits control the output clock frequency of GCI DCL. CLK(1:0)=0H
is the initialized state.
Table 10–4. S(2:0) GCI Timeslot
Assignment
CLK1
CLK0
GCI DCL
2.048 MHz
2.048 MHz
1.536 MHz
512 kHz
0
0
1
1
0
1
0
1
10–4
MC145574
MOTOROLA
10.9 OR7
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
TSEN B1/B2
Enable,
BCL Enable
OR7
Disable
3 V
Regulator
Enable
S/G Bit
Enable
TCLK
Dual Frame
Syncs
Long
Frame
8/10 Bit
Select
TSEN
D Channel
Enable
OR7(7) — Control Register, Disable 3 V Regulator
This bit can be used to disable the supply regulator and allow three volts to be driven from an external
supply. This bit is reset to a logic 0 by RESET and software reset.
OR7(6) — Enable S/G Bit
This bit can be enabled only in GCI 1.536 MHz clock mode. This bit provides the availability of the
D channel on the S/T loop. 1 = Stop (no availability of the D channel), and 0 = Go (availability of the
D channel). Refer to Section 11.2.5.
OR7(5) — Control Register, Enable TCLK
This is available in TE IDL2 slave mode to enable TCLK instead of TFSC. Both TFSC and TCLK
are synchronized to the received S/T frames and can be used as a source of network synchronization
for the slave device. Refer to the section on slave–slave mode for further details.
OR7(4) — Control Register, Dual Frame Syncs
This bit controls whether the IDL2 operates with one– or two–frame syncs. When set to a logic 0,
the device operates with one–frame sync, and the FSC is the sync for both the Tx and Rx directions.
When this bit is set to a logic 1, the FST pin is activated to be the Tx frame sync, and the FSC pin
becomes the FSR (Rx frame sync). These pins will be either an input or an output depending onwhether
the IDL2 is a master or a slave. This bit is only functional in IDL2 mode. If dual frame syncs are enabled,
then TSEN cannot be enabled.
OR7(3) — Control Register, Long Frame
This bit controls whether the FSC operates in long or short frame mode, while operating as an IDL2
master. If this bit is set to a 1, then the IDL2 is in long frame mode. As an IDL2 slave, the MC145574
determines the mode, based on the length of the FS. The length of the long frame is eight bit clocks,
regardless of whether 8– or 10–bit format is selected. The long frame sync cannot be used in conjunc-
tion with timeslot assignment.
OR7(2) — Control Register, 8/10 Bit Select
When the device is initialized, this bit is a logic 0. When set to a logic 0, the IDL2 will use the 10–bit
format. When set to a logic 1, the IDL2 will use the 8–bit format. When IDL2 timeslot assigner mode
is enabled, the 8–bit mode is set and this bit has no effect.
OR7(1) — Control Register, TSEN B1/B2 Enable (IDL2), BCL Enable (GCI)
After any reset, this bit is a 0. This bit controls the operation of the TSEN/BCL pin.
IDL2: TSEN B1/B2 Enable. When this bit is set to a 1, the TSEN pin function is enabled during the
B1 and B2 bit times. The signal goes low when B1 or B2 data is present on D . This signal can
out
be used to control a bus or backplane driver. Dual frame syncs cannot be enabled when this bit is
set to a 1.
GCI: BCL Enable. When this bit is set to a 1, the BCL pin function (the 1/2 DCL clock rate signal)
is enabled. Dual frame syncs cannot be enabled when this bit is set to a 1.
OR7(0) — Control Register, TSEN D Channel Enable
When the device is initialized, this bit is logic 0. When set to a logic 1, the TSEN signal goes low
when D channel data is being output on D . This bit is only functional in IDL2 mode. If TSEN is
out
MOTOROLA
MC145574
10–5
enabled, dual frame syncs cannot be enabled. TSEN D channel signal can be enabled only if TSEN
B1/B2 channel signals are enabled (OR7(1) = 1).
10.10 OR8
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR8
Reserved
Reserved
Disable
XTAL
TE Mode
Enable
Master
Mode
Enable
FIX Enable
NT
Terminal
Mode
Sleep
Enable
Enable
OR8(7) — Reserved
This bit is reserved.
OR8(6) — Reserved
This bit is reserved.
OR8(5) — Disable XTAL
When an external 15.36 MHz is provided, this bit can be set to 1 to disable the internal crystal buffer,
thereby reducing unnecessary power consumption.
OR8(4) — Control Register, TE Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit is OR’d with the TE/NT pin and TE mode can be selected by setting this bit
to a 1.
OR8(3) — Control Register, Master Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit is OR’d with the M/S pin and the NT master bit, BR7(3), and master mode can
be selected by setting this bit to a 1.
OR8(2) — Control Register, FIX Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. In all NT modes except NT Terminal, the FIX register bit is OR’d with the FIX pin. In
NT Terminal mode, the FIX bit completely replaces the function of the FIX pin. Fixed timing mode
can be selected in NT mode by setting this bit to a 1.
OR8(1) — Control Register, NT Terminal Mode Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. NT Terminal mode can be enabled by setting this bit to 1. This bit only functions when
the device is in NT mode. NT Terminal mode allows the device to have a D channel terminal port
enabled. Refer to the section on NT Terminal mode.
OR8(0) — Control Register, Sleep Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. Please refer to the section on power modes for further operational details.
10–6
MC145574
MOTOROLA
10.11 OR9
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR9
Force
INFO2
Trans–
mission
T3F8
Enable
T3F6
Disable
OR9(2) — Control Register, Force INFO 2 Transmission
When the device is initialized, this bit is logic 0. When set to a logic 0, the device operates as normal
in all modes. This register bit is only operational in NT modes. In NT modes, the FI2 (force
INFO 2 transmission) allows the software to force an activated NT (state G3) to transmit INFO 2 and
reconfirm synchronization with the received INFO 3; i.e., the NT makes a G3 to G2 state jump, and
on attaining G2 the FI2 bit is automatically reset. The NT then reconfirms INFO 3 and returns to the
G3 state.
OR9(1) — Control Register, T3F8 Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit only operates in the TE mode. By setting this bit to 1, the T3EXP control bit
in NR2(1) is allowed to operate in F8. Hence, when in F8 and T3 expires, the device can be forced
to go to the F3 state. This is in accordance with the ETSI ETS 300012 S/T–interface specification.
OR9(0) — Control Register, T3F6 Disable
When the device is initialized, this bit is logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit only operates in the TE mode. By setting this bit to a 1, the T3EXP control bit
in NR2(1) is disabled from operating in F6. Hence, when in F6 and T3 expires, the device will not
be forced to go to the F3 state, but will stay in F6 and transition to F7 when INFO 4 is confirmed.
This is in accordance with the ETSI ETS 300012 S/T–interface specification.
10.12 OR15
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR15
Overlay
Register
Enable
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
OR15(7) — Overlay Register Enable
When set to a logic 1, the second set of overlay registers is enabled. The overlay register map allows
access to the TSA registers required by the IDL2 and also to a GCI control register.
OR15(5:0) — Device Revision Identification, Rev (5:0)
The Rev (5:0) bits indicate the revision status of the device. These bits are read only and can only
be modified by altering the device masks. Rev (5:0) is set to 11H for G20R1 mask set, and 03H for
F57J4 mask set.
MOTOROLA
MC145574
10–7
10–8
MC145574
MOTOROLA
11
D CHANNEL OPERATION
11.1 INTRODUCTION
The S/T–interface is designed for full–duplex transmission of two 64 kbps B channels and one 16 kbps
D channel between one NT device and one or more TEs. The TEs gain access to the B channels
by sending layer 2 frames to the network over the D channel. CCITT I.430, ETSI ETS 300012, and
ANSI T1.605 specify a D channel access algorithm for TEs to gain access to the D channel. The
MC145574 S/T transceiver is fully compliant with the D channel access algorithm as defined in CCITT
I.430, ETSI ETS 300012, and ANSI T1.605. The D channel operation is handled through the SCP
when using the S/T–interface either in IDL2 or GCI indirect mode, and handled through the C/I channel
when using the S/T–interface GCI direct mode.
The various bits and pins directly pertaining to D channel operation are shown in Tables 11–1 and
11–2.
Table 11–1. Channel SCP Bit Description
NT Mode
TE Mode
SCP Bit
NR2(0)
NR3(0)
Description
SCP Bit
NR2(0)
NR3(1)
Description
NT Terminal Class
Class
Interrupt on D Channel
Interrupt on D Channel Collision
Collision in NT Terminal Mode
NR4(0)
BR7(4)
BR13(2)
BR13(7)
OR8(1)
Interrupt Enable for NR3(0)
Invert the Echo Channel
Force the Echo Channel to 0
NT1 Star Mode Enable
NR4(1)
BR7(1)
BR4(4)
BR7(6)
Interrupt Enable for NR3(1)
LAPD Polarity Control
Map Echo Bits to D Timeslots on IDL2 Tx
D Channel Procedures Ignored
NT Terminal Mode Enable
Table 11–2. D Channel Operation Pin Description
Pin
IDL2 Mode
DGRANT/ANDOUT
DREQUEST/ANDIN
GCI Mode
TQFP Pin 5
SOIC Pin 8
SOIC Pin 9
GCI_SG/ANDOUT
TQFP Pin 6
TQFP Pin 7
Tie Low/DREQUEST/ANDIN
Tie Low/CLASS/ECHO IN
SOIC Pin 10 CLASS/ECHO IN
D channel data is clocked into the MC145574 via D on the falling edges of DCL. Data is clocked
in
out onto D
on the rising edges of DCL. For a detailed description of the above pins, refer to Sec-
out
tion 7. For a detailed description of the above SCP bits, refer to Sections 8 and 9.
MOTOROLA
MC145574
11–1
11.2 IDL2 D CHANNEL OPERATION
11.2.1 Gaining Access to the D Channel in the TE Mode
The pins DREQUEST and DGRANT are used in the TE mode of operation to request and grant access
to the D channel. An external device wishing to send a layer 2 frame should bring DREQUEST high,
and maintain it high for the duration of the layer 2 frame. DGRANT is an output signal used to indicate
to an external device that the D channel is clear. Note that the DGRANT signal actually goes high
one received E echo bit prior to the programmed priority class selection. DGRANT goes high at a
count of (n – 1) to accommodate the delay between the input of D channel data via the IDL2 interface
and the line transmission of those bits towards the NT. If at the time of the IDL2 SYNC pulse falling
edge, the DGRANT and the DREQUEST signals are both detected high, the TE mode transceiver
will begin FIFO buffering of the input D channel bits from the IDL2 interface. This FIFO is four bits
deep. Note that DGRANT goes high on the boundaries of the demodulated E bits. In order for the
contention algorithm to work on the D channel, HDLC data must be used. The MC145574 modulates
the D channel data onto the S/T bus in the form that it is received from the IDL2 bus. Thus, the data
must be presented to it in HDLC format. Note that one of the applications of the MC145488 DDLC
is for use with the MC145574 in the terminal mode. The MC145488 performs the HDLC conversion
and D channel handshaking.
11.2.2 Setting the Class forTE Mode of Operation
Recommendation CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications mandate two
classes of operation for a TE, with respect to D channel operation. These two classes of operation
are class 1 and class 2. Each of these classes has two associated priorities; high priority and low
priority. These classes and their associated priorities pertain to the number of demodulated E bits
required to be 1, before the D channel is deemed to be clear for use. Using the MC145574 in the
TE mode of operation, the user programs the device for class 1 or class 2 operation by either NR2(0)
or Pin 10.
Table 11–3 illustrates how to configure the MC145574 for either class 1 or class 2 operation. This
table also illustrates when DGRANT will go high. Note that although DGRANT goes high one E bit
before the required count, data will not be modulated onto the D bit timeslots in the S/T frame until
the required number of E bits = 1 are received. Thus, data gets modulated onto the D channel if the
E bit following the low–to–high transition of DGRANT is 1.
Table 11–3. MC145574 Class Operations
Number of E Bits = 1
MC145574
Required for DGRANT to Go High
Class 1
Class 2
NR2(0) = 0
and
Pin 10 = 0
DGRANT goes high after seven E bits = 1 in high
priority, and after eight in low priority
NR2(0) = 1
or
DGRANT goes high after nine E bits = 1
in high priority, and after ten in low priority
Pin 10 = 1
The device automatically switches from high to low priority and back, within each class of operation,
in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
11–2
MC145574
MOTOROLA
11.2.3 Generation of an Interrupt in the TE Mode
The MC145574 in the TE mode of operation generates an interrupt every time a collision occurs on
the D channel. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define a collision as having occurred
when the demodulated E bit from the NT does not match the previously modulated D bit from the
TE. Since the NT reflects back its received D data in the E echo channel, the TE knows that a collision
occurring indicates that another TE has gained access to the D channel. When a collision occurs
NR3(1) gets set. If the corresponding interrupt enable bit (NR4(1)) is set high, then IRQ goes low.
The D channel collision interrupt is cleared by writing a 0 to NR3(1).
11.2.4 Gaining Access to the D Channel in the NT Mode
When configured as an NT, the MC145574 has automatic access to the D channel. This is because
the S/T–interface is designed for communication between a single NT and one or more TEs. As such,
the NT does not have to compete for access to the D channel. Thus, there are no DREQUEST or
DGRANT functions associated with the NT mode of operation.
Data present in the D bit positions of the IDL2 frame on IDL2 Rx are modulated onto the D bit timeslots
on the S/T loop. Demodulated D channel data from the TE(s) is transmitted onto IDL2 Tx in accordance
with the IDL2 specification.
The ECHO function of an NT–configured S/T transceiver is performed internally in the MC145574.
To assist in testing an S/T loop, the MC145574 features the SCP test bits BR7(4) and BR13(2). Setting
BR7(4) in the NT mode inverts the E echo channel (i.e., the logical inverse of the demodulated D chan-
nel data from the TE(s) is transmitted in the E channel). Setting BR13(2) to a 1 forces the E channel
to all 0s. Refer to Section 9 for a more detailed description of these test bits. Setting BR13(7) to a
1 puts the NT–configured MC145574 S/T transceiver into the NT1 Star mode of operation. In this
mode, the bits to be ECHOed back to the TE(s) are obtained from the ECHO IN pin. Refer to Section 13
for a more detailed description of this function.
The active polarity of the DREQUEST and DGRANT signals may be reversed by setting the LAPD
polarity control bit (BR7(1)) in the SCP. When BR7(1) is a 0, the active polarity is as described above.
Conversely, when BR7(1) is a 1, the MC145574 will drive DGRANT to a logic 0 when DGRANT is
active, and to a logic 1 when DGRANT is inactive. Also, when BR7(1) is 1, DREQUEST will be consid-
ered to be active low.
11.2.5 GCI D Channel Operation
In GCI indirect mode, the D channel operation is identical to that of the IDL2.
In GCI direct mode, the DREQUEST/DGRANT/CLASS pins are replaced by C/I commands. D channel
availability is indicated by two methods using the SG nomenclature; SG meaning stop/go. The stop/go
refers to the availability of the D channel on the S/T loop. (1 = Stop and 0 = Go.)
The stop/go signal is available in two forms. In SCIT terminal mode, the stop/go bit is output by the
device in CH2 bit 4 of the C/I channel. This method is compatible with the IOM–2 terminal mode and
is also compatible with the MC68302. This mode must be enabled by selecting GCI_M(2:0) = 4H (termi-
nal mode) and writing to OR7(6) (S/G bit enable).
The stop/go signal is also available as a pin, SG, as an alternative to the SCIT terminal method.
The SCIT terminal frame structure for the T2 device is as follows.
• The remaining CH1 and CH2 channels are for use by other devices in the terminal application,
and do not form part of this specification.
• The class of message is selected using the C/I commands AR8 and AR10.
• AREOM can be used to terminate the D channel message.
MOTOROLA
MC145574
11–3
FSC
A
E
D
B1
B1
B2
B2
M
M
D CI
D CI
out
S/G BIT
A
E
D
in
CH0
CH1
CH2
SCIT TERMINAL MODE, DCL = 1536 kHz
Figure 11–1. SCIT Terminal Mode
11–4
MC145574
MOTOROLA
12
MULTIFRAMING
12.1 INTRODUCTION
A layer 1 signalling channel between the NT and TE is provided in the MC145574 in accordance with
CCITT I.430, ETSI ETS 300012, and ANSI T1.605. In the NT and TE direction, this layer 1 channel
is the S channel. In the TE to NT direction, it is the Q channel. The S channel is subdivided into five
subchannels: SC1, SC2, SC3, SC4, and SC5. In normal operation, the NT sets its Fa bit (Bit 14) to
a binary 0 every frame. The “wrapping” action of the TE(s), as outlined in CCITT I.430, ETSI ETS
300012, and ANSI T1.605, causes the Fa bit of the TE(s) to be a 0 also. This is to ensure the existence
of two line code violations per frame, enabling fast synchronization.
Multiframing is activated by the NT by setting the M bit (Bit 26) in the NT and TE frame to a binary
1, once every 20 frames. In addition to this, the Fa bit (Bit 14) in the NT to TE direction is set to a
binary 1, once every five frames. When multiframing is enabled, the NT sends its S channel data
(SC1 through SC5) in the S timeslot (Bit 37) every frame. Table 10–1 shows the order in which the
S channel data is transmitted. Note that the M bit = 1 sets the multiframe boundary. Once every five
frames, the Fa bit is set to 1 in the NT to TE direction. This serves as a Q bit identifier for the TE(s),
who send their Q data in their Fa bit position in the corresponding frames. In order to avoid Q data
collision, those TEs who have not been addressed for multiframing must send 1s in the Q bit timeslots.
12.2 ACTIVATION/DETECTION OF MULTIFRAMING IN THE MC145574
Multiframing is initiated by the NT. Detection and compliance with the multiframe structure is mandatory
in the TE(s), and is automatic in the MC145574. BR7(5) is set to 1 to initiate multiframing in an NT–con-
figured MC145574. This causes the M bit to be set to 1 in the next frame. Henceforth, the M, S, and
Fa bits will automatically comply with the structure as outlined in CCITT I.430, ETSI ETS 300012,
and ANSI T1.605. This format is as shown in Table 12–1. When the TE–configured MC145574 has
detected multiframing, it sets NR1(1) (multiframing detect). Henceforth, it automatically complies with
the multiframe format.
12.3 WRITING S CHANNEL DATA TO AN NT-CONFIGURED MC145574
Data written to BR2(7:4), BR9(7:4), BR9(3:0), BR10(7:4), and BR10(3:0) is transmitted in subchannels
SC1, SC2, SC3, SC4, and SC5, respectively. The NT–configured MC145574 polls these internal regis-
ters once every 5 ms (a multiframe is 5 ms in duration). If no new data has been written to these
registers, the old data is re–transmitted. When multiframing is disabled, the data in these registers
is ignored and the Fa bit is 0. Note that in the NT mode, these registers come out of reset in the all–0s
state.
MOTOROLA
MC145574
12–1
Table 12–1. S Channel Data Transmission
NT to TE
Fa Bit Position
NT to TE
M Bit
NT to TE
S Bit
TE to NT
Fa Bit Position
Frame No.
1
2
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
SC1.1
SC2.1
SC3.1
SC4.1
SC5.1
SC1.2
SC2.2
SC3.2
SC4.2
SC5.2
SC1.3
SC2.3
SC3.3
SC4.3
SC5.3
SC1.4
SC2.4
SC3.4
SC4.4
SC5.4
SC1.1
SC2.1
Q1
0
3
0
4
0
5
0
6
Q2
0
7
8
0
9
0
10
11
12
13
14
15
16
17
18
19
20
1
0
Q3
0
0
0
0
Q4
0
0
0
0
Q1
0
2
12.4 MULTIFRAME INTERRUPTS IN AN NT-CONFIGURED MC145574
The NT will generate an interrupt either once every multiframe, or only in the event of a new Q channel
nibble having been received. A new Q channel nibble is defined as one which differs from the previous
Q nibble.
Table 12–2 illustrates how to configure an NT for either of these options.
Table 12–2. Multiframe Interrupts
BR3(2)
Interrupt Every
Multiframe
NR4(2)
Enable Multiframing
Interrupt
IRQ
MC145574
X
0
0
1
Multiframing never causes an interrupt
An interrupt is generated on the reception of a
new Q Channel nibble
1
1
An interrupt is generated every multiframe
12–2
MC145574
MOTOROLA
12.5 READING Q CHANNEL DATA FROM AN NT-CONFIGURED MC145574
The Q data nibble received from the TE(s) is obtained by reading BR3(7:4). The demodulated Q chan-
nel data is written to this register every 5 ms. BR3(7:4) are read only bits.
12.6 WRITING Q CHANNEL DATA TO A TE-CONFIGURED MC145574
Data written to BR2(7:4) is transmitted in the Q channel. The TE–configured MC145574 polls this
internal register once every 5 ms (a multiframe is 5 ms in duration). If no new data has been written
to this register, the old data is re–transmitted. When multiframing is disabled, the data in this register
is ignored and the Fa bit obeys the multiframing wrapping criteria as outlined in CCITT I.430, ETSI
ETS 300012, and ANSI T1.605.
BR2(7:4) comes out of reset in the all–1s state in the TE mode of operation. To accommodate other
TEs on the loop, BR2(7:4) should be left in the all–1s state when the TE does not have access to
the Q channel.
12.7 MULTIFRAME INTERRUPTS IN A TE-CONFIGURED MC145574
The TE will generate an interrupt either once every multiframe or only in the event of a new SC1 sub-
channel nibble having been received. A new SC1 subchannel nibble is defined as one which differs
from the previous SC1 nibble. Table 12–3 illustrates how to configure a TE for either of these options.
Table 12–3. TE Multiframe Interrupts
BR3(2)
Interrupt Every
Multiframe
NR4(2)
Enable Multiframing
Interrupt
IRQ
MC145574
X
0
0
1
Multiframing never causes an interrupt
An interrupt is generated on the reception of a
new SC1 subchannel nibble
1
1
An interrupt is generated every multiframe
12.8 READING S SUBCHANNEL DATA FROM A TE-CONFIGURED
MC145574
The S subchannel nibbles SC1, SC2, SC3, SC4, and SC5 received from the NT are obtained by reading
BR3(7:4), BR9(7:4), BR9(3:0), BR10(7:4), and BR10(3:0), respectively. The demodulated S subchan-
nel data is written to these registers every 5 ms. These registers are read only registers in the TE
mode of operation.
12.9 MULTIFRAMING IN GCI MODE
Multiframing can be enabled in GCI mode by writing/reading to BR7(5) via the Monitor channel.
MOTOROLA
MC145574
12–3
12–4
MC145574
MOTOROLA
13
DEVICE CONFIGURATIONS
The MC145574 can be configured in several different modes for different applications. The following
sections describe the various configurations available for the NT and TE modes.
13.1 NT CONFIGURATIONS
To select NT mode, the TE/NT pin must be held low. The NT device can operate in a mixture of different
configurations. How each aspect of the NT’s operation is selected is discussed separately in the follow-
ing sections. However, for a broad view of the NT’s various flavors, the NT family tree is shown in
Figure 13–1.
NT
FIXED TIMING
ADAPTIVE TIMING
MASTER
SLAVE
MASTER
SLAVE
NT1 STAR
NT TERMINAL NT1 STAR
NT TERMINAL NT1 STAR
NT TERMINAL NT1 STAR
NT TERMINAL
NT (NORMAL MODE)
NT (NORMAL MODE)
NT (NORMAL MODE)
NT (NORMAL MODE)
Figure 13–1. NT Family Tree
13.1.1 NT Fixed or Adaptive Timing
The receiver/demodulator of the NT can operate in two different modes depending on the type of
loop that the device is connected to. These modes are called fixed and adaptive timing modes. The
mode of operation is chosen by the state of Pin 6. When this pin is held low the device is in adaptive
mode, and when held high the device is in fixed timing mode. The choice of mode is dependent on
the loop characteristics, and the intention is that fixed timing should be used for short passive bus
configurations and adaptive timing used for all others. However, the performance of the timing recovery
circuit employed in the MC145474/75, and also in the MC145574, allows the use of adaptive timing
in all loop configurations. Thus, it is recommended that adaptive timing be used in all configurations.
It is also possible to select fixed timing mode via the SCP/GCI control bit OR8(2). The FIX pin is inter-
nally OR’d with this SCP/GCI bit, and one should note that in the NT Terminal mode, this is the only
way to select fixed timing. The FIX pin should be held low if register programming is to be used.
13.1.2 NT Master or Slave
In NT mode, the IDL2/GCI interface can be selected either as a master or a slave. This selection
is done via Pin 5. When Pin 5 is held low, slave mode is selected. When it is held high, master mode
is selected.
MOTOROLA
MC145574
13–1
In slave mode, the IDL2/GCI interface frame sync and clock are inputs, and the S/T loop interface
timing is slaved to these inputs. In master mode, the IDL2/GCI interface frame sync and clock are
outputs; these signals being derived from the 15.36 MHz XTAL oscillator. The S/T loop interface timing,
however, is always slaved to the IDL2/GCI frame sync.
Therefore, in NT mode, the S/T loop interface timing is always slaved to the IDL2/GCI frame sync.
The source of this timing can be selected to be from the IDL2/GCI driver (slave mode) or from the
NT device itself (master mode).
NT master mode will be referred to as NTM, and NT slave mode as NTS.
It is also possible to select NTM by writing to the SCP control bit BR7(3). Or alternatively in TE or
NT mode, master selection can be made via OR8(3). The master/slave pin is internally OR’d with
these SCP bits and should be held low if register is to be used.
13.1.3
NT1 Star and NT Terminal Modes
In NT mode, two further mode extensions can be selected via control bits accessible through the SCP.
These NT mode extensions have no effect on the IDL2 interface, but alter the operation of other pins
to perform the desired functions. These two modes are called NT1 Star and NT Terminal.
Table 13–1. Pin Operations
Pin
NT
NT1 Star
NT Terminal
T_IN
TQFP Pin 3
TQFP Pin 5
TQFP Pin 6
TQFP Pin 7
SOIC Pin 6
FIX
FIX
SOIC Pin 8
SOIC Pin 9
SOIC Pin 10
High–Z
ANDOUT
ANDIN
DGRANT
DREQUEST
CLASS
Tie–Low
Tie–Low
ECHO IN
13.1.3.1
NT1 Star Mode
Appendix B of ANSI T1.605 describes an example of an NT that will support multiple T interfaces.
This is to accommodate multipoint operation with more than eight TEs. The MC145574 can be config-
ured for NT1 Star mode of operation. This mode is for use in wire OR’ing multiple NT–configured
S/T chips on the IDL2 side. Each NT has a common FSC, DCL, D , and D , as shown in Figure
out in
13–2. Each NT is then connected to its own individual S/T loop containing either a single TE or a
group of TEs. As such, the contention for either of the B channels or for the D channel is now extended
from a single passive bus to a grouping of passive busses.
ISDN employs the use of HDLC data on the D channel. Access to either of the B channels is requested
and either granted or denied by the user sending layer 2 frames on the D channel. In normal operation
where there is only one NT, the TEs are granted access to the D channel in accordance with their
priority and class. By counting the required number of E channel echo bits being 1, the TEs know
when the D channel is clear. Thus, in the NT1 Star mode of operation, where there are multiple passive
busses competing for the same B1, B2, and D channels, the same E echo channel must be transmitted
from each NT to its passive bus. This is accomplished in the MC145574 by means of the ANDIN,
ANDOUT, and ECHO IN pins.
Figure 13–2 shows how to connect the multiple number of NTs in the NT1 Star mode. Successive
connection of the ANDOUT (this is the output of an internal AND gate whose inputs are the demodu-
lated D bits and the data on the ANDIN pin) and ANDIN pins, and the common connections of the
ECHO IN pins, succeeds in sending the same E echo channel to each group of TE(s). To configure
a series of NTs for NT1 Star mode, BR13(7) must be set to 1 in each NT. Data transmitted on Tx
in NT1 Star mode will have the following format: a logic 0 is V ; a logic 1 causes D
high–impedance state. This then permits the series wire OR’ing of the IDL2 bus. Note that one of
the NTs must have its ANDIN pin pulled high.
to go to a
SS out
NT1 Star mode is not applicable to the NT using the GCI interface.
13–2
MC145574
MOTOROLA
+ 5 V
+ 5 V
IC #1
MC145574
ANDIN
DEMODULATED
D CHANNEL DATA
ANDOUT
DATA TO BE TRANSMITTED TO TEs
AS E CHANNEL DATA
ECHOIN
FSC
FSC
DCL
DCL
D
in
D
out
D
in
out
D
IC #2
MC145574
ANDIN
DEMODULATED
D CHANNEL DATA
ANDOUT
DATA TO BE TRANSMITTED TO TEs
AS E CHANNEL DATA
ECHOIN
FSC
DCL
D
in
D
out
IC #N
MC145574
ANDIN
DEMODULATED
D CHANNEL DATA
ANDOUT
DATA TO BE TRANSMITTED TO TEs
AS E CHANNEL DATA
ECHOIN
FSC
DCL
D
in
D
out
Figure 13–2. NT1 Star Mode of Operation
MOTOROLA
MC145574
13–3
13.1.3.2
NT Terminal Mode
In NT Terminal mode, another IDL2 channel data port is opened on the device. This port has four
pins associated with it. They are DREQUEST, DGRANT, CLASS, and T_IN.
This port has the capability of competing for access to the D channel with the TEs connected to the
passive bus. To do this, the DREQUEST, DGRANT, and CLASS functions normally associated with
the TE are enabled. This allows an external controlling device to request access to the D channel,
and if the D channel is idle, be given access. The NT device monitors the received S/T loop D bits
to determine whether the channel is busy or not (a TE device would monitor the E bits).
Once the controlling device has been given access to the D channel, the MC145574 indicates this
by setting DGRANT high and enabling the D slot on the T_IN pin.
The NT device ANDs the received D bits from the S/T loop with D channel data received from the
T_IN pin, and transmits this as the E bit on the S/T loop. The AND’d data is then passed to the D
for output.
out
DGRANT is high when the S/T is not activated.
Contention is monitored by comparing the transmitted E bit to the D channel data from the T_IN pin.
If they are not equal then contention from a device on the S/T loop is assumed, and the D channel
access halted. An interrupt IRQ7, NR3(0), is generated to indicate contention has occurred.
The T_IN pin also accepts data on the B1 and B2 slots. This data is AND’d with the received B1 and
B2 data from the S/T–interface and then output on the D
to detect data collision on the B channels. (The B channels are enabled by default.)
pin. There is no provision on the device
out
The T_IN IDL2 port is synchronized to the normal IDL2 port by FSC, and the DCL clock is used to
sample the T_IN pin. NT Terminal mode operates in all the IDL2 modes, including TSA and dual frame
sync modes.
When the D
is needed.
pin is configured as an open drain output, a pullup resistor (between 1 k and 10 k)
out
The T_IN port has the same format as the IDL2 or GCI that is being used.
Data can be input to the T_IN pin when the MC145574 is either activated or deactivated. NT Terminal
mode operates when the MC145574 is either activated or deactivated.
13.2 TE CONFIGURATIONS
To select TE mode, Pin 4 (TE/NT) must be held high, or alternatively, by writing to the SCP control
bit OR8(4). This bit is internally OR’d with the TE/NT pin. In TE mode, the device operates in two
different configurations, these configurations being TE slave (TES) and TE master (TEM).
The selection of slave or master is accomplished via Pin 5. When held low, slave mode is selected;
and when held high, master mode is selected.
Each mode is discussed separately in the following sections; however, certain shared pins have differ-
ent functions in TES and TEM mode. (See Table 13–2.)
Table 13–2. Pin Operations for Master and Slave
Modes
Pin
TEM
TES
TFSC/TCLK
High–Z
TQFP Pin 3
TQFP Pin 5
TQFP Pin 6
TQFP Pin 7
SOIC Pin 6
High–Z
SOIC Pin 8
SOIC Pin 9
SOIC Pin 10
DGRANT
DREQUEST
CLASS
Tie V
Tie V
SS
SS
There is no fixed/adaptive timing selection to be made in TE mode. In TE mode, the MC145574 always
uses adaptive timing.
13–4
MC145574
MOTOROLA
13.2.1 TE Master Mode (TEM)
The TEM mode is the normal mode of operation for a TE. The two main operational features of TEM
mode are as follows.
The IDL2/GCI is a master of the digital interface. This means that the IDL2/GCI outputs the frame
sync and clock. The frame sync and clock are signals derived from the received S/T loop signal (i.e.,
timing is recovered from the received INFO transmitted by the NT and is used to generate the IDL2
signals so the TE end can operate synchronously with the NT).
The D channel access procedure outlined in the ANSI spec is enabled. This means that access to
the D channel is controlled via a set of rules designed to enable secure HDLC data transmission on
a shared channel, and provides a means for the TEM to recognize when collisions have occurred.
This operation is fully detailed in Section 11, D Channel Operation.
The three pins used to control the D channel access are DREQUEST, DGRANT, and CLASS.
13.2.2 TE Slave Mode (TES)
In TES mode, the IDL2/GCI interface operates in slave mode; i.e., the IDL2/GCI frame sync and clock
are inputs. This mode is intended for use in NT2 applications where the IDL2/GCI interface timing
is derived from a low jitter network synchronous source. The MC145574 has jitter/wander buffers which
absorb the clock/frame sync jitter and prevent data loss. The MC145574 will be able to absorb 60 µs
peak–to–peak wander, which exceeds the 18 µs peak–to–peak over 24 hours wander stated in Q.502.
There is no D channel contention circuitry in TES mode. The device has transparent access to the
D channel. It is intended that the TES operates in point–to–point applications only and thus does not
need D channel contention arbitration.
To facilitate the generation of the timing signals required by the slave IDL2/GCI interface, a pin is
provided which outputs a frame sync or a clock. These signals are synchronized to the received INFO
transmitted by the NT and can be used to provide network timing if no other source in the NT2 is
available. The choice of frame sync or clock and the frequency of the clock are all selectable via the
SCP.
The TFSC output is to allow the NT2 to be synchronized to the network. The TFSC is an 8 kHz frame
sync signal that is synchronized to the received network signal.
Alternatively, TFSC can be reprogrammed via the SCP to provide TCLK. TCLK is a clock, whose fre-
quency can be chosen via the SCP, which is also synchronized to the received S/T–interface. TCLK
can be used as an alternative to TFSC in NT2 slave–slave mode. The frequency of TCLK is selected
in the same manner as the DCL frequency is selected in the TE master mode.
In both the TFSC and TCLK cases, the output pin senses if a signal is present; and if not, the output
is enabled and the device outputs its signal. This allows the TES devices to have this pin wire OR’d
with only one of the active devices outputting the sync clock. For this function to work correctly, the
pin must have an external resistor connected to V
I/O.
DD
BR13(5)
BR7(2)
TCLK
0
0
1
1
0
1
0
1
2.56 MHz
2.048 MHz
1.536 MHz
512 kHz
MOTOROLA
MC145574
13–5
An example architecture of an NT2 is shown in Figure 13–3. The TFSC signal supplied by the TE
in slave mode is used via a clocksource selector to synchronize the whole NT2 to the network.
NT
NT
NT
TE
TE
TE
TFSC
CLK
FSC SOURCE
SELECTOR
CLK
S
S
S
T
T
T
SYNC
SYNC
DATA
SYNC AND CLOCK
GENERATOR
DATA
TSA CONTROLLER
TFSC
CLK
CLK
SYNC
DATA
SYNC
DATA
CONTROL
BUS
TFSC
CLK
CLK
SYNC
CLK
FRAME SYNC
SYNC
DATA
DATA
NT
TFSC TE
CLK
CLK
S
T
SYNC
DATA
SYNC
DATA
SUBSCRIBER
LINES
S–INTERFACE
TRUNK LINES
TO CENTRAL OFFICE(S)
T–INTERFACE
Figure 13–3. NT2 Architecture
13–6
MC145574
MOTOROLA
14
CLOCK INTERFACE
Figure 14–1 shows the recommended crystal oscillator for connection to the MC145574.
XTAL
33 pF
15.36 MHz
(AT CUT
10 M
QUARTZ CRYSTAL)
—60/+ 100 ppm
TOLERANCE
V
SS
EXTAL
33 pF
V
SS
Figure 14–1. Typical Crystal Oscillator Connection
Figure 14–2 shows the connection when using an external clock.
15.36 MHz
EXTERNAL CLOCK
(COULD BE THE MC145572
OUTPUT IN THE NT1)
XTAL
EXTAL
OPEN CIRCUIT
Figure 14–2. Connection with External Clock
MOTOROLA
MC145574
14–1
14–2
MC145574
MOTOROLA
15
INTERRUPTS
15.1 INTRODUCTION
When the MC145574 in SCP is configured as a TE, it has three interrupt modes. When the MC145574
is configured as an NT, it has four interrupt modes. Each of these interrupts is maskable. When an
interrupt occurs (and if the interrupt condition is enabled), the MC145574 asserts the IRQ pin. A detailed
description of these interrupts, and how they are cleared, follows.
15.2 IRQ7 NR3(0) Ċ NT : D CHANNEL COLLISION
TE : NOT APPLICABLE
NR4(0) Ċ ENABLE
IRQ7 is used in the NT Terminal mode of the MC145574 to indicate that a collision has occurred on
the D channel. This bit operates in the same manner as the IRQ1 interrupt in TE mode, and likewise
is cleared by writing a 0 to the NR3(0) bit. This action also releases the IRQ pin.
Note that this bit is maskable by means of NR4(0). This interrupt is only applicable in the NT mode
and is therefore not available in the TE mode.
15.3 IRQ1 NR3(1) Ċ TE: D CHANNEL COLLISION
NT: NOT APPLICABLE
NR4(1) Ċ ENABLE
IRQ1 is used in the TE mode of operation of the MC145574 to indicate to external devices that a
collision has occurred on the D channel. A D channel collision is considered to have occurred when
the TE is transmitting on the D channel (both DREQUEST and DGRANT being high) and the received
E echo bit from the NT does not match the previously modulated D bit. When IRQ1 occurs, the
MC145574 internally sets NR3(1) to a 1. If the IRQ1 ENABLE is set to 1, an interrupt to an external
device is generated. The interrupt condition is cleared by writing a 0 to NR3(1). Note that this bit is
maskable by means of NR4(1). This interrupt is only applicable in the TE mode and is therefore not
available in the NT mode.
15.4 IRQ2 NR3(2) Ċ MULTIFRAME RECEPTION
NR4(2) Ċ ENABLE
IRQ2 is provided for multiframing reception indication. This interrupt is applicable and available in
both NT and TE modes of operation of the MC145574. Note that this interrupt is maskable by means
of NR4(2). Multiframing is initiated by the NT by setting BR7(5). A multiframe is 20 basic frames, or
5 ms in duration. If this interrupt is enabled (it is enabled by setting NR4(2)) and if multiframing is
in progress, then an interrupt is generated on multiframe boundaries; i.e., every 5 ms. Alternatively,
an NT–configured MC145574 can be programmed to generate an interrupt only in the event of a new
Q channel nibble having been received. Similarly, a TE–configured MC145574 can be programmed
to generate an interrupt only in the event of a new SC1 subchannel having been received. Refer to
Section 12 for a detailed description of these features.
If an interrupt is to occur, it will do so in the 47th baud of the transmitted frame of the 20th frame
in a multiframe. Data to be transmitted in the SC1 through SC5 subchannels in the NT is internally
latched from BR2(7:4), BR9(7:0), and BR10(7:0) during the 47th baud of the transmitted frame of
the 20th frame in a multiframe. At this time, the received Q channel nibble is made available by internally
MOTOROLA
MC145574
15–1
latching the data to BR3(7:4). Similarly, data to be transmitted in the Q channel of the TE is internally
latched from BR2(7:4) during the 47th baud of the transmitted INFO 3 in the 20th frame of a multiframe.
At this time, the received SC1 through SC5 subchannel nibbles is also made available. A mutiframing
interrupt is cleared by reading BR3. Reading BR3 clears the interrupt in both the NT and TE modes
of operation, regardless of whether the MC145574 is configured to generate an interrupt in the event
of a new nibble or every multiframe. Note that NR3(2) is a read only bit.
15.5 IRQ3 NR3(3) Ċ CHANGE IN RxINFO STATE
NR4(3) Ċ ENABLE
IRQ3 is provided to indicate a change in the received INFO state of the transceiver. In the NT mode,
this corresponds to a change in the receiving INFO 0, INFO 1, INFO 3, or INFO X state. Alternatively,
in the TE mode this corresponds to a change in the receiving INFO 0, INFO 2, INFO 4, or INFO X
state. Thus, when a change occurs in one of these states, the MC145574 internally sets NR3(3) to
a 1. If the IRQ3 ENABLE is set to 1, an interrupt to an external device will be generated. IRQ3 can
be cleared by writing a 0 to NR3(3). This bit is reset by a software reset or a hardware reset. Note
that the transmission states for the NT (INFO 0, INFO 2, and INFO 4) and for the TE (INFO 0, INFO 1,
and INFO 3) are as defined in Section 3. INFO X is defined as any transmission state other than those
states. An example of such a state would be when the MC145574 is programmed to transmit a 96 kHz
test signal (BR11(0) = 1). The MC145574 comes out of reset in the receiving “INFO X” state. Hence,
IRQ3 will be generated when it recognizes either INFO 0, INFO 1, INFO 2, INFO 3, or INFO 4. Note
that NR3(3) is a read/write bit.
As soon as INFO 0, INFO LOW (1 or 2), or INFO HIGH (3 or 4) is detected, an interrupt is generated.
If the INFO X state persists for > 8 ms, then an INFO X interrupt is generated.
15.6 IRQ6 NR3(1) Ċ NT : FAR-END CODE VIOLATION (FECV)
DETECTION
TE : NOT APPLICABLE
NR4(1) Ċ ENABLE
The interrupt request condition IRQ6 is generated when the NT has detected a far–end code violation
(FECV). An FECV occurs when a multiframe incoming to the NT from the TE(s) contains one or more
illegal S/T line code violations. This interrupt is used to indicate to an NT when to send an FECV
layer 1 maintenance message to the TEs as defined in ANSI T1.605. When IRQ6 occurs, the
MC145574 internally sets NR3(1) to a 1. If the IRQ6 ENABLE is set to 1, an interrupt to an external
device will be generated. The interrupt condition is cleared by writing a 0 to NR3(1).
Note that this bit is maskable by means of NR4(1). This interrupt is applicable in the NT mode of opera-
tion and only when multiframing has been enabled.
15.7 GCI MODE
In GCI mode, a Monitor channel message is output by the MC145574 if an equivalent SCP interrupt
condition has occurred. This message must be enabled by writing to the NR4 register (via the Monitor
channel). The Monitor channel message that occurs in response to an interrupt condition contains
the content of NR3.
15–2
MC145574
MOTOROLA
16
TRANSMISSION LINE INTERFACE CIRCUITRY
16.1 INTRODUCTION
The MC145574 is an ISDN S/T transceiver fully compliant with CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. As such, it is designed to interface with a four–wire transmission medium, one pair being
the transmit path, the other pair the receive path. TxP and TxN, a fully–differential output transmit
pair from the MC145574, are designed to interface to the transmit pair of the transmission medium
via auxiliary discrete components and a 1:2.5 turns ratio transformer. RxP and RxN are a high–imped-
ance differential input pair used for coupling the receive line signal through a 1:2.5 turns ratio transform-
er.
16.2 TRANSMIT LINE INTERFACE CIRCUITRY
The TxP and TxN pins on the MC145574 act as a current–limited differential voltage source pair. The
TxP and TxN pair behave as active drivers when creating logical 0 line signals (CCITT I.430, ETSI
ETS 300012, and ANSI T1.605 define the nominal pulse amplitude to be 750 mV, zero to peak, for
a 50 Ω load), and are high–impedance outputs when generating logical 1 signals. The transmit circuitry
within the S/T transceiver is designed to operate with a 1:2.5 turns ratio line interface transformer.
The transmit transformer is similar in design to the receive transformer.
The TxP and TxN pair operate as a 2.8 V current–limited differential voltage source on the device
side (1.12 V on the S/T loop side). As such, two 5% series resistors should be inserted in the line
interface circuit so that the combined resistance of these two resistors and the winding resistance
of the transformer is 145 Ω. The current limit value is set by circuitry within the S/T transceiver and
is approximately 9 mA.
The TxP and TxN transmit pair supplies a current such that a positive potential is created between
the TxP and TxN pins, respectively, when transmitting the F frame bit of each frame. The TxP and
TxN line drive circuit of the MC145574 S/T transceiver is designed such that the device continues
to provide a high–impedance circuit to the transmit pair of the S/T loop when power is removed (i.e.,
when the circuit between V
mended line interface and protection circuitry for interfacing the MC145574 to the S/T loop.
and V
becomes a short circuit). Figure 16–1 illustrates the recom-
DD
SS
16.3 RECEIVE LINE INTERFACE CIRCUITRY
The RxP and RxN pins serve as a fully–differential input pair for the line signal from the S/T loop.
The input impedance seen looking into the combination of the MC145574 and the associated receive
line interface circuitry (as shown in Figure 16–2) exceeds the CCITT I.430, ETSI ETS 300012, and
ANSI T1.605 requirements under all conditions. The receive line circuitry within the MC145574 S/T
transceiver is designed to operate with a 1:2.5 turns ratio transformer. The receive transformer is similar
in design to the transmit transformer and a list of suppliers of these transformers are included.
The receive circuitry within the MC145574 automatically adapts to the optimum ternary detection
thresholds for receiving the incoming line signal, regardless of the S/T loop bus configuration. The
minimum ternary detection threshold is 90 mV, referenced to signal ground. This value then sets the
absolute maximum attenuation that can exist, before detection of the incoming signal becomes impos-
sible. The RxP and RxN pair are not sensitive to the polarity of their connection to the line interface
circuitry. Figure 16–2 illustrates the recommended line interface and protection circuitry for interfacing
the MC145574 S/T transceiver to the loop.
MOTOROLA
MC145574
16–1
V
DD
MC145574
THESE FOUR DIODES ARE
OPTIONAL IN NT MODE.
68 Ω 5%
68 Ω 5%
2.5:1
1
8
6
2
4
7
5
TxP
100 Ω
TERMINATION
TxN
T2
3
PE65857
FOR EMI SUPPRESSION
Figure 16–1. Transmit Line Interface Circuit
V
DD
MC145574
THESE FOUR DIODES ARE
OPTIONAL IN NT MODE.
5.1 kΩ 5%
2.5:1
1
8
6
2
4
7
5
RxP
100 Ω
TERMINATION
5.1 kΩ 5%
RxN
T1
3
PE65857
FOR EMI SUPPRESSION
NOTES:
1. Diodes are 1N4148 or MMAD1108.
2. The MMAD1108 is a monolithic array of eight diodes and is a Motorola preferred device.
3. All resistors are 1/4 watt.
Figure 16–2. Receive Line Interface Circuit
16–2
MC145574
MOTOROLA
16.4 ADDITIONAL NOTES
16.4.1 Sources of Line Interface Transformers
Line interface transformers for use with the MC145574 S/T may be obtained from the following
manufacturers:
Pulse Engineering
Secre Composants
P.O. Box 12235
117, rue de Cambrai
75019 Paris, France
Tel : (331) 44–89–48–00
Fax : (331) 42–05–15–19
Part # E01170, E01167
Part # E01171 (SMD)
San Diego, California 92112
Tel : 619–674–8100
Fax : 619–674–8262
Part # PE 64998 (single)
Part # PE 65498 (dual)
FEE S.A.
APC
Zone Industrielle
39270 Orgelet
France
47 Riverside, Medway City Estate
Strood, Rochester, Kent ME2 4DP
United Kingdom
Tel: (33) 84–35–04–04
Fax: (33) 84–25–46–41
Part # FE2150
Tel: (44) 1634–290–588
Fax: (44) 1634–290–591
Part # APC15103
Motorola cannot recommend one manufacturer over another and in no way implies that this is a com-
plete listing.
16.4.2 Termination Resistors
Note that the 100 Ω termination resistors in the transmit and receive line circuitry (as shown in Fig-
ures 16–1 and 16–2) are mandatory when operating as an NT in accordance with CCITT I.430, ETSI
ETS 300012, and ANSI T1.605. When operating as a TE in point–to–point mode, these are also re-
quired. However, when configured as a TE in the passive bus arrangement, only one TE has these
termination resistors. The 100 Ω termination resistor should also be removed for some conformance
tests.
16.4.3
Protection Diodes
CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specify that the S/T–interface voltage cannot exceed
1.6 times the nominal voltage of 750 mV (= 1.2 V). Since the MC145574 is designed to operate with
2.5:1 turns ratio transformers, the diode structure as illustrated in Figures 16–1 and 16–2 is required
to provide protection, while not adversely affecting the S/T–interface when power is removed from
the device. This diode structure also protects the circuit against electrostatic discharges (ESD) and
latch–up.
CAUTION
The four pins RxP, RxN, TxP, and TxN are not internally protected against ESD and caution
must be taken during handling and mounting the devices to prevent any possible electrical
overstress.
MOTOROLA
MC145574
16–3
16–4
MC145574
MOTOROLA
17
POWER MODE OPERATION
17.1 POWER SUPPLY STRATEGY
The MC145574 operates from a 5 V ± 5% supply. The MC145574 has an on–chip linear regulator.
This regulator has an output of 3.2 V. This regulated 3 V supply powers all of the internal digital logic,
resulting in reduced power consumption. The analog receiver/transmitter blocks are powered from
the 5 V supply.
The 3 V regulated output is present on the V 3 pin. A capacitor of 100 nF should be connected
DD
between this pin and V
SS
to provide filtering for the internal regulator.
If a more efficient 3 V supply is available in the application circuit, then the V 3 pin can be driven
DD
directly with this external supply. The internal 3 V regulator should then be disabled via the SCP to
gain a further improvement in device power consumption. This can be achieved by setting OR7(7).
The 5 V supply is still required when an external 3 V supply is being used.
The digital output drivers have a separate +ve supply pin, V
I/O. This pin should be connected to
DD
5 if 5 V output drivers are required, or the V 3 pin if 3 V output drivers are required. This option
V
DD
DD
allows the device to be easily interfaced to 3 V or 5 V CMOS or TTL devices. Using 3 V drivers will
give reduced power consumption while still being able to interface to 3 V CMOS and TTL devices.
All the digital inputs operate from the 3 V regulated supply (V 3) and are TTL and CMOS compatible.
DD
The input ESD protection is connected to V 5 (the 5 V supply) ensuring that the inputs are compatible
DD
with 3 V or 5 V CMOS and TTL input levels.
The 15.36 MHz crystal oscillator is powered from the 3 V regulated supply (V 3) to minimize its
DD
power consumption. The XTAL oscillator circuit can be disabled via the SCP control bit (OR8(5)) if
an external 15.36 MHz clock source is available, further improving power consumption.
17.2 POWER MODES
The MC145574 has four distinct modes in which the maximum power consumption of the device is
specified.
17.2.1 Normal Operation
In this mode, the device is free to operate and activate or be activated from the S/T–interface.
In this mode, the device consumes the maximum power when it is forced to transmit the 96 kHz test
signal into the correctly terminated (50 Ω) interface circuit. The receiver should also be receiving a
96 kHz test signal.
17.2.2 Transmit Power-Down
In this mode, the device has its transmit circuitry powered down. This is achieved by setting the NR0(2)
in the SCP. The receiver is still fully active and able to respond to S/T–interface initiated activation.
The power consumption is measured with RxINFO = INFO 0. This mode can be entered or exited
in SCP or GCI mode.
MOTOROLA
MC145574
17–1
17.2.3 Absolute Minimum Power
In this mode, the device is forced into the absolute minimum power state from which it cannot be
activated from the S/T–interface. All internal circuits are disabled, including the XTAL oscillator, and
only the SCP interface remains functional. All possible power consumption in the Tx and Rx analog
circuitry is blocked.
In IDL2/SCP mode, this power mode is entered/exited by writing to the NR0(1) register in the SCP.
In GCI mode, this power reduction mode is not available.
The characteristics of this mode are identical to that in the MC145474 except for the XTAL oscillator,
which is disabled in the MC145574.
17.2.4 Sleep
In this mode, the device is in a power conservation mode where all possible power consuming circuitry
is switched off, including the XTAL OSC.
In SCP mode, the sleep mode is enabled by writing to OR8(0). When the device goes into the sleep
state, only the SCP and an energy detector with receiver remain operational.
In GCI mode, the sleep mode is enabled by default. The sleep mode can be disabled by writing the
OR8(0) via the Monitor channel. When the device goes into the sleep state, only the GCI interface
and an energy detector in the receiver remains operational. Sleep mode is not available with NT master
GCI/SCP configuration.
In both SCP and GCI modes, the device will enter the sleep state (assuming sleep mode is enabled)
when the MC145574 detects no activity on the S/T–interface and is in the deactivated state. A timer
is then enabled which will cause the MC145574 to enter the sleep state after a period of 2 ms.
The sleep state is exited when a signal is detected on the S/T–interface. In this case, the device exits
sleep mode and tries to synchronize to the signal. If successful, the device activates in the normal
function. The sleep state can also be exited by writing an activate request via the SCP. This cause
the device to exit the sleep state and attempt to activate in the normal function.
In GCI slave mode, the sleep state is exited by using the AR command on the C/I channel.
In GCI master mode (TE master only), the sleep mode is exited by first pulling the D pin low to request
in
that the GCI clock starts, and then issuing the TIM command (if only the GCI interface is to be activated),
or by issuing the AR command if an activation is to be attempted.
When the MC145574 enters the sleep state, the crystal oscillator is disabled, i.e., stopped.
17–2
MC145574
MOTOROLA
18
ELECTRICAL SPECIFICATIONS
18.1 MAXIMUM RATINGS
This device contains circuitry to protect the inputs against damage due to high static voltages or electri-
cal fields; however, it is advised that normal precautions be taken to avoid applications of any voltage
higher than maximum rated voltages to this high–impedance circuit. For proper operation, it is recom-
mendedthatV andV beconstrainedintherangeV ≤(V orV )≥V 5.Reliabilityofoperation
in out SS in out DD
is enhanced if unused inputs are tied to an appropriate logic voltage (e.g., either V
SS
or V 5). All
DD
of the reliability data and the ESD results are available on request from your local sales office or your
nearest distributor.
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Supply Voltage
Input Voltage (Any Pin to V
Value
Unit
V
V
DD
5
– 0.5 to + 7
V
in
)
SS
– 0.3 to V 5 + 0.3
DD
V
I
DC Current (Any Pin Excluding V 5,
DD
± 10
mA
V
I/O, V 3, V , TxP, and TxN)
DD
DD SS
T
Operating Temperature Range
Storage Temperature Range
– 40 to + 85
°C
°C
A
T
stg
– 85 to + 150
NOTE: MaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.
Functional operation should be restricted to the limits in the Electrical Characteris-
tics tables or Pin Description section.
18.2 DIGITAL DC ELECTRICAL CHARACTERISTICS
(T = – 40 to + 85°C, V 5 = 5.0 V ± 5%, Voltages Referenced to V
)
SS
A
DD
Characteristic
Symbol
Min
2.0
—
Max
—
Unit
V
Input High Voltage
Input Low Voltage
V
IH
V
IL
0.8
5
V
Input Leakage Current @ 5.25 V
High Impedance Input Current @ 4.5/0.5 V
Input Capacitance
l
in
—
µA
µA
pF
V
Ilkg(Z)
—
10
C
—
10
in
Output High Voltage (I
= – 400 µA)
V
OH
2.4
—
—
OH
Output Low Voltage (I
XTAL Input High level
XTAL Input Low level
= 5.0 mA)
V
OL
0.4
—
V
OL
V
IH(X)
3.0
—
V
V
IL(X)
0.5
– 400
400
2
V
EXTAL Output Current (V
EXTAL Output Current (V
= 4.6 V)
I
—
µA
µA
mA
kΩ
OH
OH(X)
= 0.4 V)
= 0.4 V)
I
—
OL
OL(X)
IRQ Output Low Current (V
OL
—
IRQ Output Off State Impedance
100
—
MOTOROLA
MC145574
18–1
18.3 ANALOG CHARACTERISTICS
(T = – 40 to + 85°C, V
= 5.0 V ± 5%, Voltages Referenced to V
)
SS
A
DD
Characteristic
TxP/TxN Drive Current: R = 50 Ω
Min
5.4
—
Typ
6.0
—
Max
6.6
1.17
—
Unit
mA
L
(TxP – TxN) Voltage Limit
Vpeak
mVpeak
mVpeak
V
Rx Input Sensitivity, Normal Mode (RxP – RxN)
Rx Input Sensitivity, Sleep Mode (RxP – RxN)
Voltage Regulator
—
90
220
—
—
3.0
3.2
3.4
18.4 POWER DISSIPATION
(T = – 40 to + 85°C, V
= 5.0 V ± 5%, Voltages Referenced to V
SS
and V
I/O Connected to V
)
DD
A
DD
DD
Characteristic
Min
4.75
—
Typ
5
Max
5.25
90
70
4
Unit
V
DC Supply Voltage
Worst Case Power Consumption**
Transmit Power Down
Sleep Mode
60*
50*
0.5*
0.1*
mW
mW
mW
mW
—
—
Absolute Minimum Power Down
NOTES:
—
2
*
These values have been measured on some sampled devices from several lots at 25°C and 5 V V
.
DD
** While sending and receiving 96 kHz signal on S/T–interface.
18–2
MC145574
MOTOROLA
18.5 IDL2 TIMING CHARACTERISTICS
18.5.1 IDL2 MasterTiming, 8- and 10-Bit Formats
Ref. No.
Parameter
Min
125
—
Typ
125
—
Max
—
Unit
µs
Note
1
2
3
4
5
FSC Period
1
Delay From the Rising Edge of DCL to the Rising Edge of FSC
Delay From the Rising Edge of DCL to the Falling Edge of FSC
DCL Clock Period
30
ns
—
—
30
ns
391
—
1953
ns
2
3
DCL Pulse Width High, Nominal
512 kHz
1.536 MHz
2.048 MHz
2.56 MHz
878
293
220
175
—
—
—
—
1074
358
265
215
ns
6
7
DCL Pulse Width Low
45
—
55
% of
DCL
Period
Delay From Rising Edge of DCL to Low–Z and Valid Data on
—
—
30
ns
D
out
8
Delay From Rising Edge of DCL to Data Valid on D
5
—
—
—
—
—
—
30
30
—
—
30
30
ns
ns
ns
ns
ns
ns
out
out
Data Valid on D Before Falling Edge of DCL (D Setup Time)
9
10
Delay From Rising Edge of DCL to High–Z on D
—
25
25
—
—
in in
11
Data Valid on D After Falling Edge of DCL (D Hold Time)
in
in
12
Delay From Rising Edge of DCL to TSEN Low
4
13
Delay From Falling Edge of DCL to TSEN High
NOTES:
1. FSC occurs on average every 125 µs.
2. The DCL frequency may be 512 kHz, 1.536 MHz, 2.048 MHz, or 2.56 MHz.
3. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode.
4. In IDL 8– and 10–bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
1
FSC
DCL
4
6
3
2
5
9
8
7
D
out
11
10
D
in
13
12
TSEN
Figure 18–1. IDL2 Master Timing, 8– and 10–Bit Formats
MC145574
MOTOROLA
18–3
18.5.2 IDL2 Slave Timing, 8- and 10-Bit Formats
Ref. No.
14
Parameter
Min
125
25
Max
—
Unit
µs
Note
FSC Period
1
15
FSC High Before the Falling Edge of DCL (FSC Setup Time)
FSC High After the Falling Edge of DCL (FSC Hold Time)
Delay From Rising Edge of DCL to Low–Z and Valid Data on
—
ns
16
25
—
ns
17
—
30
ns
D
out
18
19
20
21
22
23
Delay From Rising Edge of DCL to Data Valid on D
—
5
30
30
ns
ns
ns
ns
ns
out
out
Delay From Rising Edge of DCL to High–Z on D
Delay From Rising Edge of DCL to TSEN Low
Delay From Rising Edge of DCL to TSEN High
DCL Clock Period
—
30
2
3
—
30
244
45
1953
55
DCL Pulse Width High
% of DCL
Period
24
DCL Pulse Width Low
45
55
% of DCL
Period
25
26
Data Valid on D Before Falling Edge of DCL (D Setup Time)
in in
25
25
—
—
ns
ns
Data Valid on D After Falling Edge of DCL (D Hold Time)
in in
NOTES:
1. FSC occurs on average every 125 µs. FSC must occur every 125 µs with a maximum instantaneous phase titter of ± 30 µs.
2. In IDL2 8– and 10–bit formats, TSEN is valid during the B1, B2, and D channel timeslots. TSEN will be aligned with data
on the D
pin.
out
3. In IDL2 Slave mode, DCL may be any frequency multiple of 8 kHz between 256 kHz and 4.096 MHz inclusive.
18–4
MC145574
MOTOROLA
Figure 18–2. IDL2 Slave Timing, 8– and 10–Bit Formats
MOTOROLA
MC145574
18–5
18.6 GCI TIMING FOR MASTER AND SLAVE MODE
Ref. No.
Parameter
Min
—
Max
30
Unit
ns
Note
1
2
Delay From Rising Edge of DCL to FSC Output High
Delay From Rising Edge of DCL to FSC Output Low
FSC Input High Before the Falling Edge of DCL (FSC Setup Time)
FSC Input High After the Falling Edge of FSC (FSC Hold Time)
DCL Clock Period Master Mode
—
30
ns
1
3
25
—
ns
4
25
—
ns
5a
5b
6
488
244
1953
1953
ns
2
3
4
DCL Clock Period Slave Mode
ns
DCL Pulse Width High
512 kHz
2.048 kHz
878
210
1074
265
ns
7
DCL Pulse Width Low
45
55
% of DCL
Period
8
9
DCL Fall Time
DCL Rise Time
5
5
15
15
30
30
30
—
—
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
Delay From Rising Edge of FSC to Low–Z and Valid Data on D
—
—
5
out
11
Delay From Rising Edge of DCL to Data Valid on D
out
12
Delay From Rising Edge of DCL High–Z on D
out
13
Data Valid on D Before Rising Edge of DCL
in
25
25
—
—
14
Data Valid on D After Rising Edge of DCL
in
15
Delay From Rising Edge of FSC to TSEN Low
Delay From Rising Edge of DCL to TSEN High
16
NOTES:
1. The FSC pulse is normally two DCL clock periods wide in GCI mode.
2. In GCI Master mode, the MC145574 will output a 512 kHz, 1.536 MHz or 2.048 MHz clock as selected by M2, M1 and M0
pins.
3. In GCI Slave mode, DCL may be any frequency that is a multiple of 512 kHz and is between 512 kHz and 4.096 MHz.
4. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode.
18–6
MC145574
MOTOROLA
Figure 18–3. GCI Timing For Master and Slave Mode
MOTOROLA
MC145574
18–7
18.7 SCP TIMING CHARACTERISTICS
(T = – 40 to + 85°C, V
= 5.0 V ± 5%, Voltages Referenced to V
)
SS
A
DD
Ref. No.
Characteristic
Min
50
50
20
20
244
30
30
—
Max
—
—
—
—
—
—
—
50
50
40
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
13
SCPEN Active Before Rising Edge of SCPCLK
SCP Rising Edge Before SCPEN Active
SCP Rx Valid Before SCPCLK Rising Edge (Setup Time)
SCP Rx Valid After SCPCLK Rising Edge (Hold Time)
SCPCLK Period (Note 1)
14
15
16
17
SCPCLK Width (Low)
18
SCPCLK Width (High)
19
SCP Tx Active Delay
20
SCPEN Active to SCP Tx Active
—
21
SCPCLK Falling Edge to SCP Tx High–Impedance
SCPEN Inactive Before SCPCLK Rising Edge
SCPCLK Rising Edge Before SCPEN Inactive
SCPCLK Falling Edge to SCP Tx Valid Data
—
22
50
50
—
23
24
NOTE:
1. Maximum SCP Clock Frequency is 4.096 MHz.
22
SCP EN
13
23
16
12
1
2
3
4
5
6
7
8
SCPCLK
18
15
21
17
14
SCP Rx
(NOTE 1)
19
SCP Tx
(NOTE 2)
24
SCP Rx
(NOTE 3)
20
SCP Tx
(NOTE 3)
NOTES:
1. During a nibble read, four bits are presented on SCP Rx.
2. During a nibble read, SCP Tx will be active for the duration of the 4–bit transmission as shown.
3. During a byte read, eight bits are presented on SCP Rx. A byte transaction consists of two 8–bit ex-
changes. During the second 8–bit exchange, data is either written to the byte from SCP Rx or is read
fromthe byte. If the operation is a read operation, then data is presented onto SCP Tx. Refer to Section 5,
“The Serial Control Port”, for a detailed description.
Figure 18–4. SCP Timing Characteristics
18–8
MC145574
MOTOROLA
18.8 NT1 STAR MODE TIMING CHARACTERISTICS
Ref. No.
Characteristic
Min
Max
Unit
25
Propagation Delay from ANDIN to ANDOUT
—
35
ns
ANDIN
25
ANDOUT
Figure 18–5. NT1 Star Mode
18.9 D CHANNEL TIMING CHARACTERISTICS (IDL2 MODE)
Ref. No.
26
Characteristic
DREQUEST Valid Before Falling Edge of FSC
DREQUEST Valid After Falling Edge of FSC
DGRANT Valid Before Falling Edge of FSC
Min
30
Max
—
Unit
ns
27
30
—
ns
28
390
—
ns
DREQUEST
FSC
26
27
Figure 18–6. D Channel Request Timing
DGRANT
FSC
28
Figure 18–7. D Channel Grant Timing
MOTOROLA
MC145574
18–9
18–10
MC145574
MOTOROLA
19
MECHANICAL DATA
19.1 PIN ASSIGNMENTS
ISET
RxN
RxP
1
2
3
28 RESET
27 TxP
26 TxN
TE/NT
M/S
4
5
6
7
8
9
25 XTAL
24 EXTAL
T_IN/TFSC/TCLK/FIX
23
22
21
V 5
DD
V
SS
V
DD
I/O
SG/DGRANT/ANDOUT
DREQUEST/ANDIN
V 3
DD
20 IRQ/IND
CLASS/ECHO_IN 10
FSC/FSR 11
DCL 12
19 TSEN/FST/BCL/LBA
18 SCPEN/GCIEN
17 SCPCLK/S2/M2
16 SCPRx/S1/M1
15 SCPTx/S0/M0
D
13
14
in
D
out
Figure 19–1. MC145574DW Pin Assignment
(SOIC 28–Pin Package, Case 751F)
32 31 30 29 28 27 26 25
TE/NT
M/S
T_IN/TFSC/TCLK/FIX
1
2
3
4
5
6
7
8
24 XTAL
23 EXTAL
22
21
20
19 IRQ/IND
18 TSEN/FSX/BCL/LBA
17 SCPEN/GCIEN
V 5
DD
V
V
DD
I/O
SS
SG/DGRANT/ANDOUT
DREQUEST/ANDIN
CLASS/ECHO_IN
FSC/FSR
V 3
DD
9 10 11 12 13 14 15 16
Figure 19–2. MC145574PB Pin Assignment
(TQFP 32–Pin Package, Case 873A)
MOTOROLA
MC145574
19–1
19.2 PACKAGE DIMENSIONS
DW SUFFIX
SOIC
CASE 751F–04
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
15
28
1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
14X P
M
M
0.010 (0.25)
B
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
14
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
28X D
M
MILLIMETERS
DIM MIN MAX
INCHES
M
S
S
0.010 (0.25)
T A
B
MIN
MAX
0.711
0.299
0.104
0.019
0.035
R
X 45
_
A
B
C
D
F
17.80
7.40
2.35
0.35
0.41
18.05 0.701
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.016
C
–T–
SEATING
PLANE
26X G
G
J
K
M
P
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32 0.009
0.29 0.005
0.013
0.011
8
K
F
8
0
_
_
_
_
10.01
0.25
10.55 0.395
0.75 0.010
0.415
0.029
J
R
19–2
MC145574
MOTOROLA
PB SUFFIX
TQFP
CASE 873A–02
4X
A
A1
0.20 (0.008) AB T–U Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
_
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SECTION AE–AE
E
C
B1
C
D
E
F
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
_
Q
H
K
X
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
_
_
12 REF
12 REF
DETAIL AD
0.090 0.160 0.004 0.006
0.400 BSC
0.016 BSC
Q
R
1_
5_
1_
5_
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
MOTOROLA
MC145574
19–3
19–4
MC145574
MOTOROLA
20
F57J4 MASK SET DIFFERENCES
20.1 FUNCTIONAL DIFFERENCES
This section refers to MC145574 S/T–interfaces marked F57F4 and with a revision number BR15
= 03.
This mask set of the MC145574 has some functional differences from what is presented in this data
book.
20.1.1 Differences in Section 6
In GCI TE master mode, the DCL = 2.048 MHz option is not available. (See Table 6–4.)
In GCI TE mode, B1 and B2 channels are enabled by default. NR5(3:2) bits allow the B channels
to be set to idle 1s.
20.1.2 Differences in Section 10
OR6(3) is not available. In NT Terminal mode, the D
out
pin is always an open drain output.
20.1.3
Differences in Section 13.1.3.2
In NT Terminal mode, T_IN pin is only available when the device is activated. When the device is
not activated, 2B+D data should be sent directly to the U–interface.
MOTOROLA
MC145574
20–1
20–2
MC145574
MOTOROLA
A
MC145574EVK ISDN S/T-INTERFACE
TRANSCEIVER EVALUATION KIT
A.1
INTRODUCTION
The MC145574EVK S/T–Interface Transceiver Evaluation Kit provides Motorola ISDN customers a
convenient and efficient vehicle for evaluation of the MC145574 ISDN S/T–Interface Transceiver. The
approach taken to demonstrate the MC145574 S/T–Interface Transceiver is to provide the user with
a complete set of two S/T–Interfaces, either programmable for TE or NT modes. The MC145574EVK
does not terminate any ISDN call control messages.
The kit provides the ability to interactively manipulate status registers in the MC145574 S/T–Interface
Transceivers with the aid of an external terminal.
TA
MC145488
MC145574
SCP
IDL
S/T
S/T
CHIP
DDLC
MC14LC5480
MPU
SYSTEM
CODEC
HOST BUS
MC145574EVK
MC145574
MC145574
MC145572
IDL
SCP
IDL
S/T
CHIP
U
CHIP
S/T
CHIP
MPC
SYSTEM
SCP
MC14LC5480
RAM
ROM
MCU
CODEC
TE1
NT1
Figure A–1. Motorola Silicon Applications and the MC145574EVK
MOTOROLA
MC145574
A–1
A.2
FEATURES
General
A.2.1
• Provides Standalone NT and TE on a Single Board
• On–Board 68HC11 Microcontroller With Resident Monitor Software
• Convenient Access to Key Signals
• NT and TE Software Development Platform
A.2.2
Hardware
• Only + 5 Volt Power Supply
• Gated Data Clocks Provided for Bit Error Rate Testing
• Can Be Used as an S/T–Interface Terminal Development Tool
• EIA–232 (V.28) Serial Port for Terminal Interface
A.2.3
Software
• Computer Operation
• Resident Firmware Monitor for User Control of Board
• Activation and Deactivation Menus
• MC68HC11 Assembly Language Source Code Available
A–2
MC145574
MOTOROLA
A.3
BLOCK DIAGRAM
EIA–232
MC145407
PROM
SCP
BERT
CLK
MC68HC11E9
MICROCONTROLLER
XILINX
XC3020A
SCP
IDL
IDL
IDL
MC145574
ISDN
MC145574
ISDN
S/T–INTERFACE
TRANSCEIVER
S/T–INTERFACE
TRANSCEIVER
LINE ANALOG
INTERFACE
LINE ANALOG
INTERFACE
S/T
S/T
Figure A–2. Block Diagram
MOTOROLA
MC145574
A–3
A–4
MC145574
MOTOROLA
B
GLOSSARY OF TERMS AND ABBREVIATIONS
The list contains terms found in this and other Motorola publications concerned with Motorola Semiconductor prod-
ucts for Communications.
A–Law — A European companding/encoding law commonly used in PCM systems.
A/B Signaling — A special case of 8th–bit (LSB) signaling in a µ–law system that allows four logic states to be multiplexed
with voice on PCM channels.
A/D (analog–to–digital) converter (ADC) — A converter that uniquely represents all analog input values within a specified total
input range by a limited number of digital output codes, each of them exclusively representing a fractional part of the total analog
input range.
Aliasing Noise — A distortion component that is created when frequencies present in a sampled signal are greater than one–half
the sample rate.
Answer Back — A signal sent by receiving data–processing device in response to a request from a transmitting device, indicating
that the receiver is ready to accept or has received data.
Anti–Aliasing Filter — A filter (normally low pass) that band limits an input signal before sampling to prevent aliasing noise.
Asynchronous — A mode of data transmission in which the time occurrence of the bits within each character or block of charac-
ters relates to a fixed time frame, but the start of each character or block of characters is not related to this fixed time frame.
Attenuation — A decrease in magnitude of a communication signal.
Bandwidth — The information–carrying frequencies between the limiting frequencies of a communication line or channel.
Baseband — The frequency band occupied by information–bearing signals before combining with a carrier in the modulation
process.
Baud — A unit of signaling speed equal to the number of discrete signal conditions or events per second. This refers to the
physical symbols/second used within a transmission channel.
Bit Rate — The speed at which data bits are transmitted over a communication path, usually expressed in bits per second.
A 9600 bps terminal is a 2400 baud system with 4 bits/baud.
Blocking — A condition in a switching system in which no paths or circuits are available to establish a connection to the called
party even though it is not busy, resulting in a busy tone to the calling party.
BORS(C)HT — Battery, Overvoltage, Ringing, Supervision, (Codec), Hybrid, Test; the functions performed by a subscriber line
card in a telephone exchange.
Broadband — A transmission facility whose bandwidth is greater than that available on voice–grade facilities. (Also called wide
band.)
C Message — A frequency weighting that evaluates the effects of noise based on its annoyance to the “typical” subscriber of
standard telephone service or the effects of noise (background and impulse) on voice–grade data service.
Carrier — An analog signal of fixed amplitude and frequency that combines with an information–bearing signal by modulation
to produce an output signal suitable for transmission.
CCITT — Consultative Committee for International Telephone and Telegraph; an international standards group of European
International Telecommunications Union.
CCSN — Common Channel Signaling Network.
Central Office (CO) — A main telephone office, usually within a few miles of a subscriber, that houses switching gear; commonly
capable of handling about 10,000 subscribers.
Channel Bank — Communication equipment commonly used for multiplexing voice–grade channels into a digital transmission
signal (typically 24 channels in the U.S. and 30 channels in Europe).
MOTOROLA
MC145574
B–1
CIDCW — Calling Identity Delivery on Call Waiting; a subscriber feature which allows for the display of the time, date, number,
and possible other information about the caller to the called party while the called party is off–hook.
CLASS — Custom Local Area Signaling Service; a set of services, enhancements, provided to TELCO customers which may
include CND, CNAM, Message Waiting, and other features.
CLID — Calling Line IDentification; a subscriber feature which allows for the display of the time, date, number, and possible
other information about the caller to the called party.
CNAM — Calling Name Delivery; a subscriber feature which allows for the display of the time, date, number, and name of the
caller to the called party.
CND — Calling Number Delivery; a subscriber feature which allows for the display of the time, date, number, and possible other
information about the caller to the called party.
CODEC — COder–DECoder; the A/D and D/A function on a subscriber line card in a telephone exchange.
COFIDEC — COder–Filter–DECoder; the combination of a codec, the associated filtering, and voltage references required to
code and decode voice in a subscriber line card.
Common Mode Rejection — The ability of a device having a balanced input to reject a voltage applied simultaneously to both
differential–input terminals.
Companding — The process in which dynamic range compression of a signal is followed by expansion in accordance with
a given transfer characteristic (companding law) which is usually logarithmic.
Compander — A combination of a compressor at one point in a communication path for reducing the amplitude range of signals,
followed by an expander at another point for restoring the original amplitude range, usually to improve the signal–to–noise ratio.
Conference Call — A call between three or more stations, in which each station can carry on a conversation simultaneously.
CPE — Customer Premise Equipment; this could be a POTS phone, answering machine, fax machine, or any number of other
devices connected to the PSTN.
Crosspoint — The operating contacts or other low–impedance–path connection over which conversations can be routed.
Crosstalk — The undesired transfer of energy from one signal path to another.
CSN — Circuit Switched Network.
CTS — Clear to send; a control signal between a modem and a controller used to initiate data transmission over a communication
line.
CVSD — Continuous Variable Slope Delta (modulation); a simple technique to converting an analog signal (like voice) into a
serial bit stream.
D3 — D3 channel bank; a specific generation of AT&T 24–channel PCM terminal that multiplexes 24 voice channels into a 1.544
MHz digital bit stream. The specifications associated with D3 channel banks are the basis for all PCM device specifications.
D/A (digital–to–analog) converter (DAC) — A converter that represents a limited number of different digital input codes by a
corresponding number of discrete analog output values.
Data Compression — A technique that provides for the transmission of fewer data bits than originally required without information
loss. The receiving location expands the received data bits into the original bit sequence.
dB (decibel) — A power or voltage measurement unit, referred to another power or voltage. It is generally computed as:
10 x log (P1/P2) for power measurements, and
20 x log (V1/V2) for voltage measurements.
dBm — An indication of signal power. 1.0 mW across 600 Ω, or 0.775 volts rms, is defined as 0 dBm. Any other voltage level
is converted to dBm by:
dBm = 20 x log (Vrms/0.775), or
dBm = [20 x log (Vrms)] + 2.22.
dBmO — Signal power measured at a point in a standard test tone level at the same point.
i.e., dBmO = dBm = dBr
where dBr is the relative transmission level, or level relative to the point in the system defined as the zero transmission level
point.
B–2
MC145574
MOTOROLA
dBmOp — Relative power expressed in dBmp. (See dBmO and dBmp.)
dBmp — Indicates dBm measurement made with a psophometric weighting filter.
dBrn — Relative signal level expressed in decibels above reference noise, where reference noise is 1 pW. Hence, 0 dBrn =
1 pW = – 90 dBm.
dBrnC — Indicates dBrn measurement made with a C–message weighting filter. (These units are most commonly used in the
U.S., where psophometric weighting is rarely used.)
dBrnc0 — Noise measured in dBrnc referenced to zero transmission level.
Decoding — A process in which one of a set of reconstructed analog samples is generated from the digital character signal
representing a sample.
Delay Distortion — Distortion that occurs on communication lines due to the different propagation speeds of signals at different
frequencies, measured in microseconds of delay relative to the delay at 1700 Hz. (This type of distortion does not affect voice
communication, but can seriously impair data transmission.)
Delta Modulation — A simple digital coding technique that produces a serial bit stream corresponding to changes in analog
input levels; usually utilized in devices employing continuously variable–slope delta (CVSD) modulation.
Demodulator — A functional section of a modem that converts received analog line signals to digital form.
DN — Directory Number.
Digital Telephone — A telephone terminal that digitizes a voice signal for transmission and decodes a received digital signal
back to a voice signal. (It will usually multiplex 64 kbps voice and separate data inputs at multiples of 8 kbps.)
Distortion — The failure to reproduce an original signal’s amplitude, phase, delay, etc. characteristics accurately.
DPSK — Differential Phase Shift Keying; a modulation technique for transmission where the frequency remains constant but
phase changes will occur from 90°, 180°, and 290° to define the digital information.
DTMF — Dual Tone Multi–Frequency. It is the “tone dialing” system based on outputting two non–harmonic related frequencies
simultaneously to identify the number dialed. Eight frequencies have been assigned to the four rows and four columns of a typical
keypad.
Duplex — A mode of operation permitting the simultaneously two–way independent transmission of telegraph or data signals.
Echo — A signal that has been reflected or returned as a result of impedance mismatches, hybrid unbalance, or time delay.
Depending upon the location of impedance irregularities and the propagation characteristics of a facility, echo may interfere with
the speaker/listener or both.
Echo Suppressor — A device used to minimize the effect of echo by blocking the echo return currents; typically a voice–operated
gate that allows communication one way at a time.
Encoder (PCM) — A device that performs repeated sampling, compression, and A/D conversion to change an analog signal
to a serial stream of PCM samples representing the analog signal.
Equalizer — An electrical network in which phase delay or gain varies with frequency to compensate for an undesired amplitude
or phase characteristic in a frequency–dependent transmission line.
ET — Exchange Termination (C.O. Switch).
FDM — Frequency–Division Multiplex; a process that permits the transmission of two or more signals over a common path by
using a different frequency band for each signal.
Four Wire Circuit — The portion of a telephone, or central office, that operates on two pairs of wires. One pair is for the transmit
path (generally from the microphone), and one pair is for the receive path (generally from the receiver).
Frame — A set of consecutive digit time slots in which the position of each digit slot can be identified by reference to a frame
alignment. The frame alignment signal does not necessarily occur, in whole or in part, in each frame.
Full Duplex — A mode of operation permitting simultaneous transmission of information between two locations in both directions.
Gain — The change in signal amplitude (increase or decrease) after passing through an amplifier, or other circuit stage. Usually
expressed in dB, an increase is a positive number, and a decrease is a negative number.
Gain Tracking Error — The variation of gain from a constant level (determined at 0 dBm input level) when measuring the depen-
dence of gain on signal level by comparing the output signal to the input signal over a range of input signals.
HDLC — High–Level Data Link Control; a CCITT standard data communication line protocol.
MOTOROLA
MC145574
B–3
Half Duplex — A transmission system that permits communication in one direction at a time. CB ratios, with “push–to–talk”
switches, and voice–activated speakerphones, are half duplex.
Handset — A rigid assembly providing both telephone transmitter and receiver in a form convenient for holding simultaneously
to mouth and ear.
Hookswitch — A switch that connects the telephone circuit to the subscriber loop. The name derives from old telephones where
the switch was activated by lifting the receiver off and onto a hook on the side of the phone.
Idle Channel Noise (ICN) — The total signal energy measured at the output of a device or channel under test when the input
of the device or channel is grounded (often a wide–band noise measurement using a C–message weighting filter to band–limit
the output noise).
Intermodulation — The modulation of the components of a complex wave by each other (in a nonlinear system).
Intermodulation Distortion — An analog line impairment when two frequencies interact to create an erroneous frequency, in
turn distorting the data signal representation.
IRED — Infrared. Used as a wireless link for remote control or to transfer data.
ISDN — Integrated Services Digital Network; a communication network intended to carry digitized voice and data multiplexed
onto the public network.
Jitter — A type of analog communication line distortion caused by abrupt, spurious signal variation from a reference timing posi-
tion, and capable of causing data transmission errors, particularly at high speeds. (The variation canbeinamplitude, time, frequen-
cy, or phase.)
Key System — A miniature PABX that accepts 4 to 10 lines and can direct them to as many as 30 telsets.
µ–law — A companding law accepted as the North American standard for PCM based systems.
LAN — Local Area Network; a data–only communication network between data terminals using a standard interface to the net-
work.
Line — The portion of a circuit external to an apparatus that consists of the conductors connecting the apparatus to the exchange
or connecting two exchanges.
Line Length Compensation — Also referred to as loop length compensation, it involves changing the gain of the transmit and
receive paths, within a telephone, to compensate for different signal levels at the end of different line lengths. A short line (close
to the CO) will attenuate signals less, and therefore less gain is needed. Compensation circuits generally use the loop current
as an indication of the line length.
Longitudinal Balance — The common–mode rejection of a telephone circuit.
Loop — The loop formed by the two subscriber wires (Tip and Ring) connected to the telephone at one end, and the central
office (or PBX) at the other end. Generally it is a floating system, not referred to ground, or ac power.
Loopback — Directing signals back toward the source at some point along a communication path.
Loop Current — The dc current that flows through the subscriber loop. It is typically provided by the central office or PBX, and
ranges from 20 to 120 mA.
LT — Line Termination (Line Card).
MCU — MicroComputer Unit (also MicroController Unit).
MPU — MicroProcessor Unit.
Mu–Law — A companding/encoding law commonly used in U.S. (same as µ–law).
MUX — Multiplex or multiplexer.
Modem — MOdulator–DEModulator; a unit that modulates and demodulates digital information from a terminal or computer
port to an analog carrier signal for passage over an analog line.
Multiframing — When multiframing is enabled, 20 S/T frames are grouped together to provide maintenance subchannels be-
tween the TE and the NT. In the TE to NT direction, there is one subchannel called the Q channel. In the NT to TE direction,
there are five subchannels called SC1 through SC5. Messages for the Q, SC1, and SC2 subchannels have been defined in
CCITT I.430 and ANSI T1.605. Usage of the multiframing subchannels is not mandatory.
Multiplex — To simultaneously transmit two or more messages on a single channel.
NT1 — Network Termination 1 (OSI Layer 1 Only).
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MC145574
MOTOROLA
NT2 — Network Termination 2 (OSI Layers 2 and 3).
Off–Hook — The condition when the telephone is connected to the phone system, permitting loop current to flow. The central
office detects the dc current as an indication that the phone is busy.
On–Hook — The condition when the telephone’s dc path is open, and no dc loop current flows. The central office regards an
on–hook phone as available for ringing.
PABX — Private Automatic Branch Exchange; a customer–owned, switchable telephone system providing internal and/or exter-
nal station–to–station dialing.
Pair — The two associated conductors that form part of a communication channel.
Pass–Band Filter — A filter used in communication systems that allows only the frequencies within a communication channel
to pass, and rejects all frequencies outside the channel.
PBX — Private Branch Exchange; a class of service in standard Bell System terminology that typically provides the same service
as PABX.
PCM — Pulse Code Modulation; a method of transmitting data in which signals are sampled and converted to digital words
that are then transmitted serially, typically as 8–bit words.
Phase Jitter — Abrupt, spurious variations in an analog line, generally caused by power and communication equipment along
the line that shifts the signal phase relationship back and forth.
PLL — Phase–Locked Loop.
PLL Frequency Synthesizer — Phase–locked loop frequency synthesizer. A frequency synthesizer utilizing a closed loop, as
opposed to DDS (direct digital synthesis) which is not a closed loop.
POTS — Plain Old Telephone Service.
Propagation Delay — The time interval between specified reference points on the input and output voltage waveforms.
Psophometric Weighting — A frequency weighting similar to C–Message weighting that is used as the standard for European
telephone system testing.
PSN — Packet Switched Network.
PSTN — Public Switched Telephone Network.
Pulse Dialer — A device that generates pulse trains corresponding to digits or characters used in impulse or loop–disconnect
dialing.
Quantizing Noise — Signal–correlated noise generally associated with the quantizing error introduced by A/D and D/A conver-
sions in digital transmission systems.
REN — Ringer Equivalence Number; an indication of the impedance, or loading factor, of a telephone bell or ringer circuit. An
REN of 1.0 equals about 8 kΩ. The Bell system typically permits a maximum of 5.0 REN (1.6 kΩ) on an individual subscriber
line. A minimum REN of 0.2 (40 kΩ) is required by the Bell system.
Repeater — An amplifier and associated equipment used in a telephone circuit to process a signal and retransmit it.
Repertory Dialer — A dialer that stores a repertory of telephone numbers and dials any one of them automatically on request.
Ring — One of the two wires connecting the central office to a telephone. The name derives from the ring portion of the plugs
used by operators (in older equipment) to make the connection. Ring is traditionally negative with respect to Tip.
RTS — Request To Send; an EIA–232 control signal between a modem and user’s digital equipment that initiates the data trans-
mission sequence on a communication line.
Sampling Rate — The frequency at which the amplitude of an analog signal is gated into a coder circuit. The Nyquist sampling
theorem states that if a band–limited signal is sampled at regular intervals and at a rate equal to or greater than twice the highest
frequency of interest, the sample contains all the information of the original signal. The frequency band of interest in telephony
ranges from 300 to 3400 Hz, so a sampling rate of 8 kHz provides dc to 4000 Hz reproduction.
SCU — Subscriber Channel Unit; the circuitry at a telephone exchange associated with an individual subscriber line or channel.
Sidetone — The sound fed back to the receiver as a result of speaking into the microphone. It is a natural consequence of
the 2–to–4 wire conversion system. Sidetone was recognized by Alexander Graham Bell as necessary for a person to be able
to speak properly while using a handset.
Signaling — The transmission of control or status information between switching systems in the form of dedicated bits or channels
of information inserted on trunks with voice data.
MOTOROLA
MC145574
B–5
Signal–to–Distortion Ratio (S/D) — The ratio of the input signal level to the level of all components that are present when
the input signal (usually a 1.020 kHz sinusoid) is eliminated from the output signal (e.g., by filtering).
SLIC — Subscriber Line Interface Circuit; a circuit that performs the 2–to–4 wire conversion, battery feed, line supervision, and
common mode rejection at the central office (or PBX) end of the telephone line.
SOG Package — Small–Outline Gull–wing package; formerly SOIC with gull–wing leads. This package has leads which fold
out from the body.
SOJ Package — Small–Outline J–lead package; formerly SOIC with J leads. This package has leads which are tucked under
the body.
Speech Network — A circuit that provides 2–to–4 wire conversion, i.e., connects the microphone and receiver (or the transmit
and receive paths) to the Tip and Ring phone lines. Additionally it provides sidetone control, and in many cases, the dc loop
current interface.
Subscriber Line — The system consisting of the user’s telephone, the interconnecting wires, and the central office equipment
dedicated to that subscriber (also referred to as a loop).
Switchhook — A synonym for hookswitch.
Syn (Sync) — (1) A bit character used to synchronize a time frame in a time–division multiplexer. (2) A sequence used by a
synchronous modem to perform bit synchronization or by a line controller for character synchronization.
Synchronous Modem — A modem that uses a derived clocking signal to perform bit synchronization with incoming data.
T1 Carrier — A PCM system operating at 1.544 MHz and carrying 24 individual voice–frequency channels.
TA — Terminal Adapter.
Talkdown — Missed signals in the presence of speech. Commonly used to describe the performance of a DTMF receiver when
it fails to recognize a valid DTMF tone due to cancellation of that tone by speech.
Talkoff — False detections caused by speech. Commonly used to describe the performance of a DTMF receiver when speech,
emulating DTMF, causes the receiver to believe it has detected a valid DTMF tone.
Tandem Trunk — See trunk.
Telephone Exchange — A switching center for interconnecting the lines that service a specific area.
TE1 — Terminal Equipment 1 (ISDN Terminal).
TE2 — Terminal Equipment 2 (Non–ISDN Terminal).
TELETEX — A text communication service between entirely electronic work stations that will gradually replace TELEX with the
introduction of the digital network. (Not to be confused with teletext.)
TELETEXT — The name usually used for broadcast text (and graphics) for domestic television reception. (Not to be confused
with teletex.)
Time–Division Multiplex — A process that permits the transmission of two or more signals over a common path by using a
different time interval for each signal.
Tin Cans and String — A crude analog communications system commonly used to introduce voice communications to children.
Tip — One of the two wires connecting the central office to a telephone. The name derives from the tip of the plugs used by
operators (in older equipment) to make the connection. Tip is traditionally positive with respect to ring.
Tone Ringer — The modern solid state equivalent of the old electromechanical bell. It provides the sound when the central
office alerts the subscriber that someone is calling. Ringing voltage is typically 80–90 volts rms, 20 Hz.
Trunk — A telephone circuit or channel between two central offices or switching entities.
TSAC — Time Slot Assigner Circuit; a circuit that determines when a CODEC will put its 8 bits of data on a PCM bit stream.
TSIC — Time Slot Interchange Circuit; a device that switches digital highways in PCM based switching systems; a “digital” cross-
point switch.
Twist — The amplitude ratio of a pair of DTMF tones. (Because of transmission and equipment variations, a pair of tones that
originated equal in amplitude may arrive with a considerable difference in amplitude.)
Two Wire Circuit — Refers to the two wires connecting the central office to the subscriber’s telephone. Commonly referred
to as Tip and Ring, the two wires carry both transmit and receive signals in a differential manner.
B–6
MC145574
MOTOROLA
UDLT — Universal Digital Loop Transceiver; a Motorola originated name for a voice/data transceiver circuit.
VCO — Voltage–controlled oscillator. Input is a voltage; output is a sinusoidal waveform.
VCM — Voltage–controlled multivibrator. Input is a voltage; output is a square wave.
Voice Frequency — A frequency within that part of the audio range that is used for the transmission of speech of commercial
quality (i.e., 300–3400 Hz).
Weighting Network — A network whose loss varies with frequency in a predetermined manner.
MOTOROLA
MC145574
B–7
B–8
MC145574
MOTOROLA
INDEX
A
E
Echo Channel, 3–3, 9–7, 9–13
Activation, 3–1, 3–2, 6–14, 6–15, 8–3, 9–6, 9–8
GCI, 6–14
Error, 3–2, 8–3
ETSI ETS 300012, 1–2, 10–7
Adaptive Timing, 13–1
ANSI T1.605, 1–2
F
Fixed Timing, 13–1
B
Frame Syncs, 4–4
Byte Register, 5–3, 5–4, 9–1
Initialization, 9–2
Read, 5–3
G
Write, 5–4
GCI, 6–1, 15–2
Clock Frequency, 10–4
D Channel Operation, 11–3
DCL, 6–5
C
Din, 6–5
Direct, 6–6
CCITT I.430, 1–2
Dout, 6–5
CLASS, 7–3
FSC, 6–5
Class, 11–2
GCI Indirect Mode Enable, 10–4
GCI Timeslot, S(2:0), 10–3
Indirect, 6–4
Modes, 6–1
Multiframing, 12–3
Clock, 4–9, 7–4, 14–1
Command Indicate Channel, 6–12
Configurations, 13–1
NT, 13–1
NT Fixed or Adaptive Timing, 13–1
NT Terminal Mode, 13–2, 13–4
TE Master Mode, 13–5
TE Slave Mode, 13–5
I
IDL2, 4–1, 4–2, 4–3, 4–9, 4–10, 9–8, 9–12
Clock Speed (LSB), 9–8
Clock Speed (MSB), 9–12
Enable TCLK, 10–5
Crystal, 5–7, 7–4, 14–1
INFO State, 8–4, 9–11, 15–2
Initial State, 3–3
D
Interrupt, 8–6, 11–3
Multiframe, 9–4
D Channel, 11–1, 15–1
Deactivate, 8–4
Interrupts, 15–1
Deactivation, 3–3, 6–15
GCI, 6–14
J
DGRANT, 7–2, 11–1
DREQUEST, 7–2, 11–1
Jitter, 1–2
MOTOROLA
MC145574
Index–9
Pin Descriptions, 7–1
Point–to–Point, 2–1
L
Line Interface, 16–1
Long Frame, 4–8
Loopback, 8–7, 9–5
Loopbacks, 1–2
Power Settings, 17–1
Absolute Minimum Power, 1–2, 8–2, 17–2
Normal Power Operation, 17–1
Sleep, 1–2, 17–2
Transmit Power–Down, 1–2, 8–2, 17–1
Power–Down, 1–2, 8–2, 17–1
M
M and N Parameters, 3–3
R
Master, 4–3, 7–2, 13–1
GCI, 6–6
Register Differences, 6–12
Register Maps, 8–1, 9–1, 9–2, 10–1
Reset, 7–4, 8–2
Monitor Channel, 6–7, 6–8, 6–11
Commands, 6–10
Messages, 6–8
Operation, 6–8
Revision, 9–13
Response Messages, 6–10
Status Indication Messages, 6–10
S
Multiframing, 1–2, 8–3, 8–5, 9–3, 9–7, 9–9, 12–1,
SCP, 5–1, 5–5, 5–7, 7–3, 7–5
15–1
Interrupts, 12–2
High–Impedance Digital Output Mode (SCP
HIDOM), 5–7
IRQ, 5–7
Rx, 5–6
N
SCPCLK, 5–6
SCPEN, 5–7
Slave, 5–7
Tx, 5–6
Nibble Register, 5–1, 5–2, 8–1
Initialization, 8–2
Read, 5–1
Write, 5–2
Serial Control Port, 5–1
NT Terminal, 8–4, 10–6, 13–2
NT Terminal Mode, 8–5, 13–4
NT Terminal Modes, 1–2
Slave, 4–2, 4–3, 4–11, 7–2, 10–5, 13–1
Enable TCLK, 10–5
GCI, 6–6
TE Slave, 4–4
NT1 Star, 2–3, 7–2, 9–12, 13–2
Sleep, 10–6, 17–2
NT2, 13–6
Applications, 4–8
T
Terminal Mode, 6–7
O
Timeslot Assigner, 4–4
Overlay Register, 9–13, 10–1
Control Register, 10–4
Enable, 10–7
Rx B1 Channel Timeslot, 10–3
Rx B2 Channel Timeslot, 10–3
Rx D Channel Timeslot, 10–3
Tx B1 Channel Timeslot, 10–2
Tx B2 Channel Timeslot, 10–2
Tx D Channel Timeslot, 10–2
Initialization, 10–2
P
Packages, 1–3
Passive Bus, 2–2, 2–3
Phase, 4–4, 4–5, 4–7
Pin Assignments, 19–1
Transformers, 16–3
Transmission States, 3–1
TSEN, 4–2, 4–9, 4–11, 7–3, 10–5
Index–10
MC145574
MOTOROLA
3/1/99
MOTOROLA AUTHORIZED DISTRIBUTOR & WORLDWIDE SALES OFFICES
NORTH AMERICAN DISTRIBUTORS
UNITED STATES
CALIFORNIA – continued
San Jose
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (408)383–0366
ALABAMA
Huntsville
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (408)441–9700
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (408)428–6400
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)629–4789
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)434–0369
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (408)434–1122
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (205)721–3500
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (205)837–6955
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (205)837–9209
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (205)830–2322
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (205)837–8700
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (205)837–9091
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (205)830–1119
Santa Clara
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (408)727–2500
Santa Fe Springs
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (562)929–9722
Mobile
Sierra Madre
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (334)476–1875
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)355–6775
ARIZONA
Sunnyvale
Phoenix
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (408)435–3600
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (602)831–2002
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)730–0300
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)731–4661
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (602)968–7140
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (602)736–7000
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (602)804–7000
Thousand Oaks
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (805)449–1480
Woodland Hills
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (818)594–0404
Tempe
COLORADO
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (602)966–6600
Lakewood
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)237–1400
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (303)232–2008
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)966–6340
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)967–1620
Denver
ARKANSAS
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (303)790–1664
Little Rock
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)373–4540
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (501)225–8130
Englewood
CALIFORNIA
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (303)799–0258
Agoura Hills
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (303)790–1662
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)799–7845
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (818)871–1740
Calabassas
Thornton
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (818)880–9686
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (303)457–9953
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (818)880–9000
CONNECTICUT
Culver City
Bloomfield
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (310)558–2000
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (860)243–1731
Irvine
Cheshire
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (714)587–0404
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (203)272–7730
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (714)581–4622
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (714)753–4778
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (714)453–1515
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (714)789–4100
Wyle Laboratories Corporate . . . . . . . . . . . . . . . (714)753–9953
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (714)789–9953
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (203)250–1319
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (203)250–0083
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (203)271–5700
Wallingford
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (203)265–7741
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (203)269–8077
Los Angeles
FLORIDA
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)879–1234
Altamonte Springs
Manhattan Beach
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (310)546–8953
Orange County
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (714)727–3010
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (407)865–7900
Clearwater
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (813)530–1665
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (813)530–1222
Deerfield Beach
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (305)429–8200
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (954)420–0500
Ft. Lauderdale
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (954)428–9494
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (954)426–4043
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (954)677–3500
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (954)486–1151
Palo Alto
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (650)812–6300
Rancho Cordova
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (916)638–5282
Riverside
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (909)980–6522
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (909)980–2105
Rocklin
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (916)632–4500
Jacksonville
Roseville
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (904)739–5920
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (916)783–9953
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (904)399–5041
Sacramento
Lake Mary
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (916)632–3104
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (407)333–9300
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (916)782–7882
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (916)565–1760
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)333–3055
Largo/Tampa/St. Petersburg
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (813)507–5000
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (813)287–1578
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (813)576–3004
San Diego
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (619)279–2550
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (619)565–4800
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (619)623–2888
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (619)625–2800
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (619)571–7540
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (619)453–8211
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (619)623–9100
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (619)558–6600
Miami
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (305)558–2511
Maitland
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (407)740–7450
Orlando
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (407)539–0055
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)865–9555
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)896–8350
San Fernando Valley
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (818)598–0130
MOTOROLA
MC145574
Index–11
FLORIDA – continued
Itasca
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (708)250–0500
Tallahassee
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (904)668–7772
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (630)595–9730
Tampa
Lombard
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (813)579–4660
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (630)317–1000
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (813)287–1578
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (813)247–7556
Palatine
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (708)934–3700
Winter Park
Rockford
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (407)657–3300
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (815)636–1010
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)672–1114
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (815)229–0225
Springfield
GEORGIA
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (217)787–9972
Atlanta
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (770)497–9544
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (404)447–4767
Wood Dale
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (630)860–0007
INDIANA
Indianapolis
Duluth
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (404)497–1300
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (317)571–1880
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (770)623–4400
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (317)299–2071
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (317)575–3500
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (317)469–0441
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (317)469–0447
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (317)844–0047
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (317)581–6152
Norcross
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (770)441–7676
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)448–1300
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)734–9990
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (770)441–9045
IDAHO
Boise
Ft. Wayne
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (208)331–1414
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (219)484–0766
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (208)376–8080
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (219)432–1277
IOWA
ILLINOIS
Bettendorf
Addison
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (319)359–3711
Wyle Laboratories . . . . . . . . . . . . . . . . . . . . . . . . . (708)620–0969
Arlington Heights
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (847)797–7300
Cedar Rapids
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (319)390–5730
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (319)393–3800
Chicago
Allied Electronics, Inc. (North) . . . . . . . . . . . . . . . (847)548–9330
KANSAS
Kansas City
Allied Electronics, Inc. (South) . . . . . . . . . . . . . . . (708)535–0038
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (708)843–0034
Newark Electronics Corp. . . . . . . . . . . . . . . . . . . (773)784–5100
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (913)338–4372
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (913)381–6800
Hoffman Estates
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (708)882–1255
Lenexa
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (913)541–9542
Index–12
MC145574
MOTOROLA
3/1/99
AUTHORIZED DISTRIBUTORS – continued
UNITED STATES – continued
MINNESOTA – continued
Minneapolis
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (612)938–5633
KANSAS – continued
Olathe
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)331–6350
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (913)829–9330
MISSISSIPPI
Jackson
Overland Park
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (601)956–3834
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (913)649–1531
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (913)663–7900
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (913)677–0727
MISSOURI
Earth City
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (314)770–6300
KENTUCKY
Louisville
St. Louis
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (314)240–9405
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (502)452–2293
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (314)567–6888
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (314)469–6805
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (314)542–9922
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (314)991–0400
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (502)423–0280
LOUISIANA
New Orleans
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (504)466–7575
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (504)838–9771
NEBRASKA
Omaha
MARYLAND
Baltimore
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (402)697–0038
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (402)592–2423
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (410)312–0810
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (410)312–0833
NEVADA
Las Vegas
Columbia
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (702)258–1087
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (301)596–7800
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (702)765–7117
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (410)309–1541
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (410)290–0600
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (410)720–3400
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (410)290–3746
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (410)312–4844
NEW JERSEY
Bridgewater
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (908)575–9490
East Brunswick
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (908)613–0828
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (732)937–6600
Hanover
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (410)712–6922
Fairfield
MASSACHUSETTS
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (201)331–1133
Bedford
Marlton
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (781)271–9953
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (609)596–8000
Boston
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (609)988–1500
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (609)596–4080
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (617)255–0361
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (508)658–0900
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (508)779–3111
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–800–4NEWARK
Mt. Laurel
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (609)222–6400
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (609)439–9110
Bolton
Oradell
Future Corporate . . . . . . . . . . . . . . . . . . . . . . . . . . (978)779–3000
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (201)261–3200
Burlington
Pinebrook
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (617)229–9100
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (201)227–7880
Lowell
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (973)882–8358
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (978)551–4300
Parsippany
Peabody
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (201)299–0400
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (508)538–2401
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (201)515–1641
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (508)532–3701
NEW MEXICO
Albuquerque
Wilmington
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (978)658–4776
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (505)266–7565
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (505)293–5119
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (505)828–1878
Worchester
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (508)229–2200
MICHIGAN
Detroit
NEW YORK
Albany
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (313)416–9300
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (518)489–1963
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (313)513–0015
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (616)698–6800
Grand Rapids
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (616)365–9960
Buffalo
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (716)631–2311
Great Neck
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (516)487–5211
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (616)954–6700
Hauppauge
Livonia
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (516)234–0485
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (810)455–0850
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (516)231–1000
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (516)348–3700
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (516)234–4000
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (516)434–7400
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (516)567–4200
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (516)724–9580
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (516)231–7850
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (313)261–5270
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (313)416–5800
Novi
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (248)374–9953
Saginaw
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (517)799–0480
Troy
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (248)583–2899
Henrietta
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (716)334–5970
MINNESOTA
Bloomington
Konkoma
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)853–2280
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (516)737–0600
Burnsville
Pittsford
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)882–7630
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (716)381–4244
Eden Prairie
Poughkeepsie
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (914)452–1470
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (612)941–5280
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)947–0909
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (612)944–2200
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (612)881–2600
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (914)298–2810
Purchase
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (914)701–7400
MOTOROLA
MC145574
Index–13
NEW YORK – continued
Columbus
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (614)785–1270
Rochester
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (716)292–1670
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (614)326–0352
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (716)427–0300
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (716)387–9550
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (716)387–9600
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (716)272–2740
Dayton
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (513)427–6090
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (513)426–0090
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (513)439–6735
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (937)294–8980
Mayfield Heights
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (216)449–6996
Syracuse
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (315)446–7411
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (315)451–4405
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (315)451–2371
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (315)457–4873
Miamisburg
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (937)436–9953
Solon
NORTH CAROLINA
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (216)248–3990
Charlotte
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (216)498–1100
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (440)248–9996
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (704)525–0300
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (704)548–9503
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (704)547–1107
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (704)535–5650
Toledo
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (419)866–0404
Worthington
Greensboro
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (614)888–3313
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (910)294–2142
OKLAHOMA
Morrisville
Oklahoma City
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (919)469–1502
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (405)943–3700
Raleigh
Tulsa
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (919)876–5845
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (918)250–4505
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (919)876–3132
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (919)876–0088
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (919)790–7111
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (919)872–0712
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (918)492–1500
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (918)459–6000
OREGON
Beaverton
OHIO
Centerville
Arrow/Almac Electronics Corp. . . . . . . . . . . . . . . (503)629–8090
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (503)645–9454
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (503)526–6200
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (513)435–5563
Cincinnati
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (513)771–6990
Portland
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (503)626–9921
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (513)942–8700
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)297–5020
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)297–1984
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)646–1670
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (503)598–9953
Cleveland
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (216)831–4900
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (216)446–0061
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (216)391–9330
Index–14
MC145574
MOTOROLA
3/1/99
AUTHORIZED DISTRIBUTORS – continued
UNITED STATES – continued
UTAH
Draper
PENNSYLVANIA
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (801)523–2335
Salt Lake City
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (801)261–5244
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (801)973–6913
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (801)467–9696
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (801)467–4448
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (801)266–2022
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (801)261–5660
Allentown
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (610)434–7171
Chadds Ford
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (610)388–8455
Coatesville
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (610)383–9536
Ft. Washington
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (215)654–1434
Harrisburg
West Valley City
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (801)974–9953
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (717)540–7101
Philadelphia
VIRGINIA
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (609)234–7769
Herndon
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (703)707–9010
Pittsburgh
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (412)931–2774
Richmond
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (412)963–6807
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (412)788–4790
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (804)282–5671
Springfield
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (703)644–9515
SOUTH CAROLINA
Greenville
Virginia Beach
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (757)363–8662
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (864)288–8835
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (864)288–9610
WASHINGTON
Bellevue
TENNESSEE
Knoxville
Almac Electronics Corp. . . . . . . . . . . . . . . . . . . . (206)643–9992
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (206)454–2371
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (423)588–6493
Memphis
Bothell
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (901)396–7970
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (206)489–3400
Kirkland
TEXAS
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (425)814–6230
Austin
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (512)219–7171
Redmond
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (206)882–7000
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (512)835–4180
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (512)502–0991
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346–6426
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (512)219–3700
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)338–0287
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346–9762
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (512)833–9953
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (425)881–1150
Seattle
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (206)251–0240
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (206)485–6616
Spokane
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (509)327–1935
WISCONSIN
Brookfield
Benbrook
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (817)249–0442
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (414)792–0150
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (414)879–0244
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (414)879–0434
Brownsville
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (210)548–1129
Carrollton
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (972)380–6464
Madison
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (608)278–0177
Arrow Zeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (972)380–4330
Milwaukee
Dallas
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (414)796–1280
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (214)341–8444
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (414)792–9778
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (972)231–7195
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (972)437–2437
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (214)553–4300
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (972)458–2528
New Berlin
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (414)780–7200
Wauwatosa
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (414)453–9100
El Paso
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (915)779–6294
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (915)577–9531
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (915)772–6367
Ft. Worth
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (817)595–3500
Houston
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (281)446–8005
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (281)647–6868
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (713)952–7088
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (713)785–1155
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (713)781–6100
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (281)894–9334
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (713)784–9953
Richardson
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (972)479–9215
Wyle Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (972)235–9953
San Antonio
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (210)738–3330
MOTOROLA
MC145574
Index–15
CANADA
ONTARIO
Kanata
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (613)592–6088
ALBERTA
Calgary
London
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (519)685–4280
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (403)291–5333
Mississauga
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (403)250–5550
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (800)663–5500
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (800)463–9275
PENSTOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (905)403–0724
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (905)670–2888
Ottawa
Edmonton
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (613)228–1964
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (403)438–5888
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (613)226–6903
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (613)820–8244
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (613)727–1800
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (613)226–1700
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (403)438–2858
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (800)663–5500
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (800)463–9275
Saskatchewan
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (800)663–5500
Toronto
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (905)670–7769
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (905)612–9888
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (905)612–9200
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (905)564–6060
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (905)670–2888
BRITISH COLUMBIA
Vancouver
Allied Electronics, Inc. . . . . . . . . . . . . . . . . . . . . . (604)420–9691
QUEBEC
Montreal
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (604)421–2333
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (604)654–1050
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (604)294–1166
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (604)420–4101
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (800)463–9275
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (514)421–7411
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (514)694–8157
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (514)694–7710
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (514)335–1000
MANITOBA
Mt. Royal
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (514)738–4488
Winnipeg
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (204)786–3075
Quebec City
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (204)944–1446
Hamilton/Hallmark . . . . . . . . . . . . . . . . . . . . . . . . (800)663–5500
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (800)463–9275
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (418)687–4231
FAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (418)877–1414
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (418)877–6666
Index–16
MC145574
MOTOROLA
3/1/99
INTERNATIONAL DISTRIBUTORS
ARGENTINA
GREECE
Electrocomponentes . . . . . . . . . . . . . . . . . . . . . (5–41) 375–3366
Elko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5–41) 372–1101
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . . . (30) 13414300
HONG KONG
Avnet WKK Components Ltd. . . . . . . . . . . . . . . . . . . (852)2 357–8888
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (65) 788–0200
Future Advanced Electronics Ltd. . . . . . . . . . . . . . . . (852)2 305–3633
Nanco Electronics Supply Ltd. . . . . . . . . . . . . . . . . . (852)2 333–5121
Qing Cheng Enterprises Ltd. . . . . . . . . . . . . . . (852)2 493–4202
AUSTRALIA
Avnet VSI Electronics (Aust.) . . . . . . . . . . . . . . . . . . (61)2 9878–1299
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (61)2 9645–8888
Veltek Australia Pty. Ltd. . . . . . . . . . . . . . . . . . (61)3 9574–9300
AUSTRIA
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . . . (43) 189152–0
HUNGARY
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (49) 8961 393939
SEI/Elbatex GmbH . . . . . . . . . . . . . . . . . . . . . . . . . (43) 1 866420
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . . . . (43) 1 360460
EBV Elektronik KFT . . . . . . . . . . . . . . . . . . . . . . (36) 1 4313 495
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 2240 510
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 2030 277
SEI/Elbatex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 1409 194
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 1294 202
BELGIUM
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (32) 2 716 0010
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (32) 3 227 3647
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . (32) 3 780 3001
SEI/Belgium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (32) 2 460 0747
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . . (32) 2 725 4660
INDIA
Max India Ltd . . . . . . . . . . . . . . . . . . . . . . . . . . 0091 11 625–0250
INDONESIA
P.T. Ometraco . . . . . . . . . . . . . . . . . . . . . . . . . . (62) 21 619–6166
BRAZIL
IRELAND
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5511) 445–7400
Arrow Electronics . . . . . . . . . . . . . . . . . . . . . . . . (353) 14595540
Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (019) 235–1511
Intertek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 266–2922
Karimex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 524–2366
Masktrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 3361–2766
Panamericana . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 223–0222
Siletek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 536–4401
Tec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 5505–2046
Teleradio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (011) 574–0788
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (353) 14564034
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (353) 18309277
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (353) 6541330
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . (353) 16766904
ISRAEL
Future Israel Ltd. . . . . . . . . . . . . . . . . . . . . . . . . . (972) 9 9586555
ITALY
Avnet EMG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (39) 02 381901
BULGARIA
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (39) 02 66096290
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (39) 02 660941
Silverstar LTD . . . . . . . . . . . . . . . . . . . . . . . . . . . . (39) 02 661251
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (359) 2708140
CHINA
Arrow Asia/Pac Ltd . . . . . . . . . . . . . . . . . . . . . . (852)2 484–2113
JAPAN
Avnet WKK Components Ltd. . . . . . . . . . . . . . . . . . . (852)2 357–8888
China El. App. Corp. Beijing . . . . . . . . . . . . . . . . . (86)10 6828–9951
Future Advanced Electronics Ltd. . . . . . . . . . . . . . . . (852)2 305–3633
Nanco Electronics Supply Ltd. . . . . . . . . . . . . . . (852)2 765–3025
Qing Cheng Enterprises Ltd. . . . . . . . . . . . . . . . (852)2 493–4202
CZECH REPUBLIC
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (420) 2 90022101
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . (420) 2 71737173
SEI/Elbatex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (420) 2 4763707
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . (420) 2 3412182
AMSC Co., Ltd. . . . . . . . . . . . . . . . . . . . . . . . . . 81–422–54–6800
Fuji Electronics Co., Ltd. . . . . . . . . . . . . . . . . . 81–3–3814–1411
Marubun Corporation . . . . . . . . . . . . . . . . . . . . 81–3–3639–8951
OMRON Corporation . . . . . . . . . . . . . . . . . . . . 81–3–3779–9053
Tokyo Electron Device Ltd. . . . . . . . . . . . . . . . 81–45–474–7030
KOREA
Future Electronics Korea . . . . . . . . . . . . . . . . . . 82–2–555–6736
Jung Kwang Semiconductors Ltd. . . . . . . . . . . . . . . . 82–2–742–6681
Liteon Korea Ltd . . . . . . . . . . . . . . . . . . . . . . . . . 82–2–650–9700
Nasco Co. Ltd . . . . . . . . . . . . . . . . . . . . . . . . . . . 82–2–868–4988
Sekyung Electronics . . . . . . . . . . . . . . . . . . . . . . 82–2–514–5614
DENMARK
Arrow Denmark A/S . . . . . . . . . . . . . . . . . . . . . . . (45) 44 508200
LATVIA
A/S Avnet EMG . . . . . . . . . . . . . . . . . . . . . . . . . . . (45) 44 880800
EBV Elektronik – Soeborg . . . . . . . . . . . . . . . . . . . (45) 39690511
EBV Elektronik – Abyhoj . . . . . . . . . . . . . . . . . . . . (45) 86250466
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . (45) 961 00 961
Avnet Baltronic Ltd. . . . . . . . . . . . . . . . . . . . . . . . . (371) 8821118
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (371) 7313195
LITHUANIA
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (370) 7764937
ESTONIA
MALAYSIA
Arrow Field Eesti . . . . . . . . . . . . . . . . . . . . . . . . . . . (372) 6503288
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (60) 3 773–8000
Avnet Baltronic . . . . . . . . . . . . . . . . . . . . . . . . . . . . (372) 6397000
Strong Electronics . . . . . . . . . . . . . . . . . . . . . . . . (60) 4 656–3768
Ultro Technologies Pte. Ltd. . . . . . . . . . . . . . . . . . (65) 545–7811
FINLAND
Arrow Finland . . . . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 476660
MEXICO
Avnet Nortek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 613181
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 8557730
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . (358) 9 345 5400
Avnet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (3) 632–0182
Dicopel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5) 705–7422
Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (3) 122–0043
Semiconductores Profesionales . . . . . . . . . . . . . . . . . . . . (5) 658–6011
Steren . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (5) 325–0925
FRANCE
Arrow Electronique . . . . . . . . . . . . . . . . . . . . . (33) 1 49 78 49 78
Avnet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (33) 1 49 65 27 00
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (33) 1 40963000
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (33) 474 659466
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . (33) 1 69821111
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (33) 1 30954060
Sonepar Electronique . . . . . . . . . . . . . . . . . . . (33) 1 69 19 89 00
NETHERLANDS
HOLLAND
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (31) 3465 83010
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (31) 30 241 2323
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . (31) 76 544 4888
SEI/Benelux B.V. . . . . . . . . . . . . . . . . . . . . . . . . . (31) 7657 22500
Spoerle Electronics –
GERMANY
Avnet EMG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (49) 89 4511001
Nieuwegen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (31) 3060 91234
Spoerle Electronics –
Veldhoven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (31) 4025 45430
EBV Elektronik GmbH . . . . . . . . . . . . . . . . . . . . (49) 89 99114–0
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (49) 89 61 393939
Future Electronics GmbH . . . . . . . . . . . . . . . . . (49) 89–957 270
SEI/Jermyn GmbH . . . . . . . . . . . . . . . . . . . . . . . (49) 6431–5080
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (49)2154–70011
Sasco Semiconductor . . . . . . . . . . . . . . . . . . . . . . (49) 89–46110
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . (49) 6103–304–0
NEW ZEALAND
Arrow Components NZ Ltd . . . . . . . . . . . . . . . . (64)4 570–2260
Avnet Pacific Ltd . . . . . . . . . . . . . . . . . . . . . . . . . (64)9 636–7801
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (64)9 357–0646
MOTOROLA
MC145574
Index–17
NORWAY
S. AFRICA
Arrow Tahonic A/S . . . . . . . . . . . . . . . . . . . . . . . . (47) 2237 8440
Avnet–ASD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (27) 11 4442333
A/S Avnet EMG . . . . . . . . . . . . . . . . . . . . . . . . . . . (47) 6677 3600
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . . (47) 2267 1780
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . (47) 2290 5800
Reutech Components . . . . . . . . . . . . . . . . . . . . (27) 11 3972992
SPAIN
Amitron Arrow . . . . . . . . . . . . . . . . . . . . . . . . . . (34) 91 304 3040
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (34) 91 804 3256
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 113 231 0447
SEI/Selco S.A. . . . . . . . . . . . . . . . . . . . . . . . . . . . (34) 1 637 10 11
PHILIPPINES
Alexan Commercial . . . . . . . . . . . . . . . . . . . . . . (63) 2241–9493
Ultro Technologies Pte. Ltd . . . . . . . . . . . . . . . . . . (65) 545–7811
POLAND
SWEDEN
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (48) 713 422944
Arrow–Th:s AB . . . . . . . . . . . . . . . . . . . . . . . . . . (46) 8 56265500
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . (48) 22 61 89202
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (48) 22 224337
SEI/Elbatex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (48) 22 6217122
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . . (48) 22 6465227
Avnet EMG AB . . . . . . . . . . . . . . . . . . . . . . . . . . (46) 8 629 14 00
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . . (46) 405 92100
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (46) 8 730 5000
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . (46) 8 441 5470
PORTUGAL
SWITZERLAND
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . . (41) 1 7456161
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (41) 1204 6464
SEI/Elbatex AG . . . . . . . . . . . . . . . . . . . . . . . . . . (41) 56 4375111
Spoerle Electronic . . . . . . . . . . . . . . . . . . . . . . . . . (41) 1 8746262
Amitron Arrow . . . . . . . . . . . . . . . . . . . . . . . . . . . (35) 11471 4182
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 113289 0040
SEI/Selco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (35) 12973 8203
ROMANIA
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (401) 6343129
TAIWAN
RUSSIA
Avnet–Mercuries Co., Ltd . . . . . . . . . . . . . . . . (886)2 516–7303
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . . (7) 095 9761176
Solomon Technology Corp. . . . . . . . . . . . . . . . (886)2 788–8989
Strong Electronics Co. Ltd. . . . . . . . . . . . . . . . (886)2 917–9917
Macro Group – Moscow . . . . . . . . . . . . . . . . . . (7) 095 30600266
Macro Group – St. Petersburg . . . . . . . . . . . . . . . . . . (7) 81 25311476
THAILAND
SCOTLAND
Sahapiphat Ltd. . . . . . . . . . . . . . . . . . . . . . . . . . . (662) 237–9474
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (44) 141 4202070
Ultro Technologies Pte. Ltd. . . . . . . . . . . . . . . . . . (65) 540–8328
Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 141 9413999
TURKEY
SINGAPORE
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (90) 216 4631352
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (65) 788–0200
UNITED KINGDOM
Arrow Electronics (UK) Ltd . . . . . . . . . . . . . . . (44) 1 234 270027
Future Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . (65) 479–1300
Strong Pte. Ltd . . . . . . . . . . . . . . . . . . . . . . . . . . . . (65) 276–3996
Uraco Technologies Pte Ltd. . . . . . . . . . . . . . . . . . (65) 545–7811
Avnet EMG . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 1 438 788300
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . (44) 1 628 783688
Farnell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 1 132 636311
Future Electronics Ltd. . . . . . . . . . . . . . . . . . . (44) 1 753 763000
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 1 628 606000
Newark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44) 1 420 543333
SLOVAKIA
Macro Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (42) 89634181
SEI/Elbatex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (42) 17295007
SLOVENIA
EBV Elektronik . . . . . . . . . . . . . . . . . . . . . . . . . (386) 611 330216
SEI/Elbatex . . . . . . . . . . . . . . . . . . . . . . . . . . . . (386) 611 597198
Index–18
MC145574
MOTOROLA
3/1/99
MOTOROLA WORLDWIDE SALES OFFICES
UNITED STATES
ALABAMA
CANADA
ALBERTA
Calgary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (403)216–2190
Huntsville . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (256)464–6800
BRITISH COLUMBIA
Vancouver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (604)606–8502
ALASKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (800)635–8291
CALIFORNIA
Calabasas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)878–6800
Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (949)753–7360
Los Angeles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)878–6800
San Diego . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (619)541–2163
Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)749–0510
ONTARIO
Ottawa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (613)226–3491
Mississauga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (905)501–3500
QUEBEC
Montreal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (514)333–3300
COLORADO
INTERNATIONAL
Denver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)337–3434
AUSTRALIA
CONNECTICUT
Melbourne . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (61–3)9887 0711
Wallingford . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (203)949–4100
Sydney . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (61–2)9437 8944
FLORIDA
BRAZIL
Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (813)524–4177
Sao Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55(011)3030–5244
Maitland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)628–2636
CHINA
GEORGIA
Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86–10–65642288
Atlanta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)729–7100
Guangzhou . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86–20–87537888
Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86–21–63747668
Tianjin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86–22–25325050
CZECH REPUBLIC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (420) 2 21852222
IDAHO
Boise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (208)323–9413
ILLINOIS
Chicago/Schaumburg . . . . . . . . . . . . . . . . . . . . . . (847)413–2500
INDIANA
FINLAND
Indianapolis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (317)571–0400
Helsinki . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 6866 880
Kokomo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (765)455–5100
Direct Sales Lines . . . . . . . . . . . . . . . . . . . . . . (358) 9 6866 8844
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (358) 9 6866 8845
MARYLAND
Columbia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (410)381–1570
FRANCE
MASSACHUSETTS
Marlborough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (508)357–8207
Woburn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)932–9700
Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33134 635900
GERMANY
Langenhagen/Hanover . . . . . . . . . . . . . . . . . . . . 49(511)786880
MICHIGAN
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 89 92103–0
Nuremberg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 911 96–3190
Sindelfingen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7031 79 710
Wiesbaden . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 611 973050
HONG KONG
Kwai Fong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852–2–610–6888
Detroit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (248)347–6800
MINNESOTA
Minnetonka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)932–1500
MISSOURI
St. Louis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (314)275–7380
NEW JERSEY
Fairfield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (973)808–2400
Tai Po . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852–2–666–8333
HUNGARY
NEW YORK
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (36) 1 250 83 29
Fairport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (716)425–4000
INDIA
Fishkill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (914)896–0511
Hauppauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (516)361–7000
Bangalore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91–80–5598615
ISRAEL
NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (919)870–4355
Herzlia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972–9–9522333
ITALY
OHIO
Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39(2)82201
Cleveland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (440)349–3100
JAPAN
Dayton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (937)438–6800
Kyusyu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–92–725–7583
OREGON
Gotanda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–3–5487–8311
Nagoya . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–52–232–3500
Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–6–305–1801
Sendai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–22–268–4333
Takamatsu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–878–37–9972
Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81–3–3440–3311
Portland . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)641–3681
PENNSYLVANIA
Colmar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (215)997–1020
Philadelphia/Horsham . . . . . . . . . . . . . . . . . . . . . (215)957–4100
TENNESSEE
Knoxville . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (423)584–4841
KOREA
TEXAS
Pusan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82(51)462–2977
Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)502–2100
Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82–2–3440–7200
Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (281)251–0006
Plano . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (972)516–5100
MALAYSIA
Penang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60(4)228–2514
WASHINGTON
MEXICO
Bellevue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (425)454–4160
Chihuahua . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52(14)39–3120
Seattle (toll free) . . . . . . . . . . . . . . . . . . . . . . . . . . (206)622–9960
Mexico City . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52(5)282–0230
Guadalajara . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52(36)78–0750
Zapopan Jalisco . . . . . . . . . . . . . . . . . . . . . . . . . . 52(36)78–0750
Marketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52(36)21–2023
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . 52(36)669–9160
WISCONSIN
Milwaukee/Brookfield . . . . . . . . . . . . . . . . . . . . . . (414)792–0122
Field Applications Engineering Available
Through All Sales Offices
NETHERLANDS
Best . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (31)4993 612 11
MOTOROLA
MC145574
Index–19
PHILIPPINES
NORTH AMERICA
FULL LINE REPRESENTATIVES
Manila . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (63)2 807–8455
Paranaque . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (63)2 824–4551
Salcedo Village . . . . . . . . . . . . . . . . . . . . . . . . . . (63)2 810–0762
ARIZONA, Tempe
S&S Technologies, Inc. . . . . . . . . . . . . . . . . . . . . (602)414–1100
CALIFORNIA, Loomis
Galena Technology Group . . . . . . . . . . . . . . . . . . (916)652–0268
INDIANA, Indianapolis
Bailey’s Electronics . . . . . . . . . . . . . . . . . . . . . . . . (317)848–9958
NEVADA, Clark County
S&S Technologies, Inc. . . . . . . . . . . . . . . . . . . . . (602)414–1100
NEVADA, Reno
Galena Tech. Group . . . . . . . . . . . . . . . . . . . . . . . (702)746–0642
NEW MEXICO, Albuquerque
S&S Technologies, Inc. . . . . . . . . . . . . . . . . . . . . (602)414–1100
TEXAS, El Paso
S&S Technologies, Inc. . . . . . . . . . . . . . . . . . . . . (915)833–5461
UTAH, Salt Lake City
Utah Comp. Sales, Inc. . . . . . . . . . . . . . . . . . . . . (801)572–4010
POLAND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (48) 34 27 55 75
PUERTO RICO
Rio Piedras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)282–2300
RUSSIA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7) 095 929 90 25
SCOTLAND
East Kilbride . . . . . . . . . . . . . . . . . . . . . . . . . . . . (44)1355 565447
SINGAPORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . (65)4818188
SPAIN
Madrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457–8204
or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457–8254
SWEDEN
Solna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46(8)734–8800
SWITZERLAND
Geneva . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41(22)799 11 11
Zurich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41(1)730–4074
WASHINGTON, Spokane
Doug Kenley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (509)924–2322
TAIWAN
Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886(2)27058000
NORTH AMERICA
HYBRID/MCM COMPONENT SUPPLIERS
THAILAND
Bangkok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66(2)254–4910
Chip Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (407)298–7100
Elmo Semiconductor . . . . . . . . . . . . . . . . . . . . . . (818)768–7400
Minco Technology Labs Inc. . . . . . . . . . . . . . . . . (512)834–2022
Semi Dice Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (310)594–4631
TURKEY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (90) 212 274 66 48
UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1 (296)395252
Index–20
MC145574
MOTOROLA
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Motorola Japan Ltd.: SPD, Strategic Planning Office, 141,
4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan
81-3-5487-8488
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RMFAX0@email.sps.mot.com
– Touchtone 1-602-244-6609
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Customer Focus Center: 1-800-521-6274
Mfax is a trademark of Motorola, Inc.
For the most current information regarding this product, contact Motorola on the World Wide Web at
http://www.motorola.com/isdn-solutions
MC145574/D
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Motorola : Semiconductors : Networking : Products : Timing, Interconnect, Access and Datapath : Access and Datapath : ISDN : MC145574A
MC145574A : ISDN S/T-Interface
Page Contents
Transceiver II
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Features
Parametrics
Documentation
Development
Tools/Boards
Orderable Parts
The MC145574A second-generation S/T-Interface Transceiver provides an economical VLSI
Layer 1 interface for the transportation of two 64 kbps B channels and one 16 kbps D channel
between the network termination (NT) and terminal equipment (TE). The MC145574A
conforms to CCITT I.430, ANSI T1.605, and ETSI ETS 300 012 specifications.
●
The device provides the modulation/line-drive and demodulation/line-receive functions
required of the interface. In addition, it provides activation/deactivation, error monitoring,
framing, bit, and octet timing. The MC145574A provides the control signals for the interface
to the Layer 2 devices. Complete multiframe capability is provided.
Other Info
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●
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FAQs
Literature Services
68K/ColdFire®
Networking
The Interchip Digital Link (IDL2) is supported for the exchange of 2B+D channel information
between ISDN components and systems. Transceiver operation is programmed through the
industry standard Serial Control Port (SCP). As an alternative to IDL+SCP combination, a
General Circuit Interface (GCI) is provided.
3rd Party Design Help
Link
Block Diagram
MC145574A Features
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Fully-Activated Power Consumption of 90 mW
6-Channel Timeslot Assigner
Interchip Digital Link-2 (IDL2)
General Circuit Interface (GCI)
Compliant with ANSI T1.605-1991, ITU-TI.430, and ETSI ETS 300 012
Control, Status, and Maintenance Functions Accessible Through Serial Control Port (SCP)
Pin-Selectable Network Termination (NT) or Terminal Equipment (TE) Operating Modes
Supports 2.5:1 Transformers for Transmit and Receive
Complete Multiframing Capability (SC1 - SC5 and Q-Channel)
Optional B-Channel Idle, Invert, or Exchange
Supports Full Range of S/T and IDL Loopbacks
Transmit Power Down, Sleep, and Absolute Minimum Power Modes
Crystal or External Clock Input Modes
Support for NT Star and NT Terminal Modes
Supports TE Slave-Slave Mode
Advantages
Minimal Power Requirements Ease Power Management and System Design
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On-Chip Features Mean Fewer External Components and Lower System Cost
Versatile Digital Interface Enhances Design Flexibility
Superior Transmission Performance Results in Increased System Quality and Performance
Evaluation Kit and Comprehensive Applications Support from Motorola
[top]
MC145574A Parametrics
Description
Package
S/T-Interface Transceiver 28-pin SOIC, 32-pin LQFP
[top]
MC145574A Documentation
Errata
ID
Name
Format Size K Rev # Date Last Modified Order Availability
MC145574 G20R1 Errata Sheet Device and
document errata
MC145574DE/D
pdf
72
5
6/28/1999
-
Reports or Presentations
ID
Name
Format Size K Rev # Date Last Modified Order Availability
pdf 61 7/30/2002
Codec, Communication Processor, and ISDN
Orderable Parts
ORDPARTS
-
-
Selector Guide
ID
Name
Format Size K Rev # Date Last Modified Order Availability
Timing and Interconnect Solutions SPS Sales
Guide
SG1012/D
pdf
pdf
81
62
0
0
9/26/2002
6/24/2002
Application Selector Guide Index and Cross-
Reference.
SG2000CR/D
Application Summary - Virtual Private Network
(VPN) Router - Network router for small office
SG2103/D
home office applications, providing a gateway and pdf
firewall for dial-up, cable, or asymmetrical digital
subscriber line (ADSL) internet connections.
74
0
6/24/2002
Users Guide
ID
Name
Format Size K Rev # Date Last Modified Order Availability
MC1455574 ISDN S/T-Interface
Transceiver
MC145574/D
pdf
658
6
1/10/1999
MC145574 ISDN S/T Transceiver
Manual, Rev. 6, Downloadable by
Sections
MC145574_CHAPTERS
html
4
6
1/10/1999
-
[top]
MC145574A Development Tools/Boards
ID
Name
ISDN S/T-Interface Transceiver Evaluation Kit
Vendor ID
MOTOROLA
Order Availability
-
MC145574EVK
[top]
Orderable Parts Information
Budgetary
Price
QTY 1000+
($US)
Order
Availability
Life Cycle Description (code)
PartNumber
Package Info
Remarks
-
PRODUCT STABLE
GROWTH/MATURITY(3)
MC145574ADW
MC145574ADWR2
MC145574APB
SOIC 28W
SOIC 28W
$3.26
$3.32
$3.26
PRODUCT MATURITY/SATURATION(4) -
LQFP 32
7*7*1.4P0.8
PRODUCT MATURITY/SATURATION(4) -
LQFP 32
7*7*1.4P0.8
MC145574APBR2
PRODUCT MATURITY/SATURATION(4) -
$5.28
[top]
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