MC14597BDW [MOTOROLA]
8-Bit Bus-Compatible Latches; 8位总线兼容锁存器
| 型号： | MC14597BDW |
| 厂家： | 
MOTOROLA |
| 描述： | 8-Bit Bus-Compatible Latches |
| 文件： | 总9页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC14597B and MC14598B are 8–bit latches, one addressed with an
internal counter and the other addressed with an external binary address.
The 8 latch–outputs are high drive, three–state and bus line compatible. The
drive capability allows direct applications with MPU systems such as the
Motorola 6800 family.
L SUFFIX
CERAMIC
CASE 620
With MC14597B, a 3–bit address counter (clocked on the falling edge of
Increment) selects the appropriate latch. The latches of the MC14598B are
accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on
the MC14597B to indicate the position of the Address counter.
All 8 outputs from the latches are available in parallel when Enable is in the
low state. Data is entered into a selected latch from the Data pin when the
Strobe is high. Master reset is available on both parts.
P SUFFIX
PLASTIC
CASE 648
•
•
•
•
•
•
•
•
•
Serial Data Input
D SUFFIX
SOIC
CASE 751B
Three–State Bus Compatible Parallel Outputs
Three–State Control Pin (Enable) TTL Compatible Input
Open Drain Full Flag (Multiple Latch Wire–O Ring)
Master Reset
Level Shifting Inputs on All Except Enable
Diode Protection — All Inputs
Supply Voltage Range — 3.0 Vdc to 18 Vdc
Capable of Driving TTL Over Rated Temperature Range
With Fanout as Follows:
ORDERING INFORMATION
MC14597BCP
MC14597BCL
MC14597BDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
1 TTL Load
4 LSTTL Loads
L SUFFIX
CERAMIC
CASE 726
BLOCK DIAGRAMS
MC14597B
RESET
2
4
ENABLE
RESET
LOGIC
P SUFFIX
PLASTIC
CASE 707
D0
RESET
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
D1
D2
D3
D4
D5
D6
D7
DATA
STROBE
3
6
1
D0
DATA
ORDERING INFORMATION
15 D1
14 D2
13 D3
12 D4
11 D5
10 D6
MC14598BCP
MC14598BCL
Plastic
Ceramic
THREE
STATE
ENABLE
FULL
3–BIT
ADDRESS
DECODER
8
ADDRESS
COUNTER
LATCHES
OUTPUT
BUFFERS
T
A
= – 55° to 125°C for all packages.
STROBE
INCREMENT
7
9
D7
INCREMENT
FULL
V
V
= 16
= 8
DD
SS
LOGIC
V
SS
5
D0
RESET
DATA
ENABLE
NC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
FULL
D1
D2
D3
D4
D5
D6
D7
A2
MC14598B
ENABLE
OUTPUT
TRUTH TABLE
4
RESET
DATA
STROBE
2
3
6
Enable
Outputs
1
D0
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
THREE
STATE
1
0
High Impedance
STROBE
A0
8
A0
A1
7
8
D
n
OUTPUT
BUFFERS
LATCHES
ADDRESS
DECODER
A2 10
D
= State of nth latch
n
A1
V
V
= 18
DD
V
= 9
SS
SS
NC = NO CONNECTION
REV 3
1/94
Motorola, Inc. 1995
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
V
DD
– 0.5 to + 18.0
V
Input Voltage, Enable (DC or Transient)
– 0.5 to V
DD
+ 0.5
+ 12
V
in
in
V
Input Voltage, All other Inputs
(DC or Transient)
– 0.5 to V
V
DD
operation, V and V
should be constrained
in out
V
Output Voltage (DC or Transient)
– 0.5 to V
+ 0.5
V
out
DD
to the range V
(V or V
)
V
DD
.
SS in out
I , lout Input or Output Current (DC or Transient),
in
± 10
mA
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
per Pin
SS
or V ). Unused outputs must be left open.
DD
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65 C To 125 C Ceramic
“L” Packages: – 12 mW/ C From 100 C To 125 C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage** — Enable “0” Level
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
0.8
1.6
2.4
—
—
—
1.1
2.2
3.4
0.8
1.6
2.4
—
—
—
0.8
1.6
2.4
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
“0” Level
V
Vdc
Vdc
IH
(V = 0.5 or 4.5 Vdc)
5.0
10
15
2.0
6.0
10
—
—
—
2.0
6.0
10
1.9
3.1
4.3
—
—
—
2.0
6.0
10
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Input Voltage
Other Inputs
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
(V = 0.5 or 4.5 Vdc) “1” Level
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
(Full — Sink Only)
Source
Sink
I
mAdc
OH
(V
OH
(V
OH
(V
OH
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
5.0
10
1 5
– 1.0
—
—
–
—
—
– 1.0
—
—
– 2.0
– 6.0
– 12
—
—
—
– 1.0
—
—
—
—
—
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
1.6
—
—
—
—
—
1.6
—
—
3.2
6.0
12
—
—
—
1.6
—
—
—
—
—
mAdc
OL
Input Current
Three–State Leakage Current
I
15
15
—
—
—
—
±0.1
±0.1
—
—
—
—
±0.00001
±0.00001
5.0
±0.1
±0.1
7.5
—
—
—
±1.0
±3.0
—
µAdc
µAdc
pF
in
I
TL
Input Capacitance (V = 0)
in
C
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
DD
**Total Supply Current at an
**External Load Capacitance of
**130 pF
I
T
5.0
10
I
T
I
T
I
T
= (2.0 µA/kHz) f + I
= (4.0 µA/kHz) f + I
= (6.0 µA/kHz) f + I
µAdc
DD
DD
DD
†Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
MC14597B MC14598B
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (T = 25 C, C = 130 pF + 1 TTL Load)
A
L
All Types
Typ #
V
Vdc
DD
Characteristic
Output Rise and Fall Time
Symbol
Unit
Min
Max
t
t
,
ns
TLH
t
t
t
, t
= (0.5 ns/pF) C + 35 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
= (0.2 ns/pF) C + 25 ns
L
TLH THL
, t
TLH THL
= (0.16 ns/pF) C + 20 ns
L
Propagation Delay Time
Enable to Output
t
t
,
ns
ns
ns
PLH
5.0
10
15
—
—
—
160
125
100
320
250
200
PHL
Strobe to Output
5.0
10
15
—
—
—
200
100
80
400
200
160
Strobe to Full (MC14597B only)
Reset to Output
5.0
10
15
—
—
—
200
100
80
400
200
160
5.0
10
15
—
—
—
175
90
70
350
180
140
Pulse Width
Enable
t
,
WH
t
5.0
10
15
320
240
160
160
120
80
—
—
—
WL
Strobe
5.0
10
15
200
100
80
100
50
40
—
—
—
Increment (MC14597B only)
Reset
5.0
10
15
200
100
80
100
50
40
—
—
—
5.0
10
15
300
160
100
150
80
50
—
—
—
Setup Time
Data
t
su
5.0
10
15
100
50
35
50
25
20
—
—
—
Address (MC14598B only)
Increment (MC14597B only)
5.0
10
15
200
100
70
100
50
35
—
—
—
5.0
10
15
400
200
170
200
100
85
—
—
—
Hold Time
Data
t
h
ns
5.0
10
15
100
50
35
50
25
20
—
—
—
Address (MC14598B only)
Reset Removal Time
5.0
10
15
100
50
35
50
25
20
—
—
—
t
5.0
10
15
20
20
20
– 25
– 15
– 10
—
—
—
ns
rem
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B
3
MC14597B FUNCTION DIAGRAM
V
DD
ENABLE
RESET
4
2
5
FULL
TO OTHER
LATCHES
V
DD
R
D
Q
CLK
STROBE
DATA
6
3
V
DD
1
D
0
TO OTHER
LATCHES
SEVEN
V
SELECT
ONE LATCH
SS
ZERO
SELECT
R
15 D1
14 D2
13 D3
12 D4
11 D5
10 D6
3 STAGE COUNTER
AND DECODER
ADDITIONAL 7 LATCHES
CLK
9
D7
INCREMENT
7
MC14597B TIMING DIAGRAMS
D6 (INTERNAL)
D7 (INTERNAL)
INCREMENT
t
t
WH
WL
20 ns
90%
t
su
DATA
STROBE
FULL
10%
t
t
h
su
90%
10%
20 ns
t
t
PHL
W
t
rem
50%
RESET
t
NOTE: Enable in High state.
W
t
t
TLH
THL
90%
90%
D
1
n
10%
10%
t
PHL
FULL
ENABLE
*
*
t
WL
* 1.4 V with V
NOTES:
= 5.0 V
DD
1. High–impedance output state (another device controls bus).
2. Reset in High state.
MC14597B MC14598B
MOTOROLA CMOS LOGIC DATA
4
MC14598B FUNCTION DIAGRAM
RESET
DATA
2
3
V
DD
1
D0
TO OTHER
LATCHES
STROBE
ENABLE
6
4
V
SS
EACH LATCH
TO OTHER
ZERO
LATCHES
SELECT
17 D1
16 D2
15 D3
14 D4
13 D5
12 D6
11 D7
A0
A1
7
8
ADDRESS
DECODER
ADDITIONAL 7 LATCHES
A2 10
(M.S.B)
MC14598B TIMING DIAGRAM
90%
10%
50%
t
t
PLH
THL
90%
10%
D7
50%
1
t
t
t
TLH
PLH
PHL
RESET
A0, A1, A2
DATA
20 ns
t
W
90%
10%
50%
t
t
h
su
t
t
h
su
90%
10%
90%
10%
50%
STROBE
ENABLE
20 ns
t
W
20 ns
*
t
W
* 1.4 V with V
NOTES:
= 5.0 V
DD
1. High–impedance output state (another device controls bus).
2. Output Load as for MC14597B.
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B
5
LATCH TRUTH TABLE
Address
TRUTH TABLE FOR MC14597B
Address
Other
Strobe
Reset
Latch
Latches
Increment
Enable
Reset
Counter
Full
—
0
1
1
1
0
*
Data
0
*
*
X
X
1
0
1
1
0
1
Count Up
No Change
Reset to Zero
No Change
—
X
0
X
X
Set to One
Set to One
* = No change in state of latch
X = Don’t care
If at
ADDRESS 7
To Zero on
Falling Edge
of STROBE
X
1
1
X = Don’t care
TEST LOAD
ALL OUTPUTS
+5.0 V
R
= 2.5 k
L
D
n
130 pF
11.7 k
Circuit diagrams external to or containing Motorola prod-
ucts are included as a means of illustration only. Complete
information sufficient for construction purposes may not be
fully illustrated. Although the information herein has been
carefully checked and is believed to be reliable. Motorola
assumes no responsibility for inaccuracies. Information here-
in does not convey to the purchaser any license under the
patent rights of Motorola or others.
The information contained herein is for guidance only, with
no warranty of any type, expressed or implied. Motorola re-
serves the right to make any changes to the information and
the product(s) to which the information applies and to discon-
tinue manufacture of the product(s) at any time.
MC14597B MC14598B
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14597B MC14598B
7
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
L SUFFIX
CERAMIC DIP PACKAGE
CASE 726–04
ISSUE G
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
18
1
10
9
–B–
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.910
0.295
0.200
0.021
0.070
MIN
22.35
6.10
–––
0.38
1.40
MAX
23.11
7.49
5.08
0.53
1.78
0.880
0.240
–––
0.015
0.055
L
C
N
F
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.125
0.012
0.170
0.20
3.18
0.30
4.32
–T–
SEATING
PLANE
K
0.300 BSC
7.62 BSC
M
F
G
0
15
0
15
0.020
0.040
0.51
1.02
J 18 PL
D 18 PL
M
S
0.25 (0.010)
T B
M
S
0.25 (0.010)
T
A
MC14597B MC14598B
8
MOTOROLA CMOS LOGIC DATA
P SUFFIX
PLASTIC DIP PACKAGE
CASE 707–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
18
10
9
B
1
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
22.22
6.10
3.56
0.36
1.27
MAX
23.24
6.60
4.57
0.56
1.78
MIN
MAX
0.915
0.260
0.180
0.022
0.070
L
0.875
0.240
0.140
0.014
0.050
C
K
G
H
J
K
L
2.54 BSC
0.100 BSC
N
1.02
0.20
2.92
1.52
0.30
3.43
0.040
0.008
0.115
0.060
0.012
0.135
J
M
F
D
SEATING
PLANE
H
G
7.62 BSC
0.300 BSC
M
N
0
0.51
15
1.02
0
15
0.040
0.020
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MC14597B/D
◊
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