MC1495P [MOTOROLA]
LINEAR FOUR-QUADRANT MULTIPLIER; 线性四象限乘法器
| 型号： | MC1495P |
| 厂家： | 
MOTOROLA |
| 描述： | LINEAR FOUR-QUADRANT MULTIPLIER |
| 文件： | 总16页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC1495/D
The MC1495 is designed for use where the output is a linear product of
two input voltages. Maximum versatility is assured by allowing the user to
select the level shift method. Typical applications include: multiply, divide*,
square root*, mean square*, phase detector, frequency doubler, balanced
modulator/demodulator, and electronic gain control.
LINEAR
FOUR-QUADRANT
MULTIPLIER
• Wide Bandwidth
• Excellent Linearity:
SEMICONDUCTOR
TECHNICAL DATA
2% max Error on X Input, 4% max Error on Y Input Over Temperature
1% max Error on X Input, 2% max Error on Y Input at + 25°C
• Adjustable Scale Factor, K
• Excellent Temperature Stability
• Wide Input Voltage Range: ± 10 V
• ±15 V Operation
*When used with an operational amplifier.
14
1
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)
MAXIMUM RATINGS (T = + 25°C, unless otherwise noted.)
A
Rating
Symbol
Value
Unit
Applied Voltage
∆V
30
Vdc
14
(V –V , V –V , V –V , V –V , V –V ,
2
1
1
8
14 12
1
7
1
9
9
7
1
8
1
4
1
V –V , V –V , V –V , V –V , V –V )
12
7
4
7
Differential Input Signal
Maximum Bias Current
V
V –V
–V
± (6+I R )
13
Vdc
mA
°C
12
4
9
X
P SUFFIX
PLASTIC PACKAGE
CASE 646
± (6+I R )
8
3
Y
I
I
10
10
3
13
Operating Temperature Range
Storage Temperature Range
T
A
MC1495
MC1495B
0 to +70
– 40 to +125
T
– 65 to +150
°C
stg
ORDERING INFORMATION
Tested Operating
Temperature Range
Device
Package
MC1495D
MC1495P
MC1495BP
SO–14
T
= 0° to + 70°C
A
Plastic DIP
Plastic DIP
T
= – 40° to +125°C
A
Motorola, Inc. 1996
Rev 0
MC1495
ELECTRICAL CHARACTERISTICS (+V = + 32 V , –V = –15 V, T = + 25°C, I = I = 1.0 mA, R = R = 15 kΩ, R = 11 kΩ, unless
A
3
13
X
Y
L
otherwise noted.)
Characteristics
Figure
Symbol
Min
Typ
Max
Unit
Linearity (Output Error in percent of full scale)
5
%
T
A
= + 25°C
–10 < V < +10 (V = ±10 V)
E
E
–
–
±1.0
± 2.0
±1.0
± 2.0
X
Y
RX
RY
–10 < V < +10 (V = ±10 V)
Y
Low
X
T
A
= T
to T
High
–10 < V < +10 (V = ±10 V)
E
RX
E
RY
–
–
±1.5
± 3.0
± 2.0
± 4.0
X
Y
X
–10 < V < +10 (V = ±10 V)
Y
Square Mode Error (Accuracy in percent of full scale after
Offset and Scale Factor adjustment)
5
E
SQ
%
T
T
A
= + 25°C
–
–
± 0.75
±1.0
–
–
A
= T
to T
Low
High
Scale Factor (Adjustable)
–
7
K
–
0.1
–
2R
L
K =
1
3
R R
X Y
Input Resistance (f = 20 Hz)
R
R
–
–
30
20
–
–
MΩ
inX
inY
Differential Output Resistance (f = 20 Hz)
Input Bias Current
8
6
R
–
300
–
kΩ
µA
O
T
= + 25°C
I
I
–
–
2.0
2.0
8.0
12
A
bx, by
(I + I
9
)
(I + I )
4 8
12
I
=
T
= T
= T
to T
, I
=
bx
A
Low
High
by
2
2
Input Offset Current
|I – I
6
µA
|
T = + 25°C
A
Low
|I |, |I
iox ioy
|
–
–
0.4
0.4
1.0
2.0
9
4
12
|I – I |
T
A
to T
High
8
Average Temperature Coefficient of Input Offset Current
= T to T
6
6
|TC
|
nA/°C
µA
lio
T
–
–
–
2.5
–
A
Low
Output Offset Current
|I – I |
High
T
= + 25°C
|I
|
10
20
50
100
A
OO
T
= T
to T
14
Average Temperature Coefficient of Output Offset Current
= T to T
2
A
Low
High
6
|TC
|
nA/°C
IOO
T
A
20
–
Low
Frequency Response
3.0 dB Bandwidth, R = 11 kΩ
High
9,10
BW
(3dB)
–
–
–
–
3.0
80
750
30
–
–
–
–
MHz
MHz
kHz
kHz
L
L
3.0 dB Bandwidth, R = 50 Ω (Transconductance Bandwidth)
T
BW(3dB)
3° Relative Phase Shift Between V and V
fφ
fθ
X
Y
1% Absolute Error Due to Input-Output Phase Shift
Common Mode Input Swing
(Either Input)
11
11
12
CMV
Vdc
±10.5
±12
–
Common Mode Gain
(Either Input)
T
= + 25°C
A
CM
– 50
– 40
– 60
– 50
–
–
dB
A
T
A
= T
to T
Low
High
Common Mode Quiescent
Output Voltage
V
O1
V
O2
–
–
21
21
–
–
Vdc
Differential Output Voltage Swing Capability
Power Supply Sensitivity
9
V
–
±14
–
V
pk
O
+
–
12
S
S
–
–
5.0
10
–
–
mV/V
Power Supply Current
DC Power Dissipation
12
12
I
–
–
6.0
7.0
mA
7
P
135
170
mW
D
NOTES: 1. T
= +70°C for MC1495
= +125°C for MC1495B
T
= 0°C for MC1495
= – 40°C for MC1495B
High
Low
2
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 1. Multiplier Transfer Characteristic
Figure 2. Transconductance Bandwidth
20
10
10
8.0
6.0
+
X
KXY
Y
4.0
2.0
1
k =
10
0
0
– 2.0
– 4.0
– 6.0
– 8.0
–10
–10
V
V
X
Y
– 20
– 30
–10 – 8.0 – 6.0 – 4.0 – 2.0
0
2.0
4.0
6.0
8.0
10
1.0
10
100
1000
f, FREQUENCY (MHz)
V
, INPUT VOLTAGE (V)
X
Figure 3. Circuit Schematic
+
–
2
14
Output (KXY)
1
Q5 Q6
Q7
Q8
+
–
–
+
8
4
9
X Input
Y Input
12
Q2
Q3
Q4
Q1
4.0 k
4.0 k
4.0 k
4.0 k
11
10
13
5
6
3
500
500
500
500
500
500
V–
7
This device contains 16 active transistors.
Figure 4. Linearity (Using Null Technique)
V+
0.1
= 27 k R = 7.5 k
X
µF
+15 V
R
10 k
V
′
Y
Y
+
3.0 k
3.0 k
10 k
10 k
40 k
5
6
10
11
V
Y
10 k
1
2
E
s
+
+
4
7
3.0 k
V
2
3
7
10 k
V′
X
8
X
+
–
MC1495
2
10 k
9
8
6
8
MC1741C
10 V
10 k
6
–
14
V
E
MC1741C
5
3
12
3
7
13
12 k
1
33 k
Output
Offset
Adjust
5
Offset Adjust
See Figure 13
1
4
13 k
4
10 k
5.0 k
Scale
V–
Factor
Adjust
–15 V
0.1 µF
NOTE: Adjust “Scale Factor Adjust” for a null in V .This schematic for
E
illustrative purposes only, not specified for test conditions.
3
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 5. Linearity (Using X-Y Plotter Technique)
R
= 15 k
6
R = 15 k
X
Y
32 V
To Pin
4 or 9
R1
9.1 k
5
10
11
0.1 µF
4
9
1
V
Y
–
+
R
= 11 k
L1
V
Z
Y
X
MC1495
8
2
X–Y
Plotter
Plotter
Y-Input
Plotter
X-Input
R
= 11 k
L1
V
Offset Adjust
(See Figures 13 and 14)
O
12
14
3
I
I
7
13
3
13
12 k
R13 = 13.7 k
R3
5.0 k
Scale
Factor
Adjust
0.1 µF
–15 V
Figure 6. Input and Output Current
Figure 7. Input Resistance
+ 32 V
R
= 15 k
R
= 15 k
R = 15 k R = 15 k
Y X
+ 32 V
Y
X
e
= 1.0 Vrms
20 Hz
1
5
6
10
11
5
6
10
11
1.0 M
1.0 M
9.1 k
4
9
4
9
1
2
9.1 k
11 k
e
1
1
I
4
I
2
e
1
MC1495
MC1495
8
I
e
8
9
8
5.6 k
2
2
I
14
14
11 k
e
12
14
12
I
2
1.0 M
0.1 µF
3
7
13
3
7
13
I
I
= 1.0 mA
12
13
1.0 M
12 k
12 k
13.75 k
+
12 k
0.1 µF
I
= 1.0 mA
3
0.1 µF
–
5.0 k
5.0 k
Scale
Factor
Adjust
5.0 k
0.1
–15 V
µF
e
e
1
2
R
inX
= R
= R
–2
–15 V
inY
Figure 8. Output Resistance
Figure 9. Bandwidth (R = 11 kΩ)
L
R
= 15 k
R
= 15 k
+ 32 V
R = 15 k R = 15 k
Y X
+ 32 V
Y
X
5
6
10
11
4
9
5
6
10
11
9.1 k
11 k
4
9
1
2
9.1 k
11 k
e
in
= 1.0 Vrms
50
1
2
e
e
in
2
RL = 11 k
MC1495
MC1495
8
8
14
13
11 k
+
12
1.0 V
12
14
–
3
7
13
7
3
e
0.1 µF
1
R13
13.7 k
0.1
µF
1.0 Vrms
20 Hz
12 k
12 k
e
o
0.1 µF
C
< 3.0 pF
L
13.7 k
Scale
Factor
Adjust
Scale
Factor
Adjust
5.0 k
5.0 k
0.1
µF
e
1
2
–15V
–15 V
R
= R
L
–2
O
e
4
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 11. Common Mode Gain and
Common Mode Input Swing
Figure 10. Bandwidth (R = 50 Ω)
L
R
= 510
6
R = 510
X
+ 32 V
+ 15 V
15 k
15 k
Y
CMV
(f = 20 Hz)
X
5
10
11
5
6
10
11
4
9
4
9
8
1
2
1.0 k
50
1
2
9.1 k
e
= 1.0 Vrms
50
in
+
e
in
11 k
11 k
+
50
MC1495
MC1495
–
8
14
13
50
12
3
+
–
14
12
+
1.0 V
50
3
7
13
7
–
0.1 µF
CMV
(f = 20 Hz)
V
0.1
V
µF
Y
12 k
R13
13.7k
O
1.0 mA
12 k
12 k
1.0 mA
K = 40
e
o
5.0 k
0.1µF
0.1 µF
Scale
Factor
C
L
< 3.0 pF
O
5.0 k
5.0 k
A
= 20 log
or 20 log
CM
CMV
Y
Adjust
V
O
–15V
–15 V
CMV
X
Figure 13. Offset Adjust Circuit
Figure 12. Power Supply Sensitivity
+
V
+ 32 V
+ 32 V (V+)
15 k
15 k
10
R
2.0 k
5
6
11
4
9
1
2
9.1 k
11 k
11 k
Pot #1
Pot #2
To Pin 8
Y Offset
Adjust
To Pin 12
X Offset
Adjust
MC1495
8
10 k 10 k
2.0 k
14
12
4.3 k
3
7
13
13.7 k
0.1
6.2 V
2.0 k
+
V
V
V
15 V 32 V
10 k 22 k
0.1 µF
O2 O1
µ
F
10 k
R
|
∆
(V
– V )|
O2
–15 V
O1
V+
2N2905A
or Equivalent
S+ =
S– =
22 k
∆
|∆
(V
– V )|
O2
O1
V–
–15 V
(V–)
–15 V
∆
Figure 14. Offset Adjust Circuit (Alternate)
+
V
R
5.1 V
Pot #1
Pot #2
To Pin 8
Y Offset
Adjust
To Pin 12
X Offset
Adjust
10 k
10 k
5.1 V
+
V
R
15 V
32 V
2.0 k
2.0 k 5.1 k
–15 V
5
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 15. Linearity versus Temperature
Figure 16. Scale Factor versus Temperature
2.0
0.110
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.105
0.100
0.095
E
K Adjusted to 0.100 at 25
°C
RY
E
RX
0.2
0
–55
–25
0
25
50
75
100
125
–55
–25
0
25
50
75
100
125
T
, AMBIENT TEMPERATURE (
°C)
T
, AMBIENT TEMPERATURE (°C)
A
A
Figure 17. Error Contributed by Input
Differential Amplifier
Figure 18. Error Contributed by
Input Differential Amplifier
1.0
0.8
0.6
1.0
0.8
0.6
V
= V
=
±
10 V Max
X
I
Y
V
= V
=
±
5.0 V Max
X
I
Y
= I = 1.0 mAdc
= I = 1.0 mAdc
3
13
3
13
0.4
0.2
0
0.4
0.2
0
6.0
8.0
R
10
12
14
10
12
14
R
16
18
20
4.0
or R (kΩ)
or R (k
Y
Ω)
X
Y
X
Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7
14
12
10
8.0
Minimum
6.0
4.0
Recommended
2.0
0
0
2.0
4.0
6.0
8.0
10
12
14
16
18
|V | or |V | (V)
1
7
6
MOTOROLA ANALOG IC DEVICE DATA
MC1495
OPERATION AND APPLICATIONS INFORMATION
Theory of Operation
3 dB Bandwidth and Phase Shift
The MC1495 is a monolithic, four-quadrant multiplier
which operates on the principle of variable
transconductance. A detailed theory of operation is covered
in Application Note AN489, Analysis and Basic Operation of
the MC1595. The result of this analysis is that the differential
output current of the multiplier is given by:
Bandwidth is primarily determined by the load resistors
and the stray multiplier output capacitance and/or the
operational amplifier used to level shift the output. If
wideband operation is desired, low value load resistors
and/or a wideband operational amplifier should be used.
Stray output capacitance will depend to a large extent on
circuit layout.
Phase shift in the multiplier circuit results from two
sources: phase shift common to both X and Y channels (due
to the load resistor-output capacitance pole mentioned
above) and relative phase shift between X and Y channels
(due to differences in transadmittance in the X and Y
channels). If the input to output phase shift is only 0.6°, the
output product of two sine waves will exhibit a vector error of
2V V
R R I
X Y 3
X Y
I
A
– I = ∆I =
B
where, I and I are the currents into Pins 14 and 2,
A
B
respectively, and V and V are the X and Y input voltages at
X
Y
the multiplier input terminals.
DESIGN CONSIDERATIONS
General
1%. A 3° relative phase shift between V and V results in a
X
Y
vector error of 5%.
The MC1495 permits the designer to tailor the multiplier to
a specific application by proper selection of external
components. External components may be selected to
optimize a given parameter (e.g. bandwidth) which may in
turn restrict another parameter (e.g. maximum output voltage
swing). Each important parameter is discussed in detail in the
following paragraphs.
Maximum Input Voltage
V
, V input voltages must be such that:
X(max) Y(max)
V
<I
R
Y
X(max) 13
V (max) <I R
3 Y
Y
Exceeding this value will drive one side of the input amplifier
to “cutoff” and cause nonlinear operation.
Linearity, Output Error, E
or E
Current I and I
(observing power dissipation limitation) between 0.5 mA and
2.0 mA, approximately 1.0 mA. Then R and R can be
determined by considering the input signal handling
requirements.
are chosen at a convenient value
RX
RY
3
13
Linearity error is defined as the maximum deviation of
output voltage from a straight line transfer function. It is
expressed as error in percent of full scale (see figure below).
X
Y
V
O
For V
= V
= 10 V;
X(max)
Y(max)
+10 V
10 V
1.0 mA
V
R
X
= R
>
= 10 kΩ.
E(max)
Y
+10V
or V
2V
V
Y
R I
Y 3
X
V
x
y
The equation I – I
=
=
A
B
R
X
2V
V
Y
X
Y
+
is derived from I – I
A
B
For example, if the maximum deviation, V
±100 mV and the full scale output is 10 V, then the
, is
E(max)
2kT
2kT
qI
(R
+
(R
)
I
3
)
X
qI
3
13
percentage error is:
2kT
2kT
qI
and R >>
13
.
–3
100 x 10
10
with the assumption R >>
Y
V (max)
E
=
X
x 100 = ±1.0%.
qI
3
E
x 100 =
R
V (max
O
)
At T = +25°C and I = I = 1.0 mA,
13
A
3
Linearity error may be measured by either of the following
methods:
1.Using an X-Y plotter with the circuit shown in Figure 5,
2kT 2kT
=
= 52 Ω.
qI
qI
3
13
obtain plots for X and Y similar to the one shown above.
Therefore, with R = R = 10 kΩ the above assumption is
X
Y
valid. Reference to Figure 19 will indicate limitations of
orV duetoV andV . Exceedingtheselimits
2.Use the circuit of Figure 4. This method nulls the level
shifted output of the multiplier with the original input.The
peak output of the null operational amplifier will be equal
V
X(max)
Y(max)
1
7
will cause saturation or “cutoff” of the input transistors. See
Step 4 of General Design Procedure for further details.
to the error voltage, V
.
E (max)
Maximum Output Voltage Swing
One source of linearity error can arise from large signal
nonlinearity in the X and Y input differential amplifiers. To
avoid introducing error from this source, the emitter
degeneration resistors R and R must be chosen large
The maximum output voltage swing is dependent upon the
factors mentioned below and upon the particular circuit being
considered.
X
Y
enough so that nonlinear base-emitter voltage variation can
be ignored. Figures 17 and 18 show the error expected from
this source as a function of the values of R and R with an
For Figure 20 the maximum output swing is dependent
+
upon V for positive swing and upon the voltage at Pin 1 for
negative swing. The potential at Pin 1 determines the
X
Y
operating current of 1.0 mA in each side of the differential
amplifiers (i.e., I = I = 1.0 mA).
quiescent level for transistors Q , Q , Q and Q . This
5
6
7
8
potential should be related so that negative swing at Pins 2 or
14 does not saturate those transistors. See General Design
Procedure for further information regarding selection of
these potentials.
3
13
7
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 20. Basic Multiplier
GENERAL DESIGN PROCEDURE
+
V
Selection of component values is best demonstrated by
the following example. Assume resistive dividers are used at
the X and Y-inputs to limit the maximum multiplier input to ±
R
R
Y
X
R
R
L
I
10
11
5
6
1
R
O
L
9
2
5.0 V [V = V
] for a ± 10 V input [V = V ]
X
Y(max)
X′ Y′(max)
+
+
–
(see Figure 21). If an overall scale factor of 1/10 is desired,
V
V
X
12
4
V
X
O
–
+
14
V
V
(2V ) (2V )
X Y
X′ Y′
MC1495
= 4/10 V
V
Y
then, V
=
=
X
O
10
10
8
Y
–
Therefore, K = 4/10 for the multiplier (excluding the divider
network).
V
= K V
V
Y
I
3
13
7
2R
L
K =
Step 1. The fist step is to select current I and current I
.
3
13
There are no restrictions on the selection of either of these
currents except the power dissipation of the device. I and I
I
R
R
3
X
Y 3
R13
R3
3
13
will normally be 1.0 mA or 2.0 mA. Further, I does not have
3
to be equal to I , and there is normally no need to make
13
–
V
them different. For this example, let
If an operational amplifier is used for level shift, as shown
in Figure 21, the output swing (of the multiplier) is greatly
reduced. See Section 3 for further details.
I = I = 1.0 mA.
3 13
Figure 21. Multiplier with Operational Amplifier Level Shift
– 15 V
– 15 V
+15 V
0.1
µF
R
10 k
R
10 k
R1
3.0 k
X
Y
R0
3.0 k
R0
3.0 k
0.1
µF
7
10
+
11
5
6
7
1
4
10 k
2
3
V
Y
′
+
–
+
4
5
V
Y
10 k
–V
V
Y
6
X
V
=
MC1741C
MC1495
O
10
9
10 k
14
2
+
3
–
V
X
′
V
X
10 k
13
8
12
1
I
3
20 k
18 k
I
13
R13
12 k
R
R
L
L
5.0 k
12 k
Output
Offset
Adjust
R3
P
4
5.0 k
P
3
Scale
Factor
Adjust
Y Offset
Adjust
X Offset
Adjust
P
1
–10V
–10V
≤
≤
V
V
≤
≤
+10V
+10V
X
Y
10 k
P
2
2.0 k
5.1 V
2.0 k
5.1 V
–15 V
+15 V
10 k
8
MOTOROLA ANALOG IC DEVICE DATA
MC1495
To set currents I and I to the desired value, it is only
13
voltage. It should also be noticed that the collector voltage of
transistors Q and Q is at a potential which is two
diode-drops below the voltage at Pin 1. Thus, the voltage at
Pin 1 should be about 2.0 V higher than the maximum input
voltage. Therefore, to handle +5.0 V at the inputs, the voltage
3
necessary to connect a resistor between Pin 13 and ground,
and between Pin 3 and ground. From the schematic shown in
Figure 3, it can be seen that the resistor values necessary are
given by:
3
4
at Pin 1 must be at least +7.0 V. Let V = 9.0 Vdc.
1
|V–| –0.7 V
R13 + 500 Ω =
Since the current flowing into Pin 1 is always equal to 2I ,
the voltage at Pin 1 can be set by placing a resistor (R ) from
1
Pin 1 to the positive supply:
3
I
13
|V–| –0.7 V
R3 + 500 Ω =
I
3
+
V –V
1
R =
1
2I
3
14.3 V
1.0 mA
or R13 = 13.8 kΩ
Let V– = –15 V, then R13 + 500 =
15 V –9.0 V
(2) (1.0 mA)
Let V+ = 15 V, then R =
1
Let R = 12 kΩ. Similarly, R = 13.8 kΩ, let R = 15 kΩ
13
3
3
However, for applications which require an accurate scale
factor, the adjustment of R and consequently, I , offers a
convenient method of making a final trim of the scale factor.
R = 3.0 kΩ.
1
3
3
Note that the voltage at the base of transistors Q , Q , Q
7
and Q is one diode-drop below the voltage at Pin 1. Thus, in
8
5
6
For this reason, as shown in Figure 21, resistor R is shown
3
order that these transistors stay active, the voltage at Pins 2
and 14 should be approximately halfway between the voltage
at Pin 1 and the positive supply voltage. For this example, the
voltage at Pins 2 and 14 should be approximately 11 V.
Step 5. For dc applications, such as the multiply, divide
and square-root functions, it is usually desirable to convert
the differential output to a single-ended output voltage
referenced to ground. The circuit shown in Figure 22
performs this function. It can be shown that the output voltage
of this circuit is given by:
as a fixed resistor in series with a potentiometer.
For applications not requiring an exact scale factor
(balanced modulator, frequency doubler, AGC amplifier, etc.)
Pins 3 and 13 can be connected together and a single
resistor from Pin 3 to ground can be used. In this case, the
single resistor would have a value of 1/2 the above calculated
value for R .
13
Step 2. The next step is to select R and R . To insure that
X
Y
the input transistors will always be active, the following
conditions should be met:
V
V
Y
R
Y
V
= (I –I ) R
2 14 L
X
O
< I
,
< I
3
13
R
2I
I
2V V
X Y
I R R
3 X Y
X
X Y
And since I –I = I –I
=
=
A
B
2
14
I
3
A good rule of thumb is to make I R ≥ 1.5 V
.ThelargertheI R andI R productin
X(max)
relation to V and V respectively, the more accurate the
and
Y(max)
3 Y
3 Y 13 X
I
R ≥ 1.5V
13 X
2R V ′ V ′
L
X
Y
then V
=
where, V ′ V ′ is the voltage at
O
X
Y
Y
X
4R
R I
X 3
X
multiplier will be (see Figures 17 and 18).
the input to the voltage dividers.
Let R = R
then I R
3 Y
= 10 kΩ,
= 10 V
= 10 V
X
Y
Figure 22. Level Shift Circuit
I
R
+
13 X
V
sinceV
=V
=5.0V,thevalueofR = R = 10 kΩ
X Y
X(max) Y(max)
is sufficient.
Step 3. Now that R R and I have been chosen, R can
be determined:
X,
Y
3
L
R
2
R
O
O
V
I
+
–
2
4
2R
(2) (R )
4
10
L
L
=
=
K =
, or
V
O
R
R I
Y 3
(10 k) (10 k) (1.0 mA) 10
X
V
14
I
14
Thus R = 20 kΩ.
L
R
Step 4. To determine what power supply voltage is
necessary for this application, attention must be given to the
circuit schematic shown in Figure 3. From the circuit
schematic it can be seen that in order to maintain transistors
R
L
L
The choice of an operational amplifier for this application
should have low bias currents, low offset current, and a high
common mode input voltage range as well as a high common
mode rejection ratio. The MC1456, and MC1741C
operational amplifiers meet these requirements.
Q , Q , Q and Q in an active region when the maximum
1
2
3
4
input voltages are applied (V = V = 10 V or V = 5.0 V,
X′ Y′
X
V
= 5.0 V), their respective collector voltage should be at
Y
least a few tenths of a volt higher than the maximum input
9
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Referring to Figure 21, the level shift components will be
determined. When V = V = 0, the currents I and I will be
The versatility of the MC1495 allows the user to to
optimize its performance for various input and output signal
levels.
X
Y
2
14
equal to I . In Step 3, R was found to be 20 kΩ and in Step
13
L
4, V and V were found to be approximately 11 V. From this
2
14
information R can be found easily from the following
O
OFFSET AND SCALE FACTOR ADJUSTMENT
equation (neglecting the operational amplifiers bias current):
Offset Voltages
+
V2
R
V –V
2
I
=
+ 13
Within the monolithic multiplier (Figure 3) transistor base-
emitter junctions are typically matched within 1.0 mV and
resistors are typically matched within 2%. Even with this
careful matching, an output error can occur. This output error
is comprised of X-input offset voltage, Y-input offset voltage,
and output offset voltage. These errors can be adjusted to
zero with the techniques shown in Figure 21. Offset terms
can be shown analytically by the transfer function:
R
O
L
11 V
20 kΩ
15 V –11 V
And for this example,
+ 1.0 mA =
R
O
Solving for R : R = 2.6 kΩ, thus, select R = 3.0 kΩ
O
O
O
For R = 3.0 kΩ, the voltage at Pins 2 and 14 is calculated
O
to be:
V
= K[V ± V
iox
± V
] [V ± V
ioy
± V
y(off)
] ± V
OO
(1)
V = V = 10.4 V.
2 14
O
x
x(off)
y
Where:
K = scale factor
The linearity of this circuit (Figure 21) is likely to be as
good or better than the circuit of Figure 5. Further
V
V
= ‘‘x’’ input voltage
= ‘‘y’’ input voltage
x
y
improvements are possible as shown in Figure 23 where R
Y
V
V
= ‘‘x’’ input offset voltage
= ‘‘y’’ input offset voltage
iox
ioy
has been increased substantially to improve the Y linearity,
and R decreased somewhat so as not to materially affect
X
V
V
= ‘‘x’’ input offset adjust voltage
= ‘‘y’’ input offset adjust voltage
= output offset voltage.
x(off)
y(off)
OO
the X linearity. This avoids increasing R significantly in order
L
to maintain a K of 0.1.
V
Figure 23. Multiplier with Improved Linearity
– 15 V
– 15 V
+15 V
3.0 k
3.0 k
3.0 k
1
7.5 k
11
27 k
5
7
10
+
6
7
4
9
10 k
10 k
14
3
V
Y′
+
–
–
4
–V
V
Y
6
X
V
=
±10 V
MC1741C
O
MC1495
10
10 k
10 k
2
2
5
V
+
3
+
X′
13
8
12
1
40 k
13 k
33 k
10 k
12 k
5.0 k
Output
Offset
Adjust
Scale
Factor
Adjust
Y Offset
Adjust
X Offset
Adjust
20 k
15 k
15 k
+15 V
–15 V
20 k
2.0 k
2.0 k
10
MOTOROLA ANALOG IC DEVICE DATA
MC1495
X, Y and Output Offset Voltages
DC APPLICATIONS
Output
Offset
Output
Offset
V
V
O
Multiply
The circuit shown in Figure 21 may be used to multiply
O
signals from dc to 100 kHz. Input levels to the actual
multiplier are 5.0 V (max). With resistive voltage dividers the
maximum could be very large however, for this application
two-to-one dividers have been used so that the maximum
input level is 10 V. The maximum output level has also been
designed for 10 V (max).
V
V
y
x
X Offset
Y Offset
For most dc applications, all three offset adjust
potentiometers (P , P , P ) will be necessary. One or more
1
2
4
Squaring Circuit
offset adjust potentiometers can be eliminated for ac
applications (see Figures 28, 29, 30, 31).
If the two inputs are tied together, the resultant function is
2
squaring; that is V = KV where K is the scale factor. Note
If well regulated supply voltages are available, the offset
adjust circuit of Figure 13 is recommended. Otherwise, the
circuit of Figure 14 will greatly reduce the sensitivity to power
supply changes.
O
that all error terms can be eliminated with only three
adjustment potentiometers, thus eliminating one of the input
offset adjustments. Procedures for nulling with adjustments
are given as follows:
Scale Factor
A. AC Procedure:
The scale factor K is set by P (Figure 21). P varies I
3
which inversely controls the scale factor K. It should be noted
that current I is one-half the current through R . R sets the
bias level for Q , Q , Q , and Q (see Figure 3). Therefore, to
be sure that these devices remain active under all conditions
of input and output swing, care should be exercised in
3
3
1. Connect oscillator (1.0 kHz, 15 V ) to input.
pp
2. Monitor output at 2.0 kHz with tuned voltmeter
3
1
1
and adjust P for desired gain. (Be sure to peak
3
5
6
7
8
response of the voltmeter.)
3. Tune voltmeter to 1.0 kHz and adjust P for a
1
minimum output voltage.
adjusting P over wide voltage ranges (see General Design
3
4. Ground input and adjust P (output offset) for
4
Procedure).
0 Vdc output.
Adjustment Procedures
5. Repeat steps 1 through 4 as necessary.
The following adjustment procedure should be used to null
the offsets and set the scale factor for the multiply mode of
operation, (see Figure 21).
B. DC Procedure:
1. Set V = V = 0 V and adjust P (output offset
X
Y
4
potentiometer) such that V = 0 Vdc
O
1. X-Input Offset
2. Set V = V = 1.0 V and adjust P (Y-input offset
X
Y
1
(a) Connect oscillator (1.0 kHz, 5.0 V sinewave)
potentiometer) such that the output voltage is
+ 0.100 V.
pp
to the Y-input (Pin 4).
(b) Connect X-input (Pin 9) to ground.
3. Set V = V = 10 Vdc and adjust P such that
X
Y
3
(c) Adjust X offset potentiometer (P ) for an ac
the output voltage is + 10 V.
4. Set V = V = –10 Vdc. Repeat steps 1 through
2
null at the output.
2. Y-Input Offset
X
Y
3 as necessary.
(a) Connect oscillator (1.0 kHz, 5.0 V sinewave)
pp
to the X-input (Pin 9).
Figure 24. Basic Divide Circuit
(b) Connect Y-input (Pin 4) to ground.
(c) Adjust Y offset potentiometer (P ) for an ac null
1
KV
V
Y
X
at the output.
X
3. Output Offset
(a) Connect both X and Y-inputs to ground.
I
1
R1
V
(b) Adjust output offset potentiometer (P ) until
X
4
I
2
the output voltage (V ) is 0 Vdc.
4. Scale Factor
O
V
–
+
Z
R2
V
(a) Apply +10 Vdc to both the X and Y-inputs.
Y
(b) Adjust P to achieve + 10 V at the output.
5. Repeat steps 1 through 4 as necessary.
3
The ability to accurately adjust the MC1495 depends upon
the characteristics of potentiometers P through P .
1
4
Multi-turn, infinite resolution potentiometers with low
temperature coefficients are recommended.
11
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Divide Circuit
In terms of percentage error,
Consider the circuit shown in Figure 24 in which the
multiplier is placed in the feedback path of an operational
amplifier. For this configuration, the operational amplifier will
maintain a “virtual ground” at the inverting (–) input.
Assuming that the bias current of the operational amplifier is
negligible, then I = I and,
error
percentage error =
actual
x 100%
R2
or from Equation (5),
∆E
KV
X
R1
∆E
1
2
=
PE
=
D
R1
V
(7)
V
Z
Z
X
KV V
X Y
–V
Z
R2 K V
=
=
=
(1)
(2)
(3)
R1
R2
From Equation 7, the percentage error is inversely related
to voltage V (i.e., for increasing values of V , the percentage
–R1
V
V
Z
Z
Z
X
Solving for V ,
Y
V
Y
Y
error decreases).
R2 K
A circuit that performs the divide function is shown in
Figure 25.
Two things should be emphasized concerning Figure 25.
–V
KV
Z
X
If R1=R2,
V
1. The input voltage (V ) must be greater than zero and
X′
must be positive. This insures that the current out of
Pin 2 of the multiplier will always be in a direction
–V
Z
(4)
If R1= KR2,
V
=
Y
V
X
compatible with the polarity of V .
Z
2. Pin 2 and 14 of the multiplier have been interchanged in
respect to the operational amplifiers input terminals. In
this instance, Figure 25 differs from the circuit
connection shown in Figure 21; necessitated to insure
negative feedback around the loop.
Hence, the output voltage is the ratio of V to V and
Z
X
provides a divide function. This analysis is, of course, the
ideal condition. If the multiplier error is taken into account, the
output voltage is found to be:
V
E
∆
R1
R2 K
Z
A suggested adjustment procedure for the divide circuit.
V
= –
+
Y
(5)
V
KV
1. Set V = 0 V and adjust the output offset potentiometer
X
X
Z
(P ) until the output voltage (V ) remains at some (not
4
O
where ∆E is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of V . For example, assume
that R1 = R2, and K = 1/10. For these conditions the output of
the divide circuit is given by:
necessarily zero) constant value as V
between +1.0 V and +10 V.
is varied
X′
2. Keep V at 0 V, set V at +10 V and adjust the Y input
Z
X′
Y
offset potentiometer (P ) until V = 0 V.
1
O
3. Let V = V and adjust the X-input offsetpotentiometer
X′
Z
(P until the output voltage remains at some (not
2)
∆E
10
V
X
–10 V
necessarily – 10 V) constant value as V = V is varied
Z
Z
X′
V
=
(6)
+
Y
between +1.0 and +10 V.
V
X
4. KeepV = V andadjustthescalefactorpotentiometer
X′
Z
From Equation 6, it is seen that only when V = 10 V is the
X
error voltage of the divide circuit as low as the error of the
multiply circuit. For example, when V is small, (0.1 V) the
error voltage of the divide circuit can be expected to be a
hundred times the error of the basic multiplier circuit.
(P )untiltheaveragevalueofV is–10VasV =V is
3
O
Z
X′
varied between +1.0 V and +10 V.
X
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.
Figure 25. Divide Circuit
– 15 V
– 15 V
+15 V
0.1 µF
R
10 k
R
10 k
X
Y
10 k
4
3.9 k
3.0 k
3.0 k
0.1 µF
7
10
+
11
5
6
7
1
14
3
+
–
–
4
10 k
6
V
V
MC1741C
O
MC1495
–10 V
Z
10 k
10 k
9
2
2
V
=
5
O
V
+
3
+
V
X
X′
13
8
12
1
13 k
Z
18 k
20 k
12 k
5.0 k
Output
Offset
Adjust
P
To Offset
Adjust
(See Figure 13)
5.0 k
3
Scale
Factor
Adjust
P
4
0
≤
V
≤
≤
+10 V
+10 V
X
′
–10 V
V
≤
Z
12
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 26. Basic Square Root Circuit
AC APPLICATIONS
The applications that follow demonstrate the versatility of
the monolithic multiplier. If a potted multiplier is used for these
cases, the results generally would not be as good because
the potted units have circuits that, although they optimize dc
multiplication operation, can hinder ac applications.
Frequency doubling often is done with a diode where
the fundamental plus a series of harmonics are
generated. However, extensive filtering is required to obtain
the desired harmonic, and the second harmonic obtained
under this technique usually is small in magnitude and
requires amplification.
2
KV
+
O
MC1495
+
–
+
V
–
Z
V
O
+
2
KV
= –V
Z
O
or
|V |
Z
V
=
O
When a multiplier is used to double frequency the second
harmonic is obtained directly, except for a dc term, which can
be removed with ac coupling.
K
Square Root
2
2
A special case of the divide circuit in which the two inputs
to the multiplier are connected together is the square root
function as indicated in Figure 26. This circuit may suffer from
latch-up problems similar to those of the divide circuit. Note
that only one polarity of input is allowed and diode clamping
(see Figure 27) protects against accidental latch-up.
This circuit also may be adjusted in the closed-loop mode
as follows:
e = KE cos ωt
o
2
KE
2
e =
o
(1 + cos 2ωt).
A potted multiplier can be used to obtain the double
frequency component, but frequency would be limited by its
internal level-shift amplififer. In the monolithic units, the
amplifier is omitted.
1. Set V to –0.01 V and adjust P (output offset) for
Z
4
In a typical doubler circuit, conventional ± 15 V supplies
are used. An input dynamic range of 5.0 V peak-to-peak is
allowed. The circuit generates wave-forms that are double
frequency; less than 1% distortion is encountered without
filtering. The configuration has been successfully used in
excess of 200 kHz; reducing the scale factor by decreasing
the load resistors can further expand the bandwidth.
Figure 29 represents an application for the monolithic
multiplier as a balanced modulator. Here, the audio input
signal is 1.6 kHz and the carrier is 40 kHz.
V
= +0.316 V, being careful to approach the output
O
from the positive side to preclude the effect of the output
diode clamping.
2. Set V to –0.9 V and adjust P (X adjust) for
Z
2
V
= +3.0 V.
O
3. Set V to –10 V and adjust P (scale factor adjust)
Z
3
for V = +10 V.
O
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.
Figure 27. Square Root Circuit
– 15 V
– 15V
+15 V
0.1 µF
R
10 k
R
10 k
X
Y
10 k
3.9 k
1
3.0 k
3.0 k
0.1 µF
7
10
+
11
5
6
7
4
9
2
3
–
+
–
4
5
6
V
O
MC1741C
MC1495
V
=
√
O
10 |V |
Z
14
2
+
3
+
(11 V)
10 k
13
8
12
1
13 k
V
Z
13 k
20 k
12 k
R
L
5.0 k
To Offset
Adjust
(See Figure 13)
Output
Offset
Adjust
P
5.0 k
3
Scale
Factor
Adjust
P
4
–10
≤
V
≤
+0 V
Z
13
MOTOROLA ANALOG IC DEVICE DATA
MC1495
The defining equation for balanced modulation is
K(E cos ω t) (E cos ω t) =
Figure 28. Frequency Doubler
m
m
c
c
V
+15 V
+
R
8.2 k
R
8.2 k
CC
Y
X
KE E
c
m
[ cos (ω + ω )t + cos (ω – ω ) t ]
c
m
c
m
R1
3.0 k
5
6
10
11
2
1.0 µF
1
2
–
4
9
where ω is the carrier frequency, ω is the modulator
E cos
ω
)
t
R1
3.3 k
c
m
(< 5.0 V
frequency and K is the multiplier gain constant.
AC coupling at the output eliminates the need for level
translation or an operational amplifier; a higher operating
frequency results.
pp
MC1495
8
Y
Offset
Adjust
R1
3.3 k
12
14
A problem common to communications is to extract the
intelligence from single-sideband received signal. The ssb
signal is of the form:
C1*
3
13
7
*Select
2
E
e
≈
cos 2 ωt
o
6.8 k
1.0
µ
F
20
e
ssb
= A cos (ω + ω ) t
c m
and if multiplied by the appropriate carrier waveform, cos ω t,
c
AK
2
–15 V
e
e
=
[cos (2ω + ω )t + cos (ω ) t ].
c m c
ssb carrier
When two equal cosine waves are applied to X and Y, the result
is a wave shape of twice the input frequency. For this example
the input was a 10 kHz signal, output was 20 kHz.
If the frequency of the band-limited carrier signal (ω ) is
ascertained in advance, the designer can insert a low pass
c
filter and obtain the (AK/2) (cosω t) term with ease. He/she
c
also can use an operational amplifier for a combination level
shift-active filter, as an external component. But in potted
multipliers, even if the frequency range can be covered, the
operational amplifier is inside and not accessible, so the user
must accept the level shifting provided, and still add a low
pass filter.
Figure 29. Balanced Modulator
(A)
+15 V
R
8.2 k
R
8.2 k
Y
X
Amplitude Modulation
The multiplier performs amplitude modulation, similar to
balanced modulation, when a dc term is added to the
modulating signal with the Y-offset adjust potentiometer (see
Figure 30).
+
–
5
6
10
11
1.0 µF
1
2
3.0 k
4
9
e
= E cos
ω
t
t
Y
m
R
L
3.3 k
e
= E cos ω
c
X
MC1495
Here, the identity is:
8
R
L
Y
X
Offset
Adjust
3.3 k
+
12
14
E (1 + m cos ω t) E cos ω t = KE E cos ω t
m c
m
m
c
c
c
KE E m
m c
C1*
13
7
3
[ cos(ω + ω )t + cos (ω – ω ) t ]
c
m
c
m
2
*Select
e
o
–
where m indicates the degrees of modulation. Since m is
6.8 k
1.0 µF
+
adjustable, via potentiometer P , 100% modulation is
1
possible. Without extensive tweaking, 96% modulation may
be obtained where ω and ω are the same as in the
balanced modulator example.
–15 V
c
m
(B)
Linear Gain Control
To obtain linear gain control, the designer can feed to one
of the two MC1495 inputs a signal that will vary the unit’s
gain. The following example demonstrates the feasibility of
this application. Suppose a 200 kHz sinewave, 1.0 V
peak-to-peak, is the signal to which a gain control will be
added. The dynamic range of the control voltage V is 0 V to
C
+1.0 V. These must be ascertained and the proper values of
R and R can be selected for optimum performance. For the
X
Y
200 kHz operating frequency, load resistors of 100 Ω were
chosen to broaden the operating bandwidth of the multiplier,
but gain was sacrificed. It may be made up with an amplifier
operating at the appropriate frequency (see Figure 31).
14
MOTOROLA ANALOG IC DEVICE DATA
MC1495
Figure 30. Amplitude Modulation
V
= +15 V
R
8.2 k
R
X
CC
Y
8.2 k
R1
3.0 k
5
6
10
11
1
2
4
9
e
e
= E cos
= E cos
ω
ω
t
t
Y
m
R
L1
3.3 k
X
m
MC1495
8
Y
X
R
3.3 k
L1
% Modulation Adjust
Offset Adjust
12
14
C1*
3
13
7
*Select
e
, e < 5.0 V
Y pp
X
e
o
6.8 k
1.0 µF
–15 V
The signal is applied to the unit’s Y-input. Since the total
input range is limited to 1.0 V , a 2.0 V swing, a current
Hence, the scale factor for this configuration is:
pp
R
L
source of 2.0 mA and an R value of 1.0 kΩ is chosen. This
Y
K =
=
R
R
I
takes best advantage of the dynamic range and insures
linear operation in the Y-channel.
X
Y 3
100
–1
V
Since the X-input varies between 0 and +1.0 V, the current
3
(2 k) (1 k) (2 x 10 )
source selected was 1.0 mA, and the R value chosen
X
1
40
was 2.0 kΩ. This also insures linear operation over the
–1
V
=
X-input dynamic range. Choosing R = 100 assures wide
L
bandwidth operation.
The 2 in the numerator of the equation is missing in this scale
factor expression because the output is single-ended and ac
coupled.
Figure 31. Linear Gain Control
+12 V
1.25
2.0 k
11
1.0 k
5
V
= 1.0 V
200 kHz
in pp
10
+
6
1.0
0.75
0.5
Y
4
1
2
1.5 k
100
V
in
51
MC1495
1.0 k
0.1
X
9
V
+
C
1
k =
µF
40
100
Y
Offset
Adjust
–
–
0.25
0
8
X
14
Amplifier
= 40
V
O
A
V
12
3
13
7
0
0.2
0.4 0.6
0.8
(V)
1.0
1.2
V
2.0 mA
AGC
3.0 k
11 k
1.0 µF
5.0 k
+
P
3
NOTE: Linear gain control of a 1.0 V signal is performed with a 0 V
pp
C
to 1.0 V control voltage. If V is 0.5 V the output will be 0.5 V
.
pp
–12 V
15
MOTOROLA ANALOG IC DEVICE DATA
MC1495
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
C
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.095
0.015
0.135
1.32
0.20
2.92
2.41
0.38
3.43
J
N
0.300 BSC
7.62 BSC
SEATING
PLANE
K
0
10
0
10
0.015
0.039
0.39
1.01
H
G
D
M
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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