MC1670L [MOTOROLA]
Master-Slave Flip-Flop; 主从触发器
| 型号： | MC1670L |
| 厂家： | 
MOTOROLA |
| 描述： | Master-Slave Flip-Flop |
| 文件： | 总4页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
Master slave construction renders the MC1670 relatively insensitive to the
shape of the clock waveform, since only the voltage levels at the clock inputs
control the transfer of information from data input (D) to output.
When both clock inputs (C1 and C2) are in the low state, the data input
affects only the “Master” portion of the flip-flop. The data present in the “Master”
is transferred to the “Slave” when clock inputs (C1 “OR” C2) are taken from a
low to a high level. In other words, the output state of the flip-flop changes on the
positive transition of the clock pulse.
While either C1 “OR” C2 is in the high state, the “Master” (and data input) is
disabled.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.
Power Dissipation = 220 mW typ (No Load)
f
= 350 MHz typ
Tog
TRUTH TABLE
D
R
S
C
Q
n+1
L
H
H
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
X
X
X
L
L
L
H
H
H
X
X
X
L
H
L
N.D.
LOGIC DIAGRAM
Q
L
5
S
n
H
L
Q
Q
H
n
n
7
9
C1
C2
Q
2
3
H
Q
n
ND = Not Defined
C = C1 + C2
11
4
D
R
Q
V
V
V
= Pin 1
= Pin 16
= Pin 8
CC1
CC2
EE
ELECTRICAL CHARACTERISTICS
–30°C
+25°C
+85°C
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Drain Current
I
E
—
—
—
48
—
—
mAdc
Input Current
Set, Reset
Clock
I
µAdc
inH
PIN ASSIGNMENT
—
—
—
—
—
—
—
—
—
550
250
270
—
—
—
—
—
—
Data
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
CC1
Switching Times
Propagation Delay
ns
Q
NC
t
1.0
0.9
0.5
2.7
2.7
2.1
1.1
1.0
0.6
2.5
2.5
1.9
1.1
1.0
0.6
2.9
2.9
2.3
pd
+
Q
NC
Rise Time (10% to 90%)
Fall Time (10% to 90%)
Setup Time
t
ns
ns
ns
–
t
RESET
SET
NC
t
t
—
—
—
—
0.4
0.5
—
—
—
—
—
—
S“1”
S“0”
NC
Hold Time
t
t
—
—
—
—
0.3
0.5
—
—
—
—
—
—
ns
NC
DATA
NC
H“1”
H“0”
CLOCK 1
Toggle Frequency
f
270
—
300
—
270
—
MHz
Tog
V
CLOCK 2
EE
3/93
REV 5
Motorola, Inc. 1996
MC1670
FIGURE 1 — TOGGLE FREQUENCY WAVEFORMS
T
= 25°C
A
+1.11 V
CLOCK INPUT
300
MHZ-MAX
+0.71 V
BIAS
The maximum toggle frequency of the MC1670 has been exceeded
when either:
+0.31 V
1. The output peak-to-peak voltage swing falls below 600
millivolts,
OR
Q OR Q
OUTPUT
2. The device ceases to toggle (divide by two).
600 MV MIN
FIGURE 2 — MAXIMUM TOGGLE FREQUENCY (TYPICAL)
+1.05
+1.0
+0.95
+0.9
+0.85
+0.8
T
= 25°C
= +2.0 VDC
= –3.2 VDC
A
V
V
CC
EE
Figure 2 illustrates the variation in toggle frequency
withthedcoffsetvoltage(V )of theinput clock signal.
Figures 4 and 5 illustrate minimum clock pulse width
recommended for reliable operation of the MC1670.
+0.75
+0.7
+0.65
+0.5
Bias
+0.45
+0.4
+0.35
+0.3
+0.25
175
225
275
325
375
425
F
TOG
(MHZ)
FIGURE 3 — TYPICAL MAXIMUM TOGGLE FREQUENCY
versus TEMPERATURE
400
350
300
250
–30
0
25
50
85
T , AMBIENT TEMPERATURE (
°C)
A
+85°C
–30°C
+25°C
Temperature
+0.765 Vdc
+0.66 Vdc
+0.71 Vdc
V
Bias
Note: All power supply and logic levels are shown shifted 2.0 volts positive.
4–357
MOTOROLA
MC1670
FIGURE 4 — MINIMUM “DOWN TIME” TO CLOCK
OUTPUT LOAD = 50 Ω
CLOCK
Q OR
Q
1.0 NS/DIV.
FIGURE 5 — MINIMUM “UP TIME” TO CLOCK
OUTPUT LOAD = 50 Ω
Q OR
Q
CLOCK
1.0 NS/DIV.
MOTOROLA
4–358
MC1670
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
–A–
NOTES:
ISSUE V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
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MC1670/D
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