MC33260 [MOTOROLA]
小型廉价功率因数控制器;
MOTOROLA 
MC33260
GreenLinet Compact
Power Factor Controller:
Innovative Circuit for
Cost Effective Solutions
The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off--line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
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MARKING
DIAGRAMS
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
MC33260P
AWL
YYWWG
PDIP--8
P SUFFIX
CASE 626
8
1
8
SO--8
D SUFFIX
CASE 751
33260
ALYW
G
8
General Features
1
Standard Constant Output Voltage or “Follower Boost” Mode
Switch Mode Operation: Voltage Mode
Latching PWM for Cycle--by--Cycle On--Time Control
Constant On--Time Operation That Saves the Use of an Extra Multiplier
Totem Pole Output Gate Drive
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G = Pb--Free Package
Improved Regulation Block Dynamic Behavior
Synchronization Capability
PIN CONNECTIONS
Internally Trimmed Reference Current Source
These are Pb--Free Devices
Feedback Input
1
2
3
4
8
7
6
5
V
CC
V
Gate Drive
Gnd
control
Safety Features
Oscillator
Capacitor (C )
T
Overvoltage Protection: Output Overvoltage Detection
Undervoltage Protection: Protection Against Open Loop
Effective Zero Current Detection
Current Sense
Synchronization
Input
Input
MC33260P
Accurate and Adjustable Maximum On--Time Limitation
Overcurrent Protection
ESD Protection on Each Pin
Oscillator
1
8
V
control
Capacitor (C )
T
Current Sense
Input
Feedback Input
2
3
4
7
6
5
Synchronization
Input
V
CC
Filtering
D1...D4
Capacitor
L1
D1
Gnd
Gate Drive
C1
+
V
LOAD
MC33260D
CC
1
2
3
4
8
7
6
5
(SMPS, Lamp
Ballast,...)
M1
V
control
R
o
ORDERING INFORMATION
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 20 of this data sheet.
Sync
CT
R
OCP
R
cs
DIP--8 CONFIGURATION SHOWN
Figure 1. Typical Application
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
November, 2010 -- Rev. 11
MC33260/D
MC33260
V
o
Current Mirror
I
o
2 x I x I
FB
O
O
I
-- c h =
OSC
I
o
I
ref
Current
Mirror
I
o
I
o
I
ref
CT
V
ref
11 V
1.5 V
1
0
15 pF
300 k
V
reg
V
control
I
o
97%I
I
ref
ref
Output_Ctrl
I
/I
11 V
ovpH ovpL
V
ref
REGULATOR
Enable
+
I
ref
--
OVP
UVP
r
I
r
uvp
--
11 V/8.5 V
+
--
+
I
cs
(205 mA)
Synchro
r
-- 6 0 m V
1
0
11 V
+
--
Current
Sense
Synchro
Arrangement
LEB
V
CC
11 V
Output_Ctrl
ThStdwn
Drive
Gnd
S
R
R
R
Q
PWM
Latch
+
Output_Ctrl
--
PWM Comparator
Q
MC33260
Figure 2. Block Diagram
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2
MC33260
MAXIMUM RATINGS
Pin #
Pin #
PDIP--8 SO--8
Rating
Symbol
Value
Unit
Gate Drive Current*
Source
Sink
7
8
5
6
mA
I
--500
500
O(Source)
I
O(Sink)
V
Maximum Voltage
(Vcc)
16
V
V
CC
max
Input Voltage
V
in
--0.3 to +10
Power Dissipation and Thermal Characteristics
P Suffix, PDIP Package
P
Maximum Power Dissipation @ T = 85C
600
100
mW
C/W
D
A
R
Thermal Resistance Junction--to--Air
Operating Junction Temperature
Operating Ambient Temperature
θ
JA
T
J
150
C
C
T
A
--40 to +105
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (V = 13 V, T = 25C for typical values, T = --40 to 105C for min/max values
CC
J
J
unless otherwise noted.)
Pin #
Pin #
PDIP--8 SO--8
Characteristic
Symbol
Min
Typ
Max
Unit
GATE DRIVE SECTION
Gate Drive Resistor
Source Resistor @ I
7
5
Ω
= 100 mA
= 100 mA
R
10
5
20
10
35
25
Drive
OL
Sink Resistor @ I
R
OH
Drive
Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V)
(Note 1)
7
7
5
5
t
--
50
--
ns
ns
r
Output Voltage Falling Time (From 9.0 V Down to 3.0 V)
(Note 1)
t
f
--
50
--
OSCILLATOR SECTION
Maximum Oscillator Swing
3
3
3
3
1
1
1
1
ΔV
1.4
87.5
350
1.5
100
1.6
112.5
450
V
mA
T
Charge Current @ I = 100 mA
I
I
FB
charge
charge
Charge Current @ I = 200 mA
400
mA
FB
Ratio Multiplier Gain Over Maximum Swing
K
5600
6400
7200
1/(V.A)
osc
@ I = 100 mA
FB
Ratio Multiplier Gain Over Maximum Swing
3
3
1
1
K
5600
10
6400
15
7200
20
1/(V.A)
pF
osc
@ I = 200 mA
FB
Average Internal Oscillator Pin Capacitance Over
C
int
Oscillator Maximum Swing (C Voltage Varying From
T
0 Up to 1.5 V) (Note 2)
Discharge Time (C = 1.0 nF)
3
1
T
disch
--
0.5
1.0
ms
T
REGULATION SECTION
Regulation High Current Reference
Ratio (Regulation Low Current Reference)/I
1
1
1
7
7
7
I
192
0.965
--
200
0.97
300
208
0.98
--
mA
--
regH
I
/I
regL regH
regH
V
Impedance
Z
kΩ
control
Vcontrol
NOTE: I is the current that is drawn by the Feedback Input Pin.
FB
1. 1.0 nF being connected between the Pin 7 and ground for PDIP--8, between Pin 5 and ground for SO--8.
2. Guaranteed by design.
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3
MC33260
ELECTRICAL CHARACTERISTICS (V = 13 V, T = 25C for typical values, T = --40 to 105C for min/max values
CC
J
J
unless otherwise noted.)
Pin #
Pin #
PDIP--8 SO--8
Characteristic
REGULATION SECTION (continued)
Feedback Pin Clamp Voltage @ I = 100 mA
Symbol
Min
Typ
Max
Unit
1
1
7
7
V
V
1.5
2.0
2.1
2.6
2.5
3.0
V
V
FB
FB--100
FB--200
Feedback Pin Clamp Voltage @ I = 200 mA
FB
CURRENT SENSE SECTION
Zero Current Detection Comparator Threshold
4
4
4
7
4
2
2
2
5
2
V
-- 9 0
--
-- 6 0
-- 0 . 7
--
-- 3 0
--
mV
V
ZCD--th
Negative Clamp Level (I
= --1.0 mA)
Cl--neg
CS--pin
ZCD--th
Bias Current @ Vcs = V
I
-- 0 . 2
--
--
mA
ns
mA
ns
ns
b--cs
Propagation Delay (Vcs > V
) to Gate Drive High
T
500
205
400
160
--
ZCD--th
ZCD
OCP
Current Sense Pin Internal Current Source
Leading Edge Blanking Duration
I
192
--
218
--
LEB
OverCurrent Protection Propagation Delay
7
5
T
100
240
OCP
(Vcs < V
to Gate Drive Low)
ZCD--th
SYNCHRONIZATION SECTION
Synchronization Threshold
PDIP--8
SO--8
5
--
--
3
V
V
0.8
0.8
1.0
1.0
1.2
1.4
V
V
sync--th
sync--th
Negative Clamp Level (I
Minimum Off--Time
= --1.0 mA)
5
7
5
3
5
3
Cl--neg
--
1.5
--
-- 0 . 7
2.1
--
--
V
sync
T
off
2.7
0.5
ms
ms
Minimum Required Synchronization Pulse Duration
OVERVOLTAGE PROTECTION SECTION
T
sync
OverVoltage Protection High Current Threshold
1
1
7
7
I
-- I
8.0
0
13
--
18
--
mA
OVPH regH
and I
Difference
regH
OverVoltage Protection Low Current Threshold
I
-- I
--
OVPL regH
and I
Difference
regH
Ratio (I
/I
)
1
7
7
5
I
/I
OVPH OVPL
1.02
--
--
--
--
--
OVPH OVPL
Propagation Delay (I > 110% I to Gate Drive Low)
T
OVP
500
ns
FB
ref
UNDERVOLTAGE PROTECTION SECTION
Ratio (UnderVoltage Protection Current
1
7
7
5
I
/I
12
--
14
16
--
%
UVP regH
Threshold)/I
regH
Propagation Delay (I < 12% I to Gate Drive Low)
T
UVP
500
ns
FB
ref
THERMAL SHUTDOWN SECTION
Thermal Shutdown Threshold
Hysteresis
7
7
5
5
T
—
--
150
30
--
--
C
C
stdwn
ΔT
stdwn
V
UNDERVOLTAGE LOCKOUT SECTION
CC
Startup Threshold
8
8
6
6
V
9.7
7.4
11
12.3
9.6
V
V
stup--th
Disable Voltage After Threshold Turn--On
V
8.5
disable
TOTAL DEVICE
Power Supply Current
8
6
I
mA
CC
Startup (V = 5 V with V Increasing)
--
--
0.1
4.0
0.25
8.0
CC
CC
Operating @ I = 200 mA
FB
NOTE: Vcs is the Current Sense Pin Voltage and I is the Feedback Pin Current.
FB
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4
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.4
1.2
1.0
0.8
-- 4 0 C
25C
105C
0.6
0.4
-- 4 0 C
25C
105C
0.2
0
0.2
0
0
20 40 60 80 100 120 140 160 180 200 220 240
185
190
195
200
205
210
I : FEEDBACK CURRENT (mA)
pin1
I : FEEDBACK CURRENT (mA)
pin1
Figure 3. Regulation Block Output versus
Feedback Current
Figure 4. Regulation Block Output versus
Feedback Current
1.340
1.335
1.330
1.325
1.320
1.315
1.310
3.5
3.0
2.5
2.0
1.5
1.0
-- 4 0 C
25C
0.5
0
1.305
1.300
105C
--40
--20
0
20
40
60
80
100
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (mA)
JUNCTION TEMPERATURE (C)
I
pin1
Figure 5. Maximum Oscillator Swing versus
Temperature
Figure 6. Feedback Input Voltage versus
Feedback Current
500
450
400
350
410
405
400
395
-- 4 0 C
25C
I
= 200 mA
pin1
105C
300
250
200
150
100
390
385
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (mA)
-- 4 0
-- 2 0
0
20
40
60
80
100
I
JUNCTION TEMPERATURE (C)
pin1
Figure 7. Oscillator Charge Current versus
Feedback Current
Figure 8. Oscillator Charge Current versus
Temperature
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5
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
104
103
102
101
100
99
120
100
80
-- 4 0 C
25C
I
= 100 mA
pin1
105C
1 nF Connected to Pin 3
60
40
20
0
98
97
-- 4 0
--20
0
20
40
60
80
100
30
50
70
90
110
130 150
170 190 210
T , JUNCTION TEMPERATURE (C)
J
I : FEEDBACK CURRENT (mA)
pin1
Figure 9. Oscillator Charge Current versus
Temperature
Figure 10. On--Time versus Feedback Current
75
65
55
45
35
207
206
205
204
203
202
201
200
199
I
OCP
regH
-- 4 0 C
25C
105C
1 nF Connected to Pin 3
I
25
15
198
197
-- 4 0
50
60
70
80
90
100
--20
0
20
40
60
80
100
I : FEEDBACK CURRENT (mA)
pin1
T , JUNCTION TEMPERATURE (C)
J
Figure 11. On--Time versus Feedback Current
Figure 12. Internal Current Sources versus
Temperature
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.150
0.148
0.146
0.144
0.142
(I
/I
)
)
ovpH ref
(I /I
ovpL ref
0.140
0.138
0.136
0.134
(I /I
)
regL ref
0.97
0.96
0.132
0.130
-- 4 0
--20
0
20
40
60
80
100
-- 4 0
--20
0
20
40
60
80
100
T , JUNCTION TEMPERATURE (C)
J
T , JUNCTION TEMPERATURE (C)
J
Figure 13. (IovpH/Iref), (IovpL/Iref), (IregL/Iref
versus Temperature
)
Figure 14. Undervoltage Ratio versus
Temperature
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6
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
--54.8
-- 5 5
4.5
-- 4 0 C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
25C
--55.2
--55.4
--55.6
--55.8
-- 5 6
105C
--56.2
--56.4
--56.6
0.5
0
-- 4 0
--20
0
20
40
60
80
100
0
2
4
6
8
10
12
14
16
T , JUNCTION TEMPERATURE (C)
J
V
: SUPPLY VOLTAGE (V)
CC
Figure 16. Circuit Consumption versus
Supply Voltage
Figure 15. Current Sense Threshold versus
Temperature
Vgate
20
15
10
-- 4 0 C
25C
25C
1
2
V
= 12 V
CC
C
gate
= 1 nF
I
(50 mA/div)
cross--cond
105C
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Ch1
10.0 V
Ch2 10.0 mVΩ M 1.00 ms Ch1
600 mV
V
: PIN 2 VOLTAGE (V)
control
Figure 17. Oscillator Pin Internal Capacitance
Figure 18. Gate Drive Cross Conduction
Vgate
Vgate
-- 4 0 C
105C
1
2
1
2
V
= 12 V
V
= 12 V
CC
CC
gate
C
= 1 nF
C = 1 nF
gate
I
(50 mA/div)
I
(50 mA/div)
cross--cond
cross--cond
Ch1
10.0 V
Ch2 10.0 mVΩ M 1.00 ms Ch1
600 mV
Ch1
10.0 V
Ch2 10.0 mVΩ M 1.00 ms Ch1
600 mV
Figure 19. Gate Drive Cross Conduction
Figure 20. Gate Drive Cross Conduction
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MC33260
PIN FUNCTION DESCRIPTION
Pin #
PDIP--8
Pin #
SO--8
Function
Description
1
7
Feedback Input
This pin is designed to receive a current that is proportional to the preconverter output
voltage. This information is used for both the regulation and the overvoltage and
undervoltage protections. The current drawn by this pin is internally squared to be used
as oscillator capacitor charge current.
2
8
V
This pin makes available the regulation block output. The capacitor connected between
this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to
obtain a nondistorted input current.
control
3
4
1
2
Oscillator Capacitor The circuit uses an on--time control mode. This on--time is controlled by comparing the
(C )
T
C
T
voltage to the V
voltage. C is charged by the squared feedback current.
control T
Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current
flowing through the inductor. This information is generally built using a sense resistor.
The Zero Current Detection prevents any restart as long as the Pin 4 voltage is below
(--60 mV). This pin is also used to perform the peak current limitation. The overcurrent
threshold is programmed by the resistor connected between the pin and the external
current sense resistor.
5
3
Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to
synchronize the PFC preconverter to the associated SMPS. If not used, this pin must
be grounded.
6
7
8
4
5
6
Ground
This pin must be connected to the preregulator ground.
Gate Drive
The gate drive current capability is suited to drive an IGBT or a power MOSFET.
V
This pin is the positive supply of the IC. The circuit turns on when V becomes higher
CC
CC
than 11 V, the operating range after startup being 8.5 V up to 16 V.
Filtering
Capacitor
D1...D4
L1
D1
C1
+
Load
V
CC
(SMPS, Lamp
Ballast,...)
1
2
3
4
8
7
6
5
M1
R
o
V
control
Sync
R
OCP
CT
R
cs
DIP--8 CONFIGURATION SHOWN
Figure 21. Application Schematic
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8
MC33260
FUNCTIONAL DESCRIPTION
Pin Numbers are Relevant to the PDIP--8 Version
INTRODUCTION
OPERATION DESCRIPTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off--line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (startup,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
Rectifiers
Converter
AC
Line
+
Bulk
Load
Storage
Capacitor
Figure 22. Typical Circuit Without PFC
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneousac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
rangeof0.5-- 0.7)isgenerated,resultinginanapparentinput
power that is much higher than the real power.
A description of the functional blocks is given below.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the Pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the Pin 1. Its value is then
given by the following equation:
V
pk
Rectified DC
V
− V
o
pin1
0
0
I
=
pin1
R
o
Line Sag
where:
AC Line Voltage
AC Line Current
Ro is the feedback resistor,
Vo is the output voltage,
Vpin1 is the Pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristicdepictedinFigure 25. Accordingtothepower
and the input voltage, the output voltage regulation level
varies between two values (Vo)regL and (Vo)regH
corresponding to the IregL and IregH levels.
Figure 23. Line Waveforms Without PFC
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre--regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step--up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
Regulation Block Output
1.5 V
Rectifiers
PFC Preconverter
Converter
AC
Line
+
I
o
I
I
regH
(I )
ref
regL
ref
(97%I
)
Figure 25. Regulation Characteristic
Figure 24. PFC Preconverter
The feedback resistor must be chosen so that the feedback
current should equal the internal current source IregH when
the output voltage exceeds the chosen upper regulation
voltage [(Vo)regH].
TheMC33260wasdevelopedtocontrolanactivesolution
with the goal of increasing its robustness while lowering its
global cost.
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9
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
Consequently:
where:
V
− V
Vo is the output voltage,
o
regH
I
pin1
R
=
Ro is the feedback resistor,
o
regH
Vpin1 is the Pin 1 clamp voltage.
In practice, Vpin1 is small compared to (Vo)regH and this
equation can be simplified as follows (IregH being also
replaced by its typical value 200 mA
In practice, Vpin1 that is in the range of 2.5 V, is very small
compared to Vo. The equation can then be simplified by
neglecting Vpin1
:
2
o
( )
kΩ
R
≈ 5 × V
2 × V
o
o
regH
I
≈
charge
2
R
× I
The regulation block output is connected to the Pin 2
through a 300 kΩ resistor. The Pin 2 voltage (Vcontrol) is
compared to the oscillator sawtooth for PWM control.
An external capacitor must be connected between Pin 2
andground, for externalloopcompensation. Thebandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle.Thisintegrationthatresultsinaconstanton--timeover
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
o
ref
It must be noticed that the oscillator terminal (Pin 3) has
an internal capacitance (Cint) that varies versus the Pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
Thetotaloscillatorcapacitoristhenthesumoftheinternal
and external capacitors.
C
= C + C
pin3
T
int
PWM LATCH SECTION
OSCILLATOR SECTION
The MC33260 operates in voltage mode: the regulation
block output (Vcontrol -- Pin 2 voltage) is compared to the
oscillator sawtooth so that the gate drive signal (Pin 7) is
high until the oscillator ramp exceeds Vcontrol
The on--time is then given by the following equation:
The oscillator consists of three phases:
Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it
exceeds Vcontrol (regulation block output voltage). At
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
.
C
× V
pin3
control
t
=
on
Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
I
ch
where:
t
on is the on--time,
C
pin3 is the total oscillator capacitor (sum of the
internal and external capacitor),
I
= 2 ¢ I ¢ I / I
o o ref
charge
I
V
charge is the oscillator charge current (Pin 3 current),
control is the Pin 2 voltage (regulation block output).
1
0
Consequently, replacing Icharge by the expression given in
Output_Ctrl
the Oscillator Section:
CT
3
2
R
× I × C
× V
o
ref
pin3
2
control
1
0
t
=
on
15 pF
2 × V
o
One can notice that the on--time depends on Vo
(preconverter output voltage) and that the on--time is
maximum when Vcontrol is maximum (1.5 V typically).
At a given Vo, the maximum on--time is then expressed by
the following equation:
Figure 26. Oscillator
Theoscillatorchargecurrentisdependentonthefeedback
current (Io). In effect
2
2
I
× Vcontrol
C
× R × I
o
pin3
ref
o
max
I
= 2 ×
max =
t
charge
on
I
2
2 × V
ref
o
where:
This equation can be simplified repblaycKing
I
charge is the oscillator charge current,
2
Io is the feedback current (drawn by Pin 1),
Iref is the internal reference current (200 mA
So, the oscillator charge current is linked to the output
voltage level as follows:
osc
[(
)
]
V
* I
control max ref
Refer to Electrical Characteristics, Oscillator Section.
Then:
2 × V pin12
2
C
× R
o
pin3
− V
max =
t
o
on
2
K
× V
o
I
=
osc
charge
2
R
× I
o
ref
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10
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
Zero Current Detection
This equation shows that the maximum on--time is inversely
proportional to the squared output voltage. This property is
used for follower boost operation (refer to Follower Boost
section).
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The Pin 4 voltage is simply compared to the (--60 mV)
threshold so that as long as Vcs is lower than this threshold,
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
theinductorcurrentismeasuredassmallerthan(60mV/Rcs)
that is, the inductor current nearly equals zero.
CURRENT SENSE BLOCK
The inductor current is converted into a voltage by
insertinga groundreferencedresistor (Rcs) inseries withthe
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
I
(205 mA)
ocp
= -- Rcs L
V
× I
cs
D1...D4
S
Output_Ctrl
PWM
Latch
where:
IL is the inductor current,
Rcs is the current sense resistor,
cs is the measured Rcs voltage.
-- 6 0 m V
1
0
Output_Ctrl
R
Q
+
--
R
V
OCP
R
V
4
LEB
OCP
R
cs
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
Figure 28. Current Sense Block
Time
Overcurrent Protection
During the power switch conduction (i.e. when the Gate
Drive Pin voltage is high), a current source is applied to the
Pin 4. A voltage drop VOCP is then generated across the
resistor ROCP that is connected between the sense resistor
and the Current Sense Pin (refer to Figure 28). So, instead
of Vcs, the sum (Vcs + VOCP) is compared to (--60 mV) and
the maximum permissible current is the solution of the
following equation:
+ V
-- R × Ipk
= -- 6 0 m V
cs
max
OCP
V
OCP
where:
Ipkmax is maximum allowed current,
cs is the sensing resistor.
The overcurrent threshold is then:
R
-- 6 0 m V
-- 3
ROCP OCP+ 60 × 10
× I
Zero Current Detection
Ipk
=
max
R
cs
V
= R
pin4
¢ I
OCP
OCP OCP
where:
An overcurrent is detected if V crosses the threshold (--60 mV)
R
OCP is the resistor connected between the pin and the
during the Power Switch on state
sensing resistor (Rcs),
Figure 27. Current Sensing
I
OCP is the current supplied by the Current Sense Pin
when the gate drive signal is high (power switch
conduction phase). IOCP equals 205 mA typically.
The negative signal Vcs is applied to the current sense
through a resistor ROCP. The pin is internally protected by a
negative clamp (--0.7 V) that prevents substrate injection.
As long as the Pin 4 voltage is lower than (--60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on--time, the Pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
Practically, the VOCP offset is high compared to 60 mV
andtheprecedentequationcanbesimplified. Themaximum
current is then given by the following equation:
(
)
kΩ
R
OCP
cs
( )
× 0.205 A
Ipk
≈
max
(
)
R
Ω
Consequently, the ROCP resistor can program the OCP level
whatever the Rcs value is. This gives a high freedom in the
choice of Rcs. In particular, the inrush resistor can be utilized.
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11
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
V
Th--Stdwn
CC
Synchronization
S
R
Arrangement
Output
Buffer
5
7
Q
Q
OVP, UVP
Current Sense
Comparator
PWM
Latch
--
ZCD & OCP
+
&
Output_Ctrl
-- 6 0 m V
PWM Latch
Comparator
+
--
V
(V
-- Regulation Output)
control pin2
Oscillator Sawtooth
Figure 29. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
fromPin4anddisablesitduringthe 400firstnsof thepower
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
Practically, Vpin1 that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
(
)
(
) ( )
mA
V
= R MΩ × I
V
o
ovpH
ovpH
On the other hand, the OVP low threshold is:
+ Ro
V
= V
× I
ovpL
pin1
ovpL
PROTECTIONS
where IovpL is the internal low OVP current threshold.
Consequently, Vpin1 being neglected:
OCP (Overcurrent Protection)
Refer to Current Sense Block.
(
)
(
) ( )
mA
V
= R MΩ × I
V
o
ovpL
ovpL
The OVP hysteresis prevents erratic behavior.
OVP (Overvoltage Protection)
IovpL is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
The feedback current (Io) is compared to a threshold
current (IovpH). If it exceeds this value, the gate drive signal
is maintained low until this current gets lower than a second
level (IovpL).
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
than 14% of Iref. In this case, the PWM latch is reset and the
power switch is kept off.
Gate
Drive
Enable
This protection is useful to:
Protect the preregulator from working in too low
mains conditions.
V
control
To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
I
o
I
I
I I I
uvp
regL regH ovpL ovpH
) ( )
mA V
(
)
(
V
≈ V
+ R MΩ × I
uvp
uvp
o
pin1
Figure 30. Internal Current Thresholds
Practically (Vpin1 being neglected),
So, the OVP upper threshold is:
(
)
(
) ( )
= R MΩ × I mA
uvp
V
V
uvp
o
ovpH
V
= V
+ R × I
o
ovpH
pin1
Maximum On--Time Limitation
As explained in PWM Latch, the maximum on--time is
accurately controlled.
where:
Ro is the feedback resistor that is connected between
Pin 1 and the output voltage,
I
V
ovpH is the internal upper OVP current threshold,
pin1 is the Pin 1 clamp voltage.
Pin Protection
All the pins are ESD protected.
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12
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Feedback, Vcontrol
,
Oscillator, Current Sense, and
Synchronization.
Sync
+
5
S1
Q1
Q1 High <=>
Synchronization Mode
--
1 V
R
sync
UVLO
R2
PWM
Latch
Set
2 ms
&
S2
R2
Q2
1 V
Output_Ctrl
Figure 31. Synchronization Arrangement
OUTPUT SECTION
SYNCHRONIZATION BLOCK
The MC33260 features two modes of operation:
FreeRunningDiscontinuousMode:Thepowerswitch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. Thegatedriveiskeptinasinkingmodewhenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
REFERENCE SECTION
Aninternalreferencecurrentsource(Iref) istrimmed tobe
4% accurate over the temperature range (the typical value
is 200 mA). Iref is the reference used for the regulation
(IregH = Iref).
-- Still, the zero current must have been detected.
-- The precedent turn on must have been followed by (at
least) one synchronization raising edge crossing the
1.0 V threshold.
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (VCC) is high enough to
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
The circuit off state consumption is very low: in the range
of 100 mA @ VCC = 5.0 V. This consumption varies versus
VCC as the circuit presents a resistive load in this mode.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (on--time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 ms
minimum off--time is forced. This delay limits the switching
frequency in light load conditions.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150C typically.
The output stage is again enabled when the temperature
drops below 120C typically (30C hysteresis).
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13
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
FOLLOWER BOOST
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
TraditionalPFCpreconvertersprovidetheloadwithafixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
traditional preconverter
follower boost preconverter
Ipk
IL
Traditional Output
time
V (Follower Boost)
o
Vin
Vin
V
ac
Vin
Vout
Vin
IL
IL
Load
the power switch is off
Figure 33. Off--Time Duration Increase
the power switch is on
Figure 32. Follower Boost Characteristics
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Implementation
In the MC33260, the on--time is differently controlled
according to the feedback current level. Two areas can be
defined:
Follower Boost Benefits
When the feedback current is higher than IregL (refer
to regulation section), the regulation block output
(Vcontrol) is modulated to force the output voltage to a
desired value.
The boost presents two phases:
The on--time duringwhich the power switchis on. The
inductorcurrentgrowsuplinearlyaccordingtoaslope
(Vin/Lp), where Vin is the instantaneous input voltage
and Lp the inductor value.
The off--time during which the power switch is off.
The inductor current decreases linearly according the
slope (Vo -- V in)/Lp, where Vo is the output voltage.
This sequence that terminates when the current equals
zero, hasadurationthatisinverselyproportionaltothe
gap between the output and input voltages.
Consequently, the off--time duration becomes longer
in follower boost.
On the other hand, when the feedback current is lower
than IregL, the regulation block output and therefore,
the on--time are maximum. As explained in PWM
Latch Section, the on--time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on--time is simply limited by the output voltage
level. Note: In this equation, the Feedback Pin voltage
(Vpin1) is neglected compared to the output voltage
(refer to the PWM Latch Section).
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
thenitsconductiondissipation.Thisisthefirstbenefitofthis
technique: the MOSFET on--time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptablelevel,onecanimmediatelyseethesecondbenefit
2
C
× R
o
pin3
max =
t
= t
on
on
2
K
× V
o
osc
where:
C
pin3 is the total oscillator capacitor (sum of the
internal and external capacitors -- Cint + CT),
osc is the ratio (oscillator swing over oscillator gain),
K
Vo is the output voltage,
Ro is the feedback resistor.
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14
MC33260
Pin Numbers are Relevant to the PDIP--8 Version
On the other hand, the boost topology has its own rule that
dictatestheon--timenecessarytodelivertherequiredpower:
Regulation Block is Active
V = V
o pk
V
o
4 × L × P
p
(P )min
in
in
t
=
on
2
V
pk
P
in
where:
pk is the peak ac line voltage,
V
(P )max
in
Lp is the inductor value,
Pin is the input power.
non usable area
Combining the two equations, one can obtain the
Follower Boost equation:
C
R
2
pin3
o
×
V
=
× V
o
pk
K
× L × P
V
ac
osc
p
in
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
V
acLL
V
ac
V
acHL
Figure 35. Follower Boost Output Voltage
The Regulation Block is Active
Mode Selection
(V )max
ac
The operation mode is simply selected by adjusting the
oscillatorcapacitorvalue. AsshowninFigure 35, theoutput
voltagefirsthasanincreasinglinearcharacteristicversusthe
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
V
ac
Output Voltage
Input Power
P
in
(V )min
ac
V
o
2
t
on
= k/V
o
t
on--time
on
Figure 34. Follower Boost Characteristics
In other words, if (Vo)regL is the low output regulation
level:
The behavior of the output voltage is depicted in
Figures 34 and 35. In particular, Figure 35 illustrates how
the output voltage converges to a stable equilibrium level.
First, ata givenac linevoltage, theon--time isdictatedbythe
power demand. Then, the follower boost characteristic
makes correspond one output voltage level to this on--time.
Combining these two laws, it appears that the power level
forces the output voltage.
C
+ C
R
2
o
T
int
regL
V
≤
×
× V
o
pk
× P max
K
× L
p
osc
in
Consequently,
2
× P max × V
4 × K
× L
p
osc
o
regL
in
C
≥ -- C
+
T
int
2
2
R
× V
One can notice that the system is fully stable:
o
pk
Ifanoutputvoltageincreasemakesitmoveawayfrom
its equilibrium value, the on--time will immediately
diminishaccordingtothefollowerboostlaw. Thiswill
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
Using IregL (regulation block current reference), this
equation can be simplified as follows:
2
× P max × I
4 × K
× L
p
osc
in
regL
C
≥ -- C
+
T
int
2
V
pk
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
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15
MC33260
Synchronization
Signal
Zero Current
Detection
2 ms
Delay
2 ms
2 ms
2 ms
2 ms
V
control
Oscillator
Circuit
Output
205 mA
I
cs
Inductor
Current
1
2
3
4
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off--time (2 ms)
Figure 36. Typical Waveforms
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16
MC33260
MAIN DESIGN EQUATIONS (Note 3)
rms Input Current (I
)
(preconverter efficiency) is generally in the
range of 90 -- 95%.
ac
P
o
I
=
ac
η × V
ac
Maximum Inductor Peak Current ((I )max):
(I )max is the maximum inductor current.
pk
pk
2 × 2 × (P ) max
o
(I ) max =
pk
η × V
acLL
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((ΔVo)pk--pk):
f
is the ac line frequency (50 or 60Hz).
ac
P
o
(ΔV )
=
o
pk–pk
2π × f × C × V
ac
o
o
t is the maximum switching period.
(t = 40 ms) for universal mains operation and
(t = 20ms) for narrow range are generally
used.
V
Inductor Value (L ):
p
o
2
2 × t ×
× V
− V
acLL
acLL
2
L
=
p
V × V
× (I ) max
o
acLL
pk
Maximum Power MOSFET Conduction Losses ((p )max):
(Rds)on is the MOSFET drain source on--time
resistor.
on
1.2 × V
acLL
1
(P ) max ≈ × (Rds)on × (I ) max2 ×
1 −
In Follower Boost, the ratio (V
/V ) is
o
acLL
on
pk
3
V
higher. The on--time MOSFET losses are then
reduced.
o
Maximum Average Diode Current (I ):
The Average Diode Current depends on the
power and on the output voltage.
d
(P ) max
(V ) min
o
o
(I ) max =
d
Current Sense Resistor Losses (pR ):
cs
This formula indicates the required dissipation
capability for R (current sense resistor).
cs
1
6
pR
=
× (Rds)on × (I )2 max
cs
pk
Over Current Protection Resistor (R
R
):
The overcurrent threshold is adjusted by R
OCP
OCP
at a given R
.
R
× (I ) max
cs
cs
pk
(kΩ)
R
cs
can be a preconverter inrush resistor.
≈
OCP
0.205
The Follower Boost characteristic is adjusted
Oscillator External Capacitor Value (C ):
T
by the C choice.
The Traditional Mode is also selected by C .
--Traditional Operation
T
2 × K
× L × (P ) max × I2
osc
C
p
in
regL
T
C
≥ − C
+
×
V2
ac
C
int
is the oscillator pin internal capacitor.
T
int
-- Follower Boost:
+ C
int
R
o
2
T
V
=
× V
pk
o
K
× L × P
p
in
osc
Feedback Resistor (R ):
The output voltage regulation level is adjusted
by R .
o
(V )
− VFB
V
200
o reg
o
(MΩ)
o
R
=
≈
o
I
regH
3. The preconverter design requires the following characteristics specification:
-- ( V ) : desired output voltage regulation level
o reg
-- ( ΔV )
: admissible output peak to peak ripple voltage
o pk--pk
-- P : desired output power
o
-- V : ac rms operating line voltage
ac
acLL
-- V
: minimum ac rms operating line voltage
-- V : Feedback Pin voltage
FB
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17
MC33260
L1 320 mH
D5
MUR460E
1N4007
D1
R1
1 MΩ
0.25 W
80 W Load
(SMPS, Lamp
Ballast,...)
D2
D4
Q1
MTP4N50E
+
C2
47 mF
450 V
C1
330 nF
500 Vdc
90 to
270 Vac
EMI
Filter
D3
R2
1 MΩ
0.25 W
R4
R3
15 kΩ/0.25 W
1 Ω/2 W
R5
22 Ω/0.25 W
V
I
ref
ref
I
I
ref
MC33260
o
I
o
Feedback
Block
11 V/8.5 V
I
I
ref
--
o
REGULATOR
Enable
UVP, OVP
Feedback
Input
V
V
prot
CC
+
V
reg
Regulation
Block
1.5 V
V
V
reg
control
I
o
V
prot
(-- -- --)
C3
680 nF
I
o
300 k
I
I
I
uvp
ovpL ovpH
ThStdwn
Drive
Gnd
Output
Buffer
97%.I
I
ref
ref
PWM Comp
Oscillator
+
--
R
S
Q
Q
2x|0x|0
I
=
PWM
Latch
osc–ch
I
ref
Current
Output
I
(205 mA)
ocp
CT
Sense
Block
C4
330 pF
0
1
1
0
-- 6 0 m V
+
--
Synchro
15 pF
Synchronization
Block
LEB
Output
L1: Coilcraft N2881 -- A (primary: 62 turns of # 22 AWG -- Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072 total for a primary inductance (Lp) of 320 mH)
Figure 37. 80 W Wide Mains Power Factor Corrector
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
Current Harmonic Distortion (% I
)
DC Output
fund
V
(V)
P
(W)
PF
(--)
I
V
(V)
ΔV
(V)
I
P
o
(W)
(%)
rms
in
fund
o
o
o
(mA)
(mA)
THD
H2
H3
H5
H7
H9
90
88.2
86.3
85.2
87.0
84.7
85.3
84.0
0.991
0.996
0.995
0.994
0.982
0.975
0.967
990
782
642
480
385
359
330
8.1
7.0
0.07
0.05
0.03
0.16
0.5
5.9
2.7
1.5
4.0
8.4
9.0
11.0
4.3
5.7
6.8
6.5
7.8
7.8
7.0
1.5
1.1
1.1
3.1
5.3
7.4
9.0
1.7
0.8
1.5
4.0
1.9
3.8
4.0
181
222
265
360
379
384
392
31.2
26.4
20.8
16.0
14.0
14.0
13.2
440
360
300
225
210
210
205
79.6
79.9
79.5
81.0
79.6
80.6
80.4
90.2
92.6
93.3
93.1
94.4
94.5
95.7
110
135
180
220
240
260
8.2
9.5
15
16.5
18.8
0.7
0.7
*Measurements performed using Voltech PM1200 ac power analysis.
http://onsemi.com
18
MC33260
R
stup
r
D1...D4
+
15 V
C
pin8
V
CC
+
1
2
3
4
8
7
6
5
PDIP--8 CONFIGURATION SHOWN
Figure 38. Circuit Supply Voltage
MC33260 VCC SUPPLY VOLTAGE
When the PFC preconverter is loaded by an SMPS, the
MC33260shouldpreferablybesuppliedbytheSMPSitself.
In this configuration, the SMPS starts first and the PFC gets
active when the MC33260 VCC supplied by the power
supply, exceeds the device startup level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
Insomeapplications,thearrangementshowninFigure 38
must be implemented to supply the circuit. A startupresistor
is connected between the rectified voltage (or one--half
wave) to charge the MC33260 VCC up to its startup
threshold (11 V typically). The MC33260 turns on and the
VCC capacitor (Cpin8) starts to be charged by the PFC
transformer auxiliary winding. A resistor, r (in the range of
22 Ω)anda15 VZenershouldbeaddedtoprotectthecircuit
from excessive voltages.
PCB LAYOUT
The connections of the oscillator and Vcontrol capacitors
should be as short as possible.
Preconverter Output
+
+
+
V
+
CC
1
2
3
4
8
7
6
5
+
+
+
SMPS Driver
DIP--8 CONFIGURATION SHOWN
Figure 39. Preconverter Loaded by a Flyback SMPS: MC33260 VCC Supply
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19
MC33260
ORDERING INFORMATION
Device
†
Package
Shipping
MC33260PG
PDIP--8
(Pb--Free)
50 Units / Rail
MC33260DG
SOIC--8
(Pb--Free)
98 Units / Rail
MC33260DR2G
SOIC--8
(Pb--Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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20
MC33260
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626--05
ISSUE M
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
A
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSION E IS MEASURED WITH THE LEADS RE-
STRAINED PARALLEL AT WIDTH E2.
4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
D1
E
8
5
4
INCHES
NOM
-- -- -- -- 0 . 2 1 0
-------- --------
MILLIMETERS
E1
DIM MIN
-- -- -- --
A1 0.015
b
C
D
MAX
MIN
NOM
-- -- -- --
-- -- -- --
0.46
0.25
MAX
A
-- -- -- --
0 . 3 8
0.35
0.20
9.02
0 . 1 3
7.62
6.10
5 . 3 3
-- -- -- --
0.56
0.36
1
0.014 0.018 0.022
0.008 0.010 0.014
0.355 0.365 0.400
NOTE 5
9.27 10.02
F
c
D1 0.005
0.300 0.310 0.325
E1 0.240 0.250 0.280
--------
--------
-- -- -- --
7.87
6.35
-- -- -- --
8.26
7.11
E
E2
TOP VIEW
END VIEW
E2
E3
e
0.300 BSC
-- -- -- -- 0 . 4 3 0
0.100 BSC
7.62 BSC
NOTE 3
-- -- -- --
-- -- -- --
2.92
-- -- -- -- 1 0 . 9 2
2.54 BSC
3.30
e/2
L
0.115 0.130 0.150
3.81
A
L
A1
SEATING
PLANE
C
E3
e
8X
b
M
0.010
C A
END VIEW
SIDE VIEW
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21
MC33260
PACKAGE DIMENSIONS
SOIC--8
CASE 751--07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
-- X --
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751--01 THRU 751--06 ARE OBSOLETE. NEW
STANDARD IS 751--07.
S
M
M
B
0.25 (0.010)
Y
1
K
-- Y --
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
-- Z --
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
M
J
H
D
0
0.25
5.80
8
0
8
_
_
_
_
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
0.25 (0.010)
Z
Y
X
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
SCALE 6:1
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
MC33260/D
AND8016/D
Design of Power Factor
Correction Circuit Using
Greenline Compact Power
Factor Controller MC33260
http://onsemi.com
Prepared by
Ming Hian Chew
ON Semiconductor Analog Applications Engineering
APPLICATION NOTE
Introduction
of external components, the MC33260 can control the
follower boost operation that is an innovative mode
allowing a drastic size reduction of both the inductor and the
power switch. Ultimately, the solution system cost is
significantly lowered.
Also able to function in a traditional way (constant output
voltage regulation level), any intermediary solutions can be
easily implemented. This flexibility makes it ideal to
optimally cope with a wide range of applications.
This application note will discuss on the design of power
factor correction circuit with MC33260 with traditional
boost constant output voltage regulation level operation and
follower boost variable output voltage regulation level
operation. For derivation of the design equations related to
the IC please refer to MC33260 data sheet.
The MC33260 is an active power factor controller that
functions as a boost pre–converter which, meeting
international standard requirement in electronic ballast and
off–line power supply application. MC33260 is designed to
drive a free running frequency discontinuous mode, it can
also be synchronized and in any case, it features very
effective protections that ensure a safe and reliable
operation.
This circuit is also optimized to offer extremely compact
and cost effective PFC solutions. It does not entail the need
of auxiliary winding for zero current detection hence a
simple coil can be used instead of a transformer if the
MC33260 Vcc is drawn from the load (please refer to page
19 of the data sheet). While it requires a minimum number
D5
R6
D1
D2
D3
D4
R7
D7
C1
L1
+
C4
D5
+
C5
1
2
3
4
8
7
6
5
R5
Q1
MC33260
C2
R2
C3
R1
R3
R4
C6
Figure 1. Application Schematic of MC33260
PFC Techniques
cost. This paper will discuss design of PFC with MC33260,
which operates in critical conduction mode.
Many PFC techniques have been proposed, boost
topology, which can operate in continuous and
discontinuous mode, is the most popular. Typically,
continuous mode is more favorable for high power
application for having lower peak current. On the other
hand, for less than 500 W application, discontinuous mode
offers smaller inductor size, minimal parts count and lowest
Discontinuous Conduction Mode Operation
Critical conduction mode operation presents two major
advantages in PFC application. For critical conduction
mode, the inductor current must fall to zero before start the
next cycle. This operation results in higher efficiency and
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
June, 2002 – Rev. 1
AND8016/D
AND8016/D
Ǹ
eliminates boost rectifier reverse recovery loss as MOSFET
I
+ 2 I
(5)
where
inpk
inrms
cannot turn–on until the inductor current reaches zero.
Secondly, since there are no dead–time gaps between
cycles, the ac line current is continuous thus limiting the
peak switch to twice the average input current. The
converter works right on critical conduction mode, which
results in variable frequency operation.
Input power of the PFC circuit, P can be expressed in
following equation, by substituting equation (3) and (5).
in
V
I
V
I
inpk
inpk
inpk inpk
2
(6)
P
+ V
I
+
+
@
in
inrms inrms
Ǹ
Ǹ
2
2
The output power, P is given by:
o
Inductor Waveform
P
+ V I + ηP
o o
(7)
o
in
di
dt
V
L
(1)
+
PFC circuit efficiency is needed in the design equation, for
low line operation, it is typically set at 92% while 95% for
high line operation. Substituting equation (6) into
equation (7),
Equation (1) is the center of the operation of PFC boost
converter where V=V (t), the instantaneous voltage across
in
the inductor. Assuming the inductance and the on–time over
each line half–cycle are constant, di is actually the peak
V
I
inpk inpk
2
(8)
P
+ ηP +η
current, I , this is because the inductor always begins
o
Lpk
in
charging at zero current.
Express the above equation in term of I
,
inpk
V (t)
in
Ǹ
2P
2 P
o
o
V
inpk
(9)
I
+
+
inpk
ηV
ηV
I
I (t)
L
Lpk
inpk
inrms
The average input current is equal to average inductor
current, I
,
L(avg)
I
I (t)
in
inpk
I
+ I
(10)
L(avg)
in
It has been understood that peak inductor current, I
is
Lpk
exactly twice the average inductor current, I
conduction operation.
for critical
L(avg)
ON
MOSFET
Ǹ
2 2P
o
OFF
(11)
I
+ 2I
+
Lpk
L(avg)
ηV
inrms
Figure 2. Inductor Waveform
Since I
is maximum at minimum required ac line
Lpk
voltage, V
,
ac(LL)
Design Criteria
The basic design specification concerns the following:
• Mains Voltage Range: V – V
Ǹ
2 2 P
o
(12)
I
+
Lpk
ηV
ac(LL)
ac(HL)
ac(LL)
• Regulated DC Output Voltage: V
o
• Rated Output Power: P
• Expected Efficiency, h
Switching Time
In theory, the on–time, t
tends to increase at the ac line zero crossings due to the
charge on output capacitor C . Let V = V for initial
o
is constant. In practice, t
(on)
(on)
PFC Power Section Design
Instantaneous Input Voltage, V (t)
out
ac
ac(LL)
t
and t
calculations.
(on)
(off)
in
Peak Input Voltage, V
Both V (t) and V
inpk
On–time
are related by below equation
inpk
By solving inductor equation (1), on–time required to
charge the inductor to the correct peak current is:
in
V (t) + V
sin(ωt)
(2)
(3)
in
inpk
inpk
L
P
(13)
Ǹ
t
+ I
V
+ 2 V
where
(on)
Lpk
Vinpk
inrms
Substituting equation (3) and (12) into equation (13),
results in:
Instantaneous Input Current, I (t)
in
Peak Input Current, I
,
inpk
Ǹ
L
2P L
o
2 2 P
o
P
P
Both I (t) and I
are related by below equation
in
inpk
t
+
+
(14)
@
(on)
Ǹ
2
ηV
2 V
ac(LL)
ηV
ac(LL)
ac(LL)
I (t) + I
in
sin(ωt),
(4)
inpk
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2
AND8016/D
Off–time
The exact inductor value can be determined by solving
equation (21) by substituting equation (19) and (20) at the
selected minimum operating frequency.
The instantaneous switch off–time varies with the line and
load conditions, as well as with the instantaneous line
voltage. Off–time is analyzed by solving equation (1) for the
inductor discharging where the voltage across the inductor
t
+ t
) t
(21)
total
(on)max
(off)max
Equation (21) becomes
is V minus V .
o
in
Ǹ
2P L V
I
L
o
o
P
Lpk P
* V sin(ωt)
t
+
(15)
t
+
(22)
total
Vo
2
(off)
V
o
inpk
η ǒ ac(LL) Ǔ
V
* V
Ǹ
ac(LL)
2
Multiplying nominator and denominator with
sinw(t) results in:
By rearranging in term of L ,
p
V
inpk
Vo
2
I
L
ǒ
ǓηV
t
* V
Lpk P
Ǹ
ac(LL)
total
ac(LL)
2
(23)
L
+
V
sin(ωt)
t
p
Ǹ
inpk
(on)
o
2 V P
o o
(16)
t
+
+
(off)
V
* V
sin(ωt)
o
V
inpk
sin(ωt)
Equation (23) can be rewritten by substituting rearranged
equation (12) in term of √2P .
*1
V
Ǹ
o
2 Vinpk sin(θ)
inpk
Vo
where wt = q
The off–time, t
voltage and approaches zero at the ac line zero crossings.
Theta (q) represents the angle of the ac line voltage.
The off–time is at a minimum at ac line crossings. This
ǒ
ac(LL)ǓVac(LL)
Lpk
2 t
* V
Ǹ
total
2
(24)
is greatest at the peak of the ac line
(off)
L
+
p
V I
o
Let the switching cycle t = 40ms for universal input (85 to
265 V ) operation and 20 ms for fixed input (92 to 138 V ,
or 184 to 276 V ) operation.
ac
ac
equation is used to calculate t
as Theta approaches zero.
(off)
ac
I
L
Lpk P
(17)
°
, θ + 0
Inductor Design Summary
The required energy storage of the boost inductor is:
t
+
(off)min
V
o
2
1
2
(25)
Switching Frequency
W + L I
L
P
Lpk
1
) t
f +
(18)
The number of turns required for a selected core size and
material is:
t
(on)
(off)
Switching frequency changes with the steady state line
and load operating conditions along with the instantaneous
input line voltage. Typically, the PFC converter is designed
to operate above the audible range after accommodating all
circuit and component tolerances. 25 kHz is a good first
approximation. Higher frequency operation that can
significantly reduce the inductor size without negatively
impacting efficiency or cost should also be evaluated.
The minimum switching frequency occurs at the peak of
the ac line voltage. As the ac line voltage traverses from peak
6
L I
10
A
P Lpk
(26)
N
+
P
B
max e
where B
is in Teslas and A is in square millimeters
e
max
2
(mm )
The required air gap to achieve the correct inductance and
storage is expressed by:
*
2
7
4p10
N
A
p
e
(27)
l
+
mm
gap
L
P
to zero, t
approaches zero producing an increase in
(off)
switching frequency.
Design of Auxiliary Winding
MC33260 does not entail an auxiliary winding for zero
current detection. Hence if DC voltage can be tapped from
the SMPS or electronic ballast connected to the output of
PFC, this step can be skipped. Then an inductor is what it
needs.
The auxiliary winding exhibits a low frequency ripple
(100–120 Hz). The Vcc capacitor must be large enough
(about 47 mF) to minimize voltage variations. As a rule of
thumb, you can use the below equation to estimate the
auxiliary turn number:
Inductor Value
Maximum on–time needs to be programmed into the PFC
controller timing circuit. Both t
individually calculated and added together to obtain the
maximum conversion period, t . This is required to obtain
the inductor value.
and t
will be
(on)max
(off)max
total
2P L
o
P
t
t
+
+
(19)
(20)
(on)max
(off)max
2
ηV
ac(LL)
I
L
N @ V
N @ V
Lpk P
p
aux
p
aux
°
N
+
+
(28)
, (θ) [ 90
aux
V
L
V * V
V
o
* V
o
ac(HL)
inpk
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3
AND8016/D
The MC33260 V maximum voltage being 16 V, one
must add a resistor (in the range of 22 W) and a 15 V zener
Overcurrent protection resistor, R
with below equation:
can be determined
OCP
CC
to protect the circuit against excessive voltages. Vaux should
be chosen above the Under–Voltage Lockout threshold
(10 V) and below the zener voltage.
R
I
CS
I
Lpk
(33)
R
+
OCP
OCP
Selection of Output Capacitor
The choice of output capacitance value is dictated by the
Current Limiting With Boost Topology Power
Factor Correction Circuit
required hold–up time, t
or the acceptable output ripple
Unlike buck and flyback circuits, because there is no
series switch between input and output in the boost topology,
high current occurring with the start–up inrush current surge
charging the bulk capacitor and fault load conditions cannot
be limited or controlled without additional circuitry.
The MC33260 Zero Current Detection uses the current
sensing information to prevent any power switch turn on as
long as some current flows through the inductor. Then,
during start–up, the power MOSFET is not allowed to turn
on while in–rush current flows. Then there is no risk to have
the power switch destroyed at start–up because of the
in–rush current.
In the same way, in an overload case, the power MOSFET
is kept off as long as there is a direct output capacitor charge
current, i.e., when the input voltage is higher than the output
voltage. Consequently, overload working is fully safe for the
power MOSFET. This is one of the major advantages
compared to MC33262 and competition.
hold
voltage, V for a given application. As a rule of thumb, can
orip
start with 1 mF/watt.
Selection of Semiconductors
Maximum currents and voltages must first be determined
for over all operating conditions to select the MOSFET and
boost rectifier. As a rule of thumb, derate all semiconductors
to about 75–80% of their maximum ratings. This implying
the need of devices with at least 500 V breakdown voltage.
Bipolar transistors are an acceptable alternative to MOSFET
if the switching frequency is maintained fairly low. High
voltage diodes with recovery times of 200 ns, or less should
be used for the boost rectifier. One series of the popular
devices is the MURXXX Ultrafast Rectifier Series from
ON Semiconductor.
Maximum power MOSFET conduction losses.
1.2 V
2
Lpk
ac(LL)
1
6
(29)
P
[
R
ds(on)
I
1 *
(on)max
V
o
Current Limiting for Start–up Inrush
Initially V is zero, when the converter is turned on, the
bulk capacitor will charge resonantly to twice Vin. The
o
Designing the Oscillator Circuit
For traditional boost operation, C is chosen with below
T
voltage can be as high as 750 V if V happens to be at the
in
equation:
peak high–line 265 V condition (375 V). The peak resonant
charging current through the inductor will be many times
greater than normal full load current. the inductor must be
designed to be much larger and more expensive to avoid
saturation. The boost shunt switch cannot do anything to
prevent this and could be worse if turned on during start–up.
The inrush current and voltage overshoot during the
start–up phase is intolerable. A fuse is not suitable, as it will
blow each time the supply is turned on.
2
o
2 K
L P V
osc
P
in
2
C
w
* C
(30)
int
T
2
V
R
ac(LL)
o
Design of Regulation and Overvoltage
Protection Circuit
The output voltage regulation level can be adjusted by R ,
o
V
o
(31)
R
[
There are several methods that may be used to solve the
start–up problem:
o
200 mA
Designing the Current Sense Circuit
The inductor current is converted into a voltage by
inserting a ground referenced resistor, R in series with the
1. Start–up Bypass Rectifier
This is implemented by adding an additional rectifier
bypassing the boost inductor. The bypass rectifier will divert
the start–up inrush current away from the boost inductor as
shown in Figure 3. The bulk capacitor charges through
CS
input diode bridge. Therefore
a negative voltage
proportional to the inductor current is built.
The current sense resistor losses, P
:
Rcs
D
bypass
to the peak AC line voltage without resonant
2
overshoot and without excessive inductor current. D
is
bypass
1
6
(32)
P
+
R
CS
I
Lpk
Rcs
http://onsemi.com
4
AND8016/D
reverse–biased under normal operating conditions. If load
overcurrent pulls down V , D conducts, but this is
probably preferable to having the high current flowing
through boost inductor.
• Regulated DC Output Voltage: V = 400 V
o
dc
o
bypass
• Rated Output Power: P = 80 W
o
• Expected Efficiency, h > 90%
A. The input power, Pin is given by
D
bypass
P
o
80
0.92
P
+
+
+ 86.96 W
in
η
+
B. Input diode current is maximum at
PFC
IC
V
OUT
V
inrms
= V
ac(LL)
Ǹ
Ǹ
V
AC
2 P
2 80
o
I
+
+
+ 1.447 A
inpk
0.92 85
ηV
ac(LL)
C. Inductor design
1. Inductor peak current:
Figure 3. Rectifier bypass of start–up inrush current
I
+ 2I
+ 2 1.447 + 2.894 A
2. External Inrush Current Limiting Circuit
For low power system, a thermistor in series with the
pre–converter input will limit the inrush current. Concern is
the thermistor may not respond fast enough to provide
protection after a line dropout of a few cycles.
A series input resistor shunted by a Triac or SCR is a more
efficient approach. A control circuit is necessary. This
method can function on a cycle–by–cycle basis for
protection after a dropout.
Lpk
inpk
2. Inductor value:
Vo
ǒ
ac(LL)ǓVac(LL)
Lpk
2 t
* V
Ǹ
total
2
L
+
+
p
V I
o
*
6
ǒ
400
* 85Ǔ85
2 40 10
Ǹ
2
+ 1.162 mH
400 2.894
Let the switching cycle t = 40 ms for universal input (85 to
Load Overcurrent Limiting
If an overcurrent condition occurs and exceeds the boost
converter power limit established by the control circuit, V
265 V ) operation.
ac
3. The number of turns required for a selected core size
and material is:
o
will eventually be dragged down below the peak value of the
AC line voltage. If this happens, current will rise rapidly and
without limit through the series inductor and rectifier. This
may result in saturation of the inductor and components will
fail. The control circuit holds off the shunt switch, since the
current limit function is activated. It cannot help to turn the
switch ON – the inductor current will rise even more rapidly
and switch failure will occur.
6
L I
10
A
*
*
6
3
P Lpk
1.162 10
2.894 10
0.3 60
N
+
+
P
B
max e
+ 186.8 turns [ 187 turns
2
Using EPCOS E 30/15/7, B
4. The required air gap to achieve the correct inductance
and storage is:
=0.3 T and A = 60 mm .
e
max
Typically, a power factor correction circuit is connected to
another systems like switched mode power supply or
electronic ballast. These downstream converters typically
will have current limiting capability, eliminating concern
about load faults. However, a downstream converter or the
bulk capacitor might fail. Hence there is a possibility of a
short circuit at the load.
*
7 2
4p10
N
A
p
e
l
+
+
gap
L
P
*
*
7
6
2
4p 10
187 60 10
*3
1.162 10
+ 2.269 mm
If it is considered necessary to limit the current to a safe
value in the event of a downstream fault, some means
external to the boost converter must be provided.
5. Design of Auxiliary Winding
V
N
aux
14 187
(400 * 265)
P
+ ǒV ac(HL)Ǔ
N
+
aux
* V
o
Design Example I – Traditional Boost Constant
Output Voltage Regulation Level Operation
Power Factor Correction
+ 19.4 turns [ 20 turns
Round up to 20 turns to make sure enough voltage at the
auxiliary winding.
The basic design specification concerns the following:
• Mains Voltage Range: V
– V
= 85 – 265 V
ac(LL)
ac(HL) ac
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5
AND8016/D
445
415
D. To determine the output capacitor
As rule of thumb, for 80 W output, start with 100 mF,
385
355
325
295
265
235
205
175
145
115
85
450 V capacitor.
E. Calculation of MOSFET conduction losses
A 8A, 500V MOSFET, MTP8N50E is chosen. The on
resistance, R
[ 1.75 W@100°C. Therefore, maximum
ds(on)
power MOSFET conduction losses is:
1.2 V
2
Lpk
ac(LL)
1
6
Full Load
Half Load
Vacpeak
P
[
+
R
I
1 *
(on)max
ds(on)
V
o
1.2 85
1
6
2
1.75 2.894 1 *
+ 1.82 W
400
85 100 115 1130 145 160 175 190 205 220 235 250 265 280
F. Design of regulation and overvoltage
protection circuit
The output voltage regulation level can be adjusted by R ,
V
(V)
ac
Figure 4. Theoretical Vo versus Vac with CT = 10nF
H. Design of the current sense circuit
o
V
o
400
200 µA
R
[
+
+ 2 MΩ
o
200 µA
Choose R = 0.68 W
cs
1. So the current sense resistor losses, P
:
Rcs
Use two 1 MW resistors in series.
2
2
1
6
1
6
P
+
R
CS
I
+
1 2.894 + 0.949 W
G. Designing the oscillator circuit
Lpk
Rcs
For traditional boost operation, C is chosen with below
T
Therefore the power rating of R is chosen to be 2 W.
2. Overcurrent protection resistor, R
CS
equation:
can be
OCP
2
determined with below equation:
2 K
L P V
osc
P
in
2
o
C
w
* C
+
int
R
I
T
2
CS
I
Lpk
V
R
0.68 2.894
205 µA
ac(LL)
o
R
+
+
+ 9600 Ω
OCP
OCP
2
2 6400 1.162mH 86.96 400
* 15pF + 7.16nF
Use 10000 W resistor. This provide current limit at 3.01 A
versus calculated value of I = 2.894 A.
2
2
85 2MΩ
Lpk
Use 10 nF capacitor.
80 W, Universal Input, Traditional Boost Constant Output Voltage Level Regulation Operation Power Factor
Correction Circuit Part List
Index
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
Value
0.63 mF@600 V
680 nF
Comment
Index
R6
R7
R8
D1
D2
D3
D4
D5
D6
D7
Q1
Value
22 W@0.25 W
100 KW@2 W
1N5406
Comment
Aux Winding Resistor
Start–up Resistor
Input Diode
Filtering Capacitor
Pin 2 V
Capacitor
control
10 nF
Pin 3 Oscillator Capacitor
Aux Capacitor, E–Cap
Output Capacitor, E–Cap
Feedback Filtering Capacitor
Current Sense Resistor
OCP Sensing Resistor
Feedback Resistor
100 mF@50 V
100mF@450V
1 nF@50 V
1N5406
Input Diode
1N5406
Input Diode
1N5406
Input Diode
0.68 W@2 W
10 KW@0.25 W
1 MW@0.25 W
1 MW@0.25 W
10 W@0.25 W
1N4937
Aux Winding Diode
Boost Diode
MUR460
1N5245
Aux 15 V Zener Diode
Power MOSFET
Inductor
Feedback Resistor
MTP8N50E
1.162 mH
Gate Resistor
* E 30/15/7, N67 Material from EPCOS
Primary – 187 turns of # 23 AWG, Secondary – 19 turns of # 23 AWG.
Gap length 2.269mm total for a primary inductance L of 1.162mH.
P
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AND8016/D
D5
R6
D1
D2
D3
D4
R7
D7
C1
L1
+
C4
D5
+
C5
1
2
3
4
8
R5
Q1
7
MC33260
6
C2
R2
5
C3
R1
R3
R4
C6
Figure 5. 80 W Universal Input, Traditional Boost Constant Output Voltage Regulation Level Operation Power
Factor Correction Circuit
Design Table for Universal Input, Traditional Boost Constant Output Voltage Regulation Level Operation Power
Factor Correction
P
25
3.720
33
50
1.860
68
75
1.240
100
100
0.930
100
125
0.744
150
150
0.620
150
200
0.465
220
(Watts)
(mH)
(mF)
W
o
L
P
C
o
R
2
1
0.68
10000
0.63
10
0.5
0.39
9100
1.0
0.33
9100
1.0
0.25
9100
1.0
CS
R
10000
0.22
10
10000
0.63
10
9100
1.0
W
OCP
C
(mF)
(nF)
in
C
10
10
10
10
T
Q
MTP4N50E
MTP8N50E
MTW14N50E
out
D
MUR160
1N4007
MUR460
1N5406
D
in
Design Example II – Follower Boost Variable
Output Voltage Regulation Level Operation
Power Factor Correction
B. Input diode current is maximum at V
=
inrms
V
ac(LL)
Ǹ
Ǹ
2 P
2 80
o
I
+
+
+ 1.447 A
The basic design specification concerns the following:
inpk
0.92 85
ηV
ac(LL)
• Mains Voltage Range: V
– V
= 85 – 265 V
ac(LL)
ac(HL) ac
• Maximum Regulated DC Output Voltage: V = 400 V
o
dc
C. Inductor design
1. Inductor peak current:
• Minimum Regulated DC Output Voltage: V
=
omin
140 V
dc
I
+ 2I
+ 2 1.447 + 2.894 A
Lpk
inpk
• Rated Output Power: P = 80 W
o
2. Inductor value, for follower boost operation, V =
o
• Expected Efficiency, h > 90%
V
omin
:
A. The input power, P is given by
in
P
o
80
0.92
P
+
+
+ 86.96 W
in
η
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7
AND8016/D
Vomin
F. Design of regulation and overvoltage
protection circuit
The output voltage regulation level can be adjusted by R ,
ǒ
Ǔ
2 t
* V
ac(LL)
Ǹ
total
2
L
+
+
o
p
V
I
omin Lpk
V
o
400
200 µA
R
[
+
+ 2 MΩ
o
200 µA
140
*
6
ǒ
* 85Ǔ85
2 40 10
Ǹ
2
Use two 1MW resistors in series.
+ 0.235 µH
140 2.894
G. Designing the Oscillator Circuit
Let the switching cycle t = 40 ms for universal input (85 to
For follower boost operation, C is chosen with below
equation:
265 V ) operation.
3. The number of turns required for a selected core size
and material is:
T
ac
2
o
2 K
L P V
osc
P
in
2
C
w
* C
+
6
int
L I
P Lpk
10
T
2
V
R
ac(LL)
o
N
+
+
P
B
A
max e
2
2 6400 0.234mH 86.96 140
* 15pF + 162 pF
*
6
3
2
2
0.235 10
2.894 10
85 2 MΩ
+ 70.6 turns [ 71 turns
0.3 32.1
Use 150 pF capacitor.
Using EPCOS E 20/10/6, N67 material, B
=0.3 T and
max
2
A = 32.1 mm .
e
445
415
385
355
325
295
265
235
205
175
145
115
85
4. The required air gap to achieve the correct inductance
and storage is:
*
7 2
4p10
N
A
p
e
l
+
+
gap
L
P
*
*
7
6
2
4p 10
71 32.1 10
*3
0.235 10
+ 0.856 mm
Full Load
Half Load
Vacpeak
5. Design of Auxiliary Winding
V
N
aux
P
14 71
(400 * 265)
+ ǒV ac(HL)Ǔ
N
+
aux
85 100 115 1130 145 160 175 190 205 220 235 250 265 280
(V)
* V
o
V
ac
+ 7.4 turns [ 8 turns
Figure 6. Theoretical Vo versus Vac with CT = 150pF
H. Design of the Current Sense Circuit
Round up to 8 turns to make sure enough voltage at the
auxiliary winding.
Choose R = 0.68 W
1. So the current sense resistor losses, P
cs
D. To determine the output capacitor
As rule of thumb, for 80 W output, start with 100 mF,
450 V capacitor.
:
Rcs
2
1
6
1
6
P
+
+
R
CS
I
Lpk
Rcs
2
0.68 2.894 + 0.949 W
E. Calculation of MOSFET conduction losses
A 4A, 500 V MOSFET, MTP4N50E is chosen. The on
2. Overcurrent protection resistor, R
determined with below equation:
can be
OCP
resistance, R
[ 1.75 W@100°C. Therefore, maximum
ds(on)
power MOSFET conduction losses is:
R
I
CS
Lpk
1.2 V
0.68 2.894
205 µA
2
Lpk
ac(LL)
R
+
+
+ 9600 Ω
1
6
OCP
P
[
+
R
I
1 *
I
(on)max
ds(on)
OCP
V
omin
Use 10000 W resistor. This provide current limit at 3.01 A
versus calculated value of I = 2.894 A.
1.2 85
1
6
2
1.75 2.894 1 *
+ 0.66 W
Lpk
140
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AND8016/D
80 W, Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power Factor
Correction Circuit Part List
Index
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
Value
Comment
Index
R6
Value
22 W@0.25 W
100 KW@2 W
1N5406
Comment
Aux Winding Resistor
Start–up Resistor
Input Diode
0.63 mF@600 V
680 nF
Filtering Capacitor
Pin 2 V
Capacitor
R7
control
150 pF
Pin 3 Oscillator Capacitor
Aux Capacitor, E–Cap
Output Capacitor, E–Cap
Feedback Filtering Capacitor
Current Sense Resistor
OCP Sensing Resistor
Feedback Resistor
D1
100 mF@50 V
100 mF@450 V
1 nF@50 V
D2
1N5406
Input Diode
D3
1N5406
Input Diode
D4
1N5406
Input Diode
0.68 W@2 W
10 KW@0.25 W
1 MW@0.25 W
1 MW@0.25 W
10 W@0.25 W
D5
1N4937
Aux Winding Diode
Boost Diode
D6
MUR460
D7
1N5245
Aux 15 V Zener Diode
Power MOSFET
Inductor
Feedback Resistor
Q1
L1*
MTP4N50E
0.235 mH
Gate Resistor
* E 20/10/6, N67 Material from EPCOS
Primary – 71 turns of # 23 AWG, Secondary – 8 turns of # 23 AWG.
Gap length 0.865 mm total for a primary inductance L of 0.235 mH.
P
D5
R6
D1
D2
D3
D4
R7
D7
C1
L1
+
C4
D5
+
C5
1
2
3
4
8
7
6
5
R5
Q1
MC33260
C2
R2
C3
R1
R3
R4
C6
Figure 7. 80 W Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power Factor
Correction Circuit
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AND8016/D
Design Table for Universal Input, Follower Boost Variable Output Voltage Regulation Level Operation Power
Factor Correction
P
25
0.752
33
50
376
68
75
100
0.188
100
125
0.150
150
150
0.102
150
200
0.094
220
(Watts)
(mH)
(mF)
W
o
L
P
0.251
100
C
o
R
2
1
0.68
0.5
0.39
9100
1.0
0.33
0.25
9100
1.0
CS
R
10000
0.22
0.162
10000
0.63
0.162
10000
0.63
9100
1.0
9100
W
OCP
C
1.0
(mF)
(nF)
in
C
0.162
0.162
0.162
0.162
MTP8N50E
0.162
T
Q
MTD2N50E
MTP4N50E
D
MUR160
1N4007
MUR460
out
D
1N5406
1N5406
in
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AND8016/D
Notes
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11
AND8016/D
Greenline is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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AND8016/D
AND8123/D
Power Factor Correction
Stages Operating in Critical
Conduction Mode
Prepared by: Joel Turchi
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
This paper proposes a detailed and mathematical analysis
of the operation of a critical conduction mode Power factor
Corrector (PFC), with the goal of easing the PFC stage
dimensioning. After some words on the PFC specification
and a brief presentation of the main critical conduction
schemes, this application note gives the equations necessary
for computing the magnitude of the currents and voltages
that are critical in the choice of the power components.
Basics of the Critical Conduction Mode
Critical conduction mode (or border line conduction
mode) operation is the most popular solution for low power
applications. Characterized by a variable frequency control
scheme in which the inductor current ramps to twice the
desired average value, ramps down to zero, then
immediately ramps positive again (refer to Figures 2 and 4),
this control method has the following advantages:
• Simple Control Scheme: The application requires few
external components.
INTRODUCTION
• Ease of Stabilization: The boost keeps a first order
converter and there is no need for ramp compensation.
The IEC1000−3−2 specification, usually named Power
Factor Correction (PFC) standard, has been issued with the
goal of minimizing the Total Harmonic Distortion (THD) of
the current that is drawn from the mains. In practice, the
legislation requests the current to be nearly sinusoidal and in
phase with the AC line voltage.
• Zero Current Turn On: One major benefit of critical
conduction mode is the MOSFET turn on when the
diode current reaches zero. Therefore the MOSFET
switch on is lossless and soft and there is no need for
a low trr diode.
On the other hand, the critical conduction mode has some
disadvantages:
• Large peak currents that result in high dl/dt and rms
currents conducted throughout the PFC stage.
• Large switching frequency variations as detailed in
the paper.
Active solutions are the most effective means to meet the
legislation. A PFC pre−regulator is inserted between the
input bridge and the bulk capacitor. This intermediate stage
is designed to output a constant voltage while drawing a
sinusoidal current from the line. In practice, the step−up (or
boost) configuration is adopted, as this type of converter is
easy to implement. One can just notice that this topology
requires the output to be higher than the input voltage. That
is why the output regulation level is generally set to around
400 V in universal mains conditions.
Diode Bridge
PFC Stage
Power Supply
+
−
+
Bulk
Capacitor
AC
Line
Controller
LOAD
IN
Figure 1. Power Factor Corrected Power Converter
PFC boost pre−converters typically require a coil, a diode and a Power Switch. This stage also needs a Power Factor Correction
controller that is a circuit specially designed to drive PFC pre−regulators. ON Semiconductor has developed three controllers
(MC33262, MC33368 and MC33260) that operate in critical mode and the NCP1650 for continuous mode applications.
One generally devotes critical conduction mode to power factor control circuits below 300 W.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
September, 2003 − Rev. 1
AND8123/D
AND8123/D
Diode Bridge
Diode Bridge
Icoil
+
−
+
−
Icoil
L
L
+
V
in
V
in
V
out
IN
IN
The power switch is ON
The power switch being about zero, the input
The power switch is OFF
The coil current flows through the diode. The coil
voltage is applied across the coil. The coil current
voltage is (V −V ) and the coil current linearly decays
out in
linearly increases with a (V /L) slope.
with a (V −V )/L slope.
in
out in
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
Coil
Current
V /L
in
(V −V )/L
out in
Icoil_pk
Figure 2. Switching Sequences of the PFC Stage
In critical discontinuous mode, a boost converter presents
two phases (refer to Figure 2):
levels of the output voltage. The error amplifier
bandwidth is set low so that the error amplifier output
reacts very slowly and can be considered as a constant
within an AC line period.
• The on−time during which the power switch is on. The
inductor current grows up linearly according to a slope
• The controller multiplies the shaping information by
the error amplifier output voltage. The resulting product
is the desired envelope that as wished, is sinusoidal, in
phase with the AC line and whose amplitude depends
on the amount of power to be delivered.
(V /L) where V is the instantaneous input voltage and
L the inductor value.
in
in
• The off time during which the power switch is off. The
inductor current decreases linearly according to the
slope (V −V )/L where V is the output voltage.
out in
out
• The controller monitors the power switch current.
When this current exceeds the envelope level, the PWM
latch is reset to turn off the power switch.
This sequence terminates when the current equals zero.
Consequently, a triangular current flows through the coil.
The PFC stage adjusts the amplitude of these triangles so
that in average, the coil current is a (rectified) sinusoid (refer
to Figure 4). The EMI filter (helped by the 100 nF to 1.0 mF
input capacitor generally placed across the diodes bridge
output), performs the filtering function.
The more popular scheme to control the triangles
magnitude and shape the current, forces the inductor peak
current to follow a sinusoidal envelope. Figure 3
diagrammatically portrays its operation mode that could be
summarized as follows:
• Some circuitry detects the core reset to set the PWM
latch and initialize a new MOSFET conduction phase
as soon as the coil current has reached zero.
Consequently, when the power switch is ON, the current
ramps up from zero up to the envelope level. At that
moment, the power switch turns off and the current ramps
down to zero (refer to Figures 2 and 4). For simplicity of the
drawing, Figure 4 only shows 8 “current triangles”.
Actually, their frequency is very high compared to the AC
line one. The input filtering capacitor and the EMI filter
averages the “triangles” of the coil current, to give:
• The diode bridge output being slightly filtered, the
input voltage (V ) is a rectified sinusoid. One pin of
in
the PFC controller receives a portion of V . The
voltage of this terminal is the shaping information
necessary to build the current envelope.
in
Icoil_pk
(eq. 1)
t Icoil u
+
T
2
where <Icoil> is the average of one current triangle
(period T) and Icoil_pk is the peak current of this triangle.
T
• An error amplifier evaluates the power need in response
to the error it senses between the actual and wished
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2
AND8123/D
As Icoil_pk is forced to follow a sinusoidal
envelop (k*V ), where k is a constant modulated
Ǹ
k * 2 * Vac * sin(wt)
k * Vin
2
ǒ
t Icoil u
+
+
Ǔ
.
As
a
T
in
2
by the error amplifier, <Icoil> is also sinusoidal
T
result, this scheme makes the AC line current sinusoidal.
PFC Stage
D1
V
in
L1
+
C1
Bulk
Capacitor
Input
Filtering
Capacitor
AC Line
X1
Current Sensing
Resistor
R7
PWM Latch
S
Zero Current
Detection
Output Buffer
Q
+
R
−
Current
Envelope
Current Sense
Comparator
R3
R4
R1
R2
C2
−
+
Vref
Error
Amplifier
Multiplier
Figure 3. Switching Sequences of the PFC Stage
The controller monitors the input and output voltages and using this information and a multiplier, builds a sinusoidal envelope. When the
sensed current exceeds the envelope level, the Current Sense Comparator resets the PWM latch and the power switch turns off. Once
the core has reset, a dedicated block sets the PWM latch and a new MOSFET conduction time starts.
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AND8123/D
Peak
Icoil_pk
Average (<Icoil>T)
Inductor Current
(Icoil)
Tac/2
T
(Tac is the
AC line period)
MOSFET
DRIVE
Figure 4. Coil Current
During the power switch conduction time, the current ramps up from zero up to the envelope level. At that
moment, the power switch turns off and the current ramps down to zero. For simplicity of the drawing,
only 8 “current triangles” are shown. Actually, their frequency is very high compared to the AC line one.
t Pin u
Vac
One can note that a simple calculation would show that the on−time is constant over the sinusoid: ton + 2 * L *
and
2
that the switching frequency modulation is brought by the off−time that equals:
Ǹ
2 * Vac * sin(wt)
t Pin u
Vac * (Vout * 2 * Vac * sin(wt))
Ǹ
(eq. 2)
toff + 2 * 2 * L *
* sin(wt) + ton *
Ǹ
Ǹ
Vout * 2 * Vac * sin(wt)
That is why the MC33260 developed by ON Semiconductor
does not incorporate a multiplier inputting a portion of the
rectified AC line to shape the coil current. Instead, this part
forces a constant on−time to achieve in a simplest manner, the
power factor correction.
Main Equations
• The power switch off time (toff). During this second
phase, the coil current flows through the output diode
and feeds the output capacitor and the load. The diode
voltage being considered as null when on, the voltage
across the coil becomes negative and equal to
Switching Frequency
As already stated, the coil current consists of two phases:
• The power switch conduction time (ton). During this
time, the input voltage applies across the coil and the
current increases linearly through the coil with a
(V −V ). The coil current decreases then linearly with
in out
the slope ((V −V )/L) from (Icoil_pk) to zero, as
out in
(V /L) slope:
in
follows:
Vin
L
(eq. 3)
Icoil(t) +
* t
Vout * Vin
(eq. 6)
Icoil(t) + Icoil_pk * ǒ
* tǓ
L
This phase ends when the conduction time (ton) is
complete that is when the coil current has reached its peak
value (Icoil_pk). Thus:
This phase ends when Icoil reaches zero, then the off−time
is given by the following equation:
L * Icoil_pk
Vout * Vin
Vin
L
(eq. 4)
Icoil_pk +
* ton
(eq. 7)
toff +
The conduction time is then given by:
The total current cycle (and then the switching period, T)
is the sum of ton and toff. Thus:
L * Icoil_pk
(eq. 5)
ton +
Vin
Vout
(eq. 8)
T + ton ) toff + L * Icoil_pk *
Vin * (Vout * Vin)
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4
AND8123/D
20
As shown in the next paragraph (equation 15), the coil
peak current can be expressed as a function of the input
power and the AC line rms voltage as follows:
t Pin u
Ǹ
Icoil_pk + 2 * 2 *
* sin(wt) , where w is the AC
Vac
line angular frequency. Replacing Icoil_pk by this
expression in equation (8) leads to:
10
L *t Pin u
Ǹ
T + 2 * 2 *
* sin(wt)
Vac
(eq. 9)
Vout
*
Ǹ
2 * Vac * sin(wt) * (Vout * Vin)
This equation simplifies:
0
0
50
100
150
200
2 * L *t Pin u * Vout
Vac * (Vout * Vin)
T +
(eq. 10)
2
Pin (W)
The switching frequency is the inverse of the switching
period. Consequently:
Figure 6. Switching Frequency vs. the Input Power
(at the Sinusoid top)
Ǹ
This plot sketches the switching frequency variations versus the
input power in a normalized form where f(200 W) = 1. The
switching frequency is multiplied by 20 when the power is 10 W.
In practice, the PFC stage propagation delays clamp the
switching frequency that could theoretically exceed several
megaHertz in very light load conditions. The MC33260 minimum
off−time limits the no load frequency to around 400 kHz.
2
2 * Vac * sin(wt)
Vac
2 * L *t Pin u
(eq. 11)
f +
ǒ
1 *
Ǔ
Vout
This equation shows that the switching frequency
consists of:
2
Vac
• One term ǒ2 * L *t Pin uǓthat only varies versus the
working point (load and AC line rms voltage).
1.5
Ǹ
2 * Vac * sin(wt)
• A modulation factor
ǒ
1 *
Ǔ
that
Vout
makes the switching frequency vary within the AC line
sinusoid.
The following figure illustrates the switching frequency
variations versus the AC line amplitude, the power and
within the sinusoid.
1.0
sin (wt)
0.5
2.50
f
2.00
1.50
1.00
0.50
0
0
1.0
2.0
3.0
wt
Figure 7. Switching Frequency Over the AC Line
Sinusoid @ 230 Vac
This plot gives the switching variations over the AC line sinusoid
at Vac = 230 V and V = 400 V, in a normalized form where f
is taken equal to 1 at the AC line zero crossing. The switching
frequency is approximately divided by 5 at the top of the
sinusoid.
out
80
110
140
170
V , (V)
200
230
260
290
ac
Figure 5. Switching Frequency Over the AC Line
RMS Voltage (at the Sinusoid top)
The figure represents the switching frequency variations versus
the line rms voltage, in a normalized form where f(90) = 1. The
plot drawn for V = 400 V, shows large variations (200% at Vac =
out
180 V, 60% at Vac = 270 V). The shape of the curve tends to
flatten if V is higher. However, the minimum of the switching
out
frequency is always obtained at one of the AC line extremes
(VacLL or VacHL where VacLL and VacHL are respectively, the
lowest and highest Vac levels).
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AND8123/D
1.5
1.0
0.5
0
Provided that the AC line current results from the
averaging of the coil current, one can deduct the following
equation:
Icoil_pk
(eq. 13)
lin(t) +t Icoil u
+
T
2
sin (wt)
where <Icoil> is the average of the considered coil current
T
triangle over the switching period T and Icoil_pk is the
corresponding peak.
Thus, the peak value of the coil current triangles follows
a sinusoidal envelope and equals:
f
Ǹ
(eq. 14)
Icoil_pk + 2 * 2 * lac * sin(wt)
Since the PFC stage forces the power factor close to 1, one
can use the well known relationship linking the average
input power to the AC line rms current and rms voltage
(t Pin u+ Vac * lac) and the precedent equation leads to:
0
1.0
2.0
3.0
wt
Figure 8. Switching Frequency Over the AC Line
Sinusoid @ 90 Vac
t Pin u
Ǹ
This plot shows the same characteristic but for Vac = 90 V.
(eq. 15)
Icoil_pk + 2 * 2 *
* sin(wt)
Vac
Similarly to what was observed in Figure 5 (f versus Vac), the
higher the difference between the output and input voltages,
the flatter the switching frequency shape.
The coil current peak is maximum at the top of the
sinusoid where sin(ùt) + 1. This maximum value,
(Icoil_pk)H, is then:
Finally, the switching frequency dramatically varies
within the AC line and versus the power. This is probably the
major inconvenience of the critical conduction mode
operation. This behavior often makes tougher the EMI
filtering. It also can increase the risk of generating
interference that disturb the systems powered by the PFC
stage (for instance, it may produce some visible noise on the
screen of a monitor).
In addition, the variations of the frequency and the high
values it can reach (up to 500 kHz) practically prevent the
use of effective tools to damp EMI and reduce noise like
snubbing networks that would generate too high losses.
One can also note that the frequency increases when the
power diminishes and when the input voltage increases. In
light load conditions, the switching period can become as
low as 2.0 ms (500 kHz). All the propagation delays within
the control circuitry or the power switch reaction times are
no more negligible, what generally distorts the current
shape. The power factor is then degraded.
t Pin u
Ǹ
(eq. 16)
(Icoil_pk)H + 2 * 2 *
Vac
From this equation, one can easily deduct that the peak
coil current is maximum when the required power is
maximum and the AC line at its minimum voltage:
t Pin u max
Ǹ
(eq. 17)
Icoil_max + 2 * 2 *
VacLL
where <Pin>max is the maximum input power of the
application and VacLL the lowest level of the AC line
voltage.
Coil RMS Current
The rms value of a current is the magnitude that squared,
gives the dissipation produced by this current within a 1.0 W
resistor. One must then compute the rms coil current by:
• First calculating the “rms current” within a switching
period in such a way that once squared, it would give
the power dissipated in a 1.0 W resistor during the
considered switching period.
The switching frequency variation is a major limitation of
the system that should be reserved to application where the
load does not vary drastically.
• Then the switching period being small compared to the
input voltage cycle, regarding the obtained expression
as the instantaneous square of the coil current and
averaging it over the rectified sinusoid cycle, to have
the squared coil rms current.
This method will be used in this section.
As above explained, the current flowing through the
coil is:
Coil Peak and RMS Currents
Coil Peak Current
As the PFC stage makes the AC line current sinusoidal and
in phase with the AC line voltage, one can write:
Ǹ
(eq. 12)
lin(t) + 2 * lac * sin(wt)
• (I (t) + Vin * tńL + Icoil_pk * tńton) during the
M
MOSFET on−time, when 0<t<ton.
where Iin(t) is the instantaneous AC line current and Iac its
rms value.
NJ
Nj
• (I (t) + Icoil_pk− (Vout−Vin) * tńL + Icoil_pk * (T * t)ń
D
(T * ton) ) during the diode conduction time, that is,
when ton<t<T.
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AND8123/D
Therefore, the rms value of any coil current triangle over the corresponding switching period T, is given by the following
equation:
ton
2
2
T ƪIcoil_pk *
ƫ
Icoil_pk * t
ƪ ƫ
ton
T * t
T * ton
1
T
ŕ
ŕ
(eq. 18)
t (Icoil)rms u
+
*
* dt )
* dt
ǒ
Ǔ
Ǹ
T
0
ton
Solving the integrals, it becomes:
(eq. 19)
3
3
2
Icoil_pk
3
ton
3
* (T * ton)
3 * Icoil_pk
T * ton
T * ton
1
T
T * T
T * ton
ƪ
ƫ ƪ
ƫ
ƪ
ƫ)
* ǒ Icoil_pk *
Ǔ
ƫ
t (Icoil)rms u
+
*
*
ƪ
* Icoil_pk *
ǒ
Ǔ
Ǹ
T
2
ton
The precedent simplifies as follows:
2
Icoil_pk * ton
3
* (T * ton)
3 * Icoil_pk
1
T
3
)
(eq. 20)
(
) ƪ
ƫ
Ǔ
t (Icoil)rms u
+
*
ǒ
* * Icoil_pk
Ǹ
T
Rearrangement of the terms leads to:
gives the resistive losses at this given V . Now to have the
in
rms current over the rectified AC line period, one must not
(eq. 21)
integrate <(Icoil)rms> but the square of it, as we would
T
ton T * ton
1
T
* ǒ
Ǔ
t (Icoil)rms u + I
coil_pk
*
Ǹ
)
have proceeded to deduct the average resistive losses from
the dissipation over one switching period. However, one
must not forget to extract the root square of the result to
obtain the rms value.
T
3
3
Calculating the term under the root square sign, the
following expression is obtained:
As the consequence, the coil rms current is:
Icoil_pk
(eq. 22)
+
t (Icoil)rms u
T
Ǹ
(eq. 24)
3
Tacń2
Replacing the coil peak current by its expression as a
function of the average input power and the AC line rms
voltage (equation 15), one can write the following equation:
2
Tac
ŕ
2
* dt
(Icoil)rms +
*
t (I )rms u
coil
Ǹ
T
0
2
3
t Pin u
* sin(wt)
where Tac = 2*p/w is the AC line period (20 ms in Europe,
16.66 ms in USA). The PFC stage being fed by the rectified
AC line voltage, it operates at twice the AC line frequency.
That is why, one integrates over half the AC line period
(Tac/2).
+ 2 * Ǹ
(eq. 23)
t (Icoil)rms u
*
T
Vac
This equation gives the equivalent rms current of the coil
over one switching period, that is, at a given V . As already
in
stated, multiplying the square of it by the coil resistance,
Substitution of equation (23) into the precedent equation leads to:
Tacń2
2
2
Tac
2
3
t Pin u
ŕ
(eq. 25)
ƪ2 * Ǹ
* sin(wt)ƫ
(Icoil)rms +
*
*
* dt
Ǹ
Vac
0
This equation shows that the coil rms current is the rms
Therefore:
2
3
t Pin u
2
t Pin u
*
(eq. 26)
2 * Ǹ
value of:
*
* sin(wt), that is, the rms
Icoil(rms) +
Ǹ
Vac
Vac
3
value of a sinusoidal current whose magnitude is
2
3
t Pin u
(2 * Ǹ
*
). The rms value of such a sinusoidal
Vac
Ǹ
current is well known (the amplitude divided by 2).
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AND8123/D
Switching Losses
• The output voltage is considered as a constant. The
output voltage ripple being generally less than 5% the
nominal voltage, this assumption seems reasonable.
The switching losses are difficult to determine with
accuracy. They depend of the MOSFET type and in
particular of the gate charge, of the controller driver
capability and obviously of the switching frequency that
varies dramatically in a critical conduction mode operation.
However, one can make a rough estimation if one assumes
the following:
• The switching times (dt and t , as defined in
FR
Figure 9), are considered as constant over the sinusoid.
Dissipated Power:
(IMOSFET * Vdrain)
tFR
IMOSFET
Vdrain
dt
Figure 9. Turn Off Waveforms
(eq. 27)
Figure 9 represents a turn off sequence. One can observe
three phases:
Vout * Icoil_pk dt−t
FR
t
FR
T
) ǒVout * Icoil_pk *
Ǔ
psw + ǒ
Ǔ
*
• During approximately the second half of the gate
voltage Miller plateau, the drain−source voltage
increases linearly till it reaches the output voltage.
2
T
where: dt and t are the switching times portrayed by
FR
Figure 9 and T is the switching period.
Equation (8) gives an expression linking the coil peak
current and the switching period of the considered current
• During a short time that is part of the diode forward
recovery time, the MOSFET faces both maximum
voltage and current.
L * Icoil_pk
Vout
cycle (triangle): T +
*
.
• The gate voltage drops (from the Miller plateau) below
the gate threshold and the drain current ramps down
to zero.
Vin
Vout * Vin
Substitution of equation (8) into the equation (27) leads
to:
“dt” of Figure 9 represents the total time of the three phases,
“t ’’ the second phase duration.
FR
Vin * (Vout * Vin) * (dt ) t
)
FR
(eq. 28)
psw +
2 * L
Therefore, one can write:
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8
AND8123/D
(eq. 29)
This equation shows that the switching losses over a
Tacń2
switching period depend of the instantaneous input voltage,
the difference between the instantaneous output and input
voltages, the switching time and the coil value. Let’s
calculate the average losses (<psw>) by integrating psw
over half the AC line period:
Vin * (Vout * Vin) * (dt ) t
)
2
Tac
FR
ŕ
t psw u+
*
* dt
2 * L
0
Rearranging the terms, one obtains:
Tacń2
Tacń2
ȡ
Ȣ
ȣ
Ȥ
dt ) t
FR
2 * L
2
Tac
2
Tac
ŕ
ŕ
2
Vin * dt
(eq. 30)
t psw u+
*
*
Vin * Vout * dt
*
*
ȥǒ
Ǔ ǒ ǓȦ
0
0
V
being considered as a constant, one can easily
Q3 being not always specified, instead, one can take
the sum of Q1 with half the Miller plateau gate charge
(Q2/2). Knowing the drive capability of the circuit,
out
solve this equation if one remembers that the input
Ǹ
voltage average value is (2 * 2 * Vacńp) and that
one can deduct the turn off time (dt = Q3/I
or dt =
drive
Tacń2
2
Tac
ŕ
2
2
[Q1 + (Q2/2)]/I ).
drive
(Vac
+
*
Vin * dt). Applying this, it becomes:
0
• In a first approach, t can be taken equal to the diode
FR
forward recovery time.
(eq. 31)
Ǹ
dt ) t
2 * L
2 * 2 * Vac * Vout
2
FR
* ǒ
* Vac Ǔ
t psw u+
12
p
QT
Or in a simpler manner:
V
DS
V
GS
9
6
(eq. 32)
2
2 * (dt ) t ) * Vac
FR
Vout
p
4
* ǒǸ2 * Vac
Ǔ
t psw u+
*
p * L
The coil inductance (L) plays an important role: the losses
are inversely proportional to this value. It is simply because
the switching frequency is also inversely proportional to L.
This equation also shows that the switching losses are
independent of the power level. One could have easily
predict this result by simply noting that the switching
frequency increased when power diminished.
Q2
Q1
3
0
I
= 2.3 A
Q3
D
T = 25°C
J
Q , TOTAL GATE CHARGE (nC)
T
Equation (32) also shows that the lower the ratio
Figure 10. Typical Total Gate Charge Specification
of a MOSFET
(V /Vac), the smaller the MOSFET switching losses. That
out
is because the “Follower Boost” mode that reduces the
difference between the output and input voltages, lowers the
switching frequency. In other words, this technique enables
the use of a smaller coil for the same switching frequency
range and the same switching losses.
One must note that the calculation does not take into
account:
• The energy consumed by the controller to drive the
MOSFET (Qcc*Vcc*f), where Qcc is the MOSFET
gate charge necessary to charge the gate voltage to Vcc,
Vcc the driver supply voltage and f the switching
frequency.
For instance, the MC33260 features the “Follower Boost”
operation where the pre−converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
• The energy dissipated because of the parasitic
1
minimize the cost of the PFC stage .
capacitors of the PFC stage. Each turn on produces an
abrupt voltage change across the parasitic capacitors of
the MOSFET drain−source, the diode and the coil. This
How to extract dt and t
?
FR
• The best is to measure them.
• One can approximate dt as the time necessary to extract
the gate charge Q3 of the MOSFET (refer to Figure 10).
results in some extra dissipation across the MOSFET
2
(1/2*C
*DV *f), where C
is the
parasitic
parasitic
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AND8123/D
Power MOSFET Conduction Losses
considered parasitic capacitor and DV the voltage
As portrayed by Figure 4, the coil current is formed by
high frequency triangles. The input capacitor together with
the input RFI filter integrates the coil current ripple so that
the resulting AC line current is sinusoidal.
change across it.
1
Refer to MC33260 data sheet for more details at
http://www.onsemi.com/.
During the on−time, the current rises linearly through the
power switch as follows:
However, equation (32) should give a sufficient first
approach approximation in most applications where the two
listed sources of losses play a minor role. Nevertheless, the
losses produced by the parasitic capacitors may become
significant in light load conditions where the switching
frequency gets high. As always, bench validation is key.
Vin
L
(eq. 33)
Icoil(t) +
* t
Ǹ
where V is the input voltage (Vin + 2 * Vac * sin(wt) ), L
in
is the coil inductance and t is the time.
During the rest of the switching period, the power switch is off. The conduction losses resulting from the power dissipated
by Icoil during the on−time, one can calculate the power during the switching period T as follows:
ton
ton
2
1
T
1
T
Vin
L
ŕ
ŕ
2
Ron * ǒ * tǓ
(eq. 34)
p
T
+
*
Ron * Icoil(t) * dt +
*
* dt
0
0
where Ron is the MOSFET on−time drain source resistor,
ton is the on−time.
Solving the integral, equation (34) simplifies as follows:
One can calculate the duty cycle (d = ton/T) by:
• Either noting that the off−time (toff) can be expressed as
a function of ton (refer to equation 2) and substituting
this equation into (T = ton + Toff),
(eq. 35)
ton
2
2
3
ton
T
• Or considering that the critical conduction mode being
at the border of the continuous conduction mode
(CCM), the expression giving the duty−cycle in a CCM
boost converter applies.
Ron
T
Vin
L
1
3
Vin
L
ŕ
2
* ǒ Ǔ
* Ron * ǒ Ǔ
p
T
+
*
t * dt +
*
0
As the coil current reaches its peak value at the end of the
on−time, Icoil_pk + Vin * tonńL and the precedent equation
can be rewritten as follows:
Both methods lead to the same following result:
ton
T
Vin
Vout
(eq. 37)
d +
+ 1 *
ton
T
1
3
2
* Ron * Icoil_pk *
(eq. 36)
p
T
+
Substitution of equation (37) into equation (36) leads to:
One can recognize the traditional equation permitting to
calculate the MOSFET conduction losses in a boost or a
1
3
Vin
Vout
2
(eq. 38)
* Ron * Icoil_pk * ǒ1 *
Ǔ
p
T
+
1
3
2
flyback ( * Ron * Ipk * d, where Ipk is the peak current and
One can note that the coil peak current (Icoil_pk) that
follows a sinusoidal envelop, can be written as follows:
d, the MOSFET duty cycle).
t Pin u
Ǹ
Icoil_pk + 2 * 2 *
* sin(wt) (refer to equation 15).
Vac
t Pin u
Ǹ
Ǹ
Replacing V and Icoil_pk by their sinusoidal expression, respectively ( 2 * Vac * sin(wt) ) and (2 * 2 *
* sin(wt) ),
in
Vac
equation (38) becomes:
Ǹ
2
2 * Vac * sin(wt)
1
3
t Pin u
Ǹ
(eq. 39)
* Ron * ǒ2 * 2 *
* sin(wt)Ǔ
p
T
+
*
ǒ
1 *
Ǔ
Vac
Vout
That is in a more compact form:
Ǹ
2
2 * Vac
Vout
8
3
t Pin u
2
3
(eq. 40)
* Ron * ǒ
Ǔ
sin (wt) * ǒ * sin (wt)Ǔ
p
T
+
*
ƪ
ƫ
Vac
Equation (40) gives the conduction losses at a given V voltage. This equation must be integrated over the rectified AC line
in
sinusoid to obtain the average losses:
Taŕcń2
2
3
Ǹ
2
2 * Vac
Vout
8
3
t Pin u
2
Tac
(eq. 41)
* Ron * ǒ
Ǔ
sin (wt) * ǒ * sin (wt)Ǔ
t p u
+
*
*
* dt
ƪ
ƫ
Tac
Vac
0
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AND8123/D
2
If the average value of sin (wt) is well known (0.5), the
sin(a ) b) ) sin(a * b)
• sin(a) * cos(b) +
3
2
calculation of <sin (wt)> requires few trigonometry
Combining the two precedent formulas, one can obtain:
remembers:
1 * cos(2a)
3 * sin(wt) sin(3wt)
2
(eq. 42)
3
• sin (a) +
sin (wt) +
*
2
4
4
Substitution of equation 42) into equation (41) leads:
(eq. 43)
* dt
Taŕcń2
2
Ǹ
Ǹ
2 * Vac
4 * Vout
2
3 * 2 * Vac
4 * Vout
8
3
t Pin u
2
Tac
* Ron * ǒ
Ǔ
sin(wt) * ǒ
* sin(wt)Ǔ) ǒ * sin(3wt)Ǔ
t p u
+
*
*
ƪ
ƫ
Tac
Vac
0
Solving the integral, it becomes:
Ǹ
Ǹ
2
3 * 2 * Vac
2 * Vac
8
3
t Pin u
1
2
2
2
(eq. 44)
(eq. 45)
* Ron * ǒ
Ǔ
* ǒ
Ǔ) ǒ Ǔ
t p u
+
*
ƪ
*
*
ƫ
Tac
p
3p
4 * Vout
Vac
4 * Vout
Equation (44) simplifies as follows:
Ǹ
2
8 * 2 * Vac
4
t Pin u
* Ron * ǒ
Ǔ
1 * ǒ Ǔ
t p u
+
*
ƪ
ƫ
Tac
3
Vac
3p * Vout
This formula shows that the higher the ratio (Vac/V ),
The MC33260 monitors the whole coil current by
monitoring the voltage across a resistor inserted between
ground and the diodes bridge (negative sensing – refer to
Figure 15). The circuit utilizes the current information for
both the overcurrent protection and the core reset detection
(also named zero current detection). This technique brings
two major benefits:
out
the smaller the MOSFET conduction losses. That is why the
“Follower Boost” mode that reduces the difference between
the output and input voltages, enables to reduce the
MOSFET size.
For instance, the MC33260 features the “Follower Boost”
operation where the pre−converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
• No need for an auxiliary winding to detect the core
reset. A simple coil is sufficient in the PFC stage.
• The MC33260 detects the in−rush currents that may
flow at start−up or during some overload conditions and
prevents the power switch from turning on in that
stressful condition. The PFC stage is significantly safer.
Some increase of the power dissipated by the current
sense resistor is the counter part since the whole current is
sensed while circuits like the MC33262 only monitor the
power switch current.
2
minimize the cost of the PFC stage .
By the way, one can deduct from this equation the rms
current ((I )rms) flowing through the power switch
M
2
knowing that t p u
+ Ron * (I ) rms :
Tac
M
Ǹ
8 * 2 * Vac
2
t Pin u
*
(eq. 46)
1 * ǒ Ǔ
(I )rms +
*
Ǹ
M
Ǹ
Vac
3p * Vout
3
Dissipation of the Current Sense Resistor in MC33262
Like Circuits
Since the same current flows through the current sense
resistor and the power switch, the calculation is rather easy.
One must just square the rms value of the power switch
Dissipation within the Current Sense Resistor
PFC controllers monitor the power switch current either
to perform the shaping function or simply to prevent it from
being excessive. That is why a resistor is traditionally placed
between the MOSFET source and ground to sense the power
switch current.
current (I )rms calculated in the previous section and
M
multiply the result by the current sense resistance.
2
Refer to MC33260 data sheet for more details at
http://www.onsemi.com/.
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AND8123/D
Doing this, one obtains:
Ǹ
2
8 * 2 * Vac
4
3
t Pin u
* Rs * ǒ
Ǔ
(eq. 47)
1 * ǒ Ǔ
t pRs u
+
*
ƪ
ƫ
262
Vac
3p * Vout
where <pRs> is the power dissipated by the current sense resistor Rs.
262
Dissipation of the Current Sense Resistor in MC33260
Like Circuits
current at the switching period level and then to integrate the
obtained result over the AC line sinusoid.
In this case, the current sense resistor Rs derives the whole
coil current. Consequently, the product of Rs by the square
of the rms coil current gives the dissipation of the current
sense resistor:
As portrayed by Figure 4, the coil discharges during the
off time. More specifically, the current decays linearly
through the diode from its peak value (Icoil_pk) down to
zero that is reached at the end of the off−time. Taking the
beginning of the off−time as the time origin, one can then
write:
2
(eq. 48)
t pRs u
+ Rs * (Icoil(rms) )
260
where Icoil(rms) is the coil rms current that as expressed by
toff−t
(eq. 55)
Icoil(t) + Icoil_pk *
2
t Pin u
equation (26), equals: Icoil(rms) +
*
.
toff
Similarly to the calculation done to compute the coil rms
current, one can calculate the “diode rms current over one
switching period”:
Ǹ
Vac
3
Consequently:
2
4 * Rs
3
t Pin u
* ǒ
Ǔ
(eq. 49)
t pRs u
+
260
Vac
toff
2
toff−t
toff
1
T
ŕ
2
(eq. 56)
ƪ
ƫ
Id(rms)
+
*
Icoil_pk *
* dt
T
Comparison of the Losses Amount in the Two Cases
0
Let’s calculate the ratios: t pRs u
ń t pRs u
262
.
260
Solving the integral, one obtains the expression of the
“rms diode current over one switching period”:
One obtains:
(eq. 50)
toff
(eq. 57)
+ Ǹ
Ǹ
8 * 2 * Vac
Id(rms)
* Icoil_pk
T
+ 1 * ǒ Ǔ
t pRs u
ń t pRs u
262
3 * T
260
3p * Vout
Substitution of equation (15) that expresses Icoil_pk, into
the precedent equation leads to:
If one considers that (8/3 p) approximately equals 0.85,
the precedent equation simplifies:
toff
T
2
3
t Pin u
(eq. 58)
* sin(wt)
* Ǹ
+ 2 * Ǹ
0.85 * Vm
Id(rms)
*
T
(eq. 51)
t pRs u
ń t pRs u
[ 1 *
260
Vac
262
In addition, one can easily show that toff and T are linked
by the following equation:
where Vm is the AC line amplitude.
Average and RMS Current through the Diode
The diode average current can be easily computed if one
notes that it is the sum of the load and output capacitor
currents:
Ǹ
2 * Vac * sin(wt)
Vin
Vout
(eq. 59)
toff + T *
+ T *
Vout
Consequently, equation (58) can be changed into:
2 * Ǹ2 * 2
Ǹ
3
Id + I
) I
Cout
(eq. 52)
t Pin u
*
load
(eq. 60)
Ǹ
* ǒ sin(wt)Ǔ
Id(rms)
+
T
Ǹ
Ǹ
Vac * Vout
3
Then, in average:
This equation gives the equivalent rms current of the
(eq. 53)
diode over one switching period, that is, at a given V . As
t Id u+t I
) I
u+t I
load
u )t I
Cout
u
in
load
Cout
already stated in the Coil Peak and RMS Currents section,
the square of this expression must be integrated over a
rectified sinusoid period to obtain the square of the diode
rms current.
At the equilibrium, the average current of the output
capacitor must be 0 (otherwise the capacitor voltage will be
infinite). Thus:
Pout
Vout
(eq. 54)
t Id u+t I
load
u+
Therefore:
(eq. 61)
The rms diode current is more difficult to calculate.
Similarly to the computation of the rms coil current for
instance, it is necessary to first compute the squared rms
2
Taŕcń2
3
* sin (wt) * dt
Ǹ
2
8 * 2
2
Tac
t Pin u
Id(rms)
+
*
*
3
Vac * Vout
0
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AND8123/D
3
Similarly to the Power MOSFET Conduction Losses section, the integration of (sin (wt)) requires some preliminary
trigonometric manipulations:
1 * cos(2wt)
1
1
2
3
2
sin (wt) + sin(wt) * sin (wt) + sin(wt) * ǒ
Ǔ+ 2
* sin(wt) * * sin(wt) * cos(2wt)
2
And :
1
sin(wt) * cos(2wt) + * (sin(−wt) ) sin(4wt) )
2
Then :
3
4
1
4
3
sin (wt) + * sin(wt) * * sin(3wt)
Consequently, equation (61) can change into:
2
Taŕcń2
Ǹ
2
3 * sin(wt) sin(3wt)
8 * 2
2
Tac
Pin
Vac * Vout
(eq. 62)
* ƪ
ƫ* dt
Id(rms)
+
*
*
*
3
4
4
0
One can now solve the integral and write:
Ǹ
3 * (cos(w0) * cos(wTacń2) ) cos(3wTacń2) * cos(3w0)
2
16 * 2
t Pin u
2
(eq. 63)
(eq. 64)
* ǒ
Ǔ
Id(rms)
+
*
)
4w
12w
3 * Tac Vac * Vout
As (ù * Tac + 2p), we have:
Ǹ
2
3 * (1−cos(p) )
cos(p)−1
12w * Tac
16 * 2
Pin
Vac * Vout
2
* ǒ
Ǔ
Id(rms)
+
*
)
3
4w * Tac
One can simplify the equation replacing the cosine
elements by their value:
Thus:
(eq. 71)
Tacń2
Ǹ
4
Tac
2
ŕ
2
2
2
16 * 2
3
6
t Pin u
1
I1 * I2 * dt
Ic(rms) + I1(rms) ) I2(rms) *
*
(eq. 65)
2
* ǒ
Ǔ
Id(rms)
+
*
*
Vac * Vout 8 * p 12 * p
0
The square of the diode rms current simplifies as follows:
PFC Stage
Ǹ
2
32 * 2
t Pin u
(eq. 66)
(eq. 67)
V
2
out
Id(rms)
+
*
9 * p Vac * Vout
L
D
V
in
Finally, the diode rms current is given by:
I1
I2
Ǹ2 * 2
Ǹ
4
3
t Pin u
*
Ic
Id(rms) +
*
p
Load
Ǹ
Vac * Vout
DRV
Power
Switch
Output Capacitor RMS Current
As shown by Figure 11, the capacitor current results from
the difference between the diode current (I1) and the current
absorbed by the load (I2):
Figure 11. Output Capacitor Current
Ic(t) + I1(t) * I2(t)
(eq. 68)
2
One knows the first term (I1(rms) ). This is the diode rms
current calculated in the previous section. The second and
third terms are dependent of the load. One cannot compute
them without knowing the characteristic of this load.
Thus, the capacitor rms current over the rectified AC line
period, is the rms value of the difference between I1 and I2
during this period. As a consequence:
2
Anyway, the second term (I2(rms) ) is generally easy to
Tacń2
2
Tac
calculate once the load is known. Typically, this is the rms
current absorbed by a downstream converter. On the other
hand, the third term is more difficult to determine as it
depends on the relative occurrence of the I1 and I2 currents.
As the PFC stage and the load (generally a switching mode
power supply) are not synchronized, this term even seems
impossible to predict. One can simply note that this term
tends to decrease the capacitor rms current and
consequently, one can deduct that:
ŕ
2
2
(eq. 69)
Ic(rms)
+
*
(I1 * I2) * dt
0
2
Rearranging (I1−I2) leads to:
(eq. 70)
Tacń2
2
Tac
ŕ
2
2
2
Ic(rms)
+
*
[I1 ) I2 * (2 * I1 * I2)] * dt
0
Ǹ
(eq. 72)
Ic(rms) v
2
2
I1(rms) ) I2(rms)
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AND8123/D
Substitution of equation (67) that gives the diode rms
current into the precedent equation leads to:
where I2(rms) is the load rms current.
Ǹ
2
32 * 2 *t Pin u
(eq. 73)
Ic(rms) v Ǹ
2
) I2(rms)
9 * p * Vac * Vout
If the load is resistive, I2 = Vout/R where R is the load resistance and equation (71) changes into:
Tacń2
2
Vout
R
Vout
R
4
Tac
ŕ
2
2
+ ń1(rms) ) ǒ Ǔ
(eq. 74)
Ic(rms)
*
*
ń1 *
* dt
0
Thus, the capacitor squared rms current is:
2
Vout
2 * Vout
R
2
2
+ Id(rms) ) ǒ Ǔ
(eq. 75)
(eq. 76)
Ic(rms)
*t Id u
R
Ǹ
2
2
32 * 2
Vout
R
2 * Vout Pout
t Pin u
2
) ǒ Ǔ ǒ
Ǔ
Ic(rms)
+
*
*
*
9 * p Vac * Vout
R
Vout
As Pout = Vout2/R, the precedent equation simplifies as follows:
Ǹ
2
2
32 * 2
Vout
R
t Pin u
* ǒ Ǔ
(eq. 77)
ƪ
Ǹ
ƫ
Ic(rms) +
*
9 * p Vac * Vout
You may find a more friendly expression in the literature:
This explanation assumes that the energy that is fed by the
PFC stage perfectly matches the energy drawn by the load
over each switching period so that one can consider that the
capacitive part of the bulk has a constant voltage and that
only the ESR creates some ripple.
In fact, there is an additional low frequency ripple which
is inherent to the Power Factor Correction. The input current
and voltage being sinusoidal, the power fed by the PFC stage
has a squared sinusoid shape. On the other hand, the load
generally draws a constant power. As a consequence, the
PFC pre−converter delivers an amount of power that
matches the load demand in average only. The output
capacitor compensates the lack (excess) of input power by
supplying (storing) the part of energy necessary for the
instantaneous matching. Figures 13 and 14 sketch this
behavior.
I2
Ic(rms) +
, where I2 is the load current. This equation is
Ǹ
2
an approximate formula that does not take into account the
switching frequency ripple of the diode current. Only the
low frequency current that generates the low frequency
ripple of the bulk capacitor (refer to the next section) is
considered (this expression can easily be found by using
equation (88) and computing Ibulk + Cbulk * dVoutńdt ).
Equation (77) takes into account both high and low
frequency ripples.
Output Voltage Ripple
The output voltage (or bulk capacitor voltage) exhibits
two ripples.
The first one is traditional to Switch Mode Power
Supplies. This ripple results from the way the output is fed
by current pulses at the switching frequency pace. As bulk
capacitors exhibit a parasitic series resistor (ESR – refer to
Figure 12), they cannot fully filter this pulsed energy source.
More specifically:
PFC Stage
Id
I2
V
in
Load
Ic
• During the on−time, the PFC MOSFET conducts and
no energy is provided to the output. The bulk capacitor
feeds the load with the current it needs. The current
together with the ESR resistor of the bulk capacitor
form a negative voltage –(ESR*I2), where I2 is the
instantaneous load current,
Driver
ESR
Bulk
Capacitor
• During the off−time, the diode derives the coil current
towards the output and the current across the ESR
becomes ESR*(Id−I2), where Id is the instantaneous
diode current.
Figure 12. ESR of the Output Capacitor
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400 V
Vout (5 V/div)
Load Power (100 W)
h*Pin (40 W/div)
Vin (100 V/div)
0 V
Figure 13. Output Voltage Ripple
The dashed black line represents the power that is absorbed by the load. The PFC stage delivers a power that has a squared
sinusoid shape. As long as this power is lower than the load demand, the bulk capacitor compensates by supplying part of the
energy it stores. Consequently the output voltage decreases. When the power fed by the PFC pre−converter exceeds the load
consumption, the bulk capacitor recharges. The peak of the PFC power is twice the load demand.
Vout (5 V/div)
400 V
Ic (200 mA/div)
0 A
Vin (100 V/div)
0 V
Figure 14. Output Voltage Ripple
The output voltage equals its average value when the input voltage is minimum and maximum. The output voltage is lower than
its average value during the rising phase of the input voltage and higher during the input voltage decay. Similarly to the input
power and voltage, the frequency of the capacitor current (represented in the case of a resistive load) is twice the AC line one.
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In this calculation, one does not consider the switching
The instantaneous input power (averaged over the
switching period) is the product of the input voltage
ripple that is generally small compared to the low frequency
ripple. In addition, the switching ripple depends on the load
current shape that cannot be predicted in a general manner.
As already discussed, the average coil current over a
switching period is:
Ǹ
( 2 * Vac * sin(ùt) ) by Iin. Consequently:
2
(eq. 79)
Pin + 2 *t Pin u * sin (wt)
In average over the switching period, the bulk capacitor
receives a charge current (h * PinńVout), where h is the PFC
stage efficiency, and supplies the averaged load current
t I2 u+ h *t Pin u ń Vout. Applying the famous
“capacitor formula” I + C * dVńdt, it becomes:
Ǹ
2 *t Pin u
(eq. 78)
lin +
* sin(wt)
Vac
dVout
dt
Pin
Vout
(eq. 80)
h *
*t I2 u+ Cbulk *
Substitution of equation (79) into equation (80) leads to:
2
2 * h *t Pin u * sin (wt) h *t Pin u
dVout
dt
1
(eq. 81)
* ǒ
Ǔ
+
*
Cbulk
Vout
Vout
Rearranging the terms of this equation, one can obtain:
2
h *t Pin u * sin(2wt)
Vout
(eq. 84)
(eq. 85)
ǒt Vout u
Ǔ
+ 1 *
2
Cbulk * w *t Vout u
h *t Pin u
dVout
dt
(eq. 82)
2
ƪ
ƫ
Vout *
+
* 2 * sin (wt) * 1
Cbulk
Thus:
2
d(Vout )
dVout
dt
Noting that
+ 2 * Vout *
and that
dt
2
h *t Pin u * sin(2wt)
t Vout u ) dVout
t Vout u
+ Ǹ1 *
cos(2wt) + 1−2 * sin (wt), one can deduct the square of the
2
Cbulk * w *t Vout u
output voltage from the precedent equation:
Where dV is the instantaneous output voltage ripple.
Equation (85) can be rearranged as follows:
out
−h *t Pin u
Cbulk * w
(eq. 83)
2
2
Vout *t Vout u
+
* sin(2wt)
(eq. 86)
where <V > is the average output voltage.
out
h *t Pin u * sin(2wt)
Dividing the terms of the precedent equations by the
square of the average output voltage, it becomes:
Ǹ1 *
dVout +t Vout u*ǒ
* 1
Ǔ
2
Cbulk * w *t Vout u
One can simplify this equation considering that the output voltage ripple is small compared to the average output voltage
h *t Pin u * sin(2wt)
Ǹ1 *
(fortunately, it is generally true). This leads to say that the term
ǒ
* 1
Ǔ
is nearly zero or in other
2
Cbulk * w *t Vout u
h *t Pin u * sin(2wt)
words, that ǒ
Ǔis small compared to 1. Thus, one can write that:
2
Cbulk * w *t Vout u
h *t Pin u * sin(2wt)
h t Pin u * sin(2wt)
1
2
(eq. 87)
Ǹ1 *
[ 1 *
*
2
2
Cbulk * w *t Vout u
Cbulk * w *t Vout u
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Conclusion
Substitution of equation (86) into equation (87), leads to
the simplified ripple expression that one can generally find
in the literature:
Compared to traditional switch mode power supplies, one
faces an additional difficulty when trying to predict the
currents and voltages within a PFC stage: the sinusoid
modulation. This is particularly true in critical conduction
mode where the switching ripple cannot be neglected. As
proposed in this paper, one can overcome this difficulty by:
−h *t Pin u * sin(2wt)
2 * Cbulk * w *t Vout u
(eq. 88)
dVout +
The maximum ripple is obtained when (sin(2ùt) + −1)
and minimum when (sin(2wt) + 1). Thus, the peak−to−peak
ripple that is the difference of these two values is:
• First calculating their value within a switching period,
• Then the switching period being considered as very
small compared to the AC line cycle, integrating the
result over the sinusoid period.
h *t Pin u
Cbulk * w *t Vout u
(eq. 89)
(dVout)pk−pk +
And:
The proposed theoretical analysis helps predict the stress
faced by the main elements of the PFC stages: coil,
MOSFET, diode and bulk capacitor, with the goal of easing
the selection of the power components and therefore, the
PFC implementation. Nevertheless, as always, it cannot
replace the bench work and the reliability tests necessary to
ensure the application proper operation.
(dVout)pk−pk
(eq. 90)
Vout +t Vout u *
* sin(2wt)
2
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Peak Coil Current:
Switching Frequency:
Ǹ
t Pin u
Ǹ
2
2 * Vac * sin(wt)
Icoil_pk + 2 * 2 *
* sin(wt)
Vac
f +
ǒ
1 *
Ǔ
Vac
2 * L *t Pin u
Vout
Maximum Peak Current:
t Pin u max
Ǹ
Switching Losses:
Icoil_max + 2 * 2 *
VacLL
2
2 * (dt ) t ) * Vac
FR
Vout
p
4
* ǒ
Ǔ
t psw u[
*
RMS Coil Current:
Ǹ
p * L
2 * Vac
2
t Pin u
*
Icoil(rms) +
Ǹ
Vac
Conduction Losses:
4
3
Ǹ
2
8 * 2 * Vac
1 * ǒ Ǔ
ƪ
3p * Vout
t Pin u
Vac
* Ron * ǒ
Ǔ
t Pon u+
*
ƫ
3
Average Diode Current:
Pout
Vout
t Id u+t I
load
u+
RMS Diode Current:
Ǹ
p
2 * 2
4
3
t Pin u
*
* Ǹ
Id(rms) +
Ǹ
Vac * Vout
I
load
L1
D6
V
out
+
C1
CONTROLLER
M1
AC Line
LOAD
R7
R5
Capacitor Low Frequency Ripple:
h *t Pin u
(dVout)pk−pk +
MC33260 like Current Sense Resistor (Rs = R5)
Cbulk * w *t Vout u
Dissipation:
2
RMS Capacitor Current:
4 * Rs
3
t Pin u
* ǒ
Ǔ
t pRs u
+
260
Vac
Ǹ
2
32 * 2 *t Pin u
Ic(rms) v Ǹ
ƪ
ƫ 2
)
I
(rms)
Vout
load
9 * p * Vac * Vout
MC33262 like Current Sense Resistor (Rs = R7)
If load is resistive:
Dissipation:
Ǹ
2
Ǹ
2
8 * 2 * Vac
1 * ǒ Ǔ
ƪ
3p * Vout
4
3
t Pin u
2
32 * 2
t Pin u
*
* Rs * ǒ
Ǔ
t pRs u
+
*
ƫ
* ǒ Ǔ
262
ƪ
Ǹ
ƫ
Ic(rms) +
Vac
9 * p Vac * Vout
R
Vac: AC line rms voltage
VacLL: Vac lowest level
w: AC line angular frequency
<Pin>: Average input power
<Pin>max: Maximum pin level
Vout: Output voltage
Pout: Output power
Iload: Load current
Iload(rms): RMS load current
h: Efficiency
Ron: MOSFET on resistance
dt, t : Switching times (see Switching
FR
Losses section and Figure 10)
Cbulk = C1: Bulk capacitor value
Rs: Current sense resistance
L: Coil inductance
Figure 15. Summary
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Notes
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Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
AND8123/D
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