MC33395 [MOTOROLA]
Three-Phase Gate Driver IC; 三相栅极驱动器IC
| 型号： | MC33395 |
| 厂家： | 
MOTOROLA |
| 描述： | Three-Phase Gate Driver IC |
| 文件： | 总16页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33395/D
Rev 2.0, 01/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33395
33395T
Three-Phase Gate Driver IC
The 33395 simplifies the design of high-power BLDC motor control design by
combining the gate drive, charge pump, current sense, and protection circuitry
necessary to drive a three-phase bridge configuration of six N-channel power
MOSFETs. Mode logic is incorporated to route a pulse width modulation (PWM)
signal to either the low-side MOSFETs or high-side MOSFETs of the bridge, or
to provide complementary PWM outputs to both the low- and high-sides of the
bridge.
THREE-PHASE
GATE DRIVER IC
Detection and drive circuitry are also incorporated to control a reverse battery
protection high-side MOSFET switch. PWM frequencies up to 28 kHz are
possible. Built-in protection circuitry prevents damage to the MOSFET bridge as
well as the drive IC and includes overvoltage shutdown, overtemperature
shutdown, overcurrent shutdown, and undervoltage shutdown.
The device is parametrically specified over an ambient temperature range of
-40°C ≤ TA ≤ 125°C and 5.5 V ≤ VIGN ≤ 24 V supply.
DWB SUFFIX
CASE 1324-02
Features
• Drives Six N-Channel Low RDS(ON) Power MOSFETs
32-TERMINAL SOICW
• Built-In Charge Pump Circuitry
• Built-In Current Sense Comparator and Output Drive Current Limiting
• Built-In PWM Mode Control Logic
ORDERING INFORMATION
Temperature
• Built-In Circuit Protection
Package
Device
Range (T )
A
• Designed for Fractional to Integral HP BLDC Motors
• 32-Terminal SOIC Wide Body Surface Mount Package
• 33395 Incorporates a <5.0 µs Shoot-Through Suppression Timer
• 33395T Incorporates a <1.0 µs Shoot-Through Suppression Timer
MC33395DWB/R2
MC33395TDWB/R2
-40°C to 125°C
32 SOICW
33395 Simplified Application Diagram
VPWR
33395
VIGNP
VGDH
VIGN
VDD
VDD
GDH1
GDH2
GDH3
SRC1
SRC2
SRC3
CP1H
CP1L
CP2H
CP2L
N
N
S
S
CRES
3
2
HSE1–3
GDL1
GDL2
MODE0–1
MCU
PWM
LSE1–3
AGND
3
GDL3
-ISENS
VDD
PGND
+ISENS
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
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VIGN
VDD
Osc.
CP1H
CP1L
CP2H
CP2L
Charge
Pump
Low
Overvoltage
Voltage
Shutdown
Reset
CPRES
+ISENS
-ISENS
+
-
DriveLimiting
L
H
MODE0
MODE1
VGDH
PWM
VIGNP
GDH1
HSE1
Control
HSE2
HSE3
LSE1
LSE2
LSE3
Logic
GDH2
GDH3
SRC1
SRC2
SRC3
Gate
Drive
Circuits
AGND
GDL1
GDL2
Overtemperature
TEST
Shutdown
GDL3
PGND
Figure 1. 33395 Simplified Internal Block Diagram
33395
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CP2H
CPRES
VIGN
1
2
3
4
5
6
7
8
CP2L
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CP1H
CP1L
VGDH
VIGNP
SRC1
GDH1
GDL1
SRC2
GDH2
GDL2
SRC3
GDH3
GDL3
PGND
TEST
LSE1
LSE2
LSE3
HSE1
HSE2
HSE3
MODE0
MODE1
PWM
VDD
9
10
11
12
13
14
15
16
AGND
+ISENS
-ISENS
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal Name
Formal Name
Charge Pump Cap
Charge Pump Reserve Cap Input from external reservoir capacitor for charge pump
Definition
1
CP2H
High potential terminal connection for secondary charge pump capacitor
2
CPRES
VIGN
3
Input Voltage
High-Side Gate Voltage
Input Voltage Protected
High-Side Sense
Gate Drive High
Output for Gate
High-Side Sense
Gate Drive High
Output for Gate
High-Side Sense
Gate Drive High
Gate Drive Low
Power Ground
Input from ignition level supply voltage for power functions
Output full-time gate drive for auxiliary high-side power MOSFET switch
Input from protected ignition level supply for power functions
Sense for high-side source voltage, phase 1
Output for gate high-side, phase 1
4
VGDH
5
VIGNP
SRC1
GDH1
GDL1
SRC2
GDH2
GDL2
SRC3
GDH3
GDL3
PGND
Test
6
7
8
Output for gate drive low-side, phase 1
Sense for high-side source voltage, phase 2
Output for gate high-side, phase 2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Output for gate drive low-side, phase 2
Sense for high-side source voltage, phase 3
Output for gate drive high-side, phase 3
Output for gate drive low-side, phase 3
Ground terminals for power functions
Test Terminal
This should be connected to ground or left open
Inverting input for current limit comparator
Non-inverting input for current limit comparator
Ground terminal for logic functions
-ISENS
+ISENS
AGND
VDD
IS Minus
IS Plus
Analog Ground
Logic Supply Voltage
Pulse Width Modulator
Mode Control Bit 1
Mode Control Bit 0
High-Side Enable
Supply voltage for logic functions
PWM
Input for pulse width modulated driver duty cycle
Input for mode control selection
MODE1
MODE0
HSE3
Input for mode control selection
Input for high-side enable logic, phase 3
33395
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal Name
Formal Name
Definition
Input for high-side enable logic, phase 2
25
HSE2
High-Side Enable
26
27
28
29
30
31
32
HSE1
LSE3
LSE2
LSE1
CP1L
CP1H
CP2L
High-Side Enable
Low-Side Enable
Input for high-side enable logic, phase 1
Input for low-side enable logic, phase 3
Low-Side Enable
Input for low-side enable logic, phase 2
Low-Side Enable
Input for low-side enable logic, phase 1
External Pump Capacitor
External Pump Capacitor
Charge Pump Capacitor
Input from external pump capacitor for charge pump and secondary terminals
Input from external pump capacitor for charge pump and secondary terminals
Input from external reservoir, external pump capacitors for charge pump, and
secondary terminals
33395
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted
Rating
Symbol
Value
Unit
V
IGN Supply Voltage
VIGN
-15.5 to 40
VDC
VIGNP Load Dump Survival
V
-0.3 to 65
-0.3 to 7.0
VDC
VDC
IGNP
VDD
LD
V
DD Logic Supply Voltage (Fail Safe)
Logic Input Voltage (LSEn, HSEn, PWM, and MODEn)
Start Up Current VIGNP
VIN
0.3 to 7.0
100
VDC
mA
IVIGNStartUp
ESD Voltage
V
Human Body Model (Note 1)
Machine Model (Note 2)
VESD1
VESD2
±500
±200
Storage Temperature
TSTG
TA
-65 to 160
-40 to 125
-40 to 125
150
°C
°C
°C
°C
W
Operating Ambient Temperature
Operating Case Temperature
Maximum Junction Temperature
TC
TJ
Power Dissipation (T = 25°C)
A
P
1.5
D
Terminal Soldering Temperature
Thermal Resistance, Junction-to-Ambient
Notes
T
240
65
°C
SOLDER
RθJA
°C/W
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
2. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect
approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
IIGN
–
–
0.2
–
1.0
100
36.5
mA
mA
V
VIGN Current @ 5.5 V–24 V, V
= 5.5 V
DD
IIGNP
VIGNP Current @ 5.5 V–24 V, V
= 5.5 V
DD
V
25
33
V
IGNP Overvoltage Shutdown
IGNP Voltage
IGNP
SD
VIGNP
I
5.5
–
–
24
V
V
V
1.8
4.0
mA
Current @ 5.5 VDC, 5.5 V ≤ VIGNP ≤ 24 V
DD
V
DD
V
2.5
7.0
3.2
–
4.0
–
V
V
V
V
Low-Voltage Reset Level
DD(RESET)
–
DD
DD
One-Time Fuse (Logic Supply)
INPUT/OUTPUT
IIN
µA
V
Input Current at VDD = 5.5 V
5.0
1.0
12
25
3.0
24
LSEn, HSEn, PWM, and MODEn = 3.0 V
VTH
Input Threshold at VDD = 5.5 V
2.0
LSEn, HSEn, PWM, and MODEn (Note 3)
V
V
V
Source Sense Voltage
SCRn
SCRn
-0.3
V
IGNP
14
SRC1, SRC2, SRC3
VINP(OFFSET)
VINP(BIAS)
IINP(OFFSET)
VCMR
5.0
-500
-300
0
20
500
mV
nA
nA
VDC
V
Comparator Input Offset Voltage
Comparator Input Bias Current
-170
-3.0
–
300
Comparator Input Offset Current
Common Mode Voltage (Note 4)
Comparator Differential Input Voltage (Note 4)
VDD-2.0
+VDD
VINPdiff
-VDD
–
V
CRES-VIGNP
V
Charge Pump Voltage VIGN (Note 5)
VIGNP = 5.5 V, ICRES = 1.0 mA
VIGNP = 9.0 V, ICRES = 1.0 mA
4.0
4.0
4.5
8.0
4.5
6.0
7.5
10
18
18
18
18
18
VIGNP = 12 V, I RES = 5.0 mA
C
VIGNP = 24 V, ICRES = 1.0 mA
VIGNP = 24 V, ICRES = 5.0 mA
16
12
VGDHn( )-VSRCn
on
V
V
V
GDH Output Voltage with GDHn in ON State
4.0
4.0
4.5
5.2
9.0
11
18
18
18
V
V
IGNP = 5.5 V, IGDH = 1.0 mA
n
IGNP = 12 V, IGDH = 5.0 mA
n
VIGNP = 24 V, IGDH = 5.0 mA
n
VGDHn(
VGDH Output Voltage with GDHn in OFF State
IGNP = SRCn = 14 V, IGDH = 1.0 mA
)
off
-1.0
0.6
1.0
V
n
Notes
3. Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 µA internal sinks.
4. Guaranteed by design and characterization. Not production tested.
5. The Charge Pump has a positive temperature coefficient. Therefore the Min’s occur at -40°C, Typ’s at 25°C, and Max’s at 125°C.
33395
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect
approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INPUT/OUTPUT (continued)
VGDL(
V
VGDL Low-Side Output Voltage GDHn in ON State
)
on
5.0
8.0
8.0
8.0
8.0
14
17
16
18
18
19
19
V
V
V
IGNP = 5.5 V, IGDL = 1.0 mA
n
IGNP = 12 V, IGDL = 5.0 mA
n
IGNP = 24 V, IGDL = 0.0 mA
n
VIGNP = 24 V, IGDL = 5.0 mA
n
VGDL(off)
V
VGDL Output Voltage GDHn in OFF State
-1.0
160
0.3
–
1.0
V
IGNP = 14 V, IGDL = 1.0 mA
n
TLIM
190
°C
Thermal Shutdown (Note 6)
Notes
6. Guaranteed by design and characterization. Not production tested.
33395
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions -40°C ≤ TA ≤ 125°C, 5.5 V ≤ VIGNP ≤ 24 V unless otherwise noted. Typical values reflect
approximate parameter mean at TA = 25°C under normal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time
(25% to 75%), CISS Value = 2000 pF (Note 7)
tRH
µs
–
0.35
1.5
High-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time
(75% to 25%), CISS Value = 2000 pF (Note 7)
tFH
µs
µs
–
0.25
1.5
Shoot-Through Suppression Time Delay (33395) (Note 7), (Note 8)
tD1, tD2
33395
33395T
1.0
0.2
3.0
0.65
5.5
1.0
Current Limit Time Delay (Note 9)
tILIMDELAY
1.5
2.8
5.0
µs
Notes
7. See Figure 2, page 9.
8. Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being on
simultaneously.
9. Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOW and
sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay.
33395
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Timing Diagram
100
75
25
0
tRH tFH
tD1
tFL
tD2
tRL
100
75
25
0
TIME
Figure 2. Shoot-Through Suppression
33395
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33395 and 33395T devices are designed to provide the
charge pump circuitry so that the MOSFET array may consist
entirely of N-Channel MOSFETs. It also contains feedback
sensing circuitry and control circuitry to provide a robust overall
motor control design.
necessary drive and control signal buffering and amplification to
enable a DSP or MCU to control a three-phase array of power
MOSFETs such as would be required to energize the windings
of powerful brushless DC (BLDC) motors. It contains built-in
FUNCTIONAL DESCRIPTION
By averaging these two values, the proper CP value can be
n
Gate Drive Circuits
The gate drive outputs (GDH1, GDH2, etc.) supply the peak
currents required to turn ON and hold ON the MOSFETs, as
well as turn OFF and hold OFF the MOSFETs.
determined:
0.15 µF
0.15 µF
= .015 µF, upper limit
= 0.075 µF, lower limit; and
20
10
Charge Pump
C
P1 and CP2 =(0.0075 µF + 0.015 µF) ÷ 2 = 0.01 µF
The current capability of the charge pump is sufficient to
supply the gate drive circuit’s demands when PWM’ing at up to
28 kHz. Two external charge pump capacitors and a reservoir
capacitor are required to complete the charge pump’s circuitry.
Thermal Shutdown Function
The device has internal temperature sensing circuitry which
activates a protective shutdown function should the die reach
excessively elevated temperatures. This function effectively
limits power dissipation and thus protects the device.
Charge reservoir capacitance is a function of the total
MOSFET gate charge (QG) gate drive voltage level relative to
the source (VGS) and the allowable sag of the drive level during
the turn-on interval (VSAG). CRES can be expressed by the
following formula:
Overvoltage Shutdown Function
When the supply voltage (VIGN) exceeds the specified over-
QG x VGS
2 x VGS x VSAG - VSAG
CRES
=
2
voltage shutdown level, the part will automatically shut down to
protect both internal circuits as well as the load. Operation will
resume upon return of VIGN to normal operating levels.
For example, for QG = 60 nC, VGS = 14 V, VSAG = 0.2 V:
(60 nC) x (14 V)
Low Voltage Reset Function
When the logic supply voltage (VDD) drops below the
CRES
=
= 0.15 µF
2 x (14 V) x (0.2 V) - (0.2)2
minimum voltage level or when the part is initially powered up,
this function will turn OFF and hold OFF the external MOSFETs
until the voltage increases above the minimum voltage level
required for normal operation.
Proper charge pump capacitance is required to maintain,
and provide for, adequate gate drive during high demand turn-
ON intervals. Use the following formula to determine values for
Control Logic
CP1 and CP2
:
The control logic block controls when the low-side and high-
side drivers are enabled. The logic implements the Truth Table
found in the specification and monitors the M0, M1, PWM, CL,
OT, OV, LSE, and HSE terminals. Note that the drivers are
enabled 3 µs after the PWM edge. During complimentary chop
mode the high-side and low-side drives are alternatively
enabled and disabled during the PWM cycle. To prevent shoot-
For example, for the above determination of CRES = 0.15 µF:
CRES
20
CRES
10
< CP1 = CP2
<
through current, the high-side drive turn-on is delayed by tD1
,
and the low-side drive turn on is delayed by tD2 (see Figure 2,
page 9).
33395
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Note that the drivers are disabled during an overtemperature
sense resistor placed in series with the ground return of the
three-phase output bridge. When triggered by the comparator,
the CL (current limit) bit of the internal error register is set, and
the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and
GDL2, GDH3 and GDL3), are controlled such that current will
cease flowing through the load (refer to Table 1, Truth Table,
page 12).
or overvoltage fault. A flip-flop keeps the drive off until the
following PWM cycle. This prevents erratic operation during
fault conditions. The current limit circuit also uses a flip-flop for
latching the drive off until the following PWM cycle.
Note PWM must be toggled after POR, Thermal Limit, or
overvoltage faults to re-enable the gate drivers.
Overtemperature and Overvoltage Shutdown
Circuits
V
GDH
The VGDH terminal is used to provide a gate drive signal to a
Internal monitoring is provided for both over temperature
conditions and over voltage conditions. When any of these
conditions presents itself to the IC, the corresponding internally
set bits of the error register are set, and the output gate drive
pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and
GDL3), are controlled such that current will cease flowing
through the load (refer to Table 1).
reverse battery protection MOSFET. If reverse battery
protection is desired, VIGN would be applied to the source of an
external MOSFET, and the drain of the MOSFET would then
deliver a "protected" supply voltage (VIGNP) to the three phase
array of external MOSFETs as well as the supply voltage to the
VIGNP terminal of the IC.
In a reverse polarity event (e.g., an erroneous installation of
the system battery), the VGDH signal will not be supplied to the
external protection MOSFET, and the MOSFET will remain off
and thus prevent reverse polarity from being applied to the load
and the VIGNP supply terminal of the IC.
LSE and HSE Input Circuits
The low-side enable input terminals (LSE1, LSE2, LSE3)
and high-side enable input terminals (HSE1, HSE2, HSE3) form
the input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and
LSE3) which set the logic states of the output gate drive pairs
(i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3) in
accordance with the logic set forth in the Truth Table (page 12).
Typically these inputs are supplied from an MCU or DSP to
provide the phasing of the currents applied to a brushless dc
motor's stator coils via the output MOSFET pairs.
High-Side Gate Drive Circuits
Outputs GDH1, GDH2, and GDH3 provide the elevated drive
voltage to the high-side external MOSFETs (HS1, HS2, and
HS3; see Figure 3, page 13). These gate drive outputs supply
the peak currents required to turn ON and hold ON the high-
side MOSFETs, as well as turn OFF the MOSFETs. These gate
drive circuits are powered from an internal charge pump, and
therefore compensate for voltage dropped across the load that
is reflected to the source-gate circuits of the high-side
MOSFETs.
PWM Input
The pulse width modulation input provides a single input
terminal to accomplish PWM modulation of the output pairs in
accordance with the states of the Mode 0 and Mode 1 inputs as
set forth in the Truth Table (page 12).
Low-Side Gate Drive Circuits
Mode Selection Inputs
Outputs GDL1, GDL2, and GDL3 provide the drive voltage to
the low-side external MOSFETs (LS1, LS2, and LS3; see
Figure 3). These gate drive outputs supply the peak currents
required to turn ON and hold ON the low-side MOSFETs, as
well as turn OFF the MOSFETs.
The mode selection inputs (Mode 0 and Mode 1) determine
the PWM implementation of the output pairs in accordance with
the logic set forth in the Truth Table (page 12). PWM'ing can
thus be set to occur either on the high-side MOSFETs or the
low-side MOSFETs, or can be set to occur on both the high-side
and low-side MOSFETs as "complementary chopping".
V
Fuse
DD
Test Terminal
The VDD supply of the 33395 IC has an internal fuse, which
will blow and set all outputs of the device to OFF, if the VDD
voltage exceeds that stated in the maximum rating section of
the data sheet. When this fuse blows, the device is permanently
disabled.
This terminal should be grounded or left floating (i.e., do not
connect it to the printed circuit board). It is used by the
automated test equipment to verify proper operation of the
internal overtemperature shut down circuitry. This terminal is
susceptible to latch-up and therefore may cause erroneous
operation or device failure if connected to external circuitry.
I
Inputs
SENS
The +I
and -I
terminals are inputs to the internal
sens
sens
current sense comparator. In a typical application, these would
receive a a low-pass filtered voltage derived from a current
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Table 1. Truth Table
The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn
(n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT),
overvoltage (OV), and current limit (CL) bits provided in this table.
NORMAL OPERATION
Input Pairs
Output Pairs
Switching Modes
Internally Set Bits
(e.g., LSE2 and HSE2)
(e.g., GDL2 and GDH2)
MODE1
MODE0
OT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSEn
HSEn
GDLn
0
GDHn
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PWM
0
0
0
0
0
0
1
PWM
PWM
0
0
0
0
0
PWM
1
0
0
0
0
PWM
1
0
PWM
0
0
0
FAULT MODE OPERATION
Input Pairs
Output Pairs
(e.g., GDL2 and GDH2)
Switching Modes
Internally Set Bits
(e.g., LSE2 and HSE2)
MODE1
MODE0
OT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
OV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
CL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
x
LSEn
HSEn
GDLn
GDHn
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
x
33395
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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12 V
+
+
-
HS1
HS2
HS3
CP
CP
V
CP
CP
CP
LSE1
LSE2
LSE3
2H
RES
IGN
2L
1H
1L
1
2
3
4
5
6
32
31
30
29
28
27
V
GDH
IGNP
V
SRC1
GDH1
HSE1
7
26
GDL1
HSE2
MCU
8
25
LS1
LS2
LS3
SRC2
GDH2
GDL2
SRC3
GDH3
GDL3
PGND
TEST
HSE3
9
24
23
22
21
20
19
18
17
MODE0
MODE1
PWM
10
11
12
13
14
15
16
5.0 V
+
V
DD
AGND
+I
-I
SENS
SENS
Figure 3. Typical Application Diagram
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PACKAGE DIMENSIONS
DWB SUFFIX
32-TERMINAL SOICW
PLASTIC PACKAGE
CASE 1324-02
ISSUE A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
10.3
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
7.6
7.4
C
B
2.65
2.35
5
9
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
30X
0.65
1
32
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSION AND ADJACENT
LEAD SHALL NOT LESS THAN 0.07 MM.
PIN 1 ID
4
11.1
10.9
C
L
9
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM
THE LEAD TIP.
B
B
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH,
TIE BAR BURRS, GATE BURRS AND INTER-LEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN
THE TOP AND BOTTOM OF THE PLASTIC BODY.
16
17
SEATING
PLANE
A
5.15
2X 16 TIPS
32X
0.10
A
0.3
A
B C
A
A
(0.29)
BASE METAL
0.25
0.19
(0.203)
R0.08 MIN
0.25
0
0.38
0.22
0.29
0.13
GAUGE PLANE
MIN
PLATING
6
M
M
0.13
C
A
B
8
0.9
0.5
SECTION A-A
8
0
RE
SECTION B-B
33395
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
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MOTOROLA ANALOG INTEGRATED CIFRCoUrITMDoErVeICEInDfAoTrAmation On This Product,
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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© Motorola, Inc. 2004
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