MC33411BFTA_技术文档

Order this document by MC33411A/D

900 MHz ANALOG

CORDLESS PHONE

BASEBAND

The MC33411 900 MHz Analog Cordless Phone Baseband system is

designed to fit the requirements of a 900 MHz analog cordless telephone

system. Included are three PLLs (Phase–Locked Loops). Two are intended

for use with external VCOs and 64/65 or 128/129 dual modulus prescalers,

and can control the transmit and receive (LO1) frequencies for 900 MHz

communication. The third PLL is configured as the 2nd local oscillator (LO2),

and is functional to 80 MHz. Also included are muting, audio gain adjust

(internal and external), low battery/carrier detect, and a wide range for the

PLL reference frequency. The power supply range is 2.7 to 5.5 V. ”A” version

devices have programmable MCU clock out and reference oscillator disable

functions, whereas these functions are always enabled for ”B” version

devices.

WITH COMPANDER

SEMICONDUCTOR

TECHNICAL DATA

• Complete Expander/Compressor for Superior Noise Rejection

• Two PLLs and a LO Suitable for a 900 MHz System

• Minimal External Components

48

1

FTA SUFFIX

PLASTIC PACKAGE

CASE 932

• Transmit Path Includes Adjustable Gain Amplifier, Filters, Mute,

Compressor with Bypass and Limiter

(LQFP–48)

• Receive Path Contains Data Slicer, Adjustable Gain Amplifier, Sidetone

Attenuator, Filters, Expander with Bypass, Mute, Volume Control and

Power Amplifier

ORDERING INFORMATION

Operating

• Dual A/Ds are Provided to Monitor RSSI and V

CC

Temperature

Device

Package

• Independent Power Amplifier with Differential Outputs and Mute

• Selectable Frequency for Switched Capacitor Filters, PLLs and the LO

• Reference Frequency Source can be a Crystal or System Clock

MC33411AFTA

MC33411BFTA

T

A

= –20 to 70°C

LQFP–48

• Serial µP Port to Control Gain, Mute, Frequency Selection, Phase

Detector Gain, Power Down Modes, Low Battery Detect and Others

• Power Supply Range: 2.7 to 5.5 V

• Power Down Modes for Power Conservation

Simplified Block Diagram

Data

Slicer

DS In

DS Out

V

CC

Dual

A/D

RSSI

Tx In

Amp/Mute

Compressor

Filter Gain Adj

Tx Out

Filter Sidetone Attn

Mute Expander

Power Amp

Audio In

MCU Clock

Clock

Enable

Data

Rx Out

MCU

Interface

Programmable

Counters

2nd

LO

PLL

#1

PLL

#2

Tank

LO2 Out

LPF+ VCO +

Prescaler

LPF+ VCO +

Prescaler

LPF

This device contains 11,108 active transistors.

Motorola, Inc. 1999

Rev 2

1

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 1. Test Circuit

V

CC

V

1.0 µ

CC

1.0 µ

0.1 µ

Tx Audio

1.0 µ

47.5 k

130

1.0 µ

4.99 k

0.47 µ

0.1 µ

4.7

VB

V

Rx

Out

CC

PAO+ PA

E In

E

E Out

33

PAI

32

Gnd PA PAO–

31 30

VAG

MCI

25

cap

36

35

34

29 28

27

26

47.5 k

Vol

Ctl

Rx Mute

AALPF

Expander

Mic Amp

Power Amp

1.0 k

Power

Amp Mute

RSSI In

1.0 µ

MCO

24

23

22

21

20

19

18

37

38

39

40

41

42

43

44

45

46

47

48

Exp PT

Comp PT VB

V

CC

V

CC

Rx Audio In

Audio

Attn

1.0 µ

ALC

10 µ

R Gain Adj

1.0 µ

0.1 µ

C In

x

LPF

DS In

Compressor

SPI

RSSI 6b A/D

Converter

SPI

V

CC

V

0.47 µ

CC

C

BG V

ref

Gnd Audio

LO2 Out

cap

Low Max

Gain

1.0 µ

49.9

V

6b A/D

Side Tone

Attn

CC

Converter

V

Audio

CC

C Out

Lim In

1.0 µ

V

CC

LO2 V

CC

1.0 µ

0.001 µ

Tx Gain Adj

Tx Out

DS Out

LO2+

1.0 µ

0.1 µ

Data Slicer

Tx Mute

Limiter

LPF

10 k

5.6 p

2nd LO

VCO

LO2 Ctl

LO2–

17

16

15

14

13

Inverter

F

Out

SPI

ref

14b Ctr

100 p

0.1 µ

5.62 k

LO2 Gnd

Divide

By 2

6b SCF

Clk Ctr

SCF Clk

F

In

ref

LO2PD

Gnd Digital

LO2 Phase

Detect

12b Ref Ctr

13b N

LO2 Gnd

7b A’

13b N’

7b A

MCU

Clk Ctr

MCU Clk Out

MCU

Interface

Mod Ctl

Rx Phase

Detect

Tx Phase

Detect

Mod Ctl

SPI

1

2

3

4

5

6

7

8

9

10

11

12

Data

FRx MC FRx

V

PLL

Rx PD PLL

Gnd

Tx PD PLL

FTx

FTx MC EN

CLK

V

CC

V

CC

1.0 µ

0.001 µ

0.01 µ

49.9

RF In

2

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

MAXIMUM RATINGS

Rating

Symbol

Value

–0.5 to 6.0

–6.5 to 150

150

Unit

V

Power Supply Voltage

Junction Temperature

V

CC

T

J

°C

Maximum Power Dissipation

P

D

mW

NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Recommended Operating

Conditions, Electrical Characteristics tables or Pin Descriptions section.

2. Meets Human Body Model (HBM) ≤2000 V and Machine Model (MM) ≤200 V. ESD data

available upon request.

RECOMMENDED OPERATING CONDITIONS

Characteristic

Symbol

Min

2.7

Typ

3.6

–

Max

5.5

70

Unit

Vdc

°C

V

Supply Voltage

V

CC

Operating Ambient Temperature

Input Voltage Low (Data, CLK, EN)

Input Voltage High (Data, CLK, EN)

T

A

–20

V

il

–

0.3

–

V

ih

Tx PLL

–

V

– 0.3

CC

Frequency Range (F

)

F

4.0

–

18.25

–

MHz

V

ref in

range

Bandgap Reference Voltage

V

B

–

1.5

DC ELECTRICAL CHARACTERISTICS (V

= 3.6 V, T = 25°C, unless otherwise noted.)

A

CC

Characteristic

Symbol

Min

Typ

Max

Unit

Static Current

Active Mode (R5/8 to 0 = 0; R6/7 = 0)

Receive Mode (R5/8, 7, 3, 2, 0 = 0; R6/7 = 0; R5/6,5,4,1 = 1)

Standby Mode (R5/0 = 0; R6/7 = 0; R5/8 to 1 = 1)

Inactive Mode, A only (R5/8 to 0 =1; R6/7 = 1)

Data Slicer Only

RSSI/Batt A/D Only

Tx Audio Only

Rx Audio Only

PA Only

ACT I

Rx I

CC

–

15

10

500

10

100

70

1.4

1.0

6.0

1.0

500

20

13

1500

15

–

mA

µA

CC

STD I

CC

INA I

DS I

AD I

µA

TxA I

RxA I

mA

µA

CC

PA I

2nd LO/F Only

2LO I

CC

ref

Rx PLL/F Only

ref

RxPLL I

TxPLL I

ROSC I

CC

Tx PLL/F Only

ref

Ref Osc Only, ”A” version only

Reference Voltage, Unadjusted

V

B

1.38

1.5

1.62

V

ELECTRICAL CHARACTERISTICS (V

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

CC

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Rx AUDIO PATH

Symbol

Min

Typ

Max

Unit

Absolute Gain (V = –20 dBV)

in

Rx Audio In

E In

E Out

G

–4.0

0

4.0

dB

Gain Tracking (Referenced to E

for

G

t

out

V

in

= –20 dBV)

V

= –30 dBV

= –40 dBV

–21

–42

–20

–40

–19

–38

in

Total Harmonic Distortion (V = –20 dBV)

in

Rx Audio In

E In

PAO–

E Out

THD

–

0.7

–11.5

0

1.0

–

%

Maximum Input Voltage (V

CC

= 2.7 V)

dBV

Maximum Output Voltage (Increase input voltage

until output voltage THD = 5%, then measure

output voltage)

V

Omax

–2.0

–

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

3

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

ELECTRICAL CHARACTERISTICS (continued) (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Symbol

Min

Typ

Max

Unit

Rx AUDIO PATH (continued)

Input Impedance

Z

in

kΩ

RxAudio In

E In

–

600

7.5

–

Attack Time E

cap

= 0.5 µF, R = 40 k

filt

E In

MCI

E Out

t

–

3.0

13.5

–90

–

mS

dB

a

Release Time E

cap

= 0.5 µF, R = 40 k

filt

t

r

Compressor to Expander Crosstalk (V = –10 dBV,

in

C

–60

T

V

E In

= AC Gnd)

Rx Muting (V = –20 dBV, Rx Gain Adj = 01111)

Rx Audio In

E Out

M

–

–84

3.8

–60

4.0

dB

in

e

Rx High Frequency Corner (V = –20 dBV) SCF

Rx Out

Rx f

ch

3.6

kHz

in

Counter = 31

d

Low Pass Filter Passband Ripple (V = –20 dBV)

in

Rx Audio In

Rx Out

Ripple

–

0.4

–9.0 to 10

20

0.6

–

dB

Rx Gain Adjust Range

Rx Range

Rx n

Rx Gain Adjust Steps

–

Audio Path Noise, C–Message Weighting

EN

dBV

(V = AC Gnd)

in

Rx Out

E Out

PA Out

–

–85

<–95

–

Volume Control Adjust Range

Volume Control Levels

Rx Audio In

E In

E Out

Rx Out

E Out

V

–

–14 to 16

–

dB

CtlRange

V

cn

16

4

Side Tone Attenuate Selections

Rx Audio In

STA

n

Side Tone Attenuate (Referenced to E In)

Selection = 00

Selection = 01

Selection = 10

Selection = 11

STA

–

0.0

1.5

3.0

5.2

–

Side Tone Attenuate Threshold (C Out/E In)

STA

–

–3.0

–

dB

thr

POWER AMP/MUTE (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, f = 1.0 kHz)

B

A

in

Output Swing, ±5.0 mA load

(V @ –5.0 mA – V

PAI

PAO+

V

1.3

2.4

–

V

Omax

pp

@ 5.0 mA)

PAO+

Output Swing, ±5.0 mA load

(V @ –5.0 mA – V

PAI

PAO–

V

Omax

pp

@ 5.0 mA)

PAO–

Output Swing, No Load

Maximum Output Current

PAI

PAO+

PAO–

V

–

2.7

–

V

Omax

pp

PAO–,

PAO+

I

±5.0

mA

Power Amp Mute (V = –20 dBV, RL = 130 Ω)

in

PAI

PAO–

M

sp

–

–92

–60

dB

MIC AMP (V

CC

= 3.6 V, T = 25°C, Active Mode, f = 1.0 kHz)

in

A

Open Loop Gain

MCI

MCO

AVOL

GBW

–

100.000

100

–

V/V

kHz

Gain Bandwidth

Maximum Output Swing (RL = 10 kΩ)

V

Omax

3.2

V

pp

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

4

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

ELECTRICAL CHARACTERISTICS (continued) (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Symbol

Min

Typ

Max

Unit

Tx AUDIO PATH (V

= 3.6 V, Limiter, Mutes, ALC disabled, T = 25°C, Gain = 1, Active Mode, f = 1.0 kHz)

CC

A

in

Absolute Gain (V = –10 dBV)

in

MCI

TX Out

Tx Out

G

–4.0

0

4.0

dB

Gain Tracking (Referenced to Tx Out for

G

t

V

in

= –10 dBV)

V

= –30 dBV

= –40 dBV

–11

–17

–10

–15

–9.0

–13

in

Total Harmonic Distortion (V = –10 dBV)

in

MCI

Tx Out

THD

–

0.5

1.2

–

%

Maximum Output Voltage (Increase input voltage

until output voltage THD = 5%, then measure

output voltage. Tx Gain Adj = 8.0 dB)

V

Omax

–8.0

–5.0

dBV

Input Impedance

C In

Z

–

10

3.0

–

kΩ

mS

dB

in

Attack Time C

cap

= 0.5 µF, R = 40 k

filt

C In

E In

Tx Out

t

a

Release Time C

cap

= 0.5 µF, R = 40 k

filt

t

13.5

–60

–

r

Expander to Compressor Crosstalk (V = –20 dBV,

in

PA no load, VC = AC Gnd)

in

C

–40

T

Tx Muting (V = –10 dBV)

in

MCI

Tx Out

M

–

–88

–60

dB

c

ALC Output Level (When Enabled)

ALC

out

dBV

V

in

V

in

= –10 dBV

= –2.5 dBV

–15

–13

–11

–8.0

–6.0

ALC Slope (When Enabled)

MCI

C In

Tx Out

Slope

DR

0.1

0.25

0.4

dB/dB

V

in

V

in

= –10 dBV

= –2.5 dBV

ALC Input Dynamic Range

Tx Out

–

–16 to

–2.5

–

dBV

kHz

Limiter Output Level (When Enabled, V = –2.5

in

dBV)

Lim In

V

lim

–10

3.45

–7.0

Tx High Frequency Corner (V = –10 dBV,

in

Unity Gain) SCF Counter = 31

Tx f

3.65

3.85

ch

d

Low Pass Filter Passband Ripple (V = –10 dBV)

in

Lim In

Tx Out

Ripple

–

0.4

1.0

–

dB

MCU Clock or SCF Spurs (V = –10 dBv, relative to

in

SCF or MCU Fundamental)

–25

dBc

Maximum Compressor Gain (V = –70 dBV)

in

R6/8 = 0

R6/8 = 1

MCI

Tx Out

AV

max

dB

–

21

12

–

Tx Gain Adjust Range

Tx Gain Adjust Steps

Lim In

Tx Out

Tx Range

Tx N

–

–9.0 to 10

20

–

DATA AMP COMPARATOR (V

= 3.6 V, V = 1.5 V, T = 25°C, Active or Receive Mode)

B A

CC

Hysteresis

DS In

DS Out

DS In

Hys

20

–

42

60

–

mV

V

Threshold Voltage

Input Impedance

Output Impedance

DS In

V

T

V

– 0.7

CC

250

100

Z

in

200

–

280

–

kΩ

V

DS Out

Z

out

Output High Voltage (V = V

in

– 1.0 V, I = 0 mA)

oh

DS In

V

oh

V

CC

V

Audio

–

CC

Audio

– 0.1

Output Low Voltage (V = V

in

– 0.4 V, I = 0 mA)

ol

DS In

DS Out

V

–

0.1

10

0.4

–

V

CC

ol

Maximum Frequency

F

max

kHz

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

5

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

ELECTRICAL CHARACTERISTICS (continued) (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Symbol

Min

Typ

Max

Unit

RSSI/LOW BATTERY A/D (V

= 3.6 V, V = 1.5 V, T = 25°C, Active or Receive Mode)

B A

CC

RSSI Voltage Range

RSSI In

SPI

RSSI

V

Range

Minimum (R5/17–12 = 0)

Interim (R5/17–12 = 100000)

Maximum (R5/17–12 = 1)

–

.744

–

0

–

1.6

–

.792

–

Low Battery Detect Operating Range

V

CC

Audio

SPI

LOWB

Range

V

Minimum

Interim (R5/23–18 = 101111)

Maximum (R5/23–18 = 1)

–

2.7

–

2.7

–

3.75

–

3.1

–

Differential Non–linearity

RSSI In/

Audio

SPI

A/D DNL

–1.0

±0.5

6

1.0

LSB

Bits

nA

V

CC

RSSI In/

Audio

Resolution

–

V

CC

Input Current

RSSI In

I

–80

20

80

in

ih

REFERENCE FREQUENCY (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode)

B A

Input Current High (V = V

in

)

F

I

2.0

–15

300

–

5.0

–5.0

–

15

–2.0

–

µA

CC

ref in

Input Current Low (V = 0 V)

in

F

I

il

Minimum Input Voltage F In

ref

F

ref in

F

V

in

mVpp

ref out

2.9 pF||11.6

Input Impedance

F

ref in

Z

in

–

kΩ

2.5 pF||4.5

Output Impedance

Z

out

–

ref out

kΩ

MICROPROCESSOR INTERFACE (V

= 3.6 V, V = 1.5 V, T = 25°C, Active or Receive Mode)

CC

B

A

Input Low Voltage

Data/EN

/CLK

V

0

–

0.3

V

il

Input High Voltage

Data/EN

/CLK

V

ih

Tx PLL

V

–

V

CC

0.3

Input Current Low (V = 0.3 V, Standby Mode)

in

Data, EN,

CLK

I

–5.0

–

0.4

1.6

1.0

–

µA

V

il

Data, EN, CLK

Input Current High (V = 3.3 V, Standby Mode)

in

Data, EN, CLK

Data, EN,

CLK

I

ih

5.0

–

Hysteresis Voltage Data, EN, CLK

Data, EN,

CLK

V

–

hys

Maximum Clock Frequency

CLK

F

2.0

–

MHz

pF

max

Input Capacitance Data, EN, CLK

Data, CLK,

EN

C

8.0

in

EN to CLK Setup Time

Data to CLK Setup Time

Hold Time

EN, CLK

Data, CLK

EN, CLK

t

–

200

100

90

–

nS

µS

V

suEC

t

–

suDC

t

h

–

Recovery Time

t

–

90

rec

Input Pulse Width

t

w

–

100

3.5

MCU Interface Power–Up Delay

t

puMCU

Output High Voltage (I = 0 mA)

oh

MCU Clk

Out

V

oh

Tx PLL

V

–

CC

0.3

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

6

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

ELECTRICAL CHARACTERISTICS (continued) (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Symbol

Min

Typ

Max

Unit

MICROPROCESSOR INTERFACE (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active or Receive Mode)

B A

Output Low Voltage (I = 0 mA)

ol

MCU Clk

Out

V

–

0.1

3.5

0.3

–

V

ol

Output High Voltage (I = 0 mA)

oh

Data

V

oh

Tx PLL

V

–

CC

0.3

Output Low Voltage (I = 0 mA)

ol

Data

V

ol

–

0.1

0.3

V

Rx/Tx PLL CHARACTERISTICS (V

= 3.6 V, V = 1.5 V, T = 25°C, Active or Receive Mode)

CC

B

A

Output Source Current (V

= 0.5 V or

I

oh

µA

PD

V

CC

– 0.5 V)

±100 µA mode

±400 µA mode

Rx PD &

Tx PD

–130

–520

–100

–400

–70

–280

Output Sink Current (V

±100 µA mode

±400 µA mode

= 0.5 V or V

– 0.5 V)

I

ol

µA

PD

CC

Rx PD &

Tx PD

70

280

100

400

130

520

Current Match, ±100 µA mode or ±400 µA mode,

= V / 2 (i.e., 100 x (ABS (I / I )))

Rx PD

Tx PD

Match

80

100

125

%

V

PD

CC

oh ol

/2),±100 µA mode

Output Off Current (V

= V

Rx PD

Tx PD

I

oz

–80

5.0

80

nA

PD

CC

or ±400 µA mode

Input Current Low (V = 0 V)

in

FRx FTx

FRxMC

I

–10

–

–7.5

10

–

14

–

µA

V

il

Input Current High (V = V

in

)

I

ih

CC

Input Bias Voltage

V

–

1.5

bias

Output Voltage High (I = 0 mA, Voltage Mode)

oh

V

oh

–

Rx PLL

–

V

– 0.1

CC

Output Voltage High (I = 0 mA, Voltage Mode)

oh

FTxMC

V

–

Tx PLL

–

V

oh

V

CC

– 0.1

Output Voltage Low (I = 0 mA, Voltage Mode)

ol

FRxMC

FTxMC

V

0.1

ol

Output Current High (V = 0.8 V, Current Mode)

oh

FRxMC

FTxMC

I

–130

70

–100

100

–

–70

130

–

µA

oh

Output Current Low (V = 0.8 V, Current Mode)

ol

FRxMC

FTxMC

I

µA

ol

Maximum Input Frequency

Input Voltage Swing

FRx

FTx

F

max

20

MHz

mVpp

nS

FRx

FTx

V

200

–

1200

–

in

Modulus Control Prop Delay

FRx

FTx

FRxMC

FTxMC

–

20

LO2 PLL CHARACTERISTICS (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode)

B

A

Output Source Current (V

= 0.5 V or

LO2PD

I

oh

µA

PD

V

CC

– 0.5 V)

±100 µA mode

±400 µA mode

–130

–520

–100

–400

–70

–280

Output Sink Current (V

±100 µA mode

±400 µA mode

= 0.5 V or V

– 0.5 V)

LO2PD

I

ol

µA

PD

CC

70

280

100

400

130

520

Current Match, ±100 µA mode or ±400 µA mode,

= V / 2 (i.e., 100 x (ABS (I / I )))

Match

80

100

125

%

V

PD

CC

oh ol

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

7

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

ELECTRICAL CHARACTERISTICS (continued) (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode, Rx Gain = 01111,

B

A

Vol Adj = 0111, f = 1.0 kHz, unless otherwise noted.)

in

Input

Measure

Characteristics

Symbol

Min

Typ

Max

Unit

LO2 PLL CHARACTERISTICS (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode)

B A

Output Off Current (V

PD

= V

/2)

LO2PD

LO2Ctl

I

–80

–1.0

–

5.0

–0.02

0.02

–

80

–

nA

µA

CC

oz

Input Current Low (V = 0.5 V)

in

I

il

Input Current High (V = V

in

– 0.5 V)

I

1.0

µA

CC

ih

Input Voltage Range

V

0.4

65

V

CC

V

range

Maximum 2nd LO Frequency

80

–

MHz

mVpp

LO2 Out Drive (25 Ω load)

V

112

180

245

out

COUNTERS (V

CC

= 3.6 V, V = 1.5 V, T = 25°C, Active Mode)

B A

12–Bit Reference Counter Range [Note 1]

–

3 to 4095

3 to 8191

–

13–Bit N Counter Range [Note 1]

7–Bit A Counter Range [Note 1]

64/65 Modulus Prescaler

128/129 Modulus Prescaler

–

0 to 63

0 to 127

–

14–Bit LO2 Counter Range [Note 1]

–

12 to

–

16383

6–Bit Counters (for SCF) [Note 1]

–

3 to 63

–

NOTES: 1. Values specified are pure numbers to the base 10.

2. Typical performance parameters indicate the potential of the device under ideal operating conditions.

PIN FUNCTION DESCRIPTION

Symbol/Type

Description

1

FRx MC

(Output)

Modulus Control Output for the Rx PLL section.

Can be set to output in current mode or voltage

mode, selectable with bit 3/16.

Rx PLL V

CC

100 µA

Current Mode

1

FRx MC

100 µA

Rx PLL V

CC

Voltage Mode

2

FRx

(Input)

Receives the signal from the external 64/65 or

128/129 prescaler. DC bias is at 1.3 V.

PLL

V

CC

2

200 k

Bias

FRx

80 µA

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

8

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

3

Rx PLL V

(Input)

Supply pin for the Rx PLL section. Allowable range

is 2.7 to 5.5 V and must be within 0.5 V of all other

CC

3

10

0.01

10

V

CC

pins. Good bypassing is required and isolation

V

CC

Rx PLL

Section

with a 10 Ω resistor is recommended.

4

Rx PD

(Output)

Rx Phase Detector Output. The output either

sources or sinks current, or neither, depending on

the phase difference of the phase detector input

signals. During lock, very narrow pulses with a

frequency equal to the PLL reference frequency are

present. Output current is either ±100 µA or

±400 µA, selectable with bit 2/20.

Rx

PLL

V

CC

100/

400 µA

125

4

to Filter

Rx PD

Rx PLL V

CC

100/

400 µA

5

6

7

PLL Gnd

Ground pin for the PLL section. A direct connection

to a ground plane is strongly recommended.

Tx PD

(Output)

Same as Pin 4, except powered from Tx PLL V

CC

.

Tx Phase Detector Output. Description same as for

Pin 4, except bit 1/20 controls the current level.

Tx PLL V

Supply pin for the Tx PLL section, MCU Serial

Interface, MCU Clock Counter, and the Reference

Oscillator. Allowable range is 2.7 to 5.5 V and must

CC

(Input)

7

10

0.01

10

V

CC

Tx PLL

Section,

MCU Serial

Interface,

Reference

Oscillator

be within 0.5 V of all other V

bypassing is required and isolation with a 10 Ω

pins. Good

CC

resistor is recommended.

8

9

FTx

(Input)

Same as Pin 2.

Receives the signal from the external 64/65 or

128/129 prescaler. DC bias is at 1.5 V.

FTx MC

(Output)

Modulus Control Output for the Tx PLL section. Can

be set to output in a current mode or a voltage

mode, selectable with bit 3/16.

Tx PLL V

CC

100 µA

Current Mode

9

FTx MC

Tx PLL V

CC

Voltage Mode

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

9

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

10

EN

Enable Input for the MCU Interface section.

Tx PLL

(Input)

V

Hysteresis threshold is within 0.5 V of ground and

CC

V

CC

pin.

. See text for proper waveform required at this

240

10

Enable

≈1.0 µA

11

12

CLK

(Input)

Same as Pin 10.

Clock Input for the MCU Interface section.

Hysteresis threshold is within 0.5 V of ground and

V

. Data is written or read out on clock’s rising

CC

edge. Maximum clock rate is 2.0 MHz.

Data

(I/O)

Data I/O line for the MCU Interface section. Both

address and data are provided to/from this pin.

Tx PLL

V

CC

Input threshold is within 0.5 V of ground and V

CC

Data is written or read out on clock’s rising edge.

.

240

12

Data

1.0 µA

Tx PLL

V

CC

Disable

Data

13

MCU Clk Out

(Output)

The microprocessor clock output is derived from the

reference oscillator and a programmable divider

with divide ratios of 2 to 312.5. It can be used to

drive a microprocessor and thereby reduce the

number of crystals required in the system design.

The driver has an internal resistor in series with the

output which can be combined with an external

capacitor to form a low–pass filter to reduce

radiated noise on the PCB. This output also

functions as the output for the counter test modes.

Tx PLL

V

CC

1.0 k

13

Clk Out

1) For the MC33411A the Clk Out can be disabled

via the MCU interface.

2) For the MC33411B this output is always active

(on).

14

Gnd Digital

Ground for the Data, MCU Clk Out, and F Out

ref

digital Outputs. A direct connection to the ground

plane is strongly recommended.

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

10

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

15, 16

F

In,

Out

Reference Frequency Input for various portions of

the circuit, including the PLLs, SCF clock, etc.

A crystal (4 to 18.25 MHz) may be connected as

shown, or an external frequency source may be

capacitor coupled to Pin 15. See text for crystal

requirements.

ref

F

ref

Tx PLL

V

CC

100

F

Out

ref

16

1) For the MC33411A the F Out can be disabled

ref

via the MCU interface.

2) For the MC33411B this output is always active

(on).

Tx PLL

V

CC

15

F

100

In

Disable

ref

17

DS Out

(Output)

Data Slicer Output (open collector with internal

100 kΩ pull–up resistor).

V

CC

Audio

100 k

17

DS Out

18

Tx Out

(Output)

Tx Out is the Tx path audio output. Internally this

pin has a low–pass filter circuitry with –3.0 dB

bandwidth of 4.0 kHz. Tx gain and mute are

programmable through the MCU interface. This pin

is sensitive to load capacitance.

V

Audio

CC

18, 20

Tx Out,

C Out

20

19

C Out

(Output)

C Out is the compressor output.

V

B

Lim In

(Input)

Lim In is the limiter input. This pin is internally

biased and has an input impedance of 400 kΩ.

Lim In must be ac–coupled.

V

Audio

CC

400 k

19

Lim In

V

B

21

C

is the compressor rectifier filter capacitor pin. It

cap

is recommended that an external filter capacitor to

audio be used. A practical capacitor range is

V

Audio

CC

Audio

CC

V

CC

0.1 to 1.0 µF. The recommended value is 0.47 µF.

40 k

21

C

cap

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

11

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

22

C In

(Input)

C In is the compressor input. This pin is internally

biased and has an input impedance of 12.5 kΩ.

C In must be ac–coupled.

V

CC

Audio

12.5 k

22

C In

V

B

23

24

V

Audio

Supply input for the audio section, filters, A/D

Converters, and Data Slicer. Allowable range is 2.7

to 5.5 V. Good bypassing is required.

CC

(Input)

23

10

0.01

V

CC

Audio

Section,

Filters, A/D

Converters,

Data Slicer

MCO

Output of the Microphone amplifier. Maximum

Audio

V

(Output)

output swing is ≈3.0 V for V

Maximum output current is >1.0 mA peak.

≥ 3.0 V.

CC

pp

CC

24

MCO

25

MCI

(Input)

Inverting input of the microphone amplifier. Gain

and frequency response are set with external

resistors and capacitors from this pin to the audio

source and to MCO.

V

Audio

CC

25

V

B

MCI

2.5 µA

Audio

26

27

28

VAG

(Output)

Analog ground for the audio section filters. VAG is

equal to VB and is buffered from VB. Maximum

current which can be sourced from this pin is

500 µA.

V

CC

26

0.1

µF

VAG

30 k

Audio

V

B

An internal 1.5 V reference for several sections.

This voltage is adjustable with bits 3/20–17.

Maximum source current is 100 µA. PSRR, noise

and crosstalk depends on the external capacitor.

V

CC

(Output)

240

27

4.7

µF

V

B

30 k

V

PA

CC

(Input)

Supply pin for the power amplifier outputs.

Allowable range is 2.7 to 5.5 V. Good bypassing is

required.

28

10

0.01

V

CC

Audio

Power

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

12

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

29

PAO+

(Output)

Output of the second power amplifier. This amplifier

is set for unity inverting gain and is driven by PAO–.

Audio

V

CC

Maximum swing is 2.9 V and maximum output

pp

current is >5.0 mA peak. DC level is ≈1.5 V.

29

PAO+

30

31

32

PAO–

(Output)

Same as Pin 29.

Output of the first power amplifier. Its gain is set

with external resistors and capacitors from this pin

to PAI. Output capability is the same as Pin 28.

Gnd PA

Ground pin for the power amplifier outputs. A direct

connection to a ground plane is strongly

recommended.

PAI

(Input)

Inverting input of the power amplifier. Gain and

frequency response are set with external resistors

and capacitors from this pin to the audio source and

to PAO–.

V

CC

Audio

32

V

B

PAI

2.5 µA

Audio

33

E Out

(Output)

Expander output. This output is sensitive to load

capacitance. Maximum output signal level is

V

CC

≈2.5 V . Maximum output current is >1.0 mA.

pp

33

Rx Audio

Output

V

B

34

E

cap

E

is the expander rectifier filter capacitor pin.

V

cap

Connect an external filter capacitor between V

CC

Audio

CC

Audio

CC

. The recommended capacitance

audio and E

range is 0.1 to 1.0 µF. The suggested value is

0.47 µF.

cap

40 k

34

E

cap

V

CC

35

E In

(Input)

The expander input pin is internally biased and has

input impedance of 30 kΩ.

Audio

30 k

35

E In

V

B

V

CC

36

Rx Out

(Output)

Rx Out is the Rx audio output. An internal low–pass

filter has a –3.0 dB bandwidth of 4.0 kHz.

Audio

36

Rx Out

V

B

NOTE: 1. All V

CC

pins must be within ±0.5 V of each other.

13

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

V

37

RSSI In

(Input)

Voltage input to RSSI A/D converter. Full scale is 0

to 1.6 V.

CC

Audio

37

RSSI In

38

Rx Audio In

(Input)

Input to the Rx Audio Path. Input impedance is

600 kΩ. Input signal must be capacitor coupled

V

CC

Audio

RC

Network

600 k

38

Rx Audio

In

V

B

V

Audio

39

DS In

(Input)

Input for the digital data from the RF Receiver

section. Input impedance is 250 kΩ. Hysteresis is

internally provided. Input signal level must be

between 50 and 700 mVpp.

CC

250 k

39

DS In

40

41

Gnd Audio

Ground pin for the audio section. A direct

connection to a ground plan is strongly

recommended.

LO2

LO2 Out

(Output)

Buffered output of the 2nd LO. This high frequency

output is a current, requiring an external pullup

resistor.

LO2

V

LO2

CC

V

CC

V

CC

50

41

LO2 Out

2.5 mA

42

LO2 V

CC

(Input)

Supply pin for the LO2 section. Allowable range is

2.7 to 5.5 V and must be within 0.5 V of all other

42

10

0.01

10

V

pins. Good bypassing is required and isolation

V

CC

with a 10 Ω resistor is recommended.

CC

LO2

Section

NOTE: 1. All V

pins must be within ±0.5 V of each other.

CC

14

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

PIN FUNCTION DESCRIPTION (continued)

Description

Symbol/Type

Description

43, 45

LO2+, LO2–

The 2nd LO. External tank components are

required. The internal capacitance across the pins

is adjustable from 0 to 7.6 pF for fine tuning

performance with bits 7/20–18.

LO2

V

CC

43

LO2+

44

LO2 Ctl

(Input)

LO2 Control is the dc control input for this VCO.

Typically it is the output of the low–pass filter fed

from the phase detector output.

45

LO2–

LO2

V

CC

44

55 k

LO2 Ctl

46

47

LO2 Gnd

Ground pin for the LO2 section. A direct connection

to a ground plane is strongly recommended.

LO2PD

(Output)

LO2 Phase Detector Output. The output either

sources or sinks current, or neither, depending on

the phase difference of the phase detector input

signals. During lock, very narrow pulses with a

frequency equal to the PLL reference frequency are

present. Output current is either ±100 µA or

±400 µA, selectable with bit 3/14.

LO2

PLL

V

CC

100/

400 µA

125

47 to Filter

LO2 PD

LO2 PLL V

CC

100/

400 µA

48

LO2 Gnd

Ground pin for the LO2 section. A direct connection

to a ground plane is strongly recommended.

NOTE: 1. All V

CC

pins must be within ±0.5 V of each other.

15

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

FUNCTIONAL DESCRIPTION

The following text, graphics, tables and schematics are

RSSI and low battery detect circuitry and serial interface for a

provided to the user as a source of valuable technical

information about the MC33411. This information originates

from thorough evaluation of the device performance. This

data was obtained by using units from typical wafer lots. It is

important to note that the forgoing data and information was

from a limited number of units. By no means is the user to

assume that the data following is a guaranteed parametric.

Only the minimum and maximum limits identified in the

electrical characteristics tables found earlier in the spec are

guaranteed.

Note: In the following descriptions, control bits in the MCU

Serial Interface for the various functions will be identified by

register number and bit number. For example, bit 3/19

indicates bit 19 of register 3. Bits 5/14–11 indicates register 5,

bits 14 through 11. Please refer to Figure 1.

microprocessor.

”A” versions of the device have the ability to disable either

the reference oscillator or MCU clock outputs. This feature is

useful for systems where the MCU has an internal clock,

allowing the user to place the MC33411 into Inactive (lowest

power consumption) mode. The ”A” version is also useful for

systems where the MCU has a dedicated clock source,

allowing for lower power consumption from the MC33411 by

disabling the MCU clock output.

”B” versions of the device are intended for systems where

the MCU clock will always be driven from the MC33411.

These bits are purposefully ”hard–wired” to the enable state

to ensure proper operation of the reference oscillator and

MCU clock output even during battery discharge/recharge

cycles.

All internal registers are completely static – no refreshing

is required under normal operation conditions.

General Circuit Description

The MC33411A/B is a low power baseband IC designed to

interface with the MC13145 UHF Wideband Receiver and

MC13146 Transmitter for applications up to 2.0 GHz. The

devices are primarily designated to be used for 900 MHz ISM

band in a CT–900, low power, dual conversion cordless

phone, but other applications such as data links with analog

processing could be developed. This device contains

complete baseband transmit and receive processing

sections, a transmit and receive PLL section, a

programmable PLL second local oscillator usable to 80 MHz,

DC Current

Figures 2 through 5 are the current consumption for

Inactive (MC33411 ”A” version only), Standby, Receive, and

Active modes versus supply voltages. Figures 6 and 7 show

the typical behavior of current consumption in relation to

temperature.

Figure 8 illustrates the effect of the MCU clock output

frequency to supply current during Active mode.

Figure 3. Supply Current versus

Figure 2. Supply Current versus

Supply Voltage (Standby Mode)

Supply Voltage (Inactive Mode)

6.0

1.8

T = 25°C

A

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.0

T = 25°C

A

5.0

4.0

3.0

2.0

1.0

0

MCU Clock Off

4.7 5.1

2.7

3.1

3.5

3.9

4.3

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

SUPPLY VOLTAGE (V)

16

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 4. Supply Current versus

Supply Voltage (Receive Mode)

Figure 5. Supply Current versus

Supply Voltage (Active Mode)

10

9.5

9.0

8.5

8.0

7.5

14

13

12

11

T = 25°C

A

T = 25°C

A

MCU Clock Out On

MCU Clock Out Off

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

SUPPLY VOLTAGE (V)

Figure 6. Supply Current versus Temperature

Figure 7. Supply Current versus Temperature

Normalized to 25°C (Standby Mode)

Normalized to 25°C (Receive & Active Mode)

740

720

700

680

660

640

620

600

20

19

18

17

16

15

14

13

12

11

10

Active

V

CC

= 3.6 V

V

CC

= 3.6 V

70

Receive

–5.0

–20

10

25

40

55

85

–20

0

25

70

85

DEGREES (°C)

Figure 8. Supply Current versus

MCU Clock Output Frequency (Active Mode)

12.5

12.3

12.1

11.9

11.7

11.5

V

= 3.6 V

CC

T = 25°C

A

30

1030

2030

3030

4030

5030

MCU CLK OUT (kHz)

17

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Table 1. Tx Gain Adjust Programming (Register 7)

Gain Control Gain Control

Gain Control

Bit #7

Gain Control

Bit #6

Gain Control

Bit #5

Gain

Ctl #

Gain/Attenuation

Amount

Bit #9

Bit #8

<6

6

–9.0 dB

–8.0 dB

–7.0 dB

–6.0 dB

–5.0 dB

–4.0 dB

–3.0 dB

–2.0 dB

–1.0 dB

0 dB

0

1

–

0

1

0

1

–

1

0

1

0

1

0

–

1

0

1

0

1

0

1

0

1

0

–

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

>25

1.0 dB

2.0 dB

3.0 dB

4.0 dB

5.0 dB

6.0 dB

7.0 dB

8.0 dB

9.0 dB

10 dB

Transmit Speech Processing System

frequency is dependent upon the SCF clock, nominaly set to

165 kHz and is directly proportional to the SCF clock. The

filter response for inband, ripple, wideband, as well as phase

and group delay, are shown in Figures 10 through 14.

The mute switch at Pin 18 will mute a minimum of 60 dB.

Bit 6/2 controls the mute. The limiter can be disabled by

programming a logic 1 into 6/5.

The compressor with ALC transfer characteristic is shown

in Figure 15. The ALC gain is controlled by bits 6/11–12. If

both bits are programmed to a logic 0, the ALC gain is set to

5.0 dB. If bit 6/11 is set to a logic 1, the ALC gain will be set to

10 dB, whereas if bit 6/12 is set to a logic 1 the ALC gain will be

25 dB. The ALC function may be disabled by programming a

logic 1 into bit 6/6.

The compressor low maximum gain can be set with bit 6/8.

Programming this bit to a logic 0 sets the maximum gain to

23 dB. A lower maximum gain, nominally 13.5 dB, is

achieved by programming the bit to a logic 1. The entire

compressor can be bypassed (i.e., 0 dB) by programming bit

6/4 to a logic 1.

This portion of the audio path goes from ”Tx Audio” to ”Tx

Out”. The gain of the microphone amplifier is set with external

resistors to receive the audio from the microphone hybrid or

any other audio source. The MCO output has rail–to–rail

capability. The ”Tx Audio” pin will be ac–coupled. The audio

transmit signal path includes automatic level control (ALC)

(also referred to as the Compressor), Tx mute, limiter, filters,

and Tx gain adjust. The ALC provides ”soft” limiting to the

output signal swing as the input voltage slowly increases.

With this technique the gain is slightly lowered to help reduce

distortion of the audio signal. The limiter section provides

hard limiting due to rapidly changing singal levels, or

transients. The ALC, TX mute, and limiter functions can be

enabled or disabled vis the MCU serial interface. The Tx gain

adjust can also be remotely controlled to set different desired

signal levels.

The adjustable gain stage provides 20 levels of gain in

1.0 dB increments. It is controlled with bits 7/9–5 as shown in

Table 1. The effect of the gain setting under various

ALC/Limiter On/Off settings is shown in Figure 9.

The Low–Pass Filter before the gain stage is a switched

capacitor filter with a corner frequency at 3.7 kHz. This

Figures 16 through 22 describe the characteristics of the

compressor, ALC, and limiter.

18

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 9. Tx Audio Output Voltage

versus Gain Control Setting

Figure 10. Lim In to Tx Out

Gain versus Frequency (Inband)

2.0

0

5.0

0

V

A

in

= 3.6 V

CC

T = 25°C

V = –10 dBV

ALC Off, Limiter Off

–5.0

–10

–15

–20

–25

–2.0

–4.0

–6.0

–8.0

–10

–12

–14

–16

–18

–20

ALC Off, Limiter On

–30

–35

–40

–45

–50

–55

V

A

= 3.6 V

T = 25°C

V = –10 dBV

in

CC

ALC On, Limiter On/Off

–9.0 –7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0

11

100

1000

10000

Tx GAIN SETTING (dB)

f, FREQUENCY (Hz)

Figure 12. Lim In to Tx Out

Figure 11. Lim In to Tx Out

Gain versus Frequency (Wideband)

Gain versus Frequency (Ripple)

–0.5

10

0

–0.6

–0.7

–0.8

–0.9

–1.0

–1.1

–1.2

–1.3

–1.4

–1.5

V

A

= 3.6 V

T = 25°C

V = –10 dBV

in

CC

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

A

= 3.6 V

T = 25°C

CC

V = –10 dBV

in

100

1000

10000

100

1000

10000

100000

1000000

f, FREQUENCY (Hz)

Figure 13. Lim In to Tx Out

Phase versus Frequency

Figure 14. Lim In to Tx Out

Group Delay versus Frequency

180

135

90

10

1.0

0.1

0

V

A

= 3.6 V

T = 25°C

V = –10 dBV

in

V

A

in

= 3.6 V

T = 25°C

V = –10 dBV

CC

45

0

–45

–90

–135

–180

100

1000

10000

100

1000

10000

f, FREQUENCY (Hz)

19

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 16. Tx Audio Compressor Response

(Distortion & Amplitude, ALC off, Lim off)

Figure 15. Compressor Characteristic with

Programmable Compressor Maximum Gain

0

–10

–20

–30

–40

–50

0

–5.0

–10

–15

14

12

10

8.0

6.0

4.0

2.0

0

V > = –4.0 dBV, V = 1.26 V

in out pp

(rapidly changing limited signals)

V

= 3.6 V

CC

T = 25°C

Compressor Transfer

A

R6/8 = 1

V = –2.5 dBV,

in

out

“Comp Low Max Gain En” = 0

Maximum Gain = 21

V

= –10 dBV

–20

–25

–30

–35

–40

–45

–23.5

V = –16 dBV,

in

–30

–33

V

= –13 dBV

out

(slowly changing ALC signals)

“Comp Low Max Gain En” = 1.0

Maximum Gain = 12

Distortion

–10

–60

–50

–40

–30

–20

–10

0

–60

–50

–40

–30

–20

0

10

C IN (dBV)

C IN VOLTAGE (dBV)

Figure 17. Tx Audio Compressor Response

(Distortion & Amplitude, ALC off, Lim off)

Figure 18. Tx Output Audio Response

(Lim & ALC off)

0

–5.0

–10

–15

–20

–25

–30

–35

–40

–45

14

12

10

8.0

6.0

4.0

2.0

0

–5.0

–10

–15

–20

–25

–30

–35

–40

4.0

3.0

2.0

1.0

0

V

= 3.6 V

CC

V

= 3.6 V

Compressor Transfer

CC

T = 25°C

A

T = 25°C

A

R6/8 = 0

Tx Out

Distortion

–10

Distortion

–10

–60

–50

–40

–30

–20

0

10

–60

–50

–40

–30

–20

0

10

C IN VOLTAGE (dBV)

MCI VOLTAGE (dBV)

Figure 19. Tx Output Audio Response

(Lim on, ALC off)

Figure 20. Tx Output Audio Response

(Lim off, ALC on)

0

–5.0

–10

–15

–20

–25

–30

–35

–40

4.0

3.0

2.0

1.0

0

–5.0

–10

–15

–20

–25

–30

–35

–40

4.0

3.0

2.0

1.0

0

V

= 3.6 V

CC

V

= 3.6 V

CC

T = 25°C

A

T = 25°C

A

Tx Out

Distortion

–20

–60

–50

–40

–30

–10

0

10

–60

–50

–40

–30

–20

–10

0

10

MCI VOLTAGE (dBV)

20

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 21. Tx Output Audio Response

(Lim off, R6/11 = 1)

Figure 22. Tx Output Audio Response

(Lim off, R6/12 = 1)

0

–5.0

–10

–15

–20

–25

–30

–35

–40

4.0

3.0

2.0

1.0

0

–5.0

–10

–15

–20

–25

–30

–35

–40

4.0

3.0

2.0

1.0

0

V

= 3.6 V

CC

V

= 3.6 V

CC

T = 25°C

A

T = 25°C

A

Tx Out

Distortion

–20

–60

–50

–40

–30

–10

0

10

–60

–50

–40

–30

–20

–10

0

10

MCI VOLTAGE (dBV)

Data Slicer

The gain stage provides 20 dB of gain adjustment in

1.0 dB steps, measured from Pin 38 to 36. Bits 7/4–0 are

used to set the gain according to Table 3. The mute switch,

controlled by bit 6/1, will mute a minimum of 60 dB.

When the compressor output is within 3.0 dB of the

expander input level, the Rx output (Pin 36) can be attenuated

(referenced to the expander output) by bits 6/10–9. For

6/10–9 = 00, the attenuation is 0 dB. For the other

combinations, 6/10–9 = 01, attenuation = 3.0 dB; 6/10–9 =

10, attenuation = 6.0 dB; and 6/10–9 = 11, attenuation = 10.4

dB (See Table 2).

The data slicer will receive the low level digital signal from

the RF receiver section at Pin 39. The input signal to the data

slicer must be >200 mVpp. Hysteresis of 40 mV is internally

provided. The output of the data slicer will be same

waveform, but with an amplitude of 0 to V , and can be

CC

observed at Pin 17 if bits 5/9–8 are set to 00. The output can

be inverted by setting bit 5/9 = 1. The data slicer can be

disabled by setting bit 5/8 = 1.

Receive Audio Path

The Receive Audio Path (Pins 38, 36–33) consists of an

anti–aliasing filter, a low–pass filter, side tone attenuator, gain

adjust stage, a mute switch, expander and volume control.

The switched capacitor low–pass filter is an 8 pole filter,

with a corner frequency at 3.8 kHz. This is designed to

provide bandwidth limiting in the audio range.

The expander can be bypassed by setting bit 6/3 = 1.

Table 3 shows the various gain control settings which can

be accessed in Register 7. Table 4 is the volume control

settings, also located in Register 7.

Figures 23 through 31 illustrate the various characteristics

of the reveive audio path.

Table 2. Side Tone Attenuate Programming

Side Tone

Side Tone Attenuate

Attenuate Bit #1

Attenuate Bit #0

Select #

Amount at Expander Input

Amount at Expander Output

0

1

0

1

0

1

0

1

2

3

0 dB

3.0 dB

6.0 dB

10.4 dB

1.5 dB

3.0 dB

5.2 dB

Table 3. Rx Gain Adjust Programming (Register 7)

Gain Control Gain Control

Gain Control

Bit #2

Gain Control

Bit #1

Gain Control

Bit #0

Gain

Ctl #

Gain/Attenuation

Amount

Bit #4

Bit #3

–

0

–

0

1

–

1

0

1

–

1

0

1

0

–

0

1

0

1

0

1

0

1

<6

6

–9.0 dB

–8.0 dB

–7.0 dB

–6.0 dB

–5.0 dB

–4.0 dB

–3.0 dB

–2.0 dB

7

8

9

10

11

12

13

21

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Table 3. Rx Gain Adjust Programming (Register 7) (continued)

Gain Control Gain Control

Gain Control

Bit #2

Gain Control

Bit #1

Gain Control

Bit #0

Gain

Ctl #

Gain/Attenuation

Amount

Bit #4

Bit #3

0

1

–

1

0

1

–

1

0

1

0

–

1

0

1

0

1

0

–

0

1

0

1

0

1

0

1

0

1

0

1

–

14

15

16

17

18

19

20

21

22

23

24

25

>25

–1.0 dB

0 dB

1.0 dB

2.0 dB

3.0 dB

4.0 dB

5.0 dB

6.0 dB

7.0 dB

8.0 dB

9.0 dB

10 dB

Table 4. Volume Control Programming

Volume Control

Bit #13

Volume Control

Bit #11

Volume Control

Bit #10

Volume

Ctl #

Gain/Attenuation

Amount

Bit #12

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–14 dB

–12 dB

–10 dB

–8.0 dB

–6.0 dB

–4.0 dB

–2.0 dB

0 dB

2

3

4

5

6

7

8

2.0 dB

4.0 dB

6.0 dB

8.0 dB

10 dB

9

10

11

12

13

14

15

12 dB

14 dB

16 dB

22

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 24. E Out Maximum Output Voltage

versus Volume Control Setting

Figure 23. Rx Out Maximum Output Voltage

versus Gain Control Setting

2.0

0

1.4

1.2

1.0

0.8

0.6

0.4

V

A

= 3.6 V

V

= 3.6 V

CC

T = 25°C

CC

–2.0

–4.0

–6.0

–8.0

–10

–12

–14

–16

–18

–20

T = 25°C

A

–9.0 –7.0 –5.0 –3.0 –1.0 1.0 3.0 5.0 7.0 9.0

11

–14

–10

–6.0

–2.0

2.0

6.0

10

14

Rx GAIN SETTING (dB)

VOLUME SETTING (dB)

Figure 25. Rx Audio In to Rx Out Gain

versus Frequency (Inband)

Figure 26. Rx Audio In to Rx Out Gain

versus Frequency (Ripple)

5.0

0.3

0.2

0

–5.0

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

V

= 3.6 V

T = 25°C

V = –20 dBV

V

= 3.6 V

CC

A

in

CC

T = 25°C

A

V = –20 dBV

in

100

1000

10000

100

1000

f, FREQUENCY (Hz)

Figure 27. Rx Audio In to Rx Out Gain

versus Frequency (Wideband)

Figure 28. Rx Audio In to Rx Out Phase

versus Frequency

10

0

180

135

90

V

= 3.6 V

CC

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

T = 25°C

A

V = –20 dBV

in

45

0

–45

–90

–135

–180

V

= 3.6 V

CC

T = 25°C

A

V = –20 dBV

in

100

1000

10000

100000

1000000

100

1000

f, FREQUENCY (Hz)

23

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 30. AALPF Response

Gain versus Frequency

Figure 29. Rx Audio In to Rx Out

Group Delay versus Frequency

10

1.0

0.1

0

10

0

V

A

in

= 3.6 V

T = 25°C

V = –20 dBV

CC

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

A

= 3.6 V

T = 25°C

V = –20 dBV

in

SCF Clk = 2.5 MHz

CC

SCF Corner = 57 kHz

100

1000

10000

100

1000

10000

f, FREQUENCY (Hz)

100000

1000000

f, FREQUENCY (Hz)

Figure 31. E In to E Out

Transfer Curve

5.0

–5.0

–15

–25

–35

–45

–55

–65

28

24

20

16

12

8.0

4.0

V

= 3.6 V

CC

T = 25°C

A

Expander Transfer

Distortion

0

–40

–35

–30

–25

–20

–15

–10

–5.0

E IN VOLTAGE (dBV)

24

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Power Amplifiers

The power amplifiers (Pins 29, 30, 32) are designed to

drive the earpiece in a handset, or the telephone line via a

hybrid circuit in the base unit. Each output (PAO+ and PAO–)

can be used for frequency shaping. The pins’ dc level is VB

( 1.5 V).

The Mute switch, controlled with bit 6/0, will provide 60 dB

of muting with a 50 kΩ feedback resistor. The amount of

muting will depend on the value of the feedback resistor.

Figures 32 and 33 show the power amplifier

can source and sink 5.0 mA, and can swing 1.3 V each. For

pp

high impedance loads, each output can swing 2.7 V (5.4

pp

V

differential). The gain of the amplifiers is set with a

pp

feedback resistor from Pin 30 to 32, and an input resistor at

Pin 32. The differential gain is 2x the resistor ratio. Capacitors

swing/distortion for V

maximum swing capability for various value of V

= 3.6 V, and Figure 34 illustrates the

CC

.

CC

Figure 33. Power Amplifier

Figure 32. Power Amplifier

Distortion

Maximum Output Swing

3.2

20

V

A

= 3.6 V

Open

CC

T = 25°C

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

130 Ω

15

10

5.0

0

130 Ω

Open

V

A

= 3.6 V

T = 25°C

CC

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4

PAI (V )

pp

Figure 34. Power Amplifier

Maximum Output Swing versus V

CC

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Open

T = 25°C

A

130 Ω

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

CC

25

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Reference Oscillator/MCU Clk Out

Figure 36. Reference Oscillator

Input and Output Impedance

The reference oscillator provides the frequency basis for

the three PLLs, the switched capacitor filters, and the MCU

clock output. The source for the reference clock can be a

crystal in the range of 4.0 to 18.25 MHz connected to Pins

Input Impedance (R // C )

PI PI

11.6 kΩ // 2.9 pF

4.5 kΩ // 2.5 pF

Output Impedance (R // C

)

PO PO

15 & 16, or it can be an external source connected to F In

ref

(Pin 15). The reference frequency is directed to:

Figures 37 and 38 show a typical gain/phase response of

the oscillator. Load capacitance (C ), equivalent series

L

a. A programmable 12–bit counter (register bits 4/11–0) to

provide the reference frequency for the three PLLs. The

12–bit counter is to be set such that, in conjunction with the

programmable counters within each PLL, the proper

frequencies can be produced by each VCO.

resistance (ESR), and even supply voltage will have an effect

on the oscillator response as shown in Figures 39 and 40. It

should be noted that optimum performance is achieved when

C1 equals C2 (C1/C2 = 1).

Figure 41 represents the ESR versus crystal load

capacitance for the reference oscillator. This relationship was

defined by using a 6.0 dB minimum loop gain margin at 3.6 V.

This is considered the minimum gain margin to guarantee

oscillator start–up.

Oscillator start–up is also significantly affected by the

crystal load capacitance selection. In Figure 39, the

relationship between crystal load capacitance and ESR can

be seen. The lower the load capacitance the better the

performance.

b. A programmable 6–bit counter (register bits 4/17–12),

followedbya÷2stage, tosetthefrequencyfortheswitched

capacitor filters to 165 kHz, or as close to that as possible.

c. A programmable 3–bit counter (register bits 7/16–14)

which provides the MCU clock output (see Tables 5 and 6).

A representation of the reference oscillator is given by

Figures 35 and 36.

Figure 35. Reference Oscillator Schematic

Reference Oscillator

Given the desired crystal load capacitance, C1 and C2

can be determined from Figure 42. It should also be pointed

out that current consumption increases when C1 ≠ C2.

Be careful not to overdrive the crystal. This could cause a

noise problem. An external series resistor on the crystal

output can be added to reduce the drive level, if necessary.

R

C

PI

C

PO

R

PO

PI

Gm

F

ref

In

F

ref

Out

Xtal

C

1

C

2

26

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 38. Reference Oscillator

Figure 37. Reference Oscillator

Open Loop Phase versus Frequency

Open Loop Gain versus Frequency

16

14

100

V

= 3.6 V

80

60

CC

V

A

= 3.6 V

T = 25°C

CC

T = 25°C

A

12

10.24 MHz, 10 pF

Load Capacitance

Crystal

10.24 MHz, 10 pF

Load Capacitance

Crystal

10

40

8.0

6.0

4.0

2.0

0

20

0

F

–20

–40

–60

–80

–100

ref out ref in

16 15

16

15

13 pF

–2.0

–4.0

10.237

10.238

10.239

10.240

10.241

10.242

10.243

10.237

10.238

10.239

10.240

10.241

10.242 10.24

f, FREQUENCY (MHz)

Figure 39. Reference Oscillator Startup Time

versus Total ESR – Inactive to Rx Mode

Figure 40. Reference Oscillator

Open Loop Gain versus ESR

5.0

4.0

3.0

2.0

1.0

0

20

16

12

8.0

4.0

0

V

= 3.6 V

V

A

= 3.6 V

CC

T = 25°C

A

2.048 MHz

5.12 MHz

0

50

100

150

200

250

300

350

0

50

100

150

200

250

300

350

TOTAL ESR (Ω)

Figure 41. Maximum ESR versus

Crystal Load Capacitance (C1 = C2)

Figure 42. Optimum Values for C1, C2 versus

Equivalent Required Parallel Capacitance

1000

100

10

70

60

50

40

30

20

10

0

10 12 14 16 18 20 22 24 26 28 30 32

5.0

10

15

20

25

30

35

CRYSTAL LOAD CAPACITANCE (pF)

27

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Table 5. MCU Clock Divider Programming

MCU Clk Bit #16

MCU Clk Bit #15

MCU Clk Bit #14

Clk Out Divider Value

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.0

3.0

4.0

5.0

2.5

20

80

312.5

Table 6. MCU Clock Divider Frequencies

Clock Output Divider

Crystal

Frequency

10.24 MHz

11.15 MHz

12 MHz

2.0

2.5

3.0

4.0

5.0

20

80

312.5

5.12 MHz

5.575 MHz

6.0 MHz

4.096 MHz

4.46 MHz

4.8 MHz

3.413 MHz

3.717 MHz

4.0 MHz

2.56 MHz

2.788 MHz

3.0 MHz

2.048 MHz

2.23 MHz

2.4 MHz

512 kHz

557 kHz

600 kHz

128 kHz

139 kHz

150 kHz

32.768 kHz

35.68 kHz

38.4 kHz

Transmit and Receive (LO1) PLL Sections

f

VCO

(1)

Nt (Nt must be an integer)

The transmit and receive PLLs (Pins 6–9 and 1–4,

respectively) are designed to be part of a 900 MHz system. In

a typical application the Transmit PLL section will be set up to

generate the transmit frequency, and the Receive PLL

section will be set up to generate the LO1 frequency. The two

sections are identical, and function independently. External

requirements for each include a low–pass filter, a 900 MHz

VCO, and a 64/65 or 128/129 dual modulus prescaler.

The frequency output of the VCO is to be reduced by the

dual modulus prescaler, and then input to the MC33411 (at

Pin 8 or 2). That frequency is then further reduced by the

programmable 13–bit counter (bits 1/19–7 or 2/19–7), and

provided to one side of the Phase Detector, where it is

compared with the PLL reference frequency. The output of

the phase detector (at Pin 6 or 4) is a Three–State charge

pump which drives the VCO through the low–pass filter. Bits

1/20 and 2/20 set the gain of each of the two charge pumps

to either 100/2π µA/radian or 400/2π µA/radian. The polarity

of the two phase detector outputs is set with bits 1/21 and

2/21. If the bit = 0, the appropriate PLL is configured to

operate with a non–inverting low–pass filter/VCO

combination. If the low–pass filter/VCO combination is

inverting, the polarity bit should be set to 1.

f

PLL

Nt

P

(2)

(3)

N

A = Remainder of Equation 2

(decimal part of N x P)

where:

f

= the VCO frequency

VCO

f

= the PLL Reference Frequency set within

the MC33411

PLL

P = the smaller divisor of the dual modulus

prescaler (64 for a 64/65 prescaler)

N = the whole number portion is the setting for the

N (or N’) counter within the MC33411

A = the setting for the A (or A’) counter within the

MC33411

For example, if the VCO is to provide 910 MHz, and the

internal PLL reference frequency is 50 kHz, then the

equations yield:

6

3

910 x 10

Nt

N

18, 200

50 x 10

The 7–bit A and A’ counters (bits 1/6–0 and 2/6–0) are to

be set to drive the Modulus Control input of the 64/65 or

128/129 dual modulus prescalers. The Modulus Control

outputs (Pins 9 and 1) can be set to either a voltage mode

(logic 1) or a current mode (logic 0) with bit 3/16.

18, 200

64

284.375

A

0.375 x 64

24

To calculate the settings of the N and A registers, the

following procedure is used:

The N register setting is 284 (0 0001 0001 1100), and the

A register setting is 24 (001 1000).

28

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

and the 2nd LO frequency is to be 63.3 MHz, the 14–bit

2nd LO (LO2)

counter needs to be set to 1266 (00 0100 1111 0010). The

d

This PLL is designed to be the 2nd Local Oscillator in a

typical 900 MHz system, and is designed for frequencies up

to 80 MHz. The VCO and varactor diodes are included, and

are to be used with an external tank circuit (Pins 43–45).

Bits 4/20–18 are used to select an internal capacitor, with

a value in the range of 0 to 7.6 pF, to parallel the varactor

diodes and the tank’s external capacitor. This permits a

certain amount of fine tuning of the oscillator’s performance.

See Table 7.

A buffered output is provided to drive, e.g., a mixer. The

frequency is set with the programmable 14–bit counter

(bits 3/13–0) in conjunction with the PLL reference

frequency. For example, if the reference frequency is 50 kHz,

output level is dependent on the value of the impedance at

Pin 41, partly determined by the external pull–up resistor.

The output of the phase detector is a Three–State charge

pump which drives the varactor diodes through an external

low–pass filter. Bit 3/14 sets the gain of the charge pump to

either 100/2π µA/radian (logic 0) or 400/2π µA/radian

(logic 1). Bit 3/15 sets its polarity – if 0, the PLL is configured

to operate with a non–inverting low–pass filter/VCO

combination. If the low–pass filter/VCO combination is

inverting, the polarity bit should be set to 1. Please note that

the 2nd LO VCO on the MC33411 is of the non–inverting

type. Figures 43 through 45 describe the response of the 2nd

LO.

Table 7. LO2 Capacitor Select Programming

LO2 Capacitor Select

Bit #20

LO2 Capacitor Select

Bit #19

LO2 Capacitor Select

Bit #18

LO2 Capacitor Select

Value

Select #

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

0 pF

1.1 pF

2.2 pF

3.3 pF

4.3 pF

5.4 pF

6.5 pF

7.6 pF

29

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 43. Varicap Capacitance

versus Control Voltage

Figure 44. Minimum Overall Q

versus Coil Inductance for LO2

16

15

80

V

= 3.6 V

V

= 3.6 V

CC

70

60

50

40

30

20

10

0

30 MHz

T = 25°C

A

T = 25°C

A

14

13

12

60 MHz

11

10

9.0

8.0

7.0

6.0

80 MHz

200

0

1

2

3

4

5

6

0

400

600

800

1000

1200

CONTROL VOLTAGE (V)

COIL INDUCTANCE (nH)

Figure 45. LO2 Amplitude versus Overall Tank

Parallel Resistance

35

30

25

20

15

10

5

V

= 3.6 V

CC

T = 25°C

A

F

= 63.3 MHz

LO

0

500

1000

1500

2000

2500

3000

3500

TANK RESISTANCE (Ω)

30

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Loop Filter Characteristics

pole and a zero around the 0 dB point to guarantee sufficient

phase margin in this design (Qp in Figure 48).

Let’s consider the following discussion on loop filters. The

fundamental loop characteristics, such as capture range,

loop bandwidth, lock–up time, and transient response are

controlled externally by loop filtering.

Figure 48. Bode Plot of Gain and

Phase in Open Loop Condition

0

Figure 46 is the general model for a Phase Lock Loop

(PLL).

Open Loop Gain

0

Figure 46. PLL Model

Phase

Detector (K )

Filter

(K )

f

VCO

(K )

–90

fi

fo

pd

o

Phase

Divider

(K )

n

Q

p

Where:

K

= Phase Detector Gain Constant

ω

pd

f

o

n

–180

p

K = Loop Filter Transfer Function

K = VCO Gain Constant

K = Divide Ratio (N)

fi = Input frequency

fo = Output frequency

fo/N = Feedback frequency divided by N

The open loop gain including the filter response can be

expressed as:

K

K (1 j (R2C2))

o

pd

A

openloop

(4)

R2C1C2

C1 C2

j K

j

1

j

n

From control theory the loop transfer function can be

represented as follows:

The two time constants creating the pole and the zero in

the Bode plot can now be defined as:

K

K K

o

pd

f

Open loop gain

A

K

n

R2C1C2

T1

T2

R2C2

(5)

C1 C2

By substituting equation (5) into (4), it follows:

K

can be either expressed as being 200 µA/4π or

pd

800 µA/4π. More details about performance of different type

PLL loops, refer to Motorola application note AN535.

The loop filter can take the form of a simple low pass filter.

A current output, type 2 filter will be used in this discussion

since it has the advantage of improved step response,

velocity, and acceleration.

K

K T1

o

pd

1

j T2

j T1

A

(6)

openloop

2

C1K T2

n

The type 2 low pass filter discussed here is represented as

follows:

The phase margin (phase + 180) is thus determined by:

(

)

(

)

Q

arctan T2 –arctan T1

(7)

p

Figure 47. Loop Filter

with Additional Integrating Element

At ω=ω , the derivative of the phase margin may be set to

p

zero in order to assure maximum phase margin occurs at ω

(see also Figure 48). This provides an expression for ω :

p

From

Phase

p

To VCO

Detector

R2

C2

dQ

p

T2

T1

(8)

0

–

2

d

C1

(

)

(

)

T1

1

T2

1

p

From Figure 47, capacitor C1 forms an additional

integrator, providing the type 2 response, and filters the

discrete current steps from the phase detector output. The

function of the additional components R2 and C2 is to create

a pole and a zero (together with C1) around the 0 dB point of

the open loop gain. This will create sufficient phase margin

for stable loop operation.

In Figure 48, the open loop gain and the phase is

displayed in the form of a Bode plot. Since there are two

integrating functions in the loop, originating from the loopfilter

and the VCO gain, the open loop gain response follows a

second order slope (–40 dB/dec) creating a phase of –180

degrees at the lower and higher frequencies. The filter

characteristic needs to be determined such that it is adding a

(9)

T2T1

Or rewritten:

1

T1

2

(10)

T2

p

By substituting into equation (7), solve for T2:

Q

p

2

tan

4

(11)

31

T2

p

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

By choosing a value for ω and Q , T1 and T2 can be

calculated. The choice of Q determines the stability of the

p

The VCO gain is dependent on the selection of the

external inductor and the frequency required. The free

running frequency of the VCO is determined by:

loop. In general, choosing a phase margin of 45 degrees is a

good choice to start calculations. Choosing lower phase

margins will provide somewhat faster lock–times, but also

generate higher overshoots on the control line to the VCO.

This will present a less stable system. Larger values of phase

margin provide a more stable system, but also increase

lock–times. The practical range for phase margin is 30

degrees up to 70 degrees.

1

f

(16)

2

LC

T

In which L represents the external inductor value and C

T

represents the total capacitance (including internal

capacitance) in parallel with the inductor. The VCO gain can

be easily calculated via the internal varicap transfer curve

shown in Figure 43.

The selection of ω is strongly related to the desired

p

lock–time. Since it is quite complicated to accurately

calculate lock time, a good first order approach is:

As can be derived from Figure 43, the varicap capacitance

changes 2.0 pF over the voltage range from 1.0 V to 3.0 V:

3

p

T_lock

(12)

2.0 pF

2.0 V

(17)

Equation (12) only provides an order of magnitude for lock

time. It does not clearly define what the exact frequency

difference is from the desired frequency and it does not show

the effect of phase margin. It assumes, however, that the

phase detector steps up to the desired control voltage

without hesitation. In practice, such step response approach

is not really valid. If the two input frequencies are not locked,

their phase maybe momentarily zero and force the phase

detector into a high impedance mode. Hence, the lock times

may be found to be somewhat higher.

Cvar

Combining (16) with (17) the VCO gain can be determined

by:

1

(18)

K

o

j2.0V

2

LC

Cvar

2

T

2

L C

T

In general, ω should be chosen far below the reference

p

frequency in order for the filter to provide sufficient

attenuation at that frequency. In some applications, the

reference frequency might represent the spacing between

channels. Any feedthrough to the VCO that shows up as a

spur might affect adjacent channel rejection. In theory, with

the loop in lock, there is no signal coming from the phase

detector. But in practice small current pulses and leakage

currents will be supplied to both the VCO and the phase

detector. The external capacitors may show some leakage,

Although the basic loopfilter previously described provides

adequate performance for most applications, an extra pole

may be added for additional reference frequency filtering.

Given that the channel spacing is based on the reference

frequency, and any feedthrough to the first LO may effect

parameters like adjacent channel rejection and

intermodulation. Figure 49 shows a loopfilter architecture

incorporating an additional pole.

too. Hence, the lower ω , the better the reference frequency

is filtered, but the longer it takes for the loop to lock.

p

Figure 49. Loop Filter

with Additional Integrating Element

As shown in Figure 48, the open loop gain at ω is 1 (or

p

0 dB), and thus the absolute value of the complex open loop

gain as shown in equation (6) solves C1:

From

Phase

To VCO

Detector

R3

R2

C2

2

K

K T1

1

T2

T1

o

p

C1

C3

pd

2

C1

(13)

2

K T2

n

p

For the additional pole formed by R3 and C3 to be efficient,

the cut–off frequency must be much lower than the reference

frequency. However, it must also be higher than ω in order

With C1 known, and equation (5) solve C2 and R2:

p

not to compromise phase margin too much. The following

equations were derived in a similar manner as for the basic

filter previously described.

T2

C2

C1

1

(14)

(15)

T1

T2

C2

R2

32

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Similarly, it can be shown:

K

o

pd

1

j T2

j T1

A

–

(19)

(20)

openloop

In which:

2

C1C2C3R2R3

(

)

K

C1 C2 C3 –

n

(

)

(

)

C1 C2 T2

C1C2 T3

2

T1

C1 C2 C3

C1T2T3

(21)

(22)

T2

R2C2

T3

R3C3

From T1 it can be derived that:

2

(

)

T1 T2 C3 C1 T2 T3 T1

T1T2T3

C2

(23)

(24)

T3 T1

In analogy with (13), by forcing the loopgain to 1 (0 dB) at

ω , we obtain:

p

2

K

1

T2

o

2

p

pd

n p

(

)

C1 T1 T2

C2T3 C3T2

2

T1

p

Solving for C1:

2

K

K T1

o

1

T2

T1

p

pd

p

(

)

(

)

(

)

T3 T1

T2 T1 T3C3

T3 T1 T2C3

2

K

n

p

C1

(25)

2

(

)

(

)

T3 T1 T2

T3 T1 T3

T2 T3 T1

T1T2T3 T3

p

By selecting ω via (12), the additional time constant

expressed as T3, can be set to:

LO2 Tank:

p

Ctotal = 39.3 pF

Lext = 150 nH, Q = 50 @ 250 MHz

Reference Frequency = 10.24 MHz (unadjusted)

R Counter = 205

LO2 Counter = 1266

1

(26)

T3

K

p

The K–factor shown determines how far the additional

AC Load = 25 Ω

pole frequency will be separated from ω . Selecting too small

Frequency of LO2 = 63.258 MHz

Phase Noise @ 50 kHz offset = –107 dBc

Sidebands @ 50 kHz & 100 kHz offsets = –69 dBc

p

of a K–factor, the equations may provide negative

capacitance or resistor values. Too large of a K–factor may

not provide the maximum attenuation.

Low Battery/ RSSI Voltage Measurement

By selecting R3 to be 100 kΩ, C3 becomes known and C1

and C2 can be solved from the equations. By using equations

(11) and (10), time constants T2 and T1 can be derived by

selecting a phase margin. Finally, R2 follows from T2 and C2.

A test circuit with the following components and conditions

was constructed with these results:

Both the Low Battery (bits 5/23–18) and RSSI (bits

5/17–12) measurement circuits have a 6–bit A/D converter

whose value may be read back via the SPI. The A/D’s sample

their voltages at a frequency equal to the internal SCF clock

frequency divided by 128. The Low Battery Measurement A/D

senses and divides by 2.5 the supply voltage (at Pin 23).

Please note that the minimum Low Battery Detect (LBD)

voltage is 2.7 V, since there is no guarantee that the device will

operate below this value. The RSSI Measurement senses the

voltage at Pin 37.

Loop Filter (See Figure 49):

C1 = 470 pF

R2 = 68 kΩ

C2 = 3.9 nF

R3 = 270 kΩ

C3 = 82 pF

33

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

These values are compared to the internal reference VB

VB Voltage Adjust and Characteristics

(≈1.5 V) which is available at Pin 37. The value read back

from the LBD A/D will therefor be approximately:

VB has a production tolerance of ±8%, and can be

adjusted over a ±9% range using bits 3/20–17. The

adjustment steps will be ≈1.2% each (See Table 8). If

desired, VB can be used to bias external circuitry, as long as

63 (V

)

(27)

(28)

CC

N(for LBD)

the load current on this pin does not exceed 10 µA. V varies

B

2.5(VB)(1.07)

by less than ±0.5% over supply voltage, referenced to V

3.6 V.

=

CC

and for the RSSI

The value of the de–coupling capacitor connected from VB

to ground affects both the noise and crosstalk from the

receive and transmit audio paths, so the value should be

chosen with caution. Figures 50 and 51 show this

relationship.

63 (RSSIVoltage)

(VB)(1.07)

N(for RSSI)

Table 8. VB Voltage Reference Programming

V

ref

Adjust #

Voltage Reference

Adjustment Amount

ref

Adjust Bit #20

Adjust Bit #19

Adjust Bit #18

Adjust Bit #17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–9.0%

–7.8%

–6.6%

–5.4%

–4.2%

–3.0%

–1.8%

–0.6%

0.6%

2

3

4

5

6

7

8

9

1.8%

10

11

12

13

14

15

3.0%

4.2%

5.4%

6.6%

7.8%

9.0%

Figure 51. Crosstalk/Noise from

E In to Tx Out versus VB Capacitor

Figure 50. Crosstalk/Noise from

C In to E Out versus VB Capacitor

–105

–110

–115

–120

–125

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

–61

–63

–65

–67

Noise

–87

–92

Noise

Crosstalk

Crosstalk, 130 Ω load

–97

–69

–71

–73

–75

Crosstalk, no load

–102

–107

V

A

= 3.6 V

T = 25°C

V

A

= 3.6 V

CC

T = 25°C

0.01

0.1

1.0

10

0.01

0.1

1.0

10

VB CAPACITOR (µF)

34

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

MCU Serial Interface

The MCU Serial Interface is a 3–wire interface, consisting

of a Clock line, an Enable line, and a bi–directional Data line.

The interface is always active, i.e., it cannot be powered

down as all other sections of the MC33411 are disabled and

enabled through this interface.

The clock (Return–to–Zero format) must be supplied to the

MC33411 at Pin 11 to write or read data, and can be any

frequency up to 2.0 MHz. The clock need not be present

when data is not being transferred. The Enable line must be

low when data is not being transferred.

After the device power–up (or whenever a reset condition

is required), the MCU should perform the following steps:

Internally there are 7 data registers, 24–bits each, addressed

with 4–bits ranging from $h1 to $h7 (see Tables 9 and 10).

Register 5, bits 23–12 are read–only bits, while all other register

bits are Read/Write. All unused/unimplemented bits are

reserved for Motorola use only. The contents of the 7 registers

can be read out at any time. All bits are written in, or read out,

on the clock’s positive transition. The write and read operations

are as follows:

1. Initialize the Data line to a high impedance state.

2. Initialize the Clock line to a logic low.

3. Initialize the Enable line to a logic low.

4. Pulse the Clock line a minimum of once (RZ format)

while leaving the Enable line continuously low. This

places the SPI port into a known condition.

5. Load all registers with their desired initial values.

Figure 52. Writing Data to the MC33411

1

2

3

24

Clock

Data

MSB

LSB

4–Bit Address

24–Bit Data from MCU

Latch Address

Latch Data

Enable

a. Write Operation:

10. After the last bit is entered, the Enable line is to be taken

high and then low. The falling edge of this pulse latches in

the just entered data. The clock line must be at a logic low

and must not transition ineitherdirectionduringthisEnable

pulse.

– To write data to the MC33411, the following sequence is

required (see Figure 52):

6. The Enable line is taken high.

7. Five bits are entered:

11.The Enable line must then be kept low until the next

communication.

– The first bit must be a 0 to indicate a Write operation.

– The next four bits identify the register address

(0001–0111). The MSB is entered first.

Note: If less than 24 bits are to be written to a data register,

it is not necessary to enter the full 24 bits, as long as they are

all lower order bits. For example, if bits 0–6 of a register are to

be updated, they can be entered as 7 bits with 7 clock cycles

in step 4 above. However, if this procedure is used, a minimum

of 4 bits, with 4 clock pulses, must be entered.

8. The Enable line is taken low. At this transition, the address

is latched in and decoded.

9. The Enable line is maintained low while the data bits are

clocked in. The MSB is entered first, and the LSB last. If

24–bits are written to a register which has less than 24 active

bits (e.g., register 6), the unassigned bits are to be 0.

35

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 53. Reading Data from the MC33411

Sets Data Pin

to Output

1

2

3

24

Clock

Data

MSB

LSB

4–Bit Address

24–Bit Data from MC33411

Sets Data Pin

to Input

Latch Address and Load

Data into Shift Register

Enable

b. Read Operation:

3. Pin 3 provides power to the Rx PLL section. Pin 5 is the

ground pin.

4. Pin 7 provides power to the Tx PLL section, and the MCU

interface. Pin 5 is the ground pin.

– To read the output bits (bits 5/23–12), or the contents of

any register, the following sequence is required (see

Figure 53):

5. Pin 42 provides power to the 2nd LO section. Pins 46 and 48

are the ground pins.

1. The Enable line is taken high.

2. Five bits are entered:

6. Pin14isthegroundpinforthedigitalcircuitry. Powerforthe

digital circuitry is derived from Pin 23.

– The first bit must be a 1 to indicate a Read operation.

– The next four bits identify the register address

(0001–0111). The MSB is entered first.

To conserve power, various sections can be individually

disabled by using bits 5/7–0 and 6/7 (setting a bit to 1

disables the section).

3. The Enable line is taken low. At this transition, the address

is latched in and decoded, and the contents of the selected

register is loaded into the 24–bit output shift register. At this

point, the Data line (Pin 12) is still an input.

1. Reference Oscillator Disable (bit 5/0) – The reference

oscillator at Pins 15 and 16 is disabled, thereby denying a

clock to the three PLLs and the switched capacitor filters.

This function is not available on the “B” version.

2. Tx PLL Disable (bit 5/1) – The 13–bit and 7–bit counters,

input buffer, phase detector, and modulus control blocks

are disabled. The charge pump output at Pin 6 will be in a

Hi–Z state.

3. Rx PLL Disable (bit 5/2) – The 13–bit and 7–bit counters,

input buffer, phase detector, and modulus control blocks

are disabled. The charge pump output at Pin 4 will be in a

Hi–Z state.

4. LO2 PLL Disable (bit 5/3) – The VCO, 14–bit counter,

output buffer, and phase detector are disabled. The charge

pump output at Pin 47 will be in a Hi–Z state.

5. Power Amplifier Disable (bit 5/4) – The two speaker

amplifiers are disabled. Their outputs will go to a high

impedance state.

6. Rx Audio Path Disable (bit 5/5) – The anti–aliasing filter,

low–pass filter, and variable gain stage are disabled.

7. Tx Audio Path Disable (bit 5/6) – Disables the microphone

amplifier and low–pass filter.

8. Low Battery/RSSI Measurement Disable (bit 5/7) – Both

6–bit A/Ds are disabled.

9. Data Slicer Disable (bit 5/8) – The data slicer is disabled

and DS Out goes to high impedance.

10. MCU Clock Disable (bit 6/7) – The MCU clock counter

is disabled and the MCU Clock Output will be in a Hi–Z

state. This function is not available on the “B” version.

4. While maintaining the Enable line low, the data is read out.

The first clock rising edge will change the Data line to an

output, and the MSB will be present on this line.

5. Thefullcontentsoftheregisterarethenreadout(MSBfirst,

LSB last) with a total of 24 clock rising edges, including the

one in step 4 above. It is recommended that the MCU read

the bits after the clock’s falling edge.

6. After the last clock pulse, the Enable line is to be taken high

and then low. The falling edge of this pulse returns the Data

Pin to be an input. The clock line must be at a logic low and

must not transition in either direction during this Enable

pulse.

7. The Enable line must then be kept low until the next

communication.

Power Supply/Power Saving Modes

The power supply voltage, applied to all V

pins, can

CC

pins must be within ±0.5 V of

range from 2.7 to 5.5 V. All V

CC

each other, and each must be bypassed. It is recommended

a ground plane be used, and all leads to the MC33411 be as

short and direct as possible. To reduce the possibility of

device latch–up, it is highly recommended that the Audio,

Synthesizer and RF V

portions of the chip be isolated from

CC

the main supply through 10 to 25 Ω resistors (see the

Evaluation PCB Schematic, Figure 54). This also provides

RF–to–Audio noise isolation. The supply and ground pins are

distributed as follows:

1. Pin 23 provides power to the audio section. Pin 40 is the

ground pin.

2. Pin 28 provides power to the speaker amplifier section.

Pin 31 is the ground pin.

Note: The 12–bit reference counter is disabled if the three

PLLs are disabled (bits 5/1–3 = 1).

36

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Table 9. Register

Map

Table 10. Register

Map: Power–Up

Defaults

37

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Evaluation PCB

The evaluation PCB is a versatile board which allows the

MC33411 to be configured to analyze individual operating

parameters or the complete audio transmit and receive

paths.

The general purpose schematic and associated parts list

for the PCB are given in Figure 54. With the jumpers

positioned as shown in the parts list (either shunt or open).

the PCB is configured to analyze complete transmit and

receive audio paths.

Parts lists as ”user defined” can be installed to analyze

other functions of the device. Table 11 lists these devices

along with their respective functions.

Table 11.

Function

Component(s)

Notes

R20

Microphone Bias

Pre–emphasis/De–emphasis

Detector Low–Pass Filter (LPF)

Data Slicer LPF

R19,J24,J27

R3,C7,J5

R4,C8

L1,C21

2nd LO Tank

See Equations 16 and 17

C18,R9,C19,R10,C20

C26,R13,C27,R14,C28

C22,R11,C23,R12,C24

2nd LO LPF

See Eq. 10, 11, 12, 21, 23, 25, and 26

Rx 1st LO LPF

Tx 1st LO LPF

38

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 55. MC33411A/B Evaluation PCB Component Side

4.5″

C1,C3,C5,C6,C9,C10,C12

C13,C2

1.0

220 p

JP1,JP2,JP3

J1,J4,J9,J10

Header, 5x2

AudioJack

C4,C11

0.47

Switchcroft 3501FP

L1,R3,R4,C7,C8,R9,R10,

R11,R12,R13,R14,C18,R19,

C19,R20,C20,C21,C22,C23,

C24,C26,C27,C28

C14,C17,C25,C29,C31,C33,

C35,C37,C40

User defined

J2,J3,J6,J7,J11,J12,J15,

J23,J25,J26

J5,J8,J13,J24,J27

J14,J16

Shunt

Open

SMA EF Johnson 142–0701–201

Bananna Johnson Components

108–0902–001

0.01

J17,J18

C15,C16

C30,C32,C34,C36

C38

C39

D1

27 p

10

4.7

0.1

1N4001

R1,R2,R5,R6

R7

R8,R18

R15,R16,R17

U1

47.5 k

130

49.9

10

MC33411AFTA or MC33411BFTA

10 M Raltron A–10.000–18

Y1

Default Units: Microfarads, Microhenries, and Ohms

40

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Figure 56. MC33411A/B Evaluation PCB Solder Side

4.5″

41

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

OUTLINE DIMENSIONS

FTA SUFFIX

PLASTIC PACKAGE

CASE 932–02

(LQFP–48)

ISSUE E

4X

NOTES:

0.200 AB T–U Z

1

DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2

3

CONTROLLING DIMENSION: MILLIMETER.

DATUM PLANE AB IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

DATUMS T, U, AND Z TO BE DETERMINED AT

DATUM PLANE AB.

DETAIL Y

9

A

P

A1

48

37

4

5

6

DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

1

36

DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE AB.

DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350.

T

U

B

V

7

AE

B1

V1

8

9

MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

EXACT SHAPE OF EACH CORNER IS OPTIONAL.

12

25

MILLIMETERS

13

24

DIM MIN

MAX

7.000 BSC

3.500 BSC

Z

A

A1

B

B1

C

D

E

F

G

H

J

K

L

M

N

P

S1

7.000 BSC

3.500 BSC

T, U, Z

1.400

1.600

0.270

1.450

0.230

S

0.170

1.350

0.170

DETAIL Y

4X

0.200 AC T–U Z

0.500 BSC

0.050

0.090

0.500

1

0.150

0.200

0.700

5

0.080 AC

12 REF

G

AB

AC

0.090

0.150

0.160

0.250 BSC

R

0.250

S

9.000 BSC

S1

V

V1

W

AA

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

AD

M

BASE METAL

TOP & BOTTOM

R

N

J

E

C

F

D

M

0.080

AC T–U Z

SECTION AE–AE

W

H

L

K

DETAIL AD

AA

42

MOTOROLA RF/IF DEVICE DATA

MC33411A/B

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Mfax is a trademark of Motorola, Inc.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan. 81–3–5487–8488

Customer Focus Center: 1–800–521–6274

Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

Motorola Fax Back System

– US & Canada ONLY 1–800–774–1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

– http://sps.motorola.com/mfax/

852–26668334

HOME PAGE: http://motorola.com/sps/

MC33411A/D

◊

43

MOTOROLA RF/IF DEVICE DATA


型号：	MC33411BFTA
厂家：	MOTOROLA
描述：	900 MHZ ANALOG CORDLESS PHONE BASEBAND WITH COMPANDER 与COMPANDER 900 MHz模拟无绳电话基带无绳技术电话
文件：	总43页 (文件大小：446K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33411BFTA [MOTOROLA]

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