MC33790DW/R2 [MOTOROLA]
Two-Channel Distributed System Interface (DSI) Physical Interface Device; 双通道分布式系统接口（ DSI ）的物理接口设备
| 型号： | MC33790DW/R2 |
| 厂家： | 
MOTOROLA |
| 描述： | Two-Channel Distributed System Interface (DSI) Physical Interface Device |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33790/D
Rev 6.0, 02/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33790
Two-Channel Distributed System
Interface (DSI) Physical Interface
Device
The 33790 is a two-channel physical layer interface IC for the Distributed
System Interface (DSI) bus. It is designed to meet automotive requirements. It
can also be used in nonautomotive applications. It supports bidirectional
communication between slave and master ICs. Some slave devices derive a
regulated 5.0 V from the bus, which can be used to power sensors, thereby
eliminating the need for additional circuitry and wiring.
TWO-CHANNEL DISTRIBUTED
SYSTEM INTERFACE (DSI)
PHYSICAL INTERFACE DEVICE
Features
• Two Independent DSI Compatible Busses
• Pinout Matched to MC68HC55 (SPI to DSI Logic)
• Wave-Shaped Bus Output Voltage
• Independent Thermal Shutdown and Current Limit
• Return Signalling Current Detection
• Internal Logic Input Pull-Ups and Pull-Downs
• On-Board Charge Pump
EG (Pb free) SUFFIX
DW SUFFIX
CASE 751G
• 2.0 kV ESD Capability
ORDERING INFORMATION
Temperature
• Communications Rate Up to 150 kbps
• Motorola now offers Pb-free packages with sufix code EG
Device
Package
Range (TJ)
MC33790DW/R2 -40°C to 150°C
MC33790EG/R2 -40°C to 150°C
16 SOICW
16 SOICW
33790 Simplified Application Diagram
33790
MC68HC55
+5.0 V
0.1 µF
V
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DD
GND
DSIBUS0
+25 V
DSI0O
V
SUP
DSIBUS1
DSI1O
GND
DSI1R
CPCAP
33793
33791
BUS_IN
BUS_OUT
BUS_IN
DSI Slave Device
33927
BUS_OUT
BUS_IN
BUS_IN
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
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Freescale Semiconductor, Inc.
V
DD (+5.0 V)
CPCAP
VSUP (IDLE Level)
Internal
Bias
Charge
Pump
Bus Supply
Voltage
+
DSI0O
DSI Bus
Bus Current
Sense
Wave-
Shaper
DSI0F
DSI0S
Transmitter
Driver
DSI0R
GND
+
DSI1O
Bus Current
Sense
DSI1F
DSI1S
Wave-
Shaper
DSI Bus
Transmitter
Driver
DSI1R
Figure 1. 33790 Simplified Internal Block Diagram
33790
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DSI0F
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
VDD
GND
DSI0O
VSUP
DSI10
GND
NC
CPCAP
NC
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1
DSI0F
This logic input controls the frame output for DSI channel 0 in accordance with Table 1, page 8.
2
3
DSI0S
DSI0R
DSI1F
DSI1S
DSI1R
NC
This logic input controls the signalling output for DSI channel 0 in accordance with Table 1, page 8.
This logic output provides the return data for DSI channel 0 in accordance with Table 1, page 8.
4
This logic input controls the frame output for DSI channel 1 in accordance with Table 1, page 8.
5
This logic input controls the signalling output for DSI channel 1 in accordance with Table 1, page 8.
6
This logic output provides the return data for DSI channel 1 in accordance with Table 1, page 8.
7
Unused.
8
CPCAP
NC
Used to store and filter charge pump output.
9
Unused.
10
11
12
13
14
15
16
NC
Unused.
GND
Circuit and bus ground return.
DSI1O
VSUP
DSI0O
GND
DSI bus 1 input/output.
Idle level supply input. The voltage supplied to this pin sets the idle level on the DSI bus.
DSI bus 0 input/output.
Circuit and bus ground return.
VDD
5.0 V logic supply input.
33790
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Supply Voltage
V
Continuous
Load Dump - t < 300 ms
V
-0.5 to 25
40
SUP
V
SUP(t)
Maximum Voltage on Input/Output Pins
V
-0.3 to 5.5
V
DD
-0.3 to VDD+0.3
DSIxS, DSIxF (Note 1)
DSIxO (Note 1)
-0.3 to VSUP+0.3
-55 to 150
-40 to 150
230
Storage Temperature
T
°C
°C
STG
Operating Junction Temperature
T
J
Lead Temperature (IR Reflow Soldering for >60 s @ >183°C), 10 s @ >215°C
Continuous Current per Pin
T
°C
SOLDER
V
0 to 10
-2.5 to 5.0
500
mA
DD
DSIxR
V
SUP
Thermal Resistance Junction to Ambient
Thermal Shutdown
R
45
°C/W
°C
JA
θ
T
155 to 190
SD
ESD Voltage (All Pins)
V
Human Body Model (Note 2)
Machine Model (Note 3)
V
±2000
±200
ESD1
VESD2
Notes
1. R= 0 Ω.
2. ESD1 performed in accordance with the Human Body Model (CZAP=100pF, RZAP=1500 Ω).
3. ESD2 performed in accordance with the Machine Model (CZAP=200 pF, RZAP=0 Ω).
33790
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY
ISUP Supply Current/Channel (Not Including IOUT
)
mA
I
–
–
1.35
5.0
3.25
9.00
DSIx0 = Idle Voltage, -100 mA ≤ IOUT ≤ 0 mA
DSIx0 = Output High Voltage, IOUT = 12 mA
SUPI
I
SUPH
I
DD Supply Current /Channel
I
–
0.5
1.0
mA
DD
BUS TRANSMITTER
VSUP to DSIxO ON Resistance (During Idle)
IOUT = -100 mA
R
Ω
DS(
)
on
–
–
10
Output High Voltage
DSIV
V
V
OH
DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA)
4.175
1.325
4.5
1.5
4.825
1.675
Output Low Voltage
DSIV
OL
DSIx0 (-15 mA ≤ IOUT ≤ 1.0 mA)
Output High-Side Current Limit (Note 4)
Output Low-Side Current Limit (Note 4)
Input Leakage
I
-100
110
–
–
-200
220
mA
mA
µA
CLH
I
CLL
DSI
IB
DSIxO When DSIxF Is High and DSIxS Is Low (0 V ≤ DSIxO ≤ Min (VSUP = 16.5 V))
-200
–
50
BUS RECEIVER
Return Current Threshold
I
-5.0
-6.0
-7.0
mA
RH
MICROCONTROLLER INTERFACE
Logic Input Thresholds DSIxS, DSIxF
V
1.10
–
–
2.20
VDD
V
V
IN(TH)
Output High Voltage
DSIxR Pin = -0.5 mA
V
OH
0.8 V
DD
*
Output Low Voltage
DSIxR Pin = 1.0 mA
V
I
V
OL
0.0
–
0.2 VDD
*
Internal Pull-Up for DSIxF
-100
10
–
–
-10
µA
µA
IL
Internal Pull-Down for DSIxS
I
100
IH
Notes
4. After 10 µs settling time (assured by design).
33790
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VSUP ≤ 25.0 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Characteristic
MICROCONTROLLER INTERFACE
Microcontroller Signal Cycle Time
Symbol
Min
Typ
Max
Unit
t
6.6
2.0
2.0
30
–
–
1000
667
667
36
µs
µs
µs
%
cyc
Microcontroller Signal Low Time
Microcontroller Signal High Time
Microcontroller Signal Duty Cycle for Logic Zero
Microcontroller Signal Duty Cycle for Logic One
Microcontroller Signal Slew Time (Note 5)
Frame Start to Signal Delay Time
Signal End to Frame End Delay Time
Rise Time (Note 5)
t
cycL
cycH
t
–
DC
33
66.7
–
Lo
DC
60.0
–
72.0
500
%
Hi
t
ns
µs
µs
ns
ns
slew
tDLY1
tDLY2
tRISE
tFALL
t
-0.1
t
t
+0.1
cyc
cyc
cyc
–
1.0
0
–
–
–
100
100
Fall Time (Note 5)
0
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate
tslew(FRAME)
V/µs
V/µs
µs
C ≤ 5.0 nF
3.0
3.0
6.0
4.5
10.0
8.0
Signal High to Low and Signal Low to High Slew Rate
tslew(SIGNAL)
C ≤ 5.0 nF
Data Valid (VSUPx = 25 V, CL ≤ 5.0 nF)
DSIxF, VIN(TH) to DSIxO = 5.3 V
DSIxS, VIN(TH) to DSIxO = 2.6 V
DSIxS, VIN(TH) to DSIxO = 3.4 V
DSIxF, VIN(TH) to DSIxO = 7.0 V
tDVLD1
tDVLD2
tDVLD3
tDVLD4
2.44
0.25
0.25
0.25
–
–
–
–
6.56
1.3
1.3
1.3
BUS RECEIVER
Receiver Delay Time
ns
tDRH
tDRL
–
–
400
400
750
750
I = 9.0 mA to DSIxR = 0.8 VDD
*
*
I = -1.0 mA to DSIxR = 0.2 VDD
Notes
5. Slew times and rise and fall times between 10% and 90% of output high and low levels.
33790
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tcyc
t
cyc
tDLY2
t
H
cyc
5.0 V
DSIxS
VIN(TH)
0 V
tRISE
t
L
cyc
tRISE
tDLY1
tFALL
5.0 V
DSIxF
VIN(TH)
0 V
t
DVLD4
t
(FRAME)
slew
tDVLD1
25 V
7.0 V
tDVLD3
t
(SIGNAL)
slew
DSIxO
5.0 V
4.5 V
tDVLD2
1.5 V
IOUT
6.0 mA
0 mA
tDRH
tDRL
5.0 V
DSIxR
0 V
Figure 2. Timing Characteristics
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33790 is designed to provide the interface between logic
current being above (Logic [1] out) the bus return logic [1]
current or below (Logic [0] out). The 33790 contains current
limiting of the bus outputs as required by the DSI Bus
specification and thermal shutdown to protect itself from
damage. Two independent DSI bus outputs are provided by the
IC.
and the DSI bus. It accepts signals with a typical 0 V to 5.0 V
logic level to control the state of the bus output (Idle Level, Logic
High Level, Logic Low Level, and High Impedance). It detects
the current drawn from the bus output during signaling and
outputs a 0 V to 5.0 V logic level corresponding to the bus
FUNCTIONAL DESCRIPTION
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Bus Driver and Receiver
The Wave-Shaper converts the 0 V to 5.0 V logic inputs from
DSIxF (frame) and DSIxS (signal) to a wave-shaped signal on
the DSIxO output, as shown in the timing diagrams in Figure 2,
page 7, and the truth table in Table 1. The Bus Current Sense
detects the current being drawn by the device(s) on the bus
during signalling (DSIxF=0). If the current is above a set level,
DSIxR will be high; otherwise, it is low.
Typically, the thermal shutdown occurs between 160°C and
170°C. If the junction temperature rises above this temperature,
the output drivers for DSIxO are disabled by the thermal
shutdown circuitry. The output drivers remain off until the
junction temperature decreases below approximately 155°C, at
which time the thermal shutdown circuitry turns off and the
outputs are re-enabled. Each DSIxO output has a unique
thermal sense and shutdown circuit, so a short on one channel
does not affect the other channel.
Table 1. DSI Bus Truth Table
TLIM
DSIxF
DSIxS
DSIR
DSIxO
0
0
1
1
0
1
0
1
0
0
0
0
Return Data
Low (1.5 V)
Charge Pump
Return Data
High (4.5 V)
The charge pump uses on-board capacitors to step the input
voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter/storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
0
0
High Impedance
Idle≥VSUP-0.5 V
X
X
1
1
High Impedance
Input Pull-Ups and Pull-Downs
The current for the idle state is from the supply connected to
SUP and this supply should not be current limited below
V
Internal current pull-ups are used on the DSIxF pins and pull-
downs on the DSIxS pins. If these pins are left unconnected,
their associated DSI bus will go to the unused (high impedance)
state.
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the VSUP voltage.
APPLICATIONS
The 33790 is intended for use in a DSI system. This device
supplies the interface between standard logic levels and the
voltage and current required for the DSI bus. Two independent
DSI busses are supported by this part. The 33790 does not
form the timing for the DSI bus. This is done by logic either
embedded in a microcontroller or by the MC68HC55, which
uses SPI commands and forms DSI protocol for
The pins from the MC68HC55 are made to line up with the
pins connecting to the 33790. This includes all the DSIxF,
DSIxS, and DSIxR pins.
A capacitor attached to CPCAP serves as a charge reservoir
for the gate drive charge pump. This circuit creates a voltage
that is higher than the source of the N-channel output transistor.
This allows turning on of the transistor enough to prevent any
significant voltage drop across it. The rest of charge pump
electronics are completely self-contained on the IC.
communications over the DSI bus.
33790
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PACKAGE DIMENSIONS
EG (Pb free)SUFFIX
DW SUFFIX
16-LEAD SOIC WIDE BODY
PLASTIC PACKAGE
CASE 751G-04
ISSUE D
M
0.25
B
2.65
A
2.35
0.25
0.10
10.55
10.05
8X
PIN'S
0.49
0.35
0.25
16X
6
NUMBER
M
T A B
1
16
PIN 1 INDEX
NOTES:
14X
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
10.45
10.15
1.27
4
A
A
3. DATUMS A AND B TO BE DETERMINED AT
THE PLANE WHERE THE BOTTOM OF THE
LEADS EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE
MOLD FLASH, PROTRUSION OR GATE
BURRS. MOLD FLASH, PROTRUSION OR
GATE BURRS SHALL NOT EXCEED
0.15mm PER SIDE. THIS DIMENSION IS
DETERMINED AT THE PLANE WHERE THE
BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
8
9
SEATING
PLANE
T
16X
7.6
7.4
B
0.1 T
5
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25mm PER SIDE.
THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE
LEADS EXIT THE PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT
CAUSE THE LEAD WIDTH TO EXCEED
0.62mm.
0.75
0.25
X45
0.32
0.23
1.0
0.4
7
0
SECTION A-A
33790
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NOTES
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NOTES
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