MC44463 [MOTOROLA]
REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER; 回放和多画面，画中画（ PIP ）控制器
| 型号： | MC44463 |
| 厂家： | 
MOTOROLA |
| 描述： | REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER |
| 文件： | 总8页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document from Analog Marketing
The MC44463 Picture–In–Picture (PIP) controller is a low cost member of
a family of high performance PIP controllers and video processors for
television. It is a follow–up to the MC44461 PIP, in which two additional
modes of operation have been added. A replay mode is provided, which
captures several seconds of the main picture for replay in four different
speeds. The capture time is programmable in four resolutions (ratio of
captured fields to total fields), which trade the number of fields captured to
the length of replay time. The second additional mode provides for multiple
small picture overlays from a second non–synchronized source. The number
of PIP images is 3 for the 1/9 screen area and 4 for the 1/16 screen area.
REPLAY AND MULTIPLE
PICTURE–IN–PICTURE
(PIP) CONTROLLER
SEMICONDUCTOR
TECHNICAL DATA
2
Like the MC44461 this is NTSC compatible, I C bus controlled and available
in the 56–pin shrink dip (SDIP) package.
The main features of the MC44463 are:
• Three PIP Functional Modes: Standard Single Active PIP Mode, Up to 8
Seconds of Capture and Replay Mode, and a 3 or 4 Multiple PIP Mode –
Vertical Stacked with 1 Active at Any One Time
• 4 Capture Resolutions – 1 out of 10, 1:8, 1:6, 1:4. 4 Playback Speeds =
1 Times Acquire Speed; 1/2; 1/4; 1/8
56
• Full 2 Frame Store for the Single PIP Removes the Rolling
Store/Playback Memory Interference – “Joint Line”
1
• External Memory for Replay and Multiple Modes: 4 Meg and 16 Meg
• Two NTSC CVBS Inputs – Switchable Main and PIP Video Signals
• Single NTSC CVBS Output Allows Simple TV Chassis Integration
• Two PIP Sizes; 1/16 and 1/9 Screen Area – Freeze Field Feature
• Variable PIP Position in 64–X by 64–Y Steps
B SUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
• PIP Border with Programmable Color
• Programmable PIP Tint and Saturation Control
• Automatic Main to PIP Contrast Balance
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
• Vertical Filter
MC44463B T = –65° to +150°C
SDIP
2
J
• I C Bus Control – No External Variable Adjustments Needed
• Operates from a Single 5.0 V Supply
• Economical 56–Pin Shrink DIP Package
Composite Video Simplified System Diagram
CV
CV
in
Tuner/IF
Video
Processor
R
G
B
CV
1
PIP
MC44463
4
Meg
Memory
Back Panel
Composite
Video Input
CV
2
IIC
This document contains information on a product under development. Motorola reserves the
right to change or discontinue this product without notice.
Motorola, Inc. 1996
Issue 1
MC44463
MAXIMUM RATINGS
Rating
Symbol
Value
–0.5 to +6.0
–0.5 to +6.0
–0.5,
Unit
V
Power Supply Voltage
Power Supply Voltage
Input Voltage Range
V
DD
CC
V
V
V
IR
V
V
DD
+ 0.5
Output Current
I
O
160
mA
Power Dissipation
Maximum Power Dissipation @ 70°C
Thermal Resistance, Junction–to–Air
P
1.3
59
W
°C/W
D
R
θJA
Junction Temperature (Storage and Operating)
T
J
–65 to +150
°C
NOTE: ESD data available upon request.
ELECTRICAL CHARACTERISTICS (V
= V
= 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
POWER SUPPLY
Total Supply (Pins 8, 15, 43 and 50)
Total I
–
110
160
mA
Supply
VIDEO
Composite Video Input (Pin 34 or 36)
CVi
–
–
–
–
–
–
–
1.0
2.0
1.0
6.0
10
–
–
–
–
–
–
Vpp
Vpp
Vdc
dB
Composite Video Output (Pin 49, Unterminated)
Video Output DC Level (Sync Tip)
Video Gain
–
–
Video Frequency Response (Main Video to –1.0 dB)
Color Bar Accuracy
–
MHz
deg
dB
–
±4.0
Video Crosstalk (@ 75% Color Bars)
Main to PIP
PIP to Main
–
–
–
55
55
–
–
Output Impedance
–
–
5.0
–
Ω
HORIZONTAL TIMEBASE
Free Run HPLL Frequency (Pin 16)
–
–
–
–
–
–
–
–
–
–
15734
±400
±4.0
1.0
–
–
–
–
–
Hz
Hz
ns
µs
µs
HPLL Pull–In Range
HPLL Jitter
Burst Gate Timing (from Trailing Edge Hsync, Pin 24)
Burst Gate Width
4.0
VERTICAL TIMEBASE
Vertical Countdown Window
–
–
–
–
232/296
31
–
–
H lines
Vertical Sync Integration Time
µs
ANALOG TO DIGITAL CONVERTER
Resolution
–
–
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
–
Bits
LSB
LSB
MHz
kHz
Integral Non–Linearity
±1
Differential Non–Linearity
+2/–1
1.0
ADC – Y Frequency Response @ –5.0 dB
ADC – U, V Frequency Response @ –5.0 dB
200
4.773
Sample Clock Frequency (4/3 F
)
MHz
SC
2
MOTOROLA ANALOG IC DEVICE DATA
MC44463
ELECTRICAL CHARACTERISTICS (continued) (V
= V
= 5.0 V, T = 25°C, unless otherwise noted.)
DD A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL TO ANALOG CONVERTER
Resolution
–
–
–
–
–
–
–
–
–
–
–
6
–
–
–
–
Bits
LSB
LSB
Deg
dB
Integral Non–Linearity
±1
Differential Non–Linearity
+2/–1
±10
±6.0
Tint DAC Control Range (in 64 Steps)
Saturation DAC Control Range (in 64 steps)
NTSC DECODER
Color Kill Threshold
–
–
–
–
–
–
–24/–16
±1.0
–
–
–
dB
dB
dB
Threshold Hysteresis
ACC (Chroma Amplitude Change, +3.0 dB to –12 dB)
PIP CHARACTERISTICS
±5.0
PIP Size
–
1/9 Screen Horizontal
1/9 Screen Vertical
1/16 Screen Horizontal
1/16 Screen Vertical
–
–
–
–
114
71
84
–
–
–
–
pels
lines
pels
lines
53
Border Size Horizontal
Border Size Vertical
–
–
–
–
–
–
–
–
–
–
3
2
–
–
–
–
–
pels
lines
MHz
%
Output PEL Clock (4 F
)
14.318
100
100
SC
Position Control Range Horizontal (% of Main Picture), 64 Steps
Position Control Range Vertical (% of Main Picture), 64 Steps
%
Figure 1. Representative Block Diagram
Decoder Clamp Caps
Filter PLL
ADC Mid–Ref
51
33
40
41
42
Filter
Tracking
28
31
Low Pass
Filter
Sync Sep
H PLL
36
34
H and V
Timebase
Video 1
Video 2
Input
Switch
Band Pass
Filter
Y
Y
6
1
2
3
4
5
Y
U V
6–Bit
ADC
Test Clock
37
49
NTSC
Decoder
Decoder ACC
Main Out
V
U
V
U
Clamp
6
H
in
3
V
in
PIP
Switch
SCL
Digital
Logic
6
57.28 MHz
0
°
90
°
38
39
7
Tint DAC
Sat DAC
SDA
Reset
Vert
Decoder Xtal
Decoder PLL
4X S/C
Osc + PLL
14.32 MHz
6
16 F
PLL
30
SC
6
Multi Test
16X S/C
Osc + PLL
44
45
NTSC
Encoder
3.0 MHz
LPF
Encoder Phase
Encoder ACC
U DAC
V DAC
Y DAC
Clamp
3.0 MHz
LPF
0°
90°
6
Y
U
V
4X S/C
Osc + PLL
Memory
Control
Logic
10 to 27
Memory
3.0 MHz
LPF
6
46
47
52 53 54
Encoder
PLL
Encoder
Xtal
Encoder Clamp Caps
This device contains approximately 300,000 active transistors.
3
MOTOROLA ANALOG IC DEVICE DATA
MC44463
Figure 2. Application Circuit
5.0 V 5.0 V
1.0 k
Horiz In
Vert In
I C Ser Cl
1.0 k
1.0 k
2
1.0 k
2
I C Ser Data
0.01
0.01
1
2
56
H
MC44463
N/C
N/C
in
470 k
55
54
53
52
51
50
49
48
47
46
45
44
43
V
5.0 V
in
3
SCL
Encoder V Cap
Encoder U Cap
Endoder Y Cap
ADC Mid Ref
0.01
0.01
2.2 µF
4
SDA
5
Reset
Test Clock
47 k
6
5.0 V
F
100
0.1
µ
7
16 F
Filter
Video Out V
CC
SC
(dig)
75
8
V
V
Video Out
Analog Gnd
DD
1000
100
Video Out
9
(dig)
SS
0.1
100 k
5.0 V
10
11
12
13
14
OEB
Encoder Xtal
Encoder PLL
Encoder ACC
Encoder Phase
12
X3
CASB
DQ2
DQ3
DQ0
DQ1
RWB
RASB
A9
1000
0.1
0.01
Analog V
CC
5.0 V
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Decoder V Cap
Decoder U Cap
Decoder Y Cap
Decoder PLL
Decoder Xtal
Decoder ACC
Video In 1
0.01
0.01
0.01
2700
68 k
A0
A1
A2
A3
A4
A5
A6
A7
A8
0.068
A0
5.0 V
A8
0.22
12
X2
A1
1
2
20
19
18
17
16
15
14
13
12
11
GN
A8
A7
A6
A5
A4
A2
A7
A6
A5
A4
0.1
CASN
DQ2
Video 1
Video 2
A3
Analog Gnd
Video In 2
3
A4
0.1
4
0.01
DQ3
A5
Filter PLL
5
Y
SS
A6
503 kHz Resonator
H PLL
75
75
X1
6
DQ0
DQ1
WN
V
1000
CC
A3
A7
A3
A2
A1
A0
7
A8
Multi Test
8
A2
A1
A0
Sync Sep
Sync In
9
RASN
A9
2.2 k
4.7
0.01
10
330
4.7 µF
MCM54400A–C
µF
62 k
2200
X1 – 503 kHz – Murata Erie CSB503F2 or equivalent
X2 – 14.31818 MHz – Fox 143–20 or equivalent
X3 – 14.31818 MHz – Fox 143–20 or equivalent
4
MOTOROLA ANALOG IC DEVICE DATA
MC44463
2
I C REGISTER DESCRIPTIONS
Base write address = 26h
Base read address = 27h
Test Mode/Main Vertical and Horizontal Polarity Register
Sub–address = 03h
Internal Test Mode Register (ITM0–2) – D0–D2
Sets the Multi Test Pin output to provide one of several
internal signals for test and production alignment. Also
controls the test memory address counter.
Read Register
There are two active bits in the single read byte available
from the MC44463 as follows:
Write Vertical Indicator (WVI0) – D7
When 0 indicates that the write operation specified by the
last I C command has been completed.
ITM (2:0)
000
Multi–Test I/O and Function
Input – Analog Test mode
Input – Digital Test mode
Output – Sync Detect
Output – PIP Switch
2
PIP Sync Detect Bit (PSD0) – D1
001
When 0 indicates that the PIP video H pulses are present
and the horizontal timebase oscillator is within acceptable
limits.
010
011
Write Registers
100
Output – PIP H Detect
Output – PIP V Detect
Output – PIP Clamp
Read Start Position/Write Start Position Registers
Sub–address = 00h
101
110
Write Raster Position Start Bits (WPS0–2) – D0–D2
Establishes the horizontal beginning of the PIP and its
black level measurement gate. This beginning may be varied
by approximately 3.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
111
Output – Main Clamp
Main vertical polarity select bit (MVP0) – D6
Selects polarity of active level of vertical reference input.
0 = positive going, 1 = negative going.
Main horizontal polarity select bit (MHP0) – D7
Selects polarity of active level of horizontal reference
input. 0 = positive going, 1 = negative going.
Read Raster Position Bits (RPS0–3) – D4–D7
Establishes the clamp gate position for the black level
reference for the main picture. This position may be varied by
approximately 5.0 µs. The position of this pulse may be
observed through the Multi Test Pin 30 (See Test Mode
Register Sub–address 03h).
PIP Freeze/PIP Size/Main and PIP Video Source Register
Sub–address = 04h
LIVE PIP Select Bits (LIVE_P0–1) – D0–D1
Selects which of the mutliple PIP pictures is the active
“live” one.
Pip Switch Delay/Vertical Filter Register
Sub–address = 01h
PIP Switch Delay Bits (PSD0–3) – D0–D3
LIVE_P (1:0)
1/16 Size
Top = LIVE
1/9 Size
Top = LIVE
Delays the start of PIP on time relative to the PIP picture.
These bits are used to center the PIP border and PIP picture
in the horizontal direction.
00
01
10
11
2nd from Top = LIVE
3rd from Top = LIVE
4th from Top = LIVE
2nd from Top = LIVE
3rd from Top = LIVE
3rd from Top = LIVE
Vertical Filter Bit (VFON) – D4
When the filter is activated (VFON = 1) a three line
weighted average is taken to provide the data stored in the
field memory.
PIP Freeze Bit (STIL0) – D4
When set to one, the most recently received field is
continuously displayed until the freeze bit is cleared.
Border Color Register
Sub–address = 02h
Border Color Bits (BC0–2) – D0–D2
PIP Size Bit (PSI90) – D5
Switches the PIP size between 1/16 main size (when 0)
and 1/9 main size (when 1).
These Bits control the color of the border. Note that when
using one of the saturated border colors it is possible to get
objectionable dot crawl at the edge of the border in some TVs
unless appropriate comb filtering is used in the TV circuitry.
Main Video Source Select Bit (MSEL0) – D6
Selects which video input will be applied to the PIP switch
as the main video out.
BC (2:0)
000
Border Color
PIP Video Source Select Bit (PSEL0) – D7
Selects which video input will be applied to the video
decoder to provide the PIP video.
Black
001
White 70%
No Border (clear)
No Border (clear)
Blue
010
MSEL/PSEL
Function
011
0
Video 1 Input to Main/
Video 1 Input to PIP
100
101
Green
1
Video 2 Input to Main/
Video 2 Input to PIP
110
Red
111
White
5
MOTOROLA ANALOG IC DEVICE DATA
MC44463
PIP On/PIP Blank Register
bits are set to a single value determined to be correct in the
Sub–address = 05h
application.
PIP On Bits (PON0–3) – D4–D3
PIP Acquire/Playback Register
When on (1) turns the corresponding PIP display on.
Sub–address = 0Bh
PIP Acquire Speed Bits (ACQ_SP0–1) – D0–D1
These select the speed of the video acquisition. This is
only active when RE_AQ = 1.
PON (3:0)
0000
1/16 Size
No PIP
1/9 Size
No PIP
0001
Top = On
Top = On
ACQ_SP (1:0)
Function
0010
2nd from Top = On
3rd from Top = On
4th from Top = On
2nd from Top = On
3rd from Top = On
3rd from Top = On
00
01
10
11
Acquire 1 Out of Every 4 Fields
Acquire 1 Out of Every 6 Fields
Acquire 1 Out of Every 8 Fields
Acquire 1 Out of Every 10 Fields
0100
1000
PIP Blanking Bits (PBL0–3) – D4–D7
When on (1) sets the corresponding PIP to black. If the
individual PIP is off, then it will be black when it is turned on.
PIP Save/Clear Bit (RE_AQ) –D2
This bit controls the save and clear function for the instant
replay. The bit value 1 is only effective when PON0–3 = 0000.
(No PIP display.)
PBL (7:4)
0000
Function
PIP Picture Normal
RE_AQ (2:2)
Function
0001
Top = Blanked (Set to Black)
0
1
Save Memory
Clear Reacquire
0010
2nd from Top = Blanked (Set to Black)
3rd from Top = Blanked (Set to Black)
4th from Top = Blanked (Set to Black)
0100
1000
PIP Playback Speed Bits (PB_SP0–1) – D4–D5
These bits control the relative playback speed, to the
acquired speed.
PIP X Position Register
Sub–address = 06h
PB_SP (5:4)
Function
X Position Bits (XPS0–5) – D0–D5
Moves the PIP start position from the left to the right
edge of the display in 64 steps. There is protection circuitry
to prevent the PIP from interfering with the main picture
sync pulses.
00
01
10
11
Playback at 1 x ACQ_SP Speed
Playback at 1/2 x ACQ_SP Speed
Playback at 1/4 x ACQ_SP Speed
Playback at 1/8 x ACQ_SP Speed
PIP Y Position Register
Sub–address = 07h
PIP Playback Control Bit (PB) – D6
This bit controls the start/stop of the instant replay
function.
Y Position Bits (YPS0–5) – D0–D5
Moves the PIP start position from the top to the bottom
edge of the display in 64 steps. There is protection circuitry to
prevent the PIP from interfering with the main picture sync
pulses.
PB (6:6)
Function
0
1
No Action
Instant Replay Activated
PIP Chroma Level Register
Sub–address = 08h
PIP Fill/Background/Free Run/Test Register
Sub–address = 0Ch
Chroma (C0–5) – D0–D5
The color of the PIP can be adjusted to suit viewer
preference by setting the value stored in these bits. A total of
64 steps varies the color from no color to maximum. This
control acts in conjunction with the auto phase control.
PIP Fill Bits (PIPFILL0–1) – D0–D1
May be used to fill the PIP with one of three selectable
solid colors
PIP Tint Level Register
PIPFILL (1:0)
Function
Sub–address = 09h
00
01
10
11
Normal
Red
Tint (T0–5) – D0–D5
An auto phase control compares the main color burst to
the internally generated pseudo color burst so that the tints
are matched. In addition to this, the tint of the PIP can be
varied ±10° in a total of 64 steps by changing the value of
these bits to suit viewer preference.
Green
Blue
Test Register Bits (INTC0 and MACR0) – D6–D7
When the FRUN is set to 1 the circuitry provides a
generated sync and displays a flat field that can be either
dark blue or gray determined by the BGND bit.
PIP Luma Delay Register
Sub–address = 0Ah
Y Delay (YDL0–2) – D0–D2
BGND (2:2)
Function
Since the Chroma passes through a bandpass filter and
the color decoder, it is delayed with respect to the Luma
signal. Therefore, to time match the Luma and Chroma these
0
1
Blue
50% White
6
MOTOROLA ANALOG IC DEVICE DATA
MC44463
2
I C REGISTER TABLE
Data Bit
Sub–
D7
D6
D5
RPS1
–
D4
RPS0
VFON
–
D3
D2
WPS2
PSD2
BC2
D1
WPS1
PSD1
BC1
D0
WPS0
PSD0
BC0
address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
RPS3
RPS2
–
PSD3
–
–
–
–
–
–
MHP0
MVP0
–
–
–
ITM2
–
ITM1
ITM0
PSEL0
MSEL0
PSI90
PBL1
XPS5
YPS5
C5
STIL0
PBL0
XPS4
YPS4
C4
–
LIVE_P1
PON1
XPS1
YPS1
C1
LIVE_P0
PON0
XPS0
YPS0
C0
PBL3
PBL2
PON3
XPS3
YPS3
C3
T3
PON2
XPS2
YPS2
C2
–
–
–
–
–
–
–
–
–
T5
T4
T2
T1
T0
–
–
–
–
YDL2
RE_AQ
BGND
YDL1
ACQ_SP1
PIPFILL1
YDL0
ACQ_SP0
PIPFILL0
–
PB
MACR
PB_SP1
FRUN
PB_SP0
–
–
INTC
–
Function Control of the MC44463
Replay PIP (RPIP) Operation
There are three modes of operation; Single PIP, Multiple
PIP and Replay. These are enabled by setting specific
register bits in the I C register set.
In sequence, the Capture Ready mode must be first
activated, allowing up to 8 seconds of fill memory with the
desired video stream. Then the Capture mode must be set,
disabling further write to memory. The Capture data may be
re–displayed at any time afterword.
2
Single PIP (SPIP) Operation
Register 0Bh : D6 –> 0
Capture Ready
Register 05h : D0–D7 –> 01h
Multiple PIP (MPIP) Operation
Register 05h : D0–D3 –> 07h or 0Fh
Register 04h : D0–D1 –> 0 to 3
Register 0Bh : D6 –> 0
Register 05h : D0–D3 –> 0
Register 0Bh : D6 –> 0, D2 –> 1, D0–D1 –> 0 to 3
Capture
Register 0Bh : D6 –> 1, D2 –> 0, D4–D5 –> 0 to 3
Register 05h: D0 –> 1
Register 0Ch : D5 –> 1, D2 –> 0 or 1 (Optional)
7
MOTOROLA ANALOG IC DEVICE DATA
MC44463
OUTLINE DIMENSIONS
B SUFFIX
PLASTIC PACKAGE
CASE 859–01
(SDIP)
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
-A-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
56
29
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
2.065
0.560
0.200
0.022
MIN
51.69
13.72
3.94
0.36
0.89 BSC
MAX
52.45
14.22
5.08
-B-
2.035
0.540
0.155
0.014
1
28
L
0.56
0.035 BSC
F
0.032
0.070 BSC
0.300 BSC
0.008
0.115
0.046
0.81
1.778 BSC
7.62 BSC
0.20
2.92
1.17
H
G
H
J
K
L
C
0.015
0.135
0.38
3.43
0.600 BSC
15
0.040
15.24 BSC
15
0.51 1.02
-T-
SEATING
PLANE
M
N
0°
°
0°
°
K
0.020
N
G
M
F
E
D 56 PL
J 56 PL
M
S
M
S
B
0.25 (0.010)
T
A
0.25 (0.010)
T
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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