MC44871DTB [MOTOROLA]
PLL TUNING CIRCUIT WITH HIGH SPEED I2C BUS AND 30 V TUNING SUPPLY; 高速I2C总线30 V调谐电源PLL调谐电路
| 型号： | MC44871DTB |
| 厂家： | 
MOTOROLA |
| 描述： | PLL TUNING CIRCUIT WITH HIGH SPEED I2C BUS AND 30 V TUNING SUPPLY |
| 文件： | 总12页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC44871/D
PLL TUNING CIRCUIT
The MC44871 is a tuning circuit for TV, VCR and Multimedia tuner
applications. This device contains on one chip all the functions required for
PLL control of a VCO. This integrated circuit also contains a high frequency
prescaler and thus can handle frequencies up to 1.3 GHz.
2
WITH HIGH SPEED I C BUS
AND 30 V TUNING SUPPLY
The MC44871 has an integrated dc/dc converter to generate the 30 V
supply voltage for the tuning amplifier on the chip. A tuner using the
MC44871 does not require an external 30 V supply.
SEMICONDUCTOR
TECHNICAL DATA
2
The MC44871 is controlled by a I C bus, and has a chip address function.
The MC44871 data format is the same as the MC44818.
The MC44871 is manufactured on a single silicon chip using Motorola’s
high density bipolar process, MOSAIC (Motorola Oxide Self Aligned
Implanted Circuits).
16
• The Pin Called V
CC2
for the MC44818 is Now Called CP (Charge
Pump). This Pin is the Output of the DC/DC Converter; a 1.0 nF
Capacitor Replaces the Need for an External 30 V Supply
1
2
• High Speed I C Bus (up to 800 kHz)
2
• I C Bus Read Mode for Lock Detector and AFC Level
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F
• HF Input is Balanced
• MC44871 has Three PNP High Current (30 mA) Band Buffers (B0, B1,
(TSSOP–16)
B2) and One NPN Low Current (5.0 mA) Band Buffer (B4)
• V
Internally Supplies PNP Band Buffers
CC
• The Tuning Voltage is Generated Through an External Pull–Up
Resistor (750 kΩ)
PIN CONNECTIONS
(16 Pin TSSOP)
• Less Phase Comparator Output Current
• Single 5.0 V Supply Operation
V
Amp In
Xtal
1
2
3
4
5
6
7
8
16
15
14
13
12
11
TUN
CP
MOSAIC is a trademark of Motorola, Inc.
HF1
HF2
Gnd
B2
SCL
SDA
ADD
V
CC
B1
10 ADC
B0
9
B4
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
(Top View)
MC44871DTB
T
A
= –20° to +85°C
TSSOP–16
This document contains information on a new product. Specifications and information herein
Motorola, Inc. 1998
Rev 1
are subject to change without notice.
MC44871
Figure 1. Representative Block Diagram
V
TUN
C4
V
R2
C3
R1
Bands Out
C1
C2
V
CP
CC
TUN
5.0 V 11
2
9
6
7
8
1
DC/DC
Converter
16
F
out
B4 B2 B1 B0
Buffers
Amp In
Test
Logic
V
ref
F
ref
Operational
Amplifier
Latches
DTB1
T13
Gnd
T14
5
Phase
Comp
T10, T11
P–On
Reset
DTB2
POR
Latches
F
out
F
ref
6
SDA
SCL
ADD
4
512/1024
13
14
12
CLO
Data
2
Shift Register
15 Bit
I C Bus
Receiver
Ref
Divider
15
RL
DTF
Latches A
15
3.2 or 4.0 MHz
Osc
Xtal
Latches B
ADC
ADC
TDI
10
Preamp
÷
8
HF1
HF2
Program Divider
15 Bit
3
4
Latch Control
DTS
Prescaler
F
out
This device contains 3,204 active transistors.
Approximate values of the external components for generation of the tuning voltage are:
C1 = 1.0 nF
R1 = 750 kΩ (560 kΩ minimum)
C4 = 330 pF
Charge Pump filter capacitor
Pull–up resistor
V
filter capacitor
TUN
Loop filter
C2 = 47 nF, C3 = 22 nF, R2 = 39 kΩ
These component values depend on the application.
2
MOTOROLA ANALOG IC DEVICE DATA
MC44871
MAXIMUM RATINGS (Maximum ratings are those values beyond which
permanent damage to the device may occur. Exposure to those limits may also affect device
reliability; T = 25°C, unless otherwise noted.)
A
Rating
Pin
11
Value
Unit
V
Power Supply Voltage (V
Storage Temperature
)
6.0
CC
–
–65 to +150
°C
°C
V
Operating Temperature Range
–
–20 to +85
Operational Amplifier Output Voltage
RF Input Level 80 MHz to 1.3 GHz
NPN Band Buffer ”Off” Voltage
1
40
3, 4
9
1.5
Vrms
V
10
NPN Band Buffer ”On” Current
9
15
mA
V
PNP Band Buffer “Off” Voltage
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
6.0
50
PNP Band Buffer “On” Current
mA
–
PNP Band Buffer – Short Circuit Duration (Note 1)
Continuous
10
Band Buffer Operation at 40 mA
all PNP Buffers “On”
s
NOTES: 1. At V
= 5.0 V and T = –20° to +80°C one buffer “On” only.
A
CC
2. ESD data available upon request.
ELECTRICAL CHARACTERISTICS (Parameter Type: A–100% Tested, B–100% Correlation Tested, C–Characterized on
Samples, D–Design Parameter, V = 5.0 V, T = 25°C, unless otherwise specified, 750 kΩ pull–up resistor between CP [Pin2] and
CC
A
V
TUN
[Pin 1].)
Characteristic
Pin
Min
Typ
Max
Unit
Type
V
CC
Supply Voltage Range
11
4.5
5.0
5.5
V
A
V
Supply Current (All Buffers “Off”)
–
–
–
35
40
80
45
50
90
A
B
B
CC
One Buffer “On” when Open
One Buffer “On” at 40 mA
11
mA
PNP Band Buffer B0, B1, B2 Leakage Current when “Off”
PNP Band Buffer B0, B1, B2 Saturation Voltage when “On” at 30 mA
NPN Band Buffer B4 Leakage Current when “Off”
NPN Band Buffer ”Off” Voltage
6, 7, 8
–
–
0.01
200
0.01
–
1.0
500
1.0
5.5
100
1.6
4.05
15
µA
mV
µA
V
A
B
A
D
A
A
D
A
A
A
A
A
6, 7, 8
9
9
–
0
NPN Band Buffer B4 Saturation Voltage when “On” at 1.0 µA
NPN Band Buffer B4 Voltage when ”On” @ 5.0 mA
Reference Oscillator Frequency Range
9
–
50
mV
V
9
–
1.2
3.2
0
15
16
16
16
2
3.15
–15
12
2.0
28
–
MHz
nA
µA
µA
V
Phase Comparator 3–State Current
Phase Comparator Output Current – High Value
Phase Comparator Output Current – Low Value
DC–DC Converter Output Voltage, Sourcing 50 µA
DC–DC Converter Maximum Current, Output Short Circuited
20
28
6.0
31
10
34.5
350
2
200
µA
DC–DC Converter setting time from VCC >4.5 V to DC–DC Converter
Voltage > 28 V @ Load = 750 kΩ/1.0 nF
2
–
–
25
ms
C
Operational Amplifier Internal Reference Voltage (V
Operational Amplifier Input Current
)
–
16
–
1.3
–15
100
0.3
–
1.9
0
2.5
15
–
V
nA
–
A
A
A
D
D
D
ref
Operational Amplifier DC Open Loop Gain
300
–
Operational Amplifier Gain Bandwidth Product (CL = 1.0 nF)
Operational Amplifier Low Output Voltage, Sinking 50 µA
Oscillator – Negative Resistance
–
–
MHz
V
16
15
0.2
–
0.4
–
1.0
kΩ
3
MOTOROLA ANALOG IC DEVICE DATA
MC44871
PIN FUNCTION DESCRIPTION (see Figure 1)
Description
Pin
1
Symbol
V
TUN
CP
Operational amplifier output which provides the tuning voltage
DC–DC Converter output (Charge Pump)
Symmetrical HF inputs
2
3, 4
5
HF1, HF2
Gnd
Ground
6, 7, 8
9
B2, B1, B0
B4
PNP Band Buffer outputs
NPN Band Buffer output
10
11
ADC
Three bit ADC for Automatic Frequency Tuning, readable through the bus
Positive supply of the circuit (5.0 V)
Chip address function
V
CC
12
13
14
15
16
ADD
SDA
2
I C bus Data Input/Output
2
SCL
I C bus Clock
Xtal
Crystal Oscillator (3.2 MHz or 4.0 MHz)
Operational amplifier input
Amp In
HF INPUT SENSITIVITY AND OVERLOAD CHARACTERISTICS (V
CC
= 5.0 V, T = 25°C.) (See Figure 2.)
A
Characteristics
Pin
3, 4
3, 4
3, 4
3, 4
3, 4
Min
Typ
1.6
–
Max
Unit
V
Type
A
DC Bias (Internal)
80–150 MHz
–
–
10
5.0
10
50
315
315
315
315
mVrms
mVrms
mVrms
mVrms
C
150–600 MHz
600–950 MHz
950–1300 MHz
–
C
–
C
–
C
Figure 2. HF Sensitivity Test Circuit
Figure 3. Typical HF Sensitivity Performance
(V = 5.0 V, Temperature = 25°C)
CC
10
Bus
Bus Controller
0
–10
–20
–30
–40
–50
–60
Guaranteed Sensitivity Performance
13
14
V
= 5.0 V
11
4
CC
MC44871
1.0 nF
HF1
3
Gnd
5
B0
8
B1
7
B2
6
B4
9
HF Generator
HF Out Gnd
1.0 nF
1.0 k
Ω 1.0 kΩ 1.0 kΩ
50
Ω
Cable
Counter
In
50
Ω
0
200
400
600
800
1000
1200
1400
FREQUENCY (MHz)
NOTE: 1. Device is in test mode. B1, B2 are “On” and B0, B4 are “Off”.
Sensitivity is level of HF generator on 50 Ω load.
4
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Figure 4. Pin Circuit Schematic
50
10 k
2.0 k
20 V
16 Amp In
V
1
TUN
Negative input of operational
amplifier and phase detector
charge pump output
Operational amplifier
output which provides
the tuning voltage
20 V
20 V
100
32 V 6.0 k
Ω
15 Xtal
Crystal oscillator
(3.2 MHz or 4.0 MHz)
CP 2
Converter output
(Charge Pump)
1.5 k
5.0 V
20 V
20 V
1
2
5.0 V
5.0 V
V
CC
96 k
6
5.0 V
132 k
500
1/2 V
14 SCL
CC
2
Clock input (I C bus)
20 V
96 k
2.0 k
2.0 k
1.2
… 1.8 V
HF1 3
V
Inputs to
presealer
CC
96 k
132 k
500
1/2 V
13 SDA
CC
HF2 4
2
Data input/output (I C bus)
20 V
96 k
ACK
V
CC
Gnd 5
Circuit ground
150 k
10 k
12 ADD
Chip Address
50 k 20 V
V
CC
11 V
CC
Positive supply of the
circuit (5.0 V)
5.0 V
5.0 V
“On”/“Off”
“On”/“Off”
“On”/“Off”
B2 6
20 V
20 V
20 V
10 k
20 V
200
20 V
10 ADC
Three bit control for AFC
PNP Band
Buffers
B1 7
9 B4
NPN Buffer
V
CC
B0 8
“On”/“Off”
5
MOTOROLA ANALOG IC DEVICE DATA
MC44871
2
2
HIGH SPEED I C BUS (The circuit is controlled by a I C bus with a Serial Data [SDA], Serial Clock [SCL], Chip Address
2
Control [ADD] inputs. The device I C bus has a read mode [odd addresses] and a write mode [even addresses].
ELECTRICAL CHARACTERISTICS (V
= 5.0 V, T = 25°C, unless otherwise specified.)
A
CC
Characteristic
Pin
Symbol
Min
Typ
–
Max
10
Unit
µA
V
Type
A
SDA/SCL Output Current at 0 V
SDA/SCL Low Input Level
SDA/SCL High Input Level
13, 14
13, 14
13, 14
13, 14
13, 14
–
V
IL
–
–
1.5
–
B
V
IH
3.0
–5.0
0
–
V
B
SDA/SCL Input Current for Input Level from 0.4 V to 0.3 V
SDA/SCL Input Level
0
5.0
µA
V
C
CC
–
V
CC
0.3
+
D
ADD Input Level
12
–0.01
–
1.1V
D
CC
V
CC
SDA/SCL Capacitance
13, 14
13
C
–
–
0.3
–
10
1.0
1.5
pF
V
C
A
C
i
SDA Low Output Level (sinking 3.0 mA)
SDA Low Output Level (sinking 15 mA)
–
–
13
V
TIMING CHARACTERISTICS
Characteristic
Pin
14
–
Symbol
Min
0
Typ
–
Max
800
–
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Type
C
Bus Clock Frequency
Bus Free Time Between Stop and Start
Setup Time for Start Conditions
Hold Time for Start Condition
Data Setup Time
T
buf
200
500
500
0
–
C
–
T
–
–
C
su;sta
hd;sta
–
T
–
–
C
–
T
–
–
C
su;dat
Data Hold Time
–
T
0
–
–
C
hd;dat
Setup Time for Stop Condition
Hold time for Stop Condition
Acknowledge Propagation Delay
SDA Fall Time at 3.0 mA sink I and 130 pF Load
SDA Fall Time at 3.0 mA sink I and 400 pF Load
SDA/SCL Rise Time
–
T
500
500
–
–
–
C
su;sto
–
T
–
–
C
hd;sto
T
–
300
50
80
300
300
50
C
ack;low
13
–
–
C
13
–
–
C
13, 14
13, 14
13,14
–
–
C
SCL Fall Time
–
–
C
Pulse Width of Spikes Suppressed by the Input Filter
T
sp
–
–
C
Timings Definition
T
buf
Stop
Start
Stop
ACK
Start
Chip address
SDA
SCL
SDA
SDA
SCL
SCL
T
T
T
T
T
T
T
ack:low
su;sta
hd;sto
su;sto hd;sta
su;dat hd;dat
Levels Definition
V
CC
V
IH
Not Defined
V
IL
0 V
6
MOTOROLA ANALOG IC DEVICE DATA
MC44871
2
Figure 5. High Speed I C Compatible Bus Data Format
1
2
3
4
5
6
7
8
9
10
18
19
SCL
SDA
STA
Chip Address ($C2)
First Byte
Stop
ACK
ACK
ACK
2 or 4 Data Bytes
2
I C Write Mode Format and Bus Receiver
ignored. If five or more data bytes are received, the fifth and
following ones are ignored, and the last acknowledge pulse is
sent at the end of the fourth data byte.
The incoming information, consisting of a chip address
2
byte followed by two or four data bytes, is treated in the I C
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information. If the function
bit is logic “1”, the two following bytes contain control and
band information. The first data byte, after the chip address,
may be byte CO or byte FM. The two bytes of frequency
information are preceeded by a logic “0”.
bus receiver. The definition of the permissible bus protocol is
shown below:
1_STA CA CO BA FM FL STO
2_STA CA FM FL CO BA STO
3_STA CA CO BA STO
4_STA CA FM FL STO
STA = Start Condition
Chip Address
CA = Chip Address Byte
CO = Control Information
BA = Band Information
Even addresses are for write mode, and odd addresses
are for read mode. Chip address is programmable by Pin 12
(ADD).
FM = Frequency Information with MSB
FL = Frequency Information with LSB
STO = Stop Condition
ADD Pin 12
Address (HEX.)
C0/C1
–0.01 V
to 0.1 V
CC
CC
0.2 V
to 0.3 V
(or Open)
C2/C3
Figure 5 shows the five bytes of information that are
needed for circuit operation: the chip address, two bytes of
control and information, and two bytes of frequency
information.
CC
CC
0.4 V
0.8 V
to 0.7 V
C4/C5
CC
CC
CC
CC
to 1.1 V
C6/C7
After the chip address, two or four data bytes may be
received: if three data bytes are received, the third one is
7
MOTOROLA ANALOG IC DEVICE DATA
MC44871
The Two Permissible Protocols with Five Bytes
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
CO_Control Information
BA_Band Information
1
T14
X
T13
X
T12
B4
T11
X
T10
B2
T9
B1
T8
B0
ACK
ACK
X
FM_Frequency Information
FL_Frequency Information
0
N14
N6
N13
N5
N12
N4
N11
N3
N10
N2
N9
N1
N8
N0
ACK
ACK
N7
CA_Chip Address
1
1
0
0
0
0/1
0/1
0
ACK
FM_Frequency Information
FL_Frequency Information
0
N14
N6
N13
N5
N12
N4
N11
N3
N10
N2
N9
N1
N8
N0
ACK
ACK
N7
CO_Control Information
BA_Band Information
1
T14
X
T13
X
T12
B4
T11
X
T10
B2
T9
B1
T8
B0
ACK
ACK
X
2
I C Read Mode Format
The incoming information consists of the chip address
byte in read mode (odd address). The device then answers
with an acknowledge followed by a byte containing lock and
ADC information. There is no ACK pulse sent after this byte.
1_STA
ADC_LO =
CA ADC_LO
ADC and Lock information
2
I C Read Format
CA_Chip Address
1
1
1
0
0
0
0/1
0/1
1
ACK
ADC_LO
LO
X
X
X
AD2
AD1
AD0
(no ACK)
Definition of the Bits for Test and Features
Bits B0, B1, B2: Control the PNP Band Buffers
Bit T10, T11: Control the Reference Divider
B0, B1, B2 = 0
= 1
Buffer is “Off”, Output Low
Buffer is “On”, Output High
T10
0
T11
0
Divider Ratio
512
0
1
1024
1024
512
Bit B4: Controls the NPN Band Buffer
1
0
B4 = 0
= 1
Buffer is “Off”, Output High
Buffer is “On”, Output Low
1
1
Bit T9, T12: Control the Phase Comparator
Bit T8: Controls the Operational Amplifier Output
T9
0
T12
0
Function
Upper Source Only
T8
T8 = 0
= 1
Operation
Operational Amplifier Normal Operation
0
1
Lower Source Only
Normal Operation
High Impedance
Output State of Operational Amplifier
Switched Off
1
0
Output Pulls High through External Resistor
1
1
8
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Bit T13: Switches the Band Buffer Output to Test Mode
OPERATING DESCRIPTION
Introduction
T13 = 0
= 1
Normal Operation
Test Mode: F Out at B2 F
A representative block diagram and typical system
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Out at B1
by2
ref
In the test mode, B2 and B1 have to be ON (B2=B1=1).
isthereferencefrequency. F istheoutputfrequencyof
the programmable divider divided–by–2.
F
ref
by2
Bit T14: Controls the Charge Pump Current
T14 = 0
= 1
Pump Current 5.0 µA
Pump Current 20 µA
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
Bit AD2, AD1, AD0: Indicate the ADC Pin Analog Level
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N0
ADC Input Voltage
0 to 0.18 V
AD2
AD1
AD0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
CC
Maximum Ratio 32767
Minimum Ratio 256
0.18 to 0.34 V
N0 … N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
CC
CC
CC
0.34 to 0.5 V
0.5 to 0.66 V
0.66 to 0.82 V
CC
CC
The Prescaler
0.82 to 1.0 V
The divide–by–8 prescaler has a preamplifier which
guarantees high input sensitivity.
Bit LO: Indicates the Status of Lock Detetector
The Phase Comparator
LO = 0
LO = 1
PLL Status Not Locked
PLL Status Locked
The phase comparator is both phase and frequency
sensitive and has very low output leakage current in the high
impedance state.
The Operational Amplifier
Figure 6. Equivalent Circuit of the Integrated
PNP Band Buffers
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
output (Pin 1) needs an external 750 kΩ pull–up resistor (560
kΩ minimum). This minimum value is defined by the charge
pump output current capability.
V
CC
Saturation Voltage
0.2 V Typical
0.5 V Max
I
B
I
The Oscillator
SUB
“On”/“Off”
The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground
in series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 15 has low amplitude and low harmonic
distortion.
30 mA (40 mA
at 0 to 80°C)
Out
B0 B2
I
I
I
+ I
SUB
= 5.5 mA Typical
= Base Current
= Substrate Current of PNP
…
B
B
SUB
Power Dissipation
The typical power dissipation of the circuit is about
200 mW (V
= 15 V with external pull–up of 560 kΩ, one
Figure 7. Equivalent Circuit of the Integrated
NPN Band Buffer
TUN
buffer “On” at 30 mA). It is calculated with the following
formula:
I
B1
V
= 5.0 V
Out B4
CC
200
V
V
Pin2
560 k
TUN
PD
V
x I
V
x V
CC
CC
TUN
I
B2
B3
Protection 20...25 V
x I
buffer
1.2 V typ
@ 5.0 mA
sat
Out
I
32 – 15
(
)
Example: 5 x 38
x 15
5
5.6 x 10
197 mW
”On”/”Off”
(
)
0.20 x 30
I
I
+ I
+ I
= 0.5 mA Typ
B3
B1
B
B2
= Base Current
9
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Figure 8. Typical Tuner Application
IF
External Switching
UHF
VHF
B III
8
7
6
9
10
ADC
Mixer
B0
B1
B2 B4
Antenna
Filter
14
13
12
SCL
SDA
ADD
Bus
Rec
MC44871
B. P. Filter
1.0 nF
HF1
3
F
osc
15
Xtal
Program
Divider
Osc &
Ref Div
÷8
1.0 nF
C
Xtal
4
HF2
3.2/4.0 MHz
V
11
Phase
Comp
CC
5.0 V
V
Oscillator
ref
CP
5
2
1
16
Gnd
C1
R1
AGC
V
TUN
R2
C3
C4
(Note 1)
C2
NOTES: 1. 330 pF minimum is required for stability.
2. Approximate values of the external components for generation of the tuning voltage are:
C1 = 1.0 nF
Charge Pump filter capacitor
Pull–up resistor
VTUN filter capacitor
Loop Filter
R1 = 750 k
C4 = 330 pF
C2 = 47 nF
C3 = 22 nF
Ω (560 kΩ minimum)
Loop Filter
R2 = 39 k
Ω
Loop Filter
These component values depend on the application.
DC–DC Converter Characteristics
The dc–to–dc converter block generates the 30 V supply
Figure 9. Typical Charge Pump Output Current
voltage on the chip from V . Pin 2 only needs an external
34
CC
capacitor (1.0 nF) instead of an external 30 V supply. The
charge pump switching frequency is taken from the oscillator.
Typical charge pump output current capability at 25°C is
shown in Figure 9.
32
30
28
26
24
V
= 5.5 V
CC
V
= 5.0 V
CC
V
= 4.5 V
CC
22
20
0
20
40
60
80
100
120
CURRENT (µA)
10
MOTOROLA ANALOG IC DEVICE DATA
MC44871
OUTLINE DIMENSIONS
DTB SUFFIX
PLASTIC PACKAGE
CASE 948F–01
(TSSOP–16)
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
S
0.15 (0.006) T
U
K
K1
NOTES:
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2
3
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
B
–U–
SECTION N–N
L
J
4
5
PIN 1
IDENT.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
6
7
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
–V–
N
F
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
0.193
0.169
–––
0.002
0.020
DETAIL E
–W–
C
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
–T–
D
G
K1
L
6.40 BSC
0.252 BSC
M
0
8
0
8
11
MOTOROLA ANALOG IC DEVICE DATA
MC44871
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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MC44871/D
◊
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