MC54HC165JD [MOTOROLA]
Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDIP16, 620-09;
| 型号： | MC54HC165JD |
| 厂家： | 
MOTOROLA |
| 描述： | Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, Complementary Output, CMOS, CDIP16, 620-09 移位寄存器 |
| 文件： | 总10页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
High–Performance Silicon–Gate CMOS
The MC54/74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
16
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
1
Low Input Current: 1 µA
ORDERING INFORMATION
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
MC54HCXXXAJ
Ceramic
Plastic
SOIC
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
•
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
TSSOP
LOGIC DIAGRAM
11
A
12
PIN ASSIGNMENT
B
9
7
13
Q
Q
SERIAL SHIFT/
H
SERIAL
DATA
OUTPUTS
C
D
E
1
2
16
15
V
CC
PARALLEL LOAD
PARALLEL
DATA
INPUTS
14
3
CLOCK
CLOCK INHIBIT
H
E
F
3
4
5
6
7
8
14
13
12
11
10
9
D
C
B
A
4
5
F
G
H
G
H
6
PIN 16 = V
CC
PIN 8 = GND
SERIAL
DATA
INPUT
10
S
A
Q
S
A
H
1
SERIAL SHIFT/
PARALLEL LOAD
GND
Q
H
2
CLOCK
15
CLOCK INHIBIT
FUNCTION TABLE
Inputs
Internal Stages
Output
Serial Shift/
Clock
Parallel Load
Inhibit
Clock
S
A
A – H
Q
Q
Q
H
Operation
A
B
L
X
X
X
a … h
a
b
h
Asynchronous Parallel Load
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An
An
Gn
Gn
Serial Shift via Clock
H
H
L
L
L
H
X
X
L
H
Q
Q
Q
Q
An
An
Gn
Gn
Serial Shift via Clock Inhibit
H
H
X
H
H
X
X
X
X
X
No Change
Inhibited Clock
No Clock
H
L
L
X
X
No Change
X = don’t care
Q
– Q
= Data shifted from the preceding stage
Gn
An
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
10/95
REV 0
Motorola, Inc. 1995
MC54/74HC165A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
IL
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
|I
|
20 µA
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
IL out
out
out
MOTOROLA
2
MC54/74HC165A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
V
OL
Maximum Low–Level Output
Voltage
V
V
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
in
IH IL
|I
|
20 µA
out
V
in
= V or V
IH
|I
|I
|I
|
|
|
2.4 mA
4.0 mA
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
IL out
out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
4
40
160
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
f
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
3.0
4.5
6.0
10
15
30
50
9
8
MHz
max
14
28
45
12
25
40
t
t
t
t
,
Maximum Propagation Delay, Clock (or Clock Inhibit) to Q or Q
H
2.0
3.0
4.5
6.0
110
36
22
125
45
26
160
60
32
ns
ns
ns
ns
pF
PLH
H
t
(Figures 1 and 8)
PHL
19
23
28
,
Maximum Propagation Delay, Serial Shift/Parallel Load to Q or Q
H
(Figures 2 and 8)
2.0
3.0
4.5
6.0
85
57
25
19
96
63
29
23
106
71
32
PLH
H
t
PHL
27
,
Maximum Propagation Delay, Input H to Q or Q
H
2.0
3.0
4.5
6.0
110
36
22
125
45
26
160
60
32
PLH
H
t
(Figures 3 and 8)
PHL
19
23
28
,
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
t
THL
19
C
Maximum Input Capacitance
—
10
10
10
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Package)*
pF
40
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
3
MOTOROLA
MC54/74HC165A
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
25 C
Unit
85 C
125 C
t
t
t
t
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
su
su
su
su
19
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
t
t
t
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
h
h
h
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
t
Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
rec
19
t
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
w
w
19
t
Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
4
MC54/74HC165A
PIN DESCRIPTIONS
INPUTS
applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are asynchro-
nously entered in parallel into the internal flip–flops when the
Serial Shift/Parallel Load input is low.
Clock, Clock Inhibit (Pins 2, 15)
Clock inputs. These two clock inputs function identically.
Either may be used as an active–high clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock input is high.
The shift register is completely static, allowing Clock rates
down to DC in a continuous or intermittent mode.
SA (Pin 10)
Serial Data input. When the Serial Shift/Parallel Load input
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.
OUTPUTS
CONTROL INPUTS
Q , Q (Pins 9, 7)
Serial Shift/Parallel Load (Pin 1)
H
H
Data–entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is
Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.
5
MOTOROLA
MC54/74HC165A
SWITCHING WAVEFORMS
t
t
f
r
V
CC
CLOCK
OR CLOCK INHIBIT
90%
50%
t
w
GND
10%
V
CC
SERIAL SHIFT/
PARALLEL LOAD
t
w
50%
PLH
50%
PHL
GND
1/f
max
t
t
t
t
PHL
PLH
90%
50%
10%
Q
OR Q
H
50%
Q
OR Q
H
H
H
t
t
THL
TLH
Figure 1. Serial–Shift Mode
Figure 2. Parallel–Load Mode
VALID
50%
V
CC
t
t
f
r
INPUTS A–H
V
CC
90%
INPUT H
GND
50%
GND
10%
t
t
su
h
t
t
PHL
PLH
V
CC
90%
50%
10%
SERIAL SHIFT/
PARALLEL LOAD
Q
OR Q
H
H
GND
t
t
THL
TLH
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)
Figure 3. Parallel–Load Mode
Figure 4. Parallel–Load Mode
V
VALID
50%
CC
SERIAL SHIFT/
PARALLEL LOAD
50%
V
CC
INPUT S
A
GND
GND
t
t
su
h
t
t
h
V
su
CC
CLOCK
OR CLOCK INHIBIT
V
50%
CC
CLOCK
50%
GND
OR CLOCK INHIBIT
GND
Figure 5. Serial–Shift Mode
Figure 6. Serial–Shift Mode
TEST POINT
CLOCK 2 INHIBITED
OUTPUT
DEVICE
UNDER
V
CC
CLOCK INHIBIT
50%
GND
C *
L
TEST
t
t
rec
su
V
CC
CLOCK
50%
GND
* Includes all probe and jig capacitance
Figure 7. Serial–Shift, Clock–Inhibit Mode
Figure 8. Test Circuit
MOTOROLA
6
MC54/74HC165A
EXPANDED LOGIC DIAGRAM
A
B
C
F
G
H
11
12
13
4
5
6
SERIAL SHIFT/
PARALLEL LOAD
1
9
Q
H
10
7
SERIAL DATA
D Q
D Q
D Q
D
Q
D
Q
D Q
Q
H
A
B
C
F
G
H
INPUT S
A
C
C
C
C
C
C
C
C
C
C
C C
2
CLOCK
CLOCK
INHIBIT
15
TIMING DIAGRAM
CLOCK
CLOCK INHIBIT
S
A
SERIAL SHIFT/
PARALLEL LOAD
A
H
L
B
C
D
E
F
H
L
PARALLEL
DATA
INPUTS
H
L
G
H
H
H
H
L
H
L
L
H
L
L
H
L
L
H
L
Q
Q
H
H
H
H
H
CLOCK
INHIBIT
MODE
SERIAL–SHIFT MODE
PARALLEL LOAD
7
MOTOROLA
MC54/74HC165A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0°
0°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
9
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
M
S
0°
10°
0°
10°
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
MIN
MAX
0.393
0.157
0.068
0.019
0.049
0.386
0.150
0.054
0.014
0.016
0.050 BSC
0.008
0.004
F
K
R X 45°
C
1.25
1.27 BSC
–T
0.19
0.10
0.25
0.25
0.009
0.009
J
SEAT
–
ING
M
K
PLANE
D 16 PL
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.229
0.010
M
S
S
0.25 (0.010)
T
B
A
MOTOROLA
8
MC54/74HC165A
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
NOTES:
S
0.15 (0.006) T
U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
–V–
DIM
A
B
C
D
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
–––
0.002
0.020
F
F
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com –TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CODELINE
MC54/74HC165A/D
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