MC68302FC16CR2 [MOTOROLA]

4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP132, 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132;


型号：	MC68302FC16CR2
厂家：	MOTOROLA
描述：	4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP132, 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 时钟局域网数据传输外围集成电路
文件：	总128页 (文件大小：641K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Microprocessors and Memory

Technologies Group

MC68EN302

Integrated

Multiprotocol Processor

with Ethernet

Reference Manual

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

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MOTOROLA

MC68EN302 REFERENCE MANUAL

iii

MC68EN302 REFERENCE MANUAL

MOTOROLA

Preface

The complete documentation package for the MC68EN302 consists of MC68EN302RM/AD,

the MC68EN302 Integrated Multiprotocol Processor with Ethernet, MC68302UM/AD, the

MC68302 Integrated Multiprotocol Processor, MC68EN302/D, the MC68EN302 Integrated

Multiprotocol Processor with Ethernet Product Brief; and M68000PM/AD, the M68000 Pro-

grammer’s Reference Manual.

The MC68EN302 Integrated Multiprotocol Processor with Ethernet User’s Manual describes

the programming, capabilities, registers, and operation of the MC68EN302 that differs from

the MC68302; the MC68302 Integrated Multiprotocol Processor describes the original

MC68302, the MC68EN302 Integrated Multiprotocol Processor with Ethernet Product Brief

provides a brief description of the MC68EN302 capabilities; and the M68000 Programmer’s

Reference Manual describes programming and the instruction set for the IMP processor.

This user’s manual is organized as follows:

Section 1

Section 2

Section 3

Section 4

Section 5

Section 6

Section 7

Section 8

Section 9

Introduction

Module Bus Controller

DRAM Control Module (DCM)

Ethernet Controller

Signal Description

Applications

IEEE 1149 Test Access Port (TAP)

Electrical Specifications

Ordering Information and Mechanical Data

Applications and Technical Information

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MC68EN302 REFERENCE MANUAL

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MC68EN302 REFERENCE MANUAL

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MOTOROLA

MC68EN302 REFERENCE MANUAL

vii

TABLE OF CONTENTS

Paragraph

Number

Title

Page

Number

Section 1

Introduction

1.1

1.2

1.3

1.3.1

1.4

Feature List ............................................................................................. 1-1

Block Diagram......................................................................................... 1-2

Memory Map ........................................................................................... 1-2

Module Controller Base Address Register (MOBAR) Address ($EE)..... 1-3

Section 2

MC68EN302 Module Bus Controller

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Introduction ............................................................................................. 2-1

Top Level Memory Map .......................................................................... 2-2

MBC Registers........................................................................................ 2-2

Module Bus Control (MBCTL)................................................................. 2-2

Interrupt Extension Register (IER) .......................................................... 2-3

Chip Select Extension Registers (CSER3–CSER0) ............................... 2-4

Parity Control and Status Register (PCSR) ............................................ 2-6

Bus Interface........................................................................................... 2-7

Bus Arbitration......................................................................................... 2-7

Dynamic Bus Sizing ................................................................................ 2-7

Bus Cycle Timing .................................................................................... 2-9

Bus Error Handling................................................................................ 2-10

Retry Handling ...................................................................................... 2-11

Parity Logic ........................................................................................... 2-11

Parity Generation .................................................................................. 2-11

Parity Checking..................................................................................... 2-11

Parity Error Reporting ........................................................................... 2-11

Parity Pin Enable................................................................................... 2-12

Interrupt Support ................................................................................... 2-12

2.8.1

2.9

2.9.1

2.9.2

2.9.3

2.10

2.10.1

2.10.2

2.10.3

2.10.4

2.11

Section 3

MC68EN302 DRAM Control Module

3.1

3.2

3.3

3.4

3.5

3.6

3.6.1

Introduction ............................................................................................ 3-1

Memory Map .......................................................................................... 3-1

DRAM Configuration Register (DCR)..................................................... 3-1

DRAM Refresh Register (DRFRSH) ...................................................... 3-2

DRAM Base Address Register (DBA1-DBA0) ....................................... 3-3

DRAM Control Module Operation .......................................................... 3-3

Reset Operation..................................................................................... 3-3

MOTOROLA

MC68EN302 USER’S MANUAL

vii

Table of Contents

Paragraph

Number

Title

Page

Number

3.6.2

3.7

3.8

3.8.1

3.8.2

3.8.3

3.8.4

3.8.5

3.8.6

3.8.7

Read and Write Cycle Operation ............................................................ 3-4

Refresh Operation................................................................................... 3-5

DRAM Controller I/O............................................................................... 3-6

Control Signal Pins ................................................................................. 3-6

Column Address Strobes (CAS1–CAS0)................................................ 3-6

Row Address Strobes (RAS1–RAS0)..................................................... 3-6

DRAM Read/Write (DRAMRW) .............................................................. 3-6

Address Mux (AMUX) ............................................................................. 3-7

Parity (PARITY1–PARITY0) ................................................................... 3-7

Muxing Scheme ...................................................................................... 3-7

Section 4

ETHERNET Controller

4.1

Ethernet Control Register (ECNTRL).......................................................4-3

Ethernet DMA Configuration Status Register (EDMA).............................4-3

Ethernet Maximum Receive Buffer Length (EMRBLR)............................4-5

Interrupt Vector Register (IVEC)..............................................................4-6

Interrupt Event Register (INTR_EVENT) .................................................4-6

Interrupt Mask Register (INTR_MASK)....................................................4-8

Ethernet Configuration (ECNFIG)............................................................4-9

Ethernet Test (ETHER_TEST)...............................................................4-10

AR Control Register (AR_CNTRL).........................................................4-11

Ethernet Buffer Descriptors....................................................................4-12

Ethernet Receive Buffer Descriptor (Rx BD)..........................................4-13

Ethernet Transmit Buffer Descriptor ......................................................4-16

DMA and Buffer Descriptor Logic ..........................................................4-18

Buffer Descriptor Logic ..........................................................................4-18

DMA Logic .............................................................................................4-19

Transmit and Receive FIFOs.................................................................4-19

Transmit FIFO........................................................................................4-19

Receive FIFO.........................................................................................4-20

Ethernet Protocol Logic..........................................................................4-20

Ethernet Transmit ..................................................................................4-20

Ethernet Receive ...................................................................................4-21

Ethernet Loopback.................................................................................4-22

Ethernet AR (Address Recognition).......................................................4-22

Buffer Descriptor Modification................................................................4-23

Writing Addresses into Tables ...............................................................4-25

Reading Addresses from Tables............................................................4-27

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.1.6

4.1.7

4.1.8

4.1.9

4.2

4.2.1

4.2.2

4.3

4.3.1

4.3.2

4.4

4.4.1

4.4.2

4.5

4.5.1

4.5.2

4.5.3

4.6

4.6.1

4.6.2

4.6.3

Section 5

Signal Descriptions

5.1

5.2

5.3

Pin/Signal Combinations..........................................................................5-1

MC68EN302/MC68302 Common Signals ...............................................5-4

MC68302 Signals Removed or Redefined...............................................5-5

viii

MC68EN302 USER’S MANUAL

MOTOROLA

Table of Contents

Paragraph

Number

Title

Page

Number

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.4

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.4.9

5.4.10

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.5.9

5.5.10

5.5.11

5.5.12

5.5.13

5.5.14

5.5.15

5.5.16

5.6

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

5.6.6

5.6.7

RMC/IOUT1............................................................................................. 5-5

IAC .......................................................................................................... 5-6

BCLR....................................................................................................... 5-6

FRZ ......................................................................................................... 5-6

BUSW...................................................................................................... 5-6

DISCPU................................................................................................... 5-6

MC68EN302 New Signals Muxed with Existing MC68302 Signals......... 5-6

AMUX - DRAM Address Mux .................................................................. 5-7

RAS0 - DRAM Row Address Select, Bit Zero ......................................... 5-7

RAS1 - DRAM Row Address Select Bit 1................................................ 5-7

CAS0 - DRAM Column Address Select Bit 0 .......................................... 5-7

CAS1- DRAM Column Address Select Bit 1 ........................................... 5-7

DRAMRW- DRAM Read/Write................................................................ 5-7

A0............................................................................................................ 5-8

WEL- Write Enable for Byte 1 (Bit 7–Bit 0).............................................. 5-8

WEH - Write Enable for Byte 0 (Bit 15–Bit 8).......................................... 5-8

OE - Output Enable................................................................................. 5-8

MC68EN302 Only Pin/Signals ................................................................ 5-8

GND ........................................................................................................ 5-8

TRST - JTAG Reset Signal ..................................................................... 5-8

TMS - JTAG Test Mode Select ............................................................... 5-9

TDO - JTAG Test Data Out..................................................................... 5-9

TDI - JTAG Test Data In.......................................................................... 5-9

TCK- JTAG Clock.................................................................................... 5-9

GND ........................................................................................................ 5-9

TENA....................................................................................................... 5-9

TCLK ....................................................................................................... 5-9

RCLK....................................................................................................... 5-9

RX ........................................................................................................... 5-9

RENA ...................................................................................................... 5-9

CLSN....................................................................................................... 5-9

PARITY0/DISCPU................................................................................... 5-9

PARITY1/BUSW.................................................................................... 5-10

PARITYE/THREESTATE ...................................................................... 5-10

DRAM Controller I/O ............................................................................. 5-10

Control Signal Pins................................................................................ 5-10

Column Address Strobes (CAS1–CAS0) .............................................. 5-10

Row Address Strobes (RAS1–RAS0) ................................................... 5-10

DRAM Read/Write (DRAMRW)............................................................. 5-10

Address Mux (AMUX)............................................................................ 5-11

Parity (PARITY1–PARITY0).................................................................. 5-11

Muxing Scheme..................................................................................... 5-11

MOTOROLA

MC68EN302 USER’S MANUAL

Table of Contents

Paragraph

Number

Title

Page

Number

Section 6

Applications

6.1

6.2

Bringing the MC68EN302 Out of Reset...................................................6-1

Moving a QUICC Ethernet Driver to a 68EN302 Ethernet Driver ............6-3

C_PRES, C_MASK:.................................................................................6-4

CRCEC: ...................................................................................................6-4

ALEC:.......................................................................................................6-4

DISFC: .....................................................................................................6-4

PADS: ......................................................................................................6-4

RET_LIM:.................................................................................................6-4

RET_Cnt: .................................................................................................6-5

MFLR: ......................................................................................................6-5

MINFLR:...................................................................................................6-5

MAXD1, MAXD2: .....................................................................................6-5

MAX_b: ....................................................................................................6-5

GADDR1-4 / PADDR_HML / IADDR1-4: .................................................6-5

P_PER: ....................................................................................................6-5

RFBD_ptr/TFBD_ptr/TLBD_ptr:...............................................................6-5

TX_len:.....................................................................................................6-5

BOFF_CNT:.............................................................................................6-6

TADDR_H/M/L:........................................................................................6-6

GSMR (QUICC Section 7.10.2) ...............................................................6-6

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

6.2.10

6.2.11

6.2.12

6.2.13

6.2.14

6.2.15

6.2.16

6.2.17

6.2.18

Section 7

IEEE 1149.1 (JTAG) Test Access Port

7.1

7.2

7.3

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.4.5

7.5

Overview..................................................................................................7-1

TAP Controller .........................................................................................7-2

Boundary Scan Register..........................................................................7-3

Instruction Register................................................................................7-12

EXTEST.................................................................................................7-13

SAMPLE/PRELOAD ..............................................................................7-13

BYPASS.................................................................................................7-13

CLAMP...................................................................................................7-14

HI-Z........................................................................................................7-14

MC68EN302 Restrictions.......................................................................7-14

Non-Scan Chain Operation....................................................................7-14

7.6

Section 8

MC68EN302 Electrical Characteristics

8.1

8.2

8.3

8.4

8.5

8.6

8.6.1

Power Dissipation ....................................................................................8-1

Changes to Existing MC68302 Timing Specs..........................................8-1

DRAM Interface Timing............................................................................8-2

Ethernet Timing........................................................................................8-5

JTAG Interface Timing.............................................................................8-7

OE, WEL, WEH Timing............................................................................8-9

OE Timing................................................................................................8-9

MC68EN302 USER’S MANUAL

MOTOROLA

Table of Contents

Paragraph

Number

Title

Page

Number

8.6.2

WEL, WEH Timing .................................................................................. 8-9

Section 9

Ordering and Mechanical Information

9.1

Pin Assignment ....................................................................................... 9-1

Pin Grid Array (PGA)............................................................................... 9-2

144 Thin Quad Flat Pack (TQFP)............................................................ 9-3

Package Dimensions............................................................................... 9-4

Pin Grid Array (PGA)............................................................................... 9-4

144 Thin Quad Flat Pack (TQFP)............................................................ 9-5

Standard Ordering Information................................................................ 9-6

9.1.1

9.1.2

9.2

9.2.1

9.2.2

9.3

MOTOROLA

MC68EN302 USER’S MANUAL

LIST OF FIGURES

Figure

Title

Page

Number

Figure 1-1. MC68EN302 Block Diagram ................................................................... 1-2

Figure 2-1. Top Level Bus Structure.......................................................................... 2-1

Figure 2-2. 8-bit External to 16-bit Internal Read ...................................................... 2-8

Figure 2-3. 16-bit Internal to 8-bit External Write....................................................... 2-8

Figure 2-4. Word Read with 3-Clock 8-Bit Accesses................................................. 2-9

Figure 2-5. Word Write with 3-Clock 8-Bit Accesses................................................. 2-9

Figure 2-6. Fast Cycle Word Read with –1 Wait State............................................ 2-10

Figure 2-7. Fast Cycle Word Write with -1 Wait State............................................. 2-10

Figure 2-8. External and Internal Interrupt Prioritization.......................................... 2-13

Figure 3-1. Consecutive Four-Clock Accesses ........................................................ 3-4

Figure 3-2. Five-Clock Accesses with Three-Clock Precharge ................................ 3-5

Figure 3-3. Precharge With DRAM Access Active ................................................... 3-6

Figure 4-1. Ethernet Controller Block Diagram.......................................................... 4-2

Figure 4-2. Ethernet Receive Buffer D.0escriptor (Rx BD)...................................... 4-13

Figure 4-3. Ethernet Transmit Buffer Descriptor (Tx BD) ........................................ 4-16

Figure 4-4. Ethernet Address Recognition Flowchart.............................................. 4-25

Figure 4-5. AR Memory Map - Perfect Match Mode................................................ 4-26

Figure 4-6. AR Memory Map - Hash Mode.............................................................. 4-27

Figure 7-1. Test Logic Block Diagram ....................................................................... 7-2

Figure 7-2. TAP Controller State Machine................................................................. 7-3

Figure 7-3. Output Latch Cell (iocell)......................................................................... 7-8

Figure 7-4. Input Pin Cell (iscell) ............................................................................... 7-8

Figure 7-5. Control Cell (dicell).................................................................................. 7-9

Figure 7-6. Bidirectional Cell (bicell).......................................................................... 7-9

Figure 7-7. Output Enable Cell (encell) ................................................................... 7-10

Figure 7-8. Output Enable Cell (encello) ................................................................. 7-10

Figure 7-9. Output Enable Cell (clko_encell)........................................................... 7-11

Figure 7-10. General Arrangement for Bidirectional Pins.......................................... 7-12

Figure 7-11. Bypass Register.................................................................................... 7-13

Figure 8-1. DRAM Read Cycle.................................................................................. 8-3

Figure 8-2. DRAM Write Cycle .................................................................................. 8-4

Figure 8-3. DRAM Refresh........................................................................................ 8-5

Figure 8-4. Ethernet Collision Timing ........................................................................ 8-6

Figure 8-5. Ethernet Receive Timing......................................................................... 8-6

Figure 8-6. Ethernet Transmit Timing........................................................................ 8-6

Figure 8-7. Test Clock Input Timing Diagram............................................................ 8-7

Figure 8-8. TRST Timing Diagram ............................................................................ 8-7

Figure 8-9. Boundary Scan (JTAG) Timing Diagram................................................. 8-8

Figure 8-10. Test Access Port Timing Diagram........................................................... 8-8

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LIST OF TABLES

Table

Title

Page

Number

Table 1-1.

Table 2-1.

Table 2-2.

Table 2-3.

Table 2-4.

Table 2-5.

Table 3-1.

Table 3-2.

Table 3-3.

Table 3-4.

Table 4-1.

Table 4-2.

Table 4-3.

Table 4-4.

Table 5-1.

Table 5-2.

Table 5-3.

Table 7-1.

Table 7-2.

Table 7-3.

Table 8-1.

Table 8-2.

MC68EN302 Additional Registers.............................................................1-4

High Level Memory Map of MBC and MB Modules ..................................2-2

Module Bus Controller Register Set..........................................................2-2

Pin Muxing Operation................................................................................2-3

DT Bit Encoding ........................................................................................2-5

Parity Pin Enable Operation....................................................................2-12

DRAM Controller Registers...................................................................... 3-1

Precharge Bit Encodings.......................................................................... 3-2

Wait State Bit Encodings.......................................................................... 3-2

Address Muxing Scheme ......................................................................... 3-7

Ethernet Controller Memory Map ..............................................................4-2

BD RAM Address Ranges.......................................................................4-18

Unicast Address Processing ...................................................................4-24

Broadcast and Multicast Address Processing.........................................4-24

MC68EN302 144-TQFP Pin/Signal Definition...........................................5-1

Pin Muxing Control....................................................................................5-6

Address Muxing Scheme ........................................................................5-11

Boundary Scan Control Bits ......................................................................7-4

Boundary Scan Bit Definition.....................................................................7-6

Instruction Decoding................................................................................7-12

DRAM Interface Timing.............................................................................8-2

Ethernet Timing.........................................................................................8-5

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Table of Contents

Paragraph

Number

Title

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Number

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SECTION 1

INTRODUCTION

The MC68EN302 is a multiprotocol integrated communications controller based on the

MC68302. The original MC68302 provided multiple WAN and ISDN support with three serial

communcations channels, glueless memory control for SRAM and EPROM and various

system integration features. The MC68EN302 builds upon the success of the MC68302 by

adding an Ethernet controller which is completely independent of the three on-board serial

channels as well as a DRAM control and a JTAG interface. No communications related

features of the original 302 are lost when using either the Ethernet controller or the DRAM

controller of the MC68EN302.

The Ethernet controller provides a 16-bit interface and provides complete IEEE 802.3

compatibility. The programming model for the Ethernet controller is based on the standard

MC68302 programming model. Buffer descriptors for the Ethernet controller are compatible

wiith the buffer descriptors used by the MC68360 QUICC Ethernet controller.

The DRAM controller is based upon other 300 family memory controllers with specific

enhancements provided for supporting parity and external bus masters.

The JTAG interface is the standard IEEE1149.1 test interface.

1.1 FEATURE LIST

The following MC68EN302 features are in addition to the MC68302 feature list:

• Full complement of existing three SCC’s plus Ethernet channel

• Ethernet channel fully compliant with IEEE 802.3 MAC Specification.

— Supports data rates up to 10 Mbps.

— Supports the MC68302 style programming model.

— Bus bandwidth requirements reduced through 128 on-chip buffer descriptors.

— Independant 128 byte transmit and receive FIFO’s.

— 64 entry CAM for Address Recognition.

— Ethernet collision results in retransmission from TX FIFO (no external bus access).

— Runt frames automatically cause RX FIFO to flush internally.

— Interfaces to MC68160 for 10Base-T or AUI Connection.

• Dynamic Bus Sizing

• Glueless ROM and SRAM interface

• DRAM Controller

— Glueless DRAM interface for internal bus master

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Introduction

— AMUX signal provided for external bus master use

— Parity generation/checking on a per byte basis

• Fully IEEE 1149.1 JTAG Compliant

• 144 TQFP package

1.2 BLOCK DIAGRAM

The MC68EN302 adds functionality to the pre-existing MC68302 by providing additional

blocks external to the MC68302 which arbitrate for use of the 68000 bus for access to off-

chip resources such as memory or other peripheral devices. This modular approach is

shown in Figure .

MC68EN302

MC68302

1 GENERAL-

PURPOSE

DMA

3 TIMERS

AND

ADDITIONAL

FEATURES

INTERRUPT

CONTROLLER

JTAG

CHANNEL

IEEE 1149.1

68000

SYSTEM BUS

MC68000

1152 BYTES

DUAL-PORT

RAM

MODULE BUS

CONTROLLER

6 DMA

CHANNELS

PERIPHERAL

BUS

MICROCODED

COMMUNICATIONS

CONTROLLER

(RISC)

DRAM

ETHERNET

CONTROLLER

OTHER

SERIAL

CHANNELS

3 SERIAL

CHANNELS

Figure 1-1. MC68EN302 Block Diagram

1.3 MEMORY MAP

The MC68EN302 memory map does not change the MC68302 memory map, but rather

adds a new 4K module block. This is in addition to the 4K module block of the MC68302.

Because of the additional register block, there are two Base Address Registers to program

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Introduction

in the MC68EN302. The BAR register is identical to the MC68302 BAR, and the Module

Controller Base Address Register is specific to the MC68EN302.

1.3.1 Module Controller Base Address Register (MOBAR) Address ($EE)

The Module Controller Base Address Register (MOBAR) sets the base address for the

MC68EN302 registers which are in addition to the register set of the MC68302. The MOBAR

is located at address $0EE and its configuration and operation match the existing MC68302

BAR. The value of MOBAR after reset defaults to $BFFE which places the Module Controller

Block directly below the MC68302 Block. The MC68EN302 must be in supervisor mode for

MOBAR to be written with a new value.

FC2 FC2 FC0 CFC BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12

FC2–FC0—Function Code 2–Function Code 0

FC2-0 sets the address space of the 4 kbyte Module Controller Block. Depending

on the value of the CFC bits, the MC68EN302 address compare logic uses these

bits to cause an address match within its address space.DO NOT assign FC2-0

to the M68000 interrupt acknowledge space (FC2-0 = 111b).

CFC—Compare Function Code

When cleared, the FC bits in the MOBAR are ignored and accesses to the Module

Controller Block occur without comparing the FC bits. When set, the address

space compare logic uses the FC bits in MOBAR to detect address matches.

MOBA—Module Controller Base Address.

The high address field is contained in bits 11-0 of the MOBAR and sets the

starting address of the Module Controller Block.

1.4 REGISTER OVERVIEW

The control and status registers for the Ethernet controller are all 16 bits with an address

range of MOBA+$000 to MOBA+$FFF. The MC68EN302 registers in addition to the 302

provided, special care must be taken when initializing the pre-existing 302 registers so there

are no contention or compatibility issues during internal arbitration. The registers that

require particular attention are:

• OR

• GIMR

• SCR.

Also, notice that DTACK is not returned for accesses to unimplemented CSRs in the MOBA

address space.

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Introduction

Table 1-1. MC68EN302 Additional Registers

ADDRESS

NAME

MNEMONIC

MBC

TYPE

MOBA + 000

MOBA + 002

MOBA + 004

MOBA + 006

MOBA + 008

MOBA + 00A

MOBA + 00C

Module Bus Control

Read/Write

Interrupt Extension Register

Chip Select 0 Extension Register

Chip Select 1 Extension Register

Chip Select 2 Extension Register

Chip Select 3 Extension Register

Parity Control & Status Register

IER

CSER0

CSER1

CSER2

CSER3

PCSR

MOBA + 010

MOBA + 012

MOBA + 014

MOBA + 016

DRAM Configuration Register

DRAM Refresh Register

DCR

DRFRSH

DBA0

Read/Write

DRAM Bank 0 Base Address Register

DRAM Bank 1 Base Address Register

DBA1

MOBA + 800

MOBA + 802

MOBA + 804

MOBA + 806

MOBA + 808

MOBA + 80A

MOBA + 80C

MOBA + 80E

MOBA + 810

Ethernet Control Register

Ethernet DMA Configuration Register

Maximum Receive Buffer Length

Interrupt Vector Register

ECNTRL

EDMA

Read/Write

EMRBLR

INTR_VECT

INTR_EVENT

INTR_MASK

ECNFIG

Interrupt Event

Interrupt Mask Register

Ethernet Configuration

Ethernet Test Register

ETHER_TEST

AR_CNTRL

Address Recognition Control Register

MOBA + A00

MOBA + BFF

CAM Entry Table

CET

EBD

Read/Write

MOBA + C00

MOBA + FFF

Buffer Descriptors Table

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SECTION 2

MC68EN302 MODULE BUS CONTROLLER

2.1 INTRODUCTION

The model of the MC68EN302 is such that the internal 302 functions are unaffected by the

addition of an Ethernet controller and the DRAM controller. The 302 core sees that it must

arbitrate with other bus masters for access to the ‘external’ bus. In the MC68EN302, the

Module Bus Controller provides the arbitration between the 302 core and the other modules

(Ethernet and DRAM) for access to the bus external to the MC68EN302. The functions

provided by the Module Bus Controller (MBC) are as follows:

• Interfaces between internal 68000 bus and the Module Bus.

• Performs Dynamic Bus sizing utilizing the chip select logic of the internal 68302.

• Provides Interrupt handling for Module Bus modules.

• Performs bus arbitration between external sources, the Module Bus, and the 68302

core.

INTERNAL

302 BUS

INTERNAL

68000 BUS

EXTERNAL

68000 BUS

MC68302

MODULE

BUS

CONTROLLER

MODULE BUS

MODULES

Figure 2-1. Top Level Bus Structure

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MC68EN302 Module Bus Controller

2.2 TOP LEVEL MEMORY MAP

A top level diagram of register allocation for the modules in the MC68EN302 is shown in

Table 2-1. A description of the DRAM control registers and the Ethernet Controller Registers

are contained in the description of those modules.

Table 2-1. High Level Memory Map of MBC and MB Modules

Address

MOBA + 000

MOBA + 00D

Block

MBC Registers

MOBA + 010

MOBA + 019

DRAM Controller Registers

Ethernet Controller Registers

MOBA + 800

MOBA + FFF

2.3 MBC REGISTERS

A memory map of the MBC control registers is shown in Table 2-2.

Table 2-2. Module Bus Controller Register Set

ADDRESS

MOBA + 000

MOBA + 002

MOBA + 004

MOBA + 006

MOBA + 008

MOBA + 00A

MOBA + 00C

MNEMONIC

MBCTL

IER

Module Bus Control Register

Interrupt Extension Register

Chip Select 0 Extension Register

Chip Select 1 Extension Register

Chip Select 2 Extension Register

Chip Select 3 Extension Register

Parity Control & Status Register

CSER0

CSER1

CSER2

CSER3

PCSR

2.4 MODULE BUS CONTROL (MBCTL)

The Module Bus Control register (MBCTL) provides the user control over the system level

functionality of the MBC. This register defaults to $0x5000 upon hardware reset.

BCE MFC2 MFC1 MFC0 BB

PPE

PM9 PM8 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

BCE—Bus Clear Enable. This bit controls the way in which the MBC responds to the Bus

Clear function inside the MC68EN302. If BCE is zero, the MBC ignores the Bus Clear

(BCLR) signal giving the DRAM and Ethernet modules priority over the 302 core. If this bit

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MC68EN302 Module Bus Controller

is set, the MBC relinquishes the bus when it detects BCLR, allowing the internal 302 core

priority over the DRAM and Ethernet controllers.

MFC—Module Function Code (MFC2-MC0). These bits determine the function code put out

when the Ethernet DMA machine is active.

BB—Bus Error Byte. This status bit (read-only) is the state of Address 0 upon the last

generated bus error. This information is useful when performing exception processing to

determine the cause of bus errors generated when the 8-bit dynamic bus sizing option is

used with the Chip Selects.

PPE—Parity Pin Enable. This bit, if set, enables parity on the appropriate pins. The parity

signals are muxed on three MC68EN302 configuration pins which are sampled at hard reset

to determine device operation. Once out of reset, the parity function may be enabled by the

PPE bit. See 2.10.4 Parity Pin Enable for more details.

PM—Pin Muxes PM9–PM0. Depending upon the setting of these bits, the MC68EN302 is

able to provide some enhancements over the 68302. Because many of these

enhancements are with existing 68302 pins, the enhancements are provided as

programmable options. Table 2-3 shows the effect of the PM bits. All PM bits are cleared at

hardware reset.

Table 2-3. Pin Muxing Operation

Bit = 0

Pin Function

AMUX

Bit = 1

Pin Function

BRG1

Mux Bit

PM0

PM1

RAS0

BRG2/SDS2/PA7

BRG3/PA12

PB0/IACK7

PB1/IACK6

PB2/IACK1

TOUT1/PB4

WEL

PM2

RAS1

PM3

CAS0

PM4

CAS1

PM5

DRAM_RW

PM6

PM7

DREQ/PA13

DACK/PA14

PM8

WEH

PM9

DONE/PA15

2.5 INTERRUPT EXTENSION REGISTER (IER)

This register replaces the MOD, ET7, ET6, and ET1 bits in the pre-existing 302 GIMR

(Global Interrupt Mode Register) requiring that when writing to the internal 302 core GIMR,

the corresponding bits must be written as a zero.This register is $0x0000 upon hardware

reset.

IMOD

MIL IET7 IET6 IET1

IMOD—Interrupt Mode. This bit determines if the 3 interrupt inputs are configured as IPL

pins or IRQ pins for the MC68EN302 and replace the MOD bit functionality in the internal

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MC68EN302 Module Bus Controller

302 GIMR. For proper operation of the MC68EN302, the MOD bit must be zero in the

internal 302 core.

0 = Configures the pins as IPL2-IPL0.

1 = Configures the pins as IRQ7, IRQ6, and IRQ1.

Bits 14–12—Reserved. Should be written as zero. These bits are always read as zero.

MIL—Module Interrupt Level. This bit determines the interrupt level at which Module Bus

Controller interrupts are generated. Because the interrupt level of the internal 302 core is set

at 4, and this bit predetermines the Module Bus Controller interrupt at either level 3 or 5,

external interrupts should not be generated at level 4 or the level preset by MIL.

0 = Interrupts are generated at level 5

1 = Interrupts are generated at level 3.

IET7—Interrupt Edge Trigger Level 7. This bit has no effect unless IMOD=1 and replaces

the operation of the ET7 bit in the Global Interrupt Mode Register (GIMR) of the internal 302

core. The ET7 bit in the GIMR register must equal zero for correct interrupt operation

0 = An interrupt is made pending when IRQ7 is low.

1 = An interrupt is made pending when IRQ7 changes from a one to a zero (falling

edge) of the MC68EN302.

IET6—Interrupt Edge Trigger Level 6. This bit is has no affect unless IMOD is one. This bit

replaces the functionality of the ET6 bit in the Global Interrupt Mode Register (GIMR) of the

internal 302 core. The ET6 bit in the GIMR register must be set to zero.

0 = An interrupt is made pending when IRQ6 is low.

1 = An interrupt is made pending when IRQ6 changes from a one to a zero (falling

edge).

IET1—Interrupt Edge Trigger Level 1. This bit is has no effect unless IMOD is one. This bit

replaces the functionality of the ET1 bit in the Global Interrupt Mode Register (GIMR) of the

internal 302 core. The ET1 bit in the GIMR register must be set to zero.

0 = An interrupt is made pending when IRQ1 is low.

1 = An interrupt is made pending when IRQ1 changes from a one to a zero (falling

edge).

Bits 7–0—Reserved. Should be written as zero. These bits are always read as zero.

2.6 CHIP SELECT EXTENSION REGISTERS (CSER3–CSER0)

These registers provide additional functionality above the 68302 chip selects including 8-bit

bus operation and parity generation and checking. Before setting the FCE, DT2–DT0 or EN8

bits, be sure that an external DTACK is supported by programming the 302 DTACK field in

the corresponding OR register to 111. These registers are initialized to 0x000C or 0x000D

upon hard reset (refer to the EN8 bit for more detail).

If at RESET, the 8-bit mode is selected through use of the PARITY1/BUSW pin, the DTACK

field in OR0 of the 302 core is forced to 111. This results in the DT2–DT0 field of CSER0

controlling DTACK.

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MC68EN302 Module Bus Controller

During reset, CS1, CS2 and CS3 are disabled via the EN bit in the BR1, BR2 and BR3

registers.

Note that when in disable CPU mode, the CS0 function is replaced by IOUT2.

CSPE

FCE DT2 DT1 DT0 EN8

Bits 15–8—Reserved. Should be written to zero by the host processor. These bits are

always read as zero.

CSPE—Chip Select Parity Enable. This bit enables parity checking and generation when

the corresponding Chip Select is generated. Unless the corresponding chip select is set to

8-bit operation, parity is generated and checked on both bytes.

Bits 6–5—Reserved. Should be written to zero by the host processor. This bit is always read

as zero.

FCE—Fast Cycle Enable. This bit enables fast mode operation. When using fast cycles, CS

and AS are not negated between 8 bits of a 16 bit transfer, allowing a 16-bit transfer to occur

on an 8-bit bus in 5 clocks rather than 6.

DT2–DT0—DTACK. These bits are used to determine whether DTACK is generated

internally with a programmable number of wait states or externally by the peripheral. When

done internally, the MC68EN302 provides the option of allowing 16-bit accesses to take

place in two-three clock external 8-bit accesses. The 68000 only sees a single six clock

access internally during this mode of operation. This functionality is also referred to as

‘minus one wait state option.’ Note that an 8-bit operand access requires a 4 clock bus cycle.

Table 2-4 shows how the bits are encoded.

Table 2-4. DT Bit Encoding

DT BIT ENCODING

WAIT STATES

000

001

010

011

100

101

110

111

-1

No DTACK

EN8—Enable 8-bit chip select. When set to a one, the 8-bit chip select operation is enabled.

If the system is booted from an 8-bit memory, the system must drive the BUSW pin low

during system reset which sets the EN8 bit for all four CSER registers. This assures that the

device is able to access 8-bit memories as well as 16-bit memories. In 8-bit mode bits D15–

D8 of the data bus are used.

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MC68EN302 Module Bus Controller

2.7 PARITY CONTROL AND STATUS REGISTER (PCSR)

This register controls and gives the status of the parity checking portions of the parity

circuitry. This register is set to 0x0000 upon hardware reset.

PIE OPAR PEC3 PEC2 PEC1 PEC0 PED1 PED0 PIV7 PIV6 PIV5 PIV4 PIV3 PIV2 PIV1 PIV0

PIE—Parity Error Interrupt Enable. This bit determines if an interrupt is generated when a

parity error is detected.

0 = No interrupt is generated.

1 = Either a level 3 or level 5 interrupt is generated, depending upon the encoding of

the MIL bit in the IER register.

OPAR—Odd Parity. This bit is used to determine if odd or even parity is used.

0 = Parity is even.

1 = Parity is odd.

PEC—Parity Error Chip Selects (PEC3–PEC0). These status bits indicate that there was a

parity error in the corresponding Chip Select Bank. If one of the three bits is set to one, a

parity error is detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt

is driven to the processor as long as one of the PEC3–PEC0 bits are set. PEC3–PEC0 are

sticky bits which are cleared when a one is written to them or upon hardware reset. Writing

a zero does not change the value of the PEC bits. The PARITYE pin is asserted until the

PEC3–PEC0 bits are all cleared.

NOTE

If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is

enabled with CSPE in CSER3–CSER0, then a parity error will be

reported on the associated PEC bit.

PED—Parity Error DRAM (PED1–PED0). These status bits indicate that there was a parity

error in the corresponding DRAM bank. If one of the two bits is set to one, a parity error is

detected in the corresponding bank. If the PIE bit is set, a level 5 (or 3) interrupt is driven to

the processor as long as one of the PED bits is set. PED are sticky bits which are cleared

when a one is written to them or upon hardware reset. Writing a zero does not change the

value of the PED bits. Writing a zero does not change the value of the PED bits. The

PARITYE pin is asserted as long as a PED bit is set.

NOTE

If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is

enabled on the DRAM interface (PE1 and/or PE0 = 1 in DCR)

then a parity error will be reported on PED1–PED0.

PIV—Parity Error Interrupt Vector (PIV7–PIV0). If the PIE bit is set, a parity error generates

a level 5 (or 3) interrupt. The PIV bits determine what interrupt vector is returned in response

to a level 5 (or 3) parity error interrupt.

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MC68EN302 Module Bus Controller

2.8 BUS INTERFACE

The MBC is responsible for determining the source of the bus mastership (module bus,

external 68K bus or internal 302 core) and for controlling the direction of the buses. The

layer of buffering between the internal 302 and internal 68000 buses mimics the operation

of the 68302 external bus, giving the module bus the appearance of an external master from

the viewpoint of the internal 302 core. The MBC does not affect the operation of the bus

outside the MC68EN302 unless it arbitrates for that bus and is given bus mastership. The

operation of the MBC as bus master is such that the bus external to the MC68EN302

operates as if an existing 302 peripheral is bus master. This is accomplished by:

• Providing I/O control at the pad which overrides the existing 68302 I/O control.

• Intercepting the external arbitration signals and merging them with the MBC arbitration.

2.8.1 Bus Arbitration

The MBC provides the circuitry which prioritizes the bus mastership requests in the following

order (highest priority to lowest):

• External bus requests

• Module bus requests (Ethernet module)

• internal 302 core

2.9 DYNAMIC BUS SIZING

The MBC accommodates dynamic bus sizing by providing control to operate on the internal

68000 bus as a 16-bit device while simultaneously providing an 8-bit option externally.

Control is provided via the EN8 bit in the CSER3–CSER0 registers and via the BUSW pin.

The MBC routes data into the proper byte of the word D15–D8, increments the address, and

runs a second bus cycle.

When reading and writing, the MBC will assure proper operation when performing even byte

accesses, even word accesses, and odd byte accesses. Figure 2-4 shows the read cases,

and Figure 2-5 shows the write cases. The even word access is the only case requiring two

bus cycles. When an internal bus cycles is taking place, both AS and the appropriate chip

select will be in operation (except when FAST CYCLES are used). The address is

incremented only in the case of an even address access. Because of this, the address

increment only involves setting A0 to one.

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MC68EN302 Module Bus Controller

EVEN

BYTE

EVEN

WORD

ODD

BYTE

ACCESS

External

D15-8

Latched

ID15-8 ID7-0

Terminated

Internally

Terminated

Internally

Increment

Address

External

D15-8

ID15-8 ID7-0

Terminated

Internally

Figure 2-2. 8-bit External to 16-bit Internal Read

Note that an external access of 16-bits to an 8-bit port requires an external address

increment as well as data muxing. It is generally recommended that external accesses using

the 8-bit chip select extensions access only 8-bits at a time and access that data on the

upper 8-bits of the bus.

EVEN

BYTE

EVEN

WORD

ODD

BYTE

ACCESS

ID15-8 ID7-0

Latched

ID15-8 ID7-0

D15-8

External

D15-8

External

D15-8

Terminated

Internally

Terminated

Internally

Increment

Address

ID15-8 ID7-0

D15-8

External

Terminated

Internally

Figure 2-3. 16-bit Internal to 8-bit External Write

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MC68EN302 Module Bus Controller

2.9.1 Bus Cycle Timing

The 8-bit extension logic for dynamic sizing is programmable from -1 to 5 wait states, and

allows the external logic to terminate the cycle. Even word accesses are a special case

which require specific control operations to allow the device to provide two external bus

cycles. In some cases, the timing generated looks like two comparable 68000 cycles.There

are two exceptions to this. First, the -1 wait state timing is a special case, since the 68000

bus is defined as a minimum 4 clock bus. The second exception is the Fast Cycle case. The

-1 wait state case appears externally as two 16-bit 3 clock bus cycles. Figure 2-4 shows the

timing for the read case, while Figure 2-5 shows the timing for writes.

CLOCK

ADDR23-1

ADDR0

AS/CS

DATA

UDS/LDS

Figure 2-4. Word Read with 3-Clock 8-Bit Accesses

CLOCK

ADDR23-1

ADDR0

AS/CS

DATA

UDS/LDS

Figure 2-5. Word Write with 3-Clock 8-Bit Accesses

The fast cycle case differs from the normal cycle in that AS and chip select do not negate

between the first and second half of the 16-bit access, allowing the two bus cycles to be

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MC68EN302 Module Bus Controller

reduced one extra clock. A0 is incremented one half clock earlier in this scheme to allow

sufficient address access in the second portion of the bus cycle. Figure 2-6 shows the fast

cycle read case, while Figure 2-7 shows the fast cycle write case. In order to use fast cycles

with SRAM, the CS signal is high between cycles, accommodating a write to SRAMs.

CLOCK

ADDR23-1

ADDR0

AS/CS

DATA

UDS/LDS

Figure 2-6. Fast Cycle Word Read with –1 Wait State

CLOCK

ADDR23-1

ADDR0

DATA

UDS/LDS

Figure 2-7. Fast Cycle Word Write with -1 Wait State

2.9.2 Bus Error Handling

Since the external bus may operate as an 8-bit bus, at the same time the internal bus

operates as 16-bits, a bus error passed from the external bus to the internal bus does not

specify which byte has been faulted. To assure that information is not lost, the Bus Error

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Byte (BB) bit is provided in the MBC register. This bit reflects the state of A0 during the last

bus error caused by an access to a byte peripheral.

2.9.3 Retry Handling

In most cases, an MC68EN302 retry is identical to 302 retry operation. If however, a retry

occurs during the second bus cycle of a word access to an 8-bit port, the retry signal is

passed to the initiating master. This causes both of the cycles to be retried, instead of just

the second cycle.

2.10 PARITY LOGIC

The MC68EN302 provides parity support to generate, check, and report parity and parity

errors.

2.10.1 Parity Generation

The MC68EN302 provides the option of generating and checking parity for the 4 chip selects

and the 2 DRAM banks. In the case of a write, parity is generated with one bit of parity per

byte of data. The parity is output on the parity pins and delayed from other data by the

propagation delay through the parity generator.

2.10.2 Parity Checking

Parity checking is performed on read accesses. If the 8-bit option of the Chip Select logic is

used, parity is checked on only the upper 8-bits. In all other options, parity is checked on

both bytes.

2.10.3 Parity Error Reporting

Parity error reporting is accomplished via three mechanisms.

• Parity Error Pin

This pin is asserted when a parity error is detected. Parity error detection does not occur

with enough time to generate a bus error on the affected cycle. The parity error pin may be

used with external circuitry to facilitate parity error handling. This pin is not negated until all

the parity error register bits are cleared.

• Parity Error Status Bits

There are 6 PCSR register bits dedicated to providing status on parity errors, corresponding

to the 2 DRAM banks and the 4 Chip Selects. If a parity error is detected, the bit that

corresponds to the module that generated the error is set. These bits are reset to zero and

are cleared by writing a one.

• Parity Error Interrupt

The PIE bit in the PCSR register is provided to allow the option of generating a level 5 (or 3)

interrupt in the event that a parity error is generated. If this option is selected, the interrupt

is driven after the error is detected until the Parity Error Status Bits are cleared.

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2.10.4 Parity Pin Enable

During hardware reset, the parity pin enable bit (PPE) in the MBC register (see 2.4 Module

Bus Control (MBCTL)) is cleared, which results in the parity pins becoming inputs. Each of

the three pins is sampled for a different function, as shown in Table 2-5. After exiting

Table 2-5. Parity Pin Enable Operation

PPE = 0

PIN FUNCTION

DISCPU

PPE = 1

PIN FUNCTION

PARITY0

BUSW

PARITY1

THREES

PARITYE

hardware reset, these pins are sampled to determine chip functions. Pullup or pulldown

resistors are required for presetting the desired state if the parity pins are to be later

programmed as input/output pins. After hardware reset, the PPE bit can be set to enable the

parity pins as outputs. The PPE bit should be set to enable parity even on reads.

2.11 INTERRUPT SUPPORT

All module bus and module bus controller interrupts are at level 5 or at level 3 if MIL is set

(See 2.5 Interrupt Extension Register (IER)). There are two sources of interrupts in the MBC:

One is the Ethernet controller; the second source is the parity error interrupt. The parity error

interrupt is the higher priority of the two. If an interrupt acknowledge cycle is generated when

both interrupts are asserted, the MBC responds to the parity error interrupt by driving its

vector onto the internal 68000 bus. Only after the parity error interrupt is cleared will the

Ethernet controller respond to an IACK cycle.

In order to accommodate an additional interrupt source within the MC68EN302, an

additional Interrupt Mode (IMOD) bit is provided in the MBC. This bit configures the Interrupt

pins as IRQ or IPL lines. This replaces the MOD bit in the Global Interrupt Mode Register

(GIMR). This means that the existing MOD bit in the Global Interrupt Mode Register (GIMR)

must always remain at zero. The IMOD bit in the IER register duplicates this function in the

MBC.

Since the MBC generates a level 5 (or level 3) interrupt, and there is no way to resolve IACK

conflicts with the external circuitry, a level 5 (or level 3) interrupt should not be asserted

externally. Figure 2-8 summarizes the interrupt configuration and priorities.

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Priority

Level

Normal Mode

IPL2–IPL0

Dedicated Mode

IRQ7, IRQ6, IRQ1

Interrupt

Source

7 (Highest)

000

001

IRQ7

IRQ6

External

MBC/External

Internal 302

External/MBC

External

101

110

1 (Lowest)

IRQ1

External

*Priority level not available to an external device in

this mode

** The level not selected by MIL is available but not both

level 3 and level 5.

Figure 2-8. External and Internal Interrupt Prioritization

The MBC passes the interrupt vector (see 4.1.4 Interrupt Vector Register (IVEC)) from the

Module bus to the 68000 bus.

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SECTION 3

MC68EN302 DRAM CONTROL MODULE

3.1 INTRODUCTION

The MC68EN302, like its predecessor the MC68302, can be connected with DRAM-type

memories easily. The difference in the MC68EN302 lies in the DRAM Control Module

(DCM), which was developed to provide seamless integration of the 68000 core with DRAM

memories. The MC68EN302 DRAM controller is able to support up to two 16-bit wide banks

and an address range from 128kbytes to 8Mbytes. Selection between the two banks occurs

externally through the MC68EN302 RAS1–RAS0 signals, and byte selection occurs via the

CAS1–CAS0 signals. The user is able to select cycle lengths ranging in duration from 4 to

7 clocks. The MC68EN302 also provides programmable refresh rates which can range

anywhere from 16 to 4096 system clocks, or be disabled altogether.

3.2 MEMORY MAP

Table 3-1 shows the basic memory map of the DRAM Control Module registers.

Table 3-1. DRAM Controller Registers

ADDRESS

MOBA + 010

MOBA + 012

MOBA + 014

MOBA + 016

NAME

MNEMONIC

DCR

TYPE

DRAM Configuration Register

DRAM Refresh Register

Read/Write

DRFRSH

DBA0

DRAM Bank 0 Base Address Register

DRAM Bank 1 Base Address Register

DBA1

3.3 DRAM CONFIGURATION REGISTER (DCR)

This register controls the specific operation of each bank of DRAM and is initialized to zero

at hardware reset.

PE1 PE0

W0 WP1 WP0 S/U1 S/U0

Bits 15–12—Reserved. Should be written to zero by the host processor. These bits are

always read as zero.

E1-E0—Refresh Enable Bits.

0 = Disable refresh operation in the corresponding DRAM bank

1 = Enable refresh operation in the corresponding bank.

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PE1-PE0—Enable Parity.

0 = Parity is generated but not checked

1 = Parity is generated on writes, and parity is checked on reads in the corresponding

bank. If a parity error is detected the bus cycle is terminated with a bus error.

NOTE

If the Parity Pin Enable bit (PPE in MBC CSR) = 0 and parity is

enabled on the DRAM interface (PE1 and/or PE0 = 1 in DCR)

then a parity error will be reported on PED1–PED0.

P1-P0—RAS Precharge bits. These bits control the minimum number of clocks the RAS

signal is precharged between bus cycles. Table 3-3 shows the encoding for these bits.

Table 3-2. Precharge Bit Encodings

PRECHARGE CLOCKS

W1-W0—Wait state bits. These bits control the number of wait states required for DRAM

bank accesses. Table 3-3 shows the wait state bit encodings.

Table 3-3. Wait State Bit Encodings

WAIT STATES

WP1-WP0—Write Protect. This bit enables and disables write protection to a corresponding

DRAM bank.

0 = The corresponding DRAM bank may be written.

1 = Write access to the corresponding DRAM bank returns a bus error.

S/U1-S/U0—Supervisor/User. This bit determines whether the given DRAM bank decodes

to Supervisor Space (FC = 6 & 5) or both Supervisor and User (FC = 6 & 5 & 1 & 2) Space.

0 = Respond to Supervisor accesses only

1 = Respond to Supervisor and User Space.

3.4 DRAM REFRESH REGISTER (DRFRSH)

This register controls the operation of the refresh circuitry and is initialized to zero on

hardware reset.

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Bits 15–8—Reserved. Should be written to zero by the host processor. These bits are

always read as zero.

R7-R0—Refresh Count Bits. The value stored in these bits is multiplied by 16 system clocks

to determine the refresh period. The divide by 16 scheme provides sufficient range to

address systems operating with standard DRAM at frequencies less than 2 Mhz as well as

systems utilizing low power DRAM running at frequencies greater than 25 Mhz. All zeroes

correspond to 4096 system clocks.

3.5 DRAM BASE ADDRESS REGISTER (DBA1-DBA0)

The base address registers for DRAM are two 16-bit registers which are initialized to zero

at hardware reset. These registers hold both the base address of each bank and mask bits

for determining which address bits initiate bus cycle accesses to the DRAM banks.

A23 A22 A21 A20 A19 A18 A17

M22 M21 M20 M19 M18 M17

A23-A17—Base Address Bits. The Base Address Bits determine where the DRAM bank is

located on 128 kbyte boundaries. These bits are compared with the corresponding

addresses generated by the MC68EN302 to determine if a given bus cycle accesses a

particular DRAM bank. These bits are used in conjunction with the Mask Bits to determine

the size and location of a given DRAM bank.

Bits 8–7—Reserved. Should be written to zero by the host processor. These bits are always

read as zero.

M22-17—Mask Bits. These bits are used in conjunction with the Base Address Bits to

determine the size and location of a given DRAM bank.

0 = The corresponding address bit is ignored.

1 = The address compare logic uses the corresponding address bit when determining

if a bus cycle access occurs within the DRAM bank.

V—Valid Bit. This bit is cleared to 0 at hardware reset.

0 = This DRAM bank is not valid

1 = Data for the corresponding DRAM bank data is valid, and DRAM accesses are

decoded by that bank’s circuitry.

3.6 DRAM CONTROL MODULE OPERATION

3.6.1 Reset Operation

Refresh accesses continue if the Ethernet module is reset and during the Reset Instruction

(soft reset), but not during system (hardware) reset.

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3.6.2 Read and Write Cycle Operation

Figure 3-1 shows two consecutive 4-clock accesses with a 2-clock precharge of RAS. RAS

is negated one clock before CAS to provide a longer precharge time between consecutive

hits in a given bank.

CLOCK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7

ADDR

RAS

CAS

DRAMRW

DATA/

PARITY

UDS/LDS

AMUX

Figure 3-1. Consecutive Four-Clock Accesses

In some cases, a DRAM access is not possible in a 4-clock cycle. In still other cases, the

precharge time of 2 clocks is not enough for the given DRAM. Figure 3-2 shows two

consecutive 5-clock accesses, with a 3-clock RAS precharge. Note that the DRAM signals

are delayed in the second cycle with respect to the processor bus signals, allowing a longer

RAS precharge time.

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CLOCK

ADDR

RAS

S0 S1 S2 S3 S4

S5 S6 S7 S0 S1 S2 S3 S4

S5 S6 S7

CAS

DRAMRW

DATA/

PARITY

UDS/LDS

AMUX

Figure 3-2. Five-Clock Accesses with Three-Clock Precharge

3.7 REFRESH OPERATION

The MC68EN302 supports CAS before RAS refresh but note that refresh operation is not

synchronized to the bus activity. A special DRAMRW (Read/Write) pin is provided so that

refresh may occur regardless of the state of the processor bus. Only active bus cycles

operating in the DRAM banks will prevent a refresh cycle. Refresh occurs in both banks

simultaneously.

DRAM refresh is initiated during an idle state between bus cycles or during a bus cycle

which does not access the DRAM. If refresh is required concurrent with a DRAM access,

the MC68EN302 will perform the access while holding off the refresh. After the MC68EN302

initiates a refresh cycle, it must hold off DRAM accesses by inserting wait states until the

RAS precharge is complete following the refresh cycle.

Figure 3-3 shows a refresh cycle. In this case, there is a DRAM access waiting on the bus

and the DRAM access must wait until after RAS precharge.

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CLOCK

ADDR

RAS

S0 S1 S2 S3 S4

S5 S6 S7

CAS

DRAMRW

UDS/LDS

AMUX

Figure 3-3. Precharge With DRAM Access Active

3.8 DRAM CONTROLLER I/O

3.8.1 Control Signal Pins

The EN302 contains 8 DRAM specific signal pins: CAS1–CAS0, RAS1–RAS0, AMUX, and

DRAMRW.

3.8.2 Column Address Strobes (CAS1–CAS0)

These active low pins allow seamless interface to column address strobe (CAS) inputs on

industry standard DRAM, providing CAS for both bank 0 and bank 1 of the DRAM controller.

Two strobes support byte operations on the external 16-bit bus. CAS0 corresponds to data

pins D15-D8. CAS1 corresponds to data pins D7–D0.

3.8.3 Row Address Strobes (RAS1–RAS0)

These active low pins allow seamless interface to row address strobe (RAS) inputs on

industry standard DRAM, providing RAS for both bytes of a given DRAM bank. A particular

bank corresponds to specific base address and control information programmed in the

MC68EN302 DRAM control registers (see 3.2 Memory Map for a description). RAS0

corresponds to bank 0 and RAS1 corresponds to Bank 1.

3.8.4 DRAM Read/Write (DRAMRW)

This active low pin is asserted to signify that a DRAM write cycle is occurring. It is separate

from the processor bus R/W so that precharge takes place without regard to the state of R/

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3.8.5 Address Mux (AMUX)

The AMUX pin is provided for implementing external address muxing circuitry so that

external masters may access DRAM modules controlled by the MC68EN302 DRAM

controller. External address muxing must take place in this situation since an access to the

MC68EN302 as a slave always results in the addresses driven as an input, and does not

output addresses to the DRAM module.

Another use for the AMUX pin would be implementations in which a linear DRAM space is

required.

3.8.6 Parity (PARITY1–PARITY0)

These two pins are provided to support parity checking of DRAM. If enabled, parity is

generated on writes and checked on reads. A parity error on a read generates a bus error.

PARITY0 is used in connection with D15–D8 and PARITY1 is used in connection with D7–

D0.

Parity checking/generation is not supported for external bus masters.

3.8.7 Muxing Scheme

To provide a simplified implementation of the Address Mux, a unique muxing scheme is

provided. Rather than providing programmability to change which addresses are muxed on

a particular signal, a generic muxing scheme is provided so that one muxing scheme may

be utilized by all supported DRAM bank sizes. Table 3-3 shows the DRAM muxing scheme.

The usage listed in the table is for typical operation. It is possible that some users may utilize

the Base Address Registers and the Mask bits in a non-standard way.

Table 3-4. Address Muxing Scheme

PROCESSOR

ADDRESS

COLUMN

ADDRESS

ROW ADDRESS

USAGE

Used for all Bank Sizes

A10

A11

A12

A13

A14

A15

A16

A18

A20

A22

Used for 512K and up

Used for 2M and up

Used for 8M

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SECTION 4

ETHERNET CONTROLLER

The MC68EN302, like the MC68360 QUICC, provides full duplex Ethernet along with

multiprotocol support on the SCC channels. On the MC68EN302, the Ethernet controller is

independent of the CPM and therefore the MC68EN302 provides the Ethernet channel in

addition to the pre-existing 302 SCC channels without sacrificing any SCC pins. The

Ethernet controller consists of an 802.3/Ethernet MAC layer protocol machine with an

internal CAM, transmit and receive FIFOs, buffer descriptor memory and a dual channel

DMA controller. The buffer descriptor memory, CAM and DMA controller all interface to the

module bus. A block diagram of the Ethernet controller is shown in Figure 4-1.

Features are:

• 802.3 Ethernet compliant MAC layer (1-10 Mbps) with industry standard interface

• Full-duplex operation

• 128 byte transmit and receive FIFOs

• Collision retry does not generate extra bus bandwidth

• Collision fragments automatically discarded

• 64 entry CAM with optional hash mode

• Buffer descriptor memory on-chip

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ETHERNET Controller

MODULE BUS

SYSTEM

INTERFACE

TX/RCV

DMA

CONTROL

STATUS

REGISTERS

DESCRIPTOR

DUAL-PORT

RAM

BUFFER

DESCRIPTOR

CONTROL

TRANSMIT

STATUS

TRANSMIT

FIFO

RECEIVE

FIFO

ADDRESS

ETHERNET

PROTOCOL

MACHINE

RECOGNITION

DUAL-PORT

RAM

PHYSICAL LAYER SERIAL INTERFACE

Figure 4-1. Ethernet Controller Block Diagram

4.1 REGISTER DESCRIPTION

Table 4-1 describes the Ethernet controller memory map.

Table 4-1. Ethernet Controller Memory Map

ADDRESS

MOBA + 800

NAME

Ethernet Control Register

MNEMONIC

ECNTRL

TYPE

Read/Write

MOBA + 802

MOBA + 804

MOBA + 806

MOBA + 808

MOBA + 80A

MOBA + 80C

MOBA + 80E

MOBA + 810

MOBA + (812-9FF)

Ethernet DMA Configuration Register

Maximum Receive Buffer Length

Interrupt Vector Register

Interrupt Event

EDMA

EMRBLR

INTR_VECT

INTR_EVENT

INTR_MASK

ECNFIG

Interrupt Mask Register

Ethernet Configuration

Ethernet Test Register

Address Recognition Control Register

Reserved

ETHER_TEST

AR_CNTRL

MOBA + A00

MOBA + BFF

CAM Entry Table

CET

EBD

Read/Write

MOBA + C00

MOBA + FFF

Buffer Descriptors Table

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Bits in the registers are R/W unless noted otherwise. Unimplemented bits will return 0 on

reads. If reserved memory locations are accessed, DTACK is not returned.

4.1.1 ETHERNET CONTROL REGISTER (ECNTRL)

The ECNTRL register controls MC68EN302 Ethernet controller operation. All implemented

bits in this register are R/W. This register is $0000 following system reset.

GTS ETHER_EN RESET

15–3 Reserved. Should be written to zero by the host processor. These bits are always

read as zero.

GTS—Graceful Transmit Stop.

0 = No change in Ethernet controller operation

1 = The Ethernet controller will stop transmission after all frames that are currently

being transmitted have completed. See GRA in 4.1.5 Interrupt Event Register

(INTR_EVENT).

ETHER_EN—Ethernet Enable.

0 = Reception is immediately stopped and transmission ends following the appending

of a bad CRC to any frame currently being transmitted. Buffer descriptor(s)

corresponding to an aborted transmit frame are not updated following ETHER_EN

deassertion. In this situation, the DMA, buffer descriptor and FIFO control logic is

reset along with the buffer descriptor and FIFO pointers.

1 = The Ethernet controller is enabled and reception and transmission of frames may

occur.

RESET—Ethernet Controller Reset.

0 = A reset is performed locally within the Ethernet controller. ETHER_EN is cleared

and all other Ethernet controller registers take their reset values. During Ethernet

controller reset, the Buffer Descriptor Table and the CAM Entry Table can not be

read or written. Any transmission/reception currently in progress is abruptly

aborted.

1 = The MC68EN302 Ethernet controller operates normally

4.1.2 ETHERNET DMA CONFIGURATION STATUS REGISTER (EDMA)

The EDMA register allows user control of the DMA unit and may be written only when the

ETHER_EN bit in the ECNTRL register is cleared. This register is cleared by a hardware

reset.

BDERR<6:0>

BDSIZE<1:0> TSRLY WMRK<1:0>

BLIM<2:0>

BDERR 6–0—Buffer descriptor error number.

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This read only field is the buffer descriptor number that was being accessed when a bus

error occurred. See 4.1.5 Interrupt Event Register (INTR_EVENT) for a description of the

bus error handling.

Bit 8—Reserved. Should be written to zero by the host processor. This bit is always read as

zero.

BDSIZE1-0—Buffer descriptor size. (R/W)

00 = 8 transmit buffer descriptors, 120 receive buffer descriptors

01 = 16 transmit buffer descriptors, 112 receive buffer descriptors

10 = 32 transmit buffer descriptors, 96 receive buffer descriptors

11 = 64 transmit buffer descriptors, 64 receive buffer descriptors

BDSIZE controls the allocation of the44 128 on-chip buffer descriptors between the

transmit and receive operations. Typical implementations will set BDSIZE(1–0) to 01

allowing 16 transmit buffer descriptors and 112 receive descriptors.

TSRLY—Transmit start early. (R/W)

TSRLY controls when the transmission of a frame will begin. Typical applications will set

TSRLY to 0.

0 = Frames do not begin transmitting until the transmit FIFO has only WMRK bytes

available (empty), where WMRK ranges from 96 to 120 bytes.

1 = The frame will begin transmitting after the WMRK number of bytes have been

written to the transmit FIFO where WMRK ranges from 8 to 32 bytes. This requires

low bus latency to avoid transmit FIFO underrun.

BYTES IN TRANSMIT FIFO AT

START OF TRANSMISSION

TSRLY

WMRK<1:0>

120

112

104

WMRK1–0—FIFO Watermark. (R/W)

00 = 8 FIFO bytes present or available

01 = 16 FIFO bytes present or available

10 = 24 FIFO bytes present or available

11 = 32 FIFO bytes present or available

The FIFO Watermark is used to control the start of a DMA burst. In the receive direction, the

DMA state machine waits for either an end-of-frame (EOF) or a WMRK number of bytes to

be in the receive FIFO prior to beginning a DMA burst of data out of the MC68EN302 to the

host bus. In the transmit direction, the DMA state machine waits for WMRK number of bytes

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of space to be available in the transmit FIFO prior to beginning a DMA burst into the

MC68EN302 transmit FIFO. WMRK is typically set to 16.

WMRK1–WMRK0, when used in conjunction with BLIM2–BLIM0, allows the system

designer to configure the MC68EN302 device for expected bus latency.

BLIM2–BLIM0—Burst Limit. (R/W)

BLIM2–BLIM0 controls the maximum length of a DMA burst in accesses from the bus

interface unit. BLIM is typically set to 8 for 16 bit systems.

000 = 1 Access

001 = 2 Accesses

010 = 4 Accesses

011 = 8 Accesses

100 = 16 Accesses

101 = 32 Accesses

110 = 64 Accesses

111 = Unlimited

4.1.3 ETHERNET MAXIMUM RECEIVE BUFFER LENGTH (EMRBLR)

The EMRBLR register determines the maximum size of all receive buffers. Because the

maximum frame is limited to 1518, only bits 10–0 are written by the user. The value written

into the maximum receive buffer length register must account for the receive CRC which is

always written into the last receive buffer. To allow one maximum size frame per buffer,

EMRBLR must be set to 0000010111101110 or larger. The EMRBLR must be evenly

divisible by 2. To ensure this, bit 0 is forced low. Only non-zero values are considered to be

valid, therefore this register should be written after reset, but before Ethernet operation is

enabled. All implemented bits are R/W. This register is cleared upon a hardware reset.

MAXIMUM RECEIVE BUFFER LENGTH

5–11—Reserved.

Should be written to zero by the host processor. These bits are always read as zero.

MRBL—Maximum receive buffer length.

Must be programmed to a non-zero value for operation.

0—Reserved.

Must be written as zero by the host processor. This bit is always read as zero.

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4.1.4 INTERRUPT VECTOR REGISTER (IVEC)

The IVEC register controls the interrupt vector generated by the Ethernet controller during

an interrupt acknowledge cycle. This register can only be written when the ETHER_EN bit

in the ECNTRL register is cleared. This register is reset to $000F.

INV<7:0>

15–8—Reserved.

Should be written to zero by the host processor. These bits are always read as zero.

VG—Vector Granularity.

0 = The interrupt vector is not modified to reflect the cause of the interrupt.

1 = The interrupt vector is modified to indicate the cause of the interrupt, replacing the

lower two bits of the interrupt vector according to the following table:

INTERRUPT VECTOR1–0

CAUSE

EXAMPLES

Receive Interrupt

RFINT, RXB

Transmit Interrupt

TFINT, TXB

HBERR, BABR, BABT, GRA, BOD, EBERR

BSY

Non-Time Critical Interrupt

Time Critical Interrupt

If multiple interrupt sources are present simultaneously and VG = 1, the INV bits will be set

based on the following priority (highest ot lowest);

1. Time critical interrupt.

2. Receive interrupt

3. Transmit interrupt

4. Non-time critical interrupt.

For example, if both RXB and TFINT interrupts are asserted, INV1–INV0 will equal 00.

Interrupt Vector1–0 represent the values of the two lower bits placed on the data bus during

an interrupt acknowledge cycle. VG is cleared by reset.

INV7–0—Interrupt Vector.

INV is the eight bit vector that the Ethernet controller places on the low byte of the data bus

during an interrupt acknowledge cycle.

4.1.5 INTERRUPT EVENT REGISTER (INTR_EVENT)

When an event occurs that sets a bit in the Interrupt Event Register, and the corresponding

bit in the interrupt mask register (INTR_MASK) is set, an interrupt will be generated. To clear

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a bit in INTR_EVENT, a one must be written to that bit position. Writing a zero will not

change the value of the bit. This register is cleared upon a hardware reset.

HBERR BABR BABT GRA BOD EBERR TFINT RFINT BSY TXB RXB

15–11—Reserved. Should be written to zero by the host processor.

HBERR—Heartbeat Error.

When HBC is set, a Heartbeat was not detected within the Heartbeat window following a

transmission.

BABR—Babbling Receiver Error.

Indicates a frame longer than 1520 bytes was received. According to 802.3, frames should

not exceed 1518 bytes but two bytes of slop is allowed. Receive frames exceeding 1520

bytes in length are truncated to prevent receive buffer overflow.

BABT—Babbling Transmitter Error.

The transmitted frame length has exceeded 1520 bytes. This condition is usually caused by

a frame that is too long being placed into the transmit data buffer(s).

GRA—Graceful Stop Complete.

A graceful stop, initiated by the setting of GTS, is now complete. Once the frame that was

in progress when GTS was set has transmitted, this bit is set. If the start of a second frame

is in the FIFO, GRA will be set after the transmission of the second frame. GRA is also set

after EBERR.

BOD—BackOff Done.

Indicates that the backoff timer has expired. This interrupt is used only for production testing

and should normally be ignored. (Set BODEN = 0)

EBERR—Ethernet Bus Error occurred.

Indicates that a bus error occurred when the Ethernet controller was bus master. The

BDERR bits in the EDMA register indicate which buffer descriptor was being used at the

time of the bus error. Once any frames currently in the transmit FIFO have completed

transmission and their status is written to the appropriate buffer descriptor, the GRA bit is

set. If no frames or only a partial frame is in the transmit FIFO, the GRA bit is set immediately

causing the partial frame to become an underrun truncated with a bad CRC.

TFINT—Transmit Frame Interrupt.

Indicates that a frame has been transmitted and that the last corresponding buffer descriptor

has been updated.

RFINT—Receive Frame Interrupt.

Indicates that a frame has been received and that the last corresponding buffer descriptor

has been updated.

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BSY—Busy Interrupt.

Indicates that the start of a frame was detected but a receive buffer was not available in

which to put the frame. If not corrected, this results in a FIFO overflow, which is indicated by

the OV bit in the receive buffer descriptor.

TXB—Transmit Buffer Interrupt.

Indicates that a transmit buffer descriptor with the I bit set in its status word has been

updated.

RXB—Receive Buffer Interrupt.

Indicates that a receive buffer descriptor with the I bit set in its status word has been

updated.

4.1.6 INTERRUPT MASK REGISTER (INTR_MASK)

The Interrupt Mask register provides control over which Ethernet controller events generate

an actual interrupt. The Interrupt Mask register is cleared on a hardware reset.

HBEEN BREN BTEN GRAEN BODEN EBERREN TFIEN RFIEN BSYEN TBIEN RBIEN

15–11—Reserved.

Must be written to zero by the host processor.

HBEEN—Heartbeat Error Interrupt Enable.

Enable interrupts when HBERR is set

BREN—Babbling Receiver Interrupt Enable.

Enable interrupts when BABR is set

BTEN—Babbling Transmitter Interrupt Enable.

Enable interrupts when BABT is set.

GRAEN—Graceful Stop Interrupt Enable.

Enable interrupts when GRA is set

BODEN—BackOff Done Enable.

Enable interrupts when BOD is set. This bit should always be cleared.

EBERREN—Ethernet Controller Bus Error Enable.

Enable interrupts when EBERR is set.

TFIEN—Transmit Frame Interrupt Enable.

Enable interrupts when TFINT is set.

RFIEN—Receive Frame Interrupt Enable.

Enable interrupts when RFINT is set.

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BSYEN—Busy Interrupt Enable.

Enable interrupts when BSY is set.

TBIEN—Transmit Buffer Interrupt Enable.

Enable interrupts when TBINT is set.

RBIEN—Receive Buffer Interrupt Enable.

Enable interrupts when RBINT is set.

4.1.7 ETHERNET CONFIGURATION (ECNFIG)

The Ethernet Configuration register provides protocol configuration information to the

Ethernet controller and can be written only when the ETHER_EN bit in the ECNTRL register

is clear. This register is cleared on a hardware reset.

RDT HBC FDEN LOOP

15–4—Reserved.

Should be written to zero by the host processor. These bits are always read as zero.

RDT—Receive Disable on Transmit

0 = Receive path operates independently of transmit.

1 = Disable reception of frames while transmitting.

The purpose of this bit is to block reception of frames while this node is transmitting. If FDEN

= 1, this bit must be 0.

If FDEN = 0, this bit should be 1, except when:

1. LOOP = 1 to select internal feedback.

2. An external loopback is being performed.

3. This node wants to receive its own transmit frames for monitoring purposes.

HBC—HeartBeat Control.

0 = The heartbeat check is not performed. Following end of transmission, the HB bit in

the TxBD will be cleared.

1 = The heartbeat check is performed. Following end of transmission, if CLSN is not

asserted during the heartbeat window, the HB bit in the TxBD will be set.

FDEN—Full Duplex Enable.

0 = Carrier Sense and Collision inputs are active, deference and collision handling is

according to IEEE 802.3

1 = Frames are transmitted independent of Carrier Sense and Collision inputs.

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LOOP—Loopback.

0 = No loopback operation is performed

1 = Transmitted frames are looped back internal to the device and TENA remains

inactive (low).

4.1.8 ETHERNET TEST (ETHER_TEST)

The Ethernet Test register controls various manufacturing test modes. Test modes may be

useful to some users, but in general it is not suggested that the user set these modes in

normal operation. This register can only be written when the ETHER_EN bit in the ECNTRL

RNGT TBO TRND SLOT COLL DRTY RWS TWS

15–8—Reserved.

Must be written to zero by the host processor. These bits are always read as zero.

RNGT—Random number generator test.

This bit allows testing of the random number generation logic used in the transmit backoff

process. To run the random number generator test, write $0080 to this register and then poll

repeatedly. This bit will be changed by hardware from 1 to 0 within 15 µsec if the random

number generator is operating properly.

TBO—Test Backoff.

0 = Normal operation of the random number generator logic.

1 = The random number generated by the transmit backoff logic is all ones.

TRND—Transmit random number control.

0 = An internal oscillator clocks the random number generator (normal mode).

1 = The transmit clock is used to generate the Ethernet random number.

SLOT—Slot Time Length.

Specifies the number of bytes in a slot time used in backoff determination.

0 = The number of bytes in a slot time is 64.

1 = The number of bytes in a slot time is 2.

COLL—Force Collision.

COLL allows the collision logic to be tested. The device must be in the internal loopback

mode for COLL to be valid.

0 = No collision is forced.

1 = A collision is forced during the subsequent transmission attempt. This results in 16

total transmission attempts with a retry error reported in the transmit descriptor.

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DRTY—Disable Retry.

0 = The MC68EN302 performs retry error reporting normally.

1 = The MC68EN302 does not perform any retries of a frame before reporting a retry

error in the transmit descriptor for the frame.

RWS—Receive Watchdog Timer Short.

0 = The Receive Watchdog Timer operates normally

1= The Receive Watchdog Timer is short cycled for test purpose causing the Receive

Watchdog Timer to expire, and a BABR interrupt to be generated if more than 100

bytes in a frame are received.

TWS—Transmit Watchdog Timer Short.

0 = The Transmit Watchdog Timer operates normally.

1 = The Transmit Watchdog Timer is short cycled for test purposes causing the

Transmit Watchdog Timer to expire and a BABT interrupt to be generated if more

than 100 bytes in a frame are transmitted.

4.1.9 AR CONTROL REGISTER (AR_CNTRL)

The AR Control register controls AR memory operation and can be written only when the

ETHER_EN bit in the Control register is clear. Bits in this register are not changed if the

ETHER_EN bit in the Control register is set. This register is set to the value $0000 on a

reset.

HASH_EN INDEX_EN MULT1–MULT0 PA_REJ PROM

HASH_EN—Hash mode enable.

0 = Perfect-entry match mode is selected for all entries

1= Hash mode is enabled instead of perfect matches on entries 62 and 63.

INDEX_EN—Index enable.

0 = The receive buffer data pointer is unmodified

1= Pass either line number or hash index into the upper byte of the receive buffer

descriptor’s data pointer.

MULT1–MULT0—Multicast and broadcast reception control.

MULT controls whether multicast frames are received. Broadcast is the special multicast

address of all ones.

MULT1–MULT0]

ACCEPT MULTICAST?

If match in tables

Yes, all

ACCEPT BROADCAST?

Yes

No, none

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PA_REJ—Physical address reject.

0 = Frames with physical addresses are accepted if there is a table match, either

perfect or hash.

1 = Frames with physical addresses are accepted if there is no perfect match. If a

physical address has a hash match but not a perfect match, the frame will be

accepted. This bit has no effect on frames with a multicast address.

PROM—Promiscuous mode.

0 = Frames are accepted only if they meet the hashing, perfect address match, or

MULT1–MULT0 criteria

1 = All frames are accepted regardless of address matching or settings of MULT1–

MULT0.

9–0—Reserved.

Should be written as zero by the host processor. These bits are always read as zero.

4.2 ETHERNET BUFFER DESCRIPTORS

The data for the Ethernet frames must reside in memory external to the MC68EN302 device

and is placed in one or more buffers. Buffer descriptors contain pointers to each buffer and

contain the current state of the buffer. The BDs are located inside the MC68EN302 in the

dual port Buffer Descriptor RAM so that the load on the processor bus is minimized.

Software “produces” buffers by allocating/initializing memory and initializing buffer

descriptors in the BDRAM. Setting the most significant bit (R for transmit and E for receive)

in the most significant word of the buffer descriptor initializes the buffer. MC68EN302 DMA

hardware constantly polls the BDs and processes the buffers after they have been

initialized. Processing in the case of transmit indicates that the data in the buffers has been

read into the MC68EN302 and transmitted out the Ethernet interface. Processing in the case

of receive indicates that data received from the Ethernet interface has been placed into data

buffers pointed to by the receive buffer descriptors. Once DMA is complete and the buffer

descriptor status bits have been written, the most signficant bit of the buffer descriptor is

cleared indicating that the buffer has been processed. Software may either poll the BDs or

may rely on the buffer/frame interrupts to detect when the buffers have been consumed.

The ETHER_EN signal operates as a reset to the BD/DMA logic. When ETHER_EN is

deasserted, the BD pointers are reset to point to the starting transmit and receive BDs. The

buffer descriptors are not initialized by hardware during reset. For proper operation, before

setting the ETHER_EN bit, initialize at least one transmit and receive buffer descriptor by

setting the most significant word of the descriptor to $0000 (this does not result in any

transmit or receive operation, but is considered to be initialization). Because the DMA polls

buffer descriptor memory to determine if the R/E bits in the next available BD are set

whenever ETHER_EN=1, initializing ‘n’ buffers, requires software to initialize n+1 buffer

descriptors, setting the most significant bit of the (n+1) descriptor to 0.

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The BDSIZE field in the EDMA register allows the user to define up to sixty-four buffers for

the transmit channel and up to one hundred twenty buffers for the receive channel. The total

number of combined transmit and receive buffers is one-hundred-twenty-eight. Each BD

table, transmit and receive, forms a circular queue with separate transmit Buffer Descriptor

and receive Buffer Descriptor pointers maintained in the hardware. The length of the circular

queues may also be controlled by using the W (wrap) bit in the buffer descriptors.

If the transmit FIFO empties of data before the end of the frame, an underrun occurs and a

bad CRC is appended to the partially transmitted data. In addition, the UN bit is set in the

last BD of the affected frame. Transmit underrun may occur if the Ethernet controller can not

access the 68000 bus or if the next BD in the frame is not available.

During the receive process, if data from a frame is available but no BD is available, the BSY

interrupt is generated, warning the user that data will soon be lost if a BD does not become

available. If the receive FIFO overruns because there is no available BD or the Ethernet

controller can not access the 68000 bus, then the last BD for the receive frame will have the

OV bit set.

4.2.1 ETHERNET RECEIVE BUFFER DESCRIPTOR (RX BD)

The user initializes the E, W, I, and (optionally) RO bits in the first word and the pointer in

3rd and 4th words of the receive buffer descriptor. The Ethernet controller writes the

following status bits:

• First word: E, L, F, M, LG, NO, SH, CR, OV and CL bits. The M, LG, NO, SH, CR, OV

and CL bits in the first word of the buffer descriptor are only modified by the Ethernet

controller when the L bit is set

• Second word: the buffer length

• Third word: the Reason and ARIndex fields if the INDEX_EN bit in the AR_CNTRL

15 14 13 12 11 10

Offset + 0

Offset + 2

Offset + 4

Offset + 6

RO W

LG NO SH CR OV CL

Data Length

Reason

ARIndex

A23–A16

Rx Data Buffer Pointer - A15–A0

Figure 4-2. Ethernet Receive Buffer Descriptor (Rx BD)

The first word of the receive buffer descriptor contains status and control information

concerning buffer descriptor handling and data flow. These status and control bits are

described in the following paragraphs.

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E—Empty, written by Ethernet controller (=0) and user (=1).

0 = The data buffer associated with this BD has been filled with received data. A

receive buffer descriptor also has the E bit set to 0 when data reception has been

aborted due to an error condition. When E is set to 0, the status, length, reason and

AR Index fields are updated according to the event that just occured during

reception.

1 = The data buffer associated with this BD is empty, or reception is currently in

progress.

RO—Receive Buffer Software Ownership, written by user.

This bit is provided as a software ownership bit, if needed. Hardware does not alter the value

of this bit.

W—Wrap (Final BD in Table), written by user.

0 = This is not the last buffer descriptor in the Rx BD table.

1 = This is the last buffer descriptor in the Rx BD table. After this buffer has been used,

the Ethernet controller receives incoming data into the first BD in the table, allowing

the user to use fewer buffer descriptors than the number programmed by BDSIZE.

I—Interrupt, written by user.

0 = No interrupt is generated after this buffer has been filled.

1 = The RBINT bit in the interrupt event register is set when this buffer has been

completely filled by the Ethernet controller, indicating that the internal 68000 core

is free to process the buffer.

L—Last in Frame, written by Ethernet controller.

0 = The buffer is not the last in a frame.

1 = The buffer is the last in a frame.

F—First in Frame, written by Ethernet controller.

0 = The buffer is not the first in a frame.

1 = The buffer is the first in a frame.

M—Miss, written by Ethernet controller.

This bit is set by the Ethernet controller when the incoming frame is not matched by the

internal address recognition but is accepted because the Ethernet controller is operating in

promiscuous mode (PROM=1). The user can monitor the M-bit to quickly determine whether

the incoming frame was destined to this station. This bit is valid only if the L-bit is set. The

M-bit is valid even if INDEX_EN is not set.

0 = An address match in the CAM or hash algorithm caused frame reception.

1 = No address match occured on the received frame - promiscuous mode operation

caused frame reception.

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LG—Rx Frame Length Violation, written by Ethernet controller.

A frame length greater than 1520 (maximum allowed receive frame length) was recognized.

In this situation, note that only the first 1520 bytes are written to the data buffer. This bit is

valid only if the L-bit is set. This frame should be discarded.

NO—Rx Nonoctet Aligned Frame, written by Ethernet controller.

The received frame contained a number of bits which is not a multiple of 8, and the CRC

check that occurred at the preceding byte boundary generated an error. This bit is valid only

if the L-bit is set. If this bit is set, the CR bit will not be set. This frame should be discarded.

SH—Short Frame, written by Ethernet controller.

The MC68EN302 does not support SH and this bit is always cleared. This bit indicates that

a frame length less than the minimum defined for this channel was recognized. This frame

should be discarded.

CR—Rx CRC Error, written by Ethernet controller.

This frame contains a CRC error and is an integral number of octets in length. This bit is

valid only if the L-bit is set. This frame should be discarded.

OV—Overrun, written by Ethernet controller.

A receive FIFO overrun occurred during frame reception. During a FIFO overflow, the status

bits also in this word (M, LG, NO, SH, CR, and CL) lose their normal meaning and are zero.

This bit is valid only if the L-bit is set. This frame should be discarded.

CL—Collision, written by Ethernet controller.

A collision occurred during frame reception and the frame was closed. This bit is set only if

a late collision occurred. This bit is valid only if the L-bit is set. This frame should be

discarded.

Data Length, written by Ethernet controller.

Data length indicates the number of octets written by the Ethernet controller into this BD’s

data buffer. It is written by the Ethernet controller upon the close of this BD.

Reason and ARIndex, written by Ethernet controller.

If INDEX_EN=1 in the AR_CNTRL register, then the Reason and ARIndex fields replace the

most significant byte of the Rx Buffer Pointer. The Reason and ARIndex are available on all

buffer descriptors for a frame when INDEX_EN is set, independent of the condition of the L

and F bits. When INDEX_EN = 0 the Reason and ARIndex fields are not modified by

hardware.

Rx Buffer Pointer, written by user.

The receive buffer pointer always points to the first location of the associated data buffer and

must be a multiple of 2. The data buffer must reside in memory external to the Ethernet

controller. When INDEX_EN=1, the most significant byte of the receive buffer pointer is

replaced by a reason and index field. When INDEX_EN=0, the receive buffer pointer is not

modified. See 4.6.1 Buffer Descriptor Modification for more details.

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4.2.2 ETHERNET TRANSMIT BUFFER DESCRIPTOR

Transmit data is presented to the Ethernet controller through buffers referenced by transmit

Buffer Descriptors. The Ethernet controller confirms transmission operation through the R

bit, and indicates error conditions through the other status bits in the most signficant word

of the BD. The host software must initialize the R, W, I, L, TC, and (optionally) TO bits in the

first word, the length in the second word, and the buffer pointer in the third and fourth words.

15 14 13 12 11 10

Offset + 0

Offset + 2

Offset + 4

Offset + 6

TO W

TC DEF HB LC RL

Data Length

UN CSL

Unused

Tx Data Buffer Pointer - A15–A0

A23–A16

Figure 4-3. Ethernet Transmit Buffer Descriptor (Tx BD)

The Tx BD fields are detailed below. The unused bits (15-8) in Offset + 4 are not used by

the hardware. These unused bits are R/W by software and are ignored by hardware.

R—Ready, written by Ethernet controller and user.

0 = The data buffer associated with this BD is not ready for transmission, leaving the

software free to manipulate this BD or its associated data buffer. The Ethernet

controller clears this bit after the buffer has been transmitted or after an error

condition is encountered.

1 = The data buffer, which has been prepared for transmission by the user, has not

been transmitted or is currently being transmitted. No fields of this BD may be

written after this bit is set.

TO—Transmit Buffer Software Ownership, written by user.

This bit is provided as a software ownership bit, if needed. Hardware does not alter the value

of this bit.

L— Last (Last BD for this frame)

0 = This is not the last BD for this frame and the Ethernet controller sets R= 0 when the

buffer has been DMA’d into the MC68EN302. Status bits are not modified.

1 = The Ethernet controller sets R = 0 and modifies the DEF, HB, LC, RL, RC, UN and

CSL status bits once the buffer has been DMA’d into the MC68EN302 and frame

transmission has completed

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W—Wrap (Final BD in Table), written by user.

0 = This is not the last buffer descriptor in the Tx BD table.

1 = This is the last buffer descriptor in the Tx BD table. After this buffer has been used,

the Ethernet controller transmits data from the first BD in the table. The maximum

number of Tx BDs in this table is programmable through the BDSIZE bits.

I—Interrupt, written by user.

0 = No interrupt is generated after this buffer has been serviced.

1 = TBINT is set in the Ethernet event register after this buffer has been serviced. If

enabled through the mask register, this bit can cause interrupts to the host.

L—Last in Frame, written by user.

0 = The buffer is not the last in the transmit frame.

1 = The buffer is the last in the transmit frame.

TC—Tx CRC, written by user (only valid if L = 1).

0 = End transmission immediately after the last data byte.

1 = Transmit the CRC sequence after the last data byte.

DEF—Defer Indication, written by Ethernet controller (only valid if L = 1).

The Ethernet controller had to defer while attempting frame transmission. DEF is not set if

a collision occurs during transmission.

HB—Heartbeat Error, written by Ethernet controller (only valid if L = 1).

The collision input was not asserted within the heartbeat window after transmit completion.

HB may be set only if HBC is not set in the ECNFIG register.

LC—Late Collision, written by Ethernet controller (only valid if L = 1).

A collision has occurred after 56 data bytes have been transmitted. The Ethernet controller

terminates the transmission.

RL—Retransmission Limit, written by Ethernet controller (only valid if L = 1).

The transmitter has failed (Retry Limit + 1) attempts to successfully transmit a message due

to repeated collisions on the medium.

RC—Retry Count, written by Ethernet controller (only valid if L = 1).

These four bits indicate the number of retries required before this frame was successfully

transmitted. If RC = 0, then the frame was transmitted correctly the first time. If RC = 15,

then the frame was transmitted successfully while the retry count was at its maximum value.

If RL is set, then RC has no meaning.

UN—Underrun, written by Ethernet controller (only valid if L = 1).

A transmit FIFO underrun occurred while transmitting one or more of the the data buffers

associated with this frame. When FIFO underrun occurs, frame transmission halts once an

incorrect CRC is appended. The remaining buffer(s) associated with this frame are DMA’d

and dumped by the transmit logic.

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CSL—Carrier Sense Lost, written by Ethernet controller (only valid if L = 1).

Carrier sense dropped out or was never asserted during a collision free frame transmission.

Data Length, written by user.

Data length is the number of octets the Ethernet controller should transmit from this BD’s

data buffer. It is never modified by the Ethernet controller. The value of this field must be

greater than zero.

Tx Buffer Pointer, written by user.

The transmit buffer pointer containing the address of the associated data buffer, may be

even or odd. The buffer must reside in memory external to the MC68EN302. This value is

never modified by the Ethernet controller.

4.3 DMA AND BUFFER DESCRIPTOR LOGIC

The DMA and buffer descriptor modules transfer data between external memory and the TX/

RX FIFOs.

4.3.1 BUFFER DESCRIPTOR LOGIC

Buffer descriptors are stored in the on-chip dual-port RAM. The RAM is sufficient to store

128 buffer descriptors of 4 sixteen-bit-words. The features of the BD circuitry are as follows:

• Flexible Buffer Descriptor allocation between transmit and receive;

• Multiple buffers per frame

• Transmit buffers may start on any byte boundary, Receive buffers must start on even

byte boundaries.

• Maximum Receive Buffer size is user controllable;

The Buffer Descriptor space is divided between transmit and receive in various

configurations depending on the value of BDSIZE in the EDMA register. Table 4-2 shows

the starting and ending addresses (offset from MOBA) in the BD RAM for the four options.

Table 4-2. BD RAM Address Ranges

TRANSMIT BUFFER

DESCRIPTOR RANGE

$C00 - $C3F

RECEIVE BUFFER

DESCRIPTOR RANGE

$C40 - $FFF

NUMBER OF TRANSMIT NUMBER OF RECEIVE

BDSIZE

BUFFERS

$00

$01

$10

$11

120

112

$C00 - $C7F

$C80 - $FFF

$C00 - $CFF

$D00 - $FFF

$C00 - $DFF

$E00 - $FFF

The Maximum Receive Buffer Length field (MRBL) in the EMRBLR register determines the

default length of all receive buffers besides the last buffer of a frame (the last buffer is usually

shorter in length than the preceding buffers).

On the transmit side, the MC68EN302 may have up to two separate frames with open

buffers at a specific point in time. While the first frame completes the transmit process, DMA

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operaton begins for the second frame as the frame status of the first frame is determined.

Frame status is not available until after the 4 microsecond heartbeat window at the end of

transmission.

When ETHER_EN changes from 0 to 1, the transmit process starts at Buffer Descriptor+

$C00 and the receiver begins processing BDs at offset $C40, $C80, $D00, or $E00

depending on BDSIZE. When GTS (graceful transmit stop) is set, the transmitter halts once

any unfinished transmit frames have completed transmission and the Buffer Descriptors

have been updated. The transmitter then generates a GRA interrupt. When GTS is cleared

(0), the transmitter begins transmission with the next frame in the transmit queue.

4.3.2 DMA LOGIC

The DMA block transfers data between the FIFOs and the data buffers that Buffer

Descriptors point to. The DMA block must arbitrate for access to the module bus. Once the

module bus controller has received a grant for the 68000 bus, a module bus grant is passed

to the DMA controller. The DMA controller alternates between transmit and receive DMA,

passing over either one if there is no outstanding data.

If there is receive data but no available buffer to place the data in, a BSY (BUSY) interrupt

is generated.

Once a data flow direction is chosen between transmit and receive, the DMA machine

continues to read a word or byte until it releases the bus and returns to the idle state. The

DMA machine will release the bus on any of the following conditions:

• The burst limit counter is reached.

• An end of frame (EOF) has been reached.

• The receive FIFO has been emptied.

• The transmit FIFO has been filled.

• At the end of a buffer.

At the beginning or end of a buffer, a byte access occurs if necessary. Once the DMA

machine releases bus mastership, if additional data must be moved, the DMA machine

generates another bus request.

4.4 TRANSMIT AND RECEIVE FIFOS

The Ethernet controller contains separate 128-byte transmit and receive FIFOs organized

as 64 locations x 18 bits each with 16 bits for data and 2 for tag information. Each FIFO has

independent control logic allowing full duplex operation.

4.4.1 TRANSMIT FIFO

The transmit FIFO control logic provides flow control information to the transmit buffer

descriptor logic. The timing for new transmit DMAs depends upon the WMRK and TSRLY

bits in the EDMA register as well as the number of locations currently available in the FIFO.

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The transmit FIFO control logic provides a signal indicating data is available to the Ethernet

transmit protocol machine. If underflow occurs, the Ethernet transmit protocol machine will

handle aborting the frame (append a bad CRC) and flushing the remainder of the frame from

the FIFO.

If a collision occurs within the slot time in a transmit frame, the FIFO supports retry by

maintaining a separate start of frame pointer (read lag pointer). New data is never written on

top of start of frame data until the slot time has passed. Two control signals pass between

the Ethernet transmit logic and the transmit FIFO to indicate when the slot time (collision

window) has been passed (Transmit Accept) or when a collision retry must take place

(Transmit Retry).

4.4.2 RECEIVE FIFO

The receive FIFO control logic provides “data available” and “receive FIFO empty” flow

control signals to the receive DMA controller. The “data available” signal is asserted as a

function of the number of bytes available in the FIFO and the WMRK bits from the EDMA

into the receive BD. The frame should be discarded by software.

Data is written into the receive FIFO by the Ethernet receive logic in the case of status

information, and by the address recognition logic if the Reason and ARIndex fields are

enabled.

The receive FIFO control logic maintains a “start of frame” pointer that allows purging

collision fragments from the FIFO so that they need not be DMA’d. This purging of fragments

(runt frames less than 64 bytes long) is automatic and cannot be disabled.

4.5 ETHERNET PROTOCOL LOGIC

This block implements the MAC (media access control) sublayer of the IEEE 802.3

standard, supporting operation up to 10 Mbps compliant with both Ethernet and 802.3

standards. This logic is subdivided into transmit, receive and loopback/serial interface

sections.

4.5.1 ETHERNET TRANSMIT

The Ethernet transmiter block performs the following functions:

• Parallel to serial conversion of data

• Encapsulation of transmit frames

— Generation of preamble (PA) and start of frame delimiter (SFD)

— Transmits serial data from the transmit FIFO interface

— Pads short frames (with 0’s)

— Appends CRC, if required

— Appends bad CRC if required

— Appends JAM pattern (all 1’s)

• Transmit Protocol

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— Guarantees minimum inter-frame gap (IFG) of 9.6 µsec between CarrierSense

deasserted and next frame transmitted.

— Provides 8 byte PA + SFD

— Appends 32 bit JAM sequence (all 1’s) and start backoff timer upon collision

— Appends 32 bit CRC (if TC = 1) or bad CRC if aborting frame

— Defers to CarrierSense for 6 µsec, then ignores CarrierSense for 3.6 µsec during

InterFrameGap

— Collision Retry occurs under the 802.3 truncated binary exponential backoff

algorithm

— Detects a babbling transmission and generates BABT interrupt

— Aborts Frame transmission if Transmit FIFO underflow, ETHER_EN deassertion

during frame transmission, Collision Retry Limit exceeded, Late Collision or

Collision and DRTY = 1

• Provides Transmit Frame Status

— Generates the DEF, HB, LC, RL, RC, UN and CSL status fields written into the end

of frame transmit buffer descriptor which provide status on the transmission of the

frame. The definition of these fields is based on the Layer Management section of

the 802.3 standard. These fields are valid after the heartbeat window following the

successful transmission of a frame or if the collision retry limit (16 attempts) is

exceeded. A “XmitStatusReady” signal is asserted to the transmit buffer descriptor

control logic when this status is available

All logic in the Ethernet Transmit block runs synchronously with the Ethernet TCLK provided

by an external Ethernet physical layer component(s).

NOTE

Deasserting ETHER_EN during frame transmission is NOT

recommended as ETHER_EN is used as a reset signal in the

Ethernet controller logic. The recommended procedure is to

assert the GTS bit to gracefully halt transmission. Once the GRA

interrupt is received indicating that transmission has completed,

then deassert ETHER_EN.

4.5.2 ETHERNET RECEIVE

The receive block consists of the following submodules:

• Serial to Parallel Conversion

• Receive Protocol Control

— Controls data path by stripping PA, SFD, and dribble bits

— Detects runt frames, and signals REJECT to the receive FIFO

— Detects giant frames, generates the BABR interrupt and discards the rest of frame

— Provides count to determine frame length (in bytes)

— Provides for interframe recovery if a minimum receive interframe gap of

approximately 2.4 µsec is provided.

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• Receive Frame Status

— Generates the M, LG, NO, SH, CR, OV and CL status fields which are written into

the end of frame receive buffer descriptor to provide status on the reception of the

frame. The definition of these fields is based on the Layer Management section of

the 802.3 standard.

The serial interface consists of TCLK, TENA, TX, RCLK, RENA, RX and CLSN. The polarity

of the TENA, TX, RENA, RX and CLSN signals is positive (1 or asserted = Voh or Vih). Zero

or more RCLK cycles are required following the deassertion of RENA at the end of a receive

frame. Logic in this module will detect end of receive frame condition and switch in TCLK if

necessary to complete flushing the frame through the receive data path and into the receive

FIFO.

4.5.3 ETHERNET LOOPBACK

The transmit to receive loopback function is selected by the LOOP bit in the ECNFIG

and CLSN will be ignored.

4.6 ETHERNET AR (ADDRESS RECOGNITION)

The MC68EN302 supports 64-entry internal address recognition with 48 bit address

matching for receive address filtering. Address Recognition memory is written as a normal

memory cycle. Note that unused entries in the AR memory map do not return DTACK if

accessed.

There are two modes for address recognition: perfect entries, and hash mode. The mode

selected determines the way in which memory is partitioned. When perfect-entry mode is

selected, the entire memory is devoted to storing addresses for 64 perfect matches. When

hash mode is selected, 8 bytes are used to store a logical address filter, and 372 bytes are

used to store addresses for 62 perfect matches.

In hash mode, a logical address filter mask is used which requires the processor to perform

final filtering. As the incoming data stream goes through the CRC Generator, once the 48th

bit of the destination address has passed this circuitry, the six most significant bits of the

CRC are sampled. Those 6 bits become an address which selects one of the 64 bits in the

logical address filter mask. If the mask bit selected is a “1”, the address matches and the

packet is accepted. When programming the hash table, the task of mapping a destination

address to one of 64 bit positions requires a computer program to generate the CRC codes

for the addresses desired. The 6 most significant bits of a given addresses’ CRC becomes

the pointer into that addresses’ hash table entry. For Ethernet, the CRC polynomial is

CRC32 or:

+ X + X + X + X + X + X + X + X + X + X + X + X + X + 1

There is no rule on what type of address can be used in which type of address matching

mode. Either physical or multicast addresses may be stored as either a perfect match or

hash table entries. If an address matches both a perfect entry and a hash entry, the perfect

entry takes precedence.

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Broadcast and multicast frames may be either unconditionally accepted or unconditionally

rejected. Note that multicast frames may be conditionally accepted based on a matching

table entry, either perfect or hash. Refer to Figure 4-4 and Table 4-3 for broadcast and

multicast frame address recognition.

Physical addresses are compared to perfect-match entries and either accepted or rejected.

If no perfect match occurs, the addresses may then be accepted (but not rejected) on the

basis of a hash match. Refer to Figure 4-4 and Table 4-4 for physical address recognition.

A physical address, but not a multicast address, may be rejected on the basis of a perfect

match. A hash table match alone on a physical address is not sufficient to reject that frame.

The address recognition memory is not initialized at reset; the user must initialize it before

setting ETHER_EN in ECNTRL. Perfect-match entries which are unused should be set to

all 1’s (broadcast address) which is a safe value since broadcast frame handling occurs

independently of any table entries. Unused hashmode entry bits must be set to 0.

4.6.1 BUFFER DESCRIPTOR MODIFICATION

Index values and reason fields may be passed into the upper byte of the receive buffer

descriptor’s data pointer by setting the INDEX_EN bit. This may help improve software

efficiency. If INDEX_EN is cleared, the receive buffer descriptor data pointer is not modified

by the MC68EN302. If INDEX_EN is set, the index value and reason field will be written into

all the BDs of a frame.

There are four reasons, not counting promiscuous mode, which cause a frame to be

accepted:

1. The frame is a multicast or broadcast frame and the appropriate MULT bits are set.

2. A perfect address match occurs.

3. A hash match occurs.

4. No perfect match occurs, the frame has a physical, not multicast address, and the

PA_REJ bit is set.

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ETHERNET Controller

Table 4-3. Unicast Address Processing

CONTROL

OPERATION

PROM

PA_REJ

AR RESULT

ACCEPT/REJ

MISS

AR REASON

INDEX

Perfect match

Line #

Hash match

No match

–

Hash index

–

Perfect match

Hash match

No match

–

Hash index

Line #

Perfect match

Hash match

No match

Hash index

Perfect match

Hash match

No match

Table 4-4. Broadcast and Multicast Address Processing

CONTROL

BROADCAST

MULTICAST

MULT1– ACCEPT/

REASON

ACCEPT/

REJECT

REASON

PROM

MISS

INDEX AR RESULT

MISS

INDEX

MULT0

REJECT

0x3F

Perfect match

Hash match

No match

–

Line #

Hash index

–

Same as above entries

0x3F

Perfect match

Hash match

No match

–

Line #

Hash index

0x00

–

0x3F

Perfect match

Hash match

No match

0x2F

0x3F

Same as above entries

Perfect match

Hash match

No match

Line #

Hash index

0x00

0x2F

Hash index

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ETHERNET Controller

CHECK

ADDRESS

YES

BROADCAST

ADDR?

MULTICAST

ADDR &

MULT[10] = 11?

YES

PERFECT

MATCH?

PHYSICAL

ADDR &

PA_REJT = 1?

YES

MULT[0] = 0?

YES

HASH

MATCH?

RECEIVE FRAME

REASON = 10

ARINDEX =

RECEIVE FRAME

REASON = 11

ARINDEX = HASH

INDEX

RECEIVE FRAME

REASON = 01

ARINDEX = 111111

MATCHING

LINE NUMBER

YES

MULTICAST

ADDR?

MULT[10] = 10?

YES

RECEIVE FRAME

REASON = 01

ARINDEX = 000000

PA_REJT = 1?

YES

PROM = 1?

RECEIVE FRAME

REASON = 00

ARINDEX = HASH

INDEX

RECEIVE FRAME

REASON = 00

ARINDEX = HASH

INDEX

DISCARD FRAME

SET MISS BIT

Figure 4-4. Ethernet Address Recognition Flowchart

4.6.2 WRITING ADDRESSES INTO TABLES

The address recognition block is written/read just like a normal memory cycle (word or byte).

Unused locations do not return DTACK if accessed.

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ETHERNET Controller

Because each entry in the perfect-match table is 48 bits, but no more than 16 bits can be

written at a time; byte 5(or the word consisting of bytes 4 and 5 of a perfect-match entry)

must be written last. This prevents an address compare from occurring on partially-written

entries. When the first byte (or word) of an entry is written, that entry is temporarily disabled

until byte 5 (or a word consisting of bytes 4 and 5) is written.

The Address Recognition memory map for perfect match mode is shown in Figure 4-5. The

least significant bit of byte 0 (bit 8 of word MOBA + $A00, +$A08,...) corresponds to the I/G

address bit - this is the first bit received off the wire. The order of the bits received starts with

Byte 0-bit0 and continues through Byte0-bit7. The next byte is received as Byte1-bit0,

Byte1-bit1,...Byte1-bit7 up through byte 5.

BYTE 1

BYTE 3

BYTE 5

UNUSED

MOBA +$ A00

MOBA + $A02

MOBA + $A04

MOBA + $A06

BYTE0

BYTE 2

BYTE 4

FIRST ENTRY

UNUSED

BYTE 0

MOBA + $A08

MOBA + $A0A

MOBA + $A0C

MOBA + $A0E

SECOND ENTRY

BYTE 5

UNUSED

BYTE 0

UNUSED

MOBA + $BF8

MOBA + $BFA

MOBA + $BFC

MOBA + $BFE

LAST ENTRY

BYTE 5

UNUSED

Figure 4-5. AR Memory Map - Perfect Match Mode

When HASH_EN is set, the last two entries in the table are used for the logical address filter

mask bits. Hash index 0 is located in the least significant bit of byte 7 in the hash table

(MOBA + BFB). Hash index 63 is bit 7 of byte 0 (MOBA + BF0) in the hash table. When

writing logical address filter mask bits there is no restriction on the ordering of the writes.

When HASH_EN is set, the memory map is changed as shown in Figure 4-6. When

HASH_EN is set, locations MOBA + BF4, + BF6 AND MOBA + BFC, +BFE should not be

read or written to (DTACK will not be returned).

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MOBA + $A00

MOBA + $A02

MOBA + $A04

MOBA + $A06

BYTE 0

FIRST ENTRY

BYTE 5

UNUSED

MOBA + $BF0

MOBA + $BF2

MOBA +$ BF4

MOBA + $BF6

MOBA + $BF8

MOBA + $BFA

MOBA + $BFC

MOBA + $BFE

FIRST FOUR

BYTES OF HASH

UNUSED

LAST FOUR

BYTES OF HASH

UNUSED

Figure 4-6. AR Memory Map - Hash Mode

4.6.3 READING ADDRESSES FROM TABLES

The address recognition block is read as a normal memory cycle. There is no restriction on

the order of bytes to be read.

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SECTION 5

SIGNAL DESCRIPTIONS

This section contains descriptions of the MC68EN302 signals using the MC68302 as a

reference.

5.1 PIN/SIGNAL COMBINATIONS

The following table defines the MC68EN302 signals and the pinouts of the 144 pin TQFP

package. The PGA package has several exclusive signals not included on the TQFP

package. The signals exclusive to the PGA package are IAC, FRZ and two temperature

sense pins which are internally connected to each other.

Table 5-1. MC68EN302 144-TQFP Pin/Signal Definition

TQFP PIN

SIGNAL(S)

TYPE

BIDIR

TIN2/PB5

A0/TOUT1/PB4

VCC1

BIDIR

PWR

BIDIR

PWR

BIDIR

PWR

OUT

TIN1/PB3

DRAMRW/PB2/IACK1

CAS1/PB1/IACK6

CAS0/PB0/IACK7

GND1

UDS

LDS

GND2

XTAL

EXTAL

VCC2

PWR

OUT

CLKO

IPL0/IRQ1

IPL1/IRQ6

IPL2/IRQ7

BERR

BIDIR

AVEC/IOUT0

RESET

HALT

BGACK

PGA only

TPAD1 (TEMP_SENSE)

TMS

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Signal Descriptions

Table 5-1. MC68EN302 144-TQFP Pin/Signal Definition

PGA only

TCK

TRST

DTACK

BIDIR

PWR

BIDIR

OUT

BIDIR

OUT

GND3

VCC3

RCLK1/L1CLK

TCLK1/L1SY0/SDS1

TXD1/L1TXD

RTS1/L1RQ/GCIDCL

RTS3/SPTXD

CD3/SPCLK

AMUX/BRG1

GND

PARITY1/BUSW

PARITY0/DISCPU

VCC4

BIDIR

PWR

FRZ

GND4

PWR

BIDIR

PWR

BIDIR

PWR

BIDIR

PWR

BIDIR

PARITYE/THREESTATE

WEL/DREQ/PA13

WEH/DACK/PA14

OE/DONE/PA15

RAS1/BRG3/PA12

RAS0/BRG2/SDS2/PA7

GND5

TCLK3/PA11

RCLK3/PA10

TXD3/PA9

RXD3/PA8

VCC5

CD2/PA6

RTS2/PA5

CTS2/PA4

GND6

TCLK2/PA3

RCLK2/PA2

TXD2/PA1

RXD2/PA0

RXD1/L1RXD

CTS1/L1GR

CD1/L1SY1

CTS3/SPRXD

BIDIR

OUT

PWR

RENA

VCC6

GND7

CLSN

RCLK

TENA

OUT

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Signal Descriptions

Table 5-1. MC68EN302 144-TQFP Pin/Signal Definition

TCLK

BIDIR

PWR

GND8

BIDIR

PWR

VCC7

BIDIR

PWR

D10

D11

GND9

D12

D13

D14

D15

GND10

VCC8

A23

A22

A21

A20

GND11

A19

A18

A17

A16

VCC9

A15

A14

A13

A12

GND12

A11

A10

BIDIR

PWR

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

BIDIR

PWR

BIDIR

PWR

BIDIR

PWR

BIDIR

PWR

GND13

BIDIR

FC0

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Signal Descriptions

Table 5-1. MC68EN302 144-TQFP Pin/Signal Definition

128

129

VCC10

PWR

BIDIR

OUT

PWR

OUT

FC1

130

FC2

131

CS0/IOUT2

132

CS1

133

GND14

134

CS2

135

CS3

PGA only

136

TPAD2 (TEMP_SENSE)

TDO

OUT

137

TDI

PGA only

138

IAC

OUT

PB11

BIDIR

PWR

BIDIR

139

PB10

140

PB9

141

PB8

142

WDOG/PB7

GND15

TOUT2/PB6

143

144

5.2 MC68EN302/MC68302 COMMON SIGNALS

The following pin/signal combinations are common between the MC68302 and

MC68EN302. Any differences in functionality are noted.

A23–A1

D15–D0

In 8-bit mode bit 15–bit 8 is used on the MC68EN302 rather than bit 7–bit 0 on the

MC68302. All 16 bits of the data bus are driven during an 8-bit write.

R/W

UDS

A0 is not multiplexed with UDS on the EN302

LDS

DTACK

AVEC/IOUT0

IPL2/IRQ7

IPL1/IRQ6

IPL0/IRQ1

FC2–FC0

BGACK

BERR

RESET

HALT

TCLK3/PA11

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Signal Descriptions

RCLK3/PA10

TXD3/PA9

RXD3/PA8

CD2/PA6

RTS2/PA5

CTS2/PA4

TCLK2/PA3

RCLK2/PA2

TXD2/PA1

PB11–PB8

WDOG/PB7

TOUT2/PB6

TIN2/PB5

TIN1/PB3

RXD1/L1RXD

TXD1/L1TXD

RCLK1/L1CLK

TCLK1/L1SY0/SDS1

CD1/S1SY1

CTS1/L1GR

RTS1/L1RQ/GCIDCL

CD3/SPCLK

CTS3/SPRXD

RTS3/SPTXD

CS3–CS1

CS0/IOUT2

CLKO

XTAL

EXTAL

5.3 MC68302 SIGNALS REMOVED OR REDEFINED

The following signals that are present on the MC68302 are not present on the MC68EN302

or have been redefined in some way.

RMC/IOUT1

IAC

BCLR

FRZ

BUSW

DISCPU

5.3.1 RMC/IOUT1

This MC68302 output is not available on the MC68EN302.

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Signal Descriptions

5.3.2 IAC

This MC68302 output is not available on the MC68EN302 in the 144-pin TQFP package. It

is available in the PGA package.

5.3.3 BCLR

This MC68302 signal is not available on the MC68EN302. The additional EN302 logic

monitors the BCLR signal from the 302 core, but does not drive it.

5.3.4 FRZ

This MC68302 input is now pulled up internally and is not available on the MC68EN302 in

the 144 pin TQFP package. It is available in the PGA package.

5.3.5 BUSW

The BUSW signal (bus width) is a dedicated pin on the MC68302, but is muxed with

PARITY1 on the MC68EN302. This pin functions as BUSW only during system reset. If the

BUSW signal is low during EN302 reset, the EN8 bits in the CSER3–CSER0 register are

set. The BUSW signal is not passed to the 302 core on the MC68EN302, since the 302 core

of the MC68EN302 always operates in 16-bit mode. In 8-bit mode, bits D15–D8 of the data

bus are used. This is in contrast with the MC68302, which uses bits D7–D0 in 8-bit mode.

5.3.6 DISCPU

The DISCPU signal is a dedicated pin on the MC68302 but is muxed with PARITY0 on the

MC68EN302. This pin is DISCPU only during system reset.

5.4 MC68EN302 NEW SIGNALS MUXED WITH EXISTING MC68302

SIGNALS

Several pins on the MC68EN302 have enhanced MC68302 functionality. The additional

signal capability is controlled by the PM9–PM0 field in the MBCTRL (Module Bus Control)

Table 5-2. Pin Muxing Control

MC68EN302

PM[I]=0

AMUX

MC68EN302

PM[I]=1

PM[I]

MC68302

BRG1

BRG2/SDS2/PA7

BRG3/PA12

PB0/IACK7

RAS0

BRG2/SDS2/PA7

BRG3/PA12

PB0/IACK7

PB1/IACK6

PB2/IACK1

TOUT1/PB4

WEL

RAS1

CAS0

CAS1

PB1/IACK6

DRAMRW

PB2/IACK1

TOUT1/PB4

DREQ/PA13

DACK/PA14

DONE/PA15

DREQ/PA13

DACK/PA14

WEH

DONE/PA15

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Signal Descriptions

5.4.1 AMUX - DRAM Address Mux

The AMUX pin is an output only pin provided for implementing external address muxing

circuitry when accessing DRAM. The user may require use of this signal if external masters

are utilizing the EN302 DRAM controller. When performing an access to the EN302 as a

slave, the address is driven as an input, preventing the EN302 DRAM controller from driving

the address bus. Because of this, external muxing must take place. The AMUX pin is also

useful in implementations where a linear DRAM space is required.

The AMUX signal appears on the pin if the PM0 bit of the MBCTRL = 0. If PM0 = 1 then the

pin becomes BRG1 instead.

5.4.2 RAS0 - DRAM Row Address Select, Bit Zero

When the PM1 bit of the MBCTRL = 0, this active low output signal is used to select one of

two banks of DRAM as determined by the DRAM Base Address Register 0 (DBA0).

If PM1 = 1 then the pin becomes BRG2/SDS2/PA7 and is bidirectional depending on the

function chosen

5.4.3 RAS1 - DRAM Row Address Select Bit 1

When the PM2 bit of the MBCTRL = 0, this active low output signal is used to select one of

two banks of DRAM as determined by the DRAM Base Address Register1 (DBA1) CSR.

If PM2 = 1, then the pin is used as BRG3/PA12 and may be bidirectional

5.4.4 CAS0 - DRAM Column Address Select Bit 0

If the PM3 bit of the MBCTRL = 0, this active low output signal is used to enable the DRAM

module upper byte (bits 15–8).

If PM3 = 1 then the pin is used for PB0/IACK7 and may be bidirectional.

5.4.5 CAS1- DRAM Column Address Select Bit 1

If the PM4 bit of the MBCTRL = 0, this active low output signal is used to enable the lower

byte (bits 7–0) of the DRAM module.

If PM4 = 1 then the pin is used for PB1/IACK6 and may be bidirectional.

5.4.6 DRAMRW- DRAM Read/Write

If the PM5 bit of the MBCTRL = 0, this pin is asserted low for a DRAM write cycle. It is

separate from the processor bus R/W signal to allow precharge to take place without regard

to the state of R/W.

If PM5 = 1 then the pin is used for PB2/IACK1 and may be bidirectional.

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Signal Descriptions

5.4.7 A0

A new signal, A0 has been added for supporting dynamic bus sizing. This signal replaces

the MC68302 A0 that was multiplexed onto UDS. A0 is bidirectional.

The A0 signal appears on the pin if the PM6 bit of the MBCTRL = 0. If PM6= 1 then the pin

is used as TOUT1/PB4.

5.4.8 WEL- Write Enable for Byte 1 (Bit 7–Bit0)

If the PM7 bit of the MBCTRL = 1, then the active low signal WEL is enabled. If PM7 = 0,

then the pin is used for DREQ/PA13 and is bidirectional.

5.4.9 WEH - Write Enable for Byte 0 (Bit 15–Bit 8)

If the PM8 bit of the MBCTRL = 1, the active low WEH signal appears on the pin. If PM8 =

0, then the pin is used for DACK/PA14 and is bidirectional.

5.4.10 OE - Output Enable

Output - asserted low, pin is bidirectional.

If the PM9 bit of the MBCTRL = 0, the active low OE signal is enabled. If PM9 = 1 then the

pin is used for DONE/PA15 and may be bidirectional.

5.5 MC68EN302 ONLY PIN/SIGNALS

TENA

TCLK

RENA

RCLK

CLSN

PARITY0/DISCPU

PARITY1/BUSW

PARITYE/THREES

TMS

TCK

TRST

TDO

TDI

GND

5.5.1 GND

For proper implementation of the EN302, this pin must be tied to ground.

5.5.2 TRST - JTAG Reset Signal

For normal operation the asynchronous TRST signal must be held low during system reset.

This pin has an internal pullup resistor.

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Signal Descriptions

5.5.3 TMS - JTAG Test Mode Select

This input controls test mode operation for the EN302 test logic as defined by the IEEE

1149.1 standard. This pin has an internal pullup resistor.

5.5.4 TDO - JTAG Test Data Out

This output is used in shifting serial test instructions and test data for on-board test logic

defined by the IEEE 1149.1 standard.

5.5.5 TDI - JTAG Test Data In

This input is used for shiftng serial test instructions and test data for on-board test logic

defined by the IEEE 1149.1 standard. This pin has an internal pullup resistor.

5.5.6 TCK- JTAG Clock

The JTAG clock runs at a frequency no greater than 10 MHz.

5.5.7 GND

Must be tied to GND in normal operation.TX

Ethernet MAC transmit data output.

5.5.8 TENA

Ethernet MAC transmit data valid output.

5.5.9 TCLK

Ethernet transmit clock input must be 10 MHz +/- 100 ppm according to the 802.3 spec.

5.5.10 RCLK

Ethernet receive clock input.

5.5.11 RX

Ethernet MAC receive data input.

5.5.12 RENA

This input indicates that the Ethernet MAC receive data is valid.

5.5.13 CLSN

This input pin indicates a collision (or SQE Test) was detected in the ethernet physical layer.

5.5.14 PARITY0/DISCPU

Parity is controlled by the PCSR register in the module bus controller. This bidirectional pin

provides even or odd parity for byte 0 (bit 15–bit 8) when not in the reset state.

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Signal Descriptions

The MC68EN302 DISCPU state is sampled during hardware reset just as in the MC68302.

The M68000 core is disabled by asserting the DISCPU pin high during total system reset.

5.5.15 PARITY1/BUSW

Parity is controlled by the PCSR Register in the module bus controller. This bidirectional pin

provides even or odd parity for byte 1 (bit 7–bit 0) when not in the reset state.

The state of BUSW is sampled during total system reset. When the BUSW is low during

hardware reset, it does not put the 68000 into 68008 mode with an 8 bit bus. Instead, having

the BUSW low during hardware reset will force the four EN8 bits in the CSER registers to

one, enabling support for dynamic bus sizing in the chip selects. Note that because the

68000 core is in normal 16 bit mode, if the 68000 accesses memory outside of the four chip

select areas, it always performs a normal 16 bit access.

5.5.16 PARITYE/THREESTATE

During normal operation, this bidirectional pin is the active low PARITYE (parity error)

output, and is asserted whenever one of the PED (Parity Error DRAM) bits in the PCSR is

asserted.

If this pin is low during total system reset, all bidirectional pins and output pins will be put

into three-state mode. This is intended for chip test purposes.

5.6 DRAM CONTROLLER I/O

5.6.1 Control Signal Pins

The EN302 contains 8 DRAM specific signal pins: CAS1–CAS0, RAS1–RAS0, AMUX, and

DRAMRW.

5.6.2 Column Address Strobes (CAS1–CAS0)

These active low pins allow seamless interface to Column Address Strobe (CAS) inputs on

industry standard DRAM, providing CAS for both bank 0 and bank 1 of the DRAM controller.

Two strobes support byte operations on the external 16-bit bus. CAS0 corresponds to data

pins D15-D8. CAS1 corresponds to data pins D7–D0.

5.6.3 Row Address Strobes (RAS1–RAS0)

These active low pins allow seamless interface to Row Address Strobe (RAS) inputs on

industry standard DRAM, providing RAS for both bytes of a given DRAM bank. A particular

bank corresponds to specific Base Address and Control information programmed in the

MC68EN302 DRAM control registers (see 3.2 Memory Map for a description). RAS0

corresponds to bank 0 and RAS1 corresponds to Bank 1.

5.6.4 DRAM Read/Write (DRAMRW)

This active low pin is asserted to signify that a DRAM write cycle is occurring. It is separate

from the processor bus R/W so that precharge takes place without regard to the state of R/

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Signal Descriptions

5.6.5 Address Mux (AMUX)

The AMUX pin is provided for implementing external address muxing circuitry so that

external masters may access DRAM modules controlled by the MC68EN302 DRAM

controller. External address muxing must take place in this situation since an access to the

MC68EN302 as a slave always results in the addresses driven as an input, and does not

output addresses to the DRAM module.

Another use for the AMUX pin would be implementations in which a linear DRAM space is

required.

5.6.6 Parity (PARITY1–PARITY0)

These two pins are provided to support parity checking of DRAM. If enabled, parity is

generated on writes and checked on reads. A parity error on a read generates a bus error.

PARITY0 is used in connection with D15-D8 and PARITY1 is used in connection with D7–

D0.

Parity checking/generation is not supported for external bus masters.

5.6.7 Muxing Scheme

To provide a simplified implementation of the Address Mux, a unique muxing scheme is

provided. Rather than providing programmability to change which addresses are muxed on

a particular signal, a generic muxing scheme is provided so that one muxing scheme may

be utilized by all supported DRAM bank sizes. Table 5-3 shows the DRAM muxing scheme.

The usage listed in the table is for typical operation. It is possible that some users may utilize

the Base Address Registers and the Mask bits in a non-standard way.

Table 5-3. Address Muxing Scheme

PROCESSOR

ADDRESS

COLUMN

ADDRESS

ROW ADDRESS

USAGE

Used for all Bank Sizes

A10

A11

A12

A13

A14

A15

A16

A18

A20

A22

Used for 512K and up

Used for 2M and up

Used for 8M

5-11

MC68EN302 REFERENCE MANUAL

MOTOROLA

Signal Descriptions

5-12

MC68EN302 REFERENCE MANUAL

MOTOROLA

SECTION 6

APPLICATIONS

6.1 BRINGING THE MC68EN302 OUT OF RESET

The following paragraphs provide an example of how to bring the MC68EN302 out of reset

and initialize the Ethernet Controller to perform internal loopback of one frame. Bank 0 of

DRAM is used as packet memory.

1. Write the Base Address Register (BAR) with the desired starting point of the 302 core

4k-byte relocatable address space. Write the Module Bus Controller Base Address

the module bus controller, DRAM controller and Ethernet controller CSRS and

memory.

2. Write to the Option Register (OR) to include 256K bytes of space and so that the

DTACK field may be written to to change the number of wait states. Also note that to

access data in the program ROM, the CFC bits should be modified.

3. OR1 affects the RAM range, controls DTACK, and will also affect whether or not

function code comparisons are performed.

4. BR1 will set up the RAM address, enable the RAM, and set the function code

appropriately.

5. Switch from ROM location to dual-port RAM location to assure that the reset vector is

supplied by the ROM, but the exception vectors all come from the RAM. This switch is

performed by a short, dual-port RAM program which is summarized below, and is

explained in depth in Appendix D.2 of the MC68302 User’s Manual.

MOVE.W #$A001, (Address of BR1).L

MOVE.W #$C201, (Address or BR0).L

JMP ($Address in ROM).L

After the code is copied, then execute the following instruction, which will cause a

jump to dual port RAM

JMP ($Base Address).L

6. MBC - the MBC register controls bits for overall system level functionality of the

Module Bus Controller. This register must be initialized to assure smooth functionality

between the SIM module on the MC68EN302 and the SIM module on the internal 302

core. In the MBC register the module bus controller response to BCLR from the

internal 302 is controlled, as is the parity, function code for the Ethernet specific core,

MOTOROLA

MC68EN302 REFERENCE MANUAL

6-1

Applications

and the pin muxing that is used in the current MC68EN302 application.

Example: Write $5400 to MBC (MFC = 5, PPE = 1).

7. IER - The interrupt extension register replaces the MOD, ET7, ET6 and ET1 bits in the

302 GIMR. The user MUST assure that the corresponding bits in the GIMR of the

internal 302 are all written as zeros for proper functionality of the MC68EN302. The

IER is reset to $0000 which configures the interrupt input pins as IPL2–IPL0 and sets

the module bus controller interrupt to level 5.

8. CSER0–CSER3. The MC68EN302 extends the functionality of that provided by the

internal 302 core chip selects through the programming of this register. Additional

functionality includes 8-bit bus operation as well as parity checking and generation.

9. PCSR - This register controls parity operation on the MC68EN302. Also, bits 9-8 show

the result of parity on the current DRAM bank.

10.DRAM controller initialization. Assume bank 0 is to be used, parity enabled, 0 wait

states.

•

DRAM Configuration Register (DCR) = $0501 (Enable refresh and parity in bank 0,

allow supervisor or user access)

•

DRAM Refresh Register (DRFRSH) = $0000 (Refresh every 4096 system clocks)

DRAM Base Address Registers

DBA0 = desired DRAM base address and size, bit 0 = 1

DBA1 = $0000 (reset value)

•

To ensure correct parity, write $0000 to each memory location used before running

other code.

11.Ethernet Controller Initialization. In this example the Ethernet Controller is initialized to

perform internal loopback of one frame. The received frame buffer will be 4 bytes

longer than the transmit buffer due to the CRC being appended by hardware.

•

ECNTRL = $0001 (Release RESET to the Ethernet Controller)

EDMA = $000B

WMRK = 01 (16 bytes)

BLIM = 011 (max DMA burst length of 8 bus transactions (16 bytes of data))

•

EMRBLR = $0600 (1536 bytes, this allows receiving a max size frame into a single

buffer).

IVEC = $0140

VG = 1 (bit 1–bit 0 of the interrupt vector will be modified).

INV7–INV0 = 40

•

INTR_MASK = $07BC (all interrupts enabled except BackOffDone, TransmitBuffer

and ReceiveBuffer).

•

ECNFIG = $0001 (enable internal loopback).

ETHER_TEST = $0000

6-2

MC68EN302 REFERENCE MANUAL

MOTOROLA

Applications

•

AR_CNTRL = $7000

HASH_EN = 0 (all 64 entries used for “match” mode)

INDEX_EN = 1 (enables hardware to write “Reason” and “ARIndex” fields into the

receive BD.

MULT1–MULT0 = 11 (reject multicast and broadcast frames).

• Place the frame to be looped internally into memory. Entire frame should be in a single

buffer. Allocate receive buffer memory to receive same frame plus 4 CRC bytes.

• Initialize CAM (arbitrarily select 1 of 64 entries to contain the DA of the frame to be

transmitted). CAM is in perfect match mode. CAM starts at MOBA + $A00.

Write $FF_FF_FF into all CAM entries except 1

Write DA of transmit frame into remaining entry

• Initialize buffer descriptors. A good practice would be to initialize all locations to $0000

before putting in any specific values.

MOBA + C48 = $0000 (clear E bit in second receive BD)

MOBA + C46 = $LLLL (A15–A0 pointer to receive buffer)

MOBA + C44 = $00HH (A23–A16 pointer to receive buffer)

MOBA + C40 = $8000 (set E bit in first receive BD)

MOBA + C08 = $0000 (clear R bit in second transmit BD)

MOBA + C06 = $LLLL (A15–A0 pointer to transmit buffer)

MOBA + C04 = $00HH (A23–A16 pointer to transmit buffer)

MOBA + C02 = $0NNN (transmit buffer length)

MOBA + C00 = $8C00 (single buffer frame, hardware appends CRC)

• ECNTRL = $0003 (assert ETHER_EN to the Ethernet Controller, this will cause the

buffer descriptor and DMA state machines to start operation)

• Frame loopback should occur under hardware control. The TFINT and RFINT interrupts

should occur. Once these interrupts have occurred, frame loopback can be verified by

the following:

— Receive buffer should contain frame transmitted plus 4 byte CRC

— Transmit buffer descriptor should contain the following:

MOBA + C00 = 0C00

MOBA + C02, C04, C06 locations should be unchanged

— Receive buffer descriptor should contain the following:

MOBA + C40 = $0C00

MOBA + C42 = value in (MOBA + C02) + 4

MOBA + C44, C46 locations should be unchanged

6.2 MOVING A QUICC ETHERNET DRIVER TO A 68EN302 ETHERNET

DRIVER

Porting an Ethernet driver written for the MC68360 QUICC to the MC68EN302 requires only

that the QUICC driver be pared down to support a simpler implementation of Ethernet. In

the case of register settings and counters, many of the functions requiring user initialization

by the QUICC are either supported directly in the MC68EN302 hardware as dictated by the

Ethernet standard, or are provided in the indications that accompany the buffer descriptors.

This simplifies the initialization routines in the area of CRC calculation as well as the

maximum and minimum frame lengths, DMA operations and the backoff counter

MOTOROLA

MC68EN302 REFERENCE MANUAL

6-3

Applications

operations.The MC68EN302 buffer descriptors are a superset of the QUICC buffer

descriptors. The transmit buffer descriptors are identical, while the MC68EN302 receive

buffer descriptors include an additional bit in the most significant word which is used as an

indication for address matching while running in promiscuous mode. Any driver that

implements Ethernet on the QUICC will be able to utilize the same buffer descriptor structure

and handling when running on the MC68EN302. Following the Ethernet register map from

the MC68360UM/AD Revision 2.0 user's manual in the table listing the Ethernet Specific

Parameters (in the Parameter RAM), the corresponding function in the MC68EN302 is listed

below. Items in italics indicate that that particular parameter was not part of the QUICC

initialization process and is not required for CRC.

The standard 32 bit CRC calculation for the CRC is performed in the MC68EN302 hardware,

and therefore there is no need to write to the CRC value.

6.2.1 C_PRES, C_MASK:

The QUICC preset and mask options for the CRC calculation are not required in the

MC68EN302 because the CRC is automatically calculated in hardware.

6.2.2 CRCEC:

In the MC68EN302, CRC errors are flagged in the buffer descriptor indication rather than

keeping a running counter as in the QUICC. A software counter may be implemented to

support this function with very little difficulty by incrementing the count each time the CR bit

(bit 2 in the most significant long word of the buffer descriptor) is set.

6.2.3 ALEC:

The Alignment error is flagged in the buffer descriptor indication and therefore a software

counter may be implemented to support this function. A counter may be incremented each

time the NO bit (bit 4 in the most significant long word of the buffer descriptor) is set.

6.2.4 DISFC:

This function is not required in standard Ethernet. If frames are discarded because of error

conditions, then the buffer descriptor is flagged with the error notification. If a buffer

descriptor is not available, then an overrun error occurs, notifying the user that a frame was

discarded because no buffer descriptors were available. If a frame is discarded because of

the address filtering that is implemented on the MC68EN302, there is no indication provided

since this function is generally used for collecting network statistics and does not add to the

station performance.

6.2.5 PADS:

In the transmit direction the padding is automatic and is always generated as all ones.

6.2.6 RET_LIM:

Set in hardware to standard Ethernet values of 15.

6-4

MC68EN302 REFERENCE MANUAL

MOTOROLA

Applications

6.2.7 RET_Cnt:

The RC field in the transmit buffer descriptor is the retry count (bits 5-2 of the most significant

long word). If the RL bit is also set (bit 6) then the RC bits have no meaning since the retry

limit has been exceeded.

6.2.8 MFLR:

The maximum frame length is set in MC68EN302 hardware to 1518.

6.2.9 MINFLR:

The minimum frame length is set in MC68EN302 hardware to 64.

6.2.10 MAXD1, MAXD2:

These operations are covered by the maximum frame length being automatically set at 1518

bytes. This is not programmable in the MC68EN302.

6.2.11 MAX_b:

The MC68EN302 supports buffer descriptor options ranging from 8 Tx and 120 RX buffer

descriptors to 64 TX and 64 RX buffer descriptors.

6.2.12 GADDR1-4 / PADDR_HML / IADDR1-4:

AR_CNTL provides the address filtering. Options in the MC68EN302 are either 64 perfect

address matches or 62 perfect address matches with address filtering via a hash routine.

6.2.13 P_PER:

The persistance is not programmable on the MC68EN302 but rather is a specific value set

in the MC68EN302 hardware.

6.2.14 RFBD_ptr/TFBD_ptr/TLBD_ptr:

Buffer descriptors in the MC68EN302 are placed at MOBAR+$C00 through MOBAR+$FFF.

The TFBD_ptr is always at MOBAR+$C00.

The TLBD_ptr can range from MOBAR+$C00 in a one buffer frame to MOBAR+$DFF in a

64 transmit buffer frame.

The RFBD_ptr is either at MOBAR+$C40, MOBAR+$C80, MOBAR+$D00 or

MOBAR+$E00 depending on the setting of the BDSIZE bits.

6.2.15 TX_len:

The TX frame length counter is part of the data length field in the buffer descriptor. To come

up with the total tx frame length the user must keep track of the data length in the buffer

descriptors belonging to that frame.

MOTOROLA

MC68EN302 REFERENCE MANUAL

6-5

Applications

6.2.16 BOFF_CNT:

The backoff count is set to a specific value in the MC68EN302 hardware.

6.2.17 TADDR_H/M/L:

Implemented in the 64 entry address recognition table as per user set up.

6.2.18 GSMR (QUICC Section 7.10.2)

The following table represents bits relating to Ethernet in the QUICC’s GSMR register and

indicate the corresponding function on the MC68EN302.

BIT(S)

47/46

MNEMONIC

TCRC

RFW

FUNCTION ON MC68EN302

Hardware function

Set width in hardware

TCI

Clocking optimized in hardware

Preamble set to 6 bytes in hardware

Preamble pattern defined as 10

Ethernet only

23-21

TPL

TPP

3-0

MODE

6-6

MC68EN302 REFERENCE MANUAL

MOTOROLA

SECTION 7

IEEE 1149.1 (JTAG) TEST ACCESS PORT

The MC68EN302 provides a dedicated user-accessible test access port (TAP) that is fully

compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architec-

ture.

The TAP consists of five dedicated signal pins, a 16-state TAP controller, boundary scan

and instruction registers. A boundary scan register links I/O pins into a single shift register.

The test logic, implemented utilizing static logic design, is independent of the device system

logic. The MC68EN302 implementation provides the capability to:

1. Perform boundary scan operations to test circuit-board electrical continuity.

2. Bypass the MC68EN302 for a given circuit-board test by effectively reducing the

boundary scan register to a single cell.

3. Sample the MC68EN302 system pins during operation and transparently shift out the

result in the boundary scan register.

4. Disable the output drive to pins during circuit-board testing.

NOTE

Certain precautions must be observed to ensure that the IEEE

1149.-like test logic does not interfere with nontest operation.

See 7.6 Non-Scan Chain Operation for details.

In addition to the scan-test logic, the MC68EN302 contains a signal that can be used to

three-state all MC68EN302 output signals. This signal, called three-state (THREESTATE),

is sampled during system reset.

7.1 OVERVIEW

An overview of the MC68EN302 scan chain implementation is shown in Figure 7-1. The

MC68EN302 implementation includes a TAP controller, a 4-bit instruction register, and two

test registers (a 1-bit bypass register and a 163-bit boundary scan register). This implemen-

tation includes a dedicated TAP consisting of the following signals:

• TCK—a test clock input to synchronize the test logic.

• TMS—a test mode select input (with an internal pullup resistor) that is sampled on the

rising edge of TCK to sequence the TAP controller’s state machine.

• TDI—a test data input (with an internal pullup resistor) that is sampled on the rising

edge of TCK.

MOTOROLA

MC68360 USER’S MANUAL

7-1

IEEE 1149.1 (JTAG) Test Access Port

• TDO—a three-stateable test data output that is actively driven in the shift-IR and shift-

DR controller states. TDO changes on the falling edge of TCK.

• TRST—an asynchronous reset (with an internal pullup resistor) that provides initializa-

tion of the TAP controller and other logic required by the standard.

195

BOUNDARY SCAN REGISTER

TDI

BYPASS

DECODER

TDO

3-BIT INSTRUCTION REGISTER

TMS

TCK

TAP

CTLR

TRST

Figure 7-1. Test Logic Block Diagram

7.2 TAP CONTROLLER

The TAP controller is responsible for interpreting the sequence of logical values on the TMS

signal. It is a synchronous state machine that controls the operation of the JTAG logic. The

state machine is shown in Figure 7-2. The value shown adjacent to each arc represents the

value of the TMS signal sampled on the rising edge of the TCK signal. For a description of

the TAP controller states, refer to the IEEE 1149.1 document.

7-2

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

TEST LOGIC

RESET

RUN-TEST/IDLE

SELECT-DR_SCAN

SELECT-IR_SCAN

CAPTURE-DR

CAPTURE-IR

SHIFT-DR

SHIFT-IR

EXIT1-IR

EXIT1-DR

PAUSE-DR

PAUSE-IR

EXIT2-DR

EXIT2-IR

UPDATE-IR

UPDATE-DR

Figure 7-2. TAP Controller State Machine

7.3 BOUNDARY SCAN REGISTER

The MC68EN302 IEEE 1149.1 implementation has a 163-bit boundary scan register. This

ing exceptions. The FRZ and IAC signals which are not pinned out on the TQFP package

are not included in the scan chain. The XTAL pin is associated with an analog signal and is

not included in the boundary scan register. The EXTAL pin (clock in) is not included to min-

imize loading on this signal, however a boundary scan cell is included for an internal signal,

SCLK which is the clock input to the MBC, Ethernet and DRAM controller logic.

MOTOROLA

7-3

IEEE 1149.1 (JTAG) Test Access Port

All MC68EN302 bidirectional pins have a single register bit in the boundary scan register for

pin data and are controlled by an associated control bit in this register. Fifty bits in the bound-

ary scan register define the output enable signal for associated groups of bidirectional and

three-stateable output pins. The control bits and their bit positions are listed in Table 7-1.

Table 7-1. Boundary Scan Control Bits

Name

Bit Number

Name

ras1_enb

oeb_enb

wehb_enb

welb_enb

paritye_enb

parity_enb

cd3_enb

Bit Number

Name

berrb_out

CLKO_enb

drv_ext_cntl

drv_ext_uds

cas0_enb

cas1_enb

dram_rw_enb

pb3_enb

Bit Number

125

out_enb

drv_ext_a

drv_ext_d

rena_enb

rx_enb

130

133

137

139

pa0_enb

txd2_enb

pa2_enb

pa3_enb

pa4_enb

pa5_enb

pa6_enb

pa8_enb

txd3_enb

pa10_enb

pa11_enb

ras0_enb

141

101

105

107

109

111

113

115

117

119

121

123

143

txd1_enb

tclk1_enb

rclk1_enb

dtack_enb

ecpt_buf

145

a0_enb

147

pb5_enb

149

pb6_enb

151

wdogb_enb

pb8_enb

153

bgack_enb

br_enb

155

pb9_enb

157

haltb_out

resetb_out

avec_enb

pb10_enb

pb11_enb

159

161

The boundary scan bit definitions are listed in Table 7-2.

The first column in the table defines the bit’s ordinal position in the boundary scan register.

The shift register cell nearest TDO (i.e., first to be shifted out) is defined as bit 0; the last bit

to be shifted out is 162.

The second column references one of the seven MC68EN302 cell types depicted in Figure

7-3 through Figure 7-9, which describe the cell structure for each type.

The third column lists the pin name for all pin-related cells or defines the name of bidirec-

tional control register bits.

The fourth column lists the pin type for convenience, where Output indicates a three-state-

able output pin, I/O indicates a bidirectional pin and Input represents an input.

The last column indicates the associated boundary scan register control bit for bidirectional

and output pins.

Bidirectional pins include a single scan cell for data (bicell) as depicted in Figure 7-6. These

bits are controlled by the cell shown in Figure 7-5. The value of the control bit determines

whether the bidirectional pin is an input or an output. One or more bidirectional data cells

7-4

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

can be serially connected to a control cell as shown in Figure 7-10. Note that, when sampling

the bidirectional data cells, the cell data can be interpreted only after examining the IO con-

trol cell to determine pin direction, and also note that the control cell captures the value of

the following cell.

MOTOROLA

7-5

IEEE 1149.1 (JTAG) Test Access Port

Table 7-2. Boundary Scan Bit Definition

Bit

Num

Cell

Type

Pin/Cell

Name

Type

Output

CTLCell

Bit

Num

Cell

Type

Pin/Cell

Name

Type

Output

CTLCell

encell

iocell

dicell

bicell

dicell

bicell

out_enb

CS3

CS1

CS0

drv_ext_a

FC2

FC1

FC0

Output

bicell

iscell

iocell

iscell

iocell

dicell

bicell

dicell

bicell

iscell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

I/O

Input

Output

Input

Output

drv_ext_d

out_enb

drv_ext_d

out_enb

drv_ext_d

out_enb

drv_ext_d

out_enb

drv_ext_d

I/O

drv_ext_a

drv_ext_d

TCLK

TENA

RCLK

CLSN

out_enb

rena_enb

RENA

rx_enb

I/O

rena_enb

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

drv_ext_d

D15

D14

D13

D12

D11

D10

I/O

Input

rx_enb

CTS3

CD1

CTS1

RXD1

pa0_enb

RXD2

txd2_enb

TXD2

pa2_enb

RCLK2

pa3_enb

TCLK2

pa4_enb

CTS2

pa5_enb

RTS2

pa6_enb

CD2

I/O

pa0_enb

I/O

txd2_enb

I/O

pa2_enb

I/O

pa3_enb

I/O

pa4_enb

I/O

drv_ext_d

I/O

pa5_enb

I/O

pa6_enb

pa8_enb

RXD3

I/O

pa8_enb

7-6

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

Table 7-2. Boundary Scan Bit Definition

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

iscell

iocell

dicell

bicell

iocell

encello

iocell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

txd3_enb

TXD3

I/O

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

iscell

haltb_out

HALT

I/O

br_enb

txd3_enb

pa10_enb

RCLK3

pa11_enb

TCLK3

I/O

haltb_ou

I/O

pa10_enb

resetb_out

RESET

avec_enb

AVEC

I/O

resetb_out

I/O

pa11_enb

ras0_enb

RAS0

I/O

avec_enb

I/O

ras0_enb

berrb_out

BERR

ras1_enb

RAS1

I/O

Input

berrb_out

I/O

ras1_enb

IPL2

oeb_enb

IPL1

I/O

oeb_enb

IPL0

wehb_enb

WEH

clko_encell CLKO_enb

I/O

wehb_enb

iocell

iscell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

bicell

dicell

CLKO

Output CLKO_enb

welb_enb

Input

SCLK (1)

drv_ext_cntl

WEL

paritye_enb

PARITYE

parity_enb

PARITY0

PARITY1

TEST302

AMUX

I/O

welb_enb

I/O

drv_ext_cntl

I/O

paritye_enb

drv_ext_cntl

LDS

drv_ext_cntl

drv_ext_uds

UDS

I/O

parity_enb

I/O

parity_enb

I/O

drv_ext_uds

Input

cas0_enb

CAS0

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

Output

out_enb

I/O

cas0_enb

cd3_enb

CD3

cas1_enb

CAS1

I/O

cd3_enb

I/O

cas1_enb

dram_rw_enb

DRAMRW

pb3_enb

TIN1

RTS3

Output

out_enb

RTS1

Output

out_enb

I/O

dram_rw_enb

txd1_enb

TXD1

Output

txd1_enb

I/O

pb3_enb

tclk1_enb

TCLK1

I/O

a0_enb

tclk1_enb

I/O

a0_enb

rclk1_enb

RCLK1

pb5_enb

TIN2

I/O

rclk1_enb

I/O

pb5_enb

dtack_enb

DTACK

ecpt_buf

pb6_enb

TOUT2

wdogb_enb

WDOG

I/O

dtack_enb

I/O

pb6_enb

I/O

ecpt_buf

I/O

wdogb_enb

bgack_enb

BGACK

br_enb

pb8_enb

PB8

I/O

bgack_enb

I/O

pb8_enb

pb9_enb

MOTOROLA

7-7

IEEE 1149.1 (JTAG) Test Access Port

Table 7-2. Boundary Scan Bit Definition

158

159

160

bicell

dicell

bicell

PB9

pb10_enb

PB10

I/O

pb9_enb

161

162

dicell

bicell

pb11_enb

PB11

I/O

pb11_enb

I/O

pb10_enb

Notes:

1. Boundary scan cell for SCLK (bit number 132 in table) is for the internal SCLK signal used in the Ethernet

controller. A boundary scan cell was not included on the EXTAL clock input signal to minimize loading.

TO NEXT

CELL

1—EXTEST / CLAMP

0—OTHERWISE

SHIFT DR

DATA FROM

TO OUTPUT

BUFFER

SYSTEM

LOGIC

MUX

FROM

LAST

CELL

CLOCK DR

UPDATE DR

Figure 7-3. Output Latch Cell (iocell)

TO DEVICE

LOGIC

INPUT

TO NEXT

CELL

MUX

CLOCK DR

FROM LAST SHIFT DR

CELL

Figure 7-4. Input Pin Cell (iscell)

7-8

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

1 – EXTEST

0 – OTHERWISE

HI_Z

OUTPUT

CONTROL

FROM

SYSTEM

LOGIC

TO OUTPUT

DIRECTION

MUX

TO NEXT

CELL

MUX

SHIFT DR

CLOCK DR

FROM

LAST

CELL

UPDATE DR

Figure 7-5. Control Cell (dicell)

1—EXTEST / CLAMP

0—OTHERWISE

OUTPUT CONTROL

FROM SYSTEM LOGIC

MUX

FROM IO

CONTROL CELL

1—EXTEST / CLAMP

0—SAMPLE

TO NEXT CELL

SHIFT DR

MODE

I/O

DATA FROM

SYSTEM

LOGIC

TO OUTPUT

DRIVER

MUX

CLOCK DR

UPDATE DR

FROM

DIRECTION

CTL

FROM I/O PIN

FROM

LAST

CELL

Figure 7-6. Bidirectional Cell (bicell)

MOTOROLA

7-9

IEEE 1149.1 (JTAG) Test Access Port

TO NEXT

CELL

1—EXTEST / CLAMP

0—OTHERWISE

HI-Z

SHIFT DR

TO OUTPUT

BUFFER

THREE-STATE

MUX

FROM

LAST

CELL

CLOCK DR

UPDATE DR

Figure 7-7. Output Enable Cell (encell)

TO NEXT

CELL

1—EXTEST / CLAMP

0—OTHERWISE

HI-Z

SHIFT DR

DATA FROM

SYSTEM LOGIC

TO OUTPUT

BUFFER

THREE-STATE

MUX

FROM

LAST

CELL

CLOCK DR

UPDATE DR

Figure 7-8. Output Enable Cell (encello)

7-10

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

1—EXTEST / CLAMP

0—OTHERWISE

TO NEXT

CELL

HI-Z

SHIFT DR

TO OUTPUT

BUFFER

THREE-STATE

MUX

CLKOMOD1

CLKOMOD2

MUX

FROM

LAST

CELL

CLOCK DR

UPDATE DR

CLKOENB16_S

CLKOENB24_S

Figure 7-9. Output Enable Cell (clko_encell)

MOTOROLA

7-11

IEEE 1149.1 (JTAG) Test Access Port

DIRECTION CTL

OUTPUT DATA

ENABLE FROM

SYSTEM LOGIC

I/O

IO CELL

INPUT DATA

FROM LAST CELL

NOTE: More than one IO.Cell could be serially connected and controlled by a single IO.Ctl.

Figure 7-10. General Arrangement for Bidirectional Pins

7.4 INSTRUCTION REGISTER

The MC68EN302 IEEE 1149.1 implementation includes the three mandatory public instruc-

tions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruc-

tion. One additional public instruction (HI-Z) provides the capability for disabling all device

output drivers. The MC68EN302 includes a 4-bit instruction register without parity. Data is

transferred from the shift register to the parallel outputs during the update-IR controller state.

The four bits used to decode the instructions are listed in Table 7-3.

Table 7-3. Instruction Decoding

Code

IR[3]

IR[2]

IR[1]

IR[0]

Instruction

EXTEST

SAMPLE/PRELOAD

BYPASS

HI-Z

CLAMP

ALL OTHER CASES

BYPASS

The parallel output of the instruction register logic is reset to the equivalent to the BYPASS

instruction. During the capture-IR controller state, the parallel inputs to the instruction shift

7-12

MOTOROLA

IEEE 1149.1 (JTAG) Test Access Port

7.4.1 EXTEST

The external test (EXTEST) instruction selects the 163-bit boundary scan register.

By using the TAP, the register is capable of a) scanning user-defined values into the output

buffers, b) capturing values presented to input pins, c) controlling the direction of bidirec-

tional pins, and d) controlling the output drive of three-stateable output pins. For more details

on the function and use of EXTEST, refer to the IEEE 1149.1 document.

7.4.2 SAMPLE/PRELOAD

The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a

means to obtain a snapshot of system data and control signals. The snapshot occurs on the

rising edge of TCK in the capture-DR controller state. The data can be observed by shifting

it transparently through the boundary scan register.

NOTE

Since there is no internal synchronization between the scan

chain clock (TCK) and the system clock (CLKO), the user must

provide some form of external synchronization to achieve mean-

ingful results.

The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output

cells prior to selection of EXTEST. This initialization ensures that known data will appear on

the outputs when entering the EXTEST instruction.

7.4.3 BYPASS

The BYPASS instruction selects the single-bit bypass register as shown in Figure 7-11. This

creates a shift register path from TDI to the bypass register and, finally, to TDO, circumvent-

ing the 163-bit boundary scan register. This instruction is used to enhance test efficiency

when a component other than the MC68EN302 becomes the device under test.

SHIFT DR

Mux

TO TDO

FROM TDI

Figure 7-11. Bypass Register

When the bypass register is selected by the current instruction, the shift register stage is set

to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the

first bit to be shifted out after selecting the bypass register will always be a logic zero.

MOTOROLA

7-13

IEEE 1149.1 (JTAG) Test Access Port

7.4.4 CLAMP

The CLAMP instruction selects the single-bit bypass register as shown in Figure 7-11, and

the state of all signals driven from system output pins is completely defined by the data pre-

viously shifted into the boundary scan register (for example, using the SAMPLE/PRELOAD

instruction).

7.4.5 HI-Z

The HI-Z instruction is provided as a manufacturer’s optional public instruction to prevent

having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all

output drivers are turned off (i.e., high impedance). The instruction selects the bypass reg-

ister.

NOTE

On the MC68EN302, the THREESTATE pin may also be used

during system reset to perform the same function.

7.5 MC68EN302 RESTRICTIONS

The control afforded by the output enable signals using the boundary scan register and the

EXTEST instruction requires a compatible circuit-board test environment to avoid device-

destructive configurations. The user must avoid situations in which the MC68EN302 output

drivers are enabled into actively driven networks.

7.6 NON-SCAN CHAIN OPERATION

In non-scan chain operation, there are two constraints. First, the TCK input does not include

an internal pullup resistor and should not be left unconnected to preclude mid-level inputs.

The second constraint is to ensure that the scan chain test logic is kept transparent to the

system logic by forcing TAP into the test-logic-reset controller state. This is accomplished

by asserting the TRST signal during system reset (RESET and HALT asserted) and leaving

TMS unconnected or tied to VCC.

7-14

MOTOROLA

SECTION 8

MC68EN302 ELECTRICAL CHARACTERISTICS

8.1 POWER DISSIPATION

At 25 MHz, typical current will be 140 mA (with all circuitry active), max current will be tbd.

8.2 CHANGES TO EXISTING MC68302 TIMING SPECS

The timing for the MC68EN302 signals that are shared with the MC68302 are the same as

specified in the MC68302 manual.

MOTOROLA

MC68EN302 REFERENCE MANUAL

8-1

MC68EN302 Electrical Characteristics

8.3 DRAM INTERFACE TIMING

Table 8-1. DRAM Interface Timing

20 MHZ

25 MHZ

NUM

6A CLKO Low to Column Address Valid

CLKO High to AS, RASx Asserted

CHARACTERISTIC

SYMBOL

UNIT

MIN

MAX

MIN

MAX

9A CLKO High to RASx Deasserted

400 RASx Asserted to Row Address Invalid

401 RASx Asserted to Column Address Valid

402 RASx Width Asserted (1)

403 RASx Width Negated (2)

404 RASx Asserted to CAS Asserted

405 CLKO High to CASx Asserted

405A CLKO High to CASx Asserted (Refresh)

406 CLKO High to CASx Negated

407 Column Address Valid to CASx Asserted

408 CASx Asserted to Column Address Negated

409 CASx Asserted to RASx Negated

410 CASx Width Asserted (1)

411 CASx Width Negated (2)

412 CASx Negated to Data, Parity-In invalid

415 DRAMRW Low to CASx Asserted

416 CASx Asserted to DRAMRW High

417 Data-Out Valid to CASx Asserted

417A Parity-Out Valid to CASx Asserted

418 CAS asserted to Data/Parity-Out Invalid (1)

419 CLKO Low to AMUX Negated

420 CLKO Low to AMUX Asserted

421 AMUX High to RASx Asserted

422 RASx Asserted to AMUX Low

423 AMUX Low to CAS Asserted

100

424 CASx Asserted to AMUX High

23A CLKO Low to Parity Out Valid

27 Data-In to CLKO Low (Parity Disabled) (3)

CLKO Low to Data Out Valid

27A Data/Parity-In to CLKO Low (Parity Enabled) (3)

425 CLKO High to PARITYE Valid

Any spec numbers shown in diagrams and not listed in the table are unchanged from the

MC68302 User’s Manual.

NOTES:

1. Width increases by clock period (Tcyc) for each wait state added.

2. Width increases by clock period (Tcyc) for each increase in P1–P0 (RAS precharge time).

3. Parity Enabled timing (spec 27A) only applies to bank(s) which have parity enabled.

8-2

MC68EN302 REFERENCE MANUAL

MOTOROLA

MC68EN302 Electrical Characteristics

CLK0

(output)

A23–A0

(output)

400

408

407

(output)

401

403

RASx

(output)

402

406

409

405

CASx

(output)

404

410

411

DRAMRW

(output)

424

420

423

419

AMUX

(output)

421

422

412

DATA15–

DATA0 (input,

PEx=0)

27A

DATA/PARITY

(input, PEx=1)

PARITYE

(output)

425

Figure 8-1. DRAM Read Cycle

MOTOROLA

MC68EN302 REFERENCE MANUAL

8-3

MC68EN302 Electrical Characteristics

CLK0

(output)

A23–A0

(output)

400

408

407

(output)

401

403

RASx

(output)

402

406

409

405

CASx

(output)

404

410

416

411

415

DRAMRW

(output)

420

423

419

424

AMUX

(output)

421

422

DATA15–

DATA0

417

(output)

418

23A

417A

PARITY1/0

(output)

Figure 8-2. DRAM Write Cycle

8-4

MC68EN302 REFERENCE MANUAL

MOTOROLA

MC68EN302 Electrical Characteristics

CLK0

(output)

A23–A0

(output)

RASx

(output)

CASx

(output)

405A

406

DRAMRW

(output)

Figure 8-3. DRAM Refresh

Table 8-2. Ethernet Timing

8.4 ETHERNET TIMING

NUM

CHARACTERISTIC

SYMBOL

MIN

MAX

UNIT

520 CLSN width high

521 RCLK Rise/Fall Time

522 RCLK width low

523 RCLK period

105

120

524 RX, RENA Setup to RCLK rising edge

525 RX Hold time from RCLK rising edge

526 RENA Active Delay (from RCLK rising edge of the last

data bit)

527 RENA Width Low

105

528 TCLK Rise/Fall Time

529 TCLK width low

530 TCLK clock period

101

531 TCLK High to TXD, TENA Active Delay (1)

532 TCLK High to TXD, TENA Inactive Delay (1)

1. NOTES:

1. TXD, TENA are actually driven by TCLK Low (falling) edge. Max delay from TCLK low to TXD, TENA change is 20 nsec.

MOTOROLA

MC68EN302 REFERENCE MANUAL

8-5

MC68EN302 Electrical Characteristics

CLSN

(input)

520

Figure 8-4. Ethernet Collision Timing

521

522

RCLK

(input)

523

525

(input)

527

RENA

(input)

524

526

Figure 8-5. Ethernet Receive Timing

528

529

TCLK

(input)

530

(output)

531

TENA

532

(output)

Figure 8-6. Ethernet Transmit Timing

8-6

MC68EN302 REFERENCE MANUAL

MOTOROLA

MC68EN302 Electrical Characteristics

8.5 JTAG INTERFACE TIMING

The TCK, TRST, TMS, TDI, TDO are new signals added to the MC68EN302 that do not exist

on the MC68302.

Num

Characteristic

TCK Frequency of Operation

Min

Max

—

Unit

MHz

TCK Cycle Time in Crystal Mode

TCK Clock Pulse Width Measured at 1.5 V

TCK Rise and Fall Times

100

Boundary Scan Input Data Setup Time

Boundary Scan Input Data Hold Time

TCK Low to Output Data Valid

—

TCK Low to Output High Impedance

10 TMS, TDI Data Setup Time

11 TMS, TDI Data Hold Time

12 TCK Low to TDO Data Valid

13 TCK Low to TDO High Impedance

14 TRST Assert Time

100

15 TRST Setup Time to TCK Low

TCK

(INPUT)

Figure 8-7. Test Clock Input Timing Diagram

TCK

(INPUT)

TRST

(INPUT)

Figure 8-8. TRST Timing Diagram

MOTOROLA

MC68EN302 REFERENCE MANUAL

8-7

MC68EN302 Electrical Characteristics

TCK

(INPUT)

DATA

INPUTS

INPUT DATA VALID

DATA

OUTPUTS

OUTPUT DATA VALID

DATA

OUTPUTS

DATA

OUTPUTS

OUTPUT DATA VALID

Figure 8-9. Boundary Scan (JTAG) Timing Diagram

TCK

(INPUT)

DATA

INPUTS

INPUT DATA VALID

DATA

OUTPUTS

OUTPUT DATA VALID

DATA

OUTPUTS

DATA

OUTPUTS

OUTPUT DATA VALID

Figure 8-10. Test Access Port Timing Diagram

8-8

MC68EN302 REFERENCE MANUAL

MOTOROLA

MC68EN302 Electrical Characteristics

8.6 OE, WEL, WEH TIMING

These are new signals added to the MC68EN302 that do not exist on the MC68302.

8.6.1 OE Timing

During a read, the timing on the OE signal is similar to the MC68302 UDS, LDS lines

(assertion and deassertion reference the same clock edges as UDS, LDS). Reference

Figure 6-2 (Read Cycle Timing Diagram) in the MC68302 User’s Manual. The following

MC68302 specifications define OE timing:

MC68302 Spec 9 - CLK0 High to OE Asserted

MC68302 Spec 12 - CLK0 Low to OE Negated

8.6.2 WEL, WEH Timing

During a write, the timing on the WEL, WEH signals is similar to the MC68302 UDS, LDS

lines (assertion and deassertion reference the same clock edges as UDS, LDS). Reference

Figure 6-3 (Write Cycle Timing Diagram) in the MC68302 User’s Manual. The following

MC68302 specifications define WEL, WEH timing:

MC68302 Spec 9 - CLK0 High to WEL, WEH Asserted

MC68302 Spec 12 - CLK0 Low to WEL, WEH Negated

MOTOROLA

MC68EN302 REFERENCE MANUAL

8-9

MC68EN302 Electrical Characteristics

8-10

MC68EN302 REFERENCE MANUAL

MOTOROLA

SECTION 9

ORDERING AND MECHANICAL INFORMATION

This section contains the ordering information, pin assignments, and package dimensions

for the MC68EN302.

9.1 PIN ASSIGNMENT

MOTOROLA

MC68EN302 REFERENCE MANUAL

9-1

Ordering and Mechanical Information

9.1.1 Pin Grid Array (PGA)

RENA

CTS3

GND

CD1 CTS1

PARITY0

RXD1 VCC VCC

CTS2

AMUX

PARITY1

GND

WEL

RCLK2 TCLK2 GND

PARITYE GND GND

FRZ GND TXD1

RXD2 TXD2

VCC

VCC TCLK RTS2 CD2 VCC

RXD3 TXD3 RAS0 RAS1 OE WEH

DTACK TCLK1

GND

RCLK3

GND GND CD3

RTS1

TRST

TCK

VCC

TCLK3

RTS3

AVEC BGACK

RCLK1

VCC

BERR

GND

CLSN

RCLK

IPL2 HALT TMS VCC

RESET TPAD1 GND

IPL1

MC68EN302RC

Top View

XTAL_PAD

LDS

DRAMRW

CLKO

IPL0

TENA GND

D10

D11

UDS

A20 GND D12

GND

TIN1

VCC

GND

D13

VCC GND

GND

VCC

GND

EXTAL RW GND VCC

VCC

VCC D14

A23

A22

FC1 FC2

A19

A18

VCC A15

FC0

CS0

D15 GND

VCC

CAS0 A0

GND VCC

CS1 GND

GND

CAS1 TIN2

GND CS2

IAC

GND GND

CS3

TD0

TDI

TPAD2

A17 A21 A10

PB11

WDOG

PB10 PB9 PB8

GND A11

GND

A16 A14 A13 A12

TOUT2

9-2

MC68EN302 REFERENCE MANUAL

MOTOROLA

Ordering and Mechanical Information

9.1.2 144 Thin Quad Flat Pack (TQFP)

144

109

A16

TIN2

127 126

108

A17

VDD

A18

TIN1

A19

GND

A20

A21

A22

A23

VDD

GND

D15

DRAMRW

CAS1

CAS0

GND

UDS

LDS

R/W

GND

XTAL

EXTAL

VDD

D14

D13

D12

GND

D11

CLKO

IPL0

D10

MC68EN302

(Top View)

IPL1

IPL2

VDD

BERR

AVEC

RESET

HALT

BGACK

GND

TMS

TCK

TRST

DTACK

GND

VDD

RCLK1

TCLK1

TXD1

TCLK

TENA

RCLK

CLSN

GND

VDD

54 55

MOTOROLA

MC68EN302 REFERENCE MANUAL

9-3

Ordering and Mechanical Information

9.2 PACKAGE DIMENSIONS

9.2.1 Pin Grid Array (PGA)

–T–

–X–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION

INCLUDES LEAD FINISH.

INCHES MILLIMETERS

–A–

DIM MIN

MAX

1.570

0.135

0.022

MIN

39.37

2.92

MAX

39.88

3.43

1.550

0.115

0.017

0.43

0.55

0.100 BSC

2.54 BSC

0.120

0.040

0.170

0.140

0.060

0.195

3.05

1.02

4.32

3.55

1.52

4.95

10 11 12 13 14 15

PIN A–1

–B–

1.400 BSC

35.56 BSC

D145 PL

0.76 (0.030)

0.25 (0.010)

T A

0.17 (0.007) T

CASE 768E-01

ISSUE O

DATE 04/04/94

9-4

MC68EN302 REFERENCE MANUAL

MOTOROLA

Ordering and Mechanical Information

9.2.2 144 Thin Quad Flat Pack (TQFP)

CASE 918-02

144 TQFP

L– M

0.20 (0.008)

L– M N

0.20 (0.008)

144

109

L, M, N

108

DETAIL "A"

DETAIL "B"

B1 V1

DETAIL "A"

BASE METAL

(ROTATED 90°)

144 PL

L – M

0.08(0.003)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF

LEAD AND COINCIDENT WITH THE LEAD WHERE

THE LEAD EXITS THE PLASTIC BODY AT THE

BOTTOM OF THE PARTING LINE.

4. DATUMS -L-, -M-, AND -N- TO BE DETERMINED AT

DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING

PLANE -T-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

ALLOWABLE PROTRUSION IS 0.25 (0.010 PER SIDE.

DIMENSIONS A AND B DO NOT INCLUDE MOLD

MISMATCH AND ARE DETERMINED AT DATUM LINE -H-.

θ2

DETAIL "C"

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE

THE D DIMENSION TO EXCEED 0.35 (0.014).

∩

0.08 (0.003)

SEATING

PLANE

DETAIL "B"

INCHES

MIN MAX

0.790 BSC

0.394 BSC

0.790 BSC

0.394 BSC

0.055 0.063

0.002 0.006

0.053 0.057

0.007 0.011

0.018 0.030

0.007 0.009

MILLIMETERS

MIN MAX

20.00 BSC

10.00 BSC

20.00 BSC

10.00 BSC

DIM

1.60

0.15

1.45

0.27

0.75

0.23

1.40

C1 0.05

C2 1.35

0.05 (0.005)

0.17

0.45

0.17

0.50 BSC.

0.20 BSC.

0.004 0.008

0.020 REF

0.25 (0.010)

0.20

0.09

GAGE PLANE

0.50 REF

0.25 BSC

0.010 BSC

0.20

22.00 BSC

11.00 BSC

22.00 BSC

11.00 BSC

R1 0.13

0.005 0.008

0.866 BSC

0.433 BSC

0.866 BSC

0.433 BSC

θ1

0.13

DETAIL "C"

0.25 REF

1.00 REF

0.010 REF

0.039 REF

0.16

0.004

AA 0.09

0.006

0°

7°

13°

0°

11°

7°

13°

11°

MOTOROLA

MC68EN302 REFERENCE MANUAL

9-5

Ordering and Mechanical Information

9.3 STANDARD ORDERING INFORMATION

PACKAGE TYPE

Thin Quad Flat Pack (TQFP)

FREQUENCY (MHZ)

TEMPERATURE

ORDER NUMBER

MC68EN302PV20

0 C-70 C

Thin Quad Flat Pack (TQFP)

MC68EN302PV25

PC68EN302RC25

0 C-70 C

Pin Grid Array (PGA)

(for development only, not available in production quantity)

0 C-70 C

9-6

MC68EN302 REFERENCE MANUAL

MOTOROLA

viii

MC68EN302 REFERENCE MANUAL

MOTOROLA

mit Q

Motorola : Semiconductors : 68K/ColdFire® : Products : 68K M683XX : MC68302

MC68302 : Integrated Multi-Protocol

Processor

Page Contents

●

Features

Parametrics

Documentation

Design Tools

The MC68302 is a versatile one-chip processor that incorporates the main building blocks

needed for the design of a wide variety of networking and communications products.

●

Orderable Parts

The MC68302 was the first device to offer the benefits of a closely coupled, industry-standard,

MC68000/MC68008 microprocessor core and a flexible communications architecture. This

multi-channel communications device may be configured to support a number of popular

industry-standard interfaces, including those for the Integrated Services Digital Network

(ISDN) basic rate and terminal adapter applications. Through a combination of architectural

and programmable features, concurrent operation of different protocols is easily achieved using

the MC68302. Data concentrators, modems, line cards, bridges, and gateways are examples of

other suitable applications for this versatile device.

Other Info

●

FAQs

Literature Services

68K/ColdFire®

Microcontrollers

Networking

PowerQUICC™

Communication

Processors

The MC68302 is an HCMOS device consisting of an MC68000/MC68008 microprocessor

core, a system integration block (SIB), and a communications processor (CP).

●

3rd Party Design Help

This device is still recommended for new designs.

Link

Product Picture

Link

Block Diagram

MC68302 Features

Product Highlights

●

MC68000/MC68008 Microprocessor Core

Efficient architecture involves a separate RISC processor for handling communications

Three Serial Communications Controllers (SCCs)

Support for HDLC/SDLC, Bisync, UART, DDCMP, and Totally Transparent protocols.

Two Serial Management Controllers (SMCs) for IDL and GCI Channel.

Available at 16, 20, 25, and 33 MHz in three different Thin Quad Flat Pack Packages.

Strong 3rd Party tools support.

Typical Applications

●

ISDN equipment

Data Concentrators

Modems

●

Line Cards

Network Bridges

Gateways

Technical Specifications

●

MC68000/MC68008 Microprocessor Core (May be disabled to use the IMP as a peripheral)

SIB Including:

❍

Independent Direct Memory Access (IDMA) Controller

Interrupt controller with two modes of operation

Parallel I/O ports, some with interrupt capability

On-Chip 1152-bytes of dual-port RAM

Three timers, with a software watchdog timer

Four programmable chip-select lines with wait-state logic

Programmable address mapping of dual-port RAM and IMP registers

●

On-Chip clock generator with an output clock signal

System Control

❍

Bus arbitration logic with low interrupt latency support

System control register

Hardware watchdog for monitoring bus activity

Low power (Standby) modes

Disable CPU logic (M68000)

Freeze control for debugging selected on-chip peripherals

DRAM refresh controller

●

CP Including:

❍

Main controller (RISC Processor)

Three full-duplex Serial Communication/Controllers with the following protocols:

❍

■

HDLC/SDLC

Bisync

UART

DDCMP

Totally Transparent

V.110

❍

Six serial DMA channels dedicated to the three SOCs

Capability to send/receive up to eight buffers/frames without M68000 core intervention

Flexible physical interface accessible by SCCs for Inter-chip Digital Link (IDL), General Circuit Interface

(GCI).

❍

Pulse Code Modulation (PCM), and Non-multiplexed Serial Interface (NMSI) Operation.

Serial Communication Port (SCP) for synchronous communication.

Two Serial Management Controllers (SMCs) for IDL and GCI Channel.

[top]

MC68302 Parametrics

Processor Speed Bus Interface

(MHz) (Bits)

Voltage

(V)

Description

Memory

Package

Performance

Integrated Multiprotocol

Processor (IMP)

No On-Chip

MMU

100 TQFP, 144

TQFP

16, 20

32 Data

1.6 (MC68000 Core)

[top]

MC68302 Documentation

Application Note

Name

Format Size K Rev # Date Last Modified Order Availability

AN2015/D

AN2016/D

Configuring the Chip Selects on the MC68302

DRAM Control with the MC68302

pdf

6/17/1991

3/21/1991

266

MC68302 Getting Started with Interrupts on the

MC68302

AN2018/D

AN2019/D

AN2020/D

AN2021/D

AN2023/D

pdf

3/14/1990

7/09/1990

1/01/1999

2/02/1993

7/26/1995

MC68302 Design Concept - Expanding Interrupts on

the MC68302

MC68302 Adapting a WAN Controller to a LAN

Environment

515

141

MC68302 Interfacing the MC68020 to a Slave

MC68302

MC68302 EKB Applications - Power Measurements

on the MC68302

AN2024/D

AN2026/D

MC68302 Software Performance

pdf

6/18/1990

2/27/1991

MC68302 Evaluating EDX on the ADS302

167

MC68302 Using the 302 Communications Peripheral

for PowerPC Microprocessors

AN2027/D

AN2028/D

AN2049/D

pdf

325

1/01/1994

3/31/1997

1/01/1998

MC68302 Design Advisory #1 - MC68SC302 Passive

ISDN Protocol Engine

MC68302, MC68360, and MPC860 Characteristics

and Design Notes for Crystal Feedback Oscillators

Brochure

Name

Format Size K Rev # Date Last Modified Order Availability

8-16BITPAK/D

8-16 Bit Microcontrollers Product Portfolio html

10/15/2002

10/14/2002

CFPITCHPAK/D

68K ColdFire Product Portfolio

html

Data Sheets

Name

Format Size K Rev # Date Last Modified Order Availability

pdf 55 1/01/1995

MC68EN302 Integrated Multiprotocol

Processor w/ Ethernet Product Brief

MC68EN302/D

MC68LC302 Low Cost Integrated

Multiprotocol Processor Product Brief

MC68LC302/D

MC68PM302/D

pdf

1/01/1995

MC68PM302 Integrated Multiprotocol

Processor w/ PCMCIA Product Brief

636

MC68QH302 Quad HDLC Integrated

Multiprotocol Processor Tech. Summary

Product Brief

MC68QH302/D

MC68SC302P/D

pdf

11/01/1997

1/01/1996

MC68SC302 Passive ISDN Protocol Engine

Product Brief

Engineering Bulletin

Name

Format Size K Rev #

pdf 31

Date Last Modified

3/30/2001

Order Availability

EB382/D

MC68302FC 132-Lead PQFP

Errata

Name

Format Size K Rev # Date Last Modified Order Availability

M68302 Errata Revision C.1 (Masks

0F26E, 1F26E)

MC68302DEC1/D

pdf

C.1

A.1

12/10/1998

2/20/1997

M68302 Device Errata - 68EN302

Integrated Multiprotocol Processor Device

MC68EN302DEA1/D

MC68EN302DEB/D

M68302 Device Errata - 68EN302

Integrated Multiprotocol Processor With

Ethernet Device

pdf

4/15/1999

8/02/1996

2/09/1999

10/28/1996

2/27/1997

M68302 Device Errata - 68LC302

Integrated Multiprotocol Processor

Devices

MC68LC302DEB/D

MC68LC302DEC/D

MC68PM302DEB1/D

MC68PM302DEC/D

M68302 Device Errata - MC68LC302

Integrated Multiprotocol Processor

Devices

M68302 Device Errata - 68PM302

Integrated Multiprotocol Processor

Devices

B.1

M68302 Revision C Changes - 68PM302

Integrated Multiprotocol Processor

Devices

M68302 Device Errata - MC68QH302

Chip Errata

MC68QH302DEC1/D

MC68SC302DEA1/D

pdf

C.1

A.1

8/05/1998

2/18/1998

M68302 Device Errata - XC68SC302

Fact Sheets

Name

Format Size K Rev # Date Last Modified Order Availability

MC68302FACT/D

M68302 Integrated Multiprotocol Processor pdf 30 1/01/1999

Miscellaneous

Name

Format Size K Rev # Date Last Modified Order Availability

M68302 Family Application Development

System

M68302FADS/D

pdf

1/01/1995

MC68302 Auto Baud Support Package

Specifications

MC68302ABSPEC/D

MC68302DEB/D

pdf

5/01/1994

8/06/2001

8/07/2001

2/06/1996

MC68302 DEB

MC68302 33 MHz AC Timing

Specification

MC68302TIMING/D

MC68EN302SCH/D

281

MC68302 Schematic for EN302

M68302 Device Errata - 68PM302

Integrated Multiprotocol Processor

Devices

MC68PM302DEC1/D

MC68QH302SUPL/D

pdf

C.1

2/27/1997

MC68QH302 Supplement to the

MC68302 Integrated Multiprotocol

Processor User's Manual

160

10/01/1997

Packages & Pinouts

Name

Format Size K Rev # Date Last Modified Order Availability

MC68302 TQFP Part Symbol (OrCAD

Capture 7.1+)

MC68302.OLB

MC68302TQFP

MC68EN302.OLB

zip

pdf

zip

pdf

10/31/1997

12/16/1999

11/06/1997

MC68302 Pin Assignment (TQFP)

MC68EN302 Part Symbol (OrCAD Capture

7.1+)

MC68EN302TQFP

PBGAPRES

MC68EN302 Pin Assignment (TQFP)

PBGA Customer Tutorial

12/16/1999

8/17/2000

pdf 2947

Product Change Notices

Name

Format Size K Rev # Date Last Modified Order Availability

PCN5656/D

MC68EN302 Capacity Expansion-PCN5656

pdf

5/25/2000

MC68EN302 Fab Transfer to TSC Addendum-

PCN5787

PCN5787/D

8/01/2000

PCN5792/D

PCN7917

MC68LC302 Fab Transfer to TSC-PCN5792

8/07/2000

8/19/2002

20X20 LQFP ASSY MOVE FROM SHC TO KLM htm

Reference Manual

Name

Format Size K Rev # Date Last Modified Order Availability

pdf 1815 12/30/1995

MC68302 Integrated Multiprotocol

Processor User's Manual

MC68302UM/D

Errata to MC68302 Integrated

Multiprotocol Processor Users Manual

MC68302UMAD3/D

MC68302UMAD4/D

pdf

3/19/1992

1/01/1998

Errata to MC68302 Integrated

Multiprotocol Processor Users Manual

Addendum to MC68302 Integrated

Multiprotocol Processor User Manual

(3.3 V Specifications)

MC68302UMADD33V/D

MC68EN302RM/D

pdf

191 0.1

7/19/2000

1/01/2000

11/15/1995

1/01/1995

2/21/1997

8/06/2001

1/01/1995

2/11/1997

MC68EN302 Integrated Multiprotocol

Processor with Ethernet Reference

Manual

686

Errata to MC68EN302 Integrated

Multiprotocol Processor with Ethernet pdf

Reference Manual Rev 1

MC68EN302RMAD/D

MC68LC302RM/AD

MC68LC302RMAD/D

MC68LC302UM/D

MC68LC302 Low Power Integrated

Multiprotocol Processor Reference

Manual

pdf 4958

MC68LC302 Low Power Integrated

Multiprotocol Processor Reference

Manual ERRATA

pdf

MC68LC302 Low Power Integrated

Multiprotocol Processor Reference

Manual

766

MC68PM302 Integrated Multiprotocol

Processor with PCMCIA Reference

Manual

MC68PM302RM/D

pdf 1126

Errata to MC68PM302 Integrated

Multiprotocol Processor with

PCMCIA Reference Manual

MC68PM302RMAD/D

pdf

MC68SC302 Passive ISDN Protocol

Engine User's Manual

MC68SC302RM /D

pdf

521

1/01/1997

7/15/1998

MC68SC302 Errata to MC68SC302

Users Manual

MC68SC302UMAD/AD

Reports or Presentations

Name

Format Size K Rev # Date Last Modified Order Availability

pdf 61 7/30/2002

Codec, Communication Processor, and ISDN

Orderable Parts

ORDPARTS

Selector Guide

Name

Format Size K Rev # Date Last Modified Order Availability

SG1006/D

SG1007/D

SG1011/D

Microcontrollers SPS Sales Guide

Network and Communications Processors Sales Guide pdf

Software and Development Tools Sales Guide pdf

pdf

600

161

259

9/26/2002

Users Guide

Name

Format Size K Rev # Date Last Modified Order Availability

MC68302FADSUM/D

MC68302FADS User's Manual

pdf

863

10/17/1995

1/01/1997

1/01/1999

1/01/1996

MC68302 PIAFS Microcode for

MC68302(IMP) Family User's Manual

MC68302PIAFSUM/D

MC68EN302ADPUM/D

MC68SC302ADSUM/D

MC68EN302 Adapter User's Manual

193

862

MC68SC302ADS Application

Development System User's Manual

[top]

Design Tools

BSDL Files

Name

Vendor ID

Format Size K Rev #

txt 20 0.1

MC68EN302 BSDL for JTAG Logic Ver. 0.1

(02/29/1996)

MC68EN302BSDL

MOTOROLA

Drivers

Name

Vendor ID

Format Size K Rev #

html

MC68302 Configuration and Driver Files

(12/04/1997)

MC68302DRV01

MOTOROLA

Microcode

Name

Vendor ID

Format Size K Rev #

MC68302 Autobaud 2.0 Microcode - M68302SWAUT

(02/22/99)

MC68302MC1

MOTOROLA

zip

srx

zip

MC68302 Centronics Microcode - M68302SWCEN

(02/22/99)

MC68302MC2

MC68302MC3

MC68302MC4

MC68302MC5

MC68302MC6

MC68QH302MC1

MC68302 Profibus Microcode - M68302SWPRO

(02/22/99)

MC68302 SS7 Microcode - M68302SWSS7

(03/06/2002)

104

1.1

MC68302 V 110 Microcode - M68302SWV110

(02/22/99)

MC68302 PIAFS Microcode - M68302SWPIA

(01/26/00)

Autobaud Microcode for the MC68QH302

(08/28/98)

Reference Designs

Name

Vendor ID Format Size K Rev #

Firefly 2B - ISDN Active Terminal Adapter Reference Design

Using MC68QH302 (Preliminary)

(01/14/1997)

MC68QH302RD1

MOTOROLA pdf

Firefly 2B - Schematics for ISDN Active Terminal Adapter

Reference Design using MC68QH302 (Preliminary)

(01/14/1997)

MC68QH302RD2

463

MC68SC302 Passive ISA U-Interface Reference Design BOM

(01/16/1997)

MC68SC302RD1

MC68SC302RD2

MOTOROLA txt

MOTOROLA zip

MC68SC302 Passive ISDN Terminal Adapter Design (Gerber)

(06/27/1997)

109

MC68SC302 Passive ISDN Terminal Adapter Design (Tango Pro

MC68SC302RD3

MC68SC302RD4

MC68SC302RD5

CAD)

(01/07/1997)

MOTOROLA zip

MOTOROLA pdf

MOTOROLA tar

288

546

160

MC68SC302 Passive U ISDN Card Reference Design

(12/06/1996)

MC68SC302 PNP EEPROM Maker Script and Example Files (for

Sun in PERL)

(01/08/1997)

MC68SC302 S/T-Interface Passive Terminal Adapter Reference

MC68SC302RD6

Design

MOTOROLA pdf

282

(01/08/1997)

Schematics

Name

Vendor ID

Format Size K Rev #

M68EN302 FADS Adapter (ENA) Schematics

(02/06/1996)

M68EN302FADSSCH

M68XX302FADSSCH

MOTOROLA

pdf

281

630

M68xx302 FADS Schematics

(12/04/1996)

MOTOROLA

Software

Name

Vendor ID Format Size K Rev #

M68xx302 Family Application Development System (302

M68XX302FADSSW1

FADS) Software

(12/23/1997)

MOTOROLA zip

563 0.4

MC68302 Application Development System Software

(12/04/1996)

MC68302ADSSW1

MC68302ADSSW2

MC68302COD1

MOTOROLA html

MOTOROLA txt

MOTOROLA html

MC68302ADS IBM-PC Host Files

(12/04/1996)

MC68302 Code for Setting Up an SCC in UART Mode

(12/04/1996)

MC68302 Demo Code for the 302ADS Board

08/31/1990

MC68302COD2

Sample Code - Configuring a UART on the MC68302

(12/04/1996)

MC68302COD3

MC68302COD4

MC68302COD5

MC68EN302COD1

MOTOROLA txt

MOTOROLA zip

MC68302 Source Code for ISDN Smart NT1 Layer 1

(02/04/1997)

MC68302 Confidence Test Software

(10/22/2001)

194

454

MC68EN302 Software Example

(05/13/1997)

MC68SC302 Application Development System Software

** Not recommended for new design. Part is on EOL

notification. **

MC68SC302SW

MOTOROLA zip

271 3.1

(09/24/1997)

Supporting Information

Name

Vendor ID

MOTOROLA

Format Size K Rev #

MC68EN302 Getting Started Hints

MC68EN302_START

txt

[top]

Orderable Parts Information

Budgetary

Price

QTY 1000+ Availability

($US)

Order

Life Cycle Description (code)

PartNumber

Package Info

Remarks

16MHz,

extended

temp

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

MC68302CFC16C

MC68302CFC20C

MC68302CPV16VC

MC68302CRC16C

$16.04

$18.20

$19.37

$42.44

20MHz,

extended

temp

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

16MHz,

extended

temp

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

16MHz,

extended

temp

PRODUCT

MATURITY/SATURATION(4)

PGA 132

20MHz,

extended

temp

PRODUCT

MATURITY/SATURATION(4)

MC68302CRC20C

MC68302FC16C

$53.05

$13.35

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

16MHz

Packaged

in Tape &

Reel

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

MC68302FC16CR2

MC68302FC20C

$15.72

$15.17

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

20MHz

Packaged

in Tape &

Reel

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

MC68302FC20CR2

MC68302FC25C

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

25MHz

$16.97

$20.44

Packaged

in Tape &

Reel

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

MC68302FC25CR2

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

MC68302PV16C

MC68302PV16VC

MC68302PV20C

MC68302PV25C

MC68302PV33C

MC68302RC16C

MC68302RC20C

MC68302RC25C

16MHz

20MHz

25MHz

33MHz

16MHz

20MHz

25MHz

$12.91

$16.13

$14.71

$16.52

$18.32

$40.32

$50.40

$63.00

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

PRODUCT

MATURITY/SATURATION(4)

PGA 132

PRODUCT

MATURITY/SATURATION(4)

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

SPAK302CFC20C

SPAK302FC25C

SPAK302PV16VC

$20.19

$20.44

$20.47

part

number for

ordering

samples

only

PQFP 132

0.950*.950P.025

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

SPAK302PV33C

$21.79

$50.79

$11.35

$13.61

$15.87

$22.73

$27.27

part

number for

ordering

samples

only

PRODUCT

MATURITY/SATURATION(4)

SPAK302RC25C

PGA 132

part

number for

ordering

samples

only

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

KMC68LC302PU16CT

KMC68LC302PU20CT

KMC68LC302PU25CT

KM68LC302PU20VCT

KMC68EN302PV20BT

KMC68EN302PV25BT

part

number for

ordering

samples

only

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

part

number for

ordering

samples

only

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

MC68EN302CPV20BT

MC68EN302PV20BT

MC68EN302PV25BT

M68LC302CPU16VCT

20MHz

25MHz

$21.65

$18.04

$21.65

$13.05

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 144

20*20*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

M68LC302CPU20VCT

MC68LC302CPU16CT

MC68LC302CPU20CT

MC68LC302PU16CT

MC68LC302PU16VCT

MC68LC302PU20CT

MC68LC302PU20VCT

MC68LC302PU25CT

$13.44

$8.74

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

16MHz

20MHz

16MHz

20MHz

25MHz

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

$10.93

$8.56

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

$12.80

$10.71

$13.18

$12.80

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

LQFP 100

14*14*1.4P0.5

PRODUCT

MATURITY/SATURATION(4)

[top]

Products | Documentation | Tools | Design Resources | Applications

MC68302FC16CR2 [MOTOROLA]

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