MC68331 [MOTOROLA]
User’s Manual; 用户手册
| 型号： | MC68331 |
| 厂家： | 
MOTOROLA |
| 描述： | User’s Manual |
| 文件： | 总254页 (文件大小：1319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68331
User’s Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability
of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and
all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including
"Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others.
Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and ! are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© MOTOROLA, INC. 1996
TABLE OF CONTENTS
Paragraph
Title
Page
SECTION 1INTRODUCTION
SECTION 2NOMENCLATURE
2.1
2.2
2.3
2.4
2.5
Symbols and Operators ..................................................................................2-1
CPU32 Registers ............................................................................................2-2
Pin and Signal Mnemonics .............................................................................2-3
Register Mnemonics .......................................................................................2-5
Conventions ...................................................................................................2-6
SECTION 3OVERVIEW
3.1
MCU Features ................................................................................................3-1
System Integration Module (SIM) ...........................................................3-1
Central Processing Unit (CPU32) ...........................................................3-1
Queued Serial Module (QSM) ................................................................3-1
General-Purpose Timer (GPT) ...............................................................3-2
System Block Diagram and Pin Assignment Diagrams ..................................3-2
Pin Descriptions .............................................................................................3-5
Signal Descriptions .........................................................................................3-7
Intermodule Bus ...........................................................................................3-10
System Memory Map ...................................................................................3-10
Internal Register Map ...........................................................................3-10
Address Space Maps ...........................................................................3-10
System Reset ...............................................................................................3-16
SIM Reset Mode Selection ...................................................................3-16
MCU Module Pin Function During Reset .............................................3-17
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
SECTION 4 SYSTEM INTEGRATION MODULE
4.1
4.2
General ...........................................................................................................4-1
System Configuration and Protection .............................................................4-2
Module Mapping .....................................................................................4-3
Interrupt Arbitration .................................................................................4-3
Show Internal Cycles ..............................................................................4-4
Factory Test Mode .................................................................................4-4
Register Access .....................................................................................4-4
Reset Status ...........................................................................................4-4
Bus Monitor ............................................................................................4-4
Halt Monitor ............................................................................................4-5
Spurious Interrupt Monitor ......................................................................4-5
Software Watchdog ................................................................................4-5
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10
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4.2.11
4.2.12
4.2.13
Periodic Interrupt Timer ..........................................................................4-7
Low-Power STOP Operation ..................................................................4-8
Freeze Operation ...................................................................................4-9
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
4.4.1.6
4.4.1.7
4.4.1.8
4.4.1.9
4.4.1.10
4.4.1.11
4.4.2
4.4.3
4.4.4
4.4.5
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
System Clock .................................................................................................4-9
Clock Sources ......................................................................................4-10
Clock Synthesizer Operation ................................................................4-10
External Bus Clock ...............................................................................4-15
Low-Power Operation ...........................................................................4-15
Loss of Reference Signal .....................................................................4-16
External Bus Interface ..................................................................................4-17
Bus Signals ..........................................................................................4-18
Address Bus ................................................................................. 4-18
Address Strobe ............................................................................ 4-18
Data Bus ...................................................................................... 4-18
Data Strobe .................................................................................. 4-18
Read/Write Signal ........................................................................ 4-18
Size Signals ................................................................................. 4-18
Function Codes ............................................................................ 4-19
Data and Size Acknowledge Signals ........................................... 4-19
Bus Error Signal ........................................................................... 4-19
Halt Signal .................................................................................... 4-20
Autovector Signal ......................................................................... 4-20
Dynamic Bus Sizing .............................................................................4-20
Operand Alignment ..............................................................................4-21
Misaligned Operands ...........................................................................4-21
Operand Transfer Cases ......................................................................4-22
Bus Operation ..............................................................................................4-22
Synchronization to CLKOUT ................................................................4-23
Regular Bus Cycles ..............................................................................4-23
Read Cycle ................................................................................... 4-24
Write Cycle ................................................................................... 4-25
Fast Termination Cycles .......................................................................4-25
CPU Space Cycles ...............................................................................4-26
Breakpoint Acknowledge Cycle .................................................... 4-27
LPSTOP Broadcast Cycle ............................................................ 4-30
Bus Exception Control Cycles ..............................................................4-30
Bus Errors .................................................................................... 4-32
Double Bus Faults ........................................................................ 4-32
Retry Operation ............................................................................ 4-33
Halt Operation .............................................................................. 4-33
External Bus Arbitration ........................................................................4-34
4.5.4
4.5.4.1
4.5.4.2
4.5.5
4.5.5.1
4.5.5.2
4.5.5.3
4.5.5.4
4.5.6
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4.5.6.1
4.5.6.2
Slave (Factory Test) Mode Arbitration ......................................... 4-35
Show Cycles ................................................................................ 4-35
4.6
Reset ............................................................................................................4-36
Reset Exception Processing ................................................................4-36
Reset Control Logic ..............................................................................4-37
Reset Mode Selection ..........................................................................4-37
Data Bus Mode Selection ............................................................. 4-38
Clock Mode Selection .................................................................. 4-40
Breakpoint Mode Selection .......................................................... 4-40
MCU Module Pin Function During Reset .............................................4-40
Pin State During Reset .........................................................................4-41
Reset States of SIM Pins ............................................................. 4-41
Reset States of Pins Assigned to Other MCU Modules ............... 4-42
Reset Timing ........................................................................................4-42
Power-On Reset ...................................................................................4-43
Reset Processing Summary .................................................................4-44
Reset Status Register ..........................................................................4-45
Interrupts ......................................................................................................4-45
Interrupt Exception Processing ............................................................4-45
Interrupt Priority and Recognition .........................................................4-45
Interrupt Acknowledge and Arbitration .................................................4-46
Interrupt Processing Summary .............................................................4-47
Interrupt Acknowledge Bus Cycles .......................................................4-48
Chip Selects .................................................................................................4-48
Chip-Select Registers ...........................................................................4-50
Chip-Select Pin Assignment Registers ........................................ 4-51
Chip-Select Base Address Registers ........................................... 4-52
Chip-Select Option Registers ....................................................... 4-52
PORTC Data Register .................................................................. 4-54
Chip-Select Operation ..........................................................................4-54
Using Chip-Select Signals for Interrupt Acknowledge ..........................4-54
Chip-Select Reset Operation ................................................................4-55
Parallel Input/Output Ports ...........................................................................4-57
Pin Assignment Registers ....................................................................4-57
Data Direction Registers ......................................................................4-57
Data Registers ......................................................................................4-57
Factory Test .................................................................................................4-57
4.6.1
4.6.2
4.6.3
4.6.3.1
4.6.3.2
4.6.3.3
4.6.4
4.6.5
4.6.5.1
4.6.5.2
4.6.6
4.6.7
4.6.8
4.6.9
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.1.3
4.8.1.4
4.8.2
4.8.3
4.8.4
4.9
4.9.1
4.9.2
4.9.3
4.10
SECTION 5 CENTRAL PROCESSING UNIT
5.1
5.2
General ...........................................................................................................5-1
CPU32 Registers ............................................................................................5-2
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5.2.1
5.2.2
5.2.3
5.2.4
5.2.4.1
5.2.4.2
5.2.5
Data Registers ........................................................................................5-4
Address Registers ..................................................................................5-5
Program Counter ....................................................................................5-6
Control Registers ....................................................................................5-6
Status Register ............................................................................... 5-6
Alternate Function Code Registers ................................................ 5-6
Vector Base Register (VBR) ...................................................................5-7
5.3
5.4
5.5
5.6
5.7
5.8
5.8.1
5.8.2
5.8.2.1
5.8.2.2
5.9
5.9.1
5.9.2
Memory Organization .....................................................................................5-7
Virtual Memory ...............................................................................................5-9
Addressing Modes ..........................................................................................5-9
Processing States ..........................................................................................5-9
Privilege Levels ............................................................................................5-10
Instructions ...................................................................................................5-10
M68000 Family Compatibility ...............................................................5-14
Special Control Instructions ..................................................................5-14
Low Power Stop (LPSTOP) ......................................................... 5-14
Table Lookup and Interpolate (TBL) ............................................ 5-14
Exception Processing ...................................................................................5-14
Exception Vectors ................................................................................5-15
Types of Exceptions .............................................................................5-16
Exception Processing Sequence ..........................................................5-17
Development Support ...................................................................................5-17
M68000 Family Development Support .................................................5-17
Background Debugging Mode ..............................................................5-18
Enabling BDM .............................................................................. 5-19
BDM Sources ............................................................................... 5-19
Entering BDM ............................................................................... 5-20
BDM Commands .......................................................................... 5-21
Background Mode Registers ........................................................ 5-21
Returning from BDM .................................................................... 5-22
Serial Interface ............................................................................. 5-22
Recommended BDM Connection ................................................. 5-24
Deterministic Opcode Tracking ............................................................5-24
On-Chip Breakpoint Hardware .............................................................5-25
Loop Mode Instruction Execution .................................................................5-25
5.9.3
5.10
5.10.1
5.10.2
5.10.2.1
5.10.2.2
5.10.2.3
5.10.2.4
5.10.2.5
5.10.2.6
5.10.2.7
5.10.2.8
5.10.3
5.10.4
5.11
SECTION 6QUEUED SERIAL MODULE
6.1
6.2
6.2.1
6.2.1.1
General ...........................................................................................................6-1
QSM Registers and Address Map ..................................................................6-2
QSM Global Registers ............................................................................6-2
Low-Power Stop Operation ............................................................ 6-2
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6.2.1.2
6.2.1.3
6.2.2
Freeze Operation ........................................................................... 6-3
QSM Interrupts ............................................................................... 6-3
QSM Pin Control Registers ....................................................................6-4
6.3
6.3.1
Queued Serial Peripheral Interface ................................................................6-5
QSPI Registers .......................................................................................6-6
Control Registers ........................................................................... 6-7
Status Register ............................................................................... 6-7
QSPI RAM ..............................................................................................6-7
Receive RAM ................................................................................. 6-8
Transmit RAM ................................................................................ 6-8
Command RAM .............................................................................. 6-8
QSPI Pins ...............................................................................................6-8
QSPI Operation ......................................................................................6-9
QSPI Operating Modes ........................................................................6-10
Master Mode ................................................................................ 6-17
Master Wraparound Mode ........................................................... 6-19
Slave Mode .................................................................................. 6-20
Slave Wraparound Mode ............................................................. 6-21
Peripheral Chip Selects ........................................................................6-21
Serial Communication Interface ...................................................................6-22
SCI Registers .......................................................................................6-22
Control Registers ......................................................................... 6-22
Status Register ............................................................................. 6-25
Data Register ............................................................................... 6-25
SCI Pins ...............................................................................................6-25
SCI Operation .......................................................................................6-25
Definition of Terms ....................................................................... 6-26
Serial Formats .............................................................................. 6-26
Baud Clock ................................................................................... 6-26
Parity Checking ............................................................................ 6-27
Transmitter Operation .................................................................. 6-27
Receiver Operation ...................................................................... 6-29
Idle-Line Detection ....................................................................... 6-29
Receiver Wakeup ......................................................................... 6-30
Internal Loop ................................................................................ 6-31
QSM Initialization .........................................................................................6-31
6.3.1.1
6.3.1.2
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.3
6.3.4
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.3.6
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.1.3
6.4.2
6.4.3
6.4.3.1
6.4.3.2
6.4.3.3
6.4.3.4
6.4.3.5
6.4.3.6
6.4.3.7
6.4.3.8
6.4.3.9
6.5
SECTION 7GENERAL-PURPOSE TIMER
7.1
7.2
7.3
General ...........................................................................................................7-1
GPT Registers and Address Map ...................................................................7-2
Special Modes of Operation ...........................................................................7-3
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7.3.1
7.3.2
7.3.3
7.3.4
Low-Power Stop Mode ...........................................................................7-3
Freeze Mode ..........................................................................................7-3
Single-Step Mode ...................................................................................7-3
Test Mode ..............................................................................................7-4
7.4
Polled and Interrupt-Driven Operation ............................................................7-4
Polled Operation .....................................................................................7-4
GPT Interrupts ........................................................................................7-5
Pin Descriptions .............................................................................................7-6
Input Capture Pins (IC[1:3]) ....................................................................7-6
Input Capture/Output Compare Pin (IC4/OC5) ......................................7-6
Output Compare Pins (OC[1:4]) .............................................................7-6
Pulse Accumulator Input Pin (PAI) .........................................................7-7
Pulse-Width Modulation (PWMA, PWMB) ..............................................7-7
Auxiliary Timer Clock Input (PCLK) ........................................................7-7
General-Purpose I/O ......................................................................................7-7
Prescaler ........................................................................................................7-8
Capture/Compare Unit ...................................................................................7-9
Timer Counter ......................................................................................7-11
Input Capture Functions .......................................................................7-11
Output Compare Functions ..................................................................7-12
Output Compare 1 ........................................................................ 7-13
Forced Output Compare .............................................................. 7-13
Input Capture 4/Output Compare 5 ..............................................................7-13
Pulse Accumulator .......................................................................................7-14
Pulse-Width Modulation Unit ........................................................................7-15
PWM Counter .......................................................................................7-16
PWM Function ......................................................................................7-17
7.4.1
7.4.2
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.7
7.8
7.8.1
7.8.2
7.8.3
7.8.3.1
7.8.3.2
7.9
7.10
7.11
7.11.1
7.11.2
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
C.1
C.2
M68MMDS1632 Modular Development System ...................................... C-1
M68MEVB1632 Modular Evaluation Board .............................................. C-2
APPENDIX D REGISTER SUMMARY
D.1
D.1.1
D.1.2
Central Processing Unit ............................................................................ D-1
CPU32 Register Model ..................................................................... D-2
— Status Register ............................................................................ D-3
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D.2
D.2.1
D.2.2
D.2.3
D.2.4
D.2.5
D.2.6
D.2.7
General-Purpose Timer ............................................................................ D-4
GPTMCR — GPT Module Configuration Register ............................ D-4
GPTMTR — GPT Module Test Register (Reserved) ........................ D-5
ICR — GPT Interrupt Configuration Register.................................... D-5
DDRGP — Port GP Data Direction Register..................................... D-6
OC1M— OC1 Action Mask Register................................................. D-6
TCNT — Timer Counter Register ..................................................... D-6
PACTL — Pulse Accumulator Control Register ................................ D-7
TIC[1:3] — Input Capture Registers 1–3 .......................................... D-8
TOC[1:4] — Output Compare Registers 1–4 ................................... D-8
TI4/O5 — Input Capture 4/Output Compare 5 Register.................... D-8
TCTL1/TCTL2 — Timer Control Registers 1 and 2........................... D-8
TMSK1/TMSK2 — Timer Interrupt Mask Registers 1 and 2 ............. D-9
TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2.............. D-10
CFORC — Compare Force Register............................................... D-10
PWMA/PWMB — PWM Registers A/B ........................................... D-12
PWMCNT — PWM Count Register ............................................... D-12
PWMBUFA — PWM Buffer Register A .......................................... D-12
PRESCL — GPT Prescaler ............................................................ D-12
System Integration Module ..................................................................... D-13
SIMCR — Module Configuration Register ...................................... D-14
SIMTR — System Integration Test Register ................................... D-15
SYNCR — Clock Synthesizer Control Register ............................. D-15
RSR — Reset Status Register ....................................................... D-16
SIMTRE — System Integration Test Register (ECLK).................... D-17
PORTE0/PORTE1 — Port E Data Register.................................... D-17
DDRE — Port E Data Direction Register ........................................ D-17
PEPAR — Port E Pin Assignment Register .................................... D-17
PORTF0/PORTF1 — Port F Data Register..................................... D-18
DDRF — Port F Data Direction Register......................................... D-18
PFPAR — Port F Pin Assignment Register..................................... D-18
SYPCR — System Protection Control Register .............................. D-19
PICR — Periodic Interrupt Control Register.................................... D-20
PITR — Periodic Interrupt Timer Register ...................................... D-20
SWSR — Software Service Register .............................................. D-21
TSTMSRA — Master Shift Register A............................................. D-21
TSTMSRB — Master Shift Register B............................................. D-21
TSTSC — Test Module Shift Count ................................................ D-21
TSTRC — Test Module Repetition Count ....................................... D-21
CREG — Test Submodule Control Register .................................. D-21
DREG — Distributed Register......................................................... D-21
D.2.8
D.2.9
D.2.10
D.2.11
D.2.12
D.2.13
D.2.14
D.2.15
D.2.16
D.2.17
D.2.18
D.3
D.3.1
D.3.2
D.3.3
D.3.4
D.3.5
D.3.6
D.3.7
D.3.8
D.3.9
D.3.10
D.3.11
D.3.12
D.3.13
D.3.14
D.3.15
D.3.16
D.3.17
D.3.18
D.3.19
D.3.20
D.3.21
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D.3.22
D.3.23
D.3.24
D.3.25
D.3.26
PORTC — Port C Data Register..................................................... D-21
CSPAR0 — Chip Select Pin Assignment Register 0....................... D-21
CSPAR1 — Chip Select Pin Assignment Register 1....................... D-22
CSBARBT — Chip Select Base Address Register Boot ROM ....... D-23
CSORBT — Chip Select Option Register Boot ROM...................... D-23
D.4
Queued Serial Module ............................................................................ D-25
QSMCR — QSM Configuration Register ........................................ D-25
QTEST — QSM Test Register ........................................................ D-26
QILR — QSM Interrupt Level Register............................................ D-26
SCCR0 — SCI Control Register 0 .................................................. D-27
SCCR1 — SCI Control Register 1................................................... D-27
SCSR — SCI Status Register ......................................................... D-29
SCDR — SCI Data Register............................................................ D-30
PORTQS — Port QS Data Register ............................................... D-30
PQSPAR — PORT QS Pin Assignment Register ........................... D-30
SPCR0 — QSPI Control Register 0 ................................................ D-32
SPCR1 — QSPI Control Register 1 ............................................... D-33
SPCR2 — QSPI Control Register 2 ............................................... D-34
SPCR3 — QSPI Control Register 3 ............................................... D-34
RR[0:F] — Receive Data RAM........................................................ D-35
TR[0:F] — Transmit Data RAM ...................................................... D-35
CR[0:F] — Command RAM............................................................. D-36
D.4.1
D.4.2
D.4.3
D.4.4
D.4.5
D.4.6
D.4.7
D.4.8
D.4.9
D.4.10
D.4.11
D.4.12
D.4.13
D.4.14
D.4.15
D.4.16
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Figure
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
MCU Block Diagram........................................................................................ 3-3
Pin Assignments for 132-Pin Package............................................................ 3-4
Pin Assignments for 144-Pin Package............................................................ 3-5
Internal Register Memory Map...................................................................... 3-11
Overall Memory Map..................................................................................... 3-12
Separate Supervisor and User Space Map................................................... 3-13
Supervisor Space (Separate Program/Data Space) Map ............................. 3-14
User Space (Separate Program/Data Space) Map....................................... 3-15
System Integration Module Block Diagram ..................................................... 4-2
System Configuration and Protection.............................................................. 4-3
Periodic Interrupt Timer and Software Watchdog Timer ................................. 4-7
System Clock Block Diagram.......................................................................... 4-9
System Clock Oscillator Circuit ..................................................................... 4-10
System Clock Filter Networks ....................................................................... 4-11
MCU Basic System ....................................................................................... 4-17
Operand Byte Order...................................................................................... 4-21
Word Read Cycle Flowchart.......................................................................... 4-24
Write Cycle Flowchart ................................................................................... 4-25
CPU Space Address Encoding ..................................................................... 4-27
Breakpoint Operation Flowchart.................................................................... 4-29
LPSTOP Interrupt Mask Level....................................................................... 4-30
Bus Arbitration Flowchart for Single Request................................................ 4-35
Data Bus Mode Select Conditioning.............................................................. 4-39
Power-On Reset............................................................................................ 4-44
Basic MCU System ....................................................................................... 4-49
Chip-Select Circuit Block Diagram ................................................................ 4-50
CPU Space Encoding for Interrupt Acknowledge.......................................... 4-55
CPU32 Block Diagram .................................................................................... 5-2
User Programming Model ............................................................................... 5-3
Supervisor Programming Model Supplement.................................................. 5-3
Data Organization in Data Registers............................................................... 5-5
Address Organization in Address Registers.................................................... 5-5
Memory Operand Addressing ......................................................................... 5-8
Common In-Circuit Emulator Diagram .......................................................... 5-18
Bus State Analyzer Configuration ................................................................. 5-19
Debug Serial I/O Block Diagram ................................................................... 5-23
BDM Serial Data Word.................................................................................. 5-24
BDM Connector Pinout.................................................................................. 5-24
Loop Mode Instruction Sequence.................................................................. 5-25
QSM Block Diagram........................................................................................ 6-1
QSPI Block Diagram ....................................................................................... 6-6
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
6-1
6-2
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Figure
Title
Page
6-3
6-4
6-5
6-5
6-5
6-6
6-6
6-7
6-8
7-1
7-2
7-3
7-4
7-5
7-6
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
A-16
A-17
A-18
A-19
B-1
B-2
D-1
D-2
QSPI RAM....................................................................................................... 6-7
Flowchart of QSPI Initialization Operation..................................................... 6-11
Flowchart of QSPI Master Operation (Part 1) ............................................... 6-12
Flowchart of QSPI Master Operation (Part 2) ............................................... 6-13
Flowchart of QSPI Master Operation (Part 3) ............................................... 6-14
Flowchart of QSPI Slave Operation (Part 1) ................................................. 6-15
Flowchart of QSPI Slave Operation (Part 2) ................................................. 6-16
SCI Transmitter Block Diagram..................................................................... 6-23
SCI Receiver Block Diagram......................................................................... 6-24
GPT Block Diagram......................................................................................... 7-2
Prescaler Block Diagram................................................................................. 7-9
Capture/Compare Unit Block Diagram.......................................................... 7-10
Input Capture Timing Example...................................................................... 7-12
Pulse Accumulator Block Diagram................................................................ 7-15
PWM Block Diagram ..................................................................................... 7-16
CLKOUT Output Timing Diagram..................................................................A-12
External Clock Input Timing Diagram............................................................A-12
ECLK Output Timing Diagram.......................................................................A-12
Read Cycle Timing Diagram .........................................................................A-13
Write Cycle Timing Diagram..........................................................................A-14
Fast Termination Read Cycle Timing Diagram .............................................A-15
Fast Termination Write Cycle Timing Diagram..............................................A-16
Bus Arbitration Timing Diagram — Active Bus Case ....................................A-17
Bus Arbitration Timing Diagram — Idle Bus Case ........................................A-18
Show Cycle Timing Diagram.........................................................................A-18
Chip Select Timing Diagram..........................................................................A-19
Reset and Mode Select Timing Diagram.......................................................A-19
Background Debugging Mode Timing Diagram—Serial Communication......A-21
Background Debugging Mode Timing Diagram —Freeze Assertion.............A-21
ECLK Timing Diagram...................................................................................A-23
QSPI Timing — Master, CPHA = 0 ...............................................................A-25
QSPI Timing — Master, CPHA = 1 ...............................................................A-25
QSPI Timing — Slave, CPHA = 0 .................................................................A-26
QSPI Timing — Slave, CPHA = 1 .................................................................A-26
132-Pin Plastic Surface Mount Package Pin Assignments .............................B-2
144-Pin Plastic Surface Mount Package Pin Assignments .............................B-3
User Programming Model ...............................................................................D-2
Supervisor Programming Model Supplement..................................................D-2
MOTOROLA
xii
MC68331
USER’S MANUAL
LIST OF TABLES
Table
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
5-1
5-2
5-3
5-4
5-5
5-6
6-1
6-2
6-3
MCU Driver Types .......................................................................................... 3-6
MCU Pin Characteristics ................................................................................ 3-6
MCU Power Connections ............................................................................... 3-7
Signal Characteristics ..................................................................................... 3-7
Signal Function ............................................................................................... 3-8
SIM Reset Mode Selection ........................................................................... 3-16
Module Pin Functions ................................................................................... 3-17
Show Cycle Enable Bits ................................................................................. 4-4
Bus Monitor Period ......................................................................................... 4-5
MODCLK Pin and SWP Bit During Reset ...................................................... 4-6
Software Watchdog Ratio ............................................................................... 4-6
MODCLK Pin and PTP Bit at Reset ............................................................... 4-7
Periodic Interrupt Priority ................................................................................ 4-8
Clock Control Multipliers ............................................................................... 4-12
System Frequencies from 32.768-kHz Reference ....................................... 4-14
Clock Control ................................................................................................ 4-16
Size Signal Encoding ................................................................................... 4-19
Address Space Encoding ............................................................................. 4-19
Effect of DSACK Signals .............................................................................. 4-20
Operand Transfer Cases .............................................................................. 4-22
DSACK, BERR, and HALT Assertion Results ............................................. 4-31
Reset Source Summary ............................................................................... 4-37
Reset Mode Selection .................................................................................. 4-38
Module Pin Functions ................................................................................... 4-41
SIM Pin Reset States ................................................................................... 4-42
Chip-Select Pin Functions ............................................................................ 4-51
Pin Assignment Field Encoding .................................................................... 4-51
Block Size Encoding ..................................................................................... 4-52
Option Register Function Summary ............................................................. 4-53
Chip Select Base and Option Register Reset Values .................................. 4-56
CSBOOT Base and Option Register Reset Values ..................................... 4-57
Instruction Set Summary .............................................................................. 5-11
Exception Vector Assignments ..................................................................... 5-16
BDM Source Summary ................................................................................. 5-19
Polling the BDM Entry Source ...................................................................... 5-20
Background Mode Command Summary ...................................................... 5-21
CPU Generated Message Encoding ............................................................ 5-24
QSM Pin Function .......................................................................................... 6-4
QSPI Pin Function .......................................................................................... 6-9
BITS Encoding ............................................................................................. 6-18
SCI Pin Function .......................................................................................... 6-25
6-4
MC68331
MOTOROLA
USER’S MANUAL
xiii
LIST OF TABLES
(Continued)
Table
Title
Page
6-5
6-6
7-1
7-2
Serial Frame Formats ...................................................................................6-26
Effect of Parity Checking on Data Size .........................................................6-27
GPT Status Flags ............................................................................................7-4
GPT Interrupt Sources ....................................................................................7-5
PWM Frequency Ranges Using 16.78-MHz/20.97-MHz System Clocks ......7-17
Maximum Ratings .......................................................................................... A-1
Typical Ratings, 16.78 MHz Operation .......................................................... A-2
Typical Ratings, 20.97 MHz Operation ......................................................... A-2
Thermal Characteristics ................................................................................. A-3
16.78 MHz Clock Control Timing ................................................................... A-3
20.97 MHz Clock Control Timing ................................................................... A-4
16.78 MHz DC Characteristics ....................................................................... A-5
20.97 MHz DC Characteristics ....................................................................... A-6
16.78 MHz AC Timing .................................................................................... A-8
20.97 MHz AC Timing .................................................................................... A-9
Background Debugging Mode Timing .......................................................... A-20
16.78 MHz ECLK Bus Timing ...................................................................... A-22
20.97 MHz ECLK Bus Timing ...................................................................... A-22
QSPI Timing ................................................................................................. A-24
MCU Ordering Information ............................................................................. B-4
Quantity Order Suffix ...................................................................................... B-4
MC68331 Development Tools ........................................................................C-1
Module Address Map .....................................................................................D-1
GPT Address Map ..........................................................................................D-4
SIM Address Map .........................................................................................D-13
Port E Pin Assignments ...............................................................................D-18
Port F Pin Assignments ................................................................................D-19
Software Watchdog Ratio ............................................................................D-19
Bus Monitor Period .......................................................................................D-20
CSPAR0 Pin Assignments ...........................................................................D-22
CSPAR1 Pin Assignments ...........................................................................D-22
CSPAR0 and CSPAR1 Pin Assignment Field Encoding ..............................D-22
Block Size Encoding ....................................................................................D-23
Option Register Function Summary .............................................................D-24
QSM Address Map .......................................................................................D-25
PQSPAR Pin Assignments ..........................................................................D-31
Effect of DDRQS on PORTQS Pins .............................................................D-31
Effect of DDRQS on QSM Pin Function .......................................................D-32
MC68331 Module Address Map ...................................................................D-37
Register Bit and Field Mnemonics ...............................................................D-40
7-3
A-1
A-2
A-2
A-3
A-4
A-4
A-5
A-5
A-6
A-6
A-7
A-8
A-8
A-9
B-1
B-2
C-1
D-1
D-2
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-11
D-12
D-13
D-14
D-15
D-16
D-17
D-18
MOTOROLA
xiv
MC68331
USER’S MANUAL
SECTION 1INTRODUCTION
The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance
data manipulation capabilities with powerful peripheral subsystems. The MCU is built
up from standard modules that interface through a common intermodule bus (IMB).
Standardization facilitates rapid development of devices tailored for specific applica-
tions.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a
general-purpose timer (GPT), and a queued serial module (QSM).
The MCU can either synthesize an internal clock signal from an external reference or
use an external clock input directly. Operation with a 32.768-kHz reference frequency
is standard. Because MCU operation is fully static, register and memory contents are
not affected by a loss of clock.
High-density complementary metal-oxide semiconductor (HCMOS) architecture
makes the basic power consumption of the MCU low. Power consumption can be min-
imized by stopping the system clock. The CPU32 instruction set includes a low-power
stop (LPSTOP) command that efficiently implements this capability.
1
Documentation for the Modular Microcontroller Family follows the modular construc-
tion of the devices in the product line. Each microcontroller has a comprehensive us-
er's manual that provides sufficient information for normal operation of the device. The
user's manual is supplemented by module reference manuals that provide detailed in-
formation about module operation and applications. Refer to Motorola publication Ad-
vanced Microcontroller Unit (AMCU) Literature (BR1116/D) for a complete listing of
documentation.
MC68331
INTRODUCTION
MOTOROLA
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USER’S MANUAL
1
MOTOROLA
1-2
INTRODUCTION
MC68331
USER’S MANUAL
SECTION 2NOMENCLATURE
The following nomenclature is used throughout the manual. Nomenclature used only
in certain sections, such as register bit mnemonics, is defined in those sections.
2.1 Symbols and Operators
+ — Addition
− — Subtraction or negation (two's complement)
— Multiplication
/ — Division
> — Greater
< — Less
= — Equal
2
≥ — Equal or greater
≤ — Equal or less
≠ — Not equal
• — AND
✛ — Inclusive OR (OR)
— Exclusive OR (EOR)
NOT — Complementation
: — Concatenation
— Transferred
— Exchanged
± — Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
MC68331
NOMENCLATURE
MOTOROLA
2-1
USER’S MANUAL
2.2 CPU32 Registers
A6–A0 — Address registers (index registers)
A7 (SSP) — Supervisor Stack Pointer
A7 (USP) — User Stack Pointer
CCR — Condition code register (user portion of SR)
D7–D0 — Data Registers (index registers)
DFC — Alternate function code register
PC — Program counter
SFC — Alternate function code register
SR — Status register
VBR — Vector base register
X — Extend indicator
N — Negative indicator
Z — Zero indicator
V — Two's complement overflow indicator
C — Carry/borrow indicator
2
MOTOROLA
2-2
NOMENCLATURE
MC68331
USER’S MANUAL
2.3 Pin and Signal Mnemonics
ADDR[23:0] — Address Bus
AS — Address Strobe
AVEC — Autovector
BERR — Bus Error
BG — Bus Grant
BGACK — Bus Grant Acknowledge
BKPT — Breakpoint
BR — Bus Request
CLKOUT — System Clock
CS[10:0] — Chip Selects
CSBOOT — Boot ROM Chip Select
DATA[15:0] — Data Bus
DS — Data Strobe
DSACK[1:0] — Data and Size Acknowledge
DSCLK — Development Serial Clock
DSI — Development Serial Input
DSO — Development Serial Output
EXTAL — External Crystal Oscillator Connection
FC[2:0] — Function Codes
FREEZE — Freeze
2
HALT — Halt
IC[4:1] — Input Capture
IFETCH — Instruction Fetch
IPIPE — Instruction Pipeline
IRQ[7:1] — Interrupt Request
MISO — Master In Slave Out
MODCLK — Clock Mode Select
MOSI — Master Out Slave In
OC[5:1] — Output Compare
PAI — Pulse Accumulator Input
PC[6:0] — SIM I/O Port C
PCLK — Pulse Accumulator Clock
PCS[3:0] — Peripheral Chip Selects
PE[7:0] — SIM I/O Port E
PF[7:0] — SIM I/O Port F
PGP[7:0] — GPT I/O Port
PQS[7:0] — QSM I/O Port
PWMA, PWMB — Pulse Width Modulator Output
QUOT — Quotient Out
MC68331
NOMENCLATURE
MOTOROLA
2-3
USER’S MANUAL
R/W — Read/Write
RESET — Reset
RMC — Read-Modify-Write Cycle
RXD — SCI Receive Data
SCK — QSPI Serial Clock
SIZ[1:0] — Size
SS — Slave Select
TSC — Three-State Control
TXD — SCI Transmit Data
XFC — External Filter Capacitor
XTAL — External Crystal Oscillator Connection
2
MOTOROLA
2-4
NOMENCLATURE
MC68331
USER’S MANUAL
2.4 Register Mnemonics
CFORC — GPT Compare Force Register
CREG — Test Control Register C
CR[0:F] — QSM Command RAM
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[0:10] — Chip-Select Base Address Registers [0:10]
CSORBT — Chip-Select Option Register Boot ROM
CSOR[0:10] — Chip-Select Option Register [0:10]
CSPAR[0:1] — Chip-Select Pin Assignment Registers [0:1]
DDRE — Port E Data Direction Register
DDRF — Port F Data Direction Register
DDRGP — Port GP Data Direction Register
DDRQS — Port QS Data Direction Register
DREG — SIM Test Module Distributed Register
GPTMCR — GPT Module Configuration Register
ICR — GPT Interrupt Configuration Register
OC1D — Output Compare 1 Action Data Register
OC1M — Output Compare 1 Action Mask Register
PACNT — Pulse Accumulator Counter
PACTL — Pulse Accumulator Control Register
PEPAR — Port E Pin Assignment Register
PFPAR — Port F Pin Assignment Register
PICR — Periodic Interrupt Control Register
PITR — Periodic Interrupt Timer Register
PORTC — Port C Data Register
2
PORTE — Port E Data Register
PORTF — Port F Data Register
PORTGP — Port GP Data Register
PORTQS — Port QS Data Register
PQSPAR — Port QS Pin Assignment Register
PRESCL — GPT Prescaler Register
PWMA — PWM Control Register A
PWMB — PWM Control Register B
PWMBUFA — PWM Buffer Register A
PWMBUFB — PWM Buffer Register B
PWMC — PWM Control Register C
PWMCNT — PWM Counter
QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
QSMCR — QSM Configuration Register
MC68331
USER’S MANUAL
NOMENCLATURE
MOTOROLA
2-5
QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
SWSR — Software Watchdog Service Register
SYNCR — Clock Synthesizer Control Register
SYPCR — System Protection Control Register
TCNT — Timer Counter Register
TCTL[1:2] — Timer Control Registers [1:2]
TFLG[1:2] — Timer Interrupt Flag Registers [1:2]
TI4/O5 — Timer Input Capture 4/Output Compare 5 Register
TIC[1:3] — Timer Input Capture Registers [1:3]
TMSK[1:2] — Timer Interrupt Mask Register [1:2]
TOC[1:4] — Timer Output Compare Registers [1:4]
TR[0:F] — QSM Transmit Data RAM
2
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
TSTRC — Test Module Repetition Count Register
TSTSC — Test Module Shift Count Register
2.5 Conventions
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Clear refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal chang-
es from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high sig-
nal changes from logic level one to logic level zero.
MOTOROLA
2-6
NOMENCLATURE
MC68331
USER’S MANUAL
A specific mnemonic within a range is referred to by mnemonic and number. A15 is
bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select op-
tion register 0. A range of mnemonics is referred to by mnemonic and the numbers
that define the range. AM[35:30] are bits 35 to 30 of accumulator M; CSOR[0:5] are
the first six option registers.
Parentheses are used to indicate the content of a register or memory location, rather
than the register or memory location itself. (A) is the content of accumulator A. (M : M
+ 1) is the content of the word at address M.
LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-
ences to low and high bytes are spelled out.
LSW means least significant word or words. MSW means most significant word or
words.
ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus.
DATA is the data bus. DATA[15:8] are the eight MSB of the data bus.
2
MC68331
NOMENCLATURE
MOTOROLA
2-7
USER’S MANUAL
2
MOTOROLA
2-8
NOMENCLATURE
MC68331
USER’S MANUAL
SECTION 3OVERVIEW
This section contains information about the entire modular microcontroller. It lists the
features of each module, shows device functional divisions and pin assignments, sum-
marizes signal and pin functions, discusses the intermodule bus, and provides system
memory maps. Timing and electrical specifications for the entire microcontroller and
for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERIS-
TICS. Comprehensive module register descriptions and memory maps are provided
in APPENDIX D REGISTER SUMMARY.
3.1 MCU Features
The following paragraphs highlight capabilities of each of the microcontroller modules.
Each module is discussed separately in a subsequent section of this user's manual.
3.1.1 System Integration Module (SIM)
3
• External Bus Support
• Programmable Chip-Select Outputs
• System Protection Logic
• Watchdog Timer, Clock Monitor, and Bus Monitor
• System Protection Logic
• PLL System Clock for Low Power Operation
• Background Debugging Mode
3.1.2 Central Processing Unit (CPU32)
• Instruction Set Supports Controller Applications
• 32-Bit Architecture
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Table Lookup and Interpolate Instruction
• Improved Exception Handling for Controller Applications
• Trace on Change of Flow
• Hardware Breakpoint Signal, Background Mode
• Fully Static Operation
3.1.3 Queued Serial Module (QSM)
• Serial Communication Interface (SCI), Enhanced Universal Asynchronous Re-
ceiver Transmitter (UART) with Modulus Baud Rate, Parity
• Queued Serial Peripheral Interface (SPI), High Speed Bidirectional Interface, 80-
Byte RAM, Up to 16 Automatic Transfers
• Dual Function I/O Ports
• Continuous Cycling, 8 to 16 Bits per Transfer
MC68331
OVERVIEW
MOTOROLA
3-1
USER’S MANUAL
3.1.4 General-Purpose Timer (GPT)
• Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler
• Three Input Capture Channels
• Four Output Compare Channels
• One Input Capture/Output Compare Channel
• One Pulse Accumulator/Event Counter Input
• Two Pulse-Width Modulation Outputs
• Optional External Clock Input
3.2 System Block Diagram and Pin Assignment Diagrams
Figure 3-1 is a functional diagram of the MCU. Although diagram blocks represent the
relative size of the physical modules, there is not a one-to-one correspondence be-
tween location and size of blocks in the diagram and location and size of integrated-
circuit modules. Figure 3-2 shows the pin assignments of the 132-pin plastic surface-
mount package. Figure 3-3 shows the pin assignments of the 144-pin plastic surface-
mount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN-
FORMATION for package dimensions. All pin functions and signal names are shown
in this drawing. Refer to subsequent paragraphs in this section for pin and signal de-
scriptions.
3
MOTOROLA
3-2
OVERVIEW
MC68331
USER’S MANUAL
CHIP
CSBOOT
SELECTS
BR
BG
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
PWMA
PWMB
PWMA
PWMB
BGACK
CS[10:0]
PCLK
PAI
PCLK
PAI
FC2
FC1
FC0
GPT
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP7/IC4/OC5/OC1
PGP6/OC4/OC1
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
BG/CS1
BR/CS0
PGP2/IC3
PGP1/IC2
PGP2/IC3
PGP1/IC2
ADDR[23:0]
ADDR[18:0]
PGP0/IC1
PGP0/IC1
SIZ1
SIZ0
DS
PE7/SIZ1
PE6/SIZ0
PE5/DS
EBI
IMB
AS
RMC
PE4/AS
PE3/RMC
AVEC
PE2/AVEC
PE1/DSACK1
PE0/DSACK0
DSACK1
DSACK0
3
RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS
PQS2/SCK
TXD
PCS3
PCS2
PCS1
PCS0/SS
SCK
MOSI
MISO
DATA[15:0]
IRQ[7:1]
DATA[15:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
PQS1/MOSI
PQS0/MISO
QSM
CPU32
MODCLK
CLOCK
CLKOUT
XTAL
EXTAL
TSC
TEST
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
QUOT
FREEZE/QUOT
331 BLOCK
Figure 3-1 MCU Block Diagram
MC68331
OVERVIEW
MOTOROLA
3-3
USER’S MANUAL
V
V
18
19
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
DD
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
NC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
DD
V
V
V
SS
DD
DATA4
DATA5
DATA6
DATA7
SS
ADDR9
ADDR10
ADDR11
ADDR12
3
V
SS
V
DATA8
DATA9
DATA10
DATA11
SS
MC68331
ADDR13
ADDR14
ADDR15
ADDR16
V
DD
V
SS
V
V
DD
DATA12
DATA13
DATA14
DATA15
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
90
89
88
87
86
85
84
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
DD
V
DD
331 132-PIN QFP
Figure 3-2 Pin Assignments for 132-Pin Package
MOTOROLA
3-4
OVERVIEW
MC68331
USER’S MANUAL
109
108
1
2
3
4
5
6
7
8
NC
NC
V
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
V
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SS
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
V
DD
SS
PCLK
PWMB
PWMA
NC
HALT
RESET
NC
NC
V
SS
MC68331
V
V
NC
PAI
CLKOUT
DD
V
NC
DD
SS
3
XFC
V
GP7/IC4/OC5/OC1
PGP6/OC4
DD
EXTAL
V
V
V
DD
DD
XTAL
SS
V
SS
NC
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PGP1/IC2
PGP0/IC1
NC
PQS7/TXD
V
NC
V
NC
SS
SS
331 144-PIN QFP
Figure 3-3 Pin Assignments for 144-Pin Package
3.3 Pin Descriptions
The following tables are a summary of the functional characteristics of MCU pins. Ta-
ble 3-1 shows types of output drivers. Table 3-2 shows all inputs and outputs. Digital
inputs and outputs use CMOS logic levels. An entry in the Discrete I/O column indi-
cates that a pin can also be used for general-purpose input, output, or both. The I/O
port designation is given when it applies. Table 3-3 shows characteristics of power
pins. Refer to Figure 3-1 for port organization.
MC68331
OVERVIEW
MOTOROLA
3-5
USER’S MANUAL
Table 3-1 MCU Driver Types
Type
A
I/O
O
Description
Output-only signals that are always driven; no external pull-up required
Type A output with weak P-channel pull-up during reset
Aw
B
O
O
Three-state output that includes circuitry to pull up output before high impedance is
established, to ensure rapid rise time. An external holding resistor is required to maintain
logic level while the pin is in the high-impedance state.
Bo
O
Type B output that can be operated in an open-drain mode
Table 3-2 MCU Pin Characteristics
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
ADDR23/CS10/ECLK
ADDR[22:19]/CS[9:6]
ADDR[18:0]
AS
A
A
Y
Y
N
N
O
O
—
PC[6:3]
—
A
Y
N
—
I/O
I/O
—
—
—
—
—
—
—
—
I/O
I/O
I/O
—
—
—
O
B
Y
N
PE5
PE2
—
AVEC
B
Y
N
BERR
B
Y
N
BG/CS1
B
—
Y
—
N
—
3
BGACK/CS2
BKPT/DSCLK
BR/CS0
B
—
—
B
Y
Y
—
Y
N
—
CLKOUT
A
—
—
Y
—
—
N
—
CSBOOT
DATA[15:0]1
DS
B
—
Aw
B
—
Y
N
PE4
PE1
PE0
—
DSACK1
B
Y
N
DSACK0
B
Y
N
DSI/IFETCH
DSO/IPIPE
EXTAL2
A
Y
Y
A
—
—
Y
—
Special
N
—
—
A
—
FC[2:0]/CS[5:3]
FREEZE/QUOT
IC4/OC5
PC[2:0]
—
A
—
Y
—
Y
—
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I
A
GP4
GP[7:5]
—
IC[3:1]
A
Y
Y
HALT
Bo
B
Y
N
IRQ[7:1]
Y
Y
PF[7:1]
PQS0
PF0
PQS1
GP[3:0]
—
MISO
Bo
B
Y
Y
1
MODCLK
Y
N
MOSI
Bo
A
Y
Y
OC[4:1]
Y
Y
2
PAI
—
—
Bo
Bo
A
Y
Y
2
Y
Y
I
—
PCLK
PCSO/SS
PCS[3:1]
PWMA, PWMB
R/W
Y
Y
I/O
I/O
O
PQS3
PQS[6:4]
—
Y
Y
—
Y
—
N
A
—
—
I/O
—
RESET
Bo
B
Y
Y
—
RMC
Y
N
PE3
MOTOROLA
3-6
OVERVIEW
MC68331
USER’S MANUAL
Table 3-2 MCU Pin Characteristics (Continued)
Pin
Mnemonic
Output
Driver
Input
Synchronized
Input
Hysteresis
Discrete
I/O
Port
Designation
RXD
SCK
—
Bo
B
N
Y
N
Y
—
I/O
—
PQS2
PE[7:6]
—
SIZ[1:0]
TSC
Y
N
Y
I/O
—
Bo
—
—
Y
—
TXD
Y
Y
I/O
PQS7
—
3
XFC
—
—
—
—
Special
Special
3
—
XTAL
1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin.
2. EXTAL, XFC, and XTAL are clock reference connections.
3. PAI and PCLK can be used for discrete input, but are not part of an I/O port.
Table 3-3 MCU Power Connections
Pin Mnemonic
Description
V
Clock Synthesizer Power
DDSYN
V
/V
External Periphery Power (Source and Drain)
Internal Module Power (Source and Drain)
SSE DDE
V
I/V
SS DDI
3
3.4 Signal Descriptions
The following tables define MCU signals. Table 3-4 shows signal origin, type, and ac-
tive state. Table 3-5 describes signal functions. Both tables are sorted alphabetically
by mnemonic. MCU pins often have multiple functions. More than one description can
apply to a pin.
Table 3-4 Signal Characteristics
Signal
Name
MCU
Module
Signal
Type
Active
State
ADDR[23:0]
AS
SIM
SIM
Bus
Output
Input
—
0
AVEC
SIM
0
BERR
SIM
Input
0
BG
SIM
Output
Input
0
BGACK
BKPT
SIM
0
CPU32
SIM
Input
0
BR
Input
0
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
SIM
Output
Output
Output
Bus
—
SIM
0
SIM
0
SIM
—
SIM
Output
Input
0
DSACK[1:0]
DSCLK
DSI
SIM
0
CPU32
CPU32
CPU32
SIM
Input
Serial Clock
(Serial Data)
(Serial Data)
—
Input
DSO
Output
Input
EXTAL
MC68331
OVERVIEW
MOTOROLA
3-7
USER’S MANUAL
Table 3-4 Signal Characteristics (Continued)
Signal
Name
MCU
Module
Signal
Type
Active
State
FC[2:0]
FREEZE
HALT
SIM
SIM
Output
Output
—
1
SIM
Input/Output
Input
0
IC[4:1]
IFETCH
IPIPE
GPT
CPU32
CPU32
SIM
—
Output
—
Output
—
IRQ[7:1]
MISO
Input
0
QSM
SIM
Input/Output
Input
—
MODCLK
MOSI
—
QSM
GPT
GPT
SIM
Input/Output
Output
—
OC[5:1]
PAI
—
Input
—
PC[6:0]
PCS[3:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
PCLK
Output
(Port)
—
QSM
SIM
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
(Port)
(Port)
(Port)
(Port)
—
SIM
GPT
QSM
GPT
GPT
SIM
3
PWMA, PWMB
QUOT
RESET
RMC
Output
—
Output
—
SIM
Input/Output
Output
0
SIM
0
R/W
SIM
Output
1/0
—
RXD
QSM
QSM
SIM
Input
SCK
Input/Output
Output
—
SIZ[1:0]
SS
—
QSM
SIM
Input
0
TSC
Input
—
TXD
QSM
SIM
Output
—
XFC
Input
—
XTAL
SIM
Output
—
Table 3-5 Signal Function
Signal Name
Address Bus
Mnemonic
ADDR[23:0] 24-bit address bus
Function
Address Strobe
Autovector
Bus Error
AS
AVEC
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
BERR
BG
Bus Grant
Indicates that the MCU has relinquished the bus
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Bus Grant Acknowledge
Breakpoint
BGACK
BKPT
Bus Request
BR
Indicates that an external device requires bus mastership
System clock output
System Clockout
Chip Selects
CLKOUT
CS[10:0]
CSBOOT
Select external devices at programmed addresses
Chip select for external boot start-up ROM
Boot Chip Select
Data Bus
DATA[15:0] 16-bit data bus
MOTOROLA
3-8
OVERVIEW
MC68331
USER’S MANUAL
Table 3-5 Signal Function (Continued)
Signal Name
Data Strobe
Mnemonic
Function
DS
During a read cycle, indicates when it is possible for an external
device to place data on the data bus. During a write cycle,
indicates that valid data is on the data bus.
Data and Size Acknowledge
DSACK[1:0] Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, Out, Clock
DSI, DSO,
DSCLK
Serial I/O and clock for background debugging mode
Crystal Oscillator
EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an
external oscillator can be used
Function Codes
Freeze
FC[2:0]
FREEZE
HALT
Identify processor state and current address space
Indicates that the CPU has entered background mode
Suspend external bus activity
Halt
Input Capture
IC[3:1]
When a specified transition is detected on an input capture pin, the
value in an internal GPT counter is latched
Input Capture 4/
IC4/OC5
Can be configured for either an input capture or output compare
Output Compare 5
Instruction Pipeline
Interrupt Request Level
Master In Slave Out
IPIPE, IFETCH Indicate instruction pipeline activity
IRQ[7:1]
MISO
Provides an interrupt priority level to the CPU
Serial input to QSPI in master mode; serial output from QSPI in
slave mode
Clock Mode Select
Master Out Slave In
MODCLK
MOSI
Selects the source and type of system clock
3
Serial output from QSPI in master mode; serial input to QSPI in
slave mode
Output Compare
OC[5:1]
Change state when the value of an internal GPT counter matches
a value stored in a GPT control register
Pulse Accumulator Input
Port C
PAI
Signal input to the pulse accumulator
SIM digital output port signals
External clock dedicated to the GPT
QSPI peripheral chip selects
SIM digital I/O port signals
PC[6:0]
PCLK
Auxiliary Timer Clock Input
Peripheral Chip Select
Port E
PCS[3:0]
PE[7:0]
PF[7:0]
PGP[7:0]
PQS[7:0]
Port F
SIM digital I/O port signals
Port GP
GPT digital I/O port signals
Port QS
QSM digital I/O port signals
Pulse-Width Modulation
Quotient Out
PWMA, PWMB Output for PWM
QUOT
RESET
RMC
R/W
Provides the quotient bit of the polynomial divider
Reset
System reset
Read-Modify-Write Cycle
Read/Write
Indicates an indivisible read-modify-write instruction
Indicates the direction of data transfer on the bus
Serial input to the SCI
SCI Receive Data
QSPI Serial Clock
RXD
SCK
Clock output from QSPI in master mode; clock input to QSPI in
slave mode
Size
SIZ[1:0]
SS
Indicates the number of bytes to be transferred during a bus cycle
Slave Select
Causes serial transmission when QSPI is in slave mode; causes
mode fault in master mode
Three-State Control
SCI Transmit Data
TSC
TXD
XFC
Places all output drivers in a high-impedance state
Serial output from the SCI
External Filter Capacitor
Connection for external phase-locked loop filter capacitor
MC68331
OVERVIEW
MOTOROLA
3-9
USER’S MANUAL
3.5 Intermodule Bus
The intermodule bus (IMB) is a standardized bus developed to facilitate both design
and operation of modular microcontrollers. It contains circuitry to support exception
processing, address space partitioning, multiple interrupt levels, and vectored inter-
rupts. The standardized modules in the MCU communicate with one another and with
external components through the IMB. The IMB in the MCU uses 24 address and 16
data lines.
3.6 System Memory Map
Figure 3-4, Figure 3-5, Figure 3-6, Figure 3-7, and Figure 3-8 are MCU memory
maps. Figure 3-4 shows IMB addresses of internal registers. Figure 3-5 through Fig-
ure 3-8 show system memory maps that use different external decoding schemes.
3.6.1 Internal Register Map
In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represent-
ed by Y determines the base address of MCU module control registers. In M68300 mi-
crocontrollers, Y is equal to M111, where M is the logic state of the module mapping
(MM) bit in the system integration module configuration register (SIMCR).
3
3.6.2 Address Space Maps
Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded
externally so that separate user/supervisor or program/data spaces are not provided.
In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces.
FC[1:0] are not decoded, so that separate program and data spaces are not provided.
In Figure 3-7 and Figure 3-8, FC[2:0] are decoded, resulting in four separate memory
spaces: supervisor/program, supervisor/data, user/program and user/data.
All exception vectors are located in supervisor data space, except the reset vector,
which is located in supervisor program space. Only the initial reset vector is fixed in
the processor's memory map. Once initialization is complete, there are no fixed as-
signments. Since the vector base register (VBR) provides the base address of the vec-
tor table, the vector table can be located anywhere in memory. Refer to SECTION 5
CENTRAL PROCESSING UNIT for more information concerning memory manage-
ment, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM
INTEGRATION MODULE for more information concerning function codes and ad-
dress space types.
MOTOROLA
3-10
OVERVIEW
MC68331
USER’S MANUAL
$YFF000
$YFF900
$YFF93F
GPT
$YFFA00
SIM
$YFFA7F
$YFFA80
RESERVED
$YFFAFF
$YFFC00
QSM
$YFFDFF
$YFFFFF
3
Y = M111, where M is the state of the module mapping (MM) bit in the SIM configuration register.
331 ADDRESS MAP
Figure 3-4 Internal Register Memory Map
MC68331
OVERVIEW
MOTOROLA
3-11
USER’S MANUAL
$000000
VECTOR VECTOR
OFFSET NUMBER
TYPE OF
EXCEPTION
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0
1
2
3
4
5
6
7
8
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
$XX0000
9
10
11
12
13
14
15
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
0040–005C 16–23
006C
0064
0068
006C
0070
0074
0078
007C
24
25
26
27
28
29
30
31
SPURIOUS INTERRUPT
COMBINED
SUPERVISOR
AND USER
SPACE
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
0080–00BC 32–47
00C0–00EB 48–58
00EC–00FC 59–63
0100–03FC 64–255
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX03FC
3
$YFF000
$YFF900
GPT
$7FF000
$YFF93F
$YFFA00
INTERNAL REGISTERS (MM = 0)
SIM
$YFFA7F
$YFFA80
$YFFAFF
RESERVED
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS (MM = 1)
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
331 S/U COMB MAP
Figure 3-5 Overall Memory Map
MOTOROLA
3-12
OVERVIEW
MC68331
USER’S MANUAL
$000000
$000000
VECTOR VECTOR
OFFSET NUMBER
TYPE OF
EXCEPTION
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0
1
2
3
4
5
6
7
8
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
$XX0000
9
10
11
12
13
14
15
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
0040–005C 16–23
006C
0064
0068
006C
0070
0074
0078
007C
24
25
26
27
28
29
30
31
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
SUPERVISOR
SPACE
USER
SPACE
0080–00BC 32–47
00C0–00EB 48–58
00EC–00FC 59–63
0100–03FC 64–255
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX03FC
3
$YFF000
$YFF900
GPT
4
$7FF000
$7FF000
$YFF93F
$YFFA00
INTERNAL REGISTERS
INTERNAL REGISTERS
SIM
$YFFA7F
$YFFA80
$YFFAFF
RESERVED
$YFFC00
QSM
$YFFDFF
4
$FF0000
$FFFFFF
$FF0000
$FFFFFF
INTERNAL REGISTERS
INTERNAL REGISTERS
$YFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
331 S/U SEP MAP
Figure 3-6 Separate Supervisor and User Space Map
MC68331
USER’S MANUAL
OVERVIEW
MOTOROLA
3-13
VECTOR VECTOR
OFFSET NUMBER
EXCEPTION VECTORS LOCATED
IN SUPERVISOR PROGRAM SPACE
$000000
$000000
$XX0000
$XX0004
0000
0004
0
1
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
VECTOR VECTOR
OFFSET NUMBER
EXCEPTION VECTORS LOCATED
IN SUPERVISOR DATA SPACE
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0
1
2
3
4
5
6
7
8
RESET — INITIAL STACK POINTER
RESET — INITIAL PC
BUS ERROR
ADDRESS ERROR
ILLEGAL INSTRUCTION
ZERO DIVISION
CHK, CHK2 INSTRUCTIONS
TRAPcc, TRAPV INSTRUCTIONS
PRIVILEGE VIOLATION
TRACE
$XX0000
9
10
11
12
13
14
15
LINE 1010 EMULATOR
LINE 1111 EMULATOR
HARDWARE BREAKPOINT
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
(UNASSIGNED, RESERVED)
SUPERVISOR
DATA
SUPERVISOR
PROGRAM
SPACE
0040–005C 16–23
SPACE
006C
0064
0068
006C
0070
0074
0078
007C
24
25
26
27
28
29
30
31
SPURIOUS INTERRUPT
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
TAP INSTRUCTION VECTORS (0–15)
(RESERVED, COPROCESSOR)
0080–00BC 32–47
00C0–00EB 48–58
00EC–00FC 59–63
0100–03FC 64–255
3
(UNASSIGNED, RESERVED)
USER-DEFINED VECTORS
$XX03FC
$YFF000
$YFF900
GPT
$7FF000
$YFF93F
$YFFA00
INTERNAL REGISTERS
SIM
$YFFA7F
$YFFA80
$YFFAFF
RESERVED
$YFFC00
QSM
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS
$YFFFFF
$FFFFFF
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
base register and the vector offset.
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration register.
Y = M111, where M is the state of the MM bit.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
4. Some internal registers are not available in user space.
331 SUPER P/D MAP
Figure 3-7 Supervisor Space (Separate Program/Data Space) Map
MOTOROLA
3-14
OVERVIEW
MC68331
USER’S MANUAL
$000000
$000000
USER
PROGRAM
SPACE
USER
DATA
SPACE
$YFF000
$YFF900
3
GPT
$7FF000
$YFF93F
$YFFA00
INTERNAL REGISTERS
SIM
$YFFA7F
$YFFA80
$YFFAFF
RESERVED
QSM
$YFFC00
$YFFDFF
$FF0000
$FFFFFF
INTERNAL REGISTERS
$YFFFFF
$FFFFFF
NOTES:
1. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configuration
register. Y = M111, where M is the state of the MM bit.
2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
3. Some internal registers are not available in user space.
331 USER P/D MAP
Figure 3-8 User Space (Separate Program/Data Space) Map
MC68331
USER’S MANUAL
OVERVIEW
MOTOROLA
3-15
3.7 System Reset
The following information is a concise reference only. System reset is a complex op-
eration. To understand operation during and after reset, refer to SECTION 4 SYSTEM
INTEGRATION MODULE, paragraph 4.6 Reset for a more complete discussion of the
reset function.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 3-6 is a summary of reset mode selection options.
Table 3-6 SIM Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
CSBOOT 16-Bit
Alternate Function
(Pin Pulled Low)
CSBOOT 8-Bit
DATA0
DATA1
CS0
CS1
CS2
BRBG
BGACK
3
DATA2
CS3
CS4
CS5
FC0FC1FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
ADDR19
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK0, DSACK1,
AVEC, DS, AS,
SIZ[1:0]
PORTE
DATA9
DATA11
MODCLK
BKPT
IRQ[7:1], MODCLK
Test Mode Disabled
PORTF
Test Mode Enabled
VCO = System Clock
Background Mode Disabled
EXTAL = System Clock
Background Mode Enabled
MOTOROLA
3-16
OVERVIEW
MC68331
USER’S MANUAL
3.7.2 MCU Module Pin Function During Reset
Generally, pins associated with modules other than the SIM default to port functions,
and input/output ports are set to input state. This is accomplished by disabling pin
functions in the appropriate control registers, and by clearing the appropriate port data
direction registers. Refer to individual module sections in this manual for more infor-
mation. Table 3-7 is a summary of module pin function out of reset.
Table 3-7 Module Pin Functions
Module
Pin Mnemonic
DSI/IFETCH
DSO/IPIPE
Function
DSI/IFETCH
DSO/IPIPE
CPU32
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Output
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
RXD
GPT
PCLK
PWMA, PWMB
PQS7/TXD
QSM
3
PQS[6:4]/PCS[3:1]
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
RXD
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OVERVIEW
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OVERVIEW
MC68331
USER’S MANUAL
SECTION 4 SYSTEM INTEGRATION MODULE
This section is an overview of SIM function. Refer to the SIM Reference Manual (SIM-
RM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D
REGISTER SUMMARY for information concerning the SIM address map and register
structure.
4.1 General
The system integration module (SIM) consists of five functional blocks. Figure 4-1 is
a block diagram of the SIM.
The system configuration and protection block controls configuration parameters and
provides bus and software watchdog monitors. In addition, it provides a periodic inter-
rupt generator to support execution of time-critical control routines.
The system clock generates clock signals used by the SIM, other IMB modules, and
external devices.
4
The external bus interface handles the transfer of information between IMB modules
and external address space. EBI pins can also be configured for use as general-pur-
pose I/O ports E and F.
The chip-select block provides 12 chip-select signals. Each chip-select signal has an
associated base register and option register that contain the programmable character-
istics of that chip select. Chip-select pins can also be configured for use as general-
purpose output port C.
The system test block incorporates hardware necessary for testing the MCU. It is used
to perform factory tests, and its use in normal applications is not supported.
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USER’S MANUAL
SYSTEM CONFIGURATION
AND PROTECTION
CLKOUT
EXTAL
CLOCK SYNTHESIZER
CHIP SELECTS
MODCLK
CHIP SELECTS
EXTERNAL BUS
RESET
EXTERNAL BUS INTERFACE
FACTORY TEST
TSC
FREEZE/QUOT
S(C)IM BLOCK
4
Figure 4-1 System Integration Module Block Diagram
4.2 System Configuration and Protection
The system configuration and protection functional block controls module configura-
tion, preserves reset status, monitors internal activity, and provides periodic interrupt
generation. Figure 4-2 is a block diagram of the submodule.
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USER’S MANUAL
MODULE CONFIGURATION
AND TEST
RESET STATUS
HALT MONITOR
BUS MONITOR
RESET REQUEST
BERR
SPURIOUS INTERRUPT MONITOR
4
CLOCK
SOFTWARE WATCHDOG TIMER
RESET REQUEST
9
2
PRESCALER
IRQ [7:1]
PERIODIC INTERRUPT TIMER
SYS PROTECT BLOCK
Figure 4-2 System Configuration and Protection
4.2.1 Module Mapping
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping bit (MM) in the SIM module configuration reg-
ister (SIMCR) determines where the control register block is located in the system
memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF;
when MM = 1, register addresses range from $FFF000 to $FFFFFF.
4.2.2 Interrupt Arbitration
Each module that can generate interrupt requests has an interrupt arbitration (IARB)
field. Arbitration between interrupt requests of the same priority is performed by serial
contention between IARB field bit values. Contention must take place whenever an in-
terrupt request is acknowledged, even when there is only a single request pending.
For an interrupt to be serviced, the appropriate IARB field must have a non-zero value.
If an interrupt request from a module with an IARB field value of %0000 is recognized,
the CPU32 processes a spurious interrupt exception.
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Because the SIM routes external interrupt requests to the CPU32, the SIM IARB field
value is used for arbitration between internal and external interrupts of the same pri-
ority. The reset value of IARB for the SIM is %1111, and the reset IARB value for all
other modules is %0000, which prevents SIM interrupts from being discarded during
initialization. Refer to 4.7 Interrupts for a discussion of interrupt arbitration.
4.2.3 Show Internal Cycles
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in the SIMCR determines what the external bus interface does during internal transfer
operations. Table 4-1 shows whether data is driven externally, and whether external
bus arbitration can occur. Refer to 4.5.6.2 Show Cycles for more information.
Table 4-1 Show Cycle Enable Bits
SHEN
00
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
01
10
11
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
4
4.2.4 Factory Test Mode
The internal IMB can serve as slave to an external master for direct module testing.
This test mode is reserved for factory test. Slave mode is enabled by holding DATA11
low during reset. The slave enabled (SLVEN) bit is a read-only bit that shows the reset
state of DATA11.
4.2.5 Register Access
The CPU32 can operate at either of two privilege levels. Supervisor level is more priv-
ileged than user level — all instructions and system resources are available at super-
visor level, but access is restricted at user level. Effective use of privilege level can
protect system resources from uncontrolled access. The state of the S bit in the CPU
status register determines access level, and whether the user or supervisor stack
pointer is used for stacking operations. The SUPV bit places SIM global registers in
either supervisor or user data space. When SUPV = 0, registers with controlled access
are accessible from either the user or supervisor privilege level; when SUPV = 1, reg-
isters with controlled access are restricted to supervisor access only.
4.2.6 Reset Status
The reset status register (RSR) latches internal MCU status during reset. Refer to
4.6.9 Reset Status Register for more information.
4.2.7 Bus Monitor
The internal bus monitor checks data and size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the in-
ternal bus error (BERR) signal when the response time is excessively long.
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DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT) field in the sys-
tem protection control register (SYPCR). Table 4-2 shows the periods allowed.
Table 4-2 Bus Monitor Period
BMT
00
Bus Monitor Time-Out Period
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
The monitor does not check DSACK response on the external bus unless the CPU32
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for inter-
nal to external bus cycles. If a system contains external bus masters, an external bus
monitor must be implemented and the internal-to-external bus monitor option must be
disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor time-out period must be at
least twice the number of clocks that a single byte access requires.
4
4.2.8 Halt Monitor
The halt monitor responds to an assertion of the HALT signal on the internal bus. Refer
to 4.5.5.2 Double Bus Faults for more information. Halt monitor reset can be inhibited
by the halt monitor (HME) bit in SYPCR.
4.2.9 Spurious Interrupt Monitor
During interrupt exception processing, the CPU32 normally acknowledges an interrupt
request, recognizes the highest priority source, and then acquires a vector or re-
sponds to a request for autovectoring. The spurious interrupt monitor asserts the in-
ternal bus error signal (BERR) if no interrupt arbitration occurs during interrupt
exception processing. The assertion of BERR causes the CPU32 to load the spurious
interrupt exception vector into the program counter. The spurious interrupt monitor
cannot be disabled. Refer to 4.7 Interrupts for further information. For detailed infor-
mation about interrupt exception processing, refer to SECTION 5 CENTRAL PRO-
CESSING UNIT.
4.2.10 Software Watchdog
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
software service register SWSR on a periodic basis. If servicing does not take place,
the watchdog times out and asserts the reset signal.
Perform a software watchdog service sequence as follows:
1. Write $55 to SWSR.
2. Write $AA to SWSR.
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Both writes must occur before time-out in the order listed, but any number of instruc-
tions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft-
ware watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
Table 4-3 MODCLK Pin and SWP Bit During Reset
MODCLK
SWP
1 (÷ 512)
0 (÷ 1)
0 (External Clock)
1 (Internal Clock)
The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
1
Time-out Period = ------------------------------------------------------------------------------------
EXTAL Frequency ⁄ Divide Ratio
4
or
Divide Ratio
Time-out Period = ------------------------------------------------
EXTAL Frequency
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new time-
out period can take effect.
Table 4-4 Software Watchdog Ratio
SWP
SWT
00
Ratio
9
2
0
0
0
0
1
1
1
1
11
2
01
13
2
10
15
2
11
18
2
00
20
2
01
22
2
10
24
2
11
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
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USER’S MANUAL
PITR
SWP
PTP
FREEZE
PITCLK
8-BIT MODULUS
COUNTER
PIT
INTERRUPT
÷ 4
CLOCK
MUX
PRECLK
CLOCK
DISABLE
9
EXTAL
PRESCALER (2 )
RESET
SWCLK
LPSTOP
SWT1
SWT0
SWE
15 STAGE
DIVIDER CHAIN (2
15
)
9
2
11
2
13
2
15
2
PIT BLOCK
Figure 4-3 Periodic Interrupt Timer and Software Watchdog Timer
4.2.11 Periodic Interrupt Timer
4
The periodic interrupt timer allows the generation of interrupts of specific priority at pre-
determined intervals. This capability is often used to schedule control system tasks
that must be performed within time constraints. The timer consists of a prescaler, a
modulus counter, and registers that determine interrupt timing, priority and vector as-
signment. Refer to SECTION 5 CENTRAL PROCESSING UNIT for further information
about interrupt exception processing.
The periodic interrupt modulus counter is clocked by a signal derived from the buffered
crystal oscillator (EXTAL) input pin unless an external frequency source is used. The
value of the periodic timer prescaler (PTP) bit in the periodic interrupt timer register
(PITR) determines system clock prescaling for the watchdog timer. One of two op-
tions, either no prescaling, or prescaling by a factor of 512, can be selected. The value
of PTP is affected by the state of the MODCLK pin during reset, as shown in Table 4-
5. System software can change PTP value.
Table 4-5 MODCLK Pin and PTP Bit at Reset
MODCLK
PTP
0 (External Clock)
1 (Internal Clock)
1 (÷ 512)
0 (÷ 1)
Either clock signal (EXTAL or EXTAL ÷ 512) is divided by four before driving the mod-
ulus counter (PITCLK). The modulus counter is initialized by writing a value to the pe-
riodic timer modulus timer modulus (PITM) field in the PITR. A zero value turns off the
periodic timer. When the modulus counter value reaches zero, an interrupt is generat-
ed. The modulus counter is then reloaded with the value in PITM and counting repeats.
If a new value is written to PITR, it is loaded into the modulus counter when the current
count is completed.
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USER’S MANUAL
Use the following expression to calculate timer period.
(PIT Modulus)(Prescaler Value)(4)
PIT Period = ----------------------------------------------------------------------------------------------
EXTAL Frequency
Interrupt priority and vectoring are determined by the values of the periodic interrupt
request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt
control register (PICR).
Content of PIRQL is compared to the CPU32 interrupt priority mask to determine
whether the interrupt is recognized. Table 4-6 shows priority of PIRQL values. Be-
cause of SIM hardware prioritization, a PIT interrupt is serviced before an external in-
terrupt request of the same priority. The periodic timer continues to run when the
interrupt is disabled.
Table 4-6 Periodic Interrupt Priority
PIRQL
000
001
010
011
100
101
110
111
Priority Level
Periodic Interrupt Disabled
Interrupt Priority Level 1
Interrupt Priority Level 2
Interrupt Priority Level 3
Interrupt Priority Level 4
Interrupt Priority Level 5
Interrupt Priority Level 6
Interrupt Priority Level 7
4
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number used to calculate the address
of the appropriate exception vector in the exception vector table. Reset value of the
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
4.2.12 Low-Power STOP Operation
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSIM bit in the SIMCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop.
During low-power stop, the clock input to the software watchdog timer is disabled and
the timer stops. The software watchdog begins to run again on the first rising clock
edge after low-power stop ends. The watchdog is not reset by low-power stop. A ser-
vice sequence must be performed to reset the timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external
interrupt request, can bring the MCU out of the low-power stop condition if it has a
higher priority than the interrupt mask value stored in the clock control logic when low-
power stop is initiated. LPSTOP can be terminated by a reset.
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4.2.13 Freeze Operation
The FREEZE signal halts MCU operations during debugging. FREEZE is asserted in-
ternally by the CPU32 if a breakpoint occurs while background mode is enabled. When
FREEZE is asserted, only the bus monitor, software watchdog, and periodic interrupt
timer are affected. The halt monitor and spurious interrupt monitor continue to operate
normally. Setting the freeze bus monitor (FRZBM) bit in the SIMCR disables the bus
monitor when FREEZE is asserted, and setting the freeze software watchdog
(FRZSW) bit disables the software watchdog and the periodic interrupt timer when
FREEZE is asserted. When FRZSW is set, FREEZE assertion must be at least two
times the PIT clock source period to ensure an accurate number of PIT counts.
4.3 System Clock
The system clock in the SIM provides timing signals for the IMB modules and for an
external peripheral bus. Because the MCU is a fully static design, register and memory
contents are not affected when the clock rate changes. System hardware and software
support changes in clock rate during operation.
The system clock signal can be generated in one of three ways. An internal phase-
locked loop can synthesize the clock from either an internal reference or an external
reference, or the clock signal can be input from an external frequency source. Keep
these clock sources in mind while reading the rest of this section. Figure 4-4 is a block
diagram of the system clock. Refer to APPENDIX A ELECTRICAL CHARACTERIS-
TICS for clock specifications.
4
V
EXTAL
XTAL
XFC
CLKOUT
DDSYN
CRYSTAL
OSCILLATOR
PHASE
COMPARATOR
LOW-PASS
FILTER
VCO
W
Y
FEEDBACK DIVIDER
X
SYSTEM CLOCK CONTROL
SYSTEM
CLOCK
32 PLL BLOCK
Figure 4-4 System Clock Block Diagram
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SYSTEM INTEGRATION MODULE
MOTOROLA
4-9
4.3.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source.
When MODCLK is held high during reset, the clock synthesizer generates a clock sig-
nal from either an internal or an external reference frequency — the clock synthesizer
control register (SYNCR) determines operating frequency and mode of operation.
When MODCLK is held low during reset, the clock synthesizer is disabled and an ex-
ternal system clock signal must be applied — SYNCR control bits have no effect.
To generate a reference frequency using the internal oscillator a reference crystal
must be connected between the EXTAL and XTAL pins. Figure 4-5 shows a recom-
mended circuit.
C1
22 pF*
R1
330k
XTAL
R2
10M
EXTAL
C2
22 pF*
4
V
SSI
Resistance and capacitance based on a test circuit constructed with a DAISHINKU DMX-38 32.768-kHz crystal.
Specific components must be based on crystal type. Contact crystal vendor for exact circuit.
*
32 OSCILLATOR
Figure 4-5 System Clock Oscillator Circuit
If an external reference signal or an external system clock signal is applied via the EX-
TAL pin, the XTAL pin must be left floating. External reference signal frequency must
be less than or equal to maximum specified reference frequency. External system
clock signal frequency must be less than or equal to maximum specified system clock
frequency.
When an external system clock signal is applied (PLL disabled, MODCLK = 0 during
reset), the duty cycle of the input is critical, especially at operating frequencies close
to maximum. The relationship between clock signal duty cycle and clock signal period
is expressed:
Minumum External Clock Period
Minimum External Clock High ⁄ Low Time
= ----------------------------------------------------------------------------------------------------------------------------------------------------------------------
50% – Percentage Variation of External Clock Input Duty Cycle
4.3.2 Clock Synthesizer Operation
V
is used to power the clock circuits when either an internal or an external ref-
DDSYN
erence frequency is applied. A separate power source increases MCU noise immunity
and can be used to run the clock when the MCU is powered down. A quiet power sup-
ply must be used as the V
source. Adequate external bypass capacitors should
DDSYN
be placed as close as possible to the V
pin to assure stable operating frequen-
DDSYN
MOTOROLA
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SYSTEM INTEGRATION MODULE
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USER’S MANUAL
cy. When an external system clock signal is applied and the PLL is disabled, V
DDSYN
should be connected to the V
supply. Refer to the SIM Reference Manual (SIMRM/
DD
AD) for more information regarding system clock power supply conditioning.
A voltage controlled oscillator (VCO) generates the system clock signal. To maintain
a 50% clock duty cycle, VCO frequency is either two or four times system clock fre-
quency, depending on the state of the X bit in SYNCR. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a
phase comparator. The other phase comparator input is a reference signal, either from
the crystal oscillator or from an external source. The comparator generates a control
signal proportional to the difference in phase between the two inputs. The signal is low-
pass filtered and used to correct VCO output frequency.
Filter geometry can vary, depending upon the external environment and required clock
stability. Figure 4-6 shows two recommended filters. XFC pin leakage must be as
specified in APPENDIX A ELECTRICAL CHARACTERISTICS to maintain optimum
stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled. The XFC pin must be left float-
ing in this case.
4
C3
0.1µF
C1
0.1µF
C3
0.1µF
C1
0.1µF
R1
18kΩ
1
XFC
1, 2
XFC
V
DDSYN
C2
0.01µF
C4
C4
0.01µF
0.01µF
V
DDSYN
V
SSI
V
SSI
NORMAL OPERATING
ENVIRONMENT
HIGH-STABILITY OPERATING
ENVIRONMENT
1. Maintain low-leakage on the XFC node. See Appendix A electrical characteristics for more information.
2. Recommended loop filter for reduced sensitivity to low-frequency noise.
16/32 XFC CONN
Figure 4-6 System Clock Filter Networks
The synthesizer locks when VCO frequency is equal to EXTAL frequency. Lock time
is affected by the filter time constant and by the amount of difference between the two
comparator inputs. Whenever comparator input changes, the synthesizer must relock.
Lock status is shown by the SLOCK bit in SYNCR. During power-up, the MCU does
not come out of reset state until the synthesizer locks. Crystal type, characteristic fre-
quency, and layout of external oscillator circuitry affect lock time.
When the clock synthesizer is used, control register SYNCR determines operating fre-
quency and various modes of operation. The SYNCR W bit controls a three-bit pres-
caler in the feedback divider. Setting W increases VCO speed by a factor of four. The
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USER’S MANUAL
SYNCR Y field determines the count modulus for a modulo 64 down counter, causing
it to divide by a value of Y + 1. When W or Y values change, VCO frequency changes,
and there is a VCO relock delay. The SYNCR X bit controls a divide-by-two circuit that
is not in the synthesizer feedback loop. When X = 0 (reset state), the divider is en-
abled, and system clock frequency is one-fourth VCO frequency; setting X disables
the divider, doubling clock speed without changing VCO speed. There is no relock de-
lay when clock speed is changed by the X bit.
Clock frequency is determined by SYNCR bit settings as follows:
FSYSTEM = FREFERENCE[4(Y + 1)(22W + X)]
The reset state of SYNCR ($3F00) produces a modulus-64 count.
For the device to perform correctly, system clock and VCO frequencies selected by
the W, X, and Y bits must be within the limits specified for the MCU. Do not use a com-
bination of bit values that selects either an operating frequency or a VCO frequency
greater than the maximum specified values in APPENDIX A ELECTRICAL CHARAC-
TERISTICS.
Table 4-7 shows clock control multipliers for all possible combinations of SYNCR bits.
Table 4-8 shows clock frequencies available with a 32.768-kHz reference and a max-
imum specified clock frequency of 20.97 MHz.
4
Table 4-7 Clock Control Multipliers
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus
Y
Prescalers
[W:X] = 00
[W:X] = 01
8
[W:X] = 10
16
[W:X] = 11
32
000000
000001
000010
011111
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
4
8
16
32
64
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
24
48
96
32
64
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
40
80
48
96
56
112
128
144
160
176
192
208
224
240
256
272
288
304
320
336
64
72
80
88
96
104
112
120
128
136
144
152
160
168
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Table 4-7 Clock Control Multipliers (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then multiply reference frequency by value
in appropriate prescaler cell.
Modulus
Y
Prescalers
[W:X] = 00
88
[W:X] = 01
176
184
192
200
208
216
224
232
240
248
256
264
272
280
288
296
304
312
320
328
336
344
352
360
368
376
384
392
400
408
416
424
432
440
448
456
464
472
480
488
496
504
512
[W:X] = 10
352
368
384
400
416
432
448
464
480
496
512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
1024
[W:X] = 11
704
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
92
736
96
768
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
184
188
192
196
200
204
208
212
216
220
224
228
232
236
240
244
248
252
256
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
2048
4
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SYSTEM INTEGRATION MODULE
MOTOROLA
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Table 4-8 System Frequencies from 32.768-kHz Reference
To obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell.
Shaded cells contain values that exceed specified maximum system frequency.
Modulus
Y
Prescaler
[W:X] = 00
131
[W:X] = 01
262
[W:X] = 10
524
[W:X] = 11
1049
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
262
524
1049
2097
393
786
1573
3146
524
1049
1311
1573
1835
2097
2359
2621
2884
3146
3408
3670
3932
4194
4456
4719
4981
5243
5505
5767
6029
6291
6554
6816
7078
7340
7602
7864
8126
8389
8651
8913
9175
9437
9699
9961
10224
10486
10748
11010
11272
11534
11796
2097
4194
655
2621
5243
786
3146
6291
918
3670
7340
1049
1180
1311
1442
1573
1704
1835
1966
2097
2228
2359
2490
2621
2753
2884
3015
3146
3277
3408
3539
3670
3801
3932
4063
4194
4325
4456
4588
4719
4850
4981
5112
5243
5374
5505
5636
5767
5898
4194
8389
4719
9437
5243
10486
11534
12583
13631
14680
15729
16777
17826
18874
19923
20972
22020
23069
24117
25166
26214
27263
28312
29360
30409
31457
32506
33554
34603
35652
36700
37749
38797
39846
40894
41943
42992
44040
45089
46137
47186
5767
6291
6816
7340
7864
4
8389
8913
9437
9961
10486
11010
11534
12059
12583
13107
13631
14156
14680
15204
15729
16253
16777
17302
17826
18350
18874
19399
19923
20447
20972
21496
22020
22544
23069
23593
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USER’S MANUAL
Table 4-8 System Frequencies from 32.768-kHz Reference (Continued)
To obtain clock frequency in kilohertz, find counter modulus in the left column, then look in appropriate prescaler cell.
Shaded cells contain values that exceed specified maximum system frequency.
Modulus
Y
Prescaler
[W:X] = 00
6029
6160
6291
6423
6554
6685
6816
6947
7078
7209
7340
7471
7602
7733
7864
7995
8126
8258
8389
[W:X] = 01
12059
12321
12583
12845
13107
13369
13631
13894
14156
14418
14680
14942
15204
15466
15729
15991
16253
16515
16777
[W:X] = 10
24117
24642
25166
25690
26214
26739
27263
27787
28312
28836
29360
2988
[W:X] = 11
48234
49283
50332
51380
52428
53477
54526
55575
56623
57672
58720
59769
60817
61866
62915
63963
65011
66060
67109
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
30409
30933
31457
31982
32506
33030
33554
4
4.3.3 External Bus Clock
The state of the external clock division bit (EDIV) in SYNCR determines clock rate for
the external bus clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock
for MC6800 devices and peripherals. ECLK frequency can be set to system clock fre-
quency divided by eight or system clock frequency divided by sixteen. The clock is en-
abled by the CS10 field in chip select pin assignment register 1 (CSPAR1). ECLK
operation during low-power stop is described in the following paragraph. Refer to 4.8
Chip Selects for more information about the external bus clock.
4.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To mini-
mize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction, which causes the SIM to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SIM brings the MCU out of
low-power operation when either an interrupt of higher priority than the stored mask or
a reset occurs. Refer to 4.5.4.2 LPSTOP Broadcast Cycle and SECTION 5 CEN-
TRAL PROCESSING UNIT for more information.
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USER’S MANUAL
During a low-power stop, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock sig-
nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to generate
the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external
clock (STEXT) bits in SYNCR determine clock operation during low-power stop. Table
4-9 is a summary of the effects of STSIM and STEXT. MODCLK value is the logic level
on the MODCLK pin during the last reset before LPSTOP execution. Any clock in the
off state is held low. If the synthesizer VCO is turned off during LPSTOP, there is a
PLL relock delay after the VCO is turned back on.
Table 4-9 Clock Control
Mode
LPSTOP
No
Pins
SYNCR Bits
STSIM STEXT
Clock Status
CLKOUT
MODCLK
EXTAL
SIMCLK
ECLK
0
External
Clock
X
X
External
Clock
External
Clock
External
Clock
Yes
Yes
Yes
Yes
No
0
0
0
0
1
1
1
1
1
External
Clock
0
0
1
1
X
0
0
1
1
0
1
0
1
X
0
1
0
1
External
Clock
Off
Off
4
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
External
Clock
Off
Off
External
Clock
External
Clock
External
Clock
External
Clock
Crystal or
Reference
VCO
VCO
VCO
Yes
Yes
Yes
Yes
Crystal or
Reference
Crystal or
Reference
Off
Off
Crystal or
Reference
Crystal or
Reference
Crystal/
Reference
Off
Crystal or
Reference
VCO
Off
Off
Crystal or
Reference
VCO
VCO
VCO
4.3.5 Loss of Reference Signal
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when
clock logic detects a reference failure.
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced
into an operating condition referred to as limp mode. Limp mode frequency varies
from device to device, but maximum limp frequency does not exceed one half max-
imum system clock when X = 0, or maximum system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a refer-
ence signal. It is set when a reference failure is detected.
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4.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 4-7 shows a basic system with external memory and pe-
ripherals.
ASYNC BUS
PERIPHERAL
1
FC
SIZ
CLKOUT
AS
SIZ
CLK
AS
DSACK
DS
DSACK
DS
CS
CS3
CS5
IACK
IRQ
ADDR[23:0]
DATA[15:0]
IRQ
ADDR[15:0]
DATA[15:0]
2
MEMORY
2
MCU
4
ADDR[23:0]
DATA[15:8]
CS
CSBOOT
R/W
R/W
MEMORY
2
ADDR[23:0]
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
32 EXAMPLE SYS BLOCK
Figure 4-7 MCU Basic System
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic
sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word
transfers. Ports are accessed through the use of asynchronous cycles controlled by
the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and
DSACK0). Multiple bus cycles may be required for a transfer to or from an 8-bit port.
The maximum number of bits transferred during an access is referred to as port width.
Widths of eight and sixteen bits can be accessed by asynchronous bus cycles con-
trolled by the data size (SIZ[1:0]) and the data and size acknowledge (DSACK[1:0])
signals. Multiple bus cycles may be required for a dynamically-sized transfer.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
can be synchronized with EBI transfers. Refer to 4.8 Chip Selects for more informa-
tion.
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USER’S MANUAL
4.4.1 Bus Signals
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an ad-
dress and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space it is to take
place in, the size of the transfer, and the type of cycle. External devices decode these
signals and respond to transfer data and terminate the bus cycle. The EBI operates in
an asynchronous mode for any port width.
4.4.1.1 Address Bus
Bus signals ADDR[23:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.
4.4.1.2 Address Strobe
Address strobe AS is a timing signal that indicates the validity of an address on the
address bus and of many control signals. It is asserted one-half clock after the begin-
ning of a bus cycle.
4
4.4.1.3 Data Bus
Signals DATA[15:0 form a bidirectional, nonmultiplexed parallel bus that transfers data
to or from the MCU. A read or write operation can transfer eight or sixteen bits of data
in one bus cycle. During a read cycle, the data is latched by the MCU on the last falling
edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are
driven, regardless of the port width or operand size. The MCU places the data on the
data bus one-half clock cycle after AS is asserted in a write cycle.
4.4.1.4 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid. The MCU asserts DS one full clock cycle after the assertion of AS during a write
cycle.
4.4.1.5 Read/Write Signal
The read/write signal (R/W determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid
while AS is asserted. R/W only transitions when a write cycle is preceded by a read
cycle or vice versa. The signal may remain low for two consecutive write cycles.
4.4.1.6 Size Signals
Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while the address strobe (AS) is asserted. Table 4-
10 shows SIZ0 and SIZ1 encoding.
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SYSTEM INTEGRATION MODULE
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USER’S MANUAL
Table 4-10 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
Byte
0
1
1
0
1
0
1
0
Word
3 Byte
Long Word
4.4.1.7 Function Codes
The CPU generates function code output signals FC[2:0] to indicate the type of activity
occurring on the data or address bus. These signals can be considered address ex-
tensions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle.
Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 4-11 shows address space encoding.
4
Table 4-11 Address Space Encoding
FC2
0
FC1
0
FC0
0
Address Space
Reserved
0
0
1
User Data Space
User Program Space
Reserved
0
1
0
0
1
1
1
0
0
Reserved
1
0
1
Supervisor Data Space
Supervisor Program Space
CPU Space
1
1
0
1
1
1
The supervisor bit in the status register determines whether the CPU is operating in
supervisor or user mode. Addressing mode and the instruction being executed deter-
mine whether a memory access is to program or data space.
4.4.1.8 Data and Size Acknowledge Signals
During normal bus transfers, external devices assert the data and size acknowledge
signals (DSACK[1:0]) to indicate port width to the MCU. During a read cycle, these sig-
nals tell the MCU to terminate the bus cycle and to latch data. During a write cycle, the
signals indicate that an external device has successfully stored data and that the cycle
can terminate. DSACK[1:0] can also be supplied internally by chip-select logic. Refer
to 4.8 Chip Selects for more information.
4.4.1.9 Bus Error Signal
The bus error signal BERR is asserted when a bus cycle is not properly terminated by
DSACK or AVEC assertion. BERR can also be asserted at the same time as DSACK,
provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Exception
Control Cycles for more information.
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USER’S MANUAL
The internal bus monitor can generate the BERR signal for internal and internal-to-ex-
ternal transfers. An external bus master must provide its own BERR generation and
drive the BERR pin, because the internal BERR monitor has no information about
transfers initiated by an external bus master. Refer to 4.5.6 External Bus Arbitration
for more information.
4.4.1.10 Halt Signal
The halt signal (HALT) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR) a retry of a bus cy-
cle in error. The HALT signal affects external bus cycles only, so a program not requir-
ing the use of external bus may continue executing, unaffected by the HALT signal.
When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is
placed in the high-impedance state, and bus control signals are driven inactive; the ad-
dress, function code, size, and read/write signals remain in the same state. If HALT is
still asserted once bus mastership is returned to the MCU, the address, function code,
size, and read/write signals are again driven to their previous states. The MCU does
not service interrupt requests while it is halted. Refer to 4.5.5 Bus Exception Control
Cycles for further information.
4
4.4.1.11 Autovector Signal
The autovector signal AVEC can be used to terminate external interrupt acknowledge
cycles. Assertion of AVEC causes the CPU32 to generate vector numbers to locate an
interrupt handler routine. If it is continuously asserted, autovectors are generated for
all external interrupt requests. AVEC is ignored during all other bus cycles. Refer to
4.7 Interrupts for more information. AVEC for external interrupt requests can also be
supplied internally by chip-select logic. Refer to 4.8 Chip Selects for more information.
The autovector function is disabled when there is an external bus master. Refer to
4.5.6 External Bus Arbitration for more information.
4.4.2 Dynamic Bus Sizing
The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During an operand transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK inputs, as
shown in Table 4-12. Chip-select logic can generate data and size acknowledge sig-
nals for an external device. Refer to 4.8 Chip Selects for further information.
Table 4-12 Effect of DSACK Signals
DSACK1
DSACK0
Result
1
1
0
0
1
0
1
0
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob-
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USER’S MANUAL
tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK signals to indicate the port width. For
instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of wheth-
er the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins.
Operand bytes are designated as shown in Figure 4-8. OP[0:3] represent the order of
access. For instance, OP0 is the most significant byte of a long-word operand, and is
accessed first, while OP3, the least significant byte, is accessed last. The two bytes of
a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-
length operand is OP0.
4
Operand
Byte Order
31
24 23
16 15
8 7
0
Long Word
Three Byte
Word
OP0
OP1
OP0
OP2
OP1
OP0
OP3
OP2
OP1
OP0
Byte
Figure 4-8 Operand Byte Order
4.4.3 Operand Alignment
The EBI data multiplexer establishes the necessary connections for different combi-
nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit
bus and routes them to their required positions. Positioning of bytes is determined by
the size and address outputs. SIZ1 and SIZ0 indicate the remaining number of bytes
to be transferred during the current bus cycle. The number of bytes transferred is equal
to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be ac-
cessed, and ADDR0 indicates the byte offset from the base.
4.4.4 Misaligned Operands
CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned
when it overlaps a word boundary. This is determined by the value of ADDR0. When
ADDR0 = 0 (an even address), the address is on a word and byte boundary. When
ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand
is aligned at any address; a word or long-word operand is misaligned at an odd ad-
dress.
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USER’S MANUAL
The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant oper-
and word is transferred on a following bus cycle.
4.4.5 Operand Transfer Cases
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.
Table 4-13 Operand Transfer Cases
Read Cycles
Write Cycles
Num
Transfer Case
SIZ ADDR0 DSACK DATA DATA DATA DATA
Next
Cycle
[1:0]
01
01
01
10
10
10
10
00
10
00
10
11
11
[1:0]
10
01
01
10
10
11
01
10
10
01
01
10
10
[15:8]
OP0
OP0
—
[7:0]
—
[15:8]
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
OP0
(OP0)
OP0
OP0
[7:0]
(OP0)
(OP0)
OP0
1
2
3
4
5
6
7
8
9
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
X
0
1
0
1
0
1
0
1
0
1
0
1
—
—
—
1
—
OP0
—
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
OP0
OP0
OP0
—
(OP1)
(OP0)
OP1
1
—
1
4
OP1
OP0
—
—
2
1
Word to 16-Bit Port (Misaligned)
OP0
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
OP0
OP0
OP0
—
(OP1)
(OP0)
OP1
13
12
6
1
—
10 Long Word to 16-Bit Port (Aligned)
OP1
OP0
—
1
11 Long Word to 16-Bit Port (Misaligned)
OP0
2
2
12 3 Byte to 8-Bit Port (Aligned)
OP0
OP0
(OP1)
(OP0)
5
2
13 3 Byte to 8-Bit Port (Misaligned)
—
4
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
4.5 Bus Operation
Internal microcontroller modules are typically accessed in two system clock cycles,
with no wait states. Regular external bus cycles use handshaking between the MCU
and external peripherals to manage transfer size and data. These accesses take three
system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Chip-select logic can
also be used to insert wait states before internal generation of handshaking signals.
Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIM-
RM/AD) for more information about each type of bus cycle.
The MCU is responsible for de-skewing signals it issues at both the start and the end
of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data
signals from peripheral devices.
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USER’S MANUAL
4.5.1 Synchronization to CLKOUT
External devices connected to the MCU bus can operate at a clock frequency different
from the frequencies of the MCU as long as the external devices satisfy the interface
signal timing constraints. Although bus cycles are classified as asynchronous, they are
interpreted relative to the MCU system clock output (CLKOUT).
Descriptions are made in terms of individual system clock states, labeled {S0, S1,
S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and
does not correspond to any implemented machine state. A clock cycle consists of two
successive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for
more information.
Bus cycles terminated by DSACK assertion normally require a minimum of three CLK-
OUT cycles. To support systems that use CLKOUT to generate DSACK and other in-
puts, asynchronous input setup time and asynchronous input hold times are specified.
When these specifications are met, the MCU is guaranteed to recognize the appropri-
ate signal on a specific edge of the CLKOUT signal.
For a read cycle, when assertion of DSACK is recognized on a particular falling edge
of the clock, valid data is latched into the MCU on the next falling clock edge, provided
that the data meets the data setup time. In this case, the parameter for asynchronous
operation can be ignored.
4
When a system asserts DSACK for the required window around the falling edge of S2
and obeys the bus protocol by maintaining DSACK and BERR or HALT until and
throughout the clock edge that negates AS, no wait states are inserted. The bus cycle
runs at the maximum speed of three clocks per cycle.
To ensure proper operation in a system synchronized to CLKOUT when either BERR,
or BERR and HALT is asserted after DSACK, BERR (or BERR and HALT) assertion
must satisfy the appropriate data-in setup and hold times before the falling edge of the
clock cycle after DSACK is recognized.
4.5.2 Regular Bus Cycles
The following paragraphs contain a discussion of cycles that use external bus control
logic. Refer to 4.5.3 Fast Termination Cycles for information about fast cycles.
To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ
signals and ADDR0 are externally decoded to select the active portion of the data bus
(refer to 4.4.2 Dynamic Bus Sizing). When AS, DS, and R/W are valid, a peripheral
device either places data on the bus (read cycle) or latches data from the bus (write
cycle), then asserts a DSACK[1:0] combination that indicates port size.
The DSACK[1:0] signals can be asserted before the data from a peripheral device is
valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period
between DSACK assertion and DS assertion is specified.
There is no specified maximum for the period between the assertion of AS and
DSACK. Although the MCU can transfer data in a minimum of three clock cycles when
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the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period incre-
ments until either DSACK signal goes low.
NOTE
The SIM bus monitor asserts BERR when response time exceeds a
predetermined limit. Bus monitor period is determined by the BMT
field in SYPCR. The bus monitor cannot be disabled; maximum mon-
itor period is 64 system clock cycles.
If no peripheral responds to an access, or if an access is invalid, external logic should
assert the BERR or HALT signals to abort the bus cycle (when BERR and HALT are
asserted simultaneously, the CPU32 acts as though only BERR is asserted). If bus ter-
mination signals are not asserted within a specified period, the bus monitor terminates
the cycle.
4.5.2.1 Read Cycle
During a read cycle, the MCU transfers data from an external memory or peripheral
device. If the instruction specifies a long-word or word operation, the MCU attempts to
read two bytes at once. For a byte operation, the MCU reads one byte. The portion of
the data bus from which each byte is read depends on operand size, peripheral ad-
dress, and peripheral port size. Figure 4-9 is a flowchart of a word read cycle. Refer
to 4.4.2 Dynamic Bus Sizing, 4.4.4 Misaligned Operands, and the SIM Reference
Manual (SIMRM/AD) for more information.
4
MCU
PERIPHERAL
ADDRESS DEVICE (S0)
1) SET R/W TO READ
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
ASSERT AS AND DS (S1)
DECODE DSACK (S3)
LATCH DATA (S4)
PRESENT DATA (S2)
1) DECODE ADDR, R/W, SIZ[1:0], DS
2) PLACE DATA ON DATA[15:0] OR
DATA[15:8] IF 8-BIT DATA
3) DRIVE DSACK SIGNALS
NEGATE AS AND DS (S5)
START NEXT CYCLE (S0)
TERMINATE CYCLE (S5)
1) REMOVE DATA FROM DATA BUS
2) NEGATE DSACK
RD CYC FLOW
Figure 4-9 Word Read Cycle Flowchart
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4.5.2.2 Write Cycle
During a write cycle, the MCU transfers data to an external memory or peripheral de-
vice. If the instruction specifies a long-word or word operation, the MCU attempts to
write two bytes at once. For a byte operation, the MCU writes one byte. The portion of
the data bus upon which each byte is written depends on operand size, peripheral ad-
dress, and peripheral port size.
Refer to 4.4.2 Dynamic Bus Sizing and 4.4.4 Misaligned Operands for more infor-
mation. Figure 4-10 is a flowchart of a write-cycle operation for a word transfer. Refer
to the SIM Reference Manual (SIMRM/AD) for more information.
MCU
PERIPHERAL
ADDRESS DEVICE (S0)
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
4
ASSERT AS (S1)
PLACE DATA ON DATA[15:0] (S2)
ASSERT DS AND WAIT FOR DSACK (S3)
ACCEPT DATA (S2 + S3)
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
OPTIONAL STATE (S4)
NO CHANGE
TERMINATE OUTPUT TRANSFER (S5)
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
TERMINATE CYCLE
1) NEGATE DSACK
START NEXT CYCLE
WR CYC FLOW
Figure 4-10 Write Cycle Flowchart
4.5.3 Fast Termination Cycles
When an external device has a fast access time, the chip-select circuit fast-termination
option can provide a two-cycle external bus transfer. Because the chip-select circuits
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are driven from the system clock, the bus cycle termination is inherently synchronized
with the system clock.
If multiple chip selects are to be used to select the same device that can support fast
termination, and match conditions can occur simultaneously, program the DSACK
field in each associated chip-select option register for fast termination. Alternately, pro-
gram one DSACK field for fast termination and the remaining DSACK fields for exter-
nal termination.
Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals.
When AS, DS, and R/W are valid, a peripheral device either places data on the bus
(read cycle) or latches data from the bus (write cycle). At the appropriate time, chip-
select logic asserts data and size acknowledge signals.
The DSACK option fields in the chip-select option registers determine whether inter-
nally generated DSACK or externally generated DSACK are used. For fast termination
cycles, the F-term encoding (%1110) must be used. Refer to 4.8.1 Chip-Select Reg-
isters for information about fast-termination setup.
4
To use fast-termination, an external device must be fast enough to have data ready,
within the specified setup time, by the falling edge of S4. Refer to APPENDIX A ELEC-
TRICAL CHARACTERISTICS for tabular information about fast termination timing.
When fast termination is in use, DS is asserted during read cycles but not during write
cycles. The STRB field in the chip-select option register used must be programmed
with the address strobe encoding to assert the chip select signal for a fast-termination
write.
4.5.4 CPU Space Cycles
Function code signals FC[2:0] designate which of eight external address spaces is ac-
cessed during a bus cycle. Address space 7 is designated CPU space. CPU space is
used for control information not normally associated with read or write bus cycles.
Function codes are valid only while AS is asserted. Refer to 4.4.1.7 Function Codes
for more information on codes and encoding.
During a CPU space access, ADDR[19:16] are encoded to reflect the type of access
being made. Figure 4-11 shows the three encodings used by 68300 family microcon-
trollers. These encodings represent breakpoint acknowledge (Type $0) cycles low
power stop broadcast (Type $3) cycles, and interrupt acknowledge (Type $F) cycles.
Refer to 4.7 Interrupts for information about interrupt acknowledge bus cycles.
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CPU SPACE CYCLES
ADDRESS BUS
FUNCTION
CODE
2
0
23
19
16
4
2 1 0
BREAKPOINT
ACKNOWLEDGE
1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0
2
0
23
19
16
0
LOW POWER
STOP BROADCAST
1 1 1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
2
0
23
19
16
0
INTERRUPT
ACKNOWLEDGE
1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
CPU SPACE
TYPE FIELD
CPU SPACE CYC TIM
Figure 4-11 CPU Space Address Encoding
4.5.4.1 Breakpoint Acknowledge Cycle
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with the background debugging
mode. The following paragraphs discuss breakpoint processing when background de-
bugging mode is not enabled. See SECTION 5 CENTRAL PROCESSING UNIT for
more information on exception processing and the background debugging mode.
4
In M68300 microcontrollers, both hardware and software can initiate breakpoints.
4.5.4.1.1 Software Breakpoints
The CPU32 BKPT instruction allows the user to insert breakpoints through software.
The CPU responds to this instruction by initiating a breakpoint-acknowledge read cy-
cle in CPU space. It places the breakpoint acknowledge (%0000) code on AD-
DR[19:16], the breakpoint number (bits [2:0] of the BKPT opcode) in ADDR[4:2], and
%0 (indicating a software breakpoint) on ADDR1.
The external breakpoint circuitry decodes the function code and address lines and re-
sponds by either asserting BERR or placing an instruction word on the data bus and
asserting DSACK.
If the bus cycle is terminated by DSACK, the CPU32 reads the instruction on the data
bus and inserts the instruction into the pipeline. (For 8-bit ports, this instruction fetch
may require two read cycles.)
If the bus cycle is terminated by BERR, the CPU32 then performs illegal-instruction
exception processing: it acquires the number of the illegal-instruction exception vector,
computes the vector address from this number, loads the content of the vector address
into the PC, and jumps to the exception handler routine at that address.
4.5.4.1.2 Hardware Breakpoints
Assertion of the BKPT input initiates a hardware breakpoint. The CPU responds by ini-
tiating a breakpoint-acknowledge read cycle in CPU space. It places $00001E on the
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address bus. (The breakpoint acknowledge code of %0000 is placed on ADDR[19:16],
the breakpoint number value of %111 is placed on ADDR[4:2], and ADDR1 is set to 1,
indicating a hardware breakpoint.)
The external breakpoint circuitry decodes the function code and address lines, places
an instruction word on the data bus, and asserts BERR. The CPU then performs hard-
ware breakpoint exception processing: it acquires the number of the hardware break-
point exception vector, computes the vector address from this number, loads the
content of the vector address into the PC, and jumps to the exception handler routine
at that address. If the external device asserts DSACK rather than BERR, the CPU ig-
nores the breakpoint and continues processing.
When BKPT assertion is synchronized with an instruction prefetch, processing of the
breakpoint exception occurs at the end of that instruction. The prefetched instruction
is “tagged” with the breakpoint when it enters the instruction pipeline, and the break-
point exception occurs after the instruction executes. If the pipeline is flushed before
the tagged instruction is executed, no breakpoint occurs. When BKPT assertion is syn-
chronized with an operand fetch, exception processing occurs at the end of the instruc-
tion during which BKPT is latched.
4
Refer to the CPU32 Reference Manual (CPU32RM/AD) and the SIM Reference Man-
ual (SIMRM/AD) for additional information.
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BREAKPOINT OPERATION FLOW
CPU32
PERIPHERAL
ACKNOWLEDGE BREAKPOINT
IF BREAKPOINT INSTRUCTION EXECUTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS
IF BKPT PIN ASSERTED:
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
IF BKPT INSTRUCTION EXECUTED:
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
OR:
7) ASSERT AS AND DS
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
IF BKPT ASSERTED:
1) ASSERT DSACK
IF BREAKPOINT INSTRUCTION EXECUTED AND
DSACK IS ASSERTED:
OR:
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
4
IF BKPT PIN ASSERTED AND
DSACK IS ASSERTED:
1) NEGATE AS AND DS
2) GO TO (A)
IF BERR ASSERTED:
1) NEGATE AS AND DS
2) GO TO (B)
(B)
(A)
IF BKPT INSTRUCTION EXECUTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
1) NEGATE DSACK OR BERR
IF BKPT PIN ASSERTED:
1) CONTINUE PROCESSING
IF BKPT INSTRUCTION EXECUTED:
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
IF BKPT PIN ASSERTED:
1) INITIATE HARDWARE BREAKPOINT PROCESSING
1110A
Figure 4-12 Breakpoint Operation Flowchart
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4.5.4.2 LPSTOP Broadcast Cycle
the STOP bits in each module configuration register or the SIM can turn off system
clocks after execution of the LPSTOP instruction. When the CPU executes LPSTOP,
the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of low-power
mode when either an interrupt of higher priority than the stored mask or a reset occurs.
Refer to 4.3.4 Low-Power Operation and SECTION 5 CENTRAL PROCESSING
UNIT for more information.
During an LPSTOP broadcast cycle, the CPU performs a CPU space write to address
$3FFFE. This write puts a copy of the interrupt mask value in the clock control logic.
The mask is encoded on the data bus as shown in Figure 4-13. The LPSTOP CPU
space cycle is shown externally (if the bus is available) as an indication to external de-
vices that the MCU is going into low-power stop mode. The SIM provides an internally
generated DSACK response to this cycle. The timing of this bus cycle is the same as
for a fast write cycle.
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
0
IP MASK
4
Figure 4-13 LPSTOP Interrupt Mask Level
4.5.5 Bus Exception Control Cycles
An external device or a chip-select circuit must assert at least one of the DSACK[1:0]
signals or the AVEC signal to terminate a bus cycle normally. Bus error processing oc-
curs when bus cycles are not terminated in the expected manner. The internal bus
monitor can be used to generate BERR internally, causing a bus error exception to be
taken. Bus cycles can also be terminated by assertion of the external BERR or HALT
signal, or by assertion of the two signals simultaneously.
Acceptable bus cycle termination sequences are summarized as follows. The case
numbers refer to Table 4-14, which indicates the results of each type of bus cycle ter-
mination.
Normal Termination
DSACK is asserted; BERR and HALT remain negated (case 1).
Halt Termination
HALT is asserted at the same time or before DSACK, and BERR remains negated
(case 2).
Bus Error Termination
BERR is asserted in lieu of, at the same time as, or before DSACK (case 3), or after
DSACK (case 4), and HALT remains negated; BERR is negated at the same time
or after DSACK.
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Retry Termination
HALT and BERR are asserted in lieu of, at the same time as, or before DSACK
(case 5) or after DSACK (case 6); BERR is negated at the same time or after
DSACK; HALT may be negated at the same time or after BERR.
Table 4-14 shows various combinations of control signal sequences and the resulting
bus cycle terminations.
Table 4-14 DSACK, BERR, and HALT Assertion Results
Case
Number
Control
Signal
Asserted on
Rising Edge
of State
Result
N
N + 2
1
2
3
4
5
6
DSACK
BERR
HALT
A
NA
NA
S
NA
X
Normal termination.
DSACK-
BERR
HALT
A
NA
A/S
S
NA
S
Halt termination: normal cycle terminate and halt.
Continue when HALT is negated.
DSACK-
BERR
HALT
NA/A
A
NA
X
S
X
Bus error termination: terminate and take bus error
exception, possibly deferred.
4
DSACK-
BERR
HALT
A
A
NA
X
S
NA
Bus error termination: terminate and take bus error
exception, possibly deferred.
DSACK-
BERR
HALT
NA/A
A
A/S
X
S
S
Retry termination: terminate and retry when HALT is
negated.
DSACK-
BERR
HALT
A
NA
NA
X
A
A
Retry termination: terminate and retry when HALT is
negated.
NOTES:
N
A
= The number of current even bus state (S2, S4, etc.).
= Signal is asserted in this bus state.
NA = Signal is not asserted in this state.
X
S
= Don't care.
= Signal was asserted in previous state and remains asserted in this state.
To properly control termination of a bus cycle for a retry or a bus error condition,
DSACK, BERR, and HALT must be asserted and negated with the rising edge of the
MCU clock. This ensures that when two signals are asserted simultaneously, the re-
quired setup time and hold time for both of them are met for the same falling edge of
the MCU clock. (Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing
requirements.) External circuitry that provides these signals must be designed with
these constraints in mind, or else the internal bus monitor must be used.
DSACK, BERR, and HALT may be negated after AS is negated.
WARNING
If DSACK or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.
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4.5.5.1 Bus Errors
The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU detects assertion of the IMB BERR signal (by the internal bus
monitor or an external source) while the HALT signal remains negated.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several fac-
tors:
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
BERR is asserted.
• Whether BERR is asserted during a program space access or a data space ac-
cess.
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
4
CAUTION
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an in-
struction prefetch, the IMB precharge state (bus pulled high, or $FF)
is latched into the CPU32 instruction register, with indeterminate re-
sults.
4.5.5.2 Double Bus Faults
Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more informa-
tion about exceptions. However, a special case of bus error, called double bus fault,
can abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in two ways:
1. When bus error exception processing begins and a second BERR is detected
before the first instruction of the first exception handler is executed.
2. When one or more bus errors occur before the first instruction after a RESET
exception is executed.
3. A bus error occurs while the CPU32 is loading information from a bus error
stack frame during a return from exception (RTE) instruction.
Multiple bus errors within a single instruction that can generate multiple bus cycles
cause a single bus error exception after the instruction has been executed.
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Immediately after assertion of a second BERR, the MCU halts and drives the HALT
line low. Only a reset can restart a halted MCU. However, bus arbitration can still occur
(refer to 4.5.6 External Bus Arbitration). A bus error or address error that occurs after
exception processing has been completed (during the execution of the exception han-
dler routine, or later) does not cause a double bus fault. The MCU continues to retry
the same bus cycle as long as the external hardware requests it.
4.5.5.3 Retry Operation
BERR and HALT during a bus cycle, the MCU enters the retry sequence. A delayed
retry can also occur. The MCU terminates the bus cycle, places the AS and DS signals
in their inactive state, and does not begin another bus cycle until the BERR and HALT
signals are negated by external logic. After a synchronization delay, the MCU retries
the previous cycle using the same address, function codes, data (for a write), and con-
trol signals. The BERR signal should be negated before S2 of the read cycle to ensure
correct operation of the retried cycle.
If BR, BERR, and HALT are all asserted on the same cycle, the EBI will enter the rerun
sequence but first relinquishes the bus to an external master. Once the external mas-
ter returns the bus and negates BERR and HALT, the EBI runs the previous bus cycle.
This feature allows an external device to correct the problem that caused the bus error
and then try the bus cycle again.
4
The MCU retries any read or write cycle of an indivisible read-modify-write operation
separately; RMC remains asserted during the entire retry sequence. The MCU will not
relinquish the bus while RMC is asserted. Any device that requires the MCU to give up
the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and
BR only (HALT must remain negated). The bus error handler software should examine
the read-modify-write bit in the special status word and take the appropriate action to
resolve this type of fault when it occurs.
4.5.5.4 Halt Operation
When HALT is asserted while BERR is not asserted, the MCU halts external bus ac-
tivity after negation of DSACK. The MCU may complete the current word transfer in
progress. For a long-word to byte transfer, this could be after S2 or S4. For a word to
byte transfer, activity ceases after S2.
Negating and reasserting HALT according to timing requirements provides single-step
(bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only,
so that a program that does not use external bus can continue executing. During dy-
namically-sized 8-bit transfers, external bus activity may not stop at the next cycle
boundary. Occurrence of a bus error while HALT is asserted causes the CPU32 to ini-
tiate a retry sequence.
When the MCU completes a bus cycle while the HALT signal is asserted, the data bus
goes to high-impedance state and the AS and DS signals are driven to their inactive
states. Address, function code, size, and read/write signals remain in the same state.
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The halt operation has no effect on bus arbitration (refer to 4.5.6 External Bus Arbi-
tration). However, when external bus arbitration occurs while the MCU is halted, ad-
dress and control signals go to high-impedance state. If HALT is still asserted when
the MCU regains control of the bus, address, function code, size, and read/write sig-
nals revert to the previous driven states. The MCU cannot service interrupt requests
while halted.
4.5.6 External Bus Arbitration
MCU bus design provides for a single bus master at any one time. Either the MCU or
an external device can be master. Bus arbitration protocols determine when an exter-
nal device can become bus master. Bus arbitration requests are recognized during
normal processing, HALT assertion, and when the CPU has halted due to a double
bus fault.
The bus controller in the MCU manages bus arbitration signals so that the MCU has
the lowest priority. External devices that need to obtain the bus must assert bus arbi-
tration signals in the sequences described in the following paragraphs.
Systems that include several devices that can become bus master require external cir-
cuitry to assign priorities to the devices, so that when two or more external devices at-
tempt to become bus master at the same time, the one having the highest priority
becomes bus master first. The protocol sequence is:
4
1. An external device asserts bus request signal (BR);
2. The MCU asserts the bus grant signal (BG) to indicate that the bus is available;
3. An external device asserts the bus grant acknowledge (BGACK) signal to indi-
cate that it has assumed bus mastership.
BR can be asserted during a bus cycle or between cycles. BG is asserted in response
to BR. To guarantee operand coherency, BG is only asserted at the end of operand
transfer. Additionally, BG is not asserted until the end of an indivisible read-modify-
write operation (when RMC is negated).
If more than one external device can be bus master, required external arbitration must
begin when a requesting device receives BG. An external device must assert BGACK
when it assumes mastership, and must maintain BGACK assertion as long as it is bus
master.
Two conditions must be met for an external device to assume bus mastership. The de-
vice must receive BG through the arbitration process, and BGACK must be inactive,
indicating that no other bus master is active. This technique allows the processing of
bus requests during data transfer cycles.
BG is negated a few clock cycles after BGACK transition. However, if bus requests are
still pending after BG is negated, the MCU asserts BG again within a few clock cycles.
This additional BG assertion allows external arbitration circuitry to select the next bus
master before the current master has released the bus.
Refer to Figure 4-14, which shows bus arbitration for a single device. The flowchart
shows BR negated at the same time BGACK is asserted.
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MCU
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
GRANT BUS ARBITRATION
1) ASSERT BUS GRANT (BG)
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3) NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
4
RELEASE BUS MASTERSHIP
1) NEGATE BGACK
RE-ARBITRATE OR RESUME PROCESSOR
OPERATION
BUS ARB FLOW
Figure 4-14 Bus Arbitration Flowchart for Single Request
State changes occur on the next rising edge of CLKOUT after the internal signal is val-
id. The BG signal transitions on the falling edge of the clock after a state is reached
during which G changes. The bus control signals (controlled by T) are driven by the
MCU immediately following a state change, when bus mastership is returned to the
MCU. State 0, in which G and T are both negated, is the state of the bus arbiter while
the MCU is bus master. Request R and acknowledge A keep the arbiter in state 0 as
long as they are both negated.
4.5.6.1 Slave (Factory Test) Mode Arbitration
This mode is used for factory production testing of internal modules. It is not supported
as a user operating mode. Slave mode is enabled by holding DATA11 low during re-
set. In slave mode, when BG is asserted, the MCU is slaved to an external master that
has full access to all internal registers.
4.5.6.2 Show Cycles
The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS is not asserted exter-
nally during show cycles.
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Show cycles are controlled by the SHEN field in the SIMCR (refer to 4.2.3 Show In-
ternal Cycles). This field is cleared by reset. When show cycles are disabled, the ad-
dress bus, function codes, size, and read/write signals reflect internal bus activity, but
AS and DS are not asserted externally and external data bus pins are in high-imped-
ance state during internal accesses.
When show cycles are enabled, DS is asserted externally during internal cycles, and
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN encoding halts internal
bus activity while there is an external master.
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus con-
ditions, and is indeterminate. During a byte write to an external address, the data mul-
tiplexer in the SIM causes the value of the byte that is written to be driven out on both
bytes of the data bus.
4.6 Reset
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when RE-
SET is asserted, reset does not occur until the clock starts. Resets are clocked to allow
completion of write cycles in progress at the time RESET is asserted.
4
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The system
integration module determines whether a reset is valid, asserts control signals, per-
forms basic system configuration and boot ROM selection based on hardware mode-
select inputs, then passes control to the CPU32.
4.6.1 Reset Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
vector base register (VBR). The VBR contains the base address of a 1024-byte excep-
tion vector table, which consists of 256 exception vectors. The CPU32 uses vector
numbers to calculate displacement into the table. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information concerning exceptions.
Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset oc-
curs at the end of a bus cycle, and not at an instruction boundary. Handling resets in
this way prevents write cycles in progress at the time the reset signal is asserted from
being corrupted. However, any processing in progress is aborted by the reset excep-
tion, and cannot be restarted. Only essential reset tasks are performed during excep-
tion processing. Other initialization tasks must be accomplished by the exception
handler routine. 4.6.8 Reset Processing Summary contains details of exception pro-
cessing.
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4.6.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals.
1. EXTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU has executed
a RESET instruction.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure; thus the reset
control logic responds by asserting reset to the system immediately. (A system reset,
however, caused by the CPU32 RESET instruction, is asynchronous but does not in-
dicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The inter-
nal bus monitor is automatically enabled for synchronous resets. When a bus cycle
does not terminate normally, the bus monitor terminates it.
4
Refer to Table 4-15 for a summary of reset sources.
Table 4-15 Reset Source Summary
Type
Source
External
EBI
Timing
Synch
Cause
Reset Lines Asserted by Controller
External
Power Up
External Signal
MSTRST
MSTRST
CLKRST
CLKRST
EXTRST
EXTRST
Asynch
V
DD
Software Watchdog Monitor
Asynch
Asynch
Time Out
MSTRST
MSTRST
CLKRST
CLKRST
EXTRST
EXTRST
HALT
Monitor
Internal HALT Assertion
(e.g. Double Bus Fault)
Loss of Clock
Test
Clock
Test
Synch
Synch
Asynch
Loss of Reference
Test Mode
MSTRST
MSTRST
—
CLKRST
EXTRST
EXTRST
EXTRST
—
—
System
CPU32
RESET Instruction
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 4-15.
4.6.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 4-16 is a summary of reset mode selection options.
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Table 4-16 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
DATA1
CSBOOT 16-Bit
CSBOOT 8-Bit
CS0
CS1
CS2
BR
BG
BGACK
DATA2
CS3
CS4
CS5
FC0
FC1
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
ADDR19
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK[1:0],
AVEC, DS, AS,
SIZE
PORTE
DATA9
IRQ[7:1]
MODCLK
PORTF
DATA11
MODCLK
BKPT
Test Mode Disabled
VCO = System Clock
Test Mode Enabled
EXTAL = System Clock
Background Mode Enabled
4
Background Mode Disabled
4.6.3.1 Data Bus Mode Selection
All data lines have weak internal pull-up drivers. When pins are held high by the inter-
nal drivers, the MCU uses a default operating configuration. However, specific lines
can be held low externally to achieve an alternate configuration.
NOTE
External bus loading can overcome the weak internal pull-up drivers
on data bus lines, and hold pins low during reset.
Use an active device to hold data bus lines low. Data bus configuration logic must re-
lease the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is re-
leased. If external mode selection logic causes a conflict of this type, an isolation re-
sistor on the driven lines may be required. Figure 4-15 shows a recommended method
for conditioning the mode select signals.
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DATA15
•
•
•
•
•
•
•
•
•
•
•
•
MODE SELECT
LINES
DATA1
DATA0
V
V
DD DD
*
*
*
RESET
DS
R/W
*Optional, to prevent conflict on RESET negation.
DATA BUS MODE DECODE
Figure 4-15 Data Bus Mode Select Conditioning
4
Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC-
TERISTICS. Do not confuse pin function with pin electrical state. Refer to 4.6.5 Pin
State During Reset for more information.
DATA0 determines the function of the boot ROM chip-select signal (CSBOOT). Unlike
other chip-select signals, CSBOOT is active at the release of reset. During reset ex-
ception processing, the MCU fetches initialization vectors beginning at address
$000000 in supervisor program space. An external memory device containing vectors
located at these addresses can be enabled by CSBOOT after a reset. The logic level
of DATA0 during reset selects boot ROM port size for dynamic bus allocation. When
DATA0 is held low, port size is eight bits; when DATA0 is held high, either by the weak
internal pull-up driver or by an external pull-up, port size is 16 bits. Refer to 4.8.4 Chip-
Select Reset Operation for more information.
DATA1 and DATA2 determine the functions of CS[2:0] and CS[5:3], respectively. DA-
TA[7:3] determine the functions of an associated chip select and all lower-numbered
chip-selects down through CS6. For example, if DATA5 is pulled low during reset,
CS[8:6] are assigned alternate function as ADDR[21:19], and CS[10:9] remain chip-
selects. Refer to 4.8.4 Chip-Select Reset Operation for more information.
DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If
DATA8 is held low during reset, these pins are assigned to I/O port E.
DATA9 determines the function of interrupt request pins IRQ[7:0] and the clock mode
select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned
to I/O port F.
DATA11 determines whether the SIM operates in test mode out of reset. This capabil-
ity is used for factory testing of the MCU.
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4.6.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency. When MODCLK is held low during reset, the clock syn-
thesizer is disabled, and an external system clock signal must be applied. Refer to 4.3
System Clock for more information.
NOTE
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
4.6.3.3 Breakpoint Mode Selection
The MCU uses internal and external breakpoint (BKPT) signals. During reset excep-
tion processing, at the release of the RESET signal, the CPU32 samples these signals
to determine how to handle breakpoints.
If either BKPT signal is at logic level zero when sampled, an internal BDM flag is set,
and the CPU32 enters background debugging mode whenever either BKPT input is
subsequently asserted.
4
If both BKPT inputs are at logic level one when sampled, breakpoint exception pro-
cessing begins whenever either BKPT signal is subsequently asserted.
Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information on back-
ground debugging mode and exceptions. Refer to 4.5.4 CPU Space Cycles for infor-
mation concerning breakpoint acknowledge bus cycles.
4.6.4 MCU Module Pin Function During Reset
Usually, module pins default to port functions, and input/output ports are set to input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 4-17 is a summary of mod-
ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
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Table 4-17 Module Pin Functions
Module
Pin Mnemonic
DSI/IFETCH
DSO/IPIPE
Function
DSI/IFETCH
DSO/IPIPE
CPU32
BKPT/DSCLK
PGP7/IC4/OC5
PGP[6:3]/OC[4:1]
PGP[2:0]/IC[3:1]
PAI
BKPT/DSCLK
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Output
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
Discrete Input
RXD
GPT
PCLK
PWMA, PWMB
PQS7/TXD
QSM
PQS[6:4]/PCS[3:1]
PQS3/PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
RXD
4
4.6.5 Pin State During Reset
It is important to keep the distinction between pin function and pin electrical state clear.
Although control register values and mode select inputs determine pin function, a pin
driver can be active, inactive or in high-impedance state while reset occurs. During
power-up reset, pin state is subject to the constraints discussed in 4.6.7 Power-On
Reset.
NOTE
Pins that are not used should either be configured as outputs, or (if
configured as inputs) pulled to the appropriate inactive state. This de-
creases additional I
ply level.
caused by digital inputs floating near mid-sup-
DD
4.6.5.1 Reset States of SIM Pins
Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance
state or are driven to their inactive states. After RESET is released, mode selection
occurs, and reset exception processing begins. Pins configured as inputs during reset
become active high-impedance loads after RESET is released. Inputs must be driven
to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins con-
figured as outputs begin to function after RESET is released. Table 4-18 is a summary
of SIM pin states during reset.
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Table 4-18 SIM Pin Reset States
State While
RESET
Asserted
1
Pin State After RESET Released
Mnemonic
Pin
Function
CS10
Pin State
Pin
Function
ADDR23
Pin State
CS10/ADDR23
CS[9:6]/ADDR[22:19]/PC[6:3]
ADDR[18:0]
AS/PE5
1
1
Unknown
1
CS[9:6]
ADDR[18:0]
AS
ADDR[22:19] Unknown
High-Z Output
High-Z Output
Disabled
Disabled
1
Unknown
Output
Input
Input
1
ADDR[18:0]
PE5
Unknown
Input
AVEC/PE2
BERR
AVEC
PE2
Input
BERR
CSM
BERR
BG
Input
CSM/BG
1
CSE/BGACK
CS0/BR
1
CSE
1
BGACK
BR
Input
1
CS0
1
Input
CLKOUT
Output
1
CLKOUT
CSBOOT
DATA[15:0]
DS
Output
0
CLKOUT
CSBOOT
DATA[15:0]
PE4
Output
0
CSBOOT
DATA[15:0]
DS/PE4
Mode Select
Disabled
Disabled
Disabled
1
Input
Output
Input
Input
1
Input
Input
DSACK0/PE0
DSACK1/PE1
CS5/FC2/PC2
FC1/PC1
DSACK0
DSACK1
CS5
PE0
Input
PE1
Input
4
FC2
Unknown
Unknown
Unknown
Input
1
FC1
1
FC1
CS3/FC0/PC0
HALT
1
CS3
1
FC0
Disabled
Disabled
Mode Select
Disabled
Asserted
Disabled
Disabled
Mode Select
HALT
Input
Input
Input
Output
Input
Output
Unknown
Input
HALT
PF[7:1]
PF0
IRQ[7:1]/PF[7:1]
MODCLK/PF0
R/W
IRQ[7:1]
MODCLK
R/W
Input
Input
R/W
Output
Input
RESET
RESET
RMC
RESET
PE3
RMC
Input
SIZ[1:0]/PE[7:6]
TSC
SIZ[1:0]
TSC
PE[7:6]
TSC
Input
Input
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
As a rule, module pins that are assigned to general-purpose I/O ports go to active high-
impedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
4.6.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven, to guarantee this length of reset to the entire system.
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If an internal source asserts a reset signal, the reset control logic asserts RESET for
a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles,
the control logic continues to assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the reset input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the reset
input is at logic level zero, the reset control logic drives the pin low for another 512 cy-
cles. At the end of this period, the pin again goes to high-impedance state for ten cy-
cles, then it is tested again. The process repeats until RESET is released.
4.6.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset in-
volves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to clock synthesizer pow-
er input pin V
for the MCU to operate. The following discussion assumes that
DDSYN
V
is applied before and during reset, which minimizes crystal start-up time.
DDSYN
When V
is applied at power-on, start-up time is affected by specific crystal pa-
DDSYN
rameters and by oscillator circuit design. V
ing reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and
timing specifications.
ramp-up time also affects pin state dur-
DD
4
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The circuit releases MSTRST as V
ramps up to
DD
the minimum specified value, and SIM pins are initialized as shown in Table 4-19. As
reaches specified minimum value, the clock synthesizer VCO begins operation
V
DD
and clock frequency ramps up to specified limp mode frequency. The external RESET
line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles
elapse line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT
cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
ramp time and VCO frequency ramp time determine how long the four cy-
DD
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 4-16 is a timing diagram of power-up reset. It shows the relationships between
RESET, V , and bus signals.
DD
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CLKOUT
VCO
LOCK
V
DD
10 CLOCKS
512 CLOCKS
RESET
BUS
CYCLES
ADDRESS AND
CONTROL SIGNALS
THREE-STATED
BUS STATE
UNKNOWN
1
2
3
4
NOTES:
1. Internal start-up time.
2. SSP fetched.
3. PC fetched.
32 POR TIM
4. First instruction fetched.
Figure 4-16 Power-On Reset
4
4.6.8 Reset Processing Summary
To prevent write cycles in progress from being corrupted, a reset is recognized at the
end of a bus cycle, and not at an instruction boundary. Any processing in progress at
the time a reset occurs is aborted. After SIM reset control logic has synchronized an
internal or external reset request, it asserts the MSTRST signal.
The following events take place when MSTRST is asserted.
A. Instruction execution is aborted.
B. The status register is initialized.
1. The T0 and T1 bits are cleared to disable tracing.
2. The S bit is set to establish supervisor privilege level.
3. The interrupt priority mask is set to $7, disabling all interrupts below priority
7.
C. The vector base register is initialized to $000000.
The following events take place when MSTRST is negated after assertion.
A. The CPU32 samples the BKPT input.
B. The CPU32 fetches the reset vector:
1. The first long word of the vector is loaded into the interrupt stack pointer.
2. The second long word of the vector is loaded into the program counter.
Vectors can be fetched from internal RAM or from external ROM enabled by
the CSBOOT signal.
C. The CPU32 fetches and begins decoding the first instruction to be executed.
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4.6.9 Reset Status Register
The reset status register (RSR) contains a bit for each reset source in the MCU. When
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of
reset occur at the same time, more than one bit in RSR may be set. The reset status
register is updated by the reset control logic when the RESET signal is released. Refer
to APPENDIX D REGISTER SUMMARY.
4.7 Interrupts
Interrupt recognition and servicing involve complex interaction between the system in-
tegration module, the central processing unit, and a device or module requesting in-
terrupt service. This discussion provides an overview of the entire interrupt process.
Chip-select logic can also be used to respond to interrupt requests. Refer to 4.8 Chip
Selects for more information.
4.7.1 Interrupt Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing. Each exception has an assigned vector in
an exception vector table that points to an associated handler routine. The CPU uses
vector numbers to calculate displacement into the table. During exception processing,
the CPU fetches the appropriate vector and executes the exception handler routine to
which the vector points.
4
Out of reset, the exception vector table is located beginning at address $000000. This
value can be changed by programming the vector base register (VBR) with a new val-
ue, and multiple vector tables can be used. Refer to SECTION 5 CENTRAL PRO-
CESSING UNIT for more information concerning exceptions.
4.7.2 Interrupt Priority and Recognition
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less
than seven can be masked by the interrupt priority (IP) field in status register.
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally
on the IMB, and are corresponding pins for external interrupt service requests. The
CPU treats all interrupt requests as though they come from internal modules — exter-
nal interrupt requests are treated as interrupt service requests from the SIM. Each of
the interrupt request signals corresponds to an interrupt priority level. IRQ1 has the
lowest priority and IRQ7 the highest.
Interrupt recognition is determined by interrupt priority level and interrupt priority mask
value, interrupt recognition is determined by interrupt priority level and interrupt priority
mask value. The interrupt priority mask consists of three bits in the CPU32 status reg-
ister. Binary values %000 to %111 provide eight priority masks. Masks prevent an in-
terrupt request of a priority less than or equal to the mask value from being recognized
and processed. IRQ7, however, is always recognized, even if the mask value is %111.
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted
until an interrupt acknowledge cycle corresponding to that level is detected.
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IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected
unless a falling edge transition is detected on the IRQ7 line. This prevents redundant
servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is
asserted as well as each time the priority mask changes from %111 to a lower number
while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. In-
terrupt request input circuitry has hysteresis: to be valid, a request signal must be as-
serted for at least two consecutive clock periods. Valid requests do not cause
immediate exception processing, but are left pending. Pending requests are pro-
cessed at instruction boundaries or when exception processing of higher-priority ex-
ceptions is complete.
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt
source of higher priority makes a service request while a lower priority request is pend-
ing, the higher priority request is serviced. If an interrupt request with a priority equal
to or lower than the current IP mask value is made, the CPU32 does not recognize the
occurrence of the request. If simultaneous interrupt requests of different priorities are
made, and both have a priority greater than the mask value, the CPU32 recognizes
the higher-level request.
4
4.7.3 Interrupt Acknowledge and Arbitration
When the CPU32 detects one or more interrupt requests of a priority higher than the
interrupt priority mask value, it places the interrupt request level on the address bus
and initiates a CPU space read cycle. The request level serves two purposes: it is de-
coded by modules or external devices that have requested interrupt service, to deter-
mine whether the current interrupt acknowledge cycle pertains to them, and it is
latched into the interrupt priority mask field in the CPU32 status register, to preclude
further interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the in-
terrupt priority mask value placed on the address bus during the interrupt acknowledge
cycle and respond if the priority of the service request corresponds to the mask value.
However, before modules or external devices respond, interrupt arbitration takes
place.
Arbitration is performed by means of serial contention between values stored in indi-
vidual module interrupt arbitration (IARB) fields. Each module that can make an inter-
rupt service request, including the SIM, has an IARB field in its configuration register.
IARB fields can be assigned values from %0000 to %1111. In order to implement an
arbitration scheme, each module that can initiate an interrupt service request must be
assigned a unique, non-zero IARB field value during system initialization. Arbitration
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an
interrupt service request from a source that has an IARB field value of %0000, a spu-
rious interrupt exception is processed.
WARNING
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
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CPU32 interprets multiple vector numbers at the same time, with un-
predictable consequences.
Because the EBI manages external interrupt requests, the SIM IARB value is used for
arbitration between internal and external interrupt requests. The reset value of IARB
for the SIM is %1111, and the reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same prior-
ity, it always takes place, even when a single source is requesting service. This is im-
portant for two reasons: the EBI does not transfer the interrupt acknowledge read cycle
to the external bus unless the SIM wins contention, and failure to contend causes the
interrupt acknowledge bus cycle to be terminated early, by a bus error.
When arbitration is complete, the module with the highest arbitration priority must ter-
minate the bus cycle. Internal modules place an interrupt vector number on the data
bus and generate appropriate internal cycle termination signals. In the case of an ex-
ternal interrupt request, after the interrupt acknowledge cycle is transferred to the ex-
ternal bus, the appropriate external device must decode the mask value and respond
with a vector number, then generate data and size acknowledge (DSACK) termination
signals, or it must assert the autovector (AVEC) request signal. If the device does not
respond in time, the EBI bus monitor asserts the bus error signal BERR, and a spuri-
ous interrupt exception is taken.
4
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-
sponse to interrupt requests from external devices (refer to 4.8.3 Using Chip-Select
Signals for Interrupt Acknowledge). Chip-select address match logic functions only
after the EBI transfers an interrupt acknowledge cycle to the external bus following
IARB contention. If a module makes an interrupt request of a certain priority, and the
appropriate chip-select registers are programmed to generate AVEC or DSACK sig-
nals in response to an interrupt acknowledge cycle for that priority level, chip-select
logic does not respond to the interrupt acknowledge cycle, and the internal module
supplies a vector number and generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PI-
CR) determines PIT priority level. A PIRQ value of %000 means that PIT interrupts are
inactive. By hardware convention, when the CPU32 receives simultaneous interrupt
requests of the same level from more than one SIM source (including external devic-
es), the periodic interrupt timer is given the highest priority, followed by the IRQ pins.
4.7.4 Interrupt Processing Summary
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction
boundary.
B. The processor state is stacked. The S bit in the status register is set, establish-
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.
C. The interrupt acknowledge cycle begins:
1. FC[2:0] are driven to %111 (CPU space) encoding.
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2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]
= %1111, which indicates that the cycle is an interrupt acknowledge CPU
space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of
the interrupt request being acknowledged; and ADDR0 = %1.
3. The request level is latched from the address bus into the interrupt priority
mask field in the status or condition code register.
D. Modules that have requested interrupt service decode the priority value in AD-
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by
IARB contention takes place.
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt moni-
tor asserts BERR, and the CPU generates the spurious interrupt vector
number.
2. The dominant interrupt source supplies a vector number and DSACK sig-
nals appropriate to the access. The CPU acquires the vector number.
3. The AVEC signal is asserted (the signal can be asserted by the dominant
interrupt source or the pin can be tied low), and the CPU generates an au-
tovector number corresponding to interrupt priority.
4
4. The bus monitor asserts BERR and the CPU32 generates the spurious in-
terrupt vector number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor
transfers control to the exception handler routine.
4.7.5 Interrupt Acknowledge Bus Cycles
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL
CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD).
4.8 Chip Selects
Typical microcontrollers require additional hardware to provide external select and ad-
dress decode signals. The MCU includes 12 programmable chip-select circuits that
can provide 2- to 20-clock-cycle access to external memory and peripherals. Address
block sizes of two Kbytes to one Mbyte can be selected. Figure 4-17 is a diagram of
a basic system that uses chip selects.
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ASYNC BUS
PERIPHERAL
1
FC
SIZ
CLKOUT
AS
SIZ
CLK
AS
DSACK
DS
DSACK
DS
CS
CS3
CS5
IACK
IRQ
ADDR[23:0]
DATA[15:0]
IRQ
ADDR[15:0]
DATA[15:0]
2
MEMORY
2
MCU
ADDR[23:0]
DATA[15:8]
CS
R/W
CSBOOT
R/W
4
MEMORY
2
ADDR[23:0]
DATA[7:0]
CS
R/W
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
32 EXAMPLE SYS BLOCK
Figure 4-17 Basic MCU System
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, ad-
dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac-
knowledge) to parameters stored in chip-select registers. If all parameters match, the
appropriate chip-select signal is asserted. Select signals are active low. If a chip-select
function is given the same address as a microcontroller module or an internal memory
array, an access to that address goes to the module or array, and the chip-select sig-
nal is not asserted. The external address and data buses do not reflect the internal ac-
cess.
All chip-select circuits are configured for operation out of reset. However, all chip-se-
lect signals except CSBOOT are disabled, and cannot be asserted until the BYTE field
in the corresponding option register is programmed to a nonzero value, selecting a
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transfer size. The chip-select option must not be written until a base address has been
written to a proper base address register. CSBOOT is automatically asserted out of
reset. Alternate functions for chip-select pins are enabled if appropriate data bus pins
are held low at the release of the reset signal (refer to 4.6.3.1 Data Bus Mode Selec-
tion for more information). Figure 4-18 is a functional diagram of a single chip-select
circuit.
INTERNAL
BASE ADDRESS REGISTER
SIGNALS
ADDRESS
ADDRESS COMPARATOR
OPTION COMPARE
TIMING
AND
CONTROL
PIN
BUS CONTROL
OPTION REGISTER
4
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
AVEC
GENERATOR
DSACK
GENERATOR
AVEC
DSACK
CHIP SEL BLOCK
Figure 4-18 Chip-Select Circuit Block Diagram
4.8.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Ship-select pin assignment reg-
isters (CSPAR[0:1]) determine functions of the pins. Pin assignment registers also de-
termine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC)
latches data for chip-select pins that are used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two
Kbytes to one Mbyte can be selected by writing values to the appropriate base address
register (CSBAR[0:10], CSBARBT). Address blocks for separate chip-select functions
can overlap.
Chip select option registers (CSOR[0:10], CSORBT) determine timing of and condi-
tions for assertion of chip-select signals. Eight parameters, including operating mode,
access size, synchronization, and wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the
chip-select circuits. A set of special chip-select functions and registers (CSORBT, CS-
BARBT) is provided to support bootstrap operation.
Comprehensive address maps and register diagrams are provided in APPENDIX D
REGISTER SUMMARY.
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4.8.1.1 Chip-Select Pin Assignment Registers
The pin assignment registers contain twelve 2-bit fields (CS[10:0] and CSBOOT) that
determine the functions of the chip-select pins. Each pin has two or three possible
functions, as shown in Table 4-19.
Table 4-19 Chip-Select Pin Functions
16-Bit
Chip Select
8-Bit
Chip Select
Alternate
Function
Discrete
Output
CSBOOT
CS0
CSBOOT
CS0
CSBOOT
BR
—
—
CS1
CS1
BG
—
CS2
CS2
BGACK
FC0
—
CS3
CS3
PC0
PC1
PC2
PC3
PC4
PC5
PC6
ECLK
CS4
CS4
FC1
CS5
CS5
FC2
CS6
CS6
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
CS7
CS7
CS8
CS8
CS9
CS9
4
CS10
CS10
Table 4-20 shows pin assignment field encoding. Pins that have no discrete output
function do not use the %00 encoding.
Table 4-20 Pin Assignment Field Encoding
Bit Field
Description
Discrete Output
00
01
10
11
Alternate Function
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
Port size determines the way in which bus transfers to an external address are allo-
cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as
a chip select. Port size and transfer size affect how the chip-select signal is asserted.
Refer to 4.8.1.3 Chip-Select Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a correspond-
ing data bus pin. These pins have weak internal pull-up drivers, but can be held low
by external devices. (Refer to 4.6.3.1 Data Bus Mode Selection for more informa-
tion.) Either 16-bit chip-select function (%11) or alternate function (%01) can be select-
ed during reset. All pins except the boot ROM select pin (CSBOOT) are disabled out
of reset. There are twelve chip-select functions and only eight associated data bus
pins. There is not a one-to-one correspondence. Refer to 4.8.4 Chip-Select Reset
Operation for more detailed information.
The CSBOOT signal is normally enabled out of reset. The state of the DATA0 line dur-
ing reset determines what port width CSBOOT uses. If DATA0 is held high (either by
the weak internal pull-up driver or by an external pull-up device), 16-bit width is select-
ed. If DATA0 is held low, 8-bit port size is selected.
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A pin programmed as a discrete output drives an external signal to the value specified
in the pin data register. No discrete output function is available on pins CSBOOT, BR,
BG, or BGACK. ADDR23 provides ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select
logic still functions and can be used to generate DSACK or AVEC internally on an ad-
dress and control signal match.
4.8.1.2 Chip-Select Base Address Registers
Each chip select has an associated base address register. A base address is the low-
est address in the block of addresses enabled by a chip select. Block size is the extent
of the address block above the base address. Block size is determined by the value
contained in a BLKSZ field. Block addresses for different chip selects can overlap.
The BLKSZ field determines which bits in the base address field are compared to cor-
responding bits on the address bus during an access. Provided other constraints de-
termined by option register fields are also satisfied, when a match occurs, the
associated chip-select signal is asserted. Table 4-21 shows BLKSZ encoding.
4
Table 4-21 Block Size Encoding
BLKSZ[2:0]
000
Block Size
2 Kbyte
Address Lines Compared
ADDR[23:11]
001
8 Kbyte
ADDR[23:13]
010
16 Kbyte
64 Kbyte
128 Kbyte
256 Kbyte
512 Kbyte
1 Mbyte
ADDR[23:14]
011
ADDR[23:16]
100
ADDR[23:17]
101
ADDR[23:18]
110
ADDR[23:19]
111
ADDR[23:20]
The chip-select address compare logic uses only the most significant bits to match an
address within a block. The value of the base address must be a multiple of block size.
Base address register diagrams show how base register bits correspond to address
lines.
After reset, the MCU fetches the initialization routine from the address contained in the
reset vector, located beginning at address $000000 of program space. To support
bootstrap operation from reset, the base address field in chip-select base address reg-
ister boot (CSBARBT) has a reset value of all zeros. A memory device containing the
reset vector and initialization routine can be automatically enabled by CSBOOT after
a reset. The block size field in CSBARBT has a reset value of 512 Kbytes. Refer to
4.8.4 Chip-Select Reset Operation for more information.
4.8.1.3 Chip-Select Option Registers
Option register fields determine timing of and conditions for assertion of chip-select
signals. To assert a chip-select signal, and to provide DSACK or autovector support,
other constraints set by fields in the option register and in the base address register
must also be satisfied. Table 4-22 is a summary of option register functions.
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Table 4-22 Option Register Function Summary
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
0 = ASYNC* 00 = Disable
00 = Rsvd
0 = AS 0000 = 0 WAIT 00 = CPU SP
000 = All*
0 = Off*
1 = SYNC
01 = Lower
10 = Upper
*11 = Both
01 = Read 1 = DS 0001 = 1 WAIT 01 = User SP 001 = Priority 1 1 = On
10 = Write
11 = Both
0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
0011 = 3 WAIT 11 = S/U SP* 011 = Priority 3
0100 = 4 WAIT
0101 = 5 WAIT
0110 = 6 WAIT
0111 = 7 WAIT
1000 = 8 WAIT
1001 = 9 WAIT
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1110 = F term
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7
1111 = External
*Use this value when function is not required for chip-select operation.
4
The MODE bit determines whether chip-select assertion simulates an asynchronous
bus cycle, or is synchronized to the M6800-type bus clock signal (ECLK) available on
ADDR23 (refer to 4.3 System Clock for more information on ECLK).
The BYTE field controls bus allocation for chip-select transfers. Port size, set when a
chip select is enabled by a pin assignment register, affects signal assertion. When an
8-bit port is assigned, any BYTE field value other than %00 enables the chip select
signal. When a 16-bit port is assigned, however, BYTE field value determines when
the chip select is enabled. The BYTE fields for CS[10:0] are cleared during reset. How-
ever, both bits in the boot ROM option register (CSORBT) BYTE field are set (%11)
when the reset signal is released.
The R/W field causes a chip-select signal to be asserted only for a read, only for a
write, or for both read and write. Use this field in conjunction with the STRB bit to gen-
erate asynchronous control signals for external devices.
The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Se-
lecting address strobe causes a chip-select signal to be asserted synchronized with
the address strobe. Selecting data strobe causes a chip-select signal to be asserted
synchronized with the data strobe. This bit has no effect in synchronous mode.
The DSACK field specifies the source of data strobe acknowledge signals used in
asynchronous mode. It also allows the user to optimize bus speed in a particular ap-
plication by controlling the number of wait states that are inserted.
The SPACE field determines the address space in which a chip select is asserted. An
access must have the space type represented by SPACE encoding in order for a chip-
select signal to be asserted.
The IPL field contains an interrupt priority mask that is used when chip-select logic is
set to trigger on external interrupt acknowledge cycles. When the SPACE field is set
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to %00 (CPU space), interrupt priority (ADDR[3:1]) is compared to IPL value. If the val-
ues are the same, and other option register constraints are satisfied, a chip select sig-
nal is asserted. This field only affects the response of chip selects and does not affect
interrupt recognition by the CPU. Encoding %000 causes a chip-select signal to be as-
serted regardless of interrupt acknowledge cycle priority, provided all other constraints
are met.
The AVEC bit selects one of two methods of acquiring an interrupt vector during an
external interrupt acknowledge cycle. The internal autovector signal is generated only
in response to interrupt requests from the SIM IRQ pins.
4.8.1.4 PORTC Data Register
The PORTC data register latches data for PORTC pins programmed as discrete out-
puts. When a pin is assigned as a discrete output, the value in this register appears at
the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no
effect, and it always reads zero.
4.8.2 Chip-Select Operation
When the MCU makes an access, enabled chip-select circuits compare the following
items:
4
1. Function codes to SPACE fields, and to the IPL field if the SPACE field encod-
ing is not for CPU32 space.
2. Appropriate ADDR bits to base address fields.
3. Read/write status to R/W fields.
4. ADDR0 and/or SIZ bits to the BYTE field (16-bit ports only).
5. Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the
access is an interrupt acknowledge cycle).
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same
time as AS or DS assertion in asynchronous mode. Assertion is synchronized with
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field de-
termines whether DSACK is generated internally. DSACK also determines the number
of wait states inserted before internal DSACK assertion.
The speed of an external device determines whether internal wait states are needed.
Normally, wait states are inserted into the bus cycle during S3 until a peripheral as-
serts DSACK. If a peripheral does not generate DSACK, internal DSACK generation
must be selected and a predetermined number of wait states can be programmed into
the chip-select option register.
Refer to the SIM Reference Manual (SIMRM/AD) for further information.
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge
Ordinary I/O bus cycles use supervisor space access, but interrupt acknowledge bus
cycles use CPU space access. Refer to 4.5.4 CPU Space Cycles for more informa-
tion. There are no differences in flow for chip selects in each type of space, but base
and option registers must be properly programmed for each type of external bus cycle.
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During a CPU space cycle, bits [15:3] of the appropriate base register must be config-
ured to match ADDR[23:11], as the address is compared to an address generated by
the CPU.
Figure 4-19 shows CPU space encoding for an interrupt acknowledge cycle. FC[2:0]
are set to %111, designating CPU space access. ADDR[3:1] indicate interrupt priority,
and the space type field (ADDR[19:16]) is set to %1111, the interrupt acknowledge
code. The rest of the address lines are set to one.
FUNCTION
CODE
ADDRESS BUS
2
0
23
19
16
0
INTERRUPT
ACKNOWLEDGE
1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
CPU SPACE
TYPE FIELD
CPU SPACE IACK TIM
Figure 4-19 CPU Space Encoding for Interrupt Acknowledge
4
Because address match logic functions only after the EBI transfers an interrupt ac-
knowledge cycle to the external address bus following IARB contention, chip-select
logic generates AVEC or DSACK signals only in response to interrupt requests from
external IRQ pins. If an internal module makes an interrupt request of a certain priority,
and the chip-select base address and option registers are programmed to generate
AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority
level, chip-select logic does not respond to the interrupt acknowledge cycle, and the
internal module supplies a vector number and generates an internal DSACK signal to
terminate the cycle.
Perform the following operations before using a chip select to generate an interrupt ac-
knowledge signal.
1. Program the base address field to all ones.
2. Program block size to no more than 64 Kbytes, so that the address comparator
checks ADDR[19:16] against the corresponding bits in the base address regis-
ter. (The CPU32 places the CPU32 space type on ADDR[19:16].)
3. Set the R/W field to read only. An interrupt acknowledge cycle is performed as
a read cycle.
4. Set the BYTE field to lower byte when using a 16-bit port, as the external vector
for a 16-bit port is fetched from the lower byte. Set the BYTE field to upper byte
when using an 8-bit port.
If an interrupting device does not provide a vector number, an autovector acknowledge
must be generated. Asserting AVEC, either by asserting the AVEC pin or by generat-
ing AVEC internally using the chip-select option register, terminates the bus cycle.
4.8.4 Chip-Select Reset Operation
The least significant bits of each of the 2-bit CS[10:0] pin assignment fields in CSPAR0
and CSPAR1 each have a reset value of one. The reset values of the most significant
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bits of each field are determined by the states of DATA[7:1] during reset. There are
weak internal pull-up drivers for each of the data lines, so that chip-select operation
will be selected by default out of reset. However, the internal pull-up drivers can be
overcome by bus loading effects — to insure a particular configuration out of reset, use
an active device to put the data lines in a known state during reset. The base address
fields in chip-select base address registers CSBAR[0:10] and chip select option regis-
ters CSOR[0:10] have the reset values shown in Table 4-23. The BYTE fields of
CSOR[0:10] have a reset value of “disable”, so that a chip-select signal cannot be as-
serted until the base and option registers are initialized.
Table 4-23 Chip Select Base and Option Register Reset Values
Fields
Base Address
Block Size
Reset Values
$000000
2 Kbyte
Async/Sync Mode
Upper/Lower Byte
Read/Write
AS/DS
Asynchronous Mode
Disabled
Reserved
AS
DSACK
No Wait States
CPU Space
Any Level
4
Address Space
IPL
Autovector
External Interrupt Vector
Following reset, the MCU fetches initial stack pointer and program counter values from
the exception vector table, beginning at $000000 in supervisor program space. The
CSBOOT chip-select signal is used to select an external boot ROM mapped to a base
address of $000000. In order to do this, the reset values of the fields that control CS-
BOOT must be different from those of other chip select signals.
The MSB of the CSBOOT field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in option register CSORBT
has a reset value of “both bytes” so that the select signal is enabled out of reset. The
LSB value of the CSBOOT field, determined by the logic level of DATA0 during reset,
selects boot ROM port size. When DATA0 is held low during reset, port size is eight
bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a weak
internal pull-up driver, so that a 16-bit port will be selected by default out of reset. How-
ever, the internal pull-up driver can be overcome by bus loading effects — to insure a
particular configuration out of reset, use an active device to put DATA0 in a known
state during reset.
The base address field in chip-select base address register boot (CSBARBT) has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 1 Mbyte. Table 4-24 shows CSBOOT reset values.
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Table 4-24 CSBOOT Base and Option Register Reset Values
Fields
Base Address
Block Size
Reset Values
$000000
1 Mbyte
Async/Sync Mode
Upper/Lower Byte
Read/Write
AS/DS
Asynchronous Mode
Both Bytes
Read/Write
AS
DSACK
13 Wait States
Supervisor/User Space
Any Level
Address Space
IPL
Autovector
Interrupt Vector Externally
4.9 Parallel Input/Output Ports
Fifteen SIM pins can be configured for general-purpose discrete input and output. Al-
though these pins are organized into two ports, port E and port F, function assignment
is by individual pin. Pin assignment registers, data direction registers, and data regis-
ters are used to implement discrete I/O.
4
4.9.1 Pin Assignment Registers
Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the
functions of the pins in each port. Any bit set to one defines the corresponding pin as
a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O
pin.
4.9.2 Data Direction Registers
Bits in the port E and port F data direction registers (DDRE and DDRF) control the di-
rection of the pin drivers when the pins are configured as I/O. Any bit in a register set
to one configures the corresponding pin as an output. Any bit in a register cleared to
zero configures the corresponding pin as an input. These registers can be read or writ-
ten at any time. Writes have no effect.
4.9.3 Data Registers
A write to the port E and port F data registers (PORTE and PORTF) is stored in an
internal data latch, and if any pin in the corresponding port is configured as an output,
the value stored for that bit is driven out on the pin. A read of a data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value
read is the value stored in the register. Both data registers can be accessed in two lo-
cations. Registers can be read or written at any time.
4.10 Factory Test
The test submodule supports scan-based testing of the various MCU modules. It is in-
tegrated into the SIM to support production test. Test submodule registers are intend-
ed for Motorola use only. Register names and addresses are provided in APPENDIX
D REGISTER SUMMARY to show the user that these addresses are occupied. The
QUOT pin is also used for factory test.
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SECTION 5 CENTRAL PROCESSING UNIT
The CPU32, the instruction processing module of the M68300 family, is based on the
industry-standard MC68000 processor. It has many features of the MC68010 and
MC68020, as well as unique features suited for high-performance controller applica-
tions. This section is an overview of the CPU32. For detailed information concerning
CPU operation, refer to the CPU32 Reference Manual (CPU32RM/AD).
5.1 General
Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a philosophy emphasizing register-memory interac-
tion. There are eight multifunction data registers and seven general-purpose address-
ing registers.
All data resources are available to all operations requiring those resources. The data
registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand
lengths for all operations. Word and long-word operations support address manipula-
tion. Although the program counter (PC) and stack pointers (SP) are special-purpose
registers, they are also available for most data addressing activities. Ease of program
checking and diagnosis is further enhanced by trace and trap capabilities at the in-
struction level.
5
A block diagram of the CPU32 is shown in Figure 5-1. The major blocks operate in a
highly independent fashion that maximizes concurrence of operation while managing
the essential synchronization of instruction execution and bus operation. The bus con-
troller loads instructions from the data bus into the decode unit. The sequencer and
control unit provide overall chip control, managing the internal buses, registers, and
functions of the execution unit.
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USER’S MANUAL
DECODE
BUFFER
STAGE
C
STAGE
B
STAGE
A
INSTRUCTION PIPELINE
CONTROL STORE
PROGRAM
COUNTER
SECTION
DATA
SECTION
CONTROL LOGIC
EXECUTION UNIT
MICROSEQUENCER AND CONTROL
WRITE PENDING
BUFFER
PREFETCH
CONTROLLER
5
MICROBUS
CONTROLLER
ADDRESS
BUS
BUS CONTROL
SIGNALS
DATA
BUS
1127A
Figure 5-1 CPU32 Block Diagram
5.2 CPU32 Registers
The CPU32 programming model consists of two groups of registers that correspond
to the user and supervisor privilege levels. User programs can use only the registers
of the user model. The supervisor programming model, which supplements the user
programming model, is used by CPU32 system programmers who wish to protect sen-
sitive operating system functions. The supervisor model is identical to that of the
MC68010 and later processors.
The CPU32 has eight 32-bit data registers, seven 32-bit address registers, a 32-bit
program counter, separate 32-bit supervisor and user stack pointers, a 16-bit status
register, two alternate function code registers, and a 32-bit vector base register (see
Figure 5-2 and Figure 5-3).
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31
16 15
8 7
0
D0
D1
D2
D3
D4
D5
D6
D7
DATA REGISTERS
31
16 15
0
A0
A1
A2
A3
A4
A5
A6
ADDRESS REGISTERS
31
31
16 15
0
0
0
A7 (USP) USER STACK POINTER
5
PC
PROGRAM COUNTER
7
CCR
CONDITION CODE REGISTER
Figure 5-2 User Programming Model
31
31
16 15
15
0
0
0
A7’ (SSP) SUPERVISOR STACK POINTER
8 7
(CCR)
SR
STATUS REGISTER
VBR
VECTOR BASE REGISTER
2
0
SFC
DFC
ALTERNATE FUNCTION
CODE REGISTERS
Figure 5-3 Supervisor Programming Model Supplement
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5.2.1 Data Registers
The eight data registers can store data operands of 1,8, 16, 32, and 64 bits and ad-
dresses of 16 or 32 bits. The following data types are supported:
• Bits
• Packed Binary-Coded Decimal Digits
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long-Word Integers (32 bits)
• Quad-Word Integers (64 bits)
Each of data registers D7–D0 is 32 bits wide. Byte operands occupy the low-order 8
bits; word operands, the low-order 16 bits; and long-word operands, the entire 32 bits.
When a data register is used as either a source or destination operand, only the ap-
propriate low-order byte or word (in byte or word operations, respectively) is used or
changed; the remaining high-order portion is unaffected. The least significant bit (LSB)
of a long-word integer is addressed as bit zero, and the most significant bit (MSB) is
addressed as bit 31. Figure 5-4 shows the organization of various types of data in the
data registers.
5
Quad-word data consists of two long words and represents the product of 32-bit mul-
tiply or the dividend of 32-bit divide operations (signed and unsigned). Quad-words
may be organized in any two data registers without restrictions on order or pairing.
There are no explicit instructions for the management of this data type, although the
MOVEM instruction can be used to move a quad-word into or out of the registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. CPU32
BCD instructions use a format in which a byte contains two digits. The four LSB con-
tain the least significant digit, and the four MSB contain the most significant digit. The
ABCD, SBCD, and NBCD instructions operate on two BCD digits packed into a single
byte.
MOTOROLA
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31
MSB
30
1
0
LSB
BYTE
31
24 23
16 15
16 15
8 7
0
HIGH-ORDER BYTE
MIDDLE HIGH BYTE
MIDDLE LOW BYTE
LOW-ORDER BYTE
16-BIT WORD
31
0
0
HIGH-ORDER WORD
LOW-ORDER WORD
LONG WORD
31
LONG WORD
QUAD-WORD
63
62
32
0
MSB
ANY Dx
5
31
1
ANY Dy
LSB
Figure 5-4 Data Organization in Data Registers
5.2.2 Address Registers
Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Ad-
dress registers cannot be used for byte-sized operands. Therefore, when an address
register is used as a source operand, either the low-order word or the entire long-word
operand is used, depending upon the operation size. When an address register is
used as the destination operand, the entire register is affected, regardless of the op-
eration size. If the source operand is a word size, it is sign-extended to 32 bits. Ad-
dress registers are used primarily for addresses and to support address computation.
The instruction set includes instructions that add to, subtract from, compare, and move
the contents of address registers. Figure 5-5 shows the organization of addresses in
address registers.
31
31
16 15
0
0
SIGN EXTENDED
16-BIT ADDRESS OPERAND
FULL 32-BIT ADDRESS OPERAND
Figure 5-5 Address Organization in Address Registers
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5.2.3 Program Counter
The PC contains the address of the next instruction to be executed by the CPU32. Dur-
ing instruction execution and exception processing, the processor automatically incre-
ments the contents of the PC or places a new value in the PC as appropriate.
5.2.4 Control Registers
The control registers described in this section contain control information for supervi-
sor functions and vary in size. With the exception of the condition code register (the
user portion of the status register), they are accessed only by instructions at the su-
pervisor privilege level.
5.2.4.1 Status Register
The status register (SR) stores the processor status. It contains the condition codes
that reflect the results of a previous operation and can be used for conditional instruc-
tion execution in a program. The condition codes are extend (X), negative (N), zero
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition
codes is the only portion of the SR information available at the user privilege level; it
is referenced as the condition code register (CCR) in user programs.
5
At the supervisor privilege level, software can access the full status register. The upper
byte of this register includes the interrupt priority (IP) mask (three bits), two bits for
placing the processor in one of two tracing modes or disabling tracing, and the super-
visor/user bit for placing the processor at the desired privilege level.
Undefined bits in the status register are reserved by Motorola for future definition. The
undefined bits are read as zeros and should be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations, but for all CCR operations,
the upper byte is read as all zeros and is ignored when written, regardless of privilege
level.
Refer to APPENDIX D REGISTER SUMMARY for bit/field definitions and a diagram
of the status register.
5.2.4.2 Alternate Function Code Registers
Alternate function code registers (SFC and DFC) contain 3-bit function codes. Func-
tion codes can be considered extensions of the 24-bit linear address that optionally
provide as many as eight 16-Mbyte address spaces. The processor automatically gen-
erates function codes to select address spaces for data and programs at the user and
supervisor privilege levels and to select a CPU address space used for processor
functions (such as breakpoint and interrupt acknowledge cycles).
Registers SFC and DFC are used by the MOVES instruction to specify explicitly the
function codes of the memory address. The MOVEC instruction is used to transfer val-
ues to and from the alternate function code registers. This is a long-word transfer; the
upper 29 bits are read as zeros and are ignored when written.
MOTOROLA
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5.2.5 Vector Base Register (VBR)
The VBR contains the base address of the 1024-byte exception vector table, consist-
ing of 256 exception vectors. Exception vectors contain the memory addresses of rou-
tines that begin execution at the completion of exception processing. Refer to 5.9
Exception Processing for more information on the VBR and exception processing.
5.3 Memory Organization
Memory is organized on a byte-addressable basis in which lower addresses corre-
spond to higher order bytes. For example, the address N of a long-word data item cor-
responds to the address of the most significant byte of the highest order word. The
address of the most significant byte of the low-order word is N + 2, and the address of
the least significant byte of the long word is N + 3. The CPU32 requires long-word and
word data and instructions to be aligned on word boundaries (refer to Figure 5-6).
Data misalignment is not supported.
5
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USER’S MANUAL
BIT DATA
1 BYTE = 8 BITS
7
6
5
4
3
2
1
0
INTEGER DATA
1 BYTE = 8 BITS
15
MSB
8
7
0
0
BYTE 0
BYTE 2
LSB
BYTE 1
BYTE 3
WORD = 16 BITS
15
MSB
WORD 0
WORD 1
WORD 2
LSB
LONG WORD = 32 BITS
15
MSB
0
5
HIGH ORDER
LOW ORDER
LONG WORD 0
LSB
LONG WORD 1
LONG WORD 2
ADDRESS 1
ADDRESS = 32 BITS
15
MSB
0
HIGH ORDER
LOW ORDER
ADDRESS 0
ADDRESS 1
ADDRESS 2
LSB
MSB = Most Significant Bit
LSB = Least Significant Bit
DECIMAL DATA
BCD DIGITS = 1 BYTE
8 7
15
12 11
MSD
4 3
0
BCD 0
BCD 4
BCD 1
BCD 5
LSD
BCD 2
BCD 6
BCD 3
BCD 7
MSD = Most Significant Digit
LSD = Least Significant Digit
1125A
Figure 5-6 Memory Operand Addressing
MOTOROLA
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5.4 Virtual Memory
The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight
address spaces. Even though most systems implement a smaller physical memory,
the system can be made to appear to have a full 16 Mbytes of memory available to
each user program by using virtual memory techniques.
A system that supports virtual memory has a limited amount of high-speed physical
memory that can be accessed directly by the processor and maintains an image of a
much larger virtual memory on a secondary storage device. When the processor at-
tempts to access a location in the virtual memory map that is not resident in physical
memory, a page fault occurs. The access to that location is temporarily suspended
while the necessary data is fetched from secondary storage and placed in physical
memory. The suspended access is then restarted or continued.
The CPU32 uses instruction restart, which requires that only a small portion of the in-
ternal machine state be saved. After correcting the fault, the machine state is restored,
and the instruction is fetched and started again. This process is completely transpar-
ent to the application program.
5.5 Addressing Modes
5
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory. There is no
need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Absolute
• Immediate
The register indirect addressing modes include postincrement, predecrement, and off-
set capability. The program counter indirect mode also has index and offset capabili-
ties. In addition to these addressing modes, many instructions implicitly specify the
use of the status register, stack pointer, and/or program counter.
5.6 Processing States
The processor is always in one of four processing states: normal, exception, halted, or
background. The normal processing state is associated with instruction execution; the
bus is used to fetch instructions and operands and to store results.
The exception processing state is associated with interrupts, trap instructions, tracing,
and other exception conditions. The exception may be internally generated explicitly
by an instruction or by an unusual condition arising during the execution of an instruc-
tion. Exception processing can be forced externally by an interrupt, a bus error, or a
reset.
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The halted processing state is an indication of catastrophic hardware failure. For ex-
ample, if during the exception processing of a bus error another bus error occurs, the
processor assumes that the system is unusable and halts.
The background processing state is initiated by breakpoints, execution of special in-
structions, or a double bus fault. Background processing is enabled by pulling BKPT
low during RESET. Background processing allows interactive debugging of the sys-
tem via a simple serial interface.
5.7 Privilege Levels
The processor operates at one of two levels of privilege: user or supervisor. Not all in-
structions are permitted to execute at the user level, but all instructions are available
at the supervisor level. Effective use of privilege level can protect system resources
from uncontrolled access. The state of the S bit in the status register determines the
privilege level and whether the user stack pointer (USP) or supervisor stack pointer
(SSP) is used for stack operations.
5.8 Instructions
The CPU32 instruction set is summarized in Table 5-1. The instruction set of the
CPU32 is very similar to that of the MC68020. Two new instructions have been added
to facilitate controller applications: low-power stop (LPSTOP) and table lookup and in-
terpolate (TBLS, TBLSN, TBLU, TBLUN).
5
The following MC68020 instructions are not implemented on the CPU32:
BFxxx
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM — Call Module, Return Module
CAS, CAS2
cpxxx
— Compare and Swap (Read-Modify-Write Instructions)
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK — Pack, Unpack BCD Instructions
Memory — Memory Indirect Addressing Modes
The CPU32 traps on unimplemented instructions or illegal effective addressing
modes, allowing user-supplied code to emulate unimplemented capabilities or to de-
fine special purpose functions. However, Motorola reserves the right to use all current-
ly unimplemented instruction operation codes for future M68000 core enhancements.
MOTOROLA
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Table 5-1 Instruction Set Summary
Instruction
Syntax
Operand Size
Operation
ABCD
Dn, Dn–
(An), – (An)
8
8
Source + Destination + X
Destination
Destination
10 10
ADD
Dn, <ea>
<ea>, Dn
8, 16, 32
8, 16, 32
Source + Destination
ADDA
ADDI
<ea>, An
16, 32
Source + Destination
Immediate data + Destination
Immediate data + Destination
Source + Destination + X
Destination
#<data>, <ea>
#<data>, <ea>
8, 16, 32
8, 16, 32
Destination
ADDQ
ADDX
Destination
Destination
Dn, Dn–
(An), – (An)
8, 16, 32
8, 16, 32
AND
<ea>, Dn
Dn, <ea>
8, 16, 32
8, 16, 32
Source · Destination
Destination
ANDI
#<data>, <ea>
#<data>, CCR
#<data>, SR
8, 16, 32
Data · Destination
Source · CCR
Source · SR
Destination
CCR
ANDI to CCR
8
1
16
SR
ANDI to SR
ASL
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ASR
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
5
Bcc
<label>
8, 16, 32
If condition true, then PC + d
PC
Z;
BCHG
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
(<bit number> of destination
bit of destination
Z
BCLR
BGND
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
(<bit number> of destination
0
bit of destination
If background mode enabled, then enter
background mode, else format/vector offset – (SSP);
PC – (SSP); SR – (SSP); (vector) PC
none
none
BKPT
#<data>
none
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
BRA
<label>
8, 16, 32
PC + d
(<bit number> of destination
bit of destination
SP; PC (SP); PC + d
(<bit number> of destination
PC
BSET
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
Z;
1
BSR
<label>
8, 16, 32
SP – 4
PC
BTST
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
Z
CHK
<ea>, Dn
<ea>, Rn
16, 32
If Dn < 0 or Dn < (ea), then CHK exception
CHK2
8, 16, 32
If Rn < lower bound or Rn > upper bound, then
CHK exception
CLR
CMP
<ea>
8, 16, 32
8, 16, 32
16, 32
0
Destination
<ea>, Dn
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Data), CCR shows results
(Destination – Source), CCR shows results
Lower bound Rn Upper bound, CCR shows result
CMPA
CMPI
CMPM
CMP2
DBcc
<ea>, An
#<data>, <ea>
(An) +, (An) +
<ea>, Rn
8, 16, 32
8, 16, 32
8, 16, 32
16
Dn, <label>
If condition false, then Dn – 1
if Dn ≠ (– 1), then PC + d
PC;
PC
DIVS/DIVU
<ea>, Dn
32/16
16: 16
Destination / Source
Destination
(signed or unsigned)
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USER’S MANUAL
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MOTOROLA
5-11
Table 5-1 Instruction Set Summary (Continued)
Instruction
Syntax
Operand Size
Operation
DIVSL/DIVUL
ea , Dr : Dq
ea , Dq
ea , Dr : Dq
64/32
32/32
32/32
32 : 32
32
32 : 32
Destination / Source
Destination
(signed or unsigned)
EOR
EORI
Dn, ea
# data , ea
# data , CCR
# data , SR
Rn, Rn
8, 16, 32
Source Destination
Destination
Destination
CCR
8, 16, 32
Data Destination
Source CCR
Source SR
EORI to CCR
8
1
16
32
SR
EORI to SR
EXG
EXT
Rn
Rn
Dn
Dn
8
16
16
32
Sign extended Destination
Destination
Destination
EXTB
Dn
8
32
Sign extended Destination
ILLEGAL
none
none
SSP – 2
SSP – 4
SSP – 2
SSP; vector offset
(SSP);
(SSP);
(SSP);
SSP; PC
SSP; SR
illegal instruction vector address
PC
JMP
JSR
LEA
LINK
ea
ea
none
none
32
Destination PC
SP – 4
SP – 4
SP; PC
(SP); destination
An
PC
ea , An
An, # d
# data
ea
16, 32
none
SP, An
(SP); SP
An, SP + d
SP
1
Data
SR; interrupt mask EBI; STOP
LPSTOP
5
LSL
Dn, Dn
# data , Dn
ea
8, 16, 32
8, 16, 32
16
LSR
Dn, Dn
# data , Dn
ea
8, 16, 32
8, 16, 32
16
MOVE
ea , ea
ea , An
8, 16, 32
Source
Source
Destination
Destination
MOVEA
16, 32
32
1
USP, An
An, USP
32
32
USP
An
CCR
An
USP
MOVEA
MOVE from CCR
MOVE to CCR
CCR, ea
ea , CCR
SR, ea
16
16
16
16
Destination
Source
SR Destination
Source SR
USP
CCR
1
MOVE from SR
1
<ea>, SR
MOVE to SR
1
USP, An
An, USP
32
32
USP
Rc
AnAn
RnRn
MOVE USP
1
Rc, Rn
Rn, Rc
32
32
Rc
MOVEC
MOVEM
MOVEP
list, <ea>
<ea>, list
16, 32
16, 32
Listed registers
Source Listed registers
Destination
32
Dn, (d , An)
16
(d , An), Dn
16
16, 32
Dn [31 : 24]
Dn [15 : 8]
(An + d); Dn [23 : 16]
(An + d + 4); Dn [7 : 0]
(An + d + 2);
(An + d + 6)
(An + d)
(An + d + 4)
Dn [31 : 24]; (An + d + 2)
Dn [15 : 8]; (An + d + 6)
Dn [23 : 16];
Dn [7 : 0]
MOVEQ
#<data>, Dn
8
32
Immediate data
Destination
1
Rn, <ea>
<ea>, Rn
8, 16, 32
Rn
Destination using DFC
MOVES
Source using SFC
Rn
MULS/MULU
NBCD
<ea>, Dn
<ea>, Dl
<ea>, Dh : Dl
16 * 16
32 * 32
32 * 32
32
32
64
Source * Destination
Destination
(signed or unsigned)
<ea>
8
8
0 – Destination – X
10
Destination
MOTOROLA
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Table 5-1 Instruction Set Summary (Continued)
Instruction
NEG
Syntax
<ea>
<ea>
none
Operand Size
8, 16, 32
8, 16, 32
none
Operation
0 – Destination
Destination
Destination
PC
NEGX
NOP
0 – Destination – X
PC + 2
NOT
<ea>
8, 16, 32
Destination
Destination
Destination
OR
<ea>, Dn
Dn, <ea>
8, 16, 32
8, 16, 32
Source; Destination
ORI
#<data>, <ea>
#<data>, CCR
#<data>, SR
<ea>
8, 16, 32
16
Data; Destination
Destination
ORI to CCR
Source; CCR
Source; SR
SR
SR
1
16
ORI to SR
PEA
32
SP – 4
SP; <ea>
SP
1
none
none
Assert RESET line
RESET
ROL
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROR
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROXL
ROXR
RTD
Dn, Dn
#<data>,
Dn<ea>
8, 16, 32
8, 16, 32
16
5
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
#<d>
none
16
(SP)
PC; SP + 4 + d
SP
SP; (SP)
SP;
1
RTE
none
(SP)
SR; SP + 2
SP + 4
restore stack according to format
PC;
PC;
RTR
none
none
none
(SP)
CCR; SP + 2
SP + 4
SP; (SP)
SP
RTS
none
88
(SP)
PC; SP + 4
SP
SBCD
Dn, Dn
– (An), – (An)
Destination – Source – X
Destination
10 10
Scc
<ea>
8
If condition true, then destination bits are set to 1;
else, destination bits are cleared to 0
1
#<data>
16
Data
SR; STOP
STOP
SUB
<ea>, Dn
Dn, <ea>
8, 16, 32
Destination – Source
Destination
SUBA
SUBI
<ea>, An
16, 32
Destination – Source
Destination – Data
Destination
Destination
Destination
Destination
#<data>, <ea>
#<data>, <ea>
8, 16, 32
8, 16, 32
SUBQ
SUBX
Destination – Data
Dn, Dn
– (An), – (An)
8, 16, 32
8, 16, 32
Destination – Source – X
SWAP
Dn
16
TBLS/TBLU
<ea>, Dn
Dym : Dyn, Dn
8, 16, 32
Dyn – Dym
(Temp * Dn [7 : 0])
Temp
Temp
(Dym * 256) + Temp
Dn
TBLSN/TBLUN
TRAP
<ea>, Dn
Dym : Dyn, Dn
8, 16, 32
none
Dyn – Dym
(Temp * Dn [7 : 0]) / 256
Dym + Temp
Temp
Temp
Dn
#<data>
SSP – 2
SSP – 4
SSP; format/vector offset
SSP; PC (SSP); SR
vector address PC
(SSP);
(SSP);
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MOTOROLA
5-13
Table 5-1 Instruction Set Summary (Continued)
Instruction
Syntax
Operand Size
Operation
TRAPcc
none
#<data>
none
16, 32
If cc true, then TRAP exception
TRAPV
TST
none
<ea>
An
none
8, 16, 32
32
If V set, then overflow TRAP exception
Source – 0, to set condition codes
UNLK
An
SP; (SP)
An, SP + 4
SP
NOTE:
1. Privileged instruction
5.8.1 M68000 Family Compatibility
It is the philosophy of the M68000 family that all user-mode programs can execute un-
changed on a more advanced processor, and supervisor-mode programs and excep-
tion handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob-
ject code from an MC68000 or MC68010 may be executed on the CPU32, and many
of the instruction and addressing mode extensions of the MC68020 are also support-
ed. Refer to the CPU32 reference manual for a detailed comparison of the CPU32 and
MC68020 instruction set.
5
5.8.2 Special Control Instructions
Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
5.8.2.1 Low Power Stop (LPSTOP)
In applications where power consumption is a consideration, the CPU32 forces the de-
vice into a low power standby mode when immediate processing is not required. The
low power stop mode is entered by executing the LPSTOP instruction. The processor
remains in this mode until a user-specified (or higher) interrupt level or reset occurs.
5.8.2.2 Table Lookup and Interpolate (TBL)
To maximize throughput for real-time applications, reference data is often precalculat-
ed and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table instruction requires that only a sample of
data points be stored, reducing memory requirements. The TBL instruction recovers
intermediate values using linear interpolation. Results can be rounded with a round-
to-nearest algorithm.
5.9 Exception Processing
Exception processing is a special condition that preempts normal processing. Excep-
tion processing is the transition from normal mode program execution to execution of
a routine that deals with an exception.
MOTOROLA
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5.9.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The vector
base register (VBR) contains the base address of a 1024-byte exception vector table,
which consists of 256 exception vectors. Sixty-four vectors are defined by the proces-
sor, and 192 vectors are reserved for user definition as interrupt vectors. Except for
the reset vector, each vector in the table is one long word in length. The reset vector
is two long words in length. Refer to Table 5-2 for information on vector assignment.
CAUTION
Because there is no protection on the 64 processor-defined vectors,
external devices can access vectors reserved for internal purposes.
This practice is strongly discouraged.
All exception vectors, except the reset vector, are located in supervisor data space.
The reset vector is located in supervisor program space. Only the initial reset vector is
fixed in the processor memory map. When initialization is complete, there are no fixed
assignments. Since the VBR stores the vector table base address, the table can be
located anywhere in memory. It can also be dynamically relocated for each task exe-
cuted by an operating system.
5
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Table 5-2 Exception Vector Assignments
Vector
Vector Offset
Space
Assignment
Number
Dec
0
Hex
000
004
008
00C
010
014
018
01C
020
024
028
02C
030
034
038
03C
0
1
SP
SP
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
Reset: Initial Stack Pointer
Reset: Initial Program Counter
Bus Error
4
2
8
3
12
16
20
24
28
32
36
40
44
48
52
56
60
Address Error
4
Illegal Instruction
5
Zero Division
6
CHK, CHK2 Instructions
TRAPcc, TRAPV Instructions
Privilege Violation
7
8
9
Trace
10
11
12
13
14
15
16–23
Line 1010 Emulator
Line 1111 Emulator
Hardware Breakpoint
(Reserved, Coprocessor Protocol Violation)
Format Error and Uninitialized Interrupt
Format Error and Uninitialized Interrupt
(Unassigned, Reserved)
5
64
92
040
05C
24
25
96
060
064
068
06C
070
074
078
07C
SD
SD
SD
SD
SD
SD
SD
SD
SD
Spurious Interrupt
100
104
108
112
116
120
124
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Trap Instruction Vectors (0–15)
26
27
28
29
30
31
32–47
128
188
080
0BC
48–58
59–63
64–255
192
232
0C0
0E8
SD
SD
SD
(Reserved, Coprocessor)
(Unassigned, Reserved)
User Defined Vectors (192)
236
252
0EC
0FC
256
1020
100
3FC
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are ob-
tained from an external device; others are supplied by the processor. The processor
multiplies the vector number by four to calculate vector offset, then adds the offset to
the contents of the VBR. The sum is the memory address of the vector.
5.9.2 Types of Exceptions
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The TRAP,
TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause excep-
tions during normal execution. Illegal instructions, instruction fetches from odd ad-
dresses, word or long-word operand accesses from odd addresses, and privilege
violations also cause internal exceptions.
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Sources of external exception include interrupts, breakpoints, bus errors, and reset re-
quests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access con-
trol and processor restart.
5.9.3 Exception Processing Sequence
For all exceptions other than a reset exception, exception processing occurs in the fol-
lowing sequence. Refer to 4.6 Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the status
register. After the copy is made, the processor state bits in the status register are
changed — the S bit is set, establishing supervisor access level, and bits T1 and T0
are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority
mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched from
CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions,
internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created and
placed on the supervisor stack. All stack frames contain copies of the status register
and the program counter for use by RTE. The type of exception and the context in
which the exception occurs determine what other information is stored in the stack
frame.
5
Finally, the processor prepares to resume normal execution of instructions. The ex-
ception vector offset is determined by multiplying the vector number by four, and the
offset is added to the contents of the VBR to determine displacement into the excep-
tion vector table. The exception vector is loaded into the program counter. If no other
exception is pending, the processor will resume normal execution at the new address
in the PC.
5.10 Development Support
The following features have been implemented on the CPU32 to enhance the instru-
mentation and development environment:
• M68000 Family Development Support
• Background Debugging Mode
• Deterministic Opcode Tracking
• Hardware Breakpoints
5.10.1 M68000 Family Development Support
All M68000 Family members include features to facilitate applications development.
These features include the following:
Trace on Instruction Execution — M68000 Family processors include an instruction-
by-instruction tracing facility as an aid to program development. The MC68020,
MC68030, MC68040, and CPU32 also allow tracing only of those instructions
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causing a change in program flow. In the trace mode, a trace exception is gener-
ated after an instruction is executed, allowing a debugger program to monitor the
execution of a program under test.
Breakpoint Instruction — An emulator may insert software breakpoints into the target
code to indicate when a breakpoint has occurred. On the MC68010, MC68020,
MC68030, and CPU32, this function is provided via illegal instructions, $4848–
$484F, to serve as breakpoint instructions.
Unimplemented Instruction Emulation — During instruction execution, when an at-
tempt is made to execute an illegal instruction, an illegal instruction exception oc-
curs. Unimplemented instructions (F-line, A-line,...) utilize separate exception
vectors to permit efficient emulation of unimplemented instructions in software.
5.10.2 Background Debugging Mode
Microcomputer systems generally provide a debugger, implemented in software, for
system analysis at the lowest level. The background debugging mode (BDM) on the
CPU32 is unique in that the debugger has been implemented in CPU microcode.
BDM incorporates a full set of debugging options: registers can be viewed or altered,
memory can be read or written to, and test features can be invoked.
5
A resident debugger simplifies implementation of an in-circuit emulator. In a common
setup (see Figure 5-7), emulator hardware replaces the target system processor. A
complex, expensive pod-and-cable interface provides a communication path between
the target system and the emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for in-
circuit emulation. The processor remains in the target system (see Figure 5-8) and the
interface is simplified. The BSA monitors target processor operation and the on-chip
debugger controls the operating environment. Emulation is much “closer” to target
hardware, and many interfacing problems (e.g., limitations on high-frequency opera-
tion, AC and DC parametric mismatches, and restrictions on cable length) are mini-
mized.
TARGET
SYSTEM
IN-CIRCUIT
EMULATOR
TARGET
MCU
1128A
Figure 5-7 Common In-Circuit Emulator Diagram
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TARGET
SYSTEM
BUS STATE
ANALYZER
TARGET
MCU
1129A
Figure 5-8 Bus State Analyzer Configuration
5.10.2.1 Enabling BDM
Accidentally entering BDM in a non-development environment can lock up the CPU32
when the serial command interface is not available. For this reason, BDM is enabled
during reset via the breakpoint (BKPT) signal.
5
BDM operation is enabled when BKPT is asserted (low), at the rising edge of RESET.
BDM remains enabled until the next system reset. A high BKPT signal on the trailing
edge of RESET disables BDM. BKPT is latched again on each rising transition of RE-
SET. BKPT is synchronized internally, and must be held low for at least two clock cy-
cles prior to negation of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT extends
into the first bus cycle following reset, the bus cycle could inadvertently be tagged with
a breakpoint. Refer to the SIM Reference Manual (SIMRM/AD) for timing information.
5.10.2.2 BDM Sources
When BDM is enabled, any of several sources can cause the transition from normal
mode to BDM. These sources include external breakpoint hardware, the BGND in-
struction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled
when an exception condition occurs, the exception is processed normally. Table 5-3
summarizes the processing of each source for both enabled and disabled cases. As
shown in Table 5-3, the BKPT instruction never causes a transition into BDM.
Table 5-3 BDM Source Summary
Source
BDM Enabled
Background
Background
Background
BDM Disabled
Breakpoint Exception
Halted
BKPT
Double Bus Fault
BGND Instruction
BKPT Instruction
Illegal Instruction
Opcode Substitution/
Illegal Instruction
Opcode Substitution/
Illegal Instruction
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5.10.2.2.1 External BKPT Signal
Once enabled, BDM is initiated whenever assertion of BKPT is acknowledged. If BDM
is disabled, a breakpoint exception (vector $0C) is acknowledged. The BKPT input has
the same timing relationship to the data strobe trailing edge as does read cycle data.
There is no breakpoint acknowledge bus cycle when BDM is entered.
5.10.2.2.2 BGND Instruction
An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32
defines $4AFA (BGND) to be a BDM entry point when BDM is enabled. If BDM is dis-
abled, an illegal instruction trap is acknowledged.
5.10.2.2.3 Double Bus Fault
The CPU32 normally treats a double bus fault, or two bus faults in succession, as a
catastrophic system error, and halts. When this condition occurs during initial system
debug (a fault in the reset logic), further debugging is impossible until the problem is
corrected. In BDM, the fault can be temporarily bypassed, so that the origin of the fault
can be isolated and eliminated.
5.10.2.2.4 Peripheral Breakpoints
5
CPU32 peripheral breakpoints are implemented in the same way as external break-
points — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user's manual for additional details on the generation of periph-
eral breakpoints.
5.10.2.3 Entering BDM
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been as-
serted, the CPU enables the serial communication hardware and awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (see Table 5-4) by issuing a read system register command
(RSREG). ATEMP is used in most debugger commands for temporary storage — it is
imperative that the RSREG command be the first command issued after transition into
BDM.
Table 5-4 Polling the BDM Entry Source
Source
ATEMP[31:16]
SSW*
ATEMP[15:0]
$FFFF
Double Bus Fault
BGND Instruction
Hardware Breakpoint
$0000
$0001
$0000
$0000
*Special status word (SSW) is described in detail in the CPU32 Reference Manual (CPU32RM/AD).
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence
is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other
time will the processor write an odd value into this register.
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5.10.2.4 BDM Commands
Commands consist of one 16-bit operation word and can include one or more 16-bit
extension words. Each incoming word is read as it is assembled by the serial interface.
The microcode routine corresponding to a command is executed as soon as the com-
mand is complete. Result operands are loaded into the output shift register to be shift-
ed out as the next command is read. This process is repeated for each command until
the CPU returns to normal operating mode. Table 5-5 is a summary of background
mode commands.
Table 5-5 Background Mode Command Summary
Command
Read D/A Register
Mnemonic
Description
RDREG/RAREG Read the selected address or data register and
return the results via the serial interface.
Write D/A Register
WDREG/WAREG The data operand is written to the specified ad-
dress or data register.
Read System Register
RSREG
The specified system control register is read. All
registers that can be read in supervisor mode can
be read in background mode.
Write System Register
Read Memory Location
WSREG
READ
The operand data is written into the specified sys-
tem control register.
5
Read the sized data at the memory location spec-
ified by the long-word address. The source func-
tion code register (SFC) determines the address
space accessed.
Write Memory Location
Dump Memory Block
WRITE
DUMP
Write the operand data to the memory location
specified by the long-word address. The destina-
tion function code (DFC) register determines the
address space accessed.
Used in conjunction with the READ command to
dump large blocks of memory. An initial READ is
executed to set up the starting address of the
block and retrieve the first result. Subsequent op-
erands are retrieved with the DUMP command.
Fill Memory Block
FILL
Used in conjunction with the WRITE command to
fill large blocks of memory. An initial WRITE is ex-
ecuted to set up the starting address of the block
and supply the first operand. Subsequent oper-
ands are written with the FILL command.
Resume Execution
Patch User Code
GO
The pipe is flushed and re-filled before resuming
instruction execution at the current PC.
CALL
Current program counter is stacked at the loca-
tion of the current stack pointer. Instruction exe-
cution begins at user patch code.
Reset Peripherals
No Operation
RST
NOP
Asserts RESET for 512 clock cycles. The CPU is
not reset by this command. Synonymous with the
CPU RESET instruction.
NOP performs no operation and may be used as
a null command.
5.10.2.5 Background Mode Registers
BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
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5.10.2.5.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a bus or
address error. This address remains available until overwritten by a subsequent bus
cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.
The address of the first fault (if there was one) is not visible to the user.
5.10.2.5.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition from
background mode to normal mode. This register should be accessed to change the
flow of a program under development. Changing the RPC to an odd value will cause
an address error when normal mode prefetching begins.
5.10.2.5.3 Current Instruction Program Counter (PCC)
The PCC holds a pointer to the first word of the last instruction executed prior to tran-
sition into background mode. Due to instruction pipelining, the instruction pointed to
may not be the instruction which caused the transition. An example is a breakpoint on
a released write. The bus cycle may overlap as many as two subsequent instructions
before stalling the instruction sequencer. A breakpoint asserted during this cycle will
not be acknowledged until the end of the instruction executing at completion of the bus
cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immedi-
ately out of reset.
5
5.10.2.6 Returning from BDM
BDM is terminated when a resume execution (GO) or call user code (CALL) command
is received. Both GO and CALL flush the instruction pipeline and refetch instructions
from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit reflect
any changes made during BDM. FREEZE is negated prior to initiating the first
prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals
revert to IPIPE/IFETCH functionality.
5.10.2.7 Serial Interface
Communication with the CPU32 during BDM occurs via a dedicated serial interface,
which shares pins with other development features. Figure 5-9 is a block diagram of
the interface. The BKPT signal becomes the serial clock (DSCLK); serial input data
(DSI) is received on IFETCH, and serial output data (DSO) is transmitted on IPIPE.
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INSTRUCTION
REGISTER BUS
DEVELOPMENT SYSTEM
CPU
DATA
16
16
0
RCV DATA LATCH
COMMAND LATCH
DSI
SERIAL IN
PARALLEL OUT
PARALLEL IN
SERIAL OUT
DSO
PARALLEL IN
SERIAL OUT
SERIAL IN
PARALLEL OUT
16
STATUS
RESULT LATCH
5
EXECUTION
UNIT
16
STATUS
SYNCHRONIZE
MICROSEQUENCER
M
DATA
DSCLK
CONTROL
LOGIC
CONTROL
LOGIC
SERIAL
CLOCK
32 DEBUG I/O BLOCK
Figure 5-9 Debug Serial I/O Block Diagram
The serial interface uses a full-duplex synchronous protocol similar to the serial pe-
ripheral interface (SPI) protocol. The development system serves as the master of the
serial link since it is responsible for the generation of DSCLK. If DSCLK is derived from
the CPU32 system clock, development system serial logic is unhindered by the oper-
ating frequency of the target processor. Operable frequency range of the serial clock
is from DC to one-half the processor system clock frequency.
The serial interface operates in full-duplex mode —data is transmitted and received
simultaneously by both master and slave devices. In general, data transitions occur on
the falling edge of DSCLK and are stable by the following rising edge of DSCLK. Data
is transmitted MSB first, and is latched on the rising edge of DSCLK.
The serial data word is 17 bits wide — 16 data bits and a status/control bit. Bit 16 in-
dicates the status of CPU-generated messages as shown in Table 5-6.
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16
15
0
S/C
DATA FIELD
STATUS CONTROL BIT
Figure 5-10 BDM Serial Data Word
Table 5-6 CPU Generated Message Encoding
Bit 16
Data
xxxx
Message Type
Valid Data Transfer
0
0
1
1
1
FFFF
0000
0001
FFFF
Command Complete; Status OK
Not Ready with Response; Come Again
BERR Terminated Bus Cycle; Data Invalid
Illegal Command
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Motorola reserves the right to
use this bit for future enhancements.
5
5.10.2.8 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Motorola recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
DS
GND
1
3
5
7
9
2
4
6
8
BERR
BKPT/DSCLK
FREEZE
GND
RESET
IFETCH/DSI
V
DD
10 IPIPE/DSO
32 BERG
Figure 5-11 BDM Connector Pinout
5.10.3 Deterministic Opcode Tracking
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch
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(IFETCH) output identifies the bus cycles in which the operand is loaded into the in-
struction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these
two signals allows a bus analyzer to synchronize itself to the instruction stream and
monitor its activity.
5.10.4 On-Chip Breakpoint Hardware
An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap
on any memory access. Off-chip address comparators preclude breakpoints unless
show cycles are enabled. Breakpoints on instruction prefetches that are ultimately
flushed from the instruction pipeline are not acknowledged; operand breakpoints are
always acknowledged. Acknowledged breakpoints initiate exception processing at the
address in exception vector number 12, or alternately enter background mode.
5.11 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the perfor-
mance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 5-12 shows the
required form of an instruction loop for the processor to enter loop mode.
5
ONE WORD INSTRUCTION
DBCC
DBCC DISPLACEMENT
$FFFC = – 4
1126A
Figure 5-12 Loop Mode Instruction Sequence
The loop mode is entered when the DBcc instruction is executed, and the loop dis-
placement is –4. Once in loop mode, the processor performs only the data cycles as-
sociated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
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SECTION 6QUEUED SERIAL MODULE
This section is an overview of queued serial module (QSM) function. Refer to the QSM
Reference Manual (QSMRM/AD) for complete information about the QSM.
6.1 General
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI)
and the serial communication interface (SCI). Figure 6-1 is a block diagram of the
QSM.
MISO/PQS0
MOSI/PQS1
SCK/PQS2
PCS0/SS/PQS3
PCS1/PQS4
PCS2/PQS5
PCS3/PQS6
QSPI
6
PORT QS
INTERFACE
LOGIC
IMB
TXD/PQS7
RXD
SCI
QSM BLOCK
Figure 6-1 QSM Block Diagram
The QSPI provides easy peripheral expansion or interprocessor communication
through a full-duplex, synchronous, three-line bus. Four programmable peripheral chip
selects can select up to 16 peripheral devices. A self-contained RAM queue allows up
to sixteen serial transfers of eight to sixteen bits each or transmission of a 256-bit data
stream without CPU intervention. A special wraparound mode supports continuous
sampling of a serial peripheral, with automatic QSPI RAM updating, for efficient inter-
facing to A/D converters.
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The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It will oper-
ate in either full- or half-duplex mode. There are separate transmitter and receiver en-
able bits and dual data buffers. A modulus-type baud rate generator provides rates
from 64 to 524 kbaud with a 16.78-MHz system clock, or 110 to 655 kbaud with a
20.97-MHz system clock. Word length of either eight or nine bits can be selected. Op-
tional parity generation and detection provide either even or odd parity check capabil-
ity. Advanced error detection circuitry catches glitches of up to 1/16 of a bit time in
duration. Wakeup functions allow the CPU to run uninterrupted until meaningful data
is available.
6.2 QSM Registers and Address Map
There are four types of QSM registers: QSM global registers, QSM pin control regis-
ters, QSPI registers, and SCI registers. Global registers and pin control registers are
discussed in 6.2.1 QSM Global Registers and 6.2.2 QSM Pin Control Registers.
QSPI and SCI registers are discussed in 6.3 Queued Serial Peripheral Interface and
6.4 Serial Communication Interface. Writes to unimplemented register bits have no
meaning or effect, and reads from unimplemented bits always return a logic zero val-
ue.
6
The QSM address map includes the QSM registers and the QSPI RAM. The module
mapping (MM) bit in the SIM configuration register (SIMCR) defines the most signifi-
cant bit (ADDR23) of the IMB address for each module in the MCU.
Refer to APPENDIX D REGISTER SUMMARY for a QSM address map and register
bit/field definitions. SECTION 4 SYSTEM INTEGRATION MODULE contains more in-
formation about how the state of MM affects the system.
6.2.1 QSM Global Registers
The QSM configuration register (QSMCR) contains parameters for interfacing to the
CPU32 and the intermodule bus. The QSM test register (QTEST) is used during fac-
tory test of the QSM. The QSM interrupt level register (QILR) interrupt level register
(QILR) determines the priority of interrupts requested by the QSM and the vector used
when an interrupt is acknowledged. The QSM interrupt vector register (QIVR) interrupt
vector register (QIVR) contains the interrupt vector for both QSM submodules. QILR
and QIVR are 8-bit registers located at the same word address. Refer to APPENDIX
D REGISTER SUMMARY for register bit and field definitions.
6.2.1.1 Low-Power Stop Operation
When the STOP bit in the QSMCR is set, the system clock input to the QSM is disabled
and the module enters a low-power operating state. QSMCR is the only register guar-
anteed to be readable while STOP is asserted. The QSPI RAM is not readable, but
writes to RAM or any register are guaranteed valid while STOP is asserted. STOP can
be set by the CPU and by reset.
System software must stop the QSPI and SCI before asserting STOP to prevent data
corruption and simplify restart. Disable both SCI receiver and transmitter after trans-
fers in progress are complete. Halt the QSPI by setting the HALT bit in SPCR3 and
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then setting STOP after the HALTA flag is set. Refer to SECTION 4 SYSTEM INTE-
GRATION MODULE for more information about low-power operation.
6.2.1.2 Freeze Operation
The freeze (FRZ[1:0]) bits in the QSMCR are used to determine what action is taken
by the QSM when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ0 has no effect;
setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE
assertion. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information
about background debugging mode.
6.2.1.3 QSM Interrupts
Both the QSPI and SCI can make interrupt requests on the IMB. Each has a separate
interrupt request priority register, but a single vector register is used to generate ex-
ception vector numbers.
The values of the ILQSPI and ILSCI fields in the QILR determine the priority of QSPI
and SCI interrupt requests. The values in these fields correspond to internal interrupt
request signals IRQ[7:1]. A value of %111 causes IRQ7 to be asserted when a QSM
interrupt request is made; lower field values cause corresponding lower-numbered in-
terrupt request signals to be asserted. Setting field value to %000 disables interrupts.
If ILQSPI and ILSCI have the same nonzero value, and the QSPI and SCI make simul-
taneous interrupt requests, the QSPI has priority.
6
When the CPU32 acknowledges an interrupt request, it places the value in the inter-
rupt priority (IP) mask in the CPU status register on the address bus. The QSM com-
pares IP mask value to request priority to determine whether it should contend for
arbitration priority. Arbitration priority is determined by the value of the IARB field in the
QSMCR. Each module that generates interrupts must have a nonzero IARB value. Ar-
bitration is performed by means of serial assertion of IARB field bit values.
When the QSM wins interrupt arbitration, it responds to the CPU interrupt acknowl-
edge cycle by placing an interrupt vector number on the data bus. The vector number
is used to calculate displacement into the CPU32 exception vector table. SCI and
QSPI vector numbers are generated from the value in the QIVR INTV field. The values
of bits INTV[7:1] are the same for QSPI and SCI, but the value of INTV0 is supplied by
the QSM when an interrupt request is made. INTV0 = 0 for SCI interrupt requests;
INTV0 = 1 for QSPI requests.
At reset, INTV is initialized to $0F, the uninitialized interrupt vector number. To enable
interrupt-driven serial communication, a user-defined vector number ($40–$FF) must
be written to QIVR, and interrupt handler routines must be located at the addresses
pointed to by the corresponding vector. CPU writes to INTV0 have no meaning or ef-
fect. Reads of INTV0 return a value of one.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
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6.2.2 QSM Pin Control Registers
The QSM uses nine pins. Eight of the pins can be used for serial communication or for
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the
pin an output. DDRQS affects both QSPI function and I/O function. DDQS1 deter-
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output. PQSPAR and DDRQS are 8-bit
registers located at the same word address. Table 6-1 is a summary of QSM pin func-
tions.
The port QS data register (PORTQS) latches I/O data. Writes to PORTQS drive pins
defined as outputs. PORTQS reads return data present on the pins when the read is
made. To avoid driving undefined data, first write PORTQS, then configure DDRQS.
Table 6-1 QSM Pin Function
6
QSM Pin
Mode
DDRQS Bit
Bit
State
Pin Function
MISO
Master
DDQS0
0
1
Serial Data Input to QSPI
Disables Data Input
Slave
Master
Slave
0
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
1
MOSI
DDQS1
DDQS2
0
1
0
1
1
SCK
Master
Slave
0
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
1
0
1
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
PCS0/SS
PCS[3:1]
Master
Slave
DDQS3
0
1
0
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
1
Master
Slave
DDQS[4:6]
0
1
0
Inactive
1
Inactive
2
TXD
Transmit
Receive
DDQS7
None
X
NA
Serial Data Output from SCI
Serial Data Input to SCI
RXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes the SPI
serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 set), in which case it becomes
SCI serial output TXD and DDRQS has no effect.
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6.3 Queued Serial Peripheral Interface
The queued serial peripheral interface (QSPI) communicates with external devices
through a synchronous serial bus. The QSPI is fully compatible with SPI systems
found on other Motorola products, but has enhanced capabilities. The QSPI can per-
form full duplex three-wire or half duplex two-wire transfers. A variety of transfer rate,
clocking, and interrupt-driven communication options are available.
Serial transfer of any number of bits from eight to sixteen can be specified. Program-
mable transfer length simplifies interfacing to a number of devices that require different
data lengths.
An inter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 sys-
tem clocks). Programmable delay simplifies the interface to a number of devices that
require different delays between transfers.
A dedicated 80-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. Serial peripher-
als can be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 16 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to in-
dependently complete one serial transfer.
6
A pointer identifies the queue location containing the command for the next serial
transfer. Normally, the pointer address is incremented after each serial transfer, but
the CPU can change the pointer value at any time. Multiple-task support can be pro-
vided by segmenting the queue.
The QSPI has four peripheral chip-select pins. Chip-select signals simplify interfacing
by reducing CPU intervention. If chip-select signals are externally decoded, 16 inde-
pendent select signals can be generated. Each chip-select pin can drive up to four in-
dependent peripherals, depending on loading.
Wraparound operating mode allows continuous execution of queued commands. In
wraparound mode, newly received data replaces previously received data in receive
RAM. Wraparound can simplify the interface with A/D converters by continuously up-
dating conversion values stored in the RAM.
Continuous transfer mode allows simultaneous transfer of an uninterrupted bit stream.
Any number of bits in a range from 8 to 256 can be transferred without CPU interven-
tion. Longer transfers are possible, but minimal CPU intervention is required to prevent
loss of data. A standard delay of 17 system clocks is inserted between each queue
entry transfer.
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USER’S MANUAL
QUEUE CONTROL
BLOCK
4
QUEUE
POINTER
COMPARATOR
DONE
END QUEUE
POINTER
80-BYTE
QSPI RAM
ADDRESS
REGISTER
4
CONTROL
LOGIC
STATUS
REGISTER
CONTROL
REGISTERS
6
CHIP SELECT
COMMAND
4
4
DELAY
COUNTER
M
S
MSB
LSB
8/16-BIT SHIFT REGISTER
Rx/Tx DATA REGISTER
MOSI
MISO
PROGRAMMABLE
LOGIC ARRAY
M
S
PCS0/SS
PCS [3:1]
3
BAUD RATE
GENERATOR
SCK
QSPI BLOCK
Figure 6-2 QSPI Block Diagram
6.3.1 QSPI Registers
The programmer's model for the QSPI consists of the QSM global and pin control reg-
isters, four QSPI control registers (SPCR[0:3]), a status register (SPCR), and the 80-
byte QSPI RAM.
Registers and RAM can be read and written by the CPU. Refer to APPENDIX D REG-
ISTER SUMMARY for register bit and field definitions.
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6.3.1.1 Control Registers
Control registers contain parameters for configuring the QSPI and enabling various
modes of operation. The CPU has read and write access to all control registers, but
the QSM has read-only access to all bits except the SPE bit in SPCR1. Control regis-
ters must be initialized before the QSPI is enabled to ensure defined operation.
SPCR1 must be written last because it contains the QSPI enable bit (SPE).
Writing a new value to any control register except SPCR2 while the QSPI is enabled
disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after
completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execu-
tion to restart at the designated location. Reads of SPCR2 return the current value of
the register, not of the buffer.
Writing the same value into any control register except SPCR2 while the QSPI is en-
abled has no effect on QSPI operation.
6.3.1.2 Status Register
The QSPI status register (SPSR) contains information concerning the current serial
transmission. Only the QSPI can set the bits in this register. The CPU reads the SPSR
to obtain QSPI status information and writes it to clear status flags.
6
6.3.2 QSPI RAM
The QSPI contains an 80-byte block of dual-access static RAM that can be accessed
by both the QSPI and the CPU. The RAM is divided into three segments: receive data
RAM, transmit data RAM, and command control data RAM. Receive data is informa-
tion received from a serial device external to the MCU. Transmit data is information
stored by the CPU for transmission to an external device. Command control data is
used to perform transfers. Refer to Figure 6-3, which shows RAM organization.
D00
RR0
RR1
RR2
D20
TR0
TR1
TR2
D40
CR0
CR1
CR2
RECEIVE
RAM
TRANSMIT
RAM
COMMAND
RAM
RRD
RRE
RRF
TRD
TRE
TRF
CRD
CRE
CRF
D1E
D3E
D4F
WORD
WORD
BYTE
QSPI RAM MAP
Figure 6-3 QSPI RAM
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USER’S MANUAL
6.3.2.1 Receive RAM
Data received by the QSPI is stored in this segment. The CPU reads this segment to
retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused bits
in a receive queue entry are set to zero by the QSPI upon completion of the individual
queue entry. The CPU can access the data using byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU
uses this information to determine which locations in receive RAM contain valid data
before reading them.
6.3.2.2 Transmit RAM
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit RAM in a right-justified for-
mat. The QSPI cannot modify information in the transmit RAM. The QSPI copies the
information to its data serializer for transmission. Information remains in transmit RAM
until overwritten.
6
6.3.2.3 Command RAM
Command RAM is used by the QSPI in master mode. The CPU writes one byte of con-
trol information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI pro-
ceeds from the address in NEWQP through the address in ENDQP (both of these
fields are in SPCR2).
6.3.3 QSPI Pins
The QSPI uses seven pins. These pins can be configured for general-purpose I/O
when not needed for QSPI application. When used for QSPI functions, the MOSI, MI-
SO, and SS pins should have pull-up resistors.
Table 6-2 shows QSPI input and output pins and their functions.
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Table 6-2 QSPI Pin Function
Pin/Signal Name
Mnemonic
Mode
Function
Master In Slave Out
MISO
Master
Slave
Serial Data Input to QSPI Serial
Data Output from QSPI
Master Out Slave In
Serial Clock
MOSI
SCK
Master
Slave
Serial Data Output from QSPI
Serial Data Input to QSPI
Master
Slave
Clock Output from QSPI
Clock Input to QSPI
Peripheral Chip Selects
Slave Select
PCS[3:1]
SS
Master
Select Peripherals
Causes Mode Fault
Master
Slave
Peripheral Chip Select 0
PCS0
Master
Initiates Serial Transfer
Selects Peripherals
6.3.4 QSPI Operation
The QSPI uses a dedicated 80-byte block of static RAM accessible by both the QSPI
and the CPU to perform queued operations. The RAM is divided into three segments.
There are 16 command control bytes, 16 transmit data words, and 16 receive data
words. QSPI RAM is organized so that one byte of command control data, one word
of transmit data, and one word of receive data correspond to one queue entry, $0–$F.
6
The CPU initiates QSPI operation by setting up a queue of QSPI commands in com-
mand RAM, writing transmit data into transmit RAM, then enabling the QSPI. The
QSPI executes the queued commands, sets a completion flag (SPIF), and then either
interrupts the CPU or waits for CPU intervention.
There are four queue pointers. The CPU can access three of them through fields in
QSPI registers. The new queue pointer (NEWQP), in SPCR2, points to the first com-
mand in the queue. An internal queue pointer points to the command currently being
executed. The completed queue pointer (CPTQP), in SPSR, points to the last com-
mand executed. The end queue pointer (ENDQP), contained in SPCR2, points to the
final command in the queue.
The internal pointer is initialized to the same value as NEWQP. During normal opera-
tion, the command pointed to by the internal pointer is executed, the value in the inter-
nal pointer is copied into CPTQP, the internal pointer is incremented, and then the
sequence repeats. Execution continues at the internal pointer address unless the
NEWQP value is changed. After each command is executed, ENDQP and CPTQP are
compared. When a match occurs, the SPIF flag is set and the QSPI stops unless wrap-
around mode is enabled.
At reset, NEWQP is initialized to $0. When the QSPI is enabled, execution begins at
queue address $0 unless another value has been written into NEWQP. ENDQP is ini-
tialized to $0 at reset, but should be changed to show the last queue entry before the
QSPI is enabled. NEWQP and ENDQP can be written at any time. When the NEWQP
value changes, the internal pointer value also changes. However, if NEWQP is written
while a transfer is in progress, the transfer is completed normally. Leaving NEWQP
and ENDQP set to $0 causes a single transfer to occur when the QSPI is enabled.
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USER’S MANUAL
6.3.5 QSPI Operating Modes
The QSPI operates in either master or slave mode. Master mode is used when the
MCU originates data transfers. Slave mode is used when an external device initiates
serial transfers to the MCU through the QSPI. Switching between the modes is con-
trolled by MSTR in SPCR0. Before either mode is entered, appropriate QSM and QSPI
registers must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in
each command RAM queue entry. Chip-select pins are activated, data is transmitted
from transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin activation by an external bus
master. Operation is similar to master mode, but no peripheral chip selects are gener-
ated, and the number of bits transferred is controlled in a different manner. When the
QSPI is selected, it automatically executes the next queue transfer to exchange data
with the external device correctly.
Although the QSPI inherently supports multimaster operation no special arbitration
mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master
arbitration. System software must provide arbitration. Note that unlike previous SPI
systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output
drivers disabled. The QSPI and associated output drivers must be disabled by clearing
SPE in SPCR1.
6
Figure 6-4 shows QSPI initialization; Figure 6-5 and Figure 6-6 show QSPI master
and slave operation. The CPU must initialize the QSM global and pin registers and the
QSPI control registers before enabling the QSPI for either mode of operation (refer to
6.5 QSM Initialization). The command queue must be written before the QSPI is en-
abled for master mode operation. Any data to be transmitted should be written into
transmit RAM before the QSPI is enabled. During wraparound operation, data for sub-
sequent transmissions can be written at any time.
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BEGIN
CPU INITIALIZES
QSM GLOBAL REGISTERS
CPU INITIALIZES
QSM PIN REGISTERS
INITIALIZATION OF
QSPI BY THE CPU
CPU INITIALIZES
QSPI CONTROL REGISTERS
6
CPU INITIALIZES
QSPI RAM
CPU ENABLES QSPI
YES
MSTR = 1
?
NO
A2
A1
QSPI FLOW 1
Figure 6-4 Flowchart of QSPI Initialization Operation
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USER’S MANUAL
QSPI CYCLE BEGINS
(MASTER MODE)
A1
IS QSPI
DISABLED
?
YES
YES
NO
HAS NEWQP
BEEN WRITTEN
?
WORKING QUEUE POINTER
CHANGED TO NEWQP
NO
READ COMMAND CONTROL
AND TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
6
ASSERT PERIPHERAL
CHIP-SELECT(S)
IS PCS TO
SCK DELAY
PROGRAMMED
?
YES
EXECUTE PROGRAMMED DELAY
NO
EXECUTE STANDARD DELAY
EXECUTE SERIAL TRANSFER
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
B1
QSPI FLOW 2
Figure 6-5 Flowchart of QSPI Master Operation (Part 1)
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USER’S MANUAL
QSPI CYCLE BEGINS
(SLAVE MODE)
A2
IS QSPI
DISABLED
?
YES
YES
NO
QUEUE POINTER
CHANGED TO NEWQP
HAS NEWQP
BEEN WRITTEN
?
NO
READ TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
6
IS SLAVE
SELECT PIN
ASSERTED
?
YES
NO
EXECUTE SERIAL TRANSFER
WHEN SCK RECEIVED
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
WRITE QUEUE POINTER TO
CPTQP STATUS BITS
B2
QSPI FLOW 3
Figure 6-5 Flowchart of QSPI Master Operation (Part 2)
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MOTOROLA
6-13
B1
WRITE QUEUE POINTER
TO CPTQP STATUS BITS
IS CONTINUE
BIT ASSERTED
?
YES
NO
6
NEGATE PERIPHERAL
CHIP-SELECT(S)
IS DELAY
AFTER TRANSFER
ASSERTED
?
YES
EXECUTE PROGRAMMED DELAY
NO
EXECUTE STANDARD DELAY
C
QSPI FLOW 4
Figure 6-5 Flowchart of QSPI Master Operation (Part 3)
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USER’S MANUAL
B2
IS QSPI
DISABLED
?
YES
YES
NO
QUEUE POINTER
CHANGED TO NEWQP
HAS NEWQP
BEEN WRITTEN
?
NO
READ TRANSMIT DATA
FROM RAM USING QUEUE
POINTER ADDRESS
6
IS SLAVE
SELECT PIN
ASSERTED
?
YES
NO
EXECUTE SERIAL TRANSFER
WHEN SCK RECEIVED
STORE RECEIVED DATA
IN RAM USING QUEUE
POINTER ADDRESS
WRITE QUEUE POINTER TO
CPTQP STATUS BITS
C
QSPI FLOW 5
Figure 6-6 Flowchart of QSPI Slave Operation (Part 1)
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USER’S MANUAL
C
IS THIS THE
LAST COMMAND
IN THE QUEUE
?
YES
ASSERT SPIF
STATUS FLAG
NO
IS INTERRUPT
ENABLE BIT SPIFIE
ASSERTED
?
YES
YES
INTERRUPT CPU
NO
IS WRAP
ENABLE BIT
ASSERTED
?
INCREMENT WORKING
QUEUE POINTER
RESET WORKING QUEUE
POINTER TO NEWQP OR $0000
NO
6
DISABLE QSPI
A1
IS HALT
OR FREEZE
ASSERTED
?
YES
HALT QSPI AND
ASSERT HALTA
NO
IS INTERRUPT
ENABLE BIT HMIE
ASSERTED
?
YES
YES
INTERRUPT CPU
NO
IS HALT
OR FREEZE
ASSERTED
?
NO
A2
QSPI FLOW 6
Figure 6-6 Flowchart of QSPI Slave Operation (Part 2)
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Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock
on the SPI bus master supplies the clock signal (SCK) to time the transfer of data. Four
possible combinations of clock phase and polarity can be specified by the CPHA and
CPOL bits in SPCR0.
Data is transferred with the most significant bit first. The number of bits transferred per
command defaults to eight, but can be set to any value from eight to sixteen bits by
writing a value into the BITSE field in command RAM.
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the
system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open-
drain outputs. An external pull-up resistor should be used on each output line. WOMQ
affects all QSPI pins regardless of whether they are assigned to the QSPI or used as
general-purpose I/O.
6.3.5.1 Master Mode
Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the
QSPI can initiate serial transfers, but cannot respond to externally initiated transfers.
When the slave select input of a device configured for master mode is asserted, a
mode fault occurs.
6
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for master mode operation are MISO
and MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data
input in master mode, and MOSI is used for serial data output. Either or both may be
necessary, depending on the particular application. SCK is the serial clock output in
master mode.
Before master mode operation is initiated, QSM register DDRQS must be written to
direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate
chip-select pins PCS[3:0]/SS as outputs. The MISO pin must be configured as an in-
put.
After pins are assigned and configured, write appropriate data to the command queue.
If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers
as appropriate.
Data transfer is synchronized with the internally-generated serial clock (SCK). Control
bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of
CPHA and CPOL determine upon which SCK edge to drive outgoing data from the
MOSI pin and to latch incoming data from the MISO pin.
Baud rate is selected by writing a value from 2 to 255 into the SPBR field in SPCR0.
The QSPI uses a modulus counter to derive SCK baud rate from the MCU system
clock.
The following expressions apply to SCK baud rate:
System Clock
SCK Baud Rate = ------------------------------------
2 × SPBR
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USER’S MANUAL
or
System Clock
SPBR = ----------------------------------------------------------------------------------------
(2 × SCK) × (Baud Rate Desired)
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state value.
The DSCK field in command RAM determines the delay period from chip-select asser-
tion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines
the period of delay before the assertion of SCK. The following expression determines
the actual delay before SCK:
DSCKL
PCS to SCK Delay = ------------------------------------------------------------------
System Clock Frequency
where DSCKL equals {1, 2, 3,..., 127}.
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the DSCK period.
There are two transfer length options. The user can choose a default value of eight
bits, or a programmed value of eight to sixteen bits, inclusive. The programmed value
must be written into the BITS field in SPCR0. The BITSE field in command RAM de-
termines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used.
Table 6-3 shows BITS field encoding.
6
Table 6-3 BITS Encoding
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. There are two transfer delay options. The user can choose to delay
a standard period after serial transfer is complete or can specify a delay period. Writing
a value to the DTL field in SPCR1 specifies a delay period. The DT bit in command
RAM determines whether the standard delay period (DT = 0) or the specified delay pe-
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riod (DT = 1) is used. The following expression is used to calculate the delay:
32 × DTL
Delay after Transfer = ------------------------------------------------------------------
System Clock Frequency
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/system clock.
17
Standard Delay after Transfer = ------------------------------------
System Clock
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased proportion-
ately.
Operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the
QSPI executes the command at the command RAM address pointed to by NEWQP.
Data at the pointer address in transmit RAM is loaded into the data serializer and
transmitted. Data that is simultaneously received is stored at the pointer address in re-
ceive RAM.
6
When the proper number of bits have been transferred, the QSPI stores the working
queue pointer value in CPTQP, increments the working queue pointer, and loads the
next data for transfer from transmit RAM. The command pointed to by the incremented
working queue pointer is executed next, unless a new value has been written to
NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in command RAM is set, PCS pins are continuously driven in
specified states during and between transfers. If the chip-select pattern changes dur-
ing or between transfers, the original pattern is driven until execution of the following
transfer begins. When CONT is cleared, the data in register PORTQS is driven be-
tween transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
6.3.5.2 Master Wraparound Mode
Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap
to pointer address $0 or to the address pointed to by NEWQP, depending on the state
of the WRTO bit in SPCR2.
In wraparound mode, the QSPI cycles through the queue continuously, even while the
QSPI is requesting interrupt service. SPE is not cleared when the last command in the
queue is executed. New receive data overwrites previously received data in receive
RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not au-
tomatically reset. If interrupt-driven SPI service is used, the service routine must clear
the SPIF bit to abort the current request. Additional interrupt requests during servicing
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USER’S MANUAL
can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not abort
a current request.
There are two recommended methods of exiting wraparound mode: clearing the
WREN bit or setting the HALT bit in SPCR3. Exiting wraparound mode by clearing
SPE is not recommended, as clearing SPE may abort a serial transfer in progress. The
QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue
after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then
stops executing commands. After the QSPI stops, SPE can be cleared.
6.3.5.3 Slave Mode
Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the
QSPI is unable to initiate serial transfers. Transfers are initiated by an external bus
master. Slave mode is typically used on a multi-master SPI bus. Only one device can
be bus master (operate in master mode) at any given time.
Before QSPI operation is initiated, QSM register PQSPAR must be written to assign
necessary pins to the QSPI. The pins necessary for slave mode operation are MISO
and MOSI, SCK, and PCS0/SS. MISO is used for serial data output in slave mode, and
MOSI is used for serial data input. Either or both may be necessary, depending on the
particular application. SCK is the serial clock input in slave mode. Assertion of the ac-
tive-low slave select signal (SS) initiates slave mode operation.
6
Before slave mode operation is initiated, DDRQS must be written to direct data flow
on the QSPI pins used. Configure the MOSI, SCK and PCS0/SS pins as inputs. The
MISO pin must be configured as an output.
After pins are assigned and configured, write data to be transmitted into transmit RAM.
Command RAM is not used in slave mode and does not need to be initialized. Unused
portions of QSPI RAM can be used by the CPU as general-purpose RAM. Initialize the
queue pointers as appropriate.
When SPE is set and MSTR is clear, a low state on the slave select (PCS0/SS) pin
begins slave mode operation at the address indicated by NEWQP. Data that is re-
ceived is stored at the pointer address in receive RAM. Data is simultaneously loaded
into the data serializer from the pointer address in transmit RAM and transmitted.
Transfer is synchronized with the externally generated SCK. The CPHA and CPOL
bits determine on which SCK edge to latch incoming data from the MISO pin and to
drive outgoing data from the MOSI pin.
Because the command control segment is not used, the command control bits and pe-
ripheral chip-select codes have no effect in slave mode operation. The PCS0/SS pin
is used only as an input.
The SPBR, DT and DSCK bits are not used in slave mode. The QSPI drives neither
the clock nor the chip-select pins and thus cannot control clock rate or transfer delay.
Because the BITSE option is not available in slave mode, the BITS field specifies the
number of bits to be transferred for all transfers in the queue. When the number of bits
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designated by BITS has been transferred, the QSPI stores the working queue pointer
value in CPTQP, increments the working queue pointer, and loads new transmit data
from transmit RAM into the data serializer. The working queue pointer address is used
the next time PCS0/SS is asserted, unless the CPU writes to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If
SS goes high before the number of bits specified by the BITS field is transferred, the
QSPI resumes operation at the same pointer address the next time SS is asserted.
The maximum value that the BITS field can have is 16. If more than 16 bits are trans-
mitted before SS is negated, pointers are incremented and operation continues. The
QSPI transmits as many bits as it receives at each queue address, until the BITS value
is reached or SS is negated. SS does not need to go high between transfers as the
QSPI transfers data until reaching the end of the queue, whether SS remains low or is
toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
6.3.5.4 Slave Wraparound Mode
6
Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can
wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the
state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master
wraparound operation.
6.3.6 Peripheral Chip Selects
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS bits in the
command. More than one chip-select signal can be asserted at a time, and more than
one external device can be connected to each PCS pin, provided proper fanout is ob-
served. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode
serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault oc-
curs.
To set up a chip-select function, set the appropriate bit in PQSPAR, then configure the
chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the
bit in PORTQS that corresponds to the chip-select pin determines the base state of
the chip-select signal. If base state is zero, chip-select assertion must be active high
(PCS bit in command RAM must be set); if base state is one, assertion must be active
low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during re-
set. If no new data is written to PORTQS before pin assignment and configuration as
an output, base state of chip-select signals is zero and chip-select pins are configured
for active-high operation.
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6.4 Serial Communication Interface
The serial communication interface (SCI) communicates with external devices through
an asynchronous serial bus. The SCI uses a standard nonreturn to zero (NRZ) trans-
mission format. The SCI is fully compatible with other Motorola SCI systems, such as
those in M68HC11 and M68HC05 devices. Figure 6-7 is a block diagram of the SCI
transmitter; Figure 6-8 is a block diagram of the SCI receiver.
6.4.1 SCI Registers
The SCI programming model includes the QSM global and pin control registers, and
four SCI registers. There are two SCI control registers (SCCR0 and SCCR1), one sta-
tus register (SCSR), and one data register (SCDR). Refer to APPENDIX D REGIS-
TER SUMMARY for register bit and field definition.
6.4.1.1 Control Registers
SCCR0 contains the baud rate selection field. Baud rate must be set before the SCI is
enabled. The CPU can read and write this register at any time.
SCCR1 contains a number of SCI configuration parameters, including transmitter and
receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU
can read and write this register at any time. The SCI can modify the RWU bit under
certain circumstances.
6
Changing the value of SCI control bits during a transfer operation may disrupt opera-
tion. Before changing register values, allow the SCI to complete the current transfer,
then disable the receiver and transmitter.
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(WRITE-ONLY)
TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
MDDR7
MDDR5
TxD
10 (11) - BIT
Tx SHIFT REGISTER
PIN BUFFER
AND CONTROL
H (8)
7
6
5
4
3
2
1
0
L
PARITY
GENERATOR
FORCE PIN
DIRECTION
(OUT)
TRANSMITTER
CONTROL LOGIC
6
15
SCCR1 (CONTROL REGISTER 1)
0
15
SCSR (STATUS REGISTER)
0
TDRE
TC
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
68300 SCI TX BLOCK
Figure 6-7 SCI Transmitter Block Diagram
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RECEIVER
BAUD RATE
CLOCK
÷16
10 (11) - BIT
Rx SHIFT REGISTER
DATA
RECOVERY
RxD
PIN BUFFER
H (8)
7
6
5
4
3
2
1
0 L
MSB
ALL ONES
PARITY
DETECT
WAKEUP
LOGIC
15
SCCR1 (CONTROL REGISTER 1)
0
6
SCDR Rx BUFFER
(READ-ONLY)
15
SCSR (STATUS REGISTER)
0
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
68300 SCI RX BLOCK
Figure 6-8 SCI Receiver Block Diagram
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6.4.1.2 Status Register
The SCI status register (SCSR) contains flags that show SCI operating conditions.
These flags are cleared either by SCI hardware or by a read/write sequence. In gen-
eral, flags are cleared by reading the SCSR, then reading (receiver status bits) or writ-
ing (transmitter status bits) the SCDR. A long-word read can consecutively access
both the SCSR and SCDR. This action clears receive status flag bits that were set at
the time of the read, but does not clear TDRE or TC flags.
If an internal SCI signal for setting a status bit comes after the CPU has read the as-
serted status bits, but before the CPU has written or read the SCDR, the newly set sta-
tus bit is not cleared. The SCSR must be read again with the bit set, and the SCDR
must be written or read before the status bit is cleared.
Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit
already set in either byte is cleared on a subsequent read or write of the SCDR.
6.4.1.3 Data Register
The SCDR contains two data registers at the same address. The RDR is a read-only
register that contains data received by the SCI serial interface. The data comes into
the receive serial shifter and is transferred to the RDR. The TDR is a write-only register
that contains data to be transmitted. The data is first written to the TDR, then trans-
ferred to the transmit serial shifter, where additional format bits are added before trans-
mission. R[7:0]/T[7:0] contain either the first eight data bits received when the SCDR
is read, or the first eight data bits to be transmitted when the SCDR is written. R8/T8
are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit
operation, they have no meaning or effect.
6
6.4.2 SCI Pins
Two unidirectional pins, TXD (transmit data) and RXD (receive data), are associated
with the SCI. TXD can be used by the SCI or for general-purpose I/O. Function is as-
signed by the port QS pin assignment register (PQSPAR). The receive data (RXD) pin
is dedicated to the SCI. Table 6-4 shows SCI pin function.
Table 6-4 SCI Pin Function
Pin Names
Mnemonics
Mode
Function
Receive Data
RXD
Receiver Disabled
Receiver Enabled
Transmitter Disabled
Transmitter Enabled
Not Used
Serial Data Input to SCI
General-Purpose I/O
Transmit Data
TXD
Serial Data Output from SCI
6.4.3 SCI Operation
SCI status flags in the SPSR support polled operation, or interrupt-driven operation
can be employed by the interrupt enable bits in SCCR1.
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6.4.3.1 Definition of Terms
Bit-Time — The time required to transmit or receive one bit of data; one cycle of the
baud frequency.
Start Bit — One bit-time of logic zero that indicates the beginning of a data frame. A
start bit must begin with a one-to-zero transition and be preceded by at least three re-
ceive time (RT) samples of logic one.
Stop Bit — One bit-time of logic one that indicates the end of a data frame.
Frame — A complete unit of serial information. The SCI can use 10-bit or 11-bit
frames.
Data Frame — A start bit, a specified number of data or information bits, and at least
one stop bit.
Idle Frame — A frame that consists of consecutive ones. An idle frame has no start bit.
Break Frame — A frame that consists of consecutive zeros. A break frame has no stop
bits.
6
6.4.3.2 Serial Formats
All data frames must have a start bit and at least one stop bit. Receiving and transmit-
ting devices must use the same data frame format. The SCI provides hardware sup-
port for both ten-bit and eleven-bit frames. The serial mode (M) bit in SCI control
register one (SCCR1) specifies the number of bits per frame.
The most common ten-bit data frame format for NRZ serial interface consists of one
start bit, eight data bits (LSB first), and one stop bit. The most common eleven-bit data
frame contains one start bit, eight data bits, a parity or control bit, and one stop bit.
Ten-bit and eleven-bit frames are shown in Table 6-5.
Table 6-5 Serial Frame Formats
10-Bit Frames
Start
Data
Parity/Control
Stop
1
1
1
7
7
8
—
1
2
1
1
—
11-Bit Frames
Start
Data
Parity/Control
Stop
1
1
7
8
1
1
2
1
6.4.3.3 Baud Clock
The SCI baud clock is programmed by writing a 13-bit value to the baud rate (SCBR)
field in SCI control register zero (SCCR0). Baud clock is derived from the MCU system
clock by a modulus counter. Writing a value of zero to SCBR disables the baud rate
generator. Baud clock rate is calculated as follows:
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System Clock
SCI Baud Clock Rate = ------------------------------------
32 × SCBR
where SCBR is in the range {1, 2, 3,..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchro-
nize with an incoming data stream. The SCI baud clock generator produces a receive
time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The
SCI determines the position of bit boundaries from transitions within the received
waveform, and adjusts sampling points to the proper positions within the bit period.
6.4.3.4 Parity Checking
The parity type (PT) bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity.
PT affects received and transmitted data. The parity enable (PE) bit in SCCR1 deter-
mines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is
set, the MSB of the data in a frame is used for the parity function. For transmitted data,
a parity bit is generated; for received data, the parity bit is checked. When parity check-
ing is enabled, the parity flag (PF) in the SCI status register (SCSR) is set if a parity
error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size. Table 6-6 shows possible data and parity formats.
6
Table 6-6 Effect of Parity Checking on Data Size
M
0
0
1
1
PE
0
Result
8 Data Bits
1
7 Data Bits, 1 Parity Bit
9 Data Bits
0
1
8 Data Bits, 1 Parity Bit
6.4.3.5 Transmitter Operation
The transmitter consists of a serial shifter and a parallel data register (TDR) located in
the SCI data register (SCDR). The serial shifter cannot be directly accessed by the
CPU. The transmitter is double-buffered, which means that data can be loaded into
the TDR while other data is shifted out. The transmitter enable (TE) bit in SCCR1 en-
ables (TE = 1) and disables (TE = 0) the transmitter.
Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1,
or TE = 0 and transmission in progress). Wired-OR operation should be specified
when more than one transmitter is used on the same SCI bus. The wired-OR mode
select bit (WOMS) in SCCR1 determines whether TXD is an open-drain (wired-OR)
output or a normal CMOS output. An external pull-up resistor on the TXD pin is nec-
essary for wired-OR operation. WOMS controls TXD function whether the pin is used
for SCI transmissions (TE = 1) or as a general-purpose I/O pin.
Data to be transmitted is written to TDR, then transferred to the serial shifter. The
transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When
TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to
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TDR again overwrites the data. TDRE is set when the data in TDR is transferred to the
shifter. Before new data can be written to TDR, however, the processor must clear
TDRE by writing to SCSR. If new data is written to TDR without first clearing TDRE,
the data will not be transmitted.
The transmission complete (TC) flag in SCSR shows transmitter shifter state. When
TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is
not automatically cleared. The processor must clear it by first reading SCSR while TC
is set, then writing new data to TDR.
The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame
is transmitted as a preamble to the following data frame. If TC = 0, the current opera-
tion continues until the final bit in the frame is sent, then the preamble is transmitted.
The TC bit is set at the end of preamble transmission.
The send break (SBK) bit in SCCR1 is used to insert break frames in a transmission.
A nonzero integer number of break frames is transmitted while SBK is set. Break trans-
mission begins when SBK is set, and ends with the transmission in progress at the
time either SBK or TE are cleared. If SBK is set while a transmission is in progress,
that transmission finishes normally before the break begins. To assure the minimum
break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of
break transmission. After break transmission, at least one bit-time of logic level one
(mark idle) is transmitted to ensure that a subsequent start bit can be detected.
6
If TE remains set, after all pending idle, data and break frames are shifted out, TDRE
and TC are set and TXD is held at logic level one (mark).
When TE is cleared, the transmitter is disabled after all pending idle, data and break
frames are transmitted. The TC flag is set, and the TXD pin reverts to control by PQS-
PAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing
data in the buffer, do not clear TE until TDRE is set.
Some serial communication systems require a mark on the TXD pin even when the
transmitter is disabled. Configure the TXD pin as an output (DDRQS), then write a one
to PORTQS bit 7. When the transmitter releases control of the TXD pin, it reverts to
driving a logic one output.
To insert a delimiter between two messages, to place nonlistening receivers in wakeup
mode between transmissions, or to signal a retransmission by forcing an idle line, clear
and then set TE before data in the serial shifter has shifted out. The transmitter finishes
the transmission, then sends a preamble. After the preamble is transmitted, if TDRE
is set, the transmitter will mark idle. Otherwise, normal transmission of the next se-
quence will begin.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCR1. Service routines can load the last byte of data in a sequence into the TDR,
then terminate the transmission when a TDRE interrupt occurs.
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6.4.3.6 Receiver Operation
The receiver enable (RE) bit in SCCR1 enables (RE = 1) and disables (RE = 0) the
transmitter. The receiver contains a receive serial shifter and a parallel receive data
register (RDR) located in the SCI data register (SCDR). The serial shifter cannot be
directly accessed by the CPU. The receiver is double-buffered, allowing data to be
held in RDR while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for
each bit-time. This state machine controls when the bit processor logic is to sample
the RXD pin and also controls when data is to be passed to the receive serial shifter.
A receive time (RT) clock is used to control sampling and synchronization. Data is
shifted into the receive serial shifter according to the most recent synchronization of
the RT clock with the incoming data stream. From this point on, data movement is syn-
chronized with the MCU system clock. Operation of the receiver state machine is de-
tailed in the QSM Reference Manual (QSMRM/AD).
The number of bits shifted in by the receiver depends on the serial format. However,
all frames must end with at least one stop bit. When the stop bit is received, the frame
is considered to be complete, and the received data in the serial shifter is transferred
to the RDR. The receiver data register flag (RDRF) is set when the data is transferred.
6
Noise errors, parity errors, and framing errors can be detected while a data stream is
being received. Although error conditions are detected as bits are received, the noise
flag (NF), the parity flag (PF), and the framing error (FE) flag in SCSR are not set until
data is transferred from the serial shifter to RDR.
RDRF must be cleared before the next transfer from the shifter can take place. If
RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR)
flag in the SCSR is set. OR indicates that the CPU needs to service RDR faster. When
OR is set, the data in RDR is preserved, but the data in the serial shifter is lost. Be-
cause framing, noise, and parity errors are detected while data is in the serial shifter,
FE, NF, and PF cannot occur at the same time as OR.
When the CPU reads the SCSR and the SCDR in sequence, it acquires status and
data, and also clears the status flags. Reading the SCSR acquires status and arms
the clearing mechanism. Reading the SCDR acquires data and clears the SCSR.
When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set.
Because receiver status flags are set at the same time as RDRF, they do not have
separate interrupt enables.
6.4.3.7 Idle-Line Detection
During a typical serial transmission, frames are transmitted isochronously and no idle
time occurs between frames. Even when all the data bits in a frame are logic ones, the
start bit provides one logic zero bit-time during the frame. An idle line is a sequence of
contiguous ones equal to the current frame size. Frame size is determined by the state
of the M bit in SCCR1.
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The SCI receiver has both short and long idle-line detection capability. Idle-line detec-
tion is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of
detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bit-
times whenever they occur. Short detection provides the earliest possible recognition
of an idle line condition, because the stop bit and contiguous logic ones before and
after it are counted. For long idle-line detection, the receiver counts logic ones after
the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, CPU overhead can cause a bit-time of logic level one to occur
between frames. This bit-time does not affect content, but if it occurs after a frame of
ones when short detection is enabled, the receiver flags an idle line.
When the idle line interrupt enable (ILIE) bit in SCCR1 is set, an interrupt request is
generated when the IDLE flag is set. The flag is cleared by reading SCSR and SCDR
in sequence. IDLE is not set again until after at least one frame has been received
(RDRF = 1). This prevents an extended idle interval from causing more than one in-
terrupt.
6
6.4.3.8 Receiver Wakeup
The receiver wakeup function allows a transmitting device to direct a transmission to
a single receiver or to a group of receivers by sending an address frame at the start of
a message. Hardware activates each receiver in a system under certain conditions.
Resident software must process address information and enable or disable receiver
operation.
A receiver is placed in wakeup mode by setting the receiver wakeup (RWU) bit in
SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although
the CPU can clear RWU, it is normally cleared by hardware during wakeup.
The WAKE bit in SCCR1 determines which type of wakeup is used. When WAKE = 0,
idle-line wakeup is selected. When WAKE = 1, address-mark wakeup is selected. Both
types require a software-based device addressing and recognition scheme.
Idle-line wakeup allows a receiver to sleep until an idle line is detected. When an idle-
line is detected, the receiver clears RWU and wakes up. The receiver waits for the first
frame of the next transmission. The byte is received normally, transferred to register
RDR, and the RDRF flag is set. If software does not recognize the address, it can set
RWU and put the receiver back to sleep. For idle-line wakeup to work, there must be
a minimum of one frame of idle line between transmissions. There must be no idle time
between frames within a transmission.
Address-mark wakeup uses a special frame format to wake up the receiver. When the
MSB of an address-mark frame is set, that frame contains address information. The
first frame of each transmission must be an address frame. When the MSB of a frame
is set, the receiver clears RWU and wakes up. The byte is received normally, trans-
ferred to register RDR, and the RDRF flag is set. If software does not recognize the
address, it can set RWU and put the receiver back to sleep. Address-mark wakeup al-
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lows idle time between frames and eliminates idle time between transmissions. How-
ever, there is a loss of efficiency because of an additional bit-time per frame.
6.4.3.9 Internal Loop
The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When
LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. TXD is
asserted (idle line). Both transmitter and receiver must be enabled before entering
loop mode.
6.5 QSM Initialization
After reset, the QSM remains in an idle state until initialized. A general sequence guide
for initialization follows.
A. Global
1. Configuration register (QSMCR)
a. Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
2. Interrupt vector and interrupt level registers (QIVR and QILR)
a. Write QSPI/SCI interrupt vector into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
3. Port data and data direction registers (PORTQS and DDRQS)
a. Write a data word to PORTQS.
6
b. Establish direction of QSM pins used for I/O by writing to DDRQS.
4. Assign pin functions by writing to the pin assignment register (PQSPAR)
B. Queued Serial Peripheral Interface
1. Write appropriate values to QSPI command RAM.
2. QSPI control register zero (SPCR0)
a. Write a transfer rate value into the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation (BIT).
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
3. QSPI control register one (SPCR1)
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
4. QSPI control register two (SPCR2)
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wraparound (WREN).
d. Write wraparound address into the WRTO field.
e. Enable or disable QSPI flag interrupt (SPIFIE).
5. QSPI control register three (SPCR3)
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
6. To enable the QSPI, set the SPE bit in SPCR1.
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C. Serial Communication Interface (SCI)
1. SCI control register zero (SCCR0)
a. Write a transfer rate (baud) value into the BR field.
2. SCI control register one (SCCR1)
a. Select serial mode (M)
b. Enable use (PE) and type (PT) of parity check.
c. Select use (RWU) and type (WAKE) of receiver wakeup.
d. Enable idle-line detection (ILT) and interrupt (ILIE).
e. Enable or disable wired-OR operation (WOMS).
f. Enable or disable break transmission (BK).
3. To receive
a. Set the receiver (RE) and receiver interrupt (RIE) bits in SCCR1.
4. To transmit
a. Set transmitter (TE) and transmitter interrupt (TIE).
b. Clear the transmitter data register empty (TDRE) and transmit complete
(TC) indicators by reading the serial communication interface status reg-
ister (SCSR).
c. Write transmit data to the serial communication data register (SCDR).
6
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SECTION 7GENERAL-PURPOSE TIMER
This section is an overview of GPT function. Refer to the GPT Reference Manual (GP-
TRM/AD) for complete information about the GPT module.
7.1 General
The 11-channel general-purpose timer (GPT) is used in systems where a moderate
level of CPU control is required. The GPT consists of a capture/compare unit, a pulse
accumulator, and two pulse-width modulators. A bus interface unit connects the GPT
to the intermodule bus (IMB).
The capture/compare unit features three input capture channels, four output compare
channels, and one channel that can be selected as an input capture or output compare
channel. These channels share a 16-bit free-running counter which derives its clock
from a nine-stage prescaler or from the external clock input signal, PCLK.
7
Pulse accumulator channel logic includes an 8-bit counter; the pulse accumulator can
operate in either event counting mode or gated time accumulation mode.
Pulse-width modulator outputs are periodic waveforms whose duty cycles can be in-
dependently selected and modified by user software. The PWM circuits share a 16-bit
free-running counter that can be clocked by the same nine-stage prescaler used by
the capture/compare unit or by the PCLK input.
All GPT pins can also be used for general-purpose input/output. The input capture and
output compare pins form a bidirectional 8-bit parallel port (PORTGP). PWM pins are
outputs only. PAI and PCLK pins are inputs only.
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OC1/PGP3
IC1/PGP0
IC2/PGP1
IC3/PGP2
OC2/OC1/PGP4
OC3/OC1/PGP5
OC4/OC1/PGP6
IC4/OC5/OC1/PGP7
CAPTURE/COMPARE UNIT
PULSE ACCUMULATOR
PRESCALER
PAI
PCLK
PWMA
PWMB
PWM UNIT
BUS INTERFACE
IMB
7
GPT BLOCK
Figure 7-1 GPT Block Diagram
7.2 GPT Registers and Address Map
The GPT programming model consists of a configuration register (GPTMCR), parallel
I/O registers (DDRGP, PORTGP), capture/compare registers (TCNT, TCTL1, TCTL2,
TIC[1:3], TOC[1:4], TI4/O5, CFORC), pulse accumulator registers (PACNT, PACTL),
pulse-width modulation registers (PWMA, PWMB, PWMC, PWMCNT, PWMBUFA,
PWMBUFB), status registers (TFLG1, TFLG2) and interrupt control registers (TMSK1,
TMSK2). Functions of the module configuration register are discussed in 7.3 Special
Modes of Operation and 7.4 Polled and Interrupt-Driven Operation. Other register
functions are discussed in the appropriate sections.
All registers can be accessed using byte or word operations. Certain capture/compare
registers and pulse-width modulation registers must be accessed by word operations
to ensure coherency. If byte accesses are used to read a register such as the timer
counter register (TCNT), there is a possibility that data in the byte not being accessed
will change while the other byte is read. Both bytes must be accessed at the same
time.
The modmap (MM) bit in the system integration module configuration register (SIM-
CR) defines the most significant bit (ADDR23) of the IMB address for each register in
the MCU.
Refer to APPENDIX D REGISTER SUMMARY for a GPT address map and register
bit/field descriptions. SECTION 4 SYSTEM INTEGRATION MODULE contains more
information about how the state of MM affects the system.
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7.3 Special Modes of Operation
The GPT module configuration register (GPTMCR) module configuration register
(GPTMCR) is used to control special GPT operating modes. These include low-power
stop mode, freeze mode, single-step mode, and test mode. Normal GPT operation can
be polled or interrupt-driven. Refer to 7.4 Polled and Interrupt-Driven Operation for
more information.
7.3.1 Low-Power Stop Mode
Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop
mode the system clock to the module is turned off. The clock remains off until STOP
is negated or a reset occurs. All counters and prescalers within the timer stop counting
while the STOP bit is set. Only the module configuration register (GPTMCR) and the
interrupt configuration register (ICR) should be accessed while in the stop mode. Ac-
cesses to other GPT registers cause unpredictable behavior. Low-power stop can also
be used to disable module operation during debugging.
7.3.2 Freeze Mode
The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by
the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the
CPU enters background debugging mode. At the present time, FRZ1 has no effect;
setting FRZ0 causes the GPT to enter freeze mode. Refer to SECTION 5 CENTRAL
PROCESSING UNIT for more information on background debugging mode.
7
Freeze mode freezes the current state of the timer. The prescaler and the pulse accu-
mulator do not increment and changes to the pins are ignored (input pin synchronizers
are not clocked). All of the other timer functions that are controlled by the CPU will op-
erate normally; for example, registers can be written to change pin directions, force
output compares, and read or write I/O pins.
While the FREEZE signal is asserted, the CPU has write access to registers and bits
that are normally read-only, or write-once. The write-once bits can be written to as of-
ten as needed. The prescaler and the pulse accumulator remain stopped and the input
pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM),
the FRZ0 bit is cleared, or the MCU is reset.
Activities that are in progress prior to FREEZE assertion are completed. For example,
if an input edge on an input capture pin is detected just as the FREEZE signal is as-
serted, the capture occurs and the corresponding interrupt flag is set.
7.3.3 Single-Step Mode
Two bits in GPTMCR support GPT debugging without using BDM. When the STOPP
bit is asserted, the prescaler and the pulse accumulator stop counting and changes at
input pins are ignored. Reads of the GPT pins return the state of the pin when STOPP
was set. After STOPP is set, the INCP bit can be set to increment the prescaler and
clock the input synchronizers once. The INCP bit is self-negating after the prescaler is
incremented. INCP can be set repeatedly. The INCP bit has no effect when the
STOPP bit is not set.
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7.3.4 Test Mode
Test mode is used during Motorola factory testing. The GPT has no dedicated test-
mode control register; all GPT testing is done under control of the system integration
module.
7.4 Polled and Interrupt-Driven Operation
Normal GPT function can be polled or interrupt-driven. All GPT functions have an as-
sociated status flag and an associated interrupt. The timer interrupt flag registers
(TFLG1 and TFLG2) contain status flags used for polled and interrupt-driven opera-
tion. The timer mask registers (TMSK1 and TMSK2) contain interrupt control bits. Con-
trol routines can monitor GPT operation by polling the status registers. When an event
occurs, the control routine transfers control to a service routine that handles that event.
If interrupts are enabled for an event, the GPT requests interrupt service when the
event occurs. Using interrupts does not require continuously polling the status flags to
see if an event has taken place. However, status flags must be cleared after an inter-
rupt is serviced, in order to disable the interrupt request.
7.4.1 Polled Operation
7
When an event occurs in the GPT, that event sets a status flag in TFLG1 or TFLG2.
The GPT sets the flags; they cannot be set by the CPU. TFLG1 and TFLG2 are 8-bit
registers that can be accessed individually or as one 16-bit register. The registers are
initialized to zero at reset. Table 7-1 shows status flag assignment.
Table 7-1 GPT Status Flags
Flag
Mnemonic
Register
Assignment
Source
IC1F
IC2F
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG2
TFLG2
TFLG2
Input Capture 1
Input Capture 2
IC3F
Input Capture 3
OC1F
OC2F
OC3F
OC4F
I4/O5F
TOF
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
PAOVF
PAIF
Pulse Accumulator Overflow
Pulse Accumulator Input
For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2
in the same bit position. If a mask bit is set and an associated event occurs, a hardware
interrupt request is generated.
To re-enable a status flag after an event occurs, the status flags must be cleared. Sta-
tus registers are cleared in a particular sequence. The register must first be read for
set flags, then zeros must be written to the flags that are to be cleared. If a new event
occurs between the time that the register is read and the time that it is written, the as-
sociated flag is not cleared.
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7.4.2 GPT Interrupts
The GPT has 11 internal sources that can cause it to request interrupt service (refer
to Table 7-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.
TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one
16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and
TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.
TMSK2 also controls the operation of the timer prescaler. Refer to 7.7 Prescaler for
more information.
The value of the interrupt level (IRL) field in the interrupt control register (ICR) deter-
mines the priority of GPT interrupt requests. IRL values correspond to MCU interrupt
request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request signal; IRQ1 is
the lowest-priority signal. A value of %111 causes IRQ7 to be asserted when a GPT
interrupt request is made; lower field values cause corresponding lower-priority inter-
rupt request signals to be asserted. Setting field value to %000 disables interrupts.
Table 7-2 GPT Interrupt Sources
Name
Source
Number
Source
Vector
Number
—
IC1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Adjusted Channel
Input Capture 1
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
7
IC2
Input Capture 2
IC3
Input Capture 3
OC1
OC2
OC3
OC4
IC4/OC5
TO
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
PAOV
PAI
Pulse Accumulator Overflow
Pulse Accumulator Input
The CPU32 recognizes only interrupt request signals of a priority greater than the sta-
tus register interrupt priority (IP) mask value. When the CPU acknowledges an inter-
rupt request, the priority of the acknowledged request is written to the IP mask and
driven out on the IMB address lines.
When the IP mask value driven out on the address lines is the same as the IRL value,
the GPT contends for arbitration priority. GPT arbitration priority is determined by the
value of the IARB field in GPTMCR. Each MCU module that can make interrupt re-
quests must be assigned a nonzero IARB value in order to implement an arbitration
scheme. Arbitration is performed by means of serial assertion of IARB field bit values.
When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge
cycle by placing an interrupt vector number on the data bus. The vector number is
used to calculate displacement into the CPU32 exception vector table. Vector num-
bers are formed by concatenating the value in the ICR IVBA field with a 4-bit value
supplied by the GPT when an interrupt request is made. Hardware prevents the vector
number from changing while it is being driven out on the IMB. Vector number assign-
ment is shown in Table 7-2.
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At reset, IVBA is initialized to $0. To enable interrupt-driven timer operation, the upper
nibble ($4–$F) of a user-defined vector number ($40–$FF) must be written to IVBA,
and interrupt handler routines must be located at the addresses pointed to by the cor-
responding vector. Note that IVBA must be written before GPT interrupts are enabled,
or the GPT could supply a vector number ($00 to $0F) that corresponds to an assigned
or reserved exception vector.
The internal GPT interrupt priority hierarchy is shown in Table 7-2. The lower the in-
terrupt source number, the higher the priority. A single GPT interrupt source can be
given priority over all other GPT interrupt sources by assigning the priority adjust field
(PAB) in the ICR a value equal to its source number.
Interrupt requests are asserted until associated status flags are cleared. Status flags
must be cleared in a particular sequence. The status register must first be read for set
flags, then zeros must be written to the flags that are to be cleared. If a new event oc-
curs between the time that the register is read and the time that it is written, the asso-
ciated flag is not cleared.
Refer to SECTION 5 CENTRAL PROCESSING UNIT and SECTION 4 SYSTEM IN-
TEGRATION MODULE for more information about exceptions and interrupts.
7
7.5 Pin Descriptions
The GPT uses 12 pins. Each pin can perform more than one function. Descriptions of
GPT pins divided into functional groups follow.
7.5.1 Input Capture Pins (IC[1:3])
Each of these pins is associated with a single GPT input capture function. Each pin
has hysteresis. Any pulse longer than two system clocks is guaranteed to be valid and
any pulse shorter than one system clock is ignored. Each pin has an associated 16-bit
capture register that holds the captured counter value. These pins can also be used
for general-purpose I/O. Refer to 7.8.2 Input Capture Functions for more informa-
tion.
7.5.2 Input Capture/Output Compare Pin (IC4/OC5)
This pin can be configured for use by either an input capture or an output compare
function. It has an associated 16-bit register that is used for holding either the input
capture value or the output match value. When used for input capture the pin has the
same hysteresis as other input capture pins. The pin can be used for general-purpose
I/O. Refer to 7.8.2 Input Capture Functions and 7.8.3 Output Compare Functions
for more information.
7.5.3 Output Compare Pins (OC[1:4])
These pins are used for GPT output compare functions. Each pin has an associated
16-bit compare register and a 16-bit comparator. Pins OC2, OC3, and OC4 are asso-
ciated with a specific output compare function. The OC1 function can affect the output
of all compare pins. If the OC1 pin is not needed for an output compare function it can
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be used to output the clock selected for the timer counter register. Any of these pins
can also be used for general-purpose I/O. Refer to 7.8.3 Output Compare Functions
for more information.
7.5.4 Pulse Accumulator Input Pin (PAI)
The PAI pin connects a discrete signal to the pulse accumulator for timed or gated
pulse accumulation. PAI has hysteresis. Any pulse longer than two system clocks is
guaranteed to be valid and any pulse shorter than one system clock is ignored. It can
be used as a general-purpose input pin. Refer to 7.10 Pulse Accumulator for more
information.
7.5.5 Pulse-Width Modulation (PWMA, PWMB)
PWMA and PWMB pins carry pulse-width modulator outputs. The modulators can be
programmed to generate a periodic waveform of variable frequency and duty cycle.
PWMA can be used to output the clock selected as the input to the PWM counter.
These pins can also be used for general-purpose output. Refer to 7.11 Pulse-Width
Modulation Unit for more information.
7
7.5.6 Auxiliary Timer Clock Input (PCLK)
PCLK connects an external clock to the GPT. The external clock can be used as the
clock source for the capture/compare unit or the PWM unit in place of one of the pres-
caler outputs. PCLK has hysteresis. Any pulse longer than two system clocks is guar-
anteed to be valid and any pulse shorter than one system clock is ignored. This pin
can also be used as a general-purpose input pin. Refer to 7.7 Prescaler for more in-
formation.
7.6 General-Purpose I/O
Any GPT pin can be used for general-purpose I/O when it is not used for another pur-
pose. Capture/compare pins are bidirectional, others can be used only for output or
input. I/O direction is controlled by a data direction bit in the port GP data direction reg-
ister (DDRGP).
Parallel data is read from and written to the port GP data register (PORTGP). Pin data
can be read even when pins are configured for a timer function. Data read from PORT-
GP always reflects the state of the external pin, while data written to PORTGP may
not always affect the external pin.
Data written to PORTGP does not immediately affect pins used for output compare
functions, but the data is latched. When an output compare function is disabled, the
last data written to PORTGP is driven out on the associated pin if it is configured as
an output. Data written to PORTGP can cause input captures if the corresponding pin
is configured for input capture function.
The pulse accumulator input (PAI and the external clock input (PCLK) pins provide
general-purpose input. The state of these pins can be read by accessing the PAIS and
PCLKS bits in the pulse accumulator control register (PACTL).
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Pulse-width modulation A and B (PWMA/PWMB) output pins can serve as general-
purpose outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in
the compare force (CFORC) and PWM control (PWMC) registers, respectively, control
their operation.
7.7 Prescaler
Capture/compare and PWM units have independent 16-bit free-running counters as a
main timing component. These counters derive their clocks from the prescaler or from
the PCLK input. Figure 7-2 is a prescaler block diagram.
In the prescaler, the system clock is divided by a nine-stage divider chain. Prescaler
outputs equal to system clock divided by 2, 4, 8, 16, 32, 64, 128, 256 and 512 are pro-
vided. Connected to these outputs are two multiplexers, one for the capture/compare
unit, the other for the PWM unit.
Multiplexers can each select one of seven prescaler taps or an external input from the
PCLK pin. Multiplexer output for the timer counter (TCNT) is selected by bits CPR[2:0]
in timer interrupt mask register 2 (TMSK2). Multiplexer output for the PWM counter
(PWMCNT) is selected by bits PPR[2:0] in PWM control register C (PWMC).
7
After reset, the GPT is configured to use system clock divided by four for TCNT and
system clock divided by two for PWMCNT. Initialization software can change the divi-
sion factor. The PPR bits can be written at any time but the CPR bits can only be writ-
ten once after reset unless the GPT is in test or freeze mode.
The prescaler can be read at any time. In freeze mode the prescaler can also be writ-
ten. Word accesses must be used to ensure coherency. If coherency is not needed
byte accesses can be used. The prescaler value is contained in bits [8:0] while bits
[15:9] are unimplemented and are read as zeros.
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SYSTEM CLOCK
DIVIDER
÷512
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
TO PULSE ACCUMULATOR
EXT.
CPR2 CPR1 CPR0
÷256
÷128
÷64
÷32
÷16
÷8
TO CAPTURE/
COMPARE
TIMER
SELECT
÷4
EXT.
7
÷128
÷64
÷32
÷16
÷8
TO
PWM UNIT
SELECT
÷4
÷2
EXT.
PCLK
PIN
SYNCHRONIZER AND
DIGITAL FILTER
GPT PRESCALER BLOCK
PPR2 PPR1 PPR0
Figure 7-2 Prescaler Block Diagram
Multiplexer outputs (including the PCLK signal) can be connected to external pins) can
be connected to external pins. The CPROUT bit in the TMSK2 register configures the
OC1 pin to output the TCNT clock and the PPROUT bit in the PWMC register config-
ures the PWMA pin to output the PWMC clock. CPROUT and PPROUT can be written
at any time. Clock signals on OC1 and PWMA do not have a 50% duty cycle. They
have the period of the selected clock but are high for only one system clock time.
The prescaler also supplies three clock signals to the pulse accumulator clock select
mux. These are the system clock divided by 512, the external clock signal from the
PCLK pin and the capture/compare clock signal.
7.8 Capture/Compare Unit
The capture/compare unit contains the timer counter (TCNT), the input capture (IC)
functions and the output compare (OC) functions. Figure 7-3 is a block diagram of the
capture/compare unit.
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PCLK
SYSTEM
CLOCK
PRESCALER–DIVIDE BY
4, 8, 16, 32, 64, 128, OR 256
TCNT (HI)
TCNT (LO)
TOI
9
16-BIT FREE-RUNNING
COUNTER
TOF
1 OF 8 SELECT
CPR2 CPR1 CPR0
INTERRUPT
REQUESTS
16-BIT TIMER BUS
TMSK1
IC1I
PIN
FUNCTIONS
TFLG1
1
2
3
4
5
6
7
8
PGP0
IC1
16-BIT LATCH CLK
IC1F
BIT-0
BIT-1
BIT-2
TIC1 (HI)
TIC1 (LO)
IC2I
IC3I
PGP1
IC2
16-BIT LATCH CLK
IC2F
TIC2 (HI)
TIC2 (LO)
PGP2
IC3
16-BIT LATCH CLK
IC3F
TIC3 (HI)
TIC3 (LO)
7
OC1I
OC2I
OC3I
OC4I
I4/O5I
CFORC
FOC1
=
16-BIT COMPARATOR
TOC1 (HI)
OC1F
OC2F
OC3F
OC4F
TOC1 (LO)
PGP3
OC1
BIT-3
BIT-4
BIT-5
BIT-6
BIT-7
=
16-BIT COMPARATOR
TOC2 (HI)
PGP4
OC2/
OC1
TOC2 (LO)
FOC2
FOC3
FOC4
FOC5
=
16-BIT COMPARATOR
TOC3 (HI)
PGP5
OC3/
OC1
TOC3 (LO)
=
16-BIT COMPARATOR
TOC4 (HI)
PGP6
OC4/
OC1
TOC4 (LO)
=
OC5
I4/O5F
16-BIT COMPARATOR
PGP7
IC4/
OC5/
OC1
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
IC4
PARALLEL
PORT PIN
CONTROL
FORCE
OUTPUT
COMPARE
STATUS
FLAGS
INTERRUPT
ENABLES
I4/O5
16/32 CC BLOCK
Figure 7-3 Capture/Compare Unit Block Diagram
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7.8.1 Timer Counter
The timer counter (TCNT) is the key timing component in the capture/compare unit.
The timer counter is a 16-bit free-running counter that starts counting after the proces-
sor comes out of reset. The counter cannot be stopped during normal operation. After
reset, the GPT is configured to use the system clock divided by four as the input to the
counter. The prescaler divides the system clock and provides selectable input fre-
quencies. User software can configure the system to use one of seven prescaler out-
puts or an external clock.
The counter can be read any time without affecting its value. Because the GPT is in-
terfaced to the IMB and the IMB supports a 16-bit bus, a word read gives a coherent
value. If coherency is not needed, byte accesses can be made. The counter is set to
$0000 during reset and is normally a read-only register. In test mode and freeze mode,
any value can be written to the timer counter.
When the counter rolls over from $FFFF to $0000, the timer overflow flag (TOF) in tim-
er interrupt flag register 2 (TFLG2) is set. An interrupt can be enabled by setting the
corresponding interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2).
Refer to 7.4.2 GPT Interrupts for more information.
7
7.8.2 Input Capture Functions
All GPT input capture functions use the same 16-bit timer counter (TCNT). Each input
capture pin has a dedicated 16-bit latch and input edge-detection/selection logic. Each
input capture function has an associated status flag, and can cause the GPT to make
an interrupt service request.
When a selected edge transition occurs on an input capture pin, the associated 16-bit
latch captures the content of TCNT and sets the appropriate status flag. An interrupt
request can be generated when the transition is detected.
Edge-detection logic consists of control bits that enable edge detection and select a
transition to detect. The EDGxA and EDGxB bits in timer control register 2 (TCTL2)
determine whether the input capture functions detect rising edges only, falling edges
only, or both rising and falling edges. Clearing both bits disables the input capture
function. Input capture functions operate independently of each other and can capture
the same TCNT value if individual input edges are detected within the same timer
count cycle.
Input capture interrupt logic includes a status flag, which indicates that an edge has
been detected, and an interrupt enable bit. An input capture event sets the ICxF bit in
the timer interrupt flag register 1 (TFLG1) and causes the GPT to make an interrupt
request if the corresponding ICxI bit is set in the timer interrupt mask register 1
(TMSK1). If the ICxI bit cleared, software must poll the status flag to determine that an
event has occurred. Refer to 7.4 Polled and Interrupt-Driven Operation for more in-
formation.
Input capture events are generally asynchronous to the timer counter. Because of this,
input capture signals are conditioned by a synchronizer and digital filter. Events are
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synchronized with the system clock so that latching of TCNT content and counter in-
crementation occur on opposite half-cycles of the system clock. Inputs have hystere-
sis. Capture of any transition longer than two system clocks is guaranteed; any
transition shorter than one system clock has no effect.
Figure 7-4 shows the relationship of system clock to synchronizer output. The value
latched into the capture register is the value of the counter several system clock cycles
after the transition that triggers the edge detection logic. There can be up to one clock
cycle of uncertainty in latching of the input transition. Maximum time is determined by
the system clock frequency.
The input capture register is a 16-bit register. A word access is required to ensure co-
herency. If coherency is not required, byte accesses can be used to read the register.
Input capture registers can be read at any time without affecting their values.
F (PH1)
SYS
CAPTURE/COMPARE
CLOCK
7
$0101
$0102
TCNT
EXTERNAL PIN
SYNCHRONIZER
OUTPUT
$0102
CAPTURE REGISTER
ICF FLAG
1153A
Figure 7-4 Input Capture Timing Example
An input capture occurs every time a selected edge is detected, even when the input
capture status flag is set. This means that the value read from the input capture regis-
ter corresponds to the most recent edge detected, which may not be the edge that
caused the status flag to be set.
7.8.3 Output Compare Functions
Each GPT output compare pin has an associated 16-bit compare register and a 16-bit
comparator. Each output compare function has an associated status flag, and can
cause the GPT to make an interrupt service request. Output compare logic is designed
to prevent false compares during data transition times.
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When the programmed content of an output compare register matches the value in
TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate in-
terrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match
occurs. Refer to 7.4.2 GPT Interrupts for more information.
Operation of output compare 1 differs from that of the other output compare functions.
OC1 control logic can be programmed to make state changes on other OC pins when
an OC1 match occurs. Control bits in the timer compare force register (CFORC) allow
for early forced compares.
7.8.3.1 Output Compare 1
Output compare 1 can affect any or all of OC[1:5] when an output match occurs. In
addition to allowing generation of multiple control signals from a single comparison op-
eration, this function makes it possible for two or more output compare functions to
control the state of a single OC pin. Output pulses as short as one timer count can be
generated in this way.
The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) con-
trol OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel
data port. Bits in OC1D determine whether selected bits are to be set or cleared when
an OC1 match occurs. Pins must be configured as outputs in order for the data in the
register to be driven out on the corresponding pin. If an OC1 match and another output
match occur at the same time and both attempt to alter the same pin, the OC1 function
controls the state of the pin.
7
7.8.3.2 Forced Output Compare
Timer compare force register (CFORC) is used to make forced compares. The action
taken as a result of a forced compare is the same as when an output compare match
occurs, except that status flags are not set. Forced channels take programmed actions
immediately after the write to CFORC.
The CFORC register is implemented as the upper byte of a 16-bit register which also
contains the PWM control register C (PWMC). It can be accessed as eight bits or a
word access can be used. Reads of force compare bits (FOC) have no meaning and
always return zeros. These bits are self-negating.
7.9 Input Capture 4/Output Compare 5
The IC4/OC5 pin can be used for input capture, output compare, or general-purpose
I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL)
configures the pin for input capture (IC4) or output compare function (OC5). Both bits
are cleared during reset, configuring the pin as an input, but also enabling the OC5
function. IC4/OC5 I/O functions are controlled by the I4/O5 bit in the port GP data di-
rection register (DDRGP).
The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture
register or as an output compare register depending on which function is selected.
When used as the input capture 4 register, it cannot be written except in test or freeze
mode.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-13
USER’S MANUAL
7.10 Pulse Accumulator
The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can
operate in external event counting or gated time accumulation modes. Figure 7-5 is a
block diagram of the pulse accumulator.
In event counting mode, the counter increments each time a selected transition of the
pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the sys-
tem clock divided by four.
In gated time accumulation mode a clock increments PACNT while the PAI pin is in
the active state. There are four possible clock sources.
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator
flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse
accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has
rolled over from $FF to $00. This can be used to extend the range of the counter be-
yond eight bits.
An interrupt request can be made when each of the status flags is set. However, op-
eration of the PAI interrupt depends on operating mode. In event counting mode, an
interrupt is requested when the edge being counted is detected. In gated mode, the
request is made when the PAI input changes from active to inactive state. Interrupt re-
quests are enabled by the PAOVI and PAII bits in the TMSK2 register.
7
Bits in the pulse accumulator control register (PACTL) control the operation of PACNT.
The PAMOD bit selects event counting or gated operation. In event counting mode,
the PEDGE control bit determines whether a rising or falling edge is detected; in gated
mode, PEDGE specifies the active state of the gate signal. Bits PACLK[1:0] select the
clock source used in gated mode.
PACTL and PACNT are implemented as one 16-bit register, but can be accessed with
byte or word access cycles. Both registers are cleared at reset, but the PAIS and
PCLKS bits show the state of the PAI and PCLK pins.
The PAI pin can also be used for general-purpose input. The logic state of the PAIS
bit in PACTL shows the state of the pin.
MOTOROLA
7-14
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
10
INTERRUPT
REQUESTS
11
TMSK2
TFLG2
EDGE
DETECT
LOGIC
SYNCHRONIZER
&
DIGITAL FILTER
OVERFLOW
ENABLE
PAI
2:1
MUX
PACNT
8-BIT COUNTER
7
PACTL
INTERNAL
DATA BUS
PCLK
TCNT OVERFLOW
CAPTURE/COMPARE CLK
MUX
PRESCALER ÷ 512
16/32 PLS ACC BLOCK
Figure 7-5 Pulse Accumulator Block Diagram
7.11 Pulse-Width Modulation Unit
The pulse-width modulation (PWM) unit has two output channels, PWMA and PWMB.
A single clock output from the prescaler multiplexer drives a 16-bit counter that is used
to control both channels. Figure 7-6 is a block diagram of the pulse-width modulation
unit.
The PWM unit has two operational modes. Fast mode uses a clocking rate equal to 1/
256 of the prescaler output rate; slow mode uses a rate equal to 1/32768 of the pres-
caler output rate. The duty cycle ratios of the two PWM channels can be individually
controlled by software. The PWMA pin can also output the clock that drives the PWM
counter. PWM pins can also be used as output pins.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-15
USER’S MANUAL
16-BIT DATA BUS
PWMA REGISTER
PWMB REGISTER
PWMBUFA REGISTER PWMBUFB REGISTER
COMPARATOR A
COMPARATOR B
7
R
LATCH
S
R
LATCH
S
PWMB
PIN
PWMA
PIN
F1A
BIT
F1B
BIT
ZERO DETECTOR
ZERO DETECTOR
SFA
BIT
SFB
BIT
MULTIPLEXER A
MULTIPLEXER B
16-BIT COUNTER
16-BIT TIMER BUS
FROM
PRESCALER
16/32 PWM BLOCK
Figure 7-6 PWM Block Diagram
7.11.1 PWM Counter
The 16-bit counter in the PWM unit is similar to the timer counter in the capture/com-
pare unit. During reset, the GPT is configured to use the system clock divided by two
to drive the counter. Initialization software can reconfigure the counter to use one of
seven prescaler outputs or an external clock input from the PCLK pin.
MOTOROLA
7-16
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
The PWM count register (PWMCNT) can be read at any time without affecting its val-
ue. A read must be a word access to ensure coherence, but byte accesses can be
made if coherence is not needed. The counter is cleared to $0000 during reset and is
a read-only register except in freeze or test mode.
Fifteen of the sixteen counter bits are output to multiplexers A and B. The multiplexers
provide the fast and slow modes of the PWM unit. Mode for PWMA is selected by the
SFA bit in the PWM control register C (PWMC). Mode for PWMB is selected by the
SFB bit in the same register.
PWMA, PWMB, and PPR[2:0] bits in PWMC control PWM output frequency. In fast
mode, bits [7:0] of PWMCNT are used to clock the PWM logic; in slow mode, bits [14:7]
are used. The period of a PWM output in is 128 times longer than the fast mode period.
Table 7-3 shows a range of PWM output frequencies using a 16.78-MHz system clock
and 20.97-MHz system clock.
Table 7-3 PWM Frequency Ranges
Using 16.78-MHz/20.97-MHz System Clocks
PPR
[2:0]
Prescaler Tap
16.78 MHz 20.97 MHz
SFA/B = 0
SFA/B = 1
7
16.78 MHz
20.97 MHz
41 kHz
16.78 MHz 20.97 MHz
000 Div 2 = 8.39 MHz Div 2 = 10.5 MHz
001 Div 4 = 4.19 MHz Div 4 = 5.25 MHz
010 Div 8 = 2.10 MHz Div 8 = 2.62 MHz
011 Div 16 = 1.05 MHz Div 16 = 1.31 MHz
100 Div 32 = 524 kHz Div 32 = 655 kHz
101 Div 64 = 262 kHz Div 64 = 328 kHz
110 Div 128 = 131 kHz Div 128 = 164 kHz
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
5.0 Hz
20.5 kHz
10.2 kHz
5.15 kHz
2.56 kHz
1.28 kHz
641 Hz
4.0 Hz
111
PCLK
PCLK
PCLK/256
PCLK/256
PCLK/32768 PCLK/32768
7.11.2 PWM Function
The pulse width values of the PWM outputs are determined by control registers PWMA
and PWMB. PWMA and PWMB are 8-bit registers implemented as two bytes of a 16-
bit register. PWMA and PWMB can be accessed as separate bytes or as one 16-bit
register. A value of $00 loaded into either register causes the corresponding output pin
to output a continuous logic level zero signal. A value of $80 causes the corresponding
output signal to have a 50% duty cycle, and so on, to the maximum value of $FF, which
corresponds to an output which is at logic level one for 255/256 of the cycle.
Setting the F1A (for PWMA) or F1B (for PWMB) bits in the register causes the corre-
sponding pin to output a continuous logic level one signal. The logic level of the asso-
ciated pin does not change until the end of the current cycle. F1A and F1B are the
lower two bits of CFORC, but can be accessed at the same word address as PWMC.
Data written to PWMA and PWMB is not used until the end of a complete cycle. This
prevents spurious short or long pulses when register values are changed. The current
duty cycle value is stored in the appropriate PWM buffer register (PWMBUFA or PW-
MBUFB). The new value is transferred from the PWM register to the buffer register at
the end of the current cycle.
MC68331
GENERAL-PURPOSE TIMER
MOTOROLA
7-17
USER’S MANUAL
Registers PWMA, PWMB, and PWMC are reset to $00 during reset. These registers
may be written or read at any time. PWMC is implemented as the lower byte of a 16-
bit register. The upper byte is the CFORC register. The buffer registers, PWMBUFA
and PWMBUFB, are read-only at all times and may be accessed as separate bytes or
as one 16-bit register.
Pins PWMA and PWMB can also be used for general-purpose output. The values of
the F1A and F1B bits in PWMC are driven out on the corresponding PWM pins when
normal PWM operation is disabled. When read, the F1A and F1B bits reflect the states
of the PWMA and PWMB pins.
7
MOTOROLA
7-18
GENERAL-PURPOSE TIMER
MC68331
USER’S MANUAL
APPENDIX A ELECTRICAL CHARACTERISTICS
This appendix contains electrical specification tables and reference timing diagrams.
Table A-1 Maximum Ratings
Num
Rating
1,2 , 7
Symbol
Value
–0.3 to +6.5
–0.3 to +6.5
25
Unit
V
1
2
3
Supply Voltage
V
DD
1, 2, 3, 5, 7
Input Voltage
V
V
in
Instantaneous Maximum Current
I
mA
D
1, 5, 6, 7
Single pin limit (applies to all pins)
Operating Maximum Current
4
5
I
–500 to 500
µA
°C
ID
4,5,6,7,8
Digital Input Disruptive Current
V
V
– 0.3 V
+ 0.3
NEGCLMAP
POSCLAMP
V
DD
Operating Temperature Range
MC68331 No Suffix
T
T to T
L H
0 to 70
A
A
MC68331 “C” Suffix
MC68331 “V” Suffix
MC68331 “M” Suffix
–40 to 85
–40 to 105
–40 to 125
6
Storage Temperature Range
T
–55 to 150
°C
stg
1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or
currents in excess of recommended values affects device reliability. Device modules may
not operate normally while being exposed to electrical extremes.
2. Although sections of the device contain circuitry to protect against damage from high static
voltages or electrical fields, take normal precautions to avoid exposure to voltages higher
than maximum-rated voltages.
3. All pins except
/TSC
TSTME
4. All functional non-supply pins are internally clamped to V . All functional pins except EX-
SS
TAL and XFC are internally clamped to V
.
DD
5. Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltag-
es, then use the larger of the two values.
6. Power supply must maintain regulation within operating V range during instantaneous and
DD
operating maximum current conditions.
7. This parameter is periodically sampled rather than 100% tested.
8. Total input current for all digital input-only and all digital input/output pins must not exceed
10 mA. Exceeding this limit can cause disruption of normal operation.
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-1
USER’S MANUAL
Table A-2 Typical Ratings, 16.78 MHz Operation
Num
Rating
Symbol
Value
5.0
Unit
V
1
2
3
Supply Voltage
Operating Temperature
Supply Current
V
DD
T
25
°C
A
V
I
DD
DD
RUN
LPSTOP, VCO off
LPSTOP, External clock, maxi f
75
125
3
mA
µA
mA
sys
4
5
Clock Synthesizer Operating Voltage
Supply Current
V
5.0
V
DDSYN
I
DDSYN
V
DDSYN
VCO on, maximum f
1.0
4.0
100
50
mA
mA
µA
sys
External Clock, maximum f
LPSTOP, VCO off
sys
V
powered down
µA
DD
6
Power Dissipation
P
455
mW
D
Table A-2a Typical Ratings, 20.97 MHz Operation
Num
Rating
Symbol
Value
5.0
Unit
V
1
2
3
Supply Voltage
Operating Temperature
Supply Current
V
DD
A
T
25
°C
A
V
I
DD
DD
RUN
LPSTOP, VCO off
LPSTOP, External clock, maxi f
113
125
3.75
mA
µA
µA
sys
4
5
Clock Synthesizer Operating Voltage
Supply Current
V
5.0
V
DDSYN
I
DDSYN
V
DDSYN
VCO on, maximum f
External Clock, maximum f
LPSTOP, VCO off
1.0
5.0
100
50
mA
mA
µA
sys
sys
V
powered down
µA
DD
6
Power Dissipation
P
570
mW
D
MOTOROLA
A-2
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
Table A-3 Thermal Characteristics
Num
Rating
Thermal Resistance
Symbol
Value
Unit
1
Θ
°C/W
ϑΑ
Plastic 132-Pin Surface Mount
Plastic 144-Pin Surface Mount
Thin Plastic 144-Pin Surface Mount
38
46
49
NOTES:
The average chip-junction temperature (T ) in C can be obtained from:
J
T = T + (P × Θ )
ϑΑ
(1)
J
A
D
where
T
Θ
P
P
P
=
=
=
=
=
Ambient Temperature, °C
Package Thermal Resistance, Junction-to-Ambient, °C/W
+ P
A
ϑΑ
D
P
INT
I/O
I
V
, Watts — Chip Internal Power
INT
DD × DD
Power Dissipation on Input and Output Pins — User Determined
and can be neglected. An approximate relationship between P and
I/O
For most applications P < P
I/O
INT
D
T (if P is neglected) is:
J
I/O
P = K ÷ (T + 273°C)
(2)
(3)
D
J
Solving equations 1 and 2 for K gives:
K = P + (T + 273°C) + Θ × P
D
2
D
A
ϑΑ
where K is a constant pertaining to the particular part. K can be determined from equation (3) by mea-
A
suring P (at equilibrium) for a known T . Using this value of K, the values of P and T can be ob-
D
A
D
J
tained by solving equations (1) and (2) iteratively for any value of T .
A
Table A-4 16.78 MHz Clock Control Timing
(V and V
= 5.0 Vdc ±10%, V = 0 Vdc, T = T to T
32.768 kHz reference)
DD
DDSYN
SS
A
L
H,
Num
Characteristic
Symbol
Min
25
Max
Unit
1
2
PLL Reference Frequency Range
f
50
kHz
ref
1
System Frequency
dc
16.78
16.78
16.78
20
On-Chip PLL System Frequency
External Clock Operation
f
0.131
dc
MHz
sys
2,3,4,5
3
4
5
PLL Lock Time
t
—
ms
lpll
6
VCO Frequency
f
2 (f max)
MHz
MHz
VCO
sys
Limp Mode Clock Frequency
SYNCR X bit = 0
f
limp
—
—
f
max/2
sys
SYNCR X bit = 1
f
max
sys
2,3,4,7
6
CLKOUT Stability
C
%
stab
Short term (5 µs interval)
Long term (500 µs interval)
–0.5
–0.05
0.5
0.05
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-3
Table A-4a 20.97 MHz Clock Control Timing
(V and V
= 5.0 Vdc ±5%, V = 0 Vdc, T = T to T
32.768 kHz reference)
DD
DDSYN
SS
A
L
H,
Num
Characteristic
Symbol
Min
25
Max
50
Unit
1
2
PLL Reference Frequency Range
f
kHz
ref
1
System Frequency
dc
20.97
20.97
20.97
20
On-Chip PLL System Frequency
External Clock Operation
f
0.131
dc
MHz
sys
2,3,4,5
3
4
5
PLL Lock Time
t
—
ms
lpll
6
VCO Frequency
f
—
2 (f max)
MHz
MHz
VCO
sys
Limp Mode Clock Frequency
SYNCR X bit = 0
f
limp
—
—
f
max/2
sys
SYNCR X bit = 1
f
max
sys
2,3,4,7
6
CLKOUT Stability
C
%
stab
Short term (5 µs interval)
Long term (500 µs interval)
–0.5
–0.05
0.5
0.05
Notes for Tables A–4 and A–4a
1. All internal registers retain data at 0 Hz
2 This parameter is periodically sampled rather than 100% tested.
A
3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
external resistance from the XFC pin due to external leakage must be greater than 15 M ∫ to guarantee this
specification. Filter network geometry can vary depending upon operating environment (See 4.3 System
Clock).
4. Proper layout procedures must be followed to achieve specifications.
5. Assumes that stable V
is applied, and that the crystal oscillator is stable. Lock time is measured from
DDSYN
the time V and V
are valid until RESET is released. This specification also applies to the period
DD
DDSYN
required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register
(SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
6. Internal VCO frequency (f
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a
VCO
divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f
sys
= f
÷ 4. When X = 1, the divider is disabled, and f
= f
÷ 2. X must equal one when operating at
VCO
sys
VCO
maximum specified f
.
sys
7. Stability is the average deviation from the programmed frequency measured over the specified interval at
maximum f . Measurements are made with the device powered by filtered supplies and clocked by a sta-
sys
ble external clock signal. Noise injected into the PLL circuitry via V
and V and variation in crystal
DDSYN
SS
oscillator frequency increase the C
percentage for a given interval. When clock stability is a critical con-
stab
straint on control system operation, this parameter should be measured during functional testing of the final
system.
MOTOROLA
A-4
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
Table A-5 16.78 MHz DC Characteristics
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
SS A L H
DD
DDSYN
Num
Characteristic
Symbol
Min
0.7 (V
Max
V + 0.3
DD
Unit
V
1
2
3
4
Input High Voltage
Input Low Voltage
V
)
IH
DD
V
V
– 0.3 0.2 (V )
DD
V
IL
SS
1
Input Hysteresis
V
0.5
–2.5
—
V
HYS
2
Input Leakage Current
I
2.5
µA
in
V = V or V
Input-only pins
in
DD
SS
2
5
High Impedance (Off-State) Leakage Current
V = V or V All input/output and output pins
I
µA
OZ
–2.5
– 0.2
DD
2.5
—
in
DD
SS
2, 3
6
7
8
9
CMOS Output High Voltage
= –10.0 µA
V
V
V
V
V
V
V
OH
I
Group 1, 2, 4 input/output and all output pins
OH
2
CMOS Output Low Voltage
= 10.0 µA
V
—
0.2
—
OL
I
Group 1, 2, 4 input/output and all output pins
Group 1, 2, 4 input/output and all output pins
OL
2, 3
Output High Voltage
= –0.8 mA
V
– 0.8
DD
OH
I
OH
2
Output Low Voltage
V
OL
I
I
I
= 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE
—
—
—
0.4
0.4
0.4
OL
OL
OL
= 5.3 mA
= 12 mA
Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS
Group 3
A
10 Three State Control Input High Voltage
V
1.6 (V
)
DD
9.1
V
IHTSC
5
11 Data Bus Mode Select Pull-up Current
I
µA
MSP
V = V
V = V
DATA[15:0]
DATA[15:0]
—
–15
–120
—
in
IL
in
IH
6
12
V
Supply Current
DD
RUN
4
I
—
—
—
124
350
5
mA
µA
mA
DD
LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum f
S
S
IDD
IDD
)
sys
13 Clock Synthesizer Operating Voltage
V
4.5
5.5
V
DDSYN
6
14
V
Supply Current
DDSYN
32.768 kHz crystal, VCO on, maximum f
I
I
—
—
—
—
1
5
150
100
mA
mA
µA
sys
DDSYN
DDSYN
External Clock, maximum f
sys
LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0)
S
IDDSYN
DDSYN
32.768 kHz crystal, V powered down
I
µA
DD
8
15 Power Dissipation
16 Input Capacitance
P
C
—
690
mW
pF
D
2, 9
All input-only pins
All input/output pins
—
—
10
20
in
2
17 Load Capacitance
Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O pins
C
—
—
—
—
90
pF
L
100
130
200
Group 4 I/O pins
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-5
USER’S MANUAL
Table A-5a 20.97 MHz DC Characteristics
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
SS A L H
DD
DDSYN
Num
Characteristic
Symbol
Min
0.7 (V
Max
V + 0.3
DD
Unit
V
1
2
3
4
Input High Voltage
Input Low Voltage
V
)
IH
DD
V
V
– 0.3 0.2 (V )
DD
V
IL
SS
1
Input Hysteresis
V
0.5
–2.5
—
V
HYS
2
Input Leakage Current
I
2.5
µA
in
V = V or V
Input-only pins
in
DD
SS
2
5
High Impedance (Off-State) Leakage Current
V = V or V All input/output and output pins
I
µA
OZ
–2.5
– 0.2
DD
2.5
—
in
DD
SS
2, 3
6
7
8
9
CMOS Output High Voltage
= –10.0 µA
V
V
V
V
V
V
V
OH
I
Group 1, 2, 4 input/output and all output pins
OH
2
CMOS Output Low Voltage
= 10.0 µA
V
—
0.2
—
OL
I
Group 1, 2, 4 input/output and all output pins
Group 1, 2, 4 input/output and all output pins
OL
2, 3
Output High Voltage
= –0.8 mA
V
– 0.8
DD
OH
I
OH
2
Output Low Voltage
V
OL
I
I
I
= 1.6 mA Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE
—
—
—
0.4
0.4
0.4
OL
OL
OL
= 5.3 mA
= 12 mA
Group 2 and Group 4 I/O Pins, CSBOOT, BG/CS
Group 3
A
10 Three State Control Input High Voltage
V
1.6 (V
)
DD
9.1
V
IHTSC
5
11 Data Bus Mode Select Pull-up Current
I
µA
MSP
V = V
V = V
DATA[15:0]
DATA[15:0]
—
–15
–120
—
in
IL
in
IH
6
12
V
Supply Current
DD
RUN
4
I
—
—
—
140
350
5
mA
µA
mA
DD
LPSTOP, 32.768 kHz crystal, VCO Off (STSIM = 0)
LPSTOP (External clock input frequency = maximum f
S
S
IDD
IDD
)
sys
13 Clock Synthesizer Operating Voltage
V
4.75
5.25
V
DDSYN
6
14
V
Supply Current
DDSYN
32.768 kHz crystal, VCO on, maximum f
I
I
—
—
—
—
2
6
150
100
mA
mA
µA
sys
DDSYN
DDSYN
External Clock, maximum f
sys
LPSTOP, 32.768 kHz crystal, VCO off (STSIM = 0)
S
IDDSYN
DDSYN
32.768 kHz crystal, V powered down
I
µA
DD
7
15 Power Dissipation
16 Input Capacitance
P
C
—
766
mW
pF
D
2, 8
All input-only pins
All input/output pins
—
—
10
20
in
2
17 Load Capacitance
Group 1 I/O Pins and CLKOUT, FREEZE/QUOT, IPIPE
Group 2 I/O Pins and CSBOOT, BG/CS
Group 3 I/O pins
C
—
—
—
—
90
pF
L
100
130
200
Group 4 I/O pins
MOTOROLA
A-6
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
Notes for Tables A–5 and A–5a
1. Applies to:
Port E [7:4] — SIZ[1:0], AS, DS
Port F [7:0] — IRQ[7:1], MODCLK
Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
Port QS [7:0] — TXD, PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO
BKPT/DSCLK, IFETCH, RESET, RXD, TSTME/TSC
EXTAL (when PLL enabled)
2. Input-Only Pins: EXTAL, TSTME/TSC, BKPT, RXD
Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE
Input/Output Pins:
Group 1:
Port GP [7:0] — IC4/OC5/OC1, IC[3:1], OC[4:1]/OC1
DATA[15:0], IFETCH
Group 2 :
Port C [6:0] — ADDR[22:19]/CS[9:6], FC[2:0]/CS[5:3]
Port E [7:0] — SIZ[1:0], AS, DS, AVEC, RMC, DSACK[1:0]
Port F [&:0] — IRQ[7:1], MODCLK
Port QS [7:3] — TXD, PCS[3:1],ÊPCS0/SS
ADDR23/CS10/ECLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2
HALT, RESET
Group 3:
Group 4:
MISO, MOSI, SCK
3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS [7:0] (TXD,
PCS[3:1],ÊPCS0/SS, SCK, MOSI, MISO) in wired-OR mode.
4. Current measured with system clock frequency of 16.78 MHz, all modules active.
5. Use of an active pulldown device is recommended.
A
6. Total operating current is the sum of the appropriate I and I
values. I values include supply currents for
DD
DD
DDSYN
device modules powered by V
and V
pins.
DDE
DDI
7. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be cal-
culated using the expression:
P = Maximum V (I + I
)
D
DD DD
DDSYN
I
includes supply currents for all device modules powered by V
and V pins.
DDI
DD
DDE
8. This parameter is periodically sampled rather than 100% tested.
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-7
USER’S MANUAL
Table A-6 16.78 MHz AC Timing
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
F1
1
Characteristic
Frequency of Operation (32.768 kHz crystal)
Clock Period
Symbol
Min
0.13
59.6
476
59.6
24
Max
16.78
—
Unit
MHz
ns
2
f
t
cyc
1A
1B
ECLK Period
t
t
—
ns
Ecyc
Xcyc
3
External Clock Input Period
—
ns
2, 3 Clock Pulse Width
t
—
ns
CW
2A, 3A ECLK Pulse Width
t
236
29.8
—
—
ns
ECW
3
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
t
—
ns
XCHL
t
5
ns
Crf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
t
—
8
ns
rf
4
4B, 5B External Clock Rise and Fall Time
t
—
5
ns
XCrf
6
7
Clock High to Address, FC, SIZE, RMC Valid
t
0
29
59
—
ns
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance
Clock High to Address, FC, SIZE, RMC Invalid
Clock Low to AS, DS, CS Asserted
t
0
ns
CHAZx
8
t
0
ns
CHAZn
9
t
t
2
25
15
22
—
ns
CLSA
5
9A
9C
11
AS to DS or CS Asserted (Read)
–15
2
ns
STSA
Clock Low to IFETCH, IPIPE Asserted
t
ns
CLIA
A
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
t
15
ns
AVSA
12
Clock Low to AS, DS, CS Negated
t
2
2
29
22
—
ns
ns
ns
CLSN
12A Clock Low to IFETCH, IPIPE Negated
t
CLIN
SNAI
13
AS, DS, CS Negated to
t
15
Address, FC, SIZE Invalid (Address Hold)
14
AS, CS Width Asserted
t
100
45
40
40
—
15
0
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
90
50
29
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWA
14A DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
14B AS, CS Width Asserted (Fast Write Cycle)
6
15
16
17
18
20
21
22
23
24
25
26
27
AS, DS, CS Width Negated
t
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
t
CHSZ
SNRN
CHRH
t
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
15
70
—
15
15
15
5
t
CHDO
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
t
DVASN
t
SNDOI
t
DVSA
t
DICL
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
t
20
0
BELCL
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
7
DS, CS Negated to Data In Invalid (Data In Hold)
t
0
SNDI
SHDI
7, 8
29A DS, CS Negated to Data In High Impedance
t
—
15
—
—
—
1
7
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
t
CLDI
7
30A CLKOUT Low to Data In High Impedance
t
CLDH
9
31
33
35
37
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
t
DADI
t
CLBAN
10
t
t
t
BRAGA
cyc
cyc
t
1
GAGN
MOTOROLA
A-8
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
Table A-6 16.78 MHz AC Timing, (Continued)
(V and V
= 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
2
Max
—
Unit
39
BG Width Negated
t
t
t
GH
cyc
39A BG Width Asserted
46 R/W Width Asserted (Write or Read)
t
1
—
GA
cyc
t
150
90
5
—
ns
ns
ns
RWA
46A R/W Width Asserted (Fast Write or Read Cycle)
t
—
RWAS
47A Asynchronous Input Setup Time
t
—
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47B Asynchronous Input Hold Time
t
15
—
0
—
30
—
28
—
—
—
29
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
AIHT
11
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
t
DABA
DOCH
t
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
t
—
40
512
0
CHDH
t
RADC
t
t
cyc
HRPW
t
ns
BNHN
t
0
ns
ns
ns
ns
ns
SCLDD
t
15
10
15
10
20
0
SCLDS
t
SCLDH
t
BKST
A
BKPT Input Hold Time
t
BKHT
Mode Select Setup Time
t
t
cyc
MSS
Mode Select Hold Time
t
ns
MSH
12
RESET Assertion Time
t
4
t
RSTA
RSTR
cyc
cyc
13
RESET Rise Time
t
—
t
Table A-6a 20.97 MHz AC Timing
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
F1
1
Characteristic
Frequency of Operation (32.768 kHz crystal)
Clock Period
Symbol
Min
0.13
47.7
381
47.7
18.8
183
23.8
—
Max
20.97
—
Unit
MHz
ns
2
f
t
cyc
1A
1B
ECLK Period
t
t
—
ns
Ecyc
3
External Clock Input Period
—
ns
Xcyc
2, 3 Clock Pulse Width
t
—
ns
CW
2A, 3A ECLK Pulse Width
t
—
ns
ECW
3
2B, 3B External Clock Input High/Low Time
4, 5 Clock Rise and Fall Time
t
—
ns
XCHL
t
5
ns
Crf
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
t
—
8
ns
rf
4
4B, 5B External Clock Rise and Fall Time
t
—
5
ns
XCrf
6
7
Clock High to Address, FC, SIZE, RMC Valid
t
0
23
47
—
ns
CHAV
Clock High to Address, Data, FC, SIZE, RMC High Impedance
Clock High to Address, FC, SIZE, RMC Invalid
Clock Low to AS, DS, CS Asserted
t
0
ns
CHAZx
8
t
0
ns
CHAZn
9
t
t
0
23
10
22
—
ns
CLSA
5
9A
9C
11
AS to DS or CS Asserted (Read)
–10
2
ns
STSA
Clock Low to IFETCH, IPIPE Asserted
t
ns
CLIA
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
t
10
ns
AVSA
12
Clock Low to AS, DS, CS Negated
t
2
2
23
22
—
ns
ns
ns
CLSN
12A Clock Low to IFETCH, IPIPE Negated
t
CLIN
13
AS, DS, CS Negated to
t
10
SNAI
Address, FC, SIZE Invalid (Address Hold)
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-9
USER’S MANUAL
Table A-6a 20.97 MHz AC Timing, (Continued)
(V and V
= 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
DDSYN
SS
A
L
H
Num
Characteristic
Symbol
Min
80
36
32
32
—
10
0
Max
—
—
—
—
47
—
23
23
—
—
23
—
—
—
—
—
60
—
48
—
72
46
23
—
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
AS, CS Width Asserted
t
SWA
14A DS, CS Width Asserted (Write)
t
SWAW
t
SWDW
14B AS, CS Width Asserted (Fast Write Cycle)
6
15
16
17
18
20
21
22
23
24
25
26
27
AS, DS, CS Width Negated
t
SN
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
t
CHSZ
SNRN
CHRH
t
t
Clock High to R/W Low
t
t
t
0
CHRL
RAAA
RASA
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
10
54
—
10
10
10
5
t
CHDO
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
t
DVASN
t
SNDOI
t
DVSA
t
DICL
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
t
15
0
BELCL
28
29
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
t
SNDN
A
7
DS, CS Negated to Data In Invalid (Data In Hold)
t
0
SNDI
SHDI
7, 8
29A DS, CS Negated to Data In High Impedance
t
—
10
—
—
—
1
7
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
t
CLDI
7
30A CLKOUT Low to Data In High Impedance
t
CLDH
9
31
33
35
37
39
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
BGACK Asserted to BG Negated
BG Width Negated
t
DADI
t
CLBAN
10
t
t
t
t
t
BRAGA
cyc
cyc
cyc
cyc
t
1
GAGN
t
2
—
—
—
—
—
GH
39A BG Width Asserted
t
1
GA
46
R/W Width Asserted (Write or Read)
t
115
70
5
ns
ns
ns
RWA
46A R/W Width Asserted (Fast Write or Read Cycle)
47A Asynchronous Input Setup Time
t
RWAS
t
AIST
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
47B Asynchronous Input Hold Time
t
12
—
0
—
30
—
23
—
—
—
23
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
AIHT
11
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
t
DABA
t
DOCH
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
t
—
32
512
0
CHDH
t
RADC
t
t
cyc
HRPW
t
ns
BNHN
t
0
ns
ns
ns
ns
ns
SCLDD
t
10
10
10
10
20
0
SCLDS
t
SCLDH
t
BKST
BKPT Input Hold Time
t
BKHT
Mode Select Setup Time
t
t
cyc
MSS
Mode Select Hold Time
t
ns
MSH
12
RESET Assertion Time
t
4
t
RSTA
RSTR
cyc
cyc
13,14
RESET Rise Time
t
—
t
MOTOROLA
A-10
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
Notes for Tables A–6 and A–6a:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. Minimum system clock frequency is four times the crystal frequency, subject to specified limits.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable t
period is reduced when the duty cycle of the external clock signal varies. The relationship be-
Xcyc
tween external clock input duty cycle and minimum t
is expressed:
Xcyc
Minimum t
period = minimum t
/ (50% – external clock input duty cycle tolerance).
Xcyc
XCHL
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low during
reset). Does not pertain to an external VCO reference applied while the PLL is enabled (MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference
signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall out-
side the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification
between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (t / 2) + 25 ns.
cyc
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup
time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data
must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must
satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
10. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after all
cycles of the current operand transfer are complete and RMC is negated.
A
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specifica-
tion 47A).
12. After external RESET negation is detected, a short transition period (approximately 2 t ) elapses, then the SIM
cyc
drives RESET low for 512 t
.
cyc
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset
is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Address access time = (2.5 + WS) t – t
– t
cyc
CHAV
DICL
Chip select access time = (2 + WS) t – t
– t
DICL
cyc
CLSA
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-11
1
4
2
3
CLKOUT
5
NOTE: Timing shown with respect to 20% and 70% V
.
DD
68300 CLKOUT TIM
NOTE: Timing shown with respect to 20% and 70% V
.
DD
Figure A-1 CLKOUT Output Timing Diagram
1B
A
4B
2B
3B
EXTAL
5B
68300 EXT CLK INPUT TIM
NOTE: Timing shown with respect to 20% and 70% V . Pulse width shown with respect to 50% V
.
DD
DD
Figure A-2 External Clock Input Timing Diagram
1A
4A
2A
3A
ECLK
5A
68300 ECLK OUTPUT TIM
NOTE: Timing shown with respect to 20% and 70% V
.
DD
Figure A-3 ECLK Output Timing Diagram
MOTOROLA
A-12
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
S0
S1
6
S2
S3
S4
S5
8
CLKOUT
A20–A23
FC0–FC2
SIZ0, SIZ1
AS
11
14
15
13
9
DS
21
9
12
CS
A
20
22
14A
17
R/W
46
DSACK0
DSACK1
D0–D15
BERR
47A
28
25
55
54
26
53
23
48
27A
HALT
73
74
BKPT
68300 RD CYC TIM
Figure A-4 Read Cycle Timing Diagram
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-13
S0
S1
6
S2
S3
S4
S5
8
CLKOUT
A20–A23
FC0–FC2
SIZ0, SIZ1
AS
11
14
15
13
9
DS
21
9
12
CS
20
22
14A
17
A
R/W
46
DSACK0
DSACK1
D0–D15
BERR
47A
28
25
55
54
26
53
23
48
27A
HALT
73
74
BKPT
68300 WR CYC TIM
Figure A-5 Write Cycle Timing Diagram
MOTOROLA
A-14
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
S0
S1
S4
S5
8
S0
CLKOUT
A0–A23
FC0–FC2
SIZ0, SIZ1
AS
6
14B
46A
74
9
12
DS
CS
20
A
18
R/W
27
73
30
30A
D0–D15
BKPT
29A
29
68300 FAST RD CYC TIM
Figure A-6 Fast Termination Read Cycle Timing Diagram
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-15
S0
S1
S4
S5
8
S0
CLKOUT
A0–A23
FC0–FC2
SIZ0, SIZ1
AS
6
14B
9
12
DS
CS
A
20
46A
R/W
24
18
D0–D15
BKPT
23
25
73
74
68300 FAST WR CYC TIM
Figure A-7 Fast Termination Write Cycle Timing Diagram
MOTOROLA
A-16
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
S0
S1
S2
S3
S4
S5
S98
A5
A5
A2
CLKOUT
A0–A23
D0–D15
AS
7
16
DS
R/W
DSACK0
DSACK1
BR
A
47A
39A
35
BG
33
33
BGACK
37
68300 BUS ARB TIM
Figure A-8 Bus Arbitration Timing Diagram — Active Bus Case
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-17
USER’S MANUAL
A0
A5
A5
A2
A3
A0
CLKOUT
A0–A23
D0–D15
AS
47A
47A
BR
35
37
BG
33
47A
33
BGACK
68300 BUS ARB TIM IDLE
A
Figure A-9 Bus Arbitration Timing Diagram — Idle Bus Case
S0
S41
S42
S43
8
S0
S1
S2
CLKOUT
A0–A23
R/W
6
18
20
AS
12
9
15
DS
71
70
72
D0–D15
BKPT
73
74
START OF
EXTERNAL CYCLE
SHOW CYCLE
68300 SHW CYC TIM
NOTE: Show cycles can stretch during S42 when bus accesses take longer than two cycles due to wait-state insertion
by IMB modules.
Figure A-10 Show Cycle Timing Diagram
MOTOROLA
A-18
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
S0
S1
S2
S3
S4
S5
6
S0
S1
S2
S3
S4
S5
8
CLKOUT
A0–A23
FC0–FC2
SIZ0, SIZ1
AS
6
14
11
9
14
11
9
13
17
15
9
12
DS
17
12
21
21
CS
A
18
20
14A
18
46
23
R/W
46
29
25
55
D0–D15
29A
53
54
27
68300 CHIP SEL TIM
NOTE: AS and DS timing shown for reference only.
Figure A-11 Chip Select Timing Diagram
77
78
RESET
75
D0–D15
76
68300 RST/MODE SEL TIM
Figure A-12 Reset and Mode Select Timing Diagram
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-19
USER’S MANUAL
Table A-7 Background Debugging Mode Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Characteristic
Symbol
Min
Max
—
Unit
ns
DSI Input Setup Time
t
15
10
15
10
—
2
DSISU
DSI Input Hold Time
t
—
ns
DSIH
DSCLK Setup Time
t
—
ns
DSCSU
DSCLK Hold Time
t
—
ns
DSCH
DSOD
DSO Delay Time
t
25
—
ns
DSCLK Cycle Time
t
t
cyc
DSCCYC
CLKOUT High to FREEZE Asserted/Negated
CLKOUT High to IFETCH High Impedance
CLKOUT High to IFETCH Valid
DSCLK Low Time
t
—
—
—
1
50
50
50
—
ns
ns
ns
FRZAN
t
IFZ
t
IF
DSCLO
t
t
cyc
cyc
B10 FREEZE Asserted to IFETCH Valid
Notes:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
t
TBD
—
t
FRZIF
DD
DD
A
MOTOROLA
A-20
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
CLKOUT
FREEZE
B5
B3
B2
B0
B9
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
B1
B4
68300 BKGD DBM SER COM TIM
Figure A-13 Background Debugging Mode Timing Diagram —
Serial Communication
A
CLKOUT
B6
FREEZE
B7
B10
B6
B10
IFETCH/DSI
B8
68300 BKGD DBM FRZ TIM
Figure A-14 Background Debugging Mode Timing Diagram —Freeze Assertion
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-21
USER’S MANUAL
Table A-8 16.78 MHz ECLK Bus Timing
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
Max
60
—
150
—
—
—
—
60
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
ECLK Low to Address Valid
t
t
—
15
—
EAD
EAH
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
15
30
30
5
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
EDHZ
ECDH
t
0
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
t
—
t
t
ECDZ
cyc
cyc
t
—
2
EDDW
EDHW
t
15
386
296
1/2
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
t
EACC
A
4
E14 Chip Select Access Time (Read)
t
EACS
E15 Address Setup Time
t
t
cyc
EAS
Table A-8a 20.97 MHz ECLK Bus Timing
(V = 5.0 Vdc ± 5%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Num
E1
E2
E3
E4
E5
E6
E7
E8
E9
Characteristic
Symbol
Min
—
Max
48
—
120
—
—
—
—
48
—
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
ECLK Low to Address Valid
t
t
EAD
EAH
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
10
—
t
t
t
t
ECSD
ECSH
ECSN
EDSR
EDHR
10
25
25
5
CS Negated Width
Read Data Setup Time
Read Data Hold Time
t
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
t
—
EDHZ
ECDH
t
0
E10 CS Negated to Data High Impedance
E11 ECLK Low to Data Valid (Write)
E12 ECLK Low to Data Hold (Write)
t
—
t
t
ECDZ
cyc
cyc
t
t
—
2
EDDW
EDHW
10
308
236
1/2
—
—
—
—
ns
ns
ns
3
E13 Address Access Time (Read)
t
EACC
4
E14 Chip Select Access Time (Read)
t
EACS
E15 Address Setup Time
t
t
cyc
EAS
Notes for Tables A–8 and A–8a:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
– t
– t
.
Ecyc
EAD
EDSR
4. Chip select access time = t
– t
– t
.
Ecyc
ECSD
EDSR
MOTOROLA
A-22
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
CLKOUT
ECLK
R/W
2A
3A
1A
E2
E1
A0–A23
CS
E14
E4
E3
E6
E5
E15
E9
E13
D0–D15
READ
E7
WRITE
E8
E10
E11
D0–D15
WRITE
A
E12
68300 E CYCLE TIM
NOTE: Shown with ECLK = system clock/8 — EDIV bit in clock synthesizer control register (SYNCR) = 0.
Figure A-15 ECLK Timing Diagram
MC68331
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-23
USER’S MANUAL
Table A-9 QSPI Timing
(V = 5.0 V ± 10%, V = 0 Vdc, T = T to T , 200 pF load on all QSPI pins)
DD
dc
SS
A
L
H
Num
Function
Operating Frequency
Symbol
Min
Max
Unit
f
op
Master
Slave
DC
DC
1/4
1/4
System Clock Frequency
System Clock Frequency
1
2
3
4
5
6
7
Cycle Time
Master
t
qcyc
4
4
510
—
t
t
cyc
cyc
Slave
Enable Lead Time
Master
t
lead
2
2
128
—
t
t
cyc
cyc
Slave
Enable Lag Time
Master
t
lag
—
2
1/2
—
SCK
Slave
t
cyc
Clock (SCK) High or Low Time
Master
t
sw
2 t – 60
255 t
—
ns
ns
cyc
cyc
2
Slave
2 t – n
cyc
Sequential Transfer Delay
Master
t
td
17
13
8192
—
t
t
cyc
cyc
Slave (Does Not Require Deselect)
A
Data Setup Time (Inputs)
t
su
Master
Slave
30
20
—
—
ns
ns
Data Hold Time (Inputs)
t
hi
Master
Slave
0
20
—
—
ns
ns
8
9
Slave Access Time
t
—
—
1
2
t
a
cyc
cyc
Slave MISO Disable Time
t
t
dis
10 Data Valid (after SCK Edge)
t
v
Master
Slave
—
—
50
50
ns
ns
11 Data Hold Time (Outputs)
t
ho
Master
Slave
0
0
—
—
ns
ns
12 Rise Time
3
Input
Output
t
—
—
2
30
µs
ns
ri
t
ro
13 Fall Time
3
Input
Output
t
—
—
2
30
µs
ns
fi
t
fo
Notes:
1 All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sources
are at valid V /V prior to SCK transitioning between valid V and V . Due to process variation, logic decision
OH OL
OL
OH
point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used.
MOTOROLA
A-24
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
3
2
PCS0–PCS3
OUTPUT
13
5
12
SCK
CPOL=0
OUTPUT
4
1
SCK
CPOL=1
OUTPUT
6
4
12
13
7
MISO
INPUT
MSB IN
DATA
LSB IN
10
MSB IN
11
MOSI
OUTPUT
MSB OUT
13
DATA
LSB OUT
PORT DATA
12
MSB OUT
PD
68300 QSPI T MAST CPHA0
A
Figure A-16 QSPI Timing — Master, CPHA = 0
3
2
PCS0–PCS3
OUTPUT
13
5
1
12
SCK
CPOL=0
OUTPUT
4
1
7
SCK
CPOL=1
OUTPUT
13
4
12
6
MISO
MSB IN
DATA
DATA
LSB IN
10
MSB IN
INPUT
11
MOSI
OUTPUT
PORT DATA
MSB OUT
13
LSB OUT
PORT DATA MSB OUT
12
68300 QSPI T MAST CPHA1
Figure A-17 QSPI Timing — Master, CPHA = 1
MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-25
3
2
SS
INPUT
13
5
12
SCK
CPOL=0
INPUT
1
4
4
13
SCK
CPOL=1
INPUT
12
11
8
11
10
9
MISO
MSB OUT
DATA
LSB OUT
12
PD
13
MSB OUT
MSB IN
OUTPUT
7
6
MOSI
INPUT
MSB IN
DATA
LSB IN
68300 QSPI T SLV CPHA0
A
Figure A-18 QSPI Timing — Slave, CPHA = 0
SS
INPUT
1
13
5
12
4
SCK
CPOL=0
INPUT
3
2
4
12
SCK
CPOL=1
INPUT
10
13
8
10
11
9
MISO
OUTPUT
MSB
OUT
SLAVE
LSB OUT
PD
DATA
PD
7
12
6
MOSI
INPUT
MSB IN
DATA
LSB IN
68300 QSPI T SLV CPHA1
Figure A-19 QSPI Timing — Slave, CPHA = 1
MOTOROLA
A-26
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
This section contains detailed information to be used as a guide when ordering.
MC68331 is available in either a 132-pin or 144-pin plastic surface mount package.
This appendix provides package pin assignment drawings and ordering information.
B
MC68331
MECHANICAL DATA AND ORDERING INFORMATION
MOTOROLA
B-1
USER’S MANUAL
V
V
18
19
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
DD
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
NC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V
DD
V
V
V
DD
SS
DATA4
DATA5
DATA6
DATA7
SS
ADDR9
ADDR10
ADDR11
ADDR12
B
V
SS
V
DATA8
DATA9
DATA10
DATA11
MC68331
SS
ADDR13
ADDR14
ADDR15
ADDR16
V
DD
V
V
V
SS
DD
DATA12
DATA13
DATA14
DATA15
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
90
89
88
87
86
85
84
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
V
DD
DD
331 132-PIN QFP
Figure B-1 132-Pin Plastic Surface Mount Package Pin Assignments
MOTOROLA
B-2
MECHANICAL DATA AND ORDERING INFORMATION
MC68331
USER’S MANUAL
109
108
1
2
3
4
5
6
7
8
NC
NC
V
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
V
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
SS
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
V
V
DD
SS
PCLK
PWMB
PWMA
NC
HALT
RESET
B
NC
NC
V
SS
MC68331
V
V
NC
PAI
CLKOUT
DD
SS
V
NC
DD
XFC
V
GP7/IC4/OC5/OC1
PGP6/OC4
DD
EXTAL
V
V
V
DD
SS
DD
XTAL
V
NC
PGP5/OC3/OC1
PGP4/OC2/OC1
PGP3/OC1
PGP2/IC3
SS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
RXD
PGP1/IC2
PGP0/IC1
NC
PQS7/TXD
V
NC
V
NC
SS
SS
331 144-PIN QFP
Figure B-2 144-Pin Plastic Surface Mount Package Pin Assignments
MC68331
MECHANICAL DATA AND ORDERING INFORMATION
MOTOROLA
B-3
USER’S MANUAL
Table B-1 MCU Ordering Information
Package Type
Temperature
Frequency
(MHz)
Package
Order
Order Number
Quantity
132-Pin PQFP
–40 to +85 °C
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
16 MHz
20 MHz
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
36 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
44 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
2 pc tray
60 pc tray
SPAKMC331CFC16
MC68331CFC16*
SPAKMC331CFC20
MC68331CFC20*
SPAKMC331VFC16
MC68331VFC16*
SPAKMC331VFC20
MC68331VFC20*
SPAKMC331MFC16
MC68331MFC16*
SPAKMC331MFC20
MC68331MFC20*
SPAKMC331CFV16
MC68331CFV16*
SPAKMC331CFV20
MC68331CFV20*
SPAKMC331VFV16
MC68331VFV16*
SPAKMC331VFV20
MC68331VFV20*
SPAKMC331MFV16
MC68331MFV16*
SPAKMC331MFV20
MC68331MFV20*
SPAKMC331CPV16
MC68331CPV16*
SPAKMC331CPV20
MC68331CPV20*
SPAKMC331VPV16
MC68331VPV16*
SPAKMC331VPV20
MC68331VPV20*
SPAKMC331MPV16
MC68331MPV16*
SPAKMC331MPV20
MC68331MPV20*
–40 to +105 °C
–40 to +125 °C
–40 to +85 °C
–40 to +105 °C
–40 to +125 °C
–40 to +85 °C
–40 to +105 °C
–40 to +125 °C
144-Pin QFP
B
144-Pin TQFP
*Quantity orders are available as shown in Table B–2. Contact your Motorola representative for ordering numbers.
Table B-2 Quantity Order Suffix
FC
36
FV
44
PV
60
180
360
220
440
300
600
MOTOROLA
B-4
MECHANICAL DATA AND ORDERING INFORMATION
MC68331
USER’S MANUAL
APPENDIX CDEVELOPMENT SUPPORT
This section serves as a brief reference to Motorola development tools for the
MC68331 microcontroller. Information provided is complete as of the time of publica-
tion, but new systems and software are continually being developed. In addition, a
growing number of third-party tools are available. The Motorola MCU Tool Box
(MCUTLBX/D Rev. C) provides an up-to-date list of development tools. Contact your
Motorola representative for further information.
Table C-1 MC68331 Development Tools
Microcontroller Part
Number
Modular Development
System
Modular Evaluation
System
MC68331
M68MMDS1632
M68MEVB1632
C.1 M68MMDS1632 Modular Development System
C
M68MMDS1632 Motorola Modular Development System (MMDS) is a development
tool for evaluating M68HC16 and M68300 MCU-based systems. The MMDS1632 is
an emulator, bus state analyzer, and control station for debugging hardware and soft-
ware. A separately purchased active probe completes MMDS functionality with regard
to a particular MCU or MCU family. The many active probes available let your MMDS
emulate a variety of different MCUs. Contact your Motorola sales representative, who
will assist you in selecting and configuring the modular system that fits your needs. A
full-featured development system, the MMDS provides both in-circuit emulation and
bus analysis capabilities, including:
• Real-time in-circuit emulation at maximum speed of 20 MHz (can be upgraded to
33 MHz)
• Built-in emulation memory
— 1 Mbyte main emulation memory (fast termination, 2 bus cycle)
— 4 Kbytes dual-port emulation memory
• Real-time bus analysis
— Instruction disassembly
— State-machine-controlled triggering
• Four hardware breakpoints, bitwise masking
• Analog/digital emulation
• Synchronized signal output
• Built-in AC power supply, 85–264 V, 50–60 Hz, FCC and EC EMI compliant
• RS-232 connection to host capable of communicating at 1200, 2400, 4800, 9600,
19200, 38400, or 57600 baud
MC68331
DEVELOPMENT SUPPORT
MOTOROLA
C-1
USER’S MANUAL
C.2 M68MEVB1632 Modular Evaluation Board
M68MEVB1632 Modular Evaluation Board (MEVB) is a development tool for evaluat-
ing M68HC16 and M68300 MCU-based systems. The MEVB consists of the
M68HC16MPFB modular platform board, an MCU personality board (MPB), an in-cir-
cuit debugger printed circuit board (ICD16 or ICD32), and development software.
MEVB features include:
• An economical means of evaluating target systems incorporating M68HC16 and
M68300 HCMOS MCU devices.
• Expansion memory sockets for installing RAM, EPROM, or EEPROM.
— Data RAM: 32K X 16, 128K X 16, or 512K X 16
— EPROM/EEPROM: 32K X 16, 64K X 16, 128K X 16, 256K X 16, or 512K X 16
— Fast RAM: 32K X 16 or 128K X 16
• Background-mode operation, for detailed operation from a personal computer
platform without an on-board monitor.
• Integrated assembly/editing/evaluation/programming environment for easy de-
velopment.
• As many as seven software breakpoints.
• Re-usable ICD hardware for your target application debug or control.
• Two RS-232C terminal input/output (I/O) ports for user evaluation of the serial
communication interface.
• Logic analyzer pod connectors.
• Port replacement unit (PRU) to rebuild I/O ports lost to address/data/control.
C
• On-board V (+12 Vdc) generation for MCU and flash EEPROM programming.
PP
MOTOROLA
C-2
DEVELOPMENT SUPPORT
MC68331
USER’S MANUAL
APPENDIX D REGISTER SUMMARY
This appendix contains address maps, register diagrams, and bit/field definitions for
the MCU. More detailed information about register function is provided in the appro-
priate sections of the manual.
Except for central processing unit resources, information is presented in the intermod-
ule bus address order shown in Table D-1.
Table D-1 Module Address Map
Module
GPT
Size (Bytes)
Base Address
$YFF900
64
SIM
128
512
$YFFA00
QSM
$YFFC00
Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte
block. The state of the module mapping (MM) bit in the SIM configuration register
(SIMCR) determines where the control registers block is located in the system mem-
ory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF; when
MM = 1, register addresses range from $FFF000 to $FFFFFF.
D
In the module memory maps in this appendix, the “Access” column specifies which
registers are accessible at the supervisor privilege level only and which registers can
be assigned to either the supervisor or user privilege level.
D.1 Central Processing Unit
CPU32 registers are not part of the module address map. The following diagram is a
functional representation of CPU resources.
MC68331
REGISTER SUMMARY
MOTOROLA
D-1
USER’S MANUAL
D.1.1 CPU32 Register Model
31
16 15
8 7
0
D0
D1
D2
D3
D4
D5
D6
D7
DATA REGISTERS
31
16 15
0
A0
A1
A2
A3
A4
A5
A6
ADDRESS REGISTERS
D
31
31
16 15
0
0
0
A7 (USP) USER STACK POINTER
PC
PROGRAM COUNTER
7
CCR
CONDITION CODE REGISTER
Figure D-1 User Programming Model
31
31
16 15
15
0
0
0
A7 (SSP) SUPERVISOR STACK POINTER
8 7
(CCR)
SR
STATUS REGISTER
VBR
VECTOR BASE REGISTER
2
0
SFC
DFC
ALTERNATE FUNCTION
CODE REGISTERS
Figure D-2 Supervisor Programming Model Supplement
MOTOROLA
D-2
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.1.2 — Status Register
15
14
13
S
12
0
11
0
10
1
8
1
7
0
6
0
5
0
4
3
2
Z
1
0
T[1:0]
RESET:
IP
1
X
N
V
C
0
0
1
0
0
0
0
0
U
U
U
U
U
The status register (SR) contains condition codes, an interrupt priority mask, and three
control bits. The condition codes are contained in the condition code register (CCR),
the lower byte of the SR. (The lower and upper bytes of the status register are also
referred to as the user and system bytes, respectively.) At the user privilege level, only
the CCR is available. At the supervisor level, software can access the full status reg-
ister.
T[1:0] — Trace Enable
00 = No tracing
01 = Trace on change of flow
10 = Trace on instruction execution
11 = Undefined; reserved
D
S — Supervisor/User State
0 = CPU operates at user privilege level
1 = CPU operates at supervisor privilege level
IP[2:0] — Interrupt Priority Mask
The priority value in this field (0 to 7) is used to mask interrupts.
X — Extend Flag
Used in multiple-precision arithmetic operations. In many instructions it is set to the
same value as the C bit.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two's complement overflow occurs as the result of an operation.
C — Carry Flag
Set when a carry or borrow occurs during an arithmetic operation. Also used during
shift and rotate instructions to facilitate multiple word operations.
MC68331
REGISTER SUMMARY
MOTOROLA
D-3
USER’S MANUAL
D.2 General-Purpose Timer
Table D-2 displays the GPT address map. The column labeled “Access” indicates the
privilege level at which the CPU must be operating to access the register. A designa-
tion of “S” indicates that supervisor access is required: a designation of “S/U” indicates
that the register can be programmed to the desired privilege level.
Table D-2 GPT Address Map
Access
S
Address 15
$YFF900
8 7
0
GPT MODULE CONFIGURATION (GPTMCR)
(RESERVED FOR TEST)
S
$YFF902
S
$YFF904
INTERRUPT CONFIGURATION (ICR)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
$YFF906 PGP DATA DIRECTION (DDRGP)
PGP DATA (PORTGP)
$YFF908
$YFF90A
$YFF90C
$YFF90E
$YFF910
$YFF912
$YFF914
$YFF916
$YFF918
$YFF91A
$YFF91C
$YFF91E
$YFF920
$YFF922
$YFF924
$YFF926
$YFF928
$YFF92A
$YFF92C
OC1 ACTION MASK (OC1M)
OC1 ACTION DATA (OC1D)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL)
PA COUNTER (PACNT)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
D
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
TIMER CONTROL 1 (TCTL1)
TIMER MASK 1 (TMSK1)
TIMER FLAG 1 (TFLG1)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 2 (TFLG2)
FORCE COMPARE (CFORC)
PWM CONTROL A (PWMA)
PWM CONTROL C (PWMC)
PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA)
PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
NOT USED
$YFF92E –
$YFF93F
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.2.1 GPTMCR — GPT Module Configuration Register
$YFF900
15
STOP
RESET:
0
14
13
12
11
10
0
9
0
8
0
7
6
0
5
0
4
0
3
0
0
FRZ1
FRZ0
STOPP
INCP
SUPV
IARB
0
0
0
0
0
0
0
1
0
0
0
0
0
0
GPTMCR bits control freeze, low-power stop, and single-step modes.
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
MOTOROLA
D-4
REGISTER SUMMARY
MC68331
USER’S MANUAL
FRZ[1:0] — FREEZE Response
FRZ1 is not used; FRZ0 encoding determines response to the IMB FREEZE signal.
0 = Ignore IMB FREEZE signal
1 = Freeze the current state of the GPT
STOPP — Stop Prescaler
0 =Normal operation
1 =Stop prescaler and pulse accumulator from incrementing. Ignore changes to in-
put pins.
INCP — Increment Prescaler
0 =Has no meaning
1 =If STOPP is asserted, increment prescaler once and clock input synchronizers
once.
SUPV — Supervisor/Unrestricted Data Space
0 =Registers with access controlled by the SUPV bit are accessible from either the
user or supervisor privilege level.
1 =Registers with access controlled by the SUPV bit are restricted to supervisor
access only.
D
IARB[3:0] — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are
used to arbitrate between interrupt requests of the same priority.
D.2.2 GPTMTR — GPT Module Test Register (Reserved)
$YFF902
This address is currently unused and returns zeros when read. It is reserved for GPT
factory test.
D.2.3 ICR — GPT Interrupt Configuration Register
$YFF904
15
12
11
0
10
8
7
4
0
3
0
2
0
1
0
0
0
IPA
IPL
0
IVBA
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ICR fields determine internal and external interrupt priority, and provide the upper nib-
ble of the interrupt vector number supplied to the CPU when an interrupt is acknowl-
edged.
IPA — Interrupt Priority Adjust
Specifies which of the 11 internal GPT interrupt sources is assigned highest priority.
IPL — Interrupt Priority Level
Specifies the priority level of GPT interrupt requests.
IVBA — Interrupt Vector Base Address
Contains the most significant nibble of interrupt vector numbers supplied by the GPT.
MC68331
REGISTER SUMMARY
MOTOROLA
D-5
USER’S MANUAL
D.2.4 DDRGP — Port GP Data Direction Register
PORTGP — Port GP Data Register
$YFF906
$YFF907
15
8
7
0
DDRGP
0
PORTGP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input
or output and PORTGP holds the 8-bit data.
DDRGP[7:0] — Parallel Data Direction Register
0 = Input only
1 = Output
PORTGP[7:0] — Parallel Data Register
D.2.5 OC1M— OC1 Action Mask Register
OC1D — OC1 Action Data Register
$YFF908
$YFF909
D
15
11
10
0
9
0
8
0
7
0
3
0
2
0
1
0
0
0
OC1M
0
OC1D
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that
determines which pins are affected. OC1D determines what outputs are affected.
OC1M[5:1] — OC1 Mask
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data
0 =If OC1 mask bit is set, clear corresponding output compare pin on OC1 match.
1 =If OC1 mask bit is set, set corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
D.2.6 TCNT — Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output com-
pare, and pulse accumulator functions of the GPT module.
MOTOROLA
D-6
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.2.7 PACTL — Pulse Accumulator Control Register
PACNT — Pulse Accumulator Counter
$YFF90C
$YFF90D
15
PAIS
RESET:
U
14
13
12
11
10
9
8
7
0
PAEN PAMOD
PEDGE
PCLKS
I4/O5
PACLK
PACNT
0
0
0
0
U
0
0
0
0
0
0
0
0
0
0
PACTL enables the pulse accumulator and selects either event counting or gated
mode. In event counting mode, PACNT is incremented each time an event occurs. In
gated mode, it is incremented by an internal clock.
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = External event counting
D
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
The effects of PEDGE and PAMOD are shown in the following table.
PAMOD
PEDGE
Effect
0
0
1
1
0
1
0
1
PAI Falling Edge Increments Counter
PAI Rising Edge Increments Counter
Zero on PAI Inhibits Counting
One on PAI Inhibits Counting
PCLKS — PCLK Pin State (Read Only)
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
PACLK[1:0]
Pulse Accumulator Clock Selected
00
01
10
11
System Clock Divided by 512
Same Clock Used to Increment TCNT
TOF Flag from TCNT
External Clock, PCLK
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumula-
tion.
MC68331
REGISTER SUMMARY
MOTOROLA
D-7
USER’S MANUAL
D.2.8 TIC[1:3] — Input Capture Registers 1–3
$YFF90E–$YFF912
The input capture registers are 16-bit read-only registers used to latch the value of
TCNT when a specified transition is detected on the corresponding input capture pin.
They are reset to $FFFF.
D.2.9 TOC[1:4] — Output Compare Registers 1–4
$YFF914–$YFF91A
The 16-bit read/write output compare registers can be used as output waveform con-
trols or as elapsed time indicators. For output compare functions, they are written to a
desired match value and compared against TCNT to control specified pin actions.
They are reset to $FFFF.
D.2.10 TI4/O5 — Input Capture 4/Output Compare 5 Register
$YFF91C
This register serves either as input capture register 4 or output compare register 5, de-
pending on the state of I4/O5 in PACTL.
D.2.11 TCTL1/TCTL2 — Timer Control Registers 1 and 2
$YFF91E
15
14
13
12
11
10
9
8
7
6
5
0
4
0
3
0
2
0
1
0
D
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
EDGE4
EDGE3
EDGE2
EDGE1
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
TCTL1 determines output compare mode and output logic level. TCTL2 determines
the type of input capture to be performed.
OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits
Each pair of bits specifies an action to be taken when output comparison is successful.
OM/OL[5:2]
Action Taken
00
01
10
11
Timer Disconnected from Output Logic
Toggle OCx Output Line
Clear OCx Output Line to zero
Set OCx Output Line to one
EDGE[4:1] — Input Capture Edge Control
Each pair of bits configures input sensing logic for the corresponding input capture.
EDGE[4:1]
Configuration
Capture Disabled
00
01
10
11
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Any (Rising or Falling) Edge
MOTOROLA
D-8
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.2.12 TMSK1/TMSK2 — Timer Interrupt Mask Registers 1 and 2
$YFF920
15
14
11
10
8
7
6
0
5
4
3
2
0
0
I4/O5I
OCI
ICI
0
TOI
PAOVI
PAII CPROUT
CPR
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMSK1 enables OC and IC interrupts. TMSK2 controls pulse accumulator interrupts
and TCNT functions.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
0 = IC4/OC5 interrupt disabled
1 = IC4/OC5 interrupt requested when I4/O5F flag in TFLG1 is set
OCI[4:1] — Output Compare Interrupt Enable
0 = OC interrupt disabled
1 = OC interrupt requested when OC flag set
OCI[4:1] correspond to OC[4:1].
ICI[3:1] — Input Capture Interrupt Enable
0 = IC interrupt disabled
D
1 = IC interrupt requested when IC flag set
ICI[3:1] correspond to IC[3:1].
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF flag is set
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF flag is set
PAII — Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF flag is set
CPROUT — Capture/Compare Unit Clock Output Enable
0 = Normal operation for OC1 pin
1 = TCNT clock driven out OC1 pin
CPR[2:0] — Timer Prescaler/PCLK Select Field
This field selects one of seven prescaler taps or PCLK to be TCNT input.
MC68331
REGISTER SUMMARY
MOTOROLA
D-9
USER’S MANUAL
D.2.13 TFLG1/TFLG2 — Timer Interrupt Flag Registers 1 and 2
$YFF922
15
I4/O5F
RESET:
0
14
11
10
8
7
6
0
5
4
3
0
2
0
1
0
0
0
OCF
ICF
0
TOF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
These registers show condition flags that correspond to GPT events. If the corre-
sponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs.
I4/O5F — Input Capture 4/Output Compare 5 Flag
When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 val-
ue in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge
is detected at the I4/O5 pin.
OCF[4:1] — Output Compare Flags
An output compare flag is set each time TCNT matches the corresponding TOC reg-
ister. OCF[4:1] correspond to OC[4:1].
ICF[3:1] — Input Capture Flags
D
A flag is set each time a selected edge is detected at the corresponding input capture
pin. ICF[3:1] correspond to IC[3:1].
TOF — Timer Overflow Flag
This flag is set each time TCNT advances from a value of $FFFF to $0000.
PAOVF — Pulse Accumulator Overflow Flag
This flag is set each time the pulse accumulator counter advances from a value of $FF
to $00.
PAIF — Pulse Accumulator Flag
In event counting mode, this flag is set when an active edge is detected on the PAI pin.
In gated time accumulation mode, it is set at the end of the timed period.
D.2.14 CFORC — Compare Force Register
PWMC — PWM Control Register C
$YFF924
$YFF925
15
11
10
0
9
8
7
6
0
4
0
3
2
1
0
FOC
FPWMA FPWMB
PPROUT
PPR
0
SFA
SFB
F1A
F1B
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets
PWM operating conditions.
FOC[5:1] — Force Output Compare
0 = Has no meaning.
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is
not set.
FOC[5:1] correspond to OC[5:1].
MOTOROLA
D-10
REGISTER SUMMARY
MC68331
USER’S MANUAL
FPWMA — Force PWMA Value
0 = Normal PWMA operation.
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of
PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation.
1 = The value of F1B is driven out on the PWMB pin.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA.
1 = TCNT clock driven out PWMA pin.
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps or PCLK to be PWMCNT input.
PPR[2:0]
System Clock
Divide-by Factor
000
001
010
011
100
101
110
111
2
4
8
D
16
32
64
128
PCLK
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows a range of PWM output frequencies using a 16.78-MHz sys-
tem clock and 20.97 system clock.
PPR
[2:0]
000
001
010
011
100
101
110
111
Prescaler Tap
SFA/B = 0
SFA/B = 1
16.78 MHz
16.78 MHz
20.97 MHz
16.78 MHz
20.97 MHz
41 kHz
20.97 MHz
320 Hz
160 Hz
80.0 Hz
40.0 Hz
20.0 Hz
10.0 Hz
5.0 Hz
Div 2 = 8.39 MHz
Div 4 = 4.19 MHz
Div 8 = 2.10 MHz
Div 2 = 10.5 MHz
Div 4 = 5.25 MHz
Div 8 = 2.62 MHz
32.8 kHz
16.4 kHz
8.19 kHz
4.09 kHz
2.05 kHz
1.02 kHz
512 Hz
256 Hz
128 Hz
64.0 Hz
32.0 Hz
16.0 Hz
8.0 Hz
20.5 kHz
10.2 kHz
5.15 kHz
2.56 kHz
1.28 kHz
641 Hz
Div 16 = 1.05 MHz Div 16 = 1.31 MHz
Div 32 = 524 kHz
Div 64 = 262 kHz
Div 32 = 655 kHz
Div 64 = 328 kHz
Div 128 = 131 kHz Div 128 = 164 kHz
PCLK PCLK
4.0 Hz
PCLK/256
PCLK/256
PCLK/32768 PCLK/32768
F1A — Force Logic Level One on PWMA
0 = Force logic level zero output on PWMA pin.
1 = Force logic level one output on PWMA pin.
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-11
F1B — Force Logic Level One on PWMB
0 = Force logic level zero output on PWMB pin.
1 = Force logic level one output on PWMB pin.
D.2.15 PWMA/PWMB — PWM Registers A/B
$YFF926, $YFF927
The value in these registers determines pulse width of the corresponding PWM output.
A value of $00 corresponds to continuously low output; a value of $80 to 50% duty cy-
cle. Maximum value ($FF) selects an output that is high for 255/256 of the period.
Writes to these registers are buffered by PWMBUFA and PWMBUFB.
D.2.16 PWMCNT — PWM Count Register
$YFF928
PWMCNT is the 16-bit free-running counter used for GPT PWM functions.
D.2.17 PWMBUFA — PWM Buffer Register A
PWMBUFB — PWM Buffer Register B
$YFF92A
$YFF92B
To prevent glitches when PWM duty cycle is changed, the contents of PWMA and
PWMB are transferred to these read-only registers at the end of each duty cycle. Re-
set state is $0000.
D
D.2.18 PRESCL — GPT Prescaler
$YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always
read as zeros. Reset state is $0000.
MOTOROLA
D-12
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.3 System Integration Module
Table D-3 displays the SIM address map. The column labeled “Access” indicates the
privilege level at which the CPU must be operating to access the register. A designa-
tion of “S” indicates that supervisor access is required. A designation of “S/U” indicates
that the register can be programmed to the desired privilege level.
Table D-3 SIM Address Map
Access
S
Address 15
$YFFA00
$YFFA02
$YFFA04
$YFFA06
$YFFA08
$YFFA0A
$YFFA0C
$YFFA0E
$YFFA10
$YFFA12
$YFFA14
$YFFA16
$YFFA18
$YFFA1A
$YFFA1C
$YFFA1E
$YFFA20
8 7
0
SIM CONFIGURATION (SIMCR)
FACTORY TEST (SIMTR)
S
S
CLOCK SYNTHESIZER CONTROL (SYNCR)
S
NOT USED
RESET STATUS REGISTER (RSR)
MODULE TEST E (SIMTRE)
S
S
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
S
S
S/U
S/U
S/U
S
PORT E DATA (PORTE0)
PORT E DATA (PORTE1)
PORT E DATA DIRECTION (DDRE)
PORT E PIN ASSIGNMENT (PEPAR)
PORT F DATA (PORTF0)
D
S/U
S/U
S/U
S
PORT F DATA (PORTF1)
PORT F DATA DIRECTION (DDRF)
PORT F PIN ASSIGNMENT (PFPAR)
S
SYSTEM PROTECTION CONTROL
(SYPCR)
S
S
$YFFA22
$YFFA24
$YFFA26
$YFFA28
$YFFA2A
$YFFA2C
$YFFA2E
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
$YFFA3C
$YFFA3E
$YFFA40
$YFFA42
$YFFA44
$YFFA46
$YFFA48
$YFFA4A
$YFFA4C
$YFFA4E
PERIODIC INTERRUPT CONTROL (PICR)
PERIODIC INTERRUPT TIMING (PITR)
S
NOT USED
SOFTWARE SERVICE (SWSR)
NOT USED
S
NOT USED
NOT USED
NOT USED
NOT USED
S
NOT USED
S
NOT USED
S
NOT USED
S
TEST MODULE MASTER SHIFT A (TSTMSRA)
S
TEST MODULE MASTER SHIFT B (TSTMSRB)
TEST MODULE SHIFT COUNT (TSTSC)
S
S
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
S
S/U
TEST MODULE DISTRIBUTED REGISTER (DREG)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
S/U
PORT C DATA (PORTC)
NOT USED
S
S
S
S
S
S
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
MC68331
REGISTER SUMMARY
MOTOROLA
D-13
USER’S MANUAL
Table D-3 SIM Address Map
Access
Address 15
$YFFA50
$YFFA52
$YFFA54
$YFFA56
$YFFA58
$YFFA5A
$YFFA5C
$YFFA5E
$YFFA60
$YFFA62
$YFFA64
$YFFA66
$YFFA68
$YFFA6A
$YFFA6C
$YFFA6E
$YFFA70
$YFFA72
$YFFA74
$YFFA76
$YFFA78
$YFFA7A
$YFFA7C
$YFFA7E
8 7
0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
CHIP-SELECT BASE 1 (CSBAR1)
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
D
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR
D.3.1 SIMCR — Module Configuration Register
$YFFA00
15
14
13
12
0
11
10
0
9
8
7
6
5
0
4
0
3
1
0
EXOFF
FRZSW
FRZBM
SLVEN
SHEN
SUPV
MM
IARB
RESET:
0
0
0
0
DATA11
0
0
0
1
1
0
0
1
1
1
SIMCR controls system configuration. SIMCR can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can only be written once.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters continue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters are disabled, preventing interrupts during software debug.
MOTOROLA
D-14
REGISTER SUMMARY
MC68331
USER’S MANUAL
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SLVEN — Factory Test Mode Enabled
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
SHEN[1:0] — Show Cycle Enable
This field determines what the EBI does with the external bus during internal transfer
operations.
SUPV — Supervisor/Unrestricted Data Space
The SUPV bit places the SIM global registers in either supervisor or user data space.
0 = Registers with access controlled by the SUPV bit are accessible from either the
user or supervisor privilege level.
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
access only.
MM — Module Mapping
D
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
IARB[3:0] — Interrupt Arbitration Field
Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to
prevent SIM interrupts from being discarded during initialization.
D.3.2 SIMTR — System Integration Test Register
$YFFA02
SIMTR is used for factory test only.
D.3.3 SYNCR — Clock Synthesizer Control Register
$YFFA04
15
W
14
X
13
8
7
6
0
5
0
4
3
2
1
0
Y
EDIV
SLIMP
SLOCK
RSTEN
STSIM
STEXT
RESET:
0
0
1
1
1
1
1
1
0
0
0
U
U
0
0
0
SYNCR determines system clock operating frequency and mode of operation.
Clock frequency is determined by SYNCR bit settings as follows:
.
W — Frequency Control (VCO)
0 = Base VCO frequency
1 = VCO frequency multiplied by four
X — Frequency Control Bit (Prescale)
0 = VCO frequency divided by four (base system clock frequency)
1 = VCO frequency divided by two (system clock frequency doubles)
MC68331
REGISTER SUMMARY
MOTOROLA
D-15
USER’S MANUAL
Y[5:0] — Frequency Control (Counter)
The Y field is the initial value for the modulus 64 down counter in the synthesizer feed-
back loop. Values range from 0 to 63.
EDIV — ECLK Divide Rate
0 = ECLK is system clock divided by 8
1 = ECLK is system clock divided by 16
SLIMP — Limp Mode
0 = External crystal is VCO reference
1 = Loss of crystal reference
SLOCK — Synthesizer Lock
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency or system clock is external.
RSTEN — Reset Enable
0 = Loss of reference causes the MCU to operate in limp mode.
1 = Loss of reference causes system reset.
STSIM — Stop Mode System Integration Clock
D
0 = SIM clock driven by an external source and VCO off during low-power stop.
1 = SIM clock driven by VCO during low-power stop.
STEXT — Stop Mode External Clock
0 = CLKOUT held low during low-power stop.
1 = CLKOUT driven from SIM clock during low-power stop.
D.3.4 RSR — Reset Status Register
$YFFA07
15
8
7
6
5
4
3
0
2
1
0
NOT USED
EXT
POW
SW
HLT
LOC
SYS
TST
RSR contains a status bit for each reset source in the MCU. RSR is updated when the
MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple
sources assert reset signals at the same time, more than one bit in RSR may be set.
This register can be read at any time; a write has no effect.
EXT — External Reset
Reset caused by an external signal.
POW — Power-Up Reset
Reset caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset caused by the halt monitor.
MOTOROLA
D-16
REGISTER SUMMARY
MC68331
USER’S MANUAL
LOC — Loss of Clock Reset
Reset caused by loss of clock frequency reference.
SYS — System Reset
Reset caused by a RESET instruction.
TST — Test Submodule Reset
Reset caused by the test submodule. Used during system test only.
D.3.5 SIMTRE — System Integration Test Register (ECLK)
$YFFA08
Register is used for factory test only.
D.3.6 PORTE0/PORTE1 — Port E Data Register
$YFFA11, $YFFA13
15
8
7
6
5
4
3
2
1
0
NOT USED
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
U
U
U
U
U
U
U
U
D
PORTE is an internal data latch that can be accessed at two locations. PORTE can be
read or written at any time. If a pin in I/O port E is configured as an output, the corre-
sponding bit value is driven out on the pin. When a pin is configured for output, a read
of PORTE returns the latched bit value; when a pin is configured for input, a read re-
turns the pin logic level.
D.3.7 DDRE — Port E Data Direction Register
$YFFA15
15
8
7
6
5
4
3
2
1
0
NOT USED
DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0
RESET:
0
0
0
0
0
0
0
0
Bits in this register control the direction of the port E pin drivers when pins are config-
ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time.
D.3.8 PEPAR — Port E Pin Assignment Register
$YFFA17
15
8
7
6
5
4
3
2
1
0
NOT USED
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
RESET:
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
DATA8
Bits in this register determine the function of port E pins. Setting a bit assigns the cor-
responding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.
MC68331
REGISTER SUMMARY
MOTOROLA
D-17
USER’S MANUAL
Table D-4 Port E Pin Assignments
PEPAR Bit
Port E Signal
PE7
Bus Control Signal
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
SIZ1
SIZ0
PE6
PE5
AS
PE4
DS
PE3
RMC
PE2
AVEC
DSACK1
DSACK0
PE1
PE0
D.3.9 PORTF0/PORTF1 — Port F Data Register
$YFFA19, $YFFA1B
15
8
7
6
5
4
3
2
1
0
NOT USED
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
U
U
U
U
U
U
U
PORTF is an internal data latch that can be accessed at two locations. It can be read
or written at any time. If a pin in I/O port F is configured as an output, the corresponding
bit value is driven out on the pin. When a pin is configured for output, a read of PORTF
returns the latched bit value; when a pin is configured for input, a read returns the pin
logic level.
D
D.3.10 DDRF — Port F Data Direction Register
$YFFA1D
15
8
7
6
5
4
3
2
1
0
NOT USED
DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0
RESET:
0
0
0
0
0
0
0
0
Bits in this register control the direction of the port F pin drivers when pins are config-
ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time.
D.3.11 PFPAR — Port F Pin Assignment Register
$YFFA1F
15
8
7
6
5
4
3
2
1
0
NOT USED
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
RESET:
DATA9
DATA9
DATA9
DATA9
DATA9
DATA9
DATA9
DATA9
Bits in this register determine the function of port F pins. Setting a bit assigns the cor-
responding pin to a control signal; clearing a bit assigns the pin to port F.
MOTOROLA
D-18
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-5 Port F Pin Assignments
PFPAR Field
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
Port F Signal
PF7
Control Signal
IRQ7
PF6
IRQ6
PF5
IRQ5
PF4
IRQ4
PF3
IRQ3
PF2
IRQ2
PF1
IRQ1
PF0
MODCLK
D.3.12 SYPCR — System Protection Control Register
$YFFA21
15
8
7
6
5
0
4
0
3
2
1
0
NOT USED
SWE
SWP
SWT
HME
BME
BMT
RESET:
1
MODCLK
0
0
0
0
SYPCR controls system monitor functions, software watchdog clock prescaling, and
bus monitor timing. This register can be written once following power-on or reset.
D
SWE — Software Watchdog Enable
0 = Software watchdog disabled
1 = Software watchdog enabled
SWP — Software Watchdog Prescale
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
SWT[1:0] — Software Watchdog Timing
This field selects software watchdog time-out period.
Table D-6 Software Watchdog Ratio
SWP
SWT
00
Ratio
9
0
0
0
0
1
1
1
1
2
11
01
2
13
10
2
15
11
2
18
00
2
20
01
2
22
10
2
24
11
2
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
MC68331
REGISTER SUMMARY
MOTOROLA
D-19
USER’S MANUAL
BME — Bus Monitor External Enable
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
BMT[1:0] — Bus Monitor Timing
This field selects bus monitor time-out period.
Table D-7 Bus Monitor Period
BMT
00
Bus Monitor Time-out Period
64 System Clocks
01
32 System Clocks
10
16 System Clocks
11
8 System Clocks
D.3.13 PICR — Periodic Interrupt Control Register
$YFFA22
15
0
14
0
13
0
12
0
11
0
10
8
7
0
PIRQL
0
PIV
RESET:
D
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Contains information concerning periodic interrupt priority and vectoring. PICR[10:0]
can be read or written at any time. PICR[15:11] are unimplemented and always return
zero.
PIRQL[2:0] — Periodic Interrupt Request Level
This field determines the priority of periodic interrupt requests.
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the periodic interrupt vector number supplied by the SIM
when the CPU acknowledges an interrupt request.
D.3.14 PITR — Periodic Interrupt Timer Register
$YFFA24
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
0
0
PTP
PITM
RESET:
0
0
0
0
0
0
0
MODCLK
0
0
0
0
0
0
0
Contains the count value for the periodic timer. This register can be read or written at
any time.
PTP — Periodic Timer Prescaler Control
0 = Periodic timer clock not prescaled
1 = Periodic timer clock prescaled by a value of 512
PITM[7:0] — Periodic Interrupt Timing Modulus
This is the 8-bit timing modulus used to determine periodic interrupt rate. Use the fol-
lowing expression to calculate timer period.
MOTOROLA
D-20
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.3.15 SWSR — Software Service Register
$YFFA27
15
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
NOT USED
RESET:
0
0
0
0
0
0
0
0
When the software watchdog is enabled, a service sequence must be written to this
register within a specific interval. When read, SWSR always returns $00. Register
shown with read value.
D.3.16 TSTMSRA — Master Shift Register A
$YFFA30
$YFFA32
$YFFA34
$YFFA36
$YFFA38
$YFFA3A
$YFFA41
Register is used for factory test only.
D.3.17 TSTMSRB — Master Shift Register B
Register is used for factory test only.
D.3.18 TSTSC — Test Module Shift Count
D
Register is used for factory test only.
D.3.19 TSTRC — Test Module Repetition Count
Register is used for factory test only.
D.3.20 CREG — Test Submodule Control Register
Register is used for factory test only.
D.3.21 DREG — Distributed Register
Register is used for factory test only.
D.3.22 PORTC — Port C Data Register
15
8
7
0
6
5
4
3
2
1
0
NOT USED
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
0
1
1
1
1
1
1
1
PORTC latches data for chip-select pins that are used for discrete output.
D.3.23 CSPAR0 — Chip Select Pin Assignment Register 0
$YFFA44
15
0
14
0
13
12
11
10
9
8
7
6
5
4
1
3
2
1
1
0
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
RESET:
0
0
DATA2
1
DATA2
1
DATA2
1
DATA1
1
DATA1
DATA1
1
DATA0
MC68331
REGISTER SUMMARY
MOTOROLA
D-21
USER’S MANUAL
Table D-8 CSPAR0 Pin Assignments
CSPAR0 Field
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
CSPAR0 Signal
CS5
Alternate Signal
Discrete Output
FC2
FC1
FC0
BGACK
BG
PC2
PC1
PC0
—
CS4
CS3
CS2
CS1
—
CS0
BR
—
CSBOOT
—
—
Contains seven 2-bit fields, CSPA0[6:1] and CSBOOT, that determine the functions of
corresponding chip-select pins. CSPAR0[15:14] are not used. These bits always read
zero; write has no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have
no effect. The alternate functions can be enabled by data bus mode selection during
reset.
D.3.24 CSPAR1 — Chip Select Pin Assignment Register 1
$YFFA46
15
0
14
0
13
0
12
0
11
0
10
0
9
8
7
6
5
4
1
3
2
1
1
0
D
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
RESET:
0
0
0
0
0
0
DATA7
1
DATA6
1
DATA5
DATA4
DATA3
1
Table D-9 CSPAR1 Pin Assignments
CSPAR1 Field
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
CSPAR1 Signal
Alternate Signal
ADDR23
Discrete Output
CS10
CS9
CS8
CS7
CS6
ECLK
PC6
PC5
PC4
PC3
ADDR22
ADDR21
ADDR20
ADDR19
Contains five 2-bit fields (CSPA1[4:0]) that determine the functions of corresponding
chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; write has
no effect. The CSPAR1 pin assignments table shows alternate functions that can be
enabled by data bus mode selection during reset.
Table D-10 CSPAR0 and CSPAR1 Pin Assignment Field Encoding
Bit Field
Description
00
01
10
11
Discrete Output*
Alternate Function*
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
*Does not apply to the CSBOOT field
MOTOROLA
D-22
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.3.25 CSBARBT — Chip Select Base Address Register Boot ROM
$YFFA48
CSBAR[0:10] — Chip Select Base Address Registers $YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
0
ADDR
23
ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR
BLKSZ
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
RESET:
0
0
Each chip-select pin has an associated base address register. A base address is the
lowest address in the block of addresses enabled by a chip select. CSBARBT contains
the base address for selection of a bootstrap peripheral memory device. Bit and field
definition for CSBARBT and CSBAR[0:10] are the same, but reset block sizes differ.
ADDR[23:11] — Base Address
This field sets the starting address of a particular address space.
BLKSZ — Block Size
This field determines the size of the block above the base address that is enabled by
the chip select.
D
Table D-11 Block Size Encoding
BLKSZ[2:0]
000
Block Size
2 K
Address Lines Compared
ADDR[23:11]
001
8 K
ADDR[23:13]
010
16 K
ADDR[23:14]
011
64 K
ADDR[23:16]
100
128 K
256 K
512 K
1 M
ADDR[23:17]
101
ADDR[23:18]
110
ADDR[23:19]
111
ADDR[23:20]
D.3.26 CSORBT — Chip Select Option Register Boot ROM
CSOR[0:10] — Chip Select Option Registers
$YFFA4A
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
6
5
4
0
3
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
0
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Contain parameters that support bootstrap operations from peripheral memory devic-
es. Bit and field definitions for CSORBT and CSOR[0:10] are the same.
MODE — Asynchronous Bus/Synchronous E-clock Mode
Synchronous mode cannot be used with internally generated autovectors.
0 = Asynchronous mode selected
1 = Synchronous mode selected
BYTE — Upper/Lower Byte Option
The value in this field determines whether a select signal can be asserted.
MC68331
REGISTER SUMMARY
MOTOROLA
D-23
USER’S MANUAL
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for
both read and write.
STRB — Address Strobe/Data Strobe
0 = Address strobe
1 = Data strobe
DSACK — Data Strobe Acknowledge
This field specifies the source of DSACK in asynchronous bus mode and controls wait
state insertion.
SPACE — Address Space Select
This field selects an address space to be used by the chip-select logic.
IPL — Interrupt Priority Level
This field determines interrupt priority level when a chip select is used for interrupt ac-
knowledge. It does not affect CPU interrupt recognition.
AVEC — Autovector Enable
Do not enable autovector support when in synchronous mode.
0 = External interrupt vector enabled
1 = Autovector enabled
D
Table D-12 Option Register Function Summary
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
0 = ASYNC 00 = Disable 00 = Rsvd 0 = AS 0000 = 0 WAIT 00 = CPU SP
000 = All
0 = Off
1 = SYNC
01 = Lower
10 = Upper
11 = Both
01 = Read 1 = DS 0001 = 1 WAIT 01 = User SP 001 = Priority 1 1 = On
10 = Write
11 = Both
0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
0011 = 3 WAIT 11 = S/U SP 011 = Priority 3
0100 = 4 WAIT
0101 = 5 WAIT
0110 = 6 WAIT
0111 = 7 WAIT
1000 = 8 WAIT
1001 = 9 WAIT
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1110 = F term
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7
1111 = External
MOTOROLA
D-24
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.4 Queued Serial Module
Table D-13 displays the QSM address map. The column labeled “Access” indicates
the privilege level at which the CPU must be operating to access the register. A des-
ignation of “S” indicates that supervisor access is required: a designation of “S/U” in-
dicates that the register can be programmed to the desired privilege level.
Table D-13 QSM Address Map
Access
S
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
15
8 7
0
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
S
S
QSM INTERRUPT LEVEL (QILR)
QSM INTERRUPT VECTOR (QIVR)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
NOT USED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
PQS PIN ASSIGNMENT (PQSPAR)
PQS DATA (PORTQS)
D
PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3)
SPI STATUS (SPSR)
$YFFC20–
$YFFCFF
NOT USED
S/U
QUEUE RAM
$YFFD00–
$YFFD1F
RECEIVE RAM (RR[0:F])
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
S/U
QUEUE RAM
$YFFD20–
$YFFD3F
S/U
QUEUE RAM
$YFFD40–
$YFFD4F
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.4.1 QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
0
11
0
10
0
9
0
8
0
7
6
0
5
0
4
0
3
0
0
STOP
FRZ1
FRZ0
SUPV
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
When STOP is set, the QSM enters low-power stop mode. System clock input to the
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
MC68331
REGISTER SUMMARY
MOTOROLA
D-25
USER’S MANUAL
valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during
reset. The SCI receiver and transmitter must be disabled before STOP is set. To stop
the QSPI, set the HALT bit in SPCR3, wait until the HALTA flag is set, then set STOP.
FRZ[1:0] — Freeze Control
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters background mode.
FRZ0 is reserved for future use.
SUPV — Supervisor/Unrestricted
0 = Supervisor access
1 = User access
IARB — Interrupt Arbitration
Each module that generates interrupts must have an IARB value. IARB values are
used to arbitrate between interrupt requests of the same priority.
D.4.2 QTEST — QSM Test Register
$YFFC02
D
Used for factory test only.
D.4.3 QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
$YFFC04
$YFFC05
15
0
14
0
13
11
10
8
7
0
0
ILQSPI
0
ILSCI
0
INTV
RESET:
0
0
0
0
0
0
0
0
0
1
1
1
1
The values of the ILQSPI and ILSCI fields in QILR determine the priority of QSPI and
SCI interrupt requests. QIVR determines the value of the interrupt vector number the
QSM supplies when it responds to an interrupt acknowledge cycle. At reset, QIVR is
initialized to vector number $0F, the uninitialized interrupt vector number. To use in-
terrupt-driven serial communication, a user-defined vector number must be written to
QIVR.
ILQSPI — Interrupt Level for QSPI
When an interrupt request is made, ILQSPI value determines which of the interrupt re-
quest signals is asserted; when a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. ILQS-
PI must have a value in the range $0 (lowest priority) to $7 (highest priority).
ILSCI — Interrupt Level for SCI
When an interrupt request is made, ILSCI value determines which of the interrupt re-
quest signals is asserted. When a request is acknowledged, the QSM compares this
value to a mask value supplied by the CPU32 to determine whether to respond. The
field must have a value in the range $0 (lowest priority) to $7 (highest priority).
If ILQSPI and ILSCI have the same nonzero value, and both submodules simulta-
neously request interrupt service, the QSPI has priority.
MOTOROLA
D-26
REGISTER SUMMARY
MC68331
USER’S MANUAL
INTV[7:0] — Interrupt Vector Number
The values of INTV[7:1] are the same for both QSPI and SCI interrupt requests; the
value of INTV0 used during an interrupt acknowledge cycle is supplied by the QSM.
INTV0 is at logic level zero during an SCI interrupt and at logic level one during a QSPI
interrupt. A write to INTV0 has no effect. Reads of INTV0 return a value of one.
D.4.4 SCCR0 — SCI Control Register 0
$YFFC08
15
0
14
0
13
0
12
0
SCBR
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
SCCR0 contains the SCI baud rate selection field. Baud rate must be set before the
SCI is enabled. The CPU32 can read and write SCCR0 at any time. Changing the val-
ue of SCCR0 bits during a transfer operation can disrupt operation.
SCBR — SCI Baud Rate
SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of
zero to SCBR disables the baud rate generator. Baud clock rate is calculated as fol-
lows:
D
$YFFC0A
D.4.5 SCCR1 — SCI Control Register 1
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOOPS
WOMS
ILT
PT
PE
M
WAKE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCCR1 contains SCI configuration parameters, including transmitter and receiver en-
able bits, interrupt enable bits, and operating mode enable bits. The CPU can read and
write SCCR0 at any time. The SCI can modify the RWU bit under certain circumstanc-
es. Changing the value of SCCR1 bits during a transfer operation can disrupt opera-
tion.
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
MC68331
REGISTER SUMMARY
MOTOROLA
D-27
USER’S MANUAL
PT — Parity Type
0 = Even parity
1 = Odd parity
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
M — Mode Select
0 = 10-bit SCI frame
1 = 11-bit SCI frame
WAKE — Wakeup by Address Mark
0 = SCI receiver awakened by idle-line detection
1 = SCI receiver awakened by address mark (last bit set)
TIE — Transmit Interrupt Enable
0 = SCI TDRE interrupts inhibited
1 = SCI TDRE interrupts enabled
TCIE — Transmit Complete Interrupt Enable
0 = SCI TC interrupts inhibited
D
1 = SCI TC interrupts enabled
RIE — Receiver Interrupt Enable
0 = SCI RDRF and OR interrupts inhibited
1 = SCI RDRF and OR interrupts enabled
ILIE — Idle-Line Interrupt Enable
0 = SCI IDLE interrupts inhibited
1 = SCI IDLE interrupts enabled
TE — Transmitter Enable
0 = SCI transmitter disabled (TXD pin can be used as I/O)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter)
RE — Receiver Enable
0 = SCI receiver disabled (status bits inhibited)
1 = SCI receiver enabled
RWU — Receiver Wakeup
0 = Normal receiver operation (received data recognized)
1 = Wakeup mode enabled (received data ignored until awakened)
SBK — Send Break
0 = Normal operation
1 = Break frame(s) transmitted after completion of current frame
MOTOROLA
D-28
REGISTER SUMMARY
MC68331
USER’S MANUAL
D.4.6 SCSR — SCI Status Register
$YFFC0C
15
9
8
7
6
5
4
3
2
1
0
NOT USED
RESET:
TDRE
TC
RDRF
RAF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
0
SCSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCI hardware or by a CPU32 read/write sequence. The sequence consists of
reading SCSR, then reading or writing SCDR.
If an internal SCI signal for setting a status bit comes after the CPU32 has read the
asserted status bits, but before the CPU has written or read SCDR, the newly set sta-
tus bit is not cleared. SCSR must be read again with the bit set and SCDR must be
written or read before the status bit is cleared.
A long-word read can consecutively access both SCSR and SCDR. This action clears
receive status flag bits that were set at the time of the read, but does not clear TDRE
or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any
status bit already set in either byte are cleared on a subsequent read or write of regis-
ter SCDR.
D
TDRE — Transmit Data Register Empty
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to register TDR.
TC — Transmit Complete
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
RDRF — Receive Data Register Full
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
RAF — Receiver Active
0 = SCI receiver is idle.
1 = SCI receiver is busy.
IDLE — Idle-Line Detected
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
OR — Overrun Error
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
NF — Noise Error Flag
0 = No noise detected on the received data
1 = Noise occurred on the received data.
MC68331
REGISTER SUMMARY
MOTOROLA
D-29
USER’S MANUAL
FE — Framing Error
0 = No framing error on the received data
1 = Framing error or break occurred on the received data.
PF — Parity Error
0 = No parity error on the received data
1 = Parity error occurred on the received data.
D.4.7 SCDR — SCI Data Register
$YFFC0E
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
RESET:
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
SCDR consists of two data registers located at the same address. RDR is a read-only
register that contains data received by the SCI serial interface. Data comes into the
receive serial shifter and is transferred to RDR. TDR is a write-only register that con-
tains data to be transmitted. Data is first written to TDR, then transferred to the transmit
serial shifter, where additional format bits are added before transmission. R[7:0]/T[7:0]
contain either the first eight data bits received when SCDR is read, or the first eight
data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is con-
figured for 9-bit operation. When the SCI is configured for 8-bit operation, R8/T8 have
no meaning or effect.
D
D.4.8 PORTQS — Port QS Data Register
$YFFC15
15
8
7
6
5
4
3
2
1
0
NOT USED
PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0
RESET:
0
0
0
0
0
0
0
0
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data
present on the pins. To avoid driving undefined data, first write a byte to PORTQS,
then configure DDRQS.
D.4.9 PQSPAR — PORT QS Pin Assignment Register
DDRQS — PORT QS Data Direction Register
$YFFC16
$YFFC17
15
0
14
13
12
11
10
0
9
8
7
6
5
4
3
2
1
0
PQSPA6 PQSPA5 PQSPA4 PQSPA3
PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; set-
ting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI.
MOTOROLA
D-30
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-14 PQSPAR Pin Assignments
PQSPAR Field
PQSPAR Bit
Pin Function
PQSPA0
PQSPA1
PQSPA2
PQSPA3
PQSPA4
PQSPA5
PQSPA6
PQSPA7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PQS0
MISO
PQS1
MOSI
1
PQS2
SCK
PQS3
PCS0/SS
PQS4
PCS1
PQS5
PCS2
PQS6
PCS3
2
PQS7
TXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case
it becomes SPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 = 1), in
which case it becomes SCI serial output TXD.
D
DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the cor-
responding pin an input; setting a bit makes the pin an output. DDRQS affects both
QSPI function and I/O function.
Table D-15 Effect of DDRQS on PORTQS Pins
Pin
DDRQS Bit
Pin Function
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
Digital Input
Digital Output
PQS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PQS1
PQS2
PQS2
PQS3
PQS4
PQS5
PQS6
PQS7
MC68331
REGISTER SUMMARY
MOTOROLA
D-31
USER’S MANUAL
Table D-16 Effect of DDRQS on QSM Pin Function
QSM Pin
Mode
DDRQS
Bit
Bit
State
Pin Function
MISO
Master
DDQS0
DDQS1
DDQS2
DDQS3
0
1
Serial Data Input to QSPI
Disables Data Input
Slave
Master
Slave
0
Disables Data Output
Serial Data Output from QSPI
Disables Data Output
Serial Data Output from QSPI
Serial Data Input to QSPI
Disables Data Input
1
MOSI
0
1
0
1
1
SCK
Master
Slave
0
Disables Clock Output
Clock Output from QSPI
Clock Input to QSPI
1
0
1
Disables Clock Input
Assertion Causes Mode Fault
Chip-Select Output
PCS0/SS
PCS[3:1]
Master
Slave
0
1
0
QSPI Slave Select Input
Disables Select Input
Disables Chip-Select Output
Chip-Select Output
1
D
Master
Slave
DDQS
[4:6]
0
1
0
Inactive
1
Inactive
2
TXD
Transmit
Receive
DDQS7
None
X
NA
Serial Data Output from SCI
Serial Data Input to SCI
RXD
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI
serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE in SCCR1 =1), in which case it
becomes SCI serial output TXD.
DDRQS determines the direction of the TXD pin only when the SCI transmitter is dis-
abled. When the SCI transmitter is enabled, the TXD pin is an output.
D.4.10 SPCR0 — QSPI Control Register 0
$YFFC18
15
MSTR
RESET:
0
14
13
10
9
8
7
0
0
WOMQ
BITS
CPOL CPHA
SP
0
0
0
0
0
0
1
0
0
0
0
1
0
0
SPCR0 contains parameters for configuring the QSPI and enabling various modes of
operation. The CPU has read/write access to SPCR0, but the QSM has read access
only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to
SPCR0 while the QSPI is enabled disrupts operation.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device.
1 = QSPI is system master.
MOTOROLA
D-32
REGISTER SUMMARY
MC68331
USER’S MANUAL
WOMQ — Wired-OR Mode for QSPI Pins
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
BITS — Bits Per Transfer
The BITS field determines the number of serial data bits transferred.
CPOL — Clock Polarity
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
CPHA — Clock Phase
0 =Data captured on the leading edge of SCK and changed on the following edge
of SCK.
1 =Data is changed on the leading edge of SCK and captured on the following
edge of SCK.
SPBR — Serial Clock Baud Rate
QSPI baud rate is selected by writing a value from 2 to 255 into SPBR. Giving BR a
value of zero or one disables SCK (disable state determined by CPOL).
D
D.4.11 SPCR1 — QSPI Control Register 1
$YFFC1A
15
14
8
7
0
0
SPE
DSCKL
0
DTL
RESET:
0
0
0
0
1
0
0
0
0
0
0
1
0
0
SPCR1 enables the QSPI and specified transfer delays. The CPU32 has read/write
access to SPCR1, but the QSM has read access only to all bits but enable bit SPE.
SPCR1 must be written last during initialization because it contains SPE. Writing a
new value to SPCR1 while the QSPI is enabled disrupts operation.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay
from PCS valid to SCK transition. PCS can be any of the four peripheral chip-select
pins.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after
serial transfer.
MC68331
REGISTER SUMMARY
MOTOROLA
D-33
USER’S MANUAL
D.4.12 SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
0
11
8
0
7
0
6
0
5
0
4
0
3
0
0
SPIFIE
WREN
WRTO
ENDQP
NEWQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt
enable bit. The CPU32 has read/write access to SPCR2, but the QSM has read ac-
cess only. SPCR2 is buffered. New SPCR2 values become effective only after com-
pletion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to
restart at the designated location. SPCR2 reads return the value of the register, not
the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
D
WRTO — Wrap To
0 = Wrap to pointer address $0
1 = Wrap to address in NEWQP
ENDQP — Ending Queue Pointer
This field contains the last QSPI queue address.
NEWQP — New Queue Pointer Value
This field contains the first QSPI queue address.
D.4.13 SPCR3 — QSPI Control Register 3
SPSR — QSPI Status Register
$YFFC1E
$YFFC1F
15
0
14
0
13
0
12
0
11
0
10
9
8
7
6
5
4
0
3
0
0
LOOPQ
HMIE
HALT
SPIF
MODF
HALTA
CPTQP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enables, and
the halt control bit. The CPU has read/write access to SPCR3, but the QSM has read
access only. SPCR3 must be initialized before QSPI operation begins. Writing a new
value to SPCR3 while the QSPI is enabled disrupts operation. SPSR contains infor-
mation concerning the current serial transmission. Only the QSPI can set bits in SPSR.
The CPU reads SPSR to obtain QSPI status information and writes it to clear status
flags.
MOTOROLA
D-34
REGISTER SUMMARY
MC68331
USER’S MANUAL
LOOPQ — QSPI Loop Mode
0 = Feedback path disabled
1 = Feedback path enabled
HMIE — HALTA and MODF Interrupt Enable
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
HALT — Halt
0 = Halt not enabled
1 = Halt enabled
SPIF — QSPI Finished Flag
0 = QSPI not finished
1 = QSPI finished
MODF — Mode Fault Flag
0 =Normal operation
1 =Another SPI node requested to become the network SPI master while the QSPI
was enabled in master mode (SS input taken low).
D
HALTA — Halt Acknowledge Flag
0 = QSPI not halted
1 = QSPI halted
CPTQP — Completed Queue Pointer
CPTQP points to the last command executed. It is updated when the current command
is complete. When the first command in a queue is executing, CPTQP contains either
the reset value ($0) or a pointer to the last command completed in the previous queue.
D.4.14 RR[0:F] — Receive Data RAM
$YFFD00–$YFFD0E
Data received by the QSPI is stored in this segment. The CPU32 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the indi-
vidual queue entry. The CPU can access the data using byte, word, or long-word ad-
dressing.
D.4.15 TR[0:F] — Transmit Data RAM
$YFFD20–$YFFD3E
Data that is to be transmitted by the QSPI is stored in this segment. The CPU32 nor-
mally writes one word of data into this segment for each queue command to be exe-
cuted.
Information to be transmitted must be written to transmit data RAM in a right-justified
format. The QSPI cannot modify information in the transmit data RAM. The QSPI cop-
ies the information to its data serializer for transmission. Information remains in trans-
mit RAM until overwritten.
MC68331
REGISTER SUMMARY
MOTOROLA
D-35
USER’S MANUAL
D.4.16 CR[0:F] — Command RAM
$YFFD40–$YFFD4F
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
COMMAND CONTROL
*The PCS0 bit represents the dual-function PCS0/SS.
PERIPHERAL CHIP SELECT
Command RAM is used by the QSPI when in master mode. The CPU32 writes one
byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from
the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
D
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
BITSE — Bits per Transfer Enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0
DT — Delay after Transfer
The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing
with peripherals that have a latency requirement. The delay between transfers is de-
termined by the SPCR1 DTL field.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK transition is one-half SCK.
1 = SPCR1 DSCKL field specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Peripheral chip-select bits are used to select an external device for serial data transfer.
More than one peripheral chip select may be activated at a time, and more than one
peripheral chip can be connected to each PCS pin, provided proper fanout is ob-
served. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode
serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault oc-
curs.
MOTOROLA
D-36
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-17 MC68331 Module Address Map
(Assumes SIMCR MM = 1)
GPT
Access
S
Address 15
8 7
0
$FFF900
$FFF902
$FFF904
$FFF906
$FFF908
$FFF90A
$FFF90C
$FFF90E
$FFF910
$FFF912
$FFF914
$FFF916
$FFF918
$FFF91A
$FFF91C
$FFF91E
$FFF920
$FFF922
$FFF924
$FFF926
$FFF928
$FFF92A
$FFF92C
GPT MODULE CONFIGURATION (GPTMCR)
(RESERVED FOR TEST)
S
S
INTERRUPT CONFIGURATION (ICR)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
PGP DATA DIRECTION (DDRGP)
PGP DATA (PORTGP)
OC1 ACTION MASK (OC1M)
OC1 ACTION DATA (OC1D)
TIMER COUNTER (TCNT)
PA CONTROL (PACTL)
PA COUNTER (PACNT)
INPUT CAPTURE 1 (TIC1)
INPUT CAPTURE 2 (TIC2)
INPUT CAPTURE 3 (TIC3)
OUTPUT COMPARE 1 (TOC1)
OUTPUT COMPARE 2 (TOC2)
OUTPUT COMPARE 3 (TOC3)
OUTPUT COMPARE 4 (TOC4)
INPUT CAPTURE 4/OUTPUT COMPARE 5 (TI4/O5)
D
TIMER CONTROL 1 (TCTL1)
TIMER CONTROL 2 (TCTL2)
TIMER MASK 2 (TMSK2)
TIMER FLAG 2 (TFLG2)
TIMER MASK 1 (TMSK1)
TIMER FLAG 1 (TFLG1)
FORCE COMPARE (CFORC)
PWM CONTROL A (PWMA)
PWM CONTROL C (PWMC)
PWM CONTROL B (PWMB)
PWM COUNT (PWMCNT)
PWMA BUFFER (PWMBUFA)
PWMB BUFFER (PWMBUFB)
GPT PRESCALER (PRESCL)
$FFF92E –
$FFF93F
NOT USED
SIM
Access
S
Address 15
$FFFA00
$FFFA02
$FFFA04
$FFFA06
$FFFA08
$FFFA0A
$FFFA0C
$FFFA0E
$FFFA10
$FFFA12
$FFFA14
$FFFA16
$FFFA18
$FFFA1A
$FFFA1C
$FFFA1E
$FFFA20
8 7
0
MODULE CONFIGURATION (SIMCR)
FACTORY TEST (SIMTR)
S
S
CLOCK SYNTHESIZER CONTROL (SYNCR)
S
NOT USED
RESET STATUS (RSR)
MODULE TEST E (SIMTRE)
S
S
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
S
S
S/U
S/U
S/U
S
PORTE DATA (PORTE0)
PORTE DATA (PORTE1)
PORTE DATA DIRECTION (DDRE)
PORTE PIN ASSIGNMENT (PEPAR)
PORTF DATA (PORTF0)
S/U
S/U
S/U
S
PORTF DATA (PORTF1)
PORTF DATA DIRECTION (DDRF)
PORTF PIN ASSIGNMENT (PFPAR)
S
SYSTEM PROTECTION CONTROL
(SYPCR)
S
$FFFA22
PERIODIC INTERRUPT CONTROL (PICR)
MC68331
REGISTER SUMMARY
MOTOROLA
D-37
USER’S MANUAL
Table D-17 MC68331 Module Address Map, (Continued)
(Assumes SIMCR MM = 1)
SIM (Continued)
Access
Address 15
$FFFA24
$FFFA26
$FFFA28
$FFFA2A
$FFFA2C
$FFFA2E
$FFFA30
$FFFA32
$FFFA34
$FFFA36
$FFFA38
$FFFA3A
$FFFA3C
$FFFA3E
$FFFA40
$FFFA42
$FFFA44
$FFFA46
$FFFA48
$FFFA4A
$FFFA4C
$FFFA4E
$FFFA50
$FFFA52
$FFFA54
$FFFA56
$FFFA58
$FFFA5A
$FFFA5C
$FFFA5E
$FFFA60
$FFFA62
$FFFA64
$FFFA66
$FFFA68
$FFFA6A
$FFFA6C
$FFFA6E
$FFFA70
$FFFA72
$FFFA74
$FFFA76
$FFFA78
$FFFA7A
$FFFA7C
$FFFA7E
8 7
0
S
S
PERIODIC INTERRUPT TIMING (PITR)
NOT USED
SOFTWARE SERVICE (SWSR)
NOT USED
S
NOT USED
NOT USED
NOT USED
NOT USED
S
NOT USED
S
NOT USED
S
NOT USED
S
TEST MODULE MASTER SHIFT A (TSTMSRA)
S
TEST MODULE MASTER SHIFT B (TSTMSRB)
TEST MODULE SHIFT COUNT (TSTSC)
TEST MODULE REPETITION COUNTER (TSTRC)
TEST MODULE CONTROL (CREG)
S
S
S
S/U
TEST MODULE DISTRIBUTED (DREG)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
S/U
PORT C DATA (PORTC)
NOT USED
D
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
CHIP-SELECT PIN ASSIGNMENT (CSPAR0)
CHIP-SELECT PIN ASSIGNMENT (CSPAR1)
CHIP-SELECT BASE BOOT (CSBARBT)
CHIP-SELECT OPTION BOOT (CSORBT)
CHIP-SELECT BASE 0 (CSBAR0)
CHIP-SELECT OPTION 0 (CSOR0)
CHIP-SELECT BASE 1 (CSBAR1)
CHIP-SELECT OPTION 1 (CSOR1)
CHIP-SELECT BASE 2 (CSBAR2)
CHIP-SELECT OPTION 2 (CSOR2)
CHIP-SELECT BASE 3 (CSBAR3)
CHIP-SELECT OPTION 3 (CSOR3)
CHIP-SELECT BASE 4 (CSBAR4)
CHIP-SELECT OPTION 4 (CSOR4)
CHIP-SELECT BASE 5 (CSBAR5)
CHIP-SELECT OPTION 5 (CSOR5)
CHIP-SELECT BASE 6 (CSBAR6)
CHIP-SELECT OPTION 6 (CSOR6)
CHIP-SELECT BASE 7 (CSBAR7)
CHIP-SELECT OPTION 7 (CSOR7)
CHIP-SELECT BASE 8 (CSBAR8)
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
CHIP-SELECT OPTION 10 (CSOR10)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
MOTOROLA
D-38
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-17 MC68331 Module Address Map, (Continued)
(Assumes SIMCR MM = 1)
QSM
Access
S
Address 15
$FFFC00
$FFFC02
$FFFC04
$FFFC06
$FFFC08
$FFFC0A
$FFFC0C
$FFFC0E
$FFFC10
$FFFC12
$FFFC14
$FFFC16
$FFFC18
$FFFC1A
$FFFC1C
$FFFC1E
8 7
0
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
S
S
QSM INTERRUPT LEVEL (QILR)
QSM INTERRUPT VECTOR (QIVR)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
NOT USED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
PQS PIN ASSIGNMENT (PQSPAR)
PQS DATA (PORTQS)
PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3)
SPI STATUS (SPSR)
D
$FFFC20–
$FFFCFF
NOT USED
S/U
QUEUE
RAM
$FFFD00–
$FFFD1F
RECEIVE RAM (RR[0:F])
S/U
QUEUE
RAM
$FFFD20–
$FFFD3F
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
S/U
QUEUE
RAM
$FFFD40–
$FFFD4F
MC68331
REGISTER SUMMARY
MOTOROLA
D-39
USER’S MANUAL
Table D-18 Register Bit and Field Mnemonics
Mnemonic
Name
Base Address
Register Location
ADDR[23:11]
AVEC
CSBAR[0:10], CSBARBT
CSOR[0:10], CSORBT
SPCR0
Autovector Enable
BITS
Bits Per Transfer
BITSE
Bits Per Transfer Enable
Block Size
CR[0:F]
BLKSZ
BME
CSBAR[0:10], CSBARBT
SYPCR
Bus Monitor External Enable
Bus Monitor Timing
Upper/Lower Byte Option
Carry Flag
BMT[1:0]
BYTE
SYPCR
CSOR[0:10], CSORBT
CCR
C
CONT
Continue
CR[0:F]
CPHA
Clock Phase
SPCR0
CPOL
Clock Polarity
SPCR0
CPROUT
CPR[2:0]
CPTQP
CSPA0[6:1]
CSPA1[4:0]
CSBOOT
DDE[7:0]
DDF[7:0]
DDRGP[7:0]
DDQS[7:0]
DSACK
DSCK
Capture/Compare Clock Output Enable
Timer Prescaler/PCLK Select Field
Completed Queue Pointer
Chip-Select [6:1]
TMSK2
TMSK2
SPSR
CSPAR0
CSPAR1
CSPAR0
DDRE
Chip-Select [4:0]
D
Boot ROM Chip Select
Port E Data Direction
Port F Data Direction
Port GP Data Direction
Port QS Data Direction
Data Strobe Acknowledge
PCS to SCK Delay
DDRF
DDRGP
DDRQS
CSOR[0:10], CSORBT
CR[0:F]
DSCKL
DT
Delay Before SCK
SPCR1
Delay After Transfer
Length of Delay After Transfer
Input Capture Edge Control
ECLK Divide Rate
CR[0:F]
DTL
SPCR1
EDGE[4:1]
EDIV
TCTL2
SYNCR
ENDQP
EXOFF
EXT
Ending Queue Pointer
External Clock Off
SPCR2
SIMCR
External Reset
RSR
F1A
Force Logic Level One on PWMA
Force Logic Level One on PWMB
Framing Error
PWMC
F1B
PWMC
FE
SCSR
FOC[5:1]
FPWMA
FPWMB
FRZBM
FRZSW
FRZ[1:0]
FRZ[1:0]
HALT
Force Output Compare
Force PWMA Value
Force PWMB Value
Freeze Bus Monitor Enable
Freeze Software Enable
Freeze Response
CFORC
CFORC
CFORC
SIMCR
SIMCR
GPTMCR
QSMCR
SPCR3
Freeze1
Halt
HALTA
HLT
Halt Acknowledge Flag
Halt Monitor Reset
SPSR
RSR
HME
Halt Monitor Enable
HALTA and MODF Interrupt Enable
SYPCR
HMIE
SPCR3
MOTOROLA
D-40
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
I4/O5
Name
Register Location
PACNT
Input Capture 4/Output Compare 5
I4/O5F
Input Capture 4/Output Compare 5
Flag
TFLG1
I4/O5I
IARB[3:0]
ICF[3:1]
ICI[3:1]
IDLE
I4/O5 Interrupt Enable
Interrupt Arbitration
TMSK1
GPTMCR, QSMCR, SIMCR
Input Capture Flags
Input Capture Interrupt Enable
Idle-Line Detected
TFLG1
TMSK1
SCSR
ILIE
Idle-Line Interrupt Enable
Interrupt Level for QSPI
Interrupt Level for SCI
Idle-Line Detect Type
Increment Prescaler
Interrupt Vector Number
Interrupt Priority Mask
Interrupt Priority Adjust
Interrupt Priority Level
Interrupt Vector Base Address
Loss of Clock Reset
QSPI Loop Mode
SCCR1
QILR
ILQSPI
ILSCI
QILR
ILT
SCCR1
GPTMCR
QIVR
INCP
INTV[7:0]
IP[2:0]
IPA
SR
ICR
IPL
CSOR[0:10], CSORBT, ICR
ICR
IVBA
D
LOC
RSR
LOOPQ
LOOPS
M
SPCR3
SCCR1
SCCR1
SIMCR
Loop Mode
Mode Select
MM
Module Mapping
MODE
MODF
MSTR
N
Asynchronous/Synchronous Mode
Mode Fault Flag
CSOR[0:10], CSORBT
SPSR
Master/Slave Mode Select
Negative Flag
SPCR0
CCR
NEWQP
NF
New Queue Pointer Value
Noise Error
SPCR2
SCSR
OC1D[5:1]
OC1M[5:1]
OCF[4:1]
OCI[4:1]
OM[5:2]
OL[5:2]
OR
OC1 Data
OC1D
OC1 Mask
OC1M
Output Compare Flags
Output Compare Interrupt Enable
Output Compare Mode Bits
Output Compare Level Bits
Overrun Error
TFLG1
TMSK1
TCTL1
TCTL1
SCSR
PACLK[1:0]
Pulse Accumulator Clock Select
(Gated Mode)
PACNT
PACNT
PAEN
PAIF
Pulse Accumulator Counter
Pulse Accumulator Enable
Pulse Accumulator Flag
PACNT
PACNT
TFLG2
TMSK2
PAII
Pulse Accumulator Input Interrupt
Enable
PAIS
PAI Pin State (Read Only)
Pulse Accumulator Mode
PACNT
PACNT
TFLG2
TMSK2
PAMOD
PAOVF
PAOVI
Pulse Accumulator Overflow Flag
Pulse Accumulator Overflow Interrupt
Enable
PC[6:0]
Port C Data
PORTC
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-41
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
PCLKS
PCS[3:0]
PE
Name
PCLK Pin State (Read Only)
Peripheral Chip Select
Parity Enable
Register Location
PACNT
CR[0:F]
SCCR1
PE[7:0]
PEDGE
PEPA[7:0]
PF
Port E Data
PORTE
Pulse Accumulator Edge Control
Port E Pin Assignment
Parity Error
PACNT
PEPAR
SCSR
PF[7:0]
PFPA[7:0]
PORTGP[7:0]
PIRQL[2:0]
PITM[7:0]
PIV[7:0]
POW
Port F Data
PORTF
Port F Pin Assignment
Port GP Data
PFPAR
PORTGP
PICR
Periodic Interrupt Request Level
Periodic Interrupt Timing Modulus
Periodic Interrupt Vector
Power-Up Reset
PITR
PICR
RSR
PPROUT
PPR[2:0]
PQS[7:0]
PQSPA[6:0]
PT
PWM Clock Output Enable
PWM Prescaler/PCLK Select
Port QS Data
PWMC
PWMC
PORTQS
PQSPAR
SCCR1
Port QS Pin Assignment
Parity Type
D
PTP
Periodic Timer Prescaler Control
Receiver Active
PITR
RAF
SCSR
RDRF
Receive Data Register Full
Receiver Enable
SCSR
RE
SCCR1
RIE
Receiver Interrupt Enable
Receive Data RAM
Reset Enable
SCCR1
RR[0:F]
RSTEN
R/W
QSPI RAM
SYNCR
CSOR[0:10], CSORBT
SCCR1
Read/Write
RWU
Receiver Wakeup
R[8:0]/T[8:0]
S
SCI Receive/Transmit Data
Supervisor/User State
Send Break
SCDR
SR
SBK
SCCR1
SCBR
SCI Baud Rate
SCCR0
SFA
PWMA Slow/Fast Select
PWMB Slow/Fast Select
Show Cycle Enable
LIMP Mode
PWMC
SFB
PWMC
SHEN[1:0]
SLIMP
SLOCK
SLVEN
SPACE
SPBR
SIMCR
SYNCR
SYNCR
SIMCR
Synthesizer Lock
Factory Test Mode Enabled
Address Space Select
Serial Clock Baud Rate
QSPI Enable
CSOR[0:10], CSORBT
SPCR0
SPE
SPCR1
SPIF
QSPI Finished Flag
SPI Finished Interrupt Enable
Stop Mode External Clock
Stop Clocks
SPSR
SPIFIE
STEXT
STOP
SPCR2
SYNCR
GPTMCR
QSMCR
GPTMCR
CSOR[0:10], CSORBT
STOP
Stop Enable
STOPP
STRB
Stop Prescaler
Address Strobe/Data Strobe
MOTOROLA
D-42
REGISTER SUMMARY
MC68331
USER’S MANUAL
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
STSIM
SUPV
SW
Name
Stop Mode System Integration Clock
Supervisor/Unrestricted
Software Watchdog Reset
Software Watchdog Enable
Software Watchdog Prescale
Software Watchdog Timing
System Reset
Register Location
SYNCR
GPTMCR, QSMCR, SIMCR
RSR
SWE
SWP
SWT[1:0]
SYS
SYPCR
SYPCR
SYPCR
RSR
T[1:0]
TC
Trace Enable
SR
Transmit Complete
SCSR
TCIE
TDRE
TE
Transmit Complete Interrupt Enable
Transmit Data Register Empty
Transmitter Enable
SCCR1
SCSR
SCCR1
SCCR1
TFLG2
TIE
Transmit Interrupt Enable
Timer Overflow Flag
TOF
TOI
Timer Overflow Interrupt Enable
Transmit Data RAM
TMSK2
QSPI RAM
RSR
TR[0:F]
TST
Test Submodule Reset
Overflow Flag
V
CCR
D
W
Frequency Control (VCO)
Wakeup by Address Mark
Wired-OR Mode for QSPI Pins
Wired-OR Mode for SCI Pins
Wrap Enable
SYNCR
SCCR1
SPCR0
SCCR1
SPCR2
SPCR2
CCR
WAKE
WOMQ
WOMS
WREN
WRTO
X
Wrap To
Extend
X
Frequency Control Bit (Prescale)
Frequency Control (Counter)
Zero Flag
SYNCR
SYNCR
CCR
Y[5:0]
Z
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-43
D
MOTOROLA
D-44
REGISTER SUMMARY
MC68331
USER’S MANUAL
INDEX
MC68331
INDEX
MOTOROLA
I-1
USER’S MANUAL
MOTOROLA
I-2
INDEX
MC68331
USER’S MANUAL
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MOTOROLA
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