MC68847FC16_技术文档

PREFACE

The complete documentation package for the MC68847 consists of the MC68847UM/AD,

MC68847 Quad ELM User’s Manual, and the MC68847 Quad ELM Product Brief.

The MC68847 Quad ELM User’s Manual describes the programming, capabilities, registers,

and operation of the MC68847; and the MC68847 Quad ELM Product Brief provides a brief

description of the MC68847 capabilities.

This user’s manual is organized as follows:

Section 1 General Description

Section 2 Functional Description

Section 3 Registers

Section 4 Signals

Section 5 Node Processor Interface

Section 6 Link Management

Section 7 Configuration Examples

Section 8 BIST Operation

Section 9 Electrical Specifications

Section 10 Ordering Information and Mechanical Data

Applications and Technical Information

For questions or comments pertaining to technical information, questions, and applications,

please contact one of the following sales offices nearest you.

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— Sales Offices —

UNITED STATES

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Table of Contents

Paragraph

Number

Page

Number

Title

Section 1

General Description

Section 2

Functional Description

2.1

New Features................................................................................................. 2-1

Stream Cipher Capability............................................................................. 2-1

NPI Changes........................................................................................... 2-1

Testing Circuitry Changes....................................................................... 2-1

Additional Counters................................................................................. 2-1

ELM Overview................................................................................................ 2-2

Framer......................................................................................................... 2-2

Elasticity Buffer............................................................................................ 2-2

Data Path Multiplexers ................................................................................ 2-3

Elasticity Buffer Local Loopback MUX......................................................... 2-3

ELM Local Loopback MUX.......................................................................... 2-3

Bypass MUX................................................................................................ 2-3

Scrub MUX .................................................................................................. 2-4

Remote Loopback MUX .............................................................................. 2-4

Test Data MUX............................................................................................ 2-4

2.1.1

2.1.1.1

2.1.1.2

2.1.1.3

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

2.2.10 Decoder....................................................................................................... 2-4

2.2.11 Encoder ....................................................................................................... 2-5

2.2.12 Repeat Filter................................................................................................ 2-7

2.2.13 Data I/O Ports.............................................................................................. 2-7

2.2.13.1

2.2.13.2

2.2.13.3

2.2.13.4

Receive Data Input ................................................................................. 2-7

Receive Data Output............................................................................... 2-7

Transmit Data Input ................................................................................ 2-7

Transmit Data Output.............................................................................. 2-8

2.2.14 Connection Management ............................................................................ 2-8

2.2.14.1

2.2.14.2

2.2.14.3

2.2.14.4

Line State Machine ................................................................................. 2-8

Link Error Monitor ................................................................................... 2-8

Data Stream Generator........................................................................... 2-8

Physical Connection Management ......................................................... 2-8

Section 3

Registers

3.1

3.1.1

Quad ELM Registers...................................................................................... 3-2

Cipher Control (CIPHER_CNTL_W, CIPHER_CNTL_X,

CIPHER_CNTL_Y, CIPHER_CNTL_Z)....................................................... 3-2

FOTOFF Timers...................................................................................... 3-2

FOTOFF Assert Timer (FOTOFF_ASSERTW, FOTOFF_ASSERTX,

FOTOFF_ASSERTY, FOTOFF_ASSERTZ)....................................... 3-2

3.1.2

3.1.2.1

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Table of Contents

Table of Contents (Continued)

Paragraph

Number

Page

Number

Title

3.1.2.2

FOTOFF De-Assert Timer (FOTOFF_DEASSERTW,

FOTOFF_DEASSERTX, FOTOFF_DEASSERTY,

FOTOFF_DEASSERTZ)..........................................................................3-3

Cipher Control Register................................................................................3-3

Crossbar Control (XBAR_P, XBAR_R, XBAR_S, XBAR_W, XBAR_X,

3.1.3

3.1.4

XBAR_Y, XBAR_Z)......................................................................................3-4

Write Crossbar (WR_XBAR) ........................................................................3-5

Interrupt Data Register (INT_DATA) ............................................................3-5

Interrupt Mask Register (INT_MASK)...........................................................3-6

ELM Registers ................................................................................................3-6

ELM Control Register A (ELM_CNTRL_A) ..................................................3-11

ELM Control Register B (ELM_CNTRL_B) ..................................................3-14

ELM Status Register A (ELM_STATUS_A)..................................................3-16

ELM Status Register B (ELM_STATUS_B)..................................................3-17

ELM Interrupt Event Register (ELM_INTR)..................................................3-19

ELM Interrupt Mask Register (ELM_MASK).................................................3-21

PCM Timers .................................................................................................3-21

TPC Timer....................................................................................................3-21

TNE Timer....................................................................................................3-22

3.1.5

3.1.6

3.1.7

3.2

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.7

3.2.8

3.2.9

3.2.10 PCM Timing Parameter Registers................................................................3-22

3.2.11 Maximum PHY Acquisition Time Register (A_MAX)....................................3-23

3.2.12 Maximum Line State Change Time Register (LS_MAX)..............................3-23

3.2.13 Minimum Break Time Register (TB_MIN) ....................................................3-23

3.2.14 Signaling Time-Out Register (T_OUT).........................................................3-23

3.2.15 Short Link Confidence Test Time Register (LC_SHORT)............................3-24

3.2.16 Scrub Time Register (T_SCRUB) ................................................................3-24

3.2.17 Noise Time Register (NS_MAX)...................................................................3-24

3.2.18 PCM Bit Signaling Registers ........................................................................3-24

3.2.19 Transmit Vector Register (XMIT_VECTOR).................................................3-24

3.2.20 Transmit Vector Length Register (VECTOR_LENGTH)...............................3-24

3.2.21 Receive Vector Register (RCV_VECTOR)...................................................3-25

3.2.22 ELM Event Counters ....................................................................................3-25

3.2.23 Violation Symbol Counter (VIOL_SYM_CTR)..............................................3-25

3.2.24 Link Error Event Counter (LINK_ERR_CTR) ...............................................3-25

3.2.25 Link Error Event Threshold Register (LE_THRESHOLD) ............................3-26

3.2.26 Minimum Idle Counter (MIN_IDLE_CTR).....................................................3-26

3.2.27 ELM Built-in Self-Test Signature Register (ELM_BIST)...............................3-27

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Table of Contents

Table of Contents (Continued)

Paragraph

Number

Page

Number

Title

Section 4

Signal Description

4.1

4.2

4.3

4.4

4.5

4.6

Clock Signals .................................................................................................. 4-1

Receive Data Signals...................................................................................... 4-1

Transmit Data Signals..................................................................................... 4-2

Node Processor Interface Signals................................................................... 4-2

Clock Recovery Signals .................................................................................. 4-3

Test Signals .................................................................................................... 4-4

Section 5

Node Processor Interface Synchronous Operation

5.1

5.2

5.3

5.4

NPI Operation ................................................................................................. 5-1

Synchronous Read Cycle................................................................................ 5-1

Synchronous Write Cycle................................................................................ 5-2

Asynchronous Write Cycle.............................................................................. 5-3

Section 6

Link Management Operation

6.1

6.2

6.3

6.4

Line State Machine Operation......................................................................... 6-1

Link Error Monitor Operation........................................................................... 6-2

Data Stream Generator................................................................................... 6-2

Physical Connection Management.................................................................. 6-3

PCM State Machine...................................................................................... 6-3

Bit Signaling Mechanism.......................................................................... 6-4

Noise Detection Mechanism .................................................................... 6-6

Noise in MAINT State .............................................................................. 6-6

Operation in Trace State.......................................................................... 6-6

Physical Connection Insertion ...................................................................... 6-6

PCI Operation for Non-Class-S Type Station .......................................... 6-7

PCI Operation for Class-S Type Station .................................................. 6-7

PCI Operation in MAINT State................................................................. 6-7

6.4.1

6.4.1.1

6.4.1.2

6.4.1.3

6.4.1.4

6.4.2

6.4.2.1

6.4.2.2

6.42.2.3

Section 7

Quad-ELM Configuration Examples

7.1

7.2

Roving MAC.................................................................................................... 7-2

More Complex Concentrator........................................................................... 7-5

Section 8

BIST Operation

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Table of Contents

Table of Contents (Continued)

Paragraph

Number

Page

Number

Title

Section 9

Electrical Characteristics

9.1

9.2

9.3

9.4

9.5

9.6

9.7

Absolute Maximum Ratings .............................................................................9-1

Recommended Operating Conditions..............................................................9-1

AC Electrical Characteristics............................................................................9-1

Synchronous Node Processor Interface Timing ..............................................9-2

Asynchronous Node Processor Interface Timing.............................................9-4

Data I/O Port Timing ........................................................................................9-6

Miscellaneous Signals Timing..........................................................................9-8

Section 10

Ordering Information

10.1

10.2

10.3

Standard Ordering Information ......................................................................10-2

Pin Assignments, 208-Lead Quad Flat Pack (QFP) .....................................10-3

Package Dimensions .....................................................................................10-4

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Table of Contents

List of Illustrations

Figure

Page

Number

Title

Number

1-1 Quad ELM Block Diagram................................................................................. 1-2

2-1 ELM High-Level Functional Block Diagram....................................................... 2-2

5-1 Node Processor Bus Read Cycles .................................................................... 5-2

5-2 Node Processor Bus Write Cycles .................................................................... 5-3

6-1 Sample FDDI PHY Connections........................................................................ 6-5

7-1 Utilization of Both the Primary and Secondary FDDI Rings .............................. 7-1

7-2 Dual-Ring MAC-Less Concentrator Using Two Quad ELMs............................. 7-2

7-3 Roving MAC Connected to Station 2 Via the S-bus .......................................... 7-3

7-4 Roving MAC Concentrator Using Two Quad ELMs........................................... 7-4

7-5 Dual-Ring Full-Featured Concentrator .............................................................. 7-6

9-1 Node Processor Interface Timing Diagram ....................................................... 9-3

9-2 Node Processor Interface Asynchronous Read Timing Diagram...................... 9-4

9-3 Node Processor Interface Asynchronous Write Timing Diagram ...................... 9-5

9-4 Data I/O Port Timing Diagram ........................................................................... 9-7

9-5 Miscellaneous Signals Timing Diagram............................................................. 9-8

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Table of Contents

List of Tables

Table

Page

Number

Title

Number

2-1

2-2

4B/5B Decoding of Data...................................................................................2-5

4B/5B Encoding of Data ...................................................................................2-6

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

Quad ELM Registers ........................................................................................3-1

Recommended Register Configuration - Fiber Media ......................................3-2

Recommended Register Configuration - Twisted Pair Media...........................3-2

Crossbar Control Registers ..............................................................................3-5

ELM W Register ...............................................................................................3-7

ELM X Registers...............................................................................................3-8

ELM Y Registers...............................................................................................3-9

ELM Z Registers.............................................................................................3-10

PCM Timing Register Recommended Values................................................3-23

3-10 Symbol Pair Count..........................................................................................3-27

3-11 Minimum Idle Occurrence Count....................................................................3-27

6-1

6-2

6-3

Line State Machine Line States........................................................................6-1

Data Stream Generator Output ........................................................................6-2

Connection Rules .............................................................................................6-3

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SECTION 1

GENERAL DESCRIPTION

The MC68847 Quad ELM implements four MC68837 ELM devices on a single chip, provid-

ing a low-cost solution for concentrator applications. The four ELMs are accessible by three

unique data buses. The features of the Quad ELM include:

• Able to perform any ANSI SMT standard conﬁguration scheme

• JTAG compliant implementation

• Provides full functionality of individual ELM devices, including:

- Implements ANSI FDDI PHY standard

- Performs 4B/5B encoding and decoding, elasticity buffer, and smoother functions

- Provides data framing and alignment to byte boundaries

- Hardware assists PCM state machine to reduce load on SMT processing

- Contains line state detector and repeat filter

- Provides link error monitor detection and counting on chip

- Performs scrubbing

- Provides for nonconcantenation of frames

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General Description

Quad ELM

R-bus

S-bus

P-bus

R-bus

S-bus

P-bus

Crossbar

Switch

ELM

W

ELM

X

ELM

Y

ELM

Z

CIPHER

Station 1

CIPHER

Station 2 Station 3 Station 4

Figure 1-1. Quad ELM Block Diagram

The crossbar switch controls the connection scheme within the Quad ELM device by allow-

ing any of the input buses or internal ELMs to be connected to any output bus or internal

ELM.

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SECTION 2

FUNCTIONAL DESCRIPTION

Although the functionality of the ELMs within the Quad ELM remains the same as an indi-

vidual MC68837 ELM chip, the overall pinout, testing circuitry, and some parts of the NPI

have been changed to accommodate the new Quad ELM part.

2.1 NEW FEATURES

The following paragraphs describe new features implemented in the Quad ELM.

2.1.1 Stream Cipher Capability

For twisted-pair applications, an M port has the option of utilizing one of the CIPHER blocks

included on the Quad ELM. There is a CIPHER block paired with each ELM on the device.

The functionality of these blocks is controlled by a register that is accessed via the Node

Processor Interface.

2.1.1.1 NPI CHANGES

In order to deal with the added complexity of the Quad ELM device, some additional regis-

ters have been added to the NPI address space. Eight additional registers are provided to

determine the connection scheme within the crossbar switch. The interrupt data register

contains information about the event which caused the QINT interrupt signal to be asserted.

An interrupt mask register has also been included, allowing any of the interrupts to be

masked. Four registers have been added to load the counters with an initial value.

In order to address all of the registers in the Quad ELM, three additional NPI address bits

have been added to the five that existed in the ELM device. These three additional bits,

NPA(7:5), determine which of the four internal ELMs is being selected, while the remaining

address bits determine the specific register.

2.1.1.2 TESTING CIRCUITRY CHANGES

The boundary scan that was implemented in the MC68837 has been replaced with a JTAG

testing scheme.

2.1.1.3 ADDITIONAL COUNTERS

Four 30-bit count-down counters are also present on the Quad ELM device. The upper 16

bits of these counters are loaded by writing the appropriate register that controls that

counter. When the register is written, the lower 14 bits are automatically loaded with 1’s, and

counting begins, causing each BYTCLK cycle to reduce the count by one. When the count

reaches the value one, a maskable interrupt will be flagged. The counter will cease counting

when it reaches zero.

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Functional Description

2.2 ELM OVERVIEW

The following sections describe the functionality of the individual ELM devices within the

Quad ELM. Figure 2-1 shows a diagram of the functional blocks and the data paths of the

ELM. This subsection contains detailed descriptions of the function of the various blocks in

the chip.

EB LOCAL

LOOPBACK

MUX

FRAMER &

ELASTICITY

BUFFER

LM LOCAL

LOOPBACK

MUX

RECEIVE

DATA INPUT

BYPASS

MUX

RECEIVE

DATA OUTPUT

SCRUB

MUX

DECODER

WRDATA,

XRDATA,

YRDATA,

RCDAT

(TO CROSSBAR)

OR ZRDATA

IDLES

LINE

STATE

ERROR

MACHINE

COUNTERS

BUILT-IN

SELF-TEST

NODE

PROCESSOR

INTERFACE

PHYSICAL

CONNECTION

MANAGEMENT

REPEAT

FILTER

REMOTE

LOOPBACK

MUX

TRANSMIT

DATA OUTPUT

DATA STREAM

GENERATOR

TRANSMIT

DATA INPUT

TEST

DATA MUX

ENCODER

WTDATA,

XTDATA,

YTDATA,

TXDAT

(FROM CROSSBAR)

OR ZTDATA

Figure 2-1. ELM High-Level Functional Block Diagram

2.2.1 Framer

The framer accepts five-bit-wide parallel data as well as RSCLK from the clock recovery de-

vice. Generally, data coming into the framer is not framed into proper FDDI symbols. The

framer is used to align the incoming data to form proper symbols before the data is passed

to the elasticity buffer. A starting delimiter that is used at the beginning of each frame is de-

tected by the framer and used to determine proper symbol boundaries for the data. The

framer has been designed such that the starting delimiter (the JK symbol pair) can be de-

tected independently of previous framing.

2.2.2 Elasticity Buffer

The elasticity buffer performs the necessary buffering to allow data to pass between different

FDDI stations with independent station clocks. The elasticity buffer consists of an 80-bit buff-

er and some control circuitry. The buffer is used to compensate for the differences in the

transmit and receive clock frequencies in the station. Data is clocked into the buffer by

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Functional Description

RSCLK and clocked out of the buffer by BYTCLK. RSCLK is also used to drive all the input

circuitry, including the input controller and input pointer. BYTCLK is also used to drive the

output circuitry, including the output pointer, the output controller, the overflow/underflow de-

tection circuitry, and the output buffer.

2.2.3 Data Path Multiplexers

The receive data path and transmit data path of the ELM include six multiplexers (MUXs) for

the purpose of altering the normal flow of data through the core (See Figure 2-1). Altering

the data paths may be necessary for physical connection insertion and removal and for test-

ing and diagnostics. All receive and transmit paths internal to the ELM are 10 bits (two sym-

bols) wide.

2.2.4 Elasticity Buffer Local Loopback MUX

In normal operating mode, the elasticity buffer local loopback MUX puts data held in the

RDATAx latch onto the receive data path of the ELM.

When the EB_LOC_LOOP bit in ELM_CNTRL_A is set or when BIST is running, the MUX

loops back the data in the TDATAx latch onto the receive data path. This creates a path

whereby data from the MAC can traverse the entire transmit and receive data paths of the

ELM and be returned to the MAC. BIST uses this loopback along with the remote loopback

MUX to create a loop that covers the entire transmit and receive data paths.

Note

When this loopback mode is in effect, data is internally looped

back using BYTCLK and RSCLK is not used in elasticity buffer

operation.

2.2.5 ELM Local Loopback MUX

In normal operating mode, the ELM local loopback MUX receives data from the elasticity

buffer and passes it through the receive data path at a point before the decoder.

When the LM_LOC_LOOP bit in ELM control register A (ELM_CNTRL_A) is set, this MUX

loops back the data in the TDATAx latch onto the receive data path. The ELM local loopback

MUX provides a method of testing most ELM circuitry without the influence of the framer or

elasticity buffer.

2.2.6 Bypass MUX

When the PCI is in the REMOVED, INSERT_SCRUB, or REMOVE_SCRUB state, or when

the SC_BYPASS bit in ELM_CNTRL_A is set while the PCM is in the MAINT state or the

CONFIG_CNTRL bit in ELM Control Register B (ELM_CNTL_B) is also set, the data in the

TXDATx latch is put on the receive path to the scrub mux. On power-up, this bypass path

will be in effect. The delay through a bypassed ELM is one BYTCLK.

When the CLASS_S bit in ELM_CNTL_B is set, as in single attach stations, whenever the

PCI would normally be in the REMOVED state, it will be in the INSERTED state. Thus, be-

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MC68847 USER’S MANUAL

2-3

Functional Description

fore entering INSERT_SCRUB or after leaving REMOVE_SCRUB, rather than putting the

ELM in the bypass mode, PHY_INVALID is output on the internal RCDATx bus.

2.2.7 Scrub MUX

The scrub MUX selects its input from either constant Idle (I) symbol pairs or the output of

the bypass MUX. When the REQ_SCRUB bit in ELM_CNTRL_A is set while the PCM is

in the MAINT state or the CONFIG_CNTRL bit in ELM_CNTL_B is set, or when the PCI is

in the INSERT_SCRUB or REMOVE_SCRUB state, the output of the scrub MUX is I-sym-

bols. Otherwise, the output of the bypass MUX is placed onto the RCDATx bus.

This MUX is used during physical connection insertion and removal to output I-symbols on

the RCDAT bus when scrubbing the ring.

2.2.8 Remote Loopback MUX

In normal operating mode, the remote loopback MUX puts the data held in the TXDATx latch

onto the transmit data path of the ELM.

When the REM_LOOP bit in ELM_CNTRL_A is set, a remote loopback path is set (the

EB_LOC_LOOP and LM_LOC_LOOP bits are not set) or when BIST is running, this MUX

loops back the data from the decoder onto the transmit data path. This loopback creates a

path on which data from the FCG can traverse the entire data path of the ELM and be trans-

mitted to the FCG. BIST uses this loopback along with elasticity buffer local loopback to cre-

ate a loop that covers the entire receive and transmit data paths.

2.2.9 Test Data MUX

In normal operating mode, the test data MUX sends the data output by the encoder to the

TDATAx latch.

When BIST is running, the test data MUX selects the input from the BIST block. Test data

is returned to the BIST block at the output of the scrub MUX.

2.2.10 Decoder

The decoder performs the 4B/5B decoding of received data symbols (see Table 2-1). The

five bits of aligned data are decoded into four bits of data and one control bit, with the high-

order bit being the control bit. The decoded symbol pairs are then sent to the MAC. Although

the decoder operates on symbol pairs, each symbol is decoded independently of the other.

Until the PCM has completed establishing a connection for the physical link, the PHY Invalid

(PI) symbol is returned to the MAC on both RCDAT(9–5) and RCDAT(4–0); the user should

note that RCDAT is routed to the crossbar switch. In addition, a Violation (V) symbol is gen-

erated when an input error condition has been detected, such as an elasticity buffer error

(buffer overflow or underflow). PI takes precedence over V; therefore, if an elasticity buffer

error occurs while the current line state is Quiet, Halt, Master, or Noise, then PI is given to

the MAC.

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Functional Description

Table 2-1. 4B/5B Decoding of Data

SYMBOL

RDATA(9–5)(4–0)

00000

11111

00100

11000

10001

01101

00111

11001

00001

00010

00011

00101

00110

01000

01100

10000

XXXXX

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

PRCDAT(9–5)(4–0)

10000

10111

10100

11100

10011

11101

10001

11001

10100

11000

10100

11000

10100

11111

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

Q

I

H1

J

K

T

R

S

H5

H4

V1

V2

V3

H3

V4

H2

PI

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

X= Don't care. When an elasticity buffer overﬂows, the ELM will impress all ones on the PRCDAT(9–0) bus.

2.2.11 Encoder

The encoder performs the 4B/5B encoding of data symbols to be transmitted over the phys-

ical medium. The four bits of data and one control bit from the MAC are encoded into a

unique 5-bit symbol that is sent to the clock recovery circuitry. Although the encoder oper-

ates on symbol pairs, each symbol is encoded independently of the other. When the

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MC68847 USER’S MANUAL

2-5

Functional Description

GOBBLE_BYTE signal is asserted by the repeat filter (see Section 3 Register Descrip-

tion), the input data symbols are ignored, and the encoder outputs an I-symbol pair.

A parity error on the internal TXDATx bus sets the ELM's internal bus to a pair of INVALID

symbols (1100011000). If the RF_DISABLE bit in ELM_CNTRL_A is clear, the repeat filter

changes these INVALID symbols to I-symbols. Parity detection can be enabled or disabled

with the ENA_PARITY_CHK bit in ELM_CNTRL_A.

The encoder can be disabled via the ENCOFF pin. The 4-bit to 5-bit symbol assignments

are defined in Table 2-2.

Table 2-2. 4B/5B Encoding of Data

Symbol

TXDAT(9–5)(4–0)

10000

10111

10100

11100

10011

11101

10001

11001

11110

10010

10101

10110

11111

11000

11010

11011

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

TDATA(9–5)(4–0)

00000

Q

I

11111

00100

11000

10001

01101

00111

11001

11111

11110

01001

10100

10101

01010

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

H

J

K

T

R

S

INVALID

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

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Functional Description

2.2.12 Repeat Filter

The repeat filter operates on the symbol stream at the output of the remote loopback MUX.

Only Idle and Active Line States are allowed to propagate through the station. Invalid Line

States will be turned into an I-symbol stream. Also, if the repeat filter detects a corrupted

frame, it truncates the frame by transmitting four Halt (H) symbols and then an I-symbol. The

H-symbols will cause the next MAC in the logical ring to count the frame as a lost frame.

Another function of the repeat filter is called the GOBBLE_BYTE. When the repeat filter de-

tects a fragment (i.e., a frame in which an I-symbol appears before the ending delimiter), it

instructs the encoder to change the previous symbol pair to Idles. After passing through re-

peat filters in other stations, the fragment will eventually be completely converted to Idles.

The repeat filter is defined in the ANSI FDDI PHY document. The ELM is a byte-wide imple-

mentation.

2.2.13 Data I/O Ports

Each ELM contains four ports for the input and output of network data. WRDATAx, XR-

DATAx, YRDATAx, and ZRDATAx are the four receive data buses between the W, X, Y and

Z ELMs respectively and the clock recovery chip. WTDATAx, XTDATAx, YTDATAx, ZT-

DATAx are the four transmit data buses between the W, X, Y and Z ELMs respectively and

the clock recovery chip. The RCDATx and TXDATx buses of each individual ELM are con-

nected to the crossbar switch of the Quad ELM allowing the ELMs access to the PRCDATx,

SRCDATx, RRCDATx and the PTXDATx, STXDATx, RTXDATx buses, and the RCDATx

and TXDATAx buses of the other ELMs. The signal timing for these ports is shown in Sec-

tion 9 Electrical Characteristics.

2.2.13.1 RECEIVE DATA INPUT

WRDATAx, XRDATAx, YRDATAx, and ZRDATAx are 5-bit (symbol wide) data buses com-

ing from the clock recovery device to the W, X, Y and Z ELMs. Data is clocked in synchro-

nously with WRSCLK, XRSCLK, YRSCLK, and ZRSCLK. WRSCLK, XRSCLK, YRSCLK,

and ZRSCLK are also used to clock the data through the framer and into the elasticity buffer.

2.2.13.2 RECEIVE DATA OUTPUT

RCDATx is a 10-bit (symbol-pair wide) data bus going from the ELM to the crossbar switch

which routes the data to either the P bus, R bus, S bus or another ELM. Data is latched in-

side the ELM on each rising edge of BYTCLK.

2.2.13.3 TRANSMIT DATA INPUT

TXDATx is a 10-bit (symbol-pair wide) data bus coming from the crossbar switch to either

the W, X, Y or Z ELMs. The data on this bus must be latched on each rising edge of BYTCLK

for use internal to the ELM. The data is initially latched into the ELM by each falling edge of

SYMCLK. The data latched by the falling edge of SYMCLK that precedes the rising edge of

BYTCLK is then latched again by that rising edge of BYTCLK. Having no skew between

SYMCLK and BYTCLK effectively adds 20 ns to the hold time provided on TXDATx. Any

amount by which BYTCLK trails SYMCLK will subtract from the hold time provided.

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Functional Description

2.2.13.4 TRANSMIT DATA OUTPUT

WTDATAx, XTDATAx, YTDATAx, ZTDATAx are 5-bit (symbol wide) data buses going from

the W, X, Y and Z ELMs to the clock recovery device. The 10-bit internal data bus is latched

initially by an ELM on each rising edge of BYTCLK. Bits 9–5 are then latched by the rising

edge of SYMCLK following the rising edge of BYTCLK. Bits 4–0 are then latched by the next

rising edge of SYMCLK, which follows the falling edge of BYTCLK. Data is available to the

clock recovery device after each rising edge of SYMCLK.

2.2.14 Connection Management

The following three logic blocks implement facilities to provide for PCM and link monitoring.

These blocks implement helpful time-critical FCSs and monitoring logic for use by SMT and

CMT pseudocode.

2.2.14.1 LINE STATE MACHINE

In FDDI networks, a special group of symbols called line state symbols (Q—Quiet, H—Halt,

I—Idle, and the JK symbol pair) are transmitted to establish the physical connection be-

tween neighboring stations. These line state symbols are unique in that they can be recog-

nized independently of symbol boundaries. Line states are comprised of consecutive line

state symbols as defined in Section 3 Registers.

2.2.14.2 LINK ERROR MONITOR

The LEM provides an indication of the inbound link quality to the PCM. The PCM uses this

information to determine if the Link Confidence Test passes to establish a new connection.

Once a link is active, the PCM continually runs an LEM test to detect and isolate links having

an inadequate bit error rate.

2.2.14.3 DATA STREAM GENERATOR

The data stream generator block uses a MUX for the purpose of generating a symbol pair

at the request of the PCM or external control when the PCM is in MAINT. The symbol pair

can be requested by the PCM state machine, the repeat filter, or while in maintenance mode

by the NP as selected in the ELM_CNTL_B by the MAINT_LS bit. The user can only control

the generation of the symbol pairs while in the maintenance mode. The repeat filter and the

PCM state machine can be turned off, but while operating, they generate symbol pairs ac-

cording to their internal algorithms.

2.2.14.4 PHYSICAL CONNECTION MANAGEMENT

CMT defines the operation of PHY layer insertion and removal and the connection of PHY

entities to the MAC entities. PCM, a subset of CMT, is the management of a physical con-

nection between the PHY being managed and another PHY.

PCM consists of two entities: the state machine and the pseudocode. The ELM implements

the PCM state machine; whereas, the pseudocode is implemented by driver software.

The PCI state machine works in conjunction with the PCM state machine. The PCI controls

ring scrubbing and the insertion and removal of a station on the ring.

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SECTION 3

REGISTERS

The Quad ELM contains 130 registers, with an address range of 00 to 8D (hex). 116 of these

registers are specific to the individual operation of ELM W, X, Y and Z. The remaining 14

registers are Quad-ELM specific, and control the operation of the crossbar switch, interrupt

handling and notification, and counters.

Table 3-1. Quad ELM Registers

Address

Name

Mnemonic

Type

(Hex)

00-1A

20-3A

40-5A

60-7A

0A

ELM W Registers

ELM X Registers

See Table 3-3

See Table 3-4

ELM Y Registers

See Table 3-5

ELM Z Registers

See Table 3-6

CIPHER CONTROL W

FOTOFF Assert Timer W

CIPHER_CNTRLW

FOTOFF_ASSERTW

Read/Write

Write

1E

1F

FOTOFF De-assert Time W FOTOFF_DEASSERTW

2A

CIPHER CONTROL X

CIPHER_CNTLX

3E

FOTOFF Assert Timer X

FOTOFF_ASSERTW

3F

FOTOFF De-assert Timer X FOTOFF_DEASSERTW

4A

CIPHER CONTROL Y

FOTOFF Assert Timer Y

FOTOFF De-assert Timer Y

CIPHER CONTROL Z

FOTOFF Assert Timer Z

FOTOFF De-assert Timer Z

Crossbar Switch W

Crossbar Switch X

Crossbar Switch Y

Crossbar Switch Z

Crossbar Switch P

Crossbar Switch S

Crossbar Switch R

Write Crossbar

CIPHER_CNTRLY

FOTOFF_ASSERTY

FOTOFF_DEASSERTY

CIPHER_CNTRLZ

FOTOFF_ASSERTZ

FOTOFF_DEASSERTZ

XBARW

5E

5F

6A

7E

7F

80

81

XBARX

82

XBARY

83

XBARZ

84

XBARP

85

XBARS

86

XBARR

87

WR_XBAR

88

Counter W

COUNTW

Read/Write

89

Counter X

COUNTX

8A

Counter Y

COUNTY

8B

Counter Z

COUNTZ

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3-1

Thi d

t

t d

ith F

M k

4 0 4

Registers

Table 3-1. Quad ELM Registers

Address

(Hex)

Name

Mnemonic

Type

8C

8D

Interrupt Mask Register

Interrupt Data Register

INT_MASK

INT_DATA

Read/Write

Read

3.1 QUAD ELM REGISTERS

The following paragraphs describe the registers used to control the overall function of the

Quad ELM.

3.1.1 Cipher Control (CIPHER_CNTLW, CIPHER_CNTLX,

CIPHER_CNTLY, CIPHER_CNTLZ)

These read/write registers provide the control signals for the cipher blocks that are paired

with each of the ELMs

3.1.2 FOTOFF Timers

Two additional timers were added to ELM revision D: FOTOFF assert timer

(FOTOFF_ASSERT) and FOTOFF de-assert timer (FOTOFF_DEASSERT). These timers

control the assertion and de-assertion delays, respectively, associated with the FOTOFF

pin. Table 3-2 and Table 3-3 give the recommended values for the FOTOFF timer registers

and the CIPHER_CNTRLW, X, Y, and Z registers.

Table 3-2. Recommended Register Configuration - Fiber Media

Suggested

Address

Name

Value

0000

0A, 2A, 4A, 6A

1E, 3E, 5E, 7E

1F, 3F, 5F, 7F

CIPHER_CNTRLW, X, Y, Z

FOTOFF_ASSERTW, X, Y, Z

FOTOFF_DEASSERTW, X, Y, Z

Table 3-3. Recommended Register Configuration - Twisted Pair Media

Suggested

Address

Name

Value

00C1

FD76

0000

0A, 2A, 4A, 6A

1E, 3E, 5E, 7E

1F, 3F, 5F, 7F

CIPHER_CNTRLW, X, Y, Z

FOTOFF_ASSERTW, X, Y, Z

FOTOFF_DEASSERTW, X, Y, Z

3.1.2.1 FOTOFF ASSERT TIMER (FOTOFF_ASSERTW, FOTOFF_ASSERTX,

FOTOFF_ASSERTY, FOTOFF_ASSERTZ)

The FOTOFF assert timer should be loaded with the twos complement of the desired asser-

tion delay in 80 ns units. It can have a maximum value of about 5.24 ms (2¹⁶× 80 ns). It is

initialized to zero at power-up reset, indicating zero assertion delay.

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Registers

3.1.2.2 FOTOFF DE-ASSERT TIMER (FOTOFF_DEASSERTW, FOTOFF_DEASSERTX,

FOTOFF_DEASSERTY, FOTOFF_DEASSERTZ)

The FOTOFF de-assert timer should be loaded with the twos complement of the desired de-

assertion delay in 80 ns units. It can have a maximum value of about 5.24 ms (2¹⁶× 80 ns).

This is initialized to zero at power-up reset, indicating zero de-assertion on delay.

3.1.3 Cipher Control Register (CIPHER_CNTRLW, CIPHER_CNTRLX,

CIPHER_CNTRLY, CIPHER_CNTRLZ)

The Cipher control register is a Read/Write register. All bits of this register are cleared with

the assertion of RESET. The Cipher control register is used for the following functions:

• Cipher Enable/Disable

• Cipher Loopback

• Signal Detect Filter Control

• FOTOFF (Quiet) Control

• Production Test

15-14

13-9

8

PRO_TEST

6

Reserved

SDNRZEN

0

7

5

4

3-2

FOTOFF_CNTRL

1

FOTOFF_

SRCE

CIPHER_

LPBCK

SDONEN

SDOFFEN

RXDATA_EN

CIPHER_EN

PRO_TEST - Production Test

These bits are reserved for production testing of the device and should be set to zero.

Bits 13–9—Reserved

Bits 13–9 are reserved and should be set to zero.

SDNRZEN - Signal Detect NRZ Data Filter Enable

When SDNRZEN is set, it causes the received descrambled data to be monitored for ac-

tivity. If 1000 ns elapse without activity, the SD input to the PHY-layer is forced low (inac-

tive).

SDONEN - Signal Detect ON Timer Enable

When SDONEN is set, it causes the assertion of the SD input to the PHY layer to be de-

layed by 1000ns. This allows the descrambler time to properly synchronize before the

PHY layer expects valid data.

SDOFFEN - Signal Detect OFF Timer Enable

When SDOFFEN is set, it causes the received scrambled data to be monitored for activity.

If 1000ns elapse without activity, the SD inputs to both the PHY layer and descrambler

are forced low (inactive).

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MC68847 USER’S MANUAL

3-3

Registers

RXDATA_EN - Receiver Data Enable

When RXDATA_EN is set, it causes the received scrambled data to be forced to all zeros

whenever either the FOTOFF control block's FOTOFF input or output are in their active

low state.

FOTOFF_SRCE - FOTOFF Source Select

When FOTOFF_SRCE is set, it causes the FOTOFF control block to use the PCM state

machine's variable PCM≠ OFF as its input instead of the PHY layer's normal FOTOFF out-

put.

FOTOFF_CNTRL - FOTOFF Mode Selection

The FOTOFF_CNTRL selects the mode of operation of the FOTOFF control block.

FOTOFF_CNTRL is defined as follows:

00 = FOTOFF_DELAY. The FOTOFF_ASSERTx and FOTOFF_DEASSERTx timers

are active. In this mode various length of scrambled and true quiet can be trans-

mitted.

01 = FOTOFF_DELAY. The FOTOFF_ASSERTx and FOTOFF_DEASSERTx timers

are active. In this mode various length of scrambled and true quiet can be trans-

mitted.

10 = FOTOFF is forced inactive. In this mode the transmit data is always scrambled

and applied to the network.

11 = FOTOFF is forced active. In this mode the transmit data is never scrambled and

no energy (true quiet) is applied to the network.

CIPHER_LPBCK - Cipher Loopback Enable

When CIPHER_LPBCK is set, it causes an internal loopback of the scrambled transmit

data to be applied to the descrambler input. This allows a loopback similar to that provid-

ed by LM_LOC_LOOP, but is closer to the edge of the device.

CIPHER_EN

When CIPHER_EN is set, it causes the scrambler and descrambler to be active. When

CIPHER_EN is cleared, the scrambler and descrambler are inactive and the transmit and

receive data pass directly between the pins and the PHY layer.

3.1.4 Crossbar Control (XBARP, XBARR, XBAR_S, XBARW, XBARX,

XBARY, XBARZ)

These read/write registers provide the control signals to configure the connection scheme

for each individual ELM. The state of the crossbar switch following the assertion of reset is

such that each of the ELMs is isolated from the S, R and P buses. The buses are initially

configured in pass-through mode. Note that a write to any of the Crossbar Control registers

is not complete until the Write Crossbar register is also written. Prior to writing the Write

Crossbar Register, a read from a Crossbar Control register will return the current state of

the crossbar, and never reflects a pending change to the Crossbar.

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Registers

Table 3-4. Crossbar Control Registers

Register Value

Output Connection

0000000000000000

0000000000000001

0000000000000010

0000000000000011

0000000000000100

0000000000000101

0000000000000110

0000000000000111

Idles/Pass-Through

P

S

R

W

X

Y

Z

3.1.5 Write Crossbar (WR_XBAR)

A write operation to this register determines at what point the contents of the Crossbar Con-

trol Registers are passed to the controlling circuitry and are no longer a pending change. To

ensure that all crossbar switching is done simultaneously, the user should first write the de-

sired configuration to the control registers, and then write to the WR_XBAR register to cause

the actual switching to occur.

3.1.6 Interrupt Data Register (INT_DATA)

This read-only register contains information pertaining to the interrupt status of the Quad

ELM. The register can be read to determine the cause of the QINT signal being asserted

low. When an interrupt has occured, the corresponding bit in this register will be set high.

When this register is read, the bits pertaining to an interrupt from the Quad ELM node pro-

cessor and from the four counters (7:4) will be cleared. To clear the bits pertaining to each

of the ELMs, the ELM_INTR register within a particular ELM must be read. When a read to

the interrupt event register within a specific ELM occurs, that ELM_INTR register is cleared,

also clearing the bit within this Quad ELM register. The entire register is cleared on the as-

sertion of PWRUP.

15

NP_ERR

7

14

0

13

12

11

10

9

8

0

5

0

4

0

3

0

2

0

1

0

6

COUNTZ COUNTY

COUNTX

COUNTW

ELM Z

ELM Y

ELM X

ELM W

NP_ERR - Node Processor Error

This bit is set when an invalid node processor operation occurs on the Quad ELM. When

a read operation is requested from a write-only register or a write operation is requested

to a read-only register within the address space greater than 80, the NP_ERR bit in this

register is set. When an invalid read or write occurs within the address space reserved for

a particular ELM, that ELMs NP_ERR bit is set to flag the error.

COUNTZ, COUNTY, COUNTX, COUNTW - ELM Counters

These bits indicate that their respective counters have reached the value one. The

counter will then count down one more count and stop at zero.

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Registers

ELM W, ELM X, ELM Y, ELM Z- ELM Interrupts

These bits indicate that their respective ELMs are asserting their individual ELMINTx pins.

The individual ELM_INTR register needs to be read to determine the cause of the inter-

rupt. These bits will be cleared when the ELM ceases to assert its individual interrupt sig-

nal.

3.1.7 Interrupt Mask Register (INT_MASK)

The read/write interrupt mask register is cleared with the assertion of PWRUP. This register

allows the disabling of the individual interrupts present in the interrupt data register. The in-

terrupt mask register contains a bit that corresponds to each bit of the interrupt event register

that, when cleared, prohibits that condition from causing an interrupt to the node processor.

For each bit set, the positive assertion of the corresponding bit in the interrupt event register

will generate an interrupt to the node processor via the QINT pin. Note, however, that the

operation of a bit in the interrupt event register remains unchanged by the state of the cor-

responding bit in the interrupt mask register. Also note that this provides the user with two

levels of masking for the ELM interrupts. The entire ELM can be masked on this level, or the

individual interrupts for that ELM can be masked within a particular ELM’s interrupt mask

register.

3.2 ELM REGISTERS

The following tables are register maps of the ELM specific register set for ELM W, X, Y and

Z.

The control, status, interrupt and timer registers of each ELM are identical and differ only in

address. Therefore the discussion of these registers is condensed into one generic expla-

nation valid for all registers of the same type within each individual ELM.

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Registers

Table 3-5. ELM W Register (00–1F Hex)

Address

Name

Control Register A

Mnemonic

ELM_CNTRL_A

ELM_CNTRL_B

ELM_MASK

Type

Read/Write

00

01

02

Control Register B

Interrupt Mask Register

1

03

04

Transmit Vector Register

XMIT_VECTOR

Read/Write

1

Transmit Vector Length Register

VECTOR_LENGTH

Read/Write

05

06

07

08

09

0B

0C

0D

Link Error Event Threshold Register

LE_THRESHOLD

A_MAX

Maximum PHY Acquisition Time Register

Maximum Line State Change Time Register LS_MAX

Minimum Break Time Register

Signaling Time Out Register

TB_MIN

T_OUT

Short Link Confidence Test Time Register LC_SHORT

Scrub Time Register

Noise Time Register

T_SCRUB

NS_MAX

2

0E

0F

TPC Load Value Register

TNE Load Value Register

TPC_LOAD_VALUE

TNE_LOAD_VALUE

Write-Only

3

10

11

12

13

14

15

16

Status Register A

ELM_STATUS_A

ELM_STATUS_B

TPC

Read-Only

Status Register B

TPC Timer Register

TNE Timer Register

Clock Divider Register

BIST Signature Register

Receive Vector Length Register

TNE

CLK_DIV

ELM_BIST

RCV_VECTOR

4

17

Interrupt Event Register

ELM_INTR

Read-Only/Clear

18

19

1A

Violation Symbol Counter Register

Minimum Idle Counter Register

Link Error Event Counter Register

VIOL_SYM_CTR

MIN_IDLE_CTR

LINK_ERR_CTR

1. Writable only when the PCM_SIGNALING bit in the ELM_STATUS_B register is not set.

2. Writable only when the PCM is in the MAINT state. Use TPC register to read the value written.

3. Writable only when the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A

register is not set.

4. For software compatibility, the former NP_ERR bit in this register is still read only/clear, however

the NP_ERR bit is located in the INTR_MASK register for the entire Quad ELM chip.

Read-Write Registers can be read and written by the node processor at any time.

Read-Only Clear Registers can be read by the node processor at any time but cannot be written at

any time, including when the chip is in test mode. These registers are automatically cleared when

they are read by the node processor.

Read-Only Registers can be read at any time by the node processor but can never be written.

These registers are not automatically cleared upon a node processor read operation.

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MC68847 USER’S MANUAL

3-7

Registers

Table 3-6. ELM X Registers (20–3F Hex)

Address

Name

Control Register A

Mnemonic

ELM_CNTRL_A

ELM_CNTRL_B

ELM_MASK

Type

Read/Write

20

21

22

Control Register B

Interrupt Mask Register

1

23

24

Transmit Vector Register

XMIT_VECTOR

Read/Write

1

Transmit Vector Length Register

VECTOR_LENGTH

Read/Write

25

26

27

28

29

2B

2C

2D

Link Error Event Threshold Register

LE_THRESHOLD

A_MAX

Maximum PHY Acquisition Time Register

Maximum Line State Change Time Register LS_MAX

Minimum Break Time Register

Signaling Time Out Register

TB_MIN

T_OUT

Short Link Confidence Test Time Register LC_SHORT

Scrub Time Register

Noise Time Register

T_SCRUB

NS_MAX

2

2E

2F

TPC Load Value Register

TNE Load Value Register

TPC_LOAD_VALUE

TNE_LOAD_VALUE

Write-Only

3

30

31

32

33

34

35

36

Status Register A

ELM_STATUS_A

ELM_STATUS_B

TPC

Read-Only

Status Register B

TPC Timer Register

TNE Timer Register

Clock Divider Register

BIST Signature Register

Receive Vector Length Register

TNE

CLK_DIV

ELM_BIST

RCV_VECTOR

4

37

Interrupt Event Register

ELM_INTR

Read-Only/Clear

38

39

3A

Violation Symbol Counter Register

Minimum Idle Counter Register

Link Error Event Counter Register

VIOL_SYM_CTR

MIN_IDLE_CTR

LINK_ERR_CTR

1. Writable only when the PCM_SIGNALING bit in the ELM_STATUS_B register is not set.

2. Writable only when the PCM is in the MAINT state. Use TPC register to read the value written.

3. Writable only when the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A

register is not set.

4. For software compatibility, the former NP_ERR bit in this register is still read only/clear, however

the NP_ERR bit is located in the INTR_MASK register for the entire Quad ELM chip.

Read-Write Registers can be read and written by the node processor at any time.

Read-Only Clear Registers can be read by the node processor at any time but cannot be written at

any time, including when the chip is in test mode. These registers are automatically cleared when

they are read by the node processor.

Read-Only Registers can be read at any time by the node processor but can never be written.

These registers are not automatically cleared upon a node processor read operation.

3-8

MC68847 USER’S MANUAL

MOTOROLA

Registers

Table 3-7. ELM Y Registers (40–5F Hex)

Address

Name

Control Register A

Mnemonic

ELM_CNTRL_A

ELM_CNTRL_B

ELM_MASK

Type

Read/Write

40

41

42

Control Register B

Interrupt Mask Register

1

43

44

Transmit Vector Register

XMIT_VECTOR

Read/Write

1

Transmit Vector Length Register

VECTOR_LENGTH

Read/Write

45

46

47

48

49

4B

4C

4D

Link Error Event Threshold Register

LE_THRESHOLD

A_MAX

Maximum PHY Acquisition Time Register

Maximum Line State Change Time Register LS_MAX

Minimum Break Time Register

Signaling Time Out Register

TB_MIN

T_OUT

Short Link Confidence Test Time Register LC_SHORT

Scrub Time Register

Noise Time Register

T_SCRUB

NS_MAX

2

4E

4F

TPC Load Value Register

TNE Load Value Register

TPC_LOAD_VALUE

TNE_LOAD_VALUE

Write-Only

3

50

51

52

53

54

55

56

Status Register A

ELM_STATUS_A

ELM_STATUS_B

TPC

Read-Only

Status Register B

TPC Timer Register

TNE Timer Register

Clock Divider Register

BIST Signature Register

Receive Vector Length Register

TNE

CLK_DIV

ELM_BIST

RCV_VECTOR

4

57

Interrupt Event Register

ELM_INTR

Read-Only/Clear

58

59

5A

Violation Symbol Counter Register

Minimum Idle Counter Register

Link Error Event Counter Register

VIOL_SYM_CTR

MIN_IDLE_CTR

LINK_ERR_CTR

1. Writable only when the PCM_SIGNALING bit in the ELM_STATUS_B register is not set.

2. Writable only when the PCM is in the MAINT state. Use TPC register to read the value written.

3. Writable only when the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A

register is not set.

4. For software compatibility, the former NP_ERR bit in this register is still read only/clear, however

the NP_ERR bit is located in the INTR_MASK register for the entire Quad ELM chip.

Read-Write Registers can be read and written by the node processor at any time.

Read-Only Clear Registers can be read by the node processor at any time but cannot be written at

any time, including when the chip is in test mode. These registers are automatically cleared when

they are read by the node processor.

Read-Only Registers can be read at any time by the node processor but can never be written.

These registers are not automatically cleared upon a node processor read operation.

MOTOROLA

MC68847 USER’S MANUAL

3-9

Registers

Table 3-8. ELM Z Registers (60–7F Hex)

Address

Name

Control Register A

Mnemonic

ELM_CNTRL_A

ELM_CNTRL_B

ELM_MASK

Type

Read/Write

60

61

62

Control Register B

Interrupt Mask Register

1

63

64

Transmit Vector Register

XMIT_VECTOR

Read/Write

1

Transmit Vector Length Register

VECTOR_LENGTH

Read/Write

65

66

67

68

69

6B

6C

6D

Link Error Event Threshold Register

LE_THRESHOLD

A_MAX

Maximum PHY Acquisition Time Register

Maximum Line State Change Time Register LS_MAX

Minimum Break Time Register

Signaling Time Out Register

TB_MIN

T_OUT

Short Link Confidence Test Time Register LC_SHORT

Scrub Time Register

Noise Time Register

T_SCRUB

NS_MAX

2

6E

6F

TPC Load Value Register

TNE Load Value Register

TPC_LOAD_VALUE

TNE_LOAD_VALUE

Write-Only

3

70

71

72

73

74

75

76

Status Register A

ELM_STATUS_A

ELM_STATUS_B

TPC

Read-Only

Status Register B

TPC Timer Register

TNE Timer Register

Clock Divider Register

BIST Signature Register

Receive Vector Length Register

TNE

CLK_DIV

ELM_BIST

RCV_VECTOR

4

77

Interrupt Event Register

ELM_INTR

Read-Only/Clear

78

79

7A

Violation Symbol Counter Register

Minimum Idle Counter Register

Link Error Event Counter Register

VIOL_SYM_CTR

MIN_IDLE_CTR

LINK_ERR_CTR

1. Writable only when the PCM_SIGNALING bit in the ELM_STATUS_B register is not set.

2. Writable only when the PCM is in the MAINT state. Use TPC register to read the value written.

3. Writable only when the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A

register is not set.

4. For software compatibility, the former NP_ERR bit in this register is still read only/clear, however

the NP_ERR bit is located in the INTR_MASK register for the entire Quad ELM chip.

Read-Write Registers can be read and written by the node processor at any time.

Read-Only Clear Registers can be read by the node processor at any time but cannot be written at

any time, including when the chip is in test mode. These registers are automatically cleared when

they are read by the node processor.

Read-Only Registers can be read at any time by the node processor but can never be written.

These registers are not automatically cleared upon a node processor read operation.

3-10

MC68847 USER’S MANUAL

MOTOROLA

Registers

3.2.1 ELM Control Register A (ELM_CNTRL_A)

Control register A is a read/write register. This register is cleared on power-up reset. Control

register A is used for the following functions:

• Timer Configuration

• PCM MAINT State Options Specification

• Counter Interrupt Frequency Selection

• ELM Data Path Configuration

• ELM BIST Execution

• Physical Layer Media Dependent Control

Note

Several bits of this register can only be set or cleared if the PCM

is in the OFF or MAINT state. If this register is written when the

PCM is in any other state, these bits are unchanged.

15

0

14

NOISE_TIMER

6

13

TNE_16BIT

5

12

TPC_16BIT

4

11

10

ENA_PAR_CHK

2

9

8

VSYM_CTR_

INTRS

MINI_CTR_

INTRS

REQ_SCRUB

3

7

1

0

FCG_LOOP_

CNTRL

FOT_OFF

EB_LOC_LOOP

LM_LOC_LOOP

SC_BYPASS

REM_LOOP

RF_DISABLE

RUN_BIST

Bit 15—Reserved

This bit is reserved and should be set to zero.

NOISE_TIMER—Noise Timer

The NOISE_TIMER bit allows the noise timing function of the PCM to be used when the

PCM is in the MAINT state. This function causes the TNE timer to be loaded with the value

in the noise time register whenever the LSM transitions from Idle Line State to Noise Line

State, Active Line State, or Unknown Line State. If the timer expires before Idle Line State

is recognized, the TNE_EXPIRED bit in the interrupt event register (ELM_INTR) is set.

TNE_16BIT—TNE 16-Bit Timer

When TNE_16BIT is set, it causes the TNE timer to operate as a 16-bit timer. In this mode,

the two bits of the TNE clock divider are bypassed, and the TNE timer is incremented ev-

ery 80 ns. TNE_16BIT can only be written if the PCM is in the OFF or MAINT state.

TPC_16BIT—TPC 16-Bit Timer

When TPC_16BIT is set, it causes the TPC timer to operate as a 16-bit timer. In this mode,

the eight bits of the TPC clock divider are bypassed, and the TPC timer is incremented

every 80 ns. TPC_16BIT can only be written if the PCM is in the OFF or MAINT state.

MOTOROLA

MC68847 USER’S MANUAL

3-11

Registers

REQ_SCRUB—Request Scrub

The REQ_SCRUB bit allows limited access to the scrub capability of the ELM core. If the

PCM is in the MAINT state or if the CONFIG_CNTRL bit is set in ELM_CONTROL_B, then

REQ_SCRUB controls the scrub MUX. If REQ_SCRUB is set, then I-symbols are sourced

at the RCDATx port. The output at the WTDATAx, XTDATAx, YTDATAx, or ZTDATAx

port is controlled separately by the MAINT_LS field in ELM_CNTRL_B. This bit can be

written at any time, but only takes effect when the PCM is in the MAINT or OFF state.

ENA_PAR_CHK—Enable Parity Check

0 = Parity checking is disabled.

1 = Parity checking is enabled.

This bit is initialized to zero on power-up reset.

VSYM_CTR_INTRS—Violation Symbol Counter Interrupt

The VSYM_CTR_INTRS bit controls when the VSYM_CTR interrupt bit in ELM_INTR is

set. When VSYM_CTR_INTRS is set, the interrupt is generated only when the

VIOL_SYM_CTR overflows (reaches 256). When VSYM_CTR__INTRS is cleared, the in-

terrupt is generated every time the VIOL_SYM_CTR is incremented (which occurs when-

ever a V-symbol pair is detected).

MINI_CTR_INTRS—Minimum Idle Counter Interrupt

The MINI_CTR_INTRS bit controls when the MINI_CTR interrupt bit in the ELM_INTR

register is set by the Minimum Idle Gap Counter portion of MIN_IDLE_CTR. This bit does

not affect interrupts caused by the Idle Counter Minimum Detector portion of

MIN_IDLE_CTR.

0 = The MINI_CTR interrupt is generated every time the Minimum Idle Gap Counter is

incremented (whenever a minimum length Idle gap is detected).

1 = The MINI_CTR interrupt is generated when the Minimum Idle Gap Counter over-

flows (reaches 16).

FCG_LOOP_CNTRL—FCG Loopback Control

Setting FCG_LOOP_CNTRL causes the WLOOPBACK, XLOOPBACK, YLOOPBACK or

ZLOOPBACK output pin to be asserted low, which, in turn, causes data to be looped back

from the output of the FCG to the input of the FCG.

FOT_OFF—Fiber-Optic Transmitter Off

Setting FOT_OFF is one of several conditions that assert the WFOTOFF, XFOTOFF,

YFOTOFF, or ZFOTOFF output pin.

EB_LOC_LOOP—Elasticity Buffer Local Loopback

When EB_LOC_LOOP is set, a loopback path is set up in the ELM just prior to the ELM-

to-FCG interface. Data from the ELM transmit path is looped back to the input of the fram-

er at the elasticity buffer local loopback MUX. This bit also controls which clock the framer

and elasticity buffer use. When EB_LOC_LOOP is cleared, the recovered byte clock de-

rived from RSCLK is used. When EB_LOC_LOOP is set, the local byte clock BYTCLK, is

used. EB_LOC_LOOP can only be written if the PCM is in the OFF or MAINT state.

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MC68847 USER’S MANUAL

MOTOROLA

Registers

LM_LOC_LOOP—ELM Local Loopback

When LM_LOC_LOOP is set, a loopback path is set up in the ELM core so that data from

TXDATx is passed through the transmit path and looped back to the input of the receive

path at the LM local loopback MUX. LM_LOC_LOOP can only be set or cleared if the PCM

is in the OFF or MAINT state.

SC_BYPASS—Scrub/Bypass.

The SC_BYPASS bit provides limited control over the data path by furnishing a physical

bypass of the ELM core. If the PCM is in the MAINT state or if the CONFIG_CNTRL bit in

ELM_CNTRL_B is set, the SC_BYPASS bit controls the bypass MUX. If REQ_SCRUB is

set, then RCDATx is driven with I-symbols. If SC_BYPASS is set and REQ_SCRUB is

cleared, then RCDATx is driven by the data entering the ELM at the TXDATx input. Oth-

erwise, RCDATx is driven by the data entering the ELM at the WRDATAx, XRDATAx, YR-

DATAx or ZRDATAx input. This bit can be written at any time, but only takes effect when

the PCM is in the MAINT state or if the CONFIG_CNTRL bit in ELM_CNTRL_B is set.

SC_BYPASS

REQ_SCRUB

RCDATx

RDATAx

I-Symbols

TXDATx

0

1

0

1

0

1

I-Symbols

When used in concentrator applications, the SC_BYPASS bit provides for isolation of the

PHYs. The data is latched only once; therefore, there is only a 1-byte clock delay through

a bypassed ELM.

REM_LOOP—Remote Loopback.

When REM_LOOP is set, a remote loopback path is set up inside the ELM whereby sym-

bols from the receive data path are looped back onto the transmit data path, traversing

both paths except for the scrub MUX, bypass MUX, RCDATx latch, and the TXDATx latch.

If the PCM is in the MAINT state or if the CONFIG_CNTRL bit in ELM_CNTRL_B is set,

the REM_LOOP bit controls the remote loopback MUX. This loopback is used by the PCM

to control the configuration and can be used to monitor the ring or otherwise control con-

figuration during normal operation. This bit has no effect if the LM_LOC_LOOP bit or the

EB_LOC_LOOP bit is set. This bit may be written at any time, but only takes effect when

the PCM is in the MAINT state or if the CONFIG_CNTRL bit in ELM_CNTRL_B is set.

RF_DISABLE—Repeat Filter Disable

When RF_DISABLE is set, it disables the ELM repeat filter state machine.

RUN_BIST—Run Built-In Self-Test

When RUN_BIST is set, it causes the ELM to begin running BIST. The completion of BIST

is indicated via an interrupt. BIST can be stopped before completion by clearing this bit.

Once BIST has completed, this bit must be cleared and set again before BIST will restart.

MOTOROLA

MC68847 USER’S MANUAL

3-13

Registers

3.2.2 ELM Control Register B (ELM_CNTRL_B)

Control register B is a read/write register. This register is cleared on power-up reset. Control

register B contains signals and requests to direct the PCM process. It is also used to control

the LS_MATCH interrupt.

15

14

11

10

8

CONFIG_

CNTRL

7

MATCH_LS

MAINT_LS

1

6

5

4

3

2

0

CLASS_S

PC_LOOP

PC_JOIN

LONG

PC_MAINT

PCM_CNTRL

CONFIG_CNTRL—Configuration Control

The CONFIG_CNTRL bit allows control over the bypass MUX and remote loopback MUX

while the PCM is in normal operation.

0 = The REQ_SCRUB, SC_BYPASS and REM_LOOP bits only have an effect if the

PCM is in the MAINT state.

1 = The REQ_SCRUB, SC_BYPASS and REM_LOOP bits in ELM_CNTRL_A have

an effect regardless of the state of the PCM.

MATCH_LS—Match Line State

The MATCH_LS field specifies the line state to be compared with the currently detected

line state (defined by LINE_ST in ELM_STATUS_A). When a match occurs, the

LS_MATCH bit in the ELM_INTR register is set. Each bit of MATCH_LS corresponds to

a line state. If more than one bit is set, the interrupt is signaled if any of the line states

match the current line state. If no bits are set, the interrupt is signaled on any change in

the LINE_ST field or the UNKN_LINE_ST bit. MATCH_LS is defined as follows:

0000 =Interrupt on change in LINE_ST or UNKN_LINE_ST

1XXX =Interrupt on Quiet Line State

X1XX =Interrupt on Master Line State

XX1X =Interrupt on Halt Line State

XXX1 =Interrupt on Idle Line State

In the above list, X means don't care. Also, Idle Line State refers to ILS16, which is sig-

naled only after 16 I-symbols (eight I-bytes) have been received.

MAINT_LS—MAINT Line State

The MAINT_LS field defines the line state the Data Stream Generator will source while

the PCM is in the MAINT state. MAINT _LS is defined as follows:

000 = Transmit_Quiet Line State

001 = Transmit_Idle Line State

010 = Transmit_Halt Line State

011 = Transmit_Master Line State

100 = Transmit_Quiet Line State

101 = Transmit_Quiet Line State

110 = Transmit_PDR (Transmit PHY_DATA request. The symbol pair at

TXDATx is transmitted.)

111 = Transmit_Quiet Line State

3-14

MC68847 USER’S MANUAL

MOTOROLA

Registers

CLASS_S—Class Slave

When CLASS_S is set during configuration (i.e., PHY is a single-attach station and PCM

is not yet in ACTIVE state), the station will be not be bypassed—i.e., data coming from

the MAC to the ELM will not be looped back to the MAC. Normally, this bit would not be

set for A, B, and M type PHYs, in which case the ELM will be bypassed anytime the PCM

is not in the ACTIVE or TRACE state. This bit has an effect when the PCM is in normal

operation. When the PCM is in the MAINT state, the REQ_SCRUB and SC_BYPASS bits

in ELM_CNTRL_A control the scrubbing and bypass operation. This bit can only be

changed when the PCM is in the OFF state. If this register is set or cleared when the PC

is in any other state, this bit will remain unchanged.

Note

It is NOT recommended to set this bit in the Quad ELM since

concentrator ports are type M PHYs.

PC_LOOP—Physical Connection Loopback

PC_LOOP controls the loopback used in the Link Confidence Test. When it is set to a val-

ue other than zero and the PCM is in the NEXT state, the PCM will set the TD_Flag bit

(defined in SMT) and perform the Link Confidence Test in one of three ways. The action

taken is according to the value of these two bits:

00 = No Link Confidence Test is performed.

01 = The PCM sets Transmit_PDR, which assumes that protocol data units

will be input at TXDATx.

10 = The PCM sets Transmit_Idle, which causes the ELM to source I-symbols.

11 = The PCM sets Transmit_PDR and sets up a remote loopback path in the ELM.

PC_LOOP should only be written after the PCM_CODE interrupt has been generated. If

the PCM is not in the NEXT state or if PCM_SIGNALING is set, then any value written to

the field is ignored. Once PC_LOOP has been written, it must be cleared and written again

to perform another Link Confidence Test.

PC_JOIN—Physical Connection Join

When PC_JOIN is set and the PCM is in the NEXT state, the PCM will transition to the

JOIN state and the PCM join sequence will be started. PC_JOIN should only be written

after the PCM_CODE interrupt has been generated. If the PCM is not in the NEXT state

or if PCM_SIGNALING is set, then any value written to this bit is ignored. After this bit has

been set, it must be cleared and then set again to cause another transition from the NEXT

state to the JOIN state. Note that if PC_JOIN is set after the Link Confidence Test has

been started but before it has completed, the test will be aborted and the PCM join se-

quence will be initiated.

LONG—Long Link Confidence Test

When LONG is set, the PCM will perform a long Link Confidence Test—that is, it will con-

tinue the test until the processor issues a PC_SIGNAL, PC_JOIN, or other command.

Otherwise, it will perform a short Link Confidence Test—that is, it will stop the test after

the length of time indicated in the LC_SHORT time parameter. In either case, the LCT will

stop whenever MLS or HLS is detected, indicating that the neighboring PHY has complet-

ed its LCT and started signaling.

MOTOROLA

MC68847 USER’S MANUAL

3-15

Registers

PC_MAINT—PCM MAINT State

When PC_MAINT is set, the PCM state machine transitions to the MAINT state if it is cur-

rently in the OFF state. If the PCM is not in the OFF state when this bit is set, it will imme-

diately transition to the MAINT state when the OFF state is reached.

PCM_CNTRL—PCM Control

PCM_CNTRL controls the PCM state machine. When this bit field is set to a value other

than zero, it causes the PCM to immediately transition to the BREAK, TRACE, or OFF

state. The transition to the BREAK or OFF state occurs regardless of the PCM state at the

time. The transition to the TRACE state only occurs if the PCM is in the ACTIVE state;

otherwise, PCM_CNTRL is ignored. This field must first be cleared and then written with

another value to cause another transition. The following table describes the action taken

described by these two bits:

00 = The PCM state is not affected.

01 = The PCM goes to the BREAK state (PC_Start).

10 = The PCM goes to the TRACE state (PC_Trace).

11 = The PCM goes to the OFF state (PC_Stop).

Note that if the PCM goes to the BREAK state for a reason other than writing

PCM_CNTRL (e.g., Quiet Line State is received or a time-out occurs), the PCM will not

go to the CONNECT state and will remain in the BREAK state until PCM_CNTRL is writ-

ten with the PC_Start value. If the PCM goes from the ACTIVE state to the BREAK state,

it will scrub the ring before leaving the BREAK state. If the PC_Start value is written to

PCM_CNTRL while scrubbing is being performed, the scrubbing will complete before the

PCM goes to the CONNECT state.

3.2.3 ELM Status Register A (ELM_STATUS_A)

Status register A is used to report status information about the LSM through the NP.

This register is read-only.

15

14

13

5

11

10

SIGNAL_

DETECT

2

9

8

0

ELM_INTEGRATION

ELM_REV_NO

PREV_LINE_ST

7

4

3

LINE_ST

LSM_STATE

UNKN_LINE_ST

SYM_PR_CTR

ELM_INTEGRATION—ELM Integration Bits

00 = ELM Revision Band C

01 = ELM Integrated into CAMEL

10 = Quad ELM

ELM_REV_NO—ELM Revision Number

000 = ELM Revision B

001 = ELM core in Revision A Quad ELM

3-16

MC68847 USER’S MANUAL

MOTOROLA

Registers

SIGNAL_DETECT—Signal Detect Value

This bit contains the inverse of the value on the SD input pin.

0 = Signal detected

1 = Signal not detected

PREV_LINE_ST—Previous Line State

This field contains the value of the previous line state when the line state changes from

Quiet, Master, Halt, or Idle (ILS16, where ILS16 is achieved after 16 I-symbols) to another

line state. When the line state changes from anything else, this field is not updated. These

two bits are defined as follows:

00 = Quiet Line State

01 = Master Line State

10 = Halt Line State

11 = Idle Line State (ILS16 achieved after 16 I-symbols)

LINE_ST—Current Line State

This field contains the most recently recognized line state by the LSM. LINE_ST is further

defined as follows:

000 = Noise Line State

001 = Active Line State

010 = Reserved

011 = Idle Line State (ILS4 achieved after 4 I-symbols)

100 = Quiet Line State

101 = Master Line State

110 = Halt Line State

111 = Idle Line State (ILS16 achieved after 16 I-symbols)

LSM_STATE—Line State Machine State

This field contains the state bit of the LSM.

0 = Not Active Line State

1 = Active Line State

UNKN_LINE_ST—Unknown Line State

This bit is the unknown line state indication.

0 = Line State Known

1 = Line State Unknown

SYM_PR_CTR—Symbol Pairs Counter

This field contains the LSM symbol pairs counter. When the count reaches seven, indicat-

ing eight consecutive like symbol pairs, then LINE_ST is set with the new line state, and

the UNKN_LINE_ST bit is reset. Note that Idle Line State is reached after just two I-sym-

bol pairs.

3.2.4 ELM Status Register B (ELM_STATUS_B)

Status register B, which is read-only, contains signals and status from the repeat filter and

PCM state machine.

MOTOROLA

MC68847 USER’S MANUAL

3-17

Registers

15

14

13

12

11

PCI_SCRUB

3

10

2

8

0

RF_STATE

PCI_STATE

PCM_STATE

7

6

5

4

PCM_

PCM_STATE

LSF

RCF

TCF

BREAK_REASON

SIGNALING

RF_STATE—Repeat Filter State

This field contains the state bits of the repeat filter state machine. The states are defined

as follows:

00 = REPEAT

01 = IDLE

10 = HALT1

11 = HALT2

PCI_STATE—Physical Connection Insertion State

This field contains the state bits of the PCI state machine. The states are defined as fol-

lows:

00 = REMOVED

01 = INSERT_SCRUB

10 = REMOVE_SCRUB

11 = INSERTED

PCI_SCRUB—Physical Connection Insertion Scrub

This flag indicates that the scrubbing function is operating—that is, I-symbol pairs are be-

ing sourced on the RCDATx output pins.

PCM_STATE—Physical Connection Management State

This field contains the state bits of the PCM state machine. The states are defined as fol-

lows:

0000 = PC0 (OFF)

0001 = PC1 (BREAK)

0010 = PC2 (TRACE)

0011 = PC3 (CONNECT)

0100 = PC4 (NEXT)

0101 = PC5 (SIGNAL)

0110 = PC6 (JOIN)

0111 = PC7 (VERIFY)

1000 = PC8 (ACTIVE)

1001 = PC9 (MAINT)

1010–0111 = Reserved

PCM_SIGNALING—Physical Connection Management Signaling

This PCM flag indicates that the transmit vector register has been written and the PCM is

in the process of transmitting these bits to its neighboring PCM. The transmit vector reg-

ister cannot be written when this flag is set.

3-18

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Registers

LSF—Line State Flag

The PCM uses this bit to indicate that a given line state has been received since entering

the current state. It is cleared on every change of PCM state.

RCF—Receive Code Flag

The PCM uses this bit to indicate that the receive logic has started execution. This flag is

used to prevent the receive station management PCM code from being started multiple

times while in the NEXT state.

TCF—Transmit Code Flag

The PCM uses this bit to indicate that the transmit logic has started execution. This flag

is used to prevent the transmit station management PCM code from being started multiple

times while in the NEXT state.

BREAK_REASON—Break Reason

This field, which indicates the reason for the PCM state machine's last transition to the

BREAK state, is defined as follows:

000 =The PCM state machine has not gone to the BREAK state

001 = PC_Start Issued

010 = TPC Timer Expired after T_OUT

011 = TNE_Timer Expired after NS_MAX

100 = Quiet Line State Detected

101 = Idle Line State Detected

110 = Halt Line State Detected

111 = Reserved

3.2.5 ELM Interrupt Event Register (ELM_INTR)

The read-only interrupt event register is cleared whenever it is read as well as when PWRUP

is asserted. The ELM uses this register to report individual PHY events to the NP.

While the RUN_BIST bit in the ELM_CNTRL_A is set, all interrupts are masked except

BIST_DONE. Since BIST_DONE is the only interrupt that can occur in this situation,

BIST_DONE does not have a bit in the interrupt event register. This interrupt is cleared by

clearing the RUN_BIST bit in ELM_CNTRL_A.

Also see Quad ELM Registers for further information on the operation of this register within

the context of the Quad ELM.

15

NP_ERR

7

14

SD

6

13

LE_CTR

5

12

MINI_CTR

4

11

VSYM_CTR

3

10

PHYINV

2

9

8

EBUF_ERR

1

TNE_EXPIRED

0

TPC_EXPIRED PCM_ENABLED

PCM_BREAK

SELF_TEST

TRACE_PROP

PCM_CODE

LS_MATCH

PARITY_ERR

NP_ERR—Node Processor Error

This bit indicates that the node processor has requested one of the following invalid op-

erations:

• A read to a write-only register

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Registers

• A write to a read-only register

• A write to a PCM timing parameter while PCM is not in the OFF state

• A write to the TPC timer register while PCM is not in the MAINT state or while

PCI_SCRUB is set

• A write to the TNE timer register while PCM is not in the MAINT state or NOISE_TIMER

is set.

SD—Signal Detect

This bit indicates that signal detect has become asserted—that is, the SD input pin has

been asserted.

LE_CTR—Link Error Counter

This bit indicates that the link error event counter has reached the value contained in the

link error event threshold register.

MINI_CTR—Minimum Counter

This bit indicates that either event or both events have occurred in the minimum idle

counter register—the idle counter minimum detector has changed to a lower value or the

minimum idle gap counter has incremented or overflowed (depending on the

MINI_CTR_INTRS bit in ELM_CNTRL_A ).

VSYM_CTR—Violation Symbol Counter

This bit indicates that the violation symbol counter has incremented or overflowed (de-

pending on the VSYM_CTR_INTRS bit in ELM_CNTRL_A ).

PHYINV—Physical Layer Invalid

This bit indicates that the physical layer invalid signal has been asserted by the PCM.

EBUF_ERR—Elasticity Buffer Error

This bit indicates that the elasticity buffer has experienced an overflow or an underflow.

EBUF_ERR is only reset after recognition of Idle or Active Line States. This bit is usually

masked during PCM operation.

TNE_EXPIRED—TNE Timer Expired

This bit indicates that the TNE timer has expired—i.e., reached zero.

TPC_EXPIRED—TPC Timer Expired

TPC_EXPIRED indicates that the TPC timer has expired—i.e., reached zero.

PCM_ENABLED—Physical Connection Management Enabled

PCM_ENABLED indicates that the PCM has asserted CF_JOIN (ANSI state transition

PC(88b)), has completed scrubbing (for class M, A, or B stations), and is in the ACTIVE

state.

PCM_BREAK—Physical Connection Management Break

This bit indicates that the PCM has entered the BREAK state.

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Registers

SELF_TEST—Self-Test

This bit indicates that a Quiet or Halt Line State has been received while the PCM is in the

TRACE state.

TRACE_PROP—Trace Propagate

This bit indicates that a Master Line State has been received while the PCM is in the AC-

TIVE or TRACE state.

PCM_CODE—Physical Connection Management Code

PCM_CODE indicates that the PCM has completed transmitting the last bit in the vector

written to the transmit vector register and has received the corresponding bit of the receive

vector length register or that the Link Confidence Test has been completed.

LS_MATCH—Line State Match

This bit indicates that the line state detected equals the line state in the MATCH_LS field

of ELM_CNTRL_B.

PARITY_ERR—Parity Error

This bit indicates that a parity error has been detected on the TXDATx input pins. The parity

feature was designed for ELMs implemented in a concentrator. Since there is no parity fea-

ture between the MAC and the ELM, this bit should be masked when the ELM is used in an

end station. The frame data is protected by the FCS field when the data path is between the

ELM and the MAC.

3.2.6 ELM Interrupt Mask Register (ELM_MASK)

Each bit corresponds bit for bit with the ELM_INTR register. When a bit in this register is set

and the corresponding bit in the ELM_INTR register is also one, an interrupt is generated

and the individual ELM interupt bit in the Quad ELM interrupt event register is set. This reg-

ister can be read and written by the NP at any time. lt is cleared on power-up reset.

3.2.7 PCM Timers

The PCM utilizes two ELM timers, TPC timer and TNE timer, to track PCM timing parame-

ters. Both timers have a clock divider circuit to reduce the frequency at which they are incre-

mented.

3.2.8 TPC Timer

The TPC timer is a 16-bit timer. The TPC timer value is read at address 12 (hex). When the

PCM is in the MAINT state and the PCI_SCRUB bit in ELM_STATUS_B is cleared, a value

can be written to the TPC load value register at address 0E. The TPC timer is incremented

by the output of an 8-bit clock divider circuit and is therefore incremented every 20.48 ms,

8

(2 × 80 ns). The instantaneous value in the TPC clock divider is contained in bits 7–0 of the

clock divider register, which can be read at address 14 (hex).

The TPC timer is used to ensure that state transitions proceed at the desired rate while the

PCM is attempting to establish a physical connection with a neighboring PCM. The timer is

loaded with a twos complement value and counts up until it reaches zero. In normal opera-

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tion, the timer is loaded by the PCM from the relevant timing parameter register, which con-

tains the twos complement of the time value in 20.48-ms units. At the same time the TPC

timer is loaded with each parameter, the TPC clock divider is initialized to zero.

In MAINT state, the TPC timer can be explicitly loaded by the NP and used to time the scrub

function (i.e., REQ_SCRUB = 1). When the TPC_EXPIRED interrupt occurs, the

REQ_SCRUB function can be deactivated (REQ_SCRUB = 0) to end scrubbing. If the PCM

is not in the MAINT state when a write is attempted to this register, the NP_ERR bit in the

ELM_INTR register will be set, and the timer will not be loaded.

For test purposes, the timer can also be used in 16-bit mode, in which the TPC clock divider

is bypassed and the timer is incremented every 80 ns when in operation. In this mode, the

value loaded into the timer is the twos complement of the remaining time in 80-ns units. This

feature is controlled by TPC_16BIT in ELM_CNTRL_A.

3.2.9 TNE Timer

The TNE timer is a 16-bit timer. The value of the TNE timer can be read at address 13 (hex).

When the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A is not

set, a value can be written to the TNE register by writing TNE load value register at address

0F. The TNE timer, which is incremented by the output of a 2-bit clock divider circuit, is in-

2

cremented every 0.32 ms (2 x 80 ns). The instantaneous value in the TNE clock divider is

contained in bits 9 and 8 of the clock divider register, which can be read at address 14 (hex).

The TNE timer is used to time the length of (potential) noise while the PCM is in the ACTIVE

state. The TNE timer is started whenever the LSM transitions from Idle Line State to Noise

Line State, Active Line State, or Unknown Line State. If the timer expires before the PCM

LSM recognizes Idle Line State again, the PCM transitions to the BREAK state.

The timer is loaded with a twos complement value and counts up until it reaches zero. In

normal operation, the timer is loaded by the PCM from the noise time register timing param-

eter register, which contains the twos complement of the time value in 0.32-ms units, when

the LSM leaves Idle Line State. At the same time the TPC timer is loaded, the TNE clock

divider is initialized to zero.

When the PCM is in the MAINT state and the NOISE_TIMER bit in ELM_CNTRL_A is not

set, the TNE timer can be loaded directly with a 16-bit value from the NP (the TNE clock

divider is still loaded with zero). If the PCM is not in the MAINT state when a write is attempt-

ed, the NP_ERR bit in the ELM_INTR register will be set, and the timer will not be loaded.

For testing purposes, the timer can also be used in 16-bit mode, in which the TNE clock di-

vider is bypassed and the timer is incremented every 80 ns when in operation. In this mode,

the value loaded into the timer is the twos complement of the remaining time in 80-ns units.

This feature is controlled by TNE_16BIT in ELM_CNTRL_A.

3.2.10 PCM Timing Parameter Registers

The PCM uses a number of different timing parameter registers when forming a physical

connection. These registers, which are readable at any time, are programmable and must

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Registers

be written by the NP. TPC-based timing parameter registers hold the twos complement of

8

the time in 20.48-ms (2 × 80 ns) units. They can have a maximum value of about 1.34 sec

16

(2 × 20.48 ms).

In addition to the TPC timing parameters, there is one timing parameter used by the TNE

2

timer, the noise time register, which holds the twos complement of the time in 0.32-ms (2

16

× 80 ns) units. It can have a maximum value of approximately 20.97 ms (2 × 0.32 ms).

The ANSI FDDI SMT document contains a recommended set of values for these parame-

ters. PCM Timing Register Recommended Values summarizes those values.

Table 3-9. PCM Timing Register Recommended Values

Parameter

A_MAX

Recommended Value (ms) Register Value (Twos Comp/Hex)

Timer

TPC

TNE

0.2

0.02

20

FFF6

FFFF

FC2F

ECED

F676

FF6D

E796

LS_MAX

TB_MIN

T_OUT

100

50

LC_SHORT

T_SCRUB

NS_MAX

3

2

3.2.11 Maximum PHY Acquisition Time Register (A_MAX)

The A_MAX register value represents the maximum time required to achieve signal acqui-

sition. This register is used for timing the length of time to remain in the Connect State to

ensure correct timing with the neighboring PCM (C_MIN).

3.2.12 Maximum Line State Change Time Register (LS_MAX)

The LS_MAX register value is the maximum time required for line state recognition. This

register is used to set the time required to transmit a given line state before advancing to the

next PCM state (TL_MIN).

3.2.13 Minimum Break Time Register (TB_MIN)

TheTB_MIN register holds the allowable length of time for the PCM to be in the BREAK state

before a response is seen on the inbound physical link. This time allows for the possibility

of a bypass failure mode in this station or a neighboring station that could cause four PHYs

to be connected in a loop and produce an invalid response to the break. In this case, the

minimum break time guarantees that the response to the break will propagate around the

loop and be seen on the inbound link.

3.2.14 Signaling Time-Out Register (T_OUT)

The T_OUT register allows for a response reception from a neighboring PCM. When a re-

sponse is expected and no transition is made in a period equal to T_OUT, the PCM goes to

the BREAK state.

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Registers

3.2.15 Short Link Confidence Test Time Register (LC_SHORT)

The LC_SHORT register specifies the time duration of the Link Confidence Test. It limits the

loopback to prevent deadlock.

3.2.16 Scrub Time Register (T_SCRUB)

T_SCRUB is the time that the ring continuity is broken to remove old PDU’s from the ring.

Its use is described in the PCI process (see Functional Description).

3.2.17 Noise Time Register (NS_MAX)

The NS_MAX register holds the maximum length of time that noise is tolerated before a con-

nection is broken down

3.2.18 PCM Bit Signaling Registers

The PCM uses three ELM registers to perform bit signaling. Bit signaling is the mechanism

the PCM uses to transfer information to the PCM in the neighboring station.

3.2.19 Transmit Vector Register (XMIT_VECTOR)

All bits of the read/write transmit vector register are cleared with the assertion of PWRUP.

The transmit vector register is writable only when the PCM_SIGNALING bit in

ELM_STATUS_B is cleared; otherwise, the register will not be written, and the NP_ERR bit

in the ELM_INTR register will be set. This register is readable at any time.

The transmit vector register contains from 1 to 16 bits of data to be transmitted from the PCM

to its neighboring PCM. Bits are transmitted one at a time by the bit signaling mechanism.

A one is represented by the transmission of Halt Line State and a zero by the transmission

of Master Line State. Bit 0 of this register is the first bit to be transmitted, then bit 1, etc., up

to the number of bits specified in the transmit vector length register (VECTOR_LENGTH).

VECTOR_LENGTH should be written before this register is written. When a write is made

to this register, VECTOR_LENGTH is sampled to determine the number of bits to transmit.

3.2.20 Transmit Vector Length Register (VECTOR_LENGTH)

The transmit vector length register is cleared with the assertion of PWRUP. This register is

sampled when the transmit vector register is written. Thus, although this register is writable

at any time, only the last value written before the transmit vector register is written will affect

the operation of the PCM.

Bits 15–4 are unused and will always be read as zeros. Any value written to these bits will

be ignored.

Bits 3–0 contain the number of bits to be transmitted. The value in this field (0 to 15) is ac-

tually one less than the number of bits to transmit (1 to 16).

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3.2.21 Receive Vector Register (RCV_VECTOR)

The read-only receive vector register contains from 1 to 16 bits of data received from the

neighboring PCM. Bits are received at the same time bits are being transmitted. As bit n is

received, it is placed in the receive vector register. If Halt Line State is received, bit n is a

one; if Master Line State is received, bit n is a zero. Bit 0 of this register is the first bit re-

ceived, then bit 1, etc., up to the number of bits specified in the transmit vector length regis-

ter.

Although this register is readable at any time, if PCM_SIGNALING is asserted when this reg-

ister is read, the data can be incomplete.

3.2.22 ELM Event Counters

The ELM contains three event counter registers and one threshold value register used for

gathering information about errors occurring on its associated physical link and for monitor-

ing I-symbol gaps between packets.

3.2.23 Violation Symbol Counter (VIOL_SYM_CTR)

The violation symbol counter has address 18 (hex). It is read-only and is cleared whenever

it is read as well as when PWRUP is asserted. The high-order 8 bits always read as zeros;

the low-order 8 bits contain the counter value. The VSYM_CTR bit in the ELM_INTR register

is set whenever the counter increments or whenever the counter overflows (reaches 256),

depending on the setting of the VSYM_CTR_INTRS bit in ELM_CNTRL_A. When the

counter overflows (reaches 256), it wraps to zero and continues to count.

The violation symbol counter is incremented whenever the 4B/5B decoder in the ELM de-

codes a V-symbol. See Table 2-1 for the symbols considered to be V-symbols by the decod-

er.

3.2.24 Link Error Event Counter (LINK_ERR_CTR)

The link error event counter has address 1A (hex). It is read-only and is cleared whenever

it is read as well as when PWRUP is asserted. An 8-bit counter is contained in bits 7–0. Bits

15–8 of the register always read as zeros. The LE_CTR bit in ELM_INTR is set whenever

the counter reaches the value contained in the link error event threshold register. The

counter will continue to count past this point. When the counter overflows (reaches 256), it

wraps to zero and continues to count.

15

0

8

0

7

Link Error Event Counter

Before the PCM is active, the link error event counter is used by the internal PCM hardware

to perform the Link Confidence Test. The number of errors that the user wants the Link Con-

fidence Test to accept should be initialized into the link error event threshold register. If the

Link Confidence Test is performed and the link error event threshold is not reached, then

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Registers

the test passed. The test result is given to the software, which then makes the decision as

to the next step.

The link error event counter is part of the link error monitor. The link error monitor monitors

the bit error rate of an active link and detects and isolates physical links having an inade-

quate bit error rate, possibly due to a marginal link quality, link degradation, or connector

unplugging.

In addition to the counter, the ELM also contains logic to detect link error events. Link error

events are defined as:

• Transitions from Idle Line State to Unknown Line State or Noise Line State.

• Transitions from Active Line State to Unknown Line State or Noise Line State with the

duration of Unknown Line State or Noise Line State exceeding eight symbol times (320

ns).

The link error event counter is only incremented by the link error monitor when a link error

occurs and the PCM state machine is in NEXT or ACTIVE state.

3.2.25 Link Error Event Threshold Register (LE_THRESHOLD)

The read/write link error event threshold register is cleared when PWRUP is asserted. Bits

7–0 of this register contain a value that controls when the LE_CTR bit in the ELM_INTR reg-

ister is set. Whenever the value in the link error event counter reaches the value contained

in this register, the LE_CTR bit is set. Bits 15–8 always read as zeros.

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

Link Error Event Threshold Value

3.2.26 Minimum Idle Counter (MIN_IDLE_CTR)

The read-only minimum idle counter is cleared whenever it is read as well as when PWRUP

is asserted. Bits 15–7 of the register always read as zeros.

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

6

4

3

0

Idle Counter Minimum Detector

Minimum Idle Gap Counter

Bits 6–4 of the counter contain the value in the idle counter minimum detector. This is the

minimum number of interpacket I-symbol pairs seen since the counter was last reset. It gets

reset to 7. Whenever the value changes to a lower value, the MINI_CTR bit in the

ELM_INTR register is set. The counter is a gray code counter. The I-symbol pair count def-

initions are given in Table 3-10

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Table 3-10. Symbol Pair Count

MIN_IDLE_CTR (6–4)

I-Symbol Pair Count

100

101

111

110

010

011

001

000

7 or more

6

5

4

3

2

1

0

Bits 3–0 of the counter contain the value in the minimum idle gap counter. This is the number

of times the minimum number of interpacket idles has been seen since the last reset. It gets

reset to zero. The MINI_CTR bit in the ELM_INTR register is set whenever the counter in-

crements or whenever the counter overflows (reaches 16), depending on the setting of the

MINI_CTR_INTRS bit in the ELM_CNTRL_A. When the counter overflows, it remains at 16.

The minimum idle occurrence count definitions are given in Table 3-11.

Table 3-11. Minimum Idle Occurrence Count

MIN_IDLE_CTR (3–0) Minimum Idle Occurrence Count

0000

1000

1100

0100

0101

0111

1111

27

1

2

3

4

5

6

7

27

9

1010

0010

0011

0001

1001

1101

0110

1011

10

11

12

13

14

15

16

This counter can be used to monitor the activity of the smoother. The number of idles should

not go below 7. If they do, it can be desirable to monitor this counter.

3.2.27 ELM Built-in Self-Test Signature Register (ELM_BIST)

This 16-bit read-only register contains the resultant signature after execution of the ELM

section self-test. Refer to IEEE 1149.1 Test Access Port and BIST Operation for further de-

tails.

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SECTION 4

SIGNAL DESCRIPTION

The following section gives a pin-list for the Quad ELM. Because of package pin-count lim-

itations, a number of status pins available on the MC68837 have been eliminated.

4.1 CLOCK SIGNALS

Recovered Symbol Clock (WRSCLK, XRSCLK,YRSCLK, ZRSCLK)

WRSCLK, XRSCLK, YRSCLK, and ZRSCLK are 25-MHz TTL-level input signals driven

from individual clock recovery circuits off chip. WRSCLK, XRSCLK, YRSCLK, and

ZRSCLK are used to latch data received on WRDATAx, XRDATAx, YRDATAx, and

ZRDATAx respectively, and to operate the elasticity buffer in each of the four corre-

sponding ELMs.

Symbol Clock (SYMCLK)

SYMCLK is a 25-MHz TTL-level input signal used to clock WTDATAx, XTDATAx,

YTDATAx, and ZTDATAx. It is used in conjunction with BYTCLK to latch data received

on TXDATx.

Byte Clock (BYTCLK)

BYTCLK is a 12.5-MHz TTL-level input signal used to clock most internal operations and

to provide synchronization for data framing. It is used in conjunction with SYMCLK to

latch data received on TXDATx.

Node Processor Clock (NPCLK)

This TTL-level input signal is used to latch node processor inputs, run the NPI state

machine, and clock output signals to the node processor. It is separated from the BYT-

CLK for test and diagnostic purposes only. By running the BYTCLK at a much slower

rate than the NPCLK, several node processor byte transactions can occur while the

ELM is essentially halted. For normal operation, BYTCLK and NPCLK must be tied

together.

4.2 RECEIVE DATA SIGNALS

Ring Receive Data Bus (WRDATAx, XRDATAx,YRDATAx, ZRDATAx)

These TTL-level parallel input buses receive unframed data from the FCG receiver sec-

tions synchronously with the rising edge of WRSCLK, XRSCLK, YRSCLK or ZRSCLK.

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Thi d

t

t d

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M k

4 0 4

Signal Description

Receive Data Bus (PRCDATx, SRCDATx, RRCDATx)

These CMOS/TTL-level output buses are used to transfer symbol pairs to a MAC or, in

the case of a concentrator, to an external ELM. The 10 bits on each of the three buses

are clocked out on the rising edge of BYTCLK. Bits 9-5 of the bus contain the ﬁrst sym-

bol, and bits 4-0 contain the second symbol.

Receive Data Parity (PRCPAR, SRCPAR, RRCPAR)

These CMOS/TTL-level output signals contain the odd parity of the PRCDATx, SRC-

DATx, and RRCDATx buses respectively.

4.3 TRANSMIT DATA SIGNALS

Ring Transmit Data Bus (WTDATAx, XTDATAx,YTDATAx, ZTDATAx)

These CMOS/TTL-level parallel output buses transmit data to the FCG transmitter sec-

tions.

Transmit Data Bus (PTXDATx, STXDATx, RTXDATx)

These TTL-level input buses are used to transfer symbol pairs from a MAC or from an

external ELM. Bits 9-5 of the bus contain the ﬁrst symbol to be transmitted, and bits 4-0

contain the second symbol.

Transmit Data Parity (PTXPAR, STXPAR, RTXPAR)

These TTL-level input signals are the odd parity of the PTXDATx, STXDATx, and RTX-

DATx buses.

4.4 NODE PROCESSOR INTERFACE SIGNALS

Quad ELM Select (QPHYSEL)

This input signal selects the Quad ELM for the current NPI bus cycle. This TTL-level sig-

nal is asserted low.

Synchronous/Asynchronous Mode Select (SISELECT)

This TTL-level input signal determines whether or not QPHYSEL needs to be asserted

synchronously to NPCLK. When SISELECT is low (SISELECT = 0), QPHYSEL is an

asynchronous input. When SISELECT is high (SISELECT = 1), QPHYSEL must meet

the setup and hold requirements speciﬁed with relation to NPCLK. Users should not tog-

gle this pin. It is expected that this pin is tied to either V or GND.

CC

Node Processor Read/Write (NPRW)

This TTL-level input signal indicates whether the current bus cycle is a read (NPRW = 1)

or a write (NPRW = 0).

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Signal Description

Node Processor Address Bus (NPA7-NPA0)

This TTL-level input bus is used to select one of the ELM registers for a read or write

cycle. NPA7 selects between the new registers that have been added to the Quad ELM

and the registers that exist within each of the ELMs. NPA(6:5) select between ELMs W,

X, Y and Z, and the remaining address bits select the individual register within each of

these groupings. This address must be valid before a node processor cycle is initiated

by the QPHYSEL signal.

Power-Up Reset (PWRUP)

This TTL-level input signal provides a means of initializing the Quad ELM on power-up.

When this signal is negated, the Quad ELM is ready to begin normal operation. When

this signal is asserted low, it causes the following actions:

• The NPI, PCI, and BIST state machines are initialized to their idle state.

• All writable registers and all registers cleared on a read are cleared.

• The xFOTOFF signals are asserted, Q-symbols are transmitted on xTDATAx, and for

each ELM on the chip, TXDATx is looped back onto RCDATx.

PWRUP is asserted low to the Quad ELM. Once released, it is held asserted internally

for 10 BYTCLK cycles. Assertion and negation are asynchronous, although a warm

reset (PWRUP assertion after the chip is operational) will cause unpredictable chip out-

puts for a few clock cycles until the chip is initialized.

Node Processor Data Bus (NPD15-NPD0)

This TTL-level, 16-bit, bidirectional, three-state data bus is used to exchange data

between the ELM and the node processor.

Quad ELM Interrupt (QINT)

This output signal indicates an interrupt request from one or more of the ELMs and/or

counters. The user can gain more information about the interrupt by reading the interrupt

data register in the NPI. This CMOS/TTL-level signal is asserted low.

4.5 CLOCK RECOVERY SIGNALS

Fiber-Optic Transmitter Off (WFOTOFF, XFOTOFF,YFOTOFF, ZFOTOFF)

These are CMOS/TTL-level output signals used to control the ﬁber-optic transmitter.

When asserted low, these signals cause their respective FCG transmitters to turn off (no

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Signal Description

light output) the ﬁber-optic transmitter. These signals are asserted if any of the following

conditions occur:

• Either the FOT_OFF bit, the FCG_LOOP_CONTROL bit, or the LM_LOC_LOOP bit is

set in ELM_CNTRL_A, or

• The MAINT_LS field = Transmit_QUIET and PC_MAINT = ON in control register B, or

• The PCM logic has set LS_REQUEST = Transmit_QUIET, or

• BIST is active.

• Conditions set in the FOTOFF_ASSERT timer are met.

Signal Detect (WSD, XSD,YSD, ZSD)

These input signals are indications from the respective FCG receivers of the presence of

a signal on the media. For each of the ELMs on the Quad ELM, the value of this signal is

held in status register A (ELM_STATUS_A), and the interrupt event register (ELM_INTR)

LSD bit is set whenever that particular ELM’s Signal Detect is asserted. These TTL-level

signals are asserted high.

FCG Control Output (WLOOPBCK, XLOOPBCK,YLOOPBCK, ZLOOPBCK)

These CMOS/TTL-level output signals control the receive symbol multiplexer in the

FCGs. If xLOOPBCK = 0, the MUX selects its input from the FCG transmitter. If xLOOP-

BCK = 1, the MUX selects its input from the ﬁber-optic receiver.

4.6 TEST SIGNALS

Reset RSCLK (RESRCK)

This TTL-level signal is used to reset the divide-by-two ﬂip-ﬂop that generates the

RSCLK. It is needed for simulation and test purposes only. In actual use, this pin should

be tied to ground.

Factory Test (TESTPIN)

This pin is reserved for factory testing purposes. Users should tie this pin to V .

CC

JTAG Reset (TRST)

This TTL-level signal is used to reset the JTAG circuitry. It is active low.

JTAG Data Output (TDO)

This is a CMOS/TTL-level serial output from either the instruction register or one of the

test data registers. JTDO changes on the falling edge of JTCK.

JTAG Data Input (TDI)

This TTL-level input signal is a serial test data input that is sampled on the rising edge of

JTCK.

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Signal Description

JTAG Test Mode Select (TMS)

This TTL-level input select signal is sampled on the rising edge of JTCK to sequence the

test controller’s state machine.

JTAG Clock (TCK)

This TTL-level input signal is the clock used by JTAG to synchronize the test logic. It is

independent of any of the system clocks.

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SECTION 5

NODE PROCESSOR INTERFACE SYNCHRONOUS

OPERATION

The NPI serves to interface an external processor and the control and status registers in the

Quad ELM. The interface is general purpose; it is not designed for a specific processor.

5.1 NPI OPERATION

The synchronous NPI operation is controlled by NPCLK. In normal operation, this clock is

the same as BYTCLK. The two clocks are separate only for diagnostics and testing. Chip

operation can be halted by stopping BYTCLK while allowing register reads via the NPCLK

There is only a single input register to the Quad ELM; therefore, only a single register to be

updated by a write cycle or altered (e.g., cleared) by a read cycle should be accessed when

BYTCLK is inactive. If multiple registers are accessed while BYTCLK is inactive, only the

last register accessed is properly written.

For synchronous operation, all signals in the NPI must be synchronous with NPCLK. They

must be stable a setup time before, and a hold time after, a rising edge of this clock.

The synchronous NPI supports two types of bus transactions—a read cycle and a write cy-

cle. A read or write transaction can occur only every two NPCLK cycles (160 ns) although it

is possible to extend the transaction. Read or write transactions to nonexistent registers,

writes to read-only registers, and reads of write-only registers are all considered program-

ming errors; the Quad ELM will ignore the transaction (not drive the data bus on a read and

not accept data on a write) and set the NP_ERR bit in the respective ELM_INTR register or

the NP_ERR bit in the INT_DATA register, depending on the address. Some registers can

only be written under certain conditions. If a write is attempted to a register that cannot be

written at that time, the NP_ERR bit is set.

5.2 SYNCHRONOUS READ CYCLE

The NP uses a read cycle to read data from registers on the Quad ELM (see Figure 5-1).

Some registers are cleared when read.

A read of a register on the Quad ELM is initiated by the assertion of QPHYSEL. The QPHY-

SEL line is sampled by the rising edge of NPCLK. It must be asserted a setup time before

and must remain asserted for a hold time after this clock edge. The QPHYSEL signal can

be asserted by the host bus logic to introduce as many wait states as necessary. NPA must

be valid a minimum of 2 ns before QPHYSEL is asserted, and must also satisfy a setup time

and hold time relative to the rising edge of NPCLK. At least 40 ns after this clock edge, the

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Quad ELM begins to drive the NPDx bus. The Quad ELM waits at least 40 ns to allow the

chip previously driving the bus time to three-state the bus.

After the next rising edge of the NPCLK (the second rising edge after the assertion of QPHY-

SEL), the data on the NPDx bus is valid. It remains valid until after the second rising edge

of NPCLK after the negation of QPHYSEL. The Quad ELM three-states the NPDx bus within

40 ns after this clock edge.

The timing described allows a read cycle to occur every 160 ns. However, if the NP needs

to extend the cycle and have the NPDx bus valid longer than one clock cycle, it can delay

the negation of QPHYSEL (see Figure 5-1). For a minimum-length read cycle, the NP must

negate QPHYSEL a setup time before the second rising edge of NPCLK following the as-

sertion of QPHYSEL. If QPHYSEL remains asserted for a hold time after the second rising

edge of NPCLK, the Quad ELM continues to drive the NPDx bus with valid data until after

the fourth rising edge of NPCLK. The NP can extend the read cycle indefinitely by maintain-

ing the assertion of QPHYSEL.

BYTCLK (NPCLK)

QPHYSEL

NPRW

NPA

NPD

Figure 5-1. Node Processor Bus Read Cycles

5.3 SYNCHRONOUS WRITE CYCLE

The NP uses a write cycle to write data into a register on the Quad ELM (see Figure 5-2). It

is similar to the read cycle, previously described. The principal differences are as follows:

1. The NPRW line must be low a setup time before, and a hold time after, the first rising

edge of NPCLK after QPHYSEL is asserted.

2. The data to be written must be valid a setup time before, and a hold time after, the sec-

ond rising edge of NPCLK after QPHYSEL is asserted.

The host bus logic can assert QPHYSEL to introduce as many wait states as necessary.

Like the Quad ELM, the NP must three-state the NPDx bus within 40 ns after the second

rising edge of NPCLK after QPHYSEL is negated. Thus, by delaying the negation of QPHY-

SEL, the NP can extend the time it has to three-state the NPDx bus. The negation of QPHY-

SEL has no effect on the Quad ELM in a write cycle. That is, the data on NPD is still captured

by the Quad ELM on the first rising edge of NPCLK following the assertion of QPHYSEL.

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Node Processor Interface Synchronous Operation

BYTCLK (NPCLK)

QPHYSEL

NPRW

NPA

NPD

Figure 5-2. Node Processor Bus Write Cycles

5.4 ASYNCHRONOUS READ AND WRITE CYCLES

The asynchronous operation of the NPI is very similar to the synchronous operation, except

that the timing of the NPI signals is with respect to the assertion of QPHYSEL instead of NP-

CLK. Refer to the timing diagrams in 9.5 Asynchronous Node Processor Interface Timing

for more detailed information. In order to select asynchronous operation, SISELECT must

be tied low.

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SECTION 6

LINK MANAGEMENT OPERATION

The ELM provides facilities for CMT and link status indications as set forth in the ANSI FDDI

SMT document. CMT defines the operation of PHY insertion and removal, and the connec-

tion of PHY entities to the MAC entities. PCM, a subset of CMT, is the management of a

physical connection between the PHY being managed and another PHY.

The logic blocks implementing these features are the LSM, the LEM, the data stream gen-

erator, and the PCM. These logic blocks are discussed in this section.

6.1 LINE STATE MACHINE OPERATION

The LSM constantly monitors incoming aligned symbol pairs. The current symbol pair is en-

coded and compared to the encoded value of the previous symbol pair. The symbol pairs

are counted until a line state is reached. Once a line state is reached, the counter is stopped,

the new line state is stored, and the UNKN_LINE_ST bit is reset to zero. Anytime a Noise

(N) symbol is received, the line state is set to Noise Line State, and the UNKN_LINE_ST bit

is reset to zero.

The recognition of these line states is reported to the PCM, which uses this information for

either insertion or removal of the station from the ring, ring recovery, or maintenance. The

LSM has no reset. After power-up into any state, it will attain a valid state by satisfying the

conditions for attaining a particular line state as listed in Table 6-1.

Table 6-1. Line State Machine Line States

Line State Name

Noise Line State

Active line State

Idle Line State 4

Quiet Line State

Master Line State

Halt Line State

Condition

Any Line State Not Defined

JK Symbol Pair

4 I-Symbols

16 Q-Symbols

8 Pairs of H/Q- or Q/H-Symbols

16 I-Symbols

6.2 LINK ERROR MONITOR OPERATION

The LEM hardware consists of a detector, accumulator, and threshold element. The detec-

tor is a state machine that constantly monitors incoming symbol pairs on the receive data

path. When link error events are detected, they are counted by the 8-bit link error event

counter register. When the link error event counter register matches the count written to the

link error event threshold register, the LE_CTR bit in the ELM_INTR is set.

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6.3 DATA STREAM GENERATOR

The data stream generator block uses a multiplexer for the purpose of generating a symbol

pair at the request of the PCM (or external control when the PCM is in the MAINT state) via

LS_REQUESTx, the repeat filter via RF_CNTRLx, or by transmitting the symbol pair from

the internal TXDATx. Table 6-2 summarizes the operation of this block.

Table 6-2. Data Stream Generator Output

LS_REQUEST (2–0)

RF_CNTRL (1–0)

DATA_STRM (9–0)

Q-Symbol Pair

000

001

010

011

100

101

110

111

XX

00

I-Symbol Pair

H-Symbol Pair

M-Symbol Pair

Q-Symbol Pair

Symbol Pair from TXDATx

I-Symbol Pair

01

10

H-Symbol Pair

I-Symbol Pair

11

XX

Q-Symbol Pair

NOTE: X = Don't care

6.4 PHYSICAL CONNECTION MANAGEMENT

The ELM implements CMT through a PCM state machine as specified in the ANSI FDDI

SMT standard. Once a connection has been established, the ELM also performs PCI. The

implementation of the PCM and PCI state machines and their functions within CMT are de-

scribed in the following subsections.

CMT defines the rules that govern the allowable topologies in an FDDI ring. Fundamental to

this task is the management of a connection between two PHYs in adjacent stations. It is

the task of the PCM state machines in both stations to cooperate in forming a connection

between the two PHYs within the rules established by CMT. The allowable types of attach-

ment as defined by the MIC connector are as follows:

• A Primary Ring In/Secondary Ring Out

• B Secondary Ring In/Primary Ring Out

• S Single Attachment End Station

• M Concentrator Attachment of an End Station

In addition, CMT defines the type of physical connection between two physical attachments

to be determined by the PHY types at each end of the connection. The characteristics of a

type of connection determine if that connection will be allowed, if the SMT will be notified of

possible connection problems, and the connection mode that will be established. Table 6-3

from the ANSI FDDI SMT document lists the connection rules, and Figure 6-1 illustrates

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some possible station interconnections to graphically show the types of stations as imple-

mented with concentrators and end stations.

Table 6-3. Connection Rules

Other PHY

A

V, N

V

B

V

S

V, N

V

M

V< P

V

A

B

S

M

This

PHY

V,N

V, N

V

V, N

V

X

NOTE:

V = Indicates a valid connection

X = Indicates an illegal connection

N = Indicates that notiﬁcation to SMT is required

P = Indicates, if active, prevent THRU in CFM and

PHY B takes precedence

More details of FDDI network topology can be found in the ANSI FDDI SMT document.

6.4.1 PCM State Machine

CMT secures a deterministic ring topology, independent of the sequence of station power-

up, etc., by allowing only a specific set of connection types. The primary purpose of PCM is

to enforce these allowable connections. The PCM announces its attachment type to the re-

mote PCM and listens for the type of attachment from the remote PCM. If they are compat-

ible, the PCM accepts the connection and reports the type of connection to the station

configurator. Once the connection type has been established, the two PCMs share in testing

the pair of physical links between them. If this test is successful, the link can then be inserted

into the ring. Note that PCM operates between two cooperating PHY entities to determine

the viability of the link between them, regardless of the actual ring operation. This fact can

be observed by reference to the upper pair of concentrators in Figure 6-1 in which the vari-

ous PHYs are connected to an input on one ring and an output on the other ring. During pow-

er-up, the PHYs will determine the viability of the connection; once both connections are

valid, multiplexing between the ELMs and MACs (if any in the concentrator) will establish

the topology of the ring or rings.

The architectural model for the PCM consists of ten states: OFF, BREAK, TRACE, CON-

NECT, NEXT, SIGNAL, JOIN, VERIFY, ACTIVE, and MAINT for both the ANSI standard

and the hardware realization. The ELM PCM state machine accomplishes all of the transi-

tions in the ANSI FDDI SMT standard, although transitions between some states are en-

abled by software in certain situations. Interrupts are provided to furnish indications when

actions have been completed that require software to specify actions for continuing the PCM

state transitions. It is also possible to accomplish non-ANSI-specified action by operating in

the MAINT state. The following PCM machine descriptions, along with the ANSI FDDI SMT

standard, can be used to produce ANSI-compliant SMT software.

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6.4.1.1 BIT SIGNALING MECHANISM

The signaling protocol is implemented to reduce the software processing overhead and to

allow enough flexibility to change the actual pseudocode without affecting the silicon imple-

mentation.

When the PCM is in the OFF state, all parameter registers and configuration registers are

loaded with the appropriate values. The transmit vector length register is written with the val-

ue n–1 (n = the number of bits to be transmitted). The transmit vector register is written with

the bit pattern to be transmitted. PC_START is then written into the PCM_CNTRL field of

ELM_CNTRL_B. The PCM then transitions through the BREAK, CONNECT, and NEXT

states. It then transitions back and forth between the NEXT state and the SIGNAL state until

all bits in the transmit vector register are transmitted. While the PCM is transmitting all the

bits, it also receives the corresponding bits from a remote station and forms a receive vector

that is stored in the receive vector length register. When all bits are received for the trans-

mitted bits, the PCM_CODE interrupt bit is set. The NP can then read the receive vector

length register. Note that the PCM is still in the NEXT state.

If for any reason (other than PC_START) the PCM transitions to the BREAK state, then a

PC_START has to be issued before the connection process can begin again. This allows

the transmit vector length register and the transmit vector register to be reinitialized. Also,

any transition to the BREAK state sets the PCM_BREAK interrupt bit and writes the reason

for the transition in the ELM_STATUS_B BREAK_REASON field.

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SECONDARY

RING

PRIMARY

RING

A-B

CONNECTION

A

B

A

B

WIRING

CONCENTRATOR

M

M-S

CONNECTION

S

END STATIONS

M-A

CONNECTION

B

A

M

S

WIRING

CONCENTRATOR

S

M

FULL-DUPLEX

CONNECTION

END

STATION

S

Figure 6-1. Sample FDDI PHY Connections

If the NP wants to do a loopback function for the purpose of a Link Confidence Test, it can

do so by setting the PC_LOOP bits in ELM_CNTRL_B. If the PCM is not in the NEXT state

or if it is in the NEXT state but PCM_SIGNALING is set, then setting the PC_LOOP bits will

have no effect on the state machine. Normally, these bits should be set after the

PCM_CODE interrupt bit is set. The NP can set the station to do a transmit_PDR function

or transmit_Idle function or a remote loopback function. If the LONG bit is not set in

ELM_CNTRL_B, the Link Confidence Test will last for LC_SHORT (a writable parameter)

period of time, after which the PCM_CODE interrupt bit is set. If the LONG bit is set, then

the ELM will be in Link Confidence Test mode continuously until the software interrupts it by

giving one of the control commands (e.g., write vector, PC_START, etc.). When PC_LOOP

is set, the PCM sets the TDF flag internally.

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After the Link Confidence Test is completed (i.e., after LC_SHORT or after Halt or Master

Line State is received), the PCM_CODE interrupt bit is set. If the NP decides to transmit

more signaling bits, it should load the transmit vector length register with a new value of n

and then load the transmit vector register with the bit pattern to be transmitted. The PCM

again starts transmitting these bits and alternates between the NEXT and SIGNAL states

until all bits have been transmitted, as indicated when the PCM_CODE interrupt bit is set

again.

This sequence continues until all the bits have been transmitted and the NP writes PC_JOIN

in ELM_CNTRL_B . The PCM then leaves the NEXT state and enters the JOIN state. Set-

ting PC_JOIN has no effect when the PCM is not in the NEXT state or when

PCM_SIGNALING is set. However, if PC_JOIN is set when the Link Confidence Test is in

progress, then the Link Confidence Test will be aborted, and the PCM JOIN state will be ini-

tiated.

6.4.1.2 NOISE DETECTION MECHANISM

The TNE timer in the PCM times the period between Idle Line State receptions. This timer

is loaded with the noise time register parameter when the LSM leaves the Idle Line State.

The TNE timer keeps counting noise until Idle Line State is again detected. If this timer ex-

pires while in the ACTIVE state, the PCM will break the link and transition to the BREAK

state. In the ACTIVE state, the TNE timer starts counting noise only after the LSF bit is set.

If PC_TRACE is received and the TNE timer expires in the same cycle, then the transition

to the TRACE state is taken. This timer is ignored in all PCM states except the ACTIVE state.

6.4.1.3 NOISE IN MAINT STATE

If the NOISE_TIMER bit in ELM_CNTRL_A is cleared, then the NP can write to the TNE

timer if the PCM is in MAINT state. If the NOISE_TIMER bit is set, the TNE timer is used in

the MAINT state to time the noise as previously described. If the TNE timer expires, then the

TNE_EXPIRED interrupt bit is set.

6.4.1.4 OPERATION IN TRACE STATE

If the trace propagation (transition 88c) is detected in the ACTIVE state, then the TRA-

CE_PROP interrupt bit is set. In the ACTIVE state, if PC_TRACE is received and a transition

is made to the TRACE state, the station remains inserted, Master Line State is sourced on

the TDATAx port, and no scrubbing is performed. If Master Line State is detected in the AC-

TIVE state, the TRACE_PROP interrupt bit is set. If Quiet Line State or Halt Line State is

detected (transition 22a), then the SELF_TEST interrupt bit is set.

6.4.2 Physical Connection Insertion

The ELM implements PCI to intelligently bring a new connection into a ring and to remove

an existing connection from a ring. The PCI state machine works in conjunction with the

PCM state machine to control the RCDATx; and TXDATx paths of the ELM

There are three primary functions of the PCI state machine:

• Provide a bypass path between TXDATx and RCDATx.

• Provide a scrubbing function upon the insertion and removal of a station from the ring.

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• Provide a direct data path between the fiber and the MAC.

The operation of the PCI state machine depends on whether the CLASS_S bit in

ELM_CNTRL_B is set and whether the PCM state machine is in the MAINT state.

6.4.2.1 PCI OPERATION FOR NON-CLASS-S TYPE STATION

After a reset, the PCI state machine will be in the REMOVED state. If the station is not a

class-S type, the ELM will be in the bypass mode whereby data input on TXDATx is directly

output on RCDATx.

When the PCM state machine enters the ACTIVE state and asserts the SC_JOIN flag, the

PCI state machine enters the INSERT_SCRUB state and I-symbol pairs are sourced on

RCDATx. At the same time, the PCM state machine causes I-symbols to be output on

WTDATAx, XTDATAx, YTDATAx, or ZTDATAx.

The PCI state machine remains in the INSERT_SCRUB state for T_SCRUB length of time,

after which it enters the INSERTED state. Upon entering the INSERTED state, the PCM_E-

NABLED interrupt bit is asserted. In this state, a direct path exists from TXDATx to TDATAx.

If the connection is broken and the PCM state machine enters the BREAK state, the PCI

state machine enters the REMOVE_SCRUB state, and I-symbol pairs are sourced on RC-

DATx. Because the PCM state machine is in the BREAK state, Q-symbols are sourced on

TDATAx. While scrubbing is being performed, the PCM state machine will not restart the

connection process. The PCI state machine remains in the REMOVE_SCRUB state for

T_SCRUB length of time and then enters the REMOVED state.

6.4.2.2 PCI OPERATION FOR CLASS-S TYPE STATION

For a class-S type station single attach, the PCI operation is identical to the non-class-S type

with one exception—whenever the PCI state machine would normally be in the REMOVED

state, it will be in the INSERTED state. Thus, before entering INSERT_SCRUB or after leav-

ing REMOVE_SCRUB, rather than putting the ELM in the bypass mode, PHY_INVALID is

output on RCDATx.

6.4.2.3 PCI OPERATION IN MAINT STATE

When the PCM state machine is in the MAINT state, the PCI state machine does not control

the previously mentioned functions. In the MAINT state, all data paths are under the control

of software via several control bits in ELM_CNTRL_A . Software can also override the PCI

functions when the PCM state machine is not in the MAINT state by setting the

CONFIG_CNTRL bit in ELM_CNTRL_B .

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SECTION 7

QUAD ELM CONFIGURATION EXAMPLES

One possible configuration of the Quad ELM is shown in Figure 7-1. If the Primary Ring is

connected to the P-bus, while the Secondary Ring is connected to the S-bus, both rings of

the dual-ring FDDI network are being utilized. In this configuration, the R-Bus is not being

used. In the connection scheme shown, Stations 1 and 3 are connected to the Primary Ring,

while Stations 2 and 4 are connected to the Secondary Ring. Note that each of the ELMs

can be configured individually to place it on any one of the three buses, allowing a wide

range of potential connection schemes.

R-Bus

S-Bus

P-Bus

S-Bus

P-Bus

ELM

W

ELM ELM

ELM

Z

X

Y

.

Station 1

Station 3

Station 2

Station 4

Figure 7-1. Utilization of Both the Primary and Secondary FDDI Rings

A dual ring concentrator is easily implemented using the Quad ELM. An example of this is

shown in Figure 7-2. The the crossbar switching structure is used to route the Primary Ring

over the P-bus and the Secondary Ring over the S-bus. Once again, the R-bus is not being

used. All of the M-port ELMs in this concentrator configuration have the ability to attach to

either the Primary Ring, the Secondary Ring, or neither of the two rings.

Note

In all examples in this section, the following apply:

R-bus represents RTXDAT(9:0), RTXPAR, RRCDAT(9:0), and RRCPAR.

S-bus represents STXDAT(9:0), STXPAR, SRCDAT(9:0), and SRCPAR.

P-bus represents PTXDAT(9:0), PTXPAR, PRCDAT(9:0), and PRCPAR.

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7.1 ROVING MAC

Figure 7-2. Dual-Ring MAC-Less Concentrator Using Two Quad ELMs

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A potential use for the third data bus is demonstrated in Figure 7-3. The “roving MAC” con-

figuration provides a connection between an external MAC and any of the internal ELMs.

This figure shows the external MAC connected to ELM X via the R-bus. The remaining three

ELMs remain connected to one of the rings on the network via either the P-bus or the S-bus.

“Roving MAC”

MAC

R-bus

S-bus

P-bus

ELM

W

ELM ELM

ELM

Z

X

Y

Station 1

Station 3

Station 2

Station 4

Figure 7-3. Roving MAC Connected to Station 2 Via the S-bus

Each ELM within the Quad ELM can be individually configured to place it on either the P-

bus, the S-bus or the R-bus. This is accomplished with the crossbar switch. Each of the

ELMs has a register in the Node Processor Interface (NPI) that determines its particular con-

nection scheme.

The “roving MAC” configuration can also be applied to a concentrator application, as can be

seen in Figure 7-4. In the configuration shown, the MAC is able to access any of the M-port

ELMs via the R-bus, while the remaining ELMs remain connected to one of the FDDI Rings

via the P-bus and the S-bus.

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.

Figure 7-4. Roving MAC Concentrator Using Two Quad ELMs

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7.2 MORE COMPLEX CONCENTRATOR

The MC68847 Quad ELM can be combined with other Motorola FDDI devices to construct

more complex concentrators. The example shown in Figure 7-5 illustrates one such config-

uration. In this concentrator design, two MC68847 Quad ELM chips act as the A and B ports

for the concentrator. Two Quad ELM parts provide eight potential M ports that can each sit

on either of the two buses. Finally, one MC68838 MAC chip performs the duties of a roving

MAC. Note that the four muxes shown in the diagram are external to both the Quad ELM

and MAC chips.

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Figure 7-5. Dual-Ring Full-Featured Concentrator

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SECTION 8

IEEE 1149.1 TEST ACCESS PORT AND BIST

OPERATION

The Quad ELM provides a dedicated user-accessible test access port (TAP) that is fully

compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architec-

ture. Problems associated with testing high-density circuit boards have led to development

of this proposed standard under the sponsorship of the Test Technology Committee of IEEE

and the Joint Test Action Group (JTAG). The Quad ELM implementation supports circuit-

board test strategies based on this standard.

The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data

registers. A boundary scan register links all device signal pins into a single shift register. The

test logic, implemented utilizing static logic design, is independent of the device system log-

ic. The Quad ELM implementation provides the capability to:

1. Perform boundary scan operations to test circuit-board electrical continuity.

2. Bypass the Quad ELM for a given circuit-board test by effectively reducing the bound-

ary scan register to a single cell.

3. Sample the Quad ELM system pins during operation and transparently shift out the re-

sult in the boundary scan register.

4. Disable the output drive to pins during circuit-board testing.

8.1 OVERVIEW

This section, which includes aspects of the IEEE 1149.1 implementation that are specific to

the Quad ELM, is intended to be used with the supporting IEEE 1149.1 document. The dis-

cussion includes those items required by the standard to be defined and, in certain cases,

provides additional information specific to the Quad ELM implementation. For internal de-

tails and applications of the standard, refer to the IEEE 1149.1 document.

An overview of the Quad ELM implementation of IEEE 1149.1 is shown in Figure 8-1. The

Quad ELM implementation includes a TAP controller, a 4-bit instruction register, and two

test registers (a 1-bit bypass register and a 163-bit boundary scan register). This implemen-

tation includes a dedicated TAP consisting of the following signals:

• TCK—a test clock input to synchronize the test logic.

• TMS—a test mode select input (with an internal pullup resistor) that is sampled on the

rising edge of TCK to sequence the TAP controller’s state machine.

• TDI—a test data input (with an internal pullup resistor) that is sampled on the rising

edge of TCK.

MOTOROLA

MC68847 USER’S MANUAL

8-1

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IEEE 1149.1 Test Access Port and BIST Operation

• TDO—a three-stateable test data output that is actively driven in the shift-IR and shift-

DR controller states. TDO changes on the falling edge of TCK.

• TRST—an asynchronous reset with an internal pullup resistor that provides initialization

of the TAP controller and other logic required by the standard.

194

0

BOUNDARY SCAN REGISTER

M

U

X

TDI

BYPASS

DECODER

1

M

U

X

3

2

0

TDO

4-BIT INSTRUCTION REGISTER

TMS

TCK

TAP

CTLR

TRST

Figure 8-1. Test Logic Block Diagram

8.2 TAP CONTROLLER

The TAP controller is responsible for interpreting the sequence of logical values on the TMS

signal. It is a synchronous state machine that controls the operation of the JTAG logic. The

state machine is shown in Figure 8-2. The value shown adjacent to each arc represents the

value of the TMS signal sampled on the rising edge of the TCK signal. For a description of

the TAP controller states, refer to the IEEE 1149.1 document.

8-2

MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

TEST LOGIC

RESET

1

0

1

SELECT-DR_SCAN

SELECT-IR_SCAN

0

RUN-TEST/IDLE

0

CAPTURE-DR

0

1

CAPTURE-IR

0

SHIFT-IR

1

0

SHIFT-DR

1

EXIT1-IR

0

EXIT1-DR

0

PAUSE-IR

1

PAUSE-DR

1

0

EXIT2-IR

1

EXIT2-DR

1

UPDATE -IR

0

UPDATE-DR

0

1

Figure 8-2. TAP Controller State Machine

8.3 BOUNDARY SCAN REGISTER

The Quad ELM IEEE 1149.1 implementation has a 163-bit boundary scan register. This reg-

ister contains bits for all device signal and clock pins and associated control signals.

A single register bit in the boundary scan register can place all Quad ELM pins in a high-

impedance state. A second boundary scan register bit controls the direction of I/O for the

scan chain. The control bits and their bit positions are listed in Table 8-1.

.

8-3

MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

Table 8-1. Boundary Scan Control

Bits

Name

Bit Number

PAD_DIR

PAD_ENA

64

0

The boundary scan bit definitions are listed in Table 8-2.

The first column in the table defines the bit’s ordinal position in the boundary scan register.

The first shift register cell to be shifted out is defined as bit 0; the last bit to be shifted out is

162.

The second column references one of the five Quad ELM cell types depicted in Figure 8-3–

Figure 8-7, which describe the cell structure for each type.

The third column lists the pin name for all pin-related cells or defines the name of bidirec-

tional control register bits.

Bidirectional pins include a single scan cell for data (IO.Cell) as depicted in Figure 8-6.

These bits are controlled by the cell shown in Figure 8-5. The value of the control bit deter-

mines whether the bidirectional pin is an input or an output. One or more bidirectional data

cells can be serially connected to a control cell as shown in Figure 8-8. Note that, when sam-

pling the bidirectional data cells, the cell data can be interpreted only after examining the

I/O control cell to determine pin direction.

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

Table 8-2. Boundary Scan Bit Definition

Bit

Num

Cell

Type

Pin/Cell

Name

Bit

Num

Cell

Type

Pin/Cell

Name

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

I.Pin

WRSCLK

WRDATA4

WRDATA3

WRDATA2

WRDATA1

WRDATA0

WSD

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

O.Latch

I.Pin

ZTDATA1

ZTDATA2

ZTDATA3

ZTDATA4

ZLOOPBCK

ZFOTOFF

ZRSCLK

I.Pin

O.Latch

I.Pin

XTDATA0

XTDATA1

XTDATA2

XTDATA3

XTDATA4

XLOOPBCK

XFOTOFF

XRSCLK

I.Pin

ZRDATA4

ZRDATA3

ZRDATA2

ZRDATA1

ZRDATA0

ZSD

I.Pin

O.Latch

I.Pin

PRCPAR

PRCDATA0

PRCDATA1

PRCDATA2

PRCDATA3

PRCDATA4

PRCDATA5

PRCDATA6

PRCDATA7

PRCDATA8

PRCDATA9

STXPAR

I.Pin

XRDATA4

XRDATA3

XRDATA2

XRDATA1

XRDATA0

XSD

I.Pin

O.Latch

I.Pin

YTDATA0

YTDATA1

YTDATA2

YTDATA3

YTDATA4

YLOOPBCK

YFOTOFF

YRSCLK

I.Pin

STXDAT0

STXDAT1

STXDAT2

STXDAT3

STXDAT4

STXDAT5

STXDAT6

STXDAT7

STXDAT8

STXDAT9

RRCPAR

I.Pin

98

I.Pin

YRDATA4

YRDATA3

YRDATA2

YRDATA1

YRDATA0

YSD

97

I.Pin

96

I.Pin

95

I.Pin

94

I.Pin

93

I.Pin

92

I.Pin

O.Latch

ZTDATA0

91

O.Latch

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MC68847 USER’S MANUAL

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IEEE 1149.1 Test Access Port and BIST Operation

Table 8-2. Boundary Scan Bit Definition

Bit

Num

Cell

Type

Pin/Cell

Name

Bit

Num

Cell

Type

Pin/Cell

Name

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

O.Latch

I/O.Cell

IO.Ctl

RRCDAT0

RRCDAT1

RRCDAT2

RRCDAT3

RRCDAT4

RRCDAT5

RRCDAT6

RRCDAT7

RRCDAT8

RRCDAT9

NPD0

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

I.Pin

RESRCK

NPA7

I.Pin

NPA6

I.Pin

NPA5

I.Pin

NPA4

I.Pin

NPA3

I.Pin

NPA2

I.Pin

NPA1

I.Pin

NPA0

I.Pin

TRST

I.Pin

TCK

NPD1

I.Pin

TMS

NPD2

O.Latch

I.Pin

TDO

NPD3

TDI

NPD4

I.Pin

RTXDAT9

RTXDAT8

RTXDAT7

RTXDAT6

RTXDAT5

RTXDAT4

RTXDAT3

RTXDAT2

RTXDAT1

RTXDAT0

RTXPAR

SRCDAT9

SRCDAT8

SRCDAT7

SRCDAT6

SRCDAT5

SRCDAT4

SRCDAT3

SRCDAT2

SRCDAT1

SRCDAT0

SRCPAR

NPD5

I.Pin

NPD6

I.Pin

NPD7

I.Pin

NPD8

I.Pin

NPD9

I.Pin

NPD10

I.Pin

NPD11

I.Pin

NPD12

I.Pin

NPD13

I.Pin

NPD14

I.Pin

NPD15

O.Latch

PAD_DIR

NPRW

I.Pin

NPCLK

BYTCLK

SYMCLK

PWRUP

SISELECT

QPHYSEL

QINT

I.Pin

O.Latch

I.Pin

TESTPIN

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

Table 8-2. Boundary Scan Bit Definition

Bit

Num

Cell

Type

Pin/Cell

Name

Bit

Num

Cell

Type

Pin/Cell

Name

18

17

16

15

14

13

12

11

10

9

I.Pin

PTXDAT9

PTXDAT8

PTXDAT7

PTXDAT6

PTXDAT5

PTXDAT4

PTXDAT3

PTXDAT2

PTXDAT1

PTXDAT0

8

7

6

5

4

3

2

1

0

I.Pin

PTXPAR

WTDATA0

WTDATA1

WTDATA2

WTDATA3

WTDATA4

WLOOPBCK

WFOTOFF

PAD_ENA

O.Latch

HI_Z.Ctl

TO NEXT

CELL

1—EXTEST / CLAMP

0—OTHERWISE

SHIFT DR

G1

DATA FROM

SYSTEM

LOGIC

TO OUTPUT

BUFFER

1

MUX

G1

1

D

MUX

D

C

FROM

LAST

CELL

CLOCK DR

UPDATE DR

Figure 8-3. Output Latch Cell (O.Latch)

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

TO DEVICE

LOGIC

INPUT

G1

1

TO NEXT

MUX

1D

C1

CELL

1

CLOCK DR

FROM LAST SHIFT DR

CELL

Figure 8-4. Input Pin Cell (I.Pin)

1 – EXTEST

0 – OTHERWISE

HI_Z

G1

1

OUTPUT

CONTROL

FROM

SYSTEM

LOGIC

TO OUTPUT

DIRECTION

MUX

1

TO NEXT

CELL

G1

1

1D

C1

MUX

1D

C1

1

SHIFT DR

CLOCK DR

FROM

LAST

CELL

UPDATE DR

Figure 8-5. Control Cell (IO.Ctl)

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

1—EXTEST / CLAMP

0—OTHERWISE

G1

OUTPUT CONTROL

1

FROM SYSTEM LOGIC

MUX

FROM IO

1

CONTROL CELL

1—EXTEST / CLAMP

0—OTHERWISE

TO NEXT CELL

SHIFT DR

G1

EN

I/O

DATA FROM

SYSTEM

LOGIC

TO OUTPUT

DRIVER

1

MUX

G1

1

D

C

MUX

1

MUX

D

C

CLOCK DR

UPDATE DR

FROM

DIRECTION

CTL

FROM I/O PIN

FROM

LAST

CELL

Figure 8-6. Bidirectional Data Cell (IO.Cell)

TO NEXT

CELL

SHIFT DR

1D

C1

Q

FROM

PREVIOUS CELL

1D

C1

PAD_ENABLE

CLOCK DR

UPDATE DR

1 = EXTEST/CLAMP

0 = OTHERWISE

HI_Z

Figure 8-7. High Impedance Control Cell (HI_Z.Ctl Cell)

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

DIRECTION CTL

*

OUTPUT DATA

ENABLE FROM

SYSTEM LOGIC

I/O

IO CELL

INPUT DATA

FROM LAST CELL

NOTE: More than one IO.Cell could be serially connected and controlled by a single IO.Ctl.

Figure 8-8. General Arrangement for Bidirectional Pins

8.4 INSTRUCTION REGISTER

The Quad ELM IEEE 1149.1 implementation includes the three mandatory public instruc-

tions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional

CLAMP instruction. One additional public instruction (HI-Z) provides the capability for dis-

abling all device output drivers. The Quad ELM includes a 4-bit instruction register without

parity consisting of a shift register with four parallel outputs. Data is transferred from the shift

register to the parallel outputs during the update-IR controller state. The four bits are used

to decode the five unique instructions listed in Table 8-3.

Table 8-3. Instruction Decoding

Code

Instruction

B3

0

B2

0

B1

0

B0

0

EXTEST

SAMPLE

HI-Z

0

1

0

1

0

1

0

CLAMP

BYPASS

1

ALL OTHER CASES

The parallel output of the instruction register is reset to all ones in the test-logic-reset con-

troller state. Note that this preset state is equivalent to the BYPASS instruction.

8-10

MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

8.4.1 EXTEST

The external test (EXTEST) instruction selects the 163-bit boundary scan register.

By using the TAP, the register is capable of; a) scanning user-defined values into the output

buffers, b) capturing values presented to input pins, c) controlling the direction of bidirection-

al pins, and d) controlling the output drive of the output pins. For more details on the function

and use of EXTEST, please refer to the IEEE 1149.1 document.

8.4.2 SAMPLE/PRELOAD

The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a

means to obtain a snapshot of system data and control signals. The snapshot occurs on the

rising edge of TCK in the capture-DR controller state. The data can be observed by shifting

it transparently through the boundary scan register.

Note

Since there is no internal synchronization between the IEEE

1149.1 clock (TCK) and the system clocks (BYTCLK, SYMCLK),

the user must provide some form of external synchronization to

achieve meaningful results.

The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output

cells prior to selection of EXTEST. This initialization ensures that known data will appear on

the outputs when entering the EXTEST instruction.

8.4.3 BYPASS

The BYPASS instruction selects the single-bit bypass register as shown in Figure 8-9. This

creates a shift register path from TDI to the bypass register and, finally, to TDO, circumvent-

ing the 163-bit boundary scan register. This instruction is used to enhance test efficiency

when a component other than the Quad ELM becomes the device under test.

G1

SHIFT DR

0

1

1 D

C1

MUX

FROM TDI

TO TDO

CLOCK DR

Figure 8-9. By-Pass Register

When the bypass register is selected by the current instruction, the shift register stage is set

to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the

first bit to be shifted out after selecting the bypass register will always be a logic zero.

8-11

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MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

8.4.4 CLAMP

The CLAMP instruction selects the single-bit bypass register as shown in Figure 8-9, and

the state of all signals driven from system output pins is completely defined by the data pre-

viously shifted into the boundary scan register (for example, using the SAMPLE/PRELOAD

instruction).

8.4.5 HI-Z

The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manu-

facturer’s optional public instruction to prevent having to backdrive the output pins during cir-

cuit-board testing. When HI-Z is invoked, all output drivers, including the two-state drivers,

are turned off (i.e., high impedance). The instruction selects the bypass register.

8.5 QUAD ELM RESTRICTIONS

The control afforded by the output enable signals using the boundary scan register and the

EXTEST instruction requires a compatible circuit-board test environment to avoid device-

destructive configurations. The user must avoid situations in which the Quad ELM output

drivers are enabled into actively driven networks.

8.6 BIST OPERATION

BIST tests the ELM by circulating pseudo-random data throughout the core. The various

subcircuits within the core are observed as they respond to the data, and a signature based

upon their behavior is generated. This signature may be checked against a correct signature

to verify functioning of the core. A fault in the ELM (within the coverage of BIST) causes a

different signature to be generated.

BIST is activated by setting the RUN_BIST bit in ELM control register A (ELM_CNTRL_A).

Upon activation, the data path linear feedback shift register and signature generator are en-

abled, and the test proceeds. The procedure for running the BIST is as follows:

• Perform a power-up reset.

• Set the EB_LOC_LOOP bit in ELM_CNTRL_A

• Read the violation symbol counter register.

• Read the link error symbol counter register.

• Set the RUN_ BIST bit in ELM_CNTRL_A.

• Get an interrupt (if enabled) when BIST has finished running.

• Read the BIST signature register; if the test was successful, it will have a value of 5B6B.

• Perform a power-up reset.

• Set ELM registers to desired value for operational mode.

When BIST has completed, the signature is frozen and may be read from the Quad ELM.

The test concludes when a value of zero is reached in the linear feedback shift register. Us-

ing a 16-bit linear feedback shift register clocked by the 80-ns BYTCLK takes approximately

5 ms to circulate about 62820 test patterns through the core. An interrupt to the node pro-

cessor/system interface after RUN_BIST has been set signifies the completion of the ELM

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MC68847 USER’S MANUAL

MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

BIST. This interrupt is cleared by clearing the RUN_BIST bit in ELM_CNTRL_A (not by read-

ing the interrupt event register). BIST is aborted if the RUN_BIST bit is cleared before the

test completes.

8-13

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MOTOROLA

IEEE 1149.1 Test Access Port and BIST Operation

8-14

MC68847 USER’S MANUAL

MOTOROLA

SECTION 9

ELECTRICAL CHARACTERISTICS

9.1 ABSOLUTE MAXIMUM RATINGS

The device contains circuitry to

protect the inputs against

damage due to high static

voltages or electric ﬁelds;

however, normal precautions

should be taken to avoid

application of voltages higher

than maximum-rated voltages to

these high-impedance circuits.

Tying unused inputs to the

appropriate logic voltage level

Characteristic

DC Supply Voltage

Symbol

Value

Unit

V

– 0.5 to + 7.0

CC

V_in

– 1.5 to V

+ 1.5

DC Input Voltage

V

CC

V

– 0.5 to V

+ 0.5

DC Output Voltage

DC Current Drain Per Pin

V

CC

out

I

25

75

mA

DC Current Drain V

CC

and GND Pins

T

Storage Temperature

– 65 to + 150

300

°C

stg

(e.g., either GND orV

)

CC

enhances reliability of operation.

T

L

Lead Temperature, Soldering (10 sec)

9.2 RECOMMENDED OPERATING CONDITIONS

Characteristic

Supply Voltage

Symbol

Value

Unit

V

4.75 to 5.25

CC

0.0 to V

CC

Input and Output Voltage

Ambient Temperature

Vin, Vout

V

T

0 to 70°C

A

9.3 AC ELECTRICAL CHARACTERISTICS

Characteristic

Symbol Min

Max

—

Unit

Vdc

CMOS, Minimum High-Level Input, V

out

= 0.1 V or V

– 0.1 V;

CC

V

3.15

3.85

2.0

—

IH

I

= 20 µA; V

= 4.5 V

out

CC

V

= 5.5 V

—

CC

TTL, Minimum High-Level Input, V

= 0.1 V or V

CC

– 0.1 V;

out

—

I

= 20 µA; V

= 4.5 V

CC

out

V

= 5.5 V

—

CC

CMOS, Maximum Low-Level Input, V

= 0.1 V or V

– 0.1 V;

out

CC

V

1.35

0.8

IL

I

= 20 µA; V

= 4.5 V

CC

out

V

= 5.5 V

—

CC

TTL, Maximum Low-Level Input, V

= 0.1 V or V – 0.1 V;

CC

out

—

I

= 20 µA; V

= 4.5 V

CC

out

V

= 5.5 V

V

I

—

Vdc

mA

CC

Minimum Low-Level Output Current, V

OL

= 0.4 V, V = 4.5 V

CC

5.8

OL

OZ

Maximum Output Leakage, Three-State, Output = High-Z,

or GND, V = 5.5 V

I

—

±4.4

µA

V

out = CC

CC

Maximum Input Capacitance, V

CC

Maximum Output Capacitance, Output High-Z, V

CC

Maximum I/O Capacitance, Configured as Input, V

= 5.0 V

C

in

10.0

12.5

15.0

—

pF

= 5.0 V

C

out

I/O

C

CC

NOTE: All AC timings assume a capacitive loading of ≤ 50 pF.

MOTOROLA

MC68847 USER’S MANUAL

9-1

Thi d

t

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Electrical Characteristics

9.4 SYNCHRONOUS NODE PROCESSOR INTERFACE TIMING

(see Figure 9-1)

Num

1

Characteristic

QPHYSEL Setup Time

Min

10

5

Max

—

30

–

Unit

ns

2

QPHYSEL Hold Time

3

NPRW Setup Time

4

NPRW Hold Time

20

5

NPA Setup Time (see Note 5)

NPA Hold Time

12

20

—

2

6

7

Time to NPD High Impedance

NPA Valid to QPHYSEL Asserted

Time to NPD Driven (Read) (see Note 2)

Time to NPD Valid (Read) (see Note 3)

Time to NPD Invalid (Read)

NPD Setup Time (Write) (see Notes1 and 4)

NPD Hold Time (Write)

8

9

2

—

30

—

40

10

11

12

13

14

15

—

2

30

20

—

Time to QINT Asserted (see Note 1)

Time to QINT Negated (see Note 1)

NOTES:

1. Relative to the rising edge of BYTCLK.

2. Relative to the falling edge of BYTCLK.

3. Data is valid on the second rising edge of NPCLK following assertion of QPHYSEL, regardless of how long

QPHYSEL is held asserted.

4. Data is sampled by the ELM on the ﬁrst rising edge of NPCLK following assertion of QPHYSEL, regardless of

how long QPHYSEL is held asserted.

5. NPA must be valid 2 ns before QPHYSEL is asserted.

9-2

MC68847 USER’S MANUAL

MOTOROLA

Electrical Characteristics

80 ns

BYTCLK

(NPCLK)

2

1

QPHYSEL

NPA

8

5

6

VALID

ADDRESS

4

3

READ = 1

WRITE = 0

NPRW

9

7

10

7

11

NPD

(READ)

VALID DATA

13

7

12

NPD

(WRITE)

VALID DATA

14

15

QINT

Figure 9-1. Node Processor Interface Timing Diagram

MOTOROLA

MC68847 USER’S MANUAL

9-3

Electrical Characteristics

9.5 ASYNCHRONOUS NODE PROCESSOR INTERFACE TIMING

(see Figure 9-2, Figure 9-3)

Num

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

Characteristic

Min

—

Max

40

—

Unit

ns

QPHYSEL Asserted to NPRW Valid

NPA Valid to QPHYSEL Asserted

2

QPHYSEL Asserted to NPD Driven (Read)

QPHYSEL Asserted to NPD Valid (Read)

QPHYSEL Deasserted to NPD Invalid (Read)

QPHYSEL Deasserted to NPD High-Impedance (Read)

QPHYSEL Asserted Time (Read)

160

—

360

—

1

—

13

—

320

280

20

5

QPHYSEL Asserted to NPRW; NPA Invalid (Read)

QPHYSEL Asserted to NPA Invalid (Write)

QPHYSEL Asserted to NPA Valid (Write1)

NPD Setup Before NPRW High (Write1)

NPD Hold After NPRW High (Write1)

—

QPHYSEL Asserted Time (Write)

280

0

—

QPHYSEL Hold After NPRW Deasserted, (Write2)

Data Setup Before QPHYSEL Deasserted (Write2)

Data Hold After QPHYSEL Deasserted, (Write2)

NPRW Hold After QPHYSEL Deasserted, (Write2)

—

20

5

—

0

—

27

QPHYSEL

28

NPRW

NPA

21

22

26

24

NPD

25

23

Figure 9-2. Node Processor Interface Asynchronous Read Timing Diagram

9-4

MC68847 USER’S MANUAL

MOTOROLA

Electrical Characteristics

Figure 9-3. Node Processor Interface Asynchronous Write Timing Diagram

MOTOROLA

MC68847 USER’S MANUAL

9-5

Electrical Characteristics

9.6 DATA I/O PORT TIMING

(see Figure 9-4)

Num

Characteristic

Min

Max

Unit

40

Skew, SYMCLK to BYTCLK

0

10

ns

WRSCLK, XRSCLK, YRSCLK, ZRSCLK

Time Low

41

42

43

44

45

46

47

15

2

25

—

30

—

ns

WRSCLK, XRSCLK, YRSCLK, ZRSCLK

Time High

Time to PRCDATx, RRCDATx, SRCDATx;

PRCPAR, RRCPAR, SRCPAR Invalid

Time to PRCDATx, RRCDATx, SRCDATx;

PRCPAR, RRCPAR, SRCPAR Valid

—

5

WRDATA, XRDATA, YRDATA, ZRDATA

Setup Time (see Note 1)

WRDATA, XRDATA, YRDATA, ZRDATA

Hold Time (see Note 1)

8

PTXDAT, RTXDAT, STXDAT; PTXPAR,

RTXPAR, STXPAR Setup Time (see Note 2)

5

PTXDAT, RTXDAT, STXDAT; PTXPAR,

RTXPAR, STXPAR Hold Time (see Note 2)

48

49

7

—

2

—

25

—

ns

Time to WTDATA, XTDATA, YTDATA,

ZTDATA Valid

Time to WTDATA, XTDATA, YTDATA,

ZTDATA Invalid

50

NOTE:

1. Times are relative to the rising edge of RSCLK.

2. Times are relative to the falling edge of SYMCLK when BYTCLK is low. All other times are relative to the rising

edge of BYTCLK or SYMCLK as shown.

9-6

MC68847 USER’S MANUAL

MOTOROLA

Electrical Characteristics

40 ns

42

WRSCLK, XRSCLK,

YRSCLK, ZRSCLK

41

40 ns

SYMCLK

40

80 ns

BYTCLK

(NPCLK)

44

43

PRCDATx, PRCPAR,

RRCDATx, RRCPAR,

SRCDATx, SRCPAR

45

46

WRDATA, XRDATA,

YRDATA, ZRDATA

S

47

48

PTXDAT, RTXDAT, STXDAT,

PTXPAR, RTXPAR, STXPAR

S

50

49

WTDATA, XTDATA,

YTDATA, ZTDATA

S

Figure 9-4. Data I/O Port Timing Diagram

MOTOROLA

MC68847 USER’S MANUAL

9-7

Electrical Characteristics

9.7 MISCELLANEOUS SIGNALS TIMING

(see Figure 9-5)

Num

52

Characteristic

WSD, XSD, YSD, ZSD Setup Time

Min

5

Max

—

Unit

ns

53

WSD, XSD, YSD, ZSD Hold Time

20

—

ns

WLOOPBACK, XLOOPBACK, YLOOPBACK, ZLOOPBACK;

WFOTOFF, XFOTOFF, YFOTOFF, ZFOTOFF Invalid

54

2

—

ns

55

56

WLOOPBACK, XLOOPBACK, YLOOPBACK, ZLOOPBACK Valid

WFOTOFF, XFOTOFF, YFOTOFF, ZFOTOFF Valid

—

25

35

ns

NOTE:

Times are relative to the rising edge of RSCLK

.

BYTCLK

52

53

WSD, XSD,

YSD, ZSD

S

54

WLOOPBACK, XLOOPBACK,

YLOOPBACK, ZLOOPBACK

S

55

WFOTOFF, XFOTOFF,

YFOTOFF, ZFOTOFF

S

56

Figure 9-5. Miscellaneous Signals Timing Diagram

9-8

MC68847 USER’S MANUAL

MOTOROLA

SECTION 10

ORDERING INFORMATION

This section contains the ordering information, pin assignments, and package dimensions

for the MC68847.

10.1 STANDARD ORDERING INFORMATION

Package Type

Frequency (MHz)

Temperature

Order Number

208-Lead Quad Flat Pack (FC Suffix)

8–16.7

0°C to 70°C

MC68847FC16

MOTOROLA

MC68847 USER’S MANUAL

10-1

Thi d

t

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M k

4 0 4

Ordering Information

10.2 PIN ASSIGNMENTS

208-Lead Quad Flat Pack (QFP)

156

157

105

104

RRCDAT9

RRCDAT8

GND

TMS

TDO

TDI

VCC

GND

RRCDAT7

RRCDAT6

RRCDAT5

GND

RTXDAT9

RTXDAT8

RTXDAT7

RTXDAT6

RTXDAT5

GND

VCC

RRCDAT4

RRCDAT3

RRCDAT2

RRCDAT1

RRCDAT0

RRCPAR

STXDAT9

STXDAT8

STXDAT7

STXDAT6

STXDAT5

STXDAT4

STXDAT3

STXDAT2

STXDAT1

GND

RTXDAT4

RTXDAT3

RTXDAT2

RTXDAT1

RTXDAT0

RTXPAR

SRCDAT9

SRCDAT8

SRCDAT7

SRCDAT6

SRCDAT5

SRCDAT4

SRCDAT3

GND

VCC

GND

VCC

MC68847

(TOP VIEW)

VCC

STXDAT0

STXPAR

PRCDAT9

PRCDAT8

PRCDAT7

PRCDAT6

GND

SRCDAT2

SRCDAT1

SRCDAT0

SRCPAR

PTXDAT9

PTXDAT8

PTXDAT7

PTXDAT6

PTXDAT5

PTXDAT4

PTXDAT3

PTXDAT2

PTXDAT1

PTXDAT0

VCC

GND

PRCDAT5

PRCDAT4

PRCDAT3

PRCDAT2

PRCDAT1

PRCDAT0

GND

VCC

PRCPAR

ZSD

PTXPAR

WTDATA0

WTDATA1

WTDATA2

WTDATA3

WTDATA4

ZRDATA0

ZRDATA1

ZRDATA2

ZRDATA3

ZRDATA4

ZRSCLK

WLOOPBCK

WFOTOFF

208

1

53

52

10-2

MC68847 USER’S MANUAL

MOTOROLA

Ordering Information

10.3 PACKAGE DIMENSIONS

208 Pin QFP (FC Suffix)

E

0.20 (0.008) M

0.05 (0.002)

S

D

C

A – B

F

G

D

K

H

A

B

DETAIL "A"

P

L

DETAIL "B"

R

D

0.20 (0.008) M

H

A – B

S

D

S

0.50 (0.002) A – B

D

A – B

0.20 (0.008) M

C

0.13/0.23

0.13/0.17

(.005/.009)

(.005/.007)

M

P

BASE METAL

Q

0 MIN.

0.13

(.005)

S

M

S

D

C A – B

R MIN.

C

B

A, B, D

DATUM

PLANE

H

0.30 R. TYP.

1.61 REF.

(.063)

12-16

DETAIL "A"

G

A

DETAIL "C"

DATUM

H

REF.

PLANE

C

∩

.076 (0.003)

DETAIL "B"

SEATING

12-16

PLANE

MILLIMETERS

DIM MIN MAX

INCHES

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER. INCHES ARE IN "( )".

3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS

COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE

PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H- .

5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.254mm(0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE

MIN

—

.010

.125

MAX

.154

—

A

B

C

D

E

F

G

H

—

0.25

3.17

30.95

27.90

25.50 REF.

1.25 REF.

4.07

—

3.67

31.45

28.10

.144

1.218

1.098

1.238

1.106

.998 REF.

.052 REF.

.

30.95

27.90

31.45

28.10

1.218

1.098

1.238

1.106

J

K

L

M

N

P

25.50 REF.

1.25 REF

1.004 REF.

.049 REF.

MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE

-H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE

LOCATED ON THE LOWER RADIUS OR THE FOOT.

0.65

—

0.95

—

.026

—

.037

—

0.50 BSC.

.0197 BSC.

Q

R

S

0.13

0.25

0.20

.005

.010

.009

8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM DIMENSIONS

BY 0.20(.008) MILLIMETERS.

0.12

.005

MOTOROLA

MC68847 USER’S MANUAL

10-3

Ordering Information

10-4

MC68847 USER’S MANUAL

MOTOROLA

INDEX

A

ELM_STATUS_B 3-7, 3-8, 3-9, 3-10, 3-17

ENA_PAR_CHK 2-6, 3-11, 3-12

Encoder 2-5

A_MAX 3-7, 3-8, 3-9, 3-10, 3-23

ENCOFF 2-6

B

F

BIST 2-3, 2-4, 3-11, 3-13, 4-3, 4-4, 8-12

BIST_DONE 3-19

BIST_SIGNATURE 3-27

Bit Signaling 3-24, 6-4

Boundary Scan Register 8-1, 8-3

BREAK_REASON 3-18, 6-4

Bypass MUX 2-3, 3-14

FCG 2-4, 3-12, 4-1, 4-2, 4-3

FCG_LOOP_ CNTRL 3-11, 3-12

FOT_OFF 3-11, 3-12

Fragment 2-7

Framer 2-2

BYTCLK 4-1, 8-12

G

C

GOBBLE 2-7

GOBBLE_BYTE 2-6, 2-7

C_MIN 3-23

CF_JOIN 3-20

I

CIPHER 2-1

CLAMP 8-12

INSERT_SCRUB 6-7

INT_MASK 3-2

CLASS_S 3-14, 3-15

CLK_DIV 3-7, 3-8, 3-9, 3-10

Clock Divider 3-22

CMT 2-8, 6-1, 6-2, 6-3

CONFIG_CNTRL 2-3, 2-4, 3-12, 3-14

J

JTAG 2-1, 8-1

L

D

LC_SHORT 3-7, 3-8, 3-9, 3-10, 3-23, 3-24,

6-5

LE_CTR 3-19, 3-25, 3-26, 6-1

LE_THRESHOLD 3-7, 3-8, 3-9, 3-10, 3-26

Line State Machine 2-8, 6-1

Line State Symbols 2-8

Data Path Configuration 3-11

Data Stream Generator 2-8, 6-2

Decoder 2-4

E

LINE_ST 3-14, 3-16, 3-17

Link Confidence Test 3-15, 3-21, 3-25, 6-5,

6-6

Link Error Monitor 3-26, 6-1

LINK_ERR_CTR 3-7, 3-8, 3-9, 3-10, 3-25

LM Local Loopback MUX 3-13

LM_LOC_LOOP 2-3, 2-4

LONG 3-14, 3-15

EB_LOC_LOOP 2-3, 2-4, 3-11, 3-12

EBUF_ERR 3-19

Elasticity Buffer 2-2, 3-20, 4-1

ELM_BIST 3-7, 3-8, 3-9, 3-10, 8-12

ELM_CNTRL_A 3-7, 3-8, 3-9, 3-10, 3-11

ELM_CNTRL_B 3-7, 3-8, 3-9, 3-10, 3-14

ELM_INTR 3-7, 3-8, 3-9, 3-10, 4-4

ELM_LOC_LOOP 3-11, 3-13

ELM_MASK 3-7, 3-8, 3-9, 3-10

ELM_REV_NO 3-16

ELM_STATUS_A 3-7, 3-8, 3-9, 3-10, 4-4

Long Link Confidence Test 3-15

LOOPBACK 3-12

LS_MATCH 3-19

MOTOROLA

MC68847 USER’S MANUAL

Index-1

Thi d

t

t d

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M k

4 0 4

LS_MAX 3-7, 3-8, 3-9, 3-10, 3-23

LS_REQUEST 6-2

LSD 3-19

PHYINV 3-19

Pin Assignments 10-2

PRCDATx 3-12, 3-18

PREV_LINE_ST 3-16

LSF 3-18

LSM_STATE 3-16

Q

M

QINT 4-3

MAINT_LS 2-8, 3-12, 3-14, 4-4

MATCH_LS 3-14, 3-21

R

MIN_IDLE_CTR 3-7, 3-8, 3-9, 3-10, 3-26

MINI_CTR 3-19, 3-26, 3-27

MINI_CTR_INTRS 3-11, 3-12, 3-20, 3-27

RCF 3-18

RCV_VECTOR 3-7, 3-8, 3-9, 3-10, 3-25

REM_LOOP 3-11, 3-13, 3-14

Remote Loopback MUX 3-14

Repeat Filter 3-13, 3-18

N

NOISE_TIMER 3-11, 3-22, 6-6

REQ_SCRUB 3-11, 3-15

NP_ERR 3-5, 3-7, 3-8, 3-9, 3-10, 3-19, 3-22, RF_CNTRL 6-2

3-24, 5-1

RF_DISABLE 3-11, 3-13

NS_MAX 3-7, 3-8, 3-9, 3-10, 3-19, 3-23

RF_STATE 3-18

RUN_BIST 3-11, 3-13, 3-19, 8-12

P

S

Package Dimensions 10-3

Parity 4-2

SC_BYPASS 3-11, 3-14, 3-15

Parity Error 3-21

SC_BYPASS—Scrub/Bypass. 3-13

PARITY_ERR 3-19

Scrubbing 3-16, 3-20, 3-22, 3-24

SD 3-17, 3-20

PC_JOIN 3-14, 3-15, 6-6

PC_LOOP 3-14, 3-15, 6-5

PC_MAINT 3-14

PC_SIGNAL 3-15

PC_START 6-4

SELF_TEST 3-19

SIGNAL_DETECT 3-16

State Options Specification 3-11

SYM_PR_CTR 3-16

PC_Start 3-19

T

PCI 2-3, 2-4, 2-8, 3-18, 6-2, 6-6, 6-7

PCI_SCRUB 3-18, 3-20, 3-21

PCI_STATE 3-18

PCM 2-3, 2-4, 2-8, 3-11, 3-12, 3-15, 3-16,

3-18, 3-20, 3-21, 3-22, 3-24, 3-25,

6-4, 6-5

PCM State Machine 6-3

PCM Timers 3-21

PCM_BREAK 3-19

T_OUT 3-7, 3-8, 3-9, 3-10, 3-19, 3-23

T_SCRUB 3-7, 3-8, 3-9, 3-10, 3-23, 3-24

TAP 8-1

TB_MIN 3-7, 3-8, 3-9, 3-10, 3-23

TB_OUT 3-23

TCF 3-18

TDATAx 3-12

TDO 8-2

PCM_CNTRL 3-14

Timer Configuration 3-11

TL_MIN 3-23

PCM_CODE 3-15, 3-19, 6-5

PCM_ENABLED 3-19

PCM_SIGNALING 3-15, 3-18, 3-24, 3-25,

6-6

TMS 8-2

TNE 3-7, 3-8, 3-9, 3-10

TNE Timer 3-19, 3-20, 3-21, 3-23

TNE_16BIT 3-11, 3-22

PCM_STATE 3-18

Index--2

MC68847 USER’S MANUAL

MOTOROLA

TNE_EXPIRED 3-19

TNE_LOAD_VALUE 3-7, 3-8, 3-9, 3-10

TPC 3-7, 3-8, 3-9, 3-10

TPC Timer 3-11, 3-19, 3-20, 3-21

TPC_16BIT 3-11, 3-22

TPC_EXPIRED 3-19

TPC_LOAD_VALUE 3-7, 3-8, 3-9, 3-10

TRACE_PROP 3-19

Transmit Vector Register 3-18

TRST 8-2

TXDATx 3-14, 3-15, 3-21

U

UNKN_LINE_ST 3-16

V

VECTOR_LENGTH 3-7, 3-8, 3-9, 3-10,

3-24

VIOL_SYM_CTR 3-7, 3-8, 3-9, 3-10, 3-25

VSYM_CTR 3-12, 3-19, 3-25

VSYM_CTR_INTRS 3-11, 3-20, 3-25

W

WFOTOFF 3-12

WLOOPBACK 3-12

X

XFOTOFF 3-12

XLOOPBACK 3-12

XMIT_VECTOR 3-7, 3-8, 3-9, 3-10, 3-24

Y

YFOTOFF 3-12

YLOOPBACK 3-12

Z

ZFOTOFF 3-12

ZLOOPBACK 3-12

MOTOROLA

MC68847 USER’S MANUAL

Index-3

Index--4

MC68847 USER’S MANUAL

MOTOROLA


型号：	MC68847FC16
厂家：	MOTOROLA
描述：	Telecom IC
文件：	总102页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC68847FC16 [MOTOROLA]

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