MC68HC08AZ32A_技术文档

Freescale Semiconductor, Inc.

MC68HC08AZ32A

Technical Data — Rev 1.0

Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets and/or

specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including "Typicals" must be validated for

each customer application by customer’s technical experts. Motorola does not convey

any license under its patent rights nor the rights of others. Motorola products are not

designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life,

or for any other application in which the failure of the Motorola product could create a

situation where personal injury or death may occur. Should Buyer purchase or use

Motorola products for any such unintended or unauthorized application, Buyer shall

indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim

alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and

are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data

4

MC68HC08AZ32A — Rev 1.0

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

List of Paragraphs

List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Section 1. General Description . . . . . . . . . . . . . . . . . . . .27

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .41

Section 3. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Section 4. ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Section 5. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .77

Section 7. System Integration Module (SIM) . . . . . . . . .95

Section 8. Clock Generator Module (CGM). . . . . . . . . .117

Section 9. Mask Options. . . . . . . . . . . . . . . . . . . . . . . . .145

Section 10. Break Module. . . . . . . . . . . . . . . . . . . . . . . .149

Section 11. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .155

Section 12. Computer Operating Properly (COP) . . . .167

Section 13. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .173

Section 14. External Interrupt Module (IRQ). . . . . . . . .179

Section 15. Serial Communications Interface (SCI). . .187

Section 16. Serial Peripheral Interface (SPI). . . . . . . . .227

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

5

List of Paragraphs

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Paragraphs

Section 17. Timer Interface Module B (TIMB). . . . . . . .259

Section 18. Programmable Interrupt Timer (PIT) . . . . .283

Section 19. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

Section 20. MSCAN08 Controller (MSCAN08) . . . . . . .321

Section 21. Keyboard Module (KBD). . . . . . . . . . . . . . .373

Section 22. Timer Interface Module A (TIMA). . . . . . . .381

Section 23. Analog-to-Digital Converter (ADC-15). . . .411

Section 24. Electrical Specifications. . . . . . . . . . . . . . .423

Section 25. MC68HC08AZ32A Changes . . . . . . . . . . . .437

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445

Technical Data

6

MC68HC08AZ32A — Rev 1.0

List of Paragraphs

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Table of Contents

List of Paragraphs

Table of Contents

List of Figures

List of Tables

Section 1. General Description

1.1

1.2

1.3

1.4

1.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Section 2. Memory Map

2.1

2.2

2.3

2.4

2.5

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Additional Status and Control Registers. . . . . . . . . . . . . . . . . .49

Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . .50

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Table of Contents

7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 3. RAM

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.2

3.3

Section 4. ROM

4.1

4.2

4.3

4.4

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Section 5. EEPROM

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .59

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

EEPROM Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . .67

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Section 6. Central Processor Unit (CPU)

6.1

6.2

6.3

6.4

6.5

6.6

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Technical Data

8

MC68HC08AZ32A — Rev 1.0

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

6.7

6.8

6.9

CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .84

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Section 7. System Integration Module (SIM)

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .98

Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .99

SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Section 8. Clock Generator Module (CGM)

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .138

8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .138

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

9

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 9. Mask Options

9.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.2

9.3

Section 10. Break Module

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Section 11. Monitor ROM (MON)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.4 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Section 12. Computer Operating Properly (COP)

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

12.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

12.5 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .171

12.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Technical Data

10

MC68HC08AZ32A — Rev 1.0

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . . . .172

Section 13. Low Voltage Inhibit (LVI)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

13.5 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .176

13.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Section 14. External Interrupt Module (IRQ)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .184

14.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .184

Section 15. Serial Communications Interface (SCI)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

15.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

11

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

15.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .208

15.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

15.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Section 16. Serial Peripheral Interface (SPI)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

16.4 Pin Name Conventions and I/O Register Addresses . . . . . . .229

16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

16.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

16.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

16.8 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .244

16.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

16.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

16.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .247

16.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

16.13 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Section 17. Timer Interface Module B (TIMB)

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

17.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

17.7 TIMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .271

Technical Data

12

MC68HC08AZ32A — Rev 1.0

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

17.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271

17.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272

Section 18. Programmable Interrupt Timer (PIT)

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

18.5 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

18.7 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .286

18.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Section 19. I/O Ports

19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

19.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

19.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

19.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

19.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

19.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312

19.9 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315

19.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

13

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 20. MSCAN08 Controller (MSCAN08)

20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322

20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323

20.4 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

20.5 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325

20.6 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .330

20.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335

20.8 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . .337

20.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338

20.10 Timer Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

20.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342

20.12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

20.13 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .346

20.14 Programmer’s Model of Control Registers . . . . . . . . . . . . . . .352

Section 21. Keyboard Module (KBD)

21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373

21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374

21.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377

21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378

21.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .378

21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379

Technical Data

14

MC68HC08AZ32A — Rev 1.0

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

Section 22. Timer Interface Module A (TIMA)

22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381

22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

22.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395

22.7 TIMA During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .396

22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396

22.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

Section 23. Analog-to-Digital Converter (ADC-15)

23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411

23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412

23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412

23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415

23.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416

23.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417

Section 24. Electrical Specifications

24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423

24.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424

24.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .425

24.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425

24.5 5.0 Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .426

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

15

Table of Contents

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Table of Contents

24.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427

24.7 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428

24.8 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing . . . .429

24.9 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .432

24.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . .433

24.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . .434

24.12 RAM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . .435

24.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . . .435

24.14 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .436

Section 25. MC68HC08AZ32A Changes

25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437

25.2 Significant Changes from the MC68HC08AZ32 (Non-A Suffix De-

vice) 437

Revision History

Major Changes Between Revision 1.0 and Revision 0.0 . . . .443

Glossary

Technical Data

16

MC68HC08AZ32A — Rev 1.0

Table of Contents

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

List of Figures

Figure

Title

Page

1-1

1-2

1-3

2-1

2-2

2-3

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

6-1

6-2

6-3

6-4

6-5

6-6

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

MC68HC08AZ32A MCU Block Diagram . . . . . . . . . . . . . . . . .30

64 QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

MC68HC08AZ32A Memory map . . . . . . . . . . . . . . . . . . . . . . .42

I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . .45

Additional Status and Control Registers. . . . . . . . . . . . . . . . . .49

EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .59

EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . . . .67

EEPROM Array Configuration Register (EEACR) . . . . . . . . . .69

EEPROM Nonvolatile Register (EENVR) . . . . . . . . . . . . . . . . .71

EEDIV Divider High Register (EEDIVH) . . . . . . . . . . . . . . . . . .72

EEDIV Divider Low Register (EEDIVL). . . . . . . . . . . . . . . . . . .72

EEPROM Divider Non-Volatile Register High (EEDIVHNVR)).74

EEPROM Divider Non-Volatile Register Low (EEDIVLNVR) . .74

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .81

SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .107

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

List of Figures

17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

7-10 WAIT Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

7-11 WAIT Recovery From Interrupt or Break . . . . . . . . . . . . . . . .110

7-12 WAIT Recovery From Internal Reset . . . . . . . . . . . . . . . . . . .110

7-13 STOP Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .111

7-14 STOP Mode Recovery From Interrupt . . . . . . . . . . . . . . . . . .112

7-15 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .112

7-16 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .114

7-17 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .115

8-1

8-2

8-3

8-4

8-5

8-6

9-1

9-2

CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .129

PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .131

PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .133

PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . .135

Mask Option Register A (MORA) . . . . . . . . . . . . . . . . . . . . . .146

Mask Option Register B (MORB) . . . . . . . . . . . . . . . . . . . . . .148

10-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .151

10-2 Break Status and Control Register (BRKSCR). . . . . . . . . . . .153

10-3 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .154

11-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

11-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

11-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .159

11-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

11-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

11-6 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .165

12-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

12-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .171

13-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .175

13-2 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .176

14-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .180

14-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

14-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .184

15-1 SCI Module Block Diagram

. . . . . . . . . . . . . . . . . . . . . . . .190

15-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .191

15-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

15-4 SCI Transmitter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

15-5 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . .195

15-6 SCI Receiver Block Diagram

. . . . . . . . . . . . . . . . . . . . . .198

Technical Data

18

MC68HC08AZ32A — Rev 1.0

MOTOROLA

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

15-7 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .199

15-8 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

15-9 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

15-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

15-11 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .210

15-12 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .213

15-13 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .215

15-14 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .217

15-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

15-16 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .221

15-17 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .222

15-18 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .223

16-1 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .230

16-2 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .231

16-3 Full-duplex Master-Slave Connections. . . . . . . . . . . . . . . . . .233

16-4 Transmission Format (CPHA = ‘0’). . . . . . . . . . . . . . . . . . . . .236

16-5 Transmission Format (CPHA = ‘1’). . . . . . . . . . . . . . . . . . . . .237

16-6 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . .238

16-7 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .240

16-8 Clearing SPRF When OVRF Interrupt is Not Enabled . . . . . .241

16-9 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .244

16-10 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .245

16-11 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

16-12 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .252

16-13 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .255

16-14 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .258

17-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

17-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .261

17-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .266

17-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .273

17-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . .275

17-6 TIMB Counter Modulo Registers (TBMODH and TBMODL) .276

17-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

17-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

17-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . .282

18-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

18-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .285

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

19

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

18-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . .288

18-4 PIT Counter Registers (PCNTH–PCNTL). . . . . . . . . . . . . . . .290

18-5 PIT Counter Modulo Registers (PMODH–PMODL) . . . . . . . .291

19-1 Port A data register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . .295

19-2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . .296

19-3 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

19-4 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .298

19-5 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .299

19-6 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

19-7 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .301

19-8 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .302

19-9 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

19-10 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .304

19-11 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .305

19-12 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

19-13 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .307

19-14 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .310

19-15 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310

19-16 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .312

19-17 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .313

19-18 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

19-19 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . .315

19-20 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . .316

19-21 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316

19-22 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .318

19-23 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . .319

19-24 Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

20-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324

20-2 User Model for Message Buffer Organization. . . . . . . . . . . . .328

20-3 Single 32-Bit Maskable Identifier Acceptance Filter . . . . . . . .331

20-4 Dual 16-Bit Maskable Acceptance Filters. . . . . . . . . . . . . . . .332

20-5 Quadruple 8-Bit Maskable Acceptance Filters . . . . . . . . . . . .333

20-6 Sleep Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . .340

20-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343

20-8 Segments Within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . .345

20-9 MSCAN08 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .346

20-10 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .347

20-11 Receive/Transmit Message Buffer Extended Identifier (IDRn)

Technical Data

20

MC68HC08AZ32A — Rev 1.0

List of Figures

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348

20-12 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .350

20-13 Transmit Buffer Priority Register (TBPR) . . . . . . . . . . . . . . . .352

20-14 MSCAN08 Control Register Structure . . . . . . . . . . . . . . . . . .353

20-15 Module Control Register 0 (CMCR0) . . . . . . . . . . . . . . . . . . .355

20-16 Module Control Register (CMCR1). . . . . . . . . . . . . . . . . . . . .357

20-17 Bus Timing Register 0 (CBTR0) . . . . . . . . . . . . . . . . . . . . . . .358

20-18 Bus Timing Register 1 (CBTR1) . . . . . . . . . . . . . . . . . . . . . . .359

20-19 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . .361

20-20 Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . . . .363

20-21 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . . . .365

20-22 Transmitter Control Register (CTCR) . . . . . . . . . . . . . . . . . . .366

20-23 Identifier Acceptance Control Register (CIDAC). . . . . . . . . . .367

20-24 Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . . . .369

20-25 Transmit Error Counter (CTXERR). . . . . . . . . . . . . . . . . . . . .369

20-26 Identifier Acceptance Registers (CIDAR0–CIDAR3) . . . . . . .370

20-27 Identifier Mask Registers (CIDMR0–CIDMR3) . . . . . . . . . . . .371

21-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . .375

21-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375

21-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .379

21-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .380

22-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383

22-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .384

22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .390

22-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .398

22-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . .400

22-6 TIMA Counter Modulo Registers (TAMODH and TAMODL) .401

22-7 TIMA Channel Status and Control Registers (TASC0–TASC5)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403

22-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407

22-9 TIMA Channel Registers (TACH0H/L–TACH5H/L) . . . . . . . .408

23-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413

23-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .417

23-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .420

23-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .420

24-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .430

24-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .431

24-3 64-pin QFP (Case #840B) . . . . . . . . . . . . . . . . . . . . . . . . . . .436

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

21

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Figures

Technical Data

22

MC68HC08AZ32A — Rev 1.0

MOTOROLA

List of Figures

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

List of Tables

Table

Title

Page

1-1

1-2

1-3

1-4

2-1

5-1

5-2

5-3

5-4

6-1

6-2

7-1

7-2

7-3

7-4

8-1

8-2

8-3

External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . .62

Example Selective Bit Programming Description . . . . . . . . . . .63

EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . .68

EEPROM Block Protect and Security Summary. . . . . . . . . . . .70

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .98

PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .121

Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . .136

10-1 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .151

11-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

11-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

11-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .161

11-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .161

11-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .162

11-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .162

11-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .163

11-8 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .163

12-1 COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .168

13-1 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .175

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

23

List of Tables

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Tables

13-2 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

14-1 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .181

15-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15-2 SCI I/O Register Address Summary. . . . . . . . . . . . . . . . . . . .191

15-3 SCI Transmitter I/O Address Summary . . . . . . . . . . . . . . . . .195

15-4 SCI Receiver I/O Address Summary . . . . . . . . . . . . . . . . . . .199

15-5 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

15-6 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-7 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

15-8 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .212

15-9 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .223

15-10 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

15-11 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .225

16-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-2 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

16-3 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

16-4 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

16-5 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .257

17-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

17-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .280

18-1 PIT I/O Register Address Summary . . . . . . . . . . . . . . . . . . . .285

18-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

19-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .294

19-2 Port A pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297

19-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

19-4 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303

19-5 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306

19-6 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

19-7 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

19-8 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

19-9 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320

20-1 MSCAN08 Interrupt Vector Addresses. . . . . . . . . . . . . . . . . .337

20-2 MSCAN08 vs CPU Operating Modes. . . . . . . . . . . . . . . . . . .338

20-3 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345

20-4 CAN Standard Compliant Bit Time Segment Settings . . . . . .345

20-5 Data Length Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

20-6 Synchronization Jump Width . . . . . . . . . . . . . . . . . . . . . . . . .358

20-7 Baud Rate Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359

Technical Data

24

MC68HC08AZ32A — Rev 1.0

List of Tables

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Tables

20-8 Time Segment Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360

20-9 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .368

20-10 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . .368

21-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .375

22-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399

22-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .406

23-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419

23-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

25

List of Tables

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

List of Tables

Technical Data

26

MC68HC08AZ32A — Rev 1.0

MOTOROLA

List of Tables

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 1. General Description

1.1 Contents

1.2

1.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

1.4

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power Supply Pins (V_DDand V_SS) . . . . . . . . . . . . . . . . . . .32

Oscillator Pins (OSC1 and OSC2). . . . . . . . . . . . . . . . . . .33

External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .33

External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . .33

Analog Power Supply Pin (V_DDA) . . . . . . . . . . . . . . . . . . .33

Analog Ground Pin (V_SSA). . . . . . . . . . . . . . . . . . . . . . . . .33

ADC Analog Ground Pin (A_vss/V_REFL) . . . . . . . . . . . . . . .33

ADC Reference High Voltage Pin (VREFH) . . . . . . . . . . .34

ADC Analog Power Supply Pin (V_DDAREF) . . . . . . . . . . . .34

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.4.9

1.4.10 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .34

1.4.11 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . .34

1.4.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . .34

1.4.13 Port C I/O Pins (PTC5–PTC0) . . . . . . . . . . . . . . . . . . . . . .34

1.4.14 Port D I/O Pins (PTD7–PTD0/ATD8) . . . . . . . . . . . . . . . . .35

1.4.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . .35

1.4.16 Port F I/O Pins (PTF6–PTF0/TACH2). . . . . . . . . . . . . . . . .35

1.4.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) . . . . . . . . . . .35

1.4.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3). . . . . . . . . . . .36

1.4.19 CAN Transmit Pin (TxCAN) . . . . . . . . . . . . . . . . . . . . . . . .36

1.4.20 CAN Receive Pin (RxCAN). . . . . . . . . . . . . . . . . . . . . . . . .36

1.5

1.5.1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

General Description

27

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.2 Introduction

The MC68HC08AZ32A is a member of the low-cost, high-performance

M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08

Family is based on the customer-specified integrated circuit (CSIC)

design strategy. All MCUs in the family use the enhanced M68HC08

central processor unit (CPU08) and are available with a variety of

modules, memory sizes and types, and package types.

1.3 Features

Features of the MC68HC08AZ32A include the following:

• High-Performance M68HC08 Architecture

• Fully Upward-Compatible Object Code with M6805, M146805,

and M68HC05 Families

• 8.4MHz Internal Bus Frequency at 125°C

• MSCAN08 Controller (Motorola Scalable CAN) (Implementing

CAN 2.0b Protocol as Defined in BOSCH Specification Sep. 1991)

• Available in 64 QFP Package

• 32,256 Bytes User ROM

• User ROM Data security

• 512 Bytes of On-Chip EEPROM with Security Feature

• 1K Byte of On-Chip RAM

• Serial Peripheral Interface (SPI) Module

• Serial Communications Interface (SCI) Module

• 16-bit Timer Interface Module (TIMA-6) with Six Input

Capture/Output Compare Channels

• 16-bit Timer Interface Module (TIMB) with Two Input

Capture/Output Compare Channels

• Programmable Interrupt Timer (PIT)

• Clock Generator Module (CGM)

Technical Data

28

MC68HC08AZ32A — Rev 1.0

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Features

• 8-Bit, 15-Channel Analog to Digital Convertor (ADC-15)

• 5-Bit Keyboard Interrupt Module

• System Protection Features

– Computer Operating Properly (COP) with Optional Reset

– Low-Voltage Detection with Optional Reset

– Illegal Opcode Detection with Optional Reset

– Illegal Address Detection with Optional Reset

• Low-Power Design (Fully Static with STOP and WAIT Modes)

• Master Reset Pin and Power-On Reset

Features of the CPU08 include the following:

• Enhanced HC05 Programming Model

• Extensive Loop ControlFunctions

• 16 Addressing Modes (8 more than the HC05)

• 16-Bit Index Register and Stack Pointer

• Memory-to-Memory Data Transfers

• Fast 8 × 8 Multiply Instruction

• Fast 16/8 Divide Instruction

• Binary-Coded Decimal (BCD) Instructions

• Optimization for Controller Applications

• ‘C’ Language Support

Figure 1-1 shows the structure of the MC68HC08AZ32A

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

29

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Assignments

1.4 Pin Assignments

Figure 1-2 shows the 64 QFP pin assignments.

PTC4

IRQ

PTH0/KBD3

PTD3/ATD11

PTD2/ATD10

1

48

2

3

4

5

6

7

47

46

45

44

43

42

41

40

39

38

37

36

35

34

RST

PTF0/TACH2

PTF1/TACH3

PTF2/TACH4

PTF3/TACH5

PTF4/TBCH0

RxCAN

A

V

/VREFL

VSS

DDAREF

PTD1/ATD9

PTD0/ATD8

PTB7/ATD7

MC68HC08AZ32A

8

PTB6/ATD6

PTB5/ATD5

PTB4/ATD4

PTB3/ATD3

PTB2/ATD2

PTB1/ATD1

PTB0/ATD0

PTA7

9

TxCAN

10

11

12

13

14

15

PTF5/TBCH1

PTF6

PTE0/TxD

PTE1/RxD

PTE2/TACH0

PTE3/TACH1

16

33

Figure 1-2. 64 QFP Pin Assignments

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

31

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.4.1 Power Supply Pins (V_DDand V_SS)

V

_DDand V_SSare the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current

demands on the power supply. To prevent noise problems, take special

care to provide power supply bypassing at the MCU as Figure 1-3

shows. Place the C1 bypass capacitor as close to the MCU as possible.

Use a high-frequency-response ceramic capacitor for C1. C2 is an

optional bulk current bypass capacitor for use in applications that require

the port pins to source high current levels.

MCU

V_DD

V_SS

C1

0.1 µF

+

C2

V_DD

NOTE: Component values shown

represent typical applications.

Figure 1-3. Power Supply Bypassing

V_SSis also the ground for the port output buffers and the ground return

for the serial clock in the Serial Peripheral Interface Module (SPI). See

Serial Peripheral Interface (SPI) on page 227.

NOTE: V_SSmust be grounded for proper MCU operation.

Technical Data

32

MC68HC08AZ32A — Rev 1.0

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Assignments

1.4.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator

circuit. See Clock Generator Module (CGM) on page 117.

1.4.3 External Reset Pin (RST)

A logic ‘0’ on the RST pin forces the MCU to a known start-up state. RST

is bidirectional, allowing a reset of the entire system. It is driven low when

any internal reset source is asserted. See System Integration Module

(SIM) on page 95.

1.4.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See External Interrupt

Module (IRQ) on page 179.

1.4.5 Analog Power Supply Pin (V_DDA

)

V_DDAis the power supply pin for the analog portion of the Clock

Generator Module (CGM). See Clock Generator Module (CGM) on

page 117.

1.4.6 Analog Ground Pin (V_SSA

)

V_SSAis the ground connection for the analog portion of the Clock

Generator Module (CGM). See Clock Generator Module (CGM) on

page 117.

1.4.7 ADC Ana log Ground Pin (A_vss/ V_REFL

)

The AV_SS/V_REFLpin provides both the analog ground connection and

the reference low voltage for the Analog-to-Digital Converter (ADC). See

Analog-to-Digital Converter (ADC-15) on page 411.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

33

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.4.8 ADC Re fe re nc e Hig h Volta g e Pin (V_REFH

)

V

_REFHprovides the reference high voltage for the Analog-to-Digital

Converter (ADC). See Analog-to-Digital Converter (ADC-15) on page

411.

1.4.9 ADC Analog Power Supply Pin (V_DDAREF

)

V

_DDAREFis the power supply pin for the analog portion of the Analog-to-

Digital Converter (ADC). See Analog-to-Digital Converter (ADC-15)

on page 411.

1.4.10 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the Clock

Generator Module (CGM). See Clock Generator Module (CGM) on

page 117.

1.4.11 Port A Input/Output (I/O) Pins (PTA7–PTA0)

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See I/O

Ports on page 293.

1.4.12 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)

Port B is an 8-bit special function port that shares all eight pins with the

Analog to Digital Convertor (ADC). See Analog-to-Digital Converter

(ADC-15) on page 411 and I/O Ports on page 293.

1.4.13 Port C I/O Pins (PTC5–PTC0)

PTC5–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O

port pins. PTC2/MCLK is a special function port that shares its pin with

the system clock. See I/O Ports on page 293.

Technical Data

34

MC68HC08AZ32A — Rev 1.0

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Assignments

1.4.14 Port D I/O Pins (PTD7–PTD0/ATD8)

Port D is an 8-bit special-function port that shares seven of its pins with

the Analog-to-Digital Converter Module (ADC-15), one of its pins with

the Timer Interface Module A (TIMA-6), and one more of its pins with the

Timer Interface Module B (TIMB). See Timer Interface Module A

(TIMA) on page 381 , Timer Interface Module B (TIMB) on page 259,

Analog-to-Digital Converter (ADC-15) on page 411 and I/O Ports on

page 293.

1.4.15 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)

Port E is an 8-bit special function port that shares two of its pins with the

Timer Interface Module A (TIMA), four of its pins with the Serial

Peripheral Interface Module (SPI), and two of its pins with the Serial

Communication Interface Module (SCI). See Serial Communications

Interface (SCI) on page 187, Serial Peripheral Interface (SPI) on page

227, Timer Interface Module A (TIMA) on page 381 and I/O Ports on

page 293.

1.4.16 Port F I/O Pins (PTF6–PTF0/TACH2)

Port F is a 7-bit special function port that shares its pins with the Timer

Interface Module B (TIMB). Six of its pins are shared with the Timer

Interface Module A (TIMA-6). See Timer Interface Module A (TIMA) on

page 381, Timer Interface Module B (TIMB) on page 259 and I/O Ports

on page 293.

1.4.17 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0)

Port G is a 3-bit special function port that shares all of its pins with the

Keyboard Module (KBD). See Keyboard Module (KBD) on page 373

and I/O Ports on page 293.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

35

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

1.4.18 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)

Port H is a 2-bit special-function port that shares all of its pins with the

Keyboard Module (KBD). See Keyboard Module (KBD) on page 373

and I/O Ports on page 293.

1.4.19 CAN Transmit Pin (TxCAN)

TxCAN is the digital output from the MSCAN08 module. See MSCAN08

Controller (MSCAN08) on page 321.

1.4.20 CAN Receive Pin (RxCAN)

RxCAN is the digital input to the MSCAN08 module. See MSCAN08

Controller (MSCAN08) on page 321.

Table 1-1. External Pins Summary

PIN NAME

PTA7 – PTA0

FUNCTION

General Purpose I/O

DRIVER TYPE

HYSTERESIS⁽¹⁾

RESET STATE

Dual State

No

Input (Hi-Z)

PTB7/ATD7 –

PTB0/ATD0

General Purpose I/0

/ ADC channel

PTC5 – PTC0

PTD7

General Purpose I/O

Dual State

No

Input (Hi-Z)

PTD6/ATD14/TACLK

General Purpose I/O/ADC Channel/Timer A Dual State

External Input clock

Yes (only for Timer A

function)

PTD5/ATD13

General Purpose I/O/ADC Channel

Dual State

No

Input (Hi-Z)

PTD4/ATD12/TBCLK

General Purpose I/O

/ADC Channel/Timer B External Input Clock

Yes (only for Timer B

function)

PTD3/ATD11–PTD0/A General Purpose I/O

Dual State

No

Input (Hi-Z)

TD8

/ADC channel

PTE7/SPSCK

General Purpose I/0

/ SPI clock

Dual State

(open drain)

Yes (only for SPI func- Input (Hi-Z)

tion)

PTE6/MOSI

PTE5/MISO

General Purpose I/0

/ SPI data path

Dual State

(open drain)

Yes (only for SPI func- Input (Hi-Z)

tion)

General Purpose I/0

/ SPI data path

Dual State

(open drain)

Yes (only for SPI func- Input (Hi-Z)

tion)

Technical Data

36

MC68HC08AZ32A — Rev 1.0

MOTOROLA

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Pin Assignments

Table 1-1. External Pins Summary (Continued)

PIN NAME

PTE4/SS

FUNCTION

DRIVER TYPE

HYSTERESIS⁽¹⁾

RESET STATE

General Purpose I/0

/ SPI Slave Select

Dual State

Yes (only for SPI func- Input (Hi-Z)

tion)

PTE3/TACH1

PTE2/TACH0

PTE1/RxD

General Purpose I/0

/ TimerA channel 1

Dual State

Yes (only for Timer A

function)

Input (Hi-Z)

General Purpose I/0

/ TimerA channel 0

Yes (only for Timer A

function)

Input (Hi-Z)

General Purpose I/0

/ SCI Receive Data

Yes (only for SCI func- Input (Hi-Z)

tion)

PTE0/TxD

General Purpose I/0

/ SCI Transmit Data

No

Input (Hi-Z)

PTF6

General Purpose I/O

Dual State

No

Input (Hi-Z)

PTF5/TBCH1

General Purpose I/O

/Timer B Channel 1

Yes (only for Timer B

function)

PTF4/TBCH0

PTF3/TACH5

PTF2/TACH4

PTF1/TACH3

PTF0/TACH2

General Purpose I/0

/ Timer B Channel 0

Dual State

Yes (only for Timer B

function)

Input (Hi-Z)

General Purpose I/0/Timer A Channel 5

Yes (only for Timer A

function)

General Purpose I/0/Timer A Channel 4

Yes (only for Timer A

function)

General Purpose I/0

/Timer A Channel 3

Yes (only for Timer A

function)

General Purpose I/0

/Timer A channel 2

Yes (only for Timer A

function)

PTG2/KBD2 –

PTG0/KBD0

General Purpose I/0/Keyboard Wakeup Pin Dual State

Yes (only for KBD func- Input (Hi-Z)

tion)

PTH1/KBD4–

PTH0/KBD3

General Purpose I/0/Keyboard Wakeup Pin Dual State

Yes (only for KBD func- Input (Hi-Z)

tion)

V

Logical Chip Power Supply

Logical Chip Ground

NA

DD

V

SS

V

CGM Analog Power Supply

CGM Analog Ground

DDA

V

SSA

VREFH

_VSS/VREFL

ADC Reference High Voltage

ADC Gnd & Reference Low Voltage

A

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

37

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Table 1-1. External Pins Summary (Continued)

PIN NAME

FUNCTION

ADC Power supply

DRIVER TYPE

HYSTERESIS⁽¹⁾

NA

RESET STATE

V

NA

DDAREF

OSC1

OSC2

CGMXFC

IRQ

External Clock In

NA

YES

NA

Input (Hi-Z)

Output

External Clock Out

PLL Loop Filter Cap

External Interrupt Request

Reset

NA

Input (Hi-Z)

Output

RST

NA

RxCAN

TxCAN

MSCAN08 Serial Input

MSCAN08 Serial Output

NA

Output

1. Hysteresis is not 100% tested but is typically a minimum of 300mV.

Details of the clock connections to each of the modules on the

MC68HC08AZ32A are shown in Table 1-3. A short description of each

clock source is also given in Table 1-2.

Table 1-2. Signal Name Conventions

Signal name

Description

CGMXCLK

CGMOUT

Buffered version of OSC1 from Clock Generator Module (CGM)

PLL-based or OSC1-based clock output from Clock Generator Module

(CGM)

Bus Clock

SPSCK

TACLK

CGMOUT divided by two

SPI serial clock

External clock Input for TIMA

External clock Input for TIMB

TBCLK

Table 1-3. Clock Source Summary

Module

ADC

Clock source

CGMXCLK or Bus Clock

CGMXCLK or CGMOUT

CGMXCLK

MSCAN08

COP

CPU

Bus Clock

Technical Data

38

MC68HC08AZ32A — Rev 1.0

General Description

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Ordering Information

Table 1-3. Clock Source Summary (Continued)

Module

EEPROM

ROM

RAM

SPI

Clock source

CGMXCLK or Bus Clock

Bus Clock

Bus Clock/SPSCK

CGMXCLK

SCI

TIMA

TIMB

PIT

Bus Clock or PTD6/ATD14/TACLK

Bus Clock or PTD4/ATD12/TBCLK

Bus Clock

KBI

Bus Clock

SIM

CGMOUT and CGMXCLK

Bus Clock

IRQ

BRK

LVI

Bus Clock

CGM

OSC1 and OSC2

1.5 Ordering Information

This section contains instructions for ordering the MC68HC08AZ32A.

1.5.1 MC Order Numbers

Table 1-4. MC Order Numbers

Operating

Temperature Range

MC Order Number

MC68HC08AZ32ACFU

– 40 °C to + 85°C

MC68HC08AZ32AVFU

MC68HC08AZ32AMFU

– 40 °C to + 105 °C

– 40 °C to + 125 °C

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

39

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Description

Technical Data

40

MC68HC08AZ32A — Rev 1.0

MOTOROLA

General Description

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 2. Memory Map

2.1 Contents

2.2

2.3

2.4

2.5

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

I/O Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Additional Status and Control Registers . . . . . . . . . . . . . . .49

Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . .50

2.2 Introduction

The CPU08 can address 64K bytes of memory space. The memory map

includes:

• 1024 bytes of RAM

• 32,256 bytes of User ROM

• 512 bytes of EEPROM

• 52 bytes of user-defined vectors

• 256 bytes of monitor ROM

The following definitions apply to the memory map representation of

reserved and unimplemented locations.

•

Reserved — Accessing a reserved location can have

unpredictable effects on MCU operation.

Unimplemented — Accessing an unimplemented location can

cause an illegal address reset (within the constraints as outlined

in System Integration Module (SIM) on page 95.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Memory Map

41

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

$0000

I/O REGISTERS (80 BYTES)

↓

$004F

$0050

↓

RAM (1024 BYTES)

$044F

$0450

↓

UNIMPLEMENTED (176 BYTES)

$04FF

$0500

↓

CAN CONTROL AND MESSAGE

BUFFERS(128 BYTES)

$057F

$0580

↓

UNIMPLEMENTED (640 BYTES)

EEPROM (512 BYTES)

$07FF

$0800

↓

$09FF

$0A00

↓

UNIMPLEMENTED (1536 BYTES)

UNIMPLEMENTED (28,672 BYTES)

ROM (16,384BYTES)

$0FFF

$1000

↓

$7FFF

$8000

↓

$BFFF

$C000

↓

ROM (15,872 BYTES)

$FDFF

$FE00

$FE01

SIM BREAK STATUS REGISTER (SBSR)

SIM RESET STATUS REGISTER (SRSR)

Figure 2-1. MC68HC08AZ32A Memory map

Technical Data

42

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Introduction

$FE02

$FE03

RESERVED

SIM BREAK FLAG CONTROL REGISTER

(SBFCR)

$FE04

$FE05

$FE06

$FE07

$FE08

$FE09

$FE0A

$FE0B

$FE0C

$FE0D

RESERVED

MORB

RESERVED

BREAK ADDRESS REGISTER HIGH (BRKH)

BREAK ADDRESS REGISTER LOW (BRKL)

BREAK STATUS AND CONTROL REGISTER

(BRKSCR)

$FE0E

$FE0F

$FE10

LVI STATUS REGISTER (LVISR)

EEPROM-EEDIVH NON-VOLATILE

REGISTER(EEDIVHNVR)

EEPROM-EEDIVL NON-VOLATILE

REGISTER(EEDIVLNVR)

$FE11

$FE12

↓

RESERVED (8 BYTES)

$FE19

$FE1A

$FE1B

EEPROM-EEDIVH REGISTER(EEDIVH)

EEPROM-EEDIVL REGISTER(EEDIVL)

EEPROM NON-VOLATILE REGISTER

(EENVR)

$FE1C

$FE1D

$FE1E

$FE1F

$FE20

↓

EEPROM CONTROL REGISTER (EECR)

RESERVED

EEPROM ARRAY CONFIGURATION (EEACR)

MONITOR ROM (256 BYTES)

$FF1F

Figure 2-1. MC68HC08AZ32A Memory map

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

43

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

$FF20

↓

UNIMPLEMENTED (160 BYTES)

$FFBF

$FFC0

↓

RESERVED (12 BYTES)

VECTORS (52 BYTES)

$FFCB

$FFCC

↓

$FFFF

Figure 2-1. MC68HC08AZ32A Memory map

Technical Data

44

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

I/O Section

2.3 I/O Section

Addresses $0000–$004F, shown in Figure 2-2, contain the I/O Data,

Status and Control Registers

Addr.

Name

Bit 7

6

5

4

3

2

1

Bit 0

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

Port A Data Register (PTA)

PTA7

PTA6

PTA5

PTA4

PTA3

PTA2

PTA1

PTA0

$0000

Port B Data Register (PTB)

Port C Data Register (PTC)

Port D Data Register (PTD)

PTB7

PTB6

PTB25

PTC5

PTD5

PTB4

PTC4

PTB3

PTC3

PTD3

PTB2

PTC2

PTD2

PTB1

PTC1

PTD1

PTB0

PTC0

PTD0

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

0

R

0

R

PTD7

PTD6

PTD4

Data Direction Register A

(DDRA)

DDRA7 DDRA6 DDRA5

DDRA4

DDRB4

DDRA3 DDRA2 DDRA1 DDRA0

DDRB3 DDRB2 DDRB1 DDRB0

Data Direction RegisterB

(DDRB)

DDRB7 DDRB6 DDRB5

0

Data Direction Register C

(DDRC)

MCLKEN

DDRC5

DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

R

Data Direction Register D

(DDRD)

DDRD7 DDRD6 DDRD5

Port E Data Register (PTE)

Port F Data Register (PTF)

PTE7

PTE6

PTF6

PTE5

PTF5

PTE4

PTF4

PTE3

PTF3

PTE2

PTF2

PTG2

PTE1

PTF1

PTG1

PTH1

PTE0

PTF0

PTG0

PTH0

0

R

0

R

0

R

0

R

0

R

0

R

0

$000A Port G Data Register (PTG)

$000B Port H Data Register (PTH)

0

R

Data Direction Register E

$000C

DDRE7 DDRE6 DDRE5

DDRE4

DDRF4

DDRE3 DDRE2 DDRE1 DDRE0

DDRF3 DDRF2 DDRF1 DDRF0

(DDRE)

0

Data Direction Register F

$000D

DDRF6 DDRF5

R

(DDRF)

0

R

0

R

0

R

0

R

0

R

0

R

Data Direction Register G

$000E

DDRG2 DDRG1 DDRG0

(DDRG)

0

R

Data Direction Register

$000F

DDRH1 DDRH0

(DDRH)

R

SP-

MSTR

$0010 SPI Control Register (SPCR)

SPRIE

R

CPOL

MODF

CPHA SPWOM

SPTE

SPE

SPTIE

SPR0

W:

R: SPRF

W:

OVRF

SPI Status and Control

$0011

ERRIE

MODFEN SPR1

Register (SPSCR)

R:

W:

R:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

$0012

$0013

SPI Data Register (SPDR)

SCI Control Register 1

(SCC1)

LOOPS ENSCI

TXINV

M

WAKE

ILTY

PEN

PTY

W:

= Unimplemented

R

= Reserved

Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 4)

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

45

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Name

Bit 7

SCTIE

R8

6

5

4

3

2

1

Bit 0

SBK

R:

W:

R:

SCI Control Register 2

(SCC2)

TCIE

SCRIE

ILIE

TE

RE

RWU

$0014

SCI Control Register 3

(SCC3)

T8

R

ORIE

OR

NEIE

NF

FEIE

FE

PEIE

PE

$0015

$0016

$0017

W:

R: SCTE

W:

TC

SCRF

IDLE

SCI Status Register 1 (SCS1)

SCI Status Register 2 (SCS2)

R:

W:

R:

0

BKF

RPF

R7

T7

0

R6

T6

0

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

$0018 SCI Data Register (SCDR)

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

W:

R:

SCI Baud Rate Register

SCP1

SCP0

R

SCR2

SCR1

SCR0

$0019

(SCBR)

0

R

0

R

0

R

0

R

0

IRQF

R

KEYF

0

ACK

0

ACKK

1

IRQ Status and Control

$001A

IMASK

MODE

Register (ISCR)

Keyboard Status/Control

IMASKK MODEK

$001B

(KBSCR)

PLLF

1

0

1

0

1

0

PLL Control Register (PCTL)

PLLIE

AUTO

MUL7

PLLON

ACQ

BCS

XLD

$001C

$001D

$001E

$001F

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

LOCK

0

PLL Bandwidth Control

Register (PBWC)

PLL Programming Register

(PPG)

MUL6

MUL5

MUL4

VRS7

VRS6

VRS5

VRS4

W:

R: LVISTOP ROMSEC LVIRST

LVIPWR SSREC COPRS STOP

COPD

R

Mask Option Register A

(MORA)

W:

R

TOIE

0

R

TSTOP

0

R

0

TRST

R

0

R

R: TOF

Timer A Status and Control

Register (TASC)

PS2

PS1

PS0

W:

R;

0

Keyboard Interrupt Enable

Register (KBIER)

KBIE4

KBIE3

KBIE2

KBIE1

KBIE0

W:

R: Bit 15

14

R

6

13

R

5

12

R

4

11

R

3

10

R

2

9

R

1

Bit 8

R

Bit 0

R

Timer A Counter Register

High (TACNTH)

W;

R

R: Bit 7

Timer A Counter Register

Low (TACNTL)

W:

R:

W:

R:

R

Timer A Modulo Register

High (TAMODH)

Bit 15

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

Timer A Modulo Register Low

(TAMODL)

Bit 7

W:

R: CH0F

Timer A Channel 0 Status and

Control Register (TASC0)

CH0IE

14

MS0B

13

MS0A

12

ELS0B

11

ELS0A

10

TOV0 CH0MAX

W:

R:

W:

R:

0

Timer A Channel 0 Register

High (TACH0H)

Bit 15

9

1

Bit 8

Bit 0

Timer A Channel 0 Register

Low (TACH0L)

Bit 7

6

5

4

3

2

W:

R: CH1F

0

R

Timer A Channel 1 Status and

Control Register (TASC1)

CH1IE

14

MS1A

12

ELS1B

11

ELS1A

10

TOV1 CH1MAX

Bit 8

W:

R:

W:

0

Timer A Channel 1 Register

High (TACH1H)

Bit 15

13

9

= Unimplemented

R

= Reserved

Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 4)

Technical Data

46

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

I/O Section

Addr.

Name

Bit 7

6

5

4

3

2

1

Bit 0

R:

W:

Timer A Channel 1 Register

Low (TACH1L)

$002B

R: CH2F

Timer A Channel 2 Status and

Control Register (TASC2)

CH2IE

14

MS2B

13

MS2A

12

ELS2B

ELS2A

TOV2 CH2MAX

$002C

$002D

$002E

$002F

$0030

$0031

$0032

$0033

$0034

$0035

$0036

$0037

$0038

$0039

$003A

$003B

$003C

$003D

$003E

$0040

$0041

$0042

W:

R:

W:

R:

0

Timer A Channel 2 Register

High (TACH2H)

Bit 15

11

10

9

1

Bit 8

Bit 0

Timer A Channel 2 Register

Low (TACH2L)

Bit 7

6

5

4

3

2

ELS3A

10

W:

R: CH3F

0

R

Timer A Channel 3 Status and

Control Register (TASC3)

CH3IE

14

MS3A

12

ELS3B

TOV3 CH3MAX

W:

R:

W:

R:

0

Timer A Channel 3 Register

High (TACH3H)

Bit 15

13

5

11

9

1

Bit 8

Bit 0

Timer A Channel 3 Register

Low (TACH3L)

Bit 7

6

4

3

ELS4B

11

2

W:

R: CH4F

Timer A Channel 4 Status and

Control Register (TASC4)

CH4IE

14

MS4B

13

MS4A

12

ELS4A

10

TOV4 CH4MAX

W:

R:

W:

R:

0

Timer A Channel 4 Register

High (TACH4H)

Bit 15

9

1

Bit 8

Bit 0

Timer A Channel 4 Register

Low (TACH4L)

Bit 7

6

5

4

3

2

W:

R: CH5F

0

R

Timer A Channel 5 Status and

Control Register (TASC5)

CH5IE

14

MS5A

12

ELS5B

11

ELS5A

10

TOV5 CH5MAX

W:

R:

W:

R:

0

Timer A Channel 5 Register

High (TACH5H)

Bit 15

13

5

9

1

Bit 8

Bit 0

Timer A Channel 5 Register

Low (TACH5L)

Bit 7

6

4

3

2

W:

R: COCO

W:

R: AD7

ADSCR

ADR

AIEN

ADCO

ADCH4

ADCH3 ADCH2 ADCH1 ADCH0

R

AD6

R

AD5

R

AD4

R

AD3

R

0

AD2

R

0

AD1

R

AD0

R

W:

R:

W:

R:

R

0

ADC Input Clock Register

(ADICLK)

ADIV2

ADIV1

ADIV0

ADICLK

R

Unimplemented

W:

R:

W:

R:

W:

R:

W:

R: TOF

0

TRST

12

R

4

R

0

R

11

R

3

Timer B Status and Control

Register (TBSC)

TOIE

TSTOP

PS2

PS1

PS0

W:

0

R: Bit 15

14

R

6

13

R

5

10

R

2

9

R

1

8

R

0

Timer B Counter Register

High (TBCNTH)

W:

R

R: Bit 7

Timer B Counter Register

Low (TBCNTL)

W:

R

= Unimplemented

R

= Reserved

Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 4)

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

47

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Addr.

Name

Bit 7

6

5

4

3

2

1

9

Bit 0

Bit 8

R:

W:

R:

Timer B Modulo Register

High (TBMODH)

Bit 15

14

13

12

11

10

$0043

Timer B Modulo Register Low

(TBMODL)

Bit 7

6

CH0IE

14

5

MS0B

13

4

MS0A

12

3

ELS0B

11

2

ELS0A

10

1

Bit 0

$0044

$0045

$0046

$0047

$0048

$0049

$004A

$004B

$004C

$004D

$004E

$004F

W:

R: CH0F

Timer B Channel 0Status and

Control Register (TBSC0)

TOV0 CH0MAX

W:

R:

W:

R:

0

Timer B Channel 0Register

High (TBCH0H)

Bit 15

9

1

8

0

Timer B Channel 0Register

Low (TBCH0L)

Bit 7

6

5

4

3

2

W:

R: CH1F

0

R

Timer B Channel 1Status/

Control Register (TBSC1)

CH1IE

14

MS1A

12

ELS1B

11

ELS1A

10

TOV1 CH1MAX

W:

R:

W:

R:

0

Timer B Channel 1Register

High (TBCH1H)

Bit 15

13

5

9

1

8

0

Timer B Channel1Register

Low (TBCH1L)

Bit 7

6

4

3

0

2

W:

R: POF

0

PIT Status & Control Register

(PSC)

POIE

14

PSTOP

13

PPS2

10

PPS1

9

PPS0

Bit 8

W:

0

PRST

12

R: Bit 15

W:

R: Bit 7

W:

11

3

PIT Counter Register HIGH)

(PCNTH)

6

5

4

2

1

Bit 0

PIT Counter Register Low

(PCNTL)

R:

W:

PIT Modulo Register High

(PMODH)

Bit 15

14

6

13

5

12

4

11

3

10

2

9

1

8

0

R:

7

PIT Modulo Register Low

(PMODL)

W:

= Unimplemented

R

= Reserved

Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 4)

Technical Data

48

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Additional Status and Control Registers

2.4 Additional Status and Control Registers

Selected addresses in the range $FE00 to $FFCB contain additional

Status and Control registers as shown in Figure 2-3. A noted exception

is the COP Control Register (COPCTL) at address $FFFF.

Addr.

Name

Bit 7

R

6

R

5

R

4

R

3

R

2

R

0

1

BW

0

Bit 0

R

R:

W:

SIM Break Status Register

(SBSR)

$FE00

R: POR

W:

COP

ILOP

ILAD

LVI

0

SIM Reset Status Register

(SRSR)

$FE01

$FE03

R:

W:

SIM Break Flag Control

Register (SBFCR)

BCFE

R

9

R

8

EEDIVCL

EEMONSE

R:

K

EESEC

AZ32A

R

Mask Option Register B

(MORB)

C

R

$FE09

W:

R:

W:

R:

W:

R:

W:

R

Break Address Register

High (BRKH)

$FE0C

$FE0D

$FE0E

Bit 15

14

6

13

12

11

10

Break Address Register

Low (BRKL)

7

5

0

4

0

3

0

2

0

1

0

Break Status and Control

Register (BRKSCR)

BRKE

BRKA

0

R: LVIOUT

W:

0

$FE0F LVI Status Register (LVISR)

R:

W:

R:

EEDIV High Non-volatile

$FE10

EEDIV

SECD

R

EEDIV10 EEDIV9 EEDIV8

Register (EEDIVHNVR)

EEDIV Low Non-volatile

$FE11

EEDIV7 EEDIV6 EEDIV5

EEDIV4 EEDIV3 EE2DIV EEDIV1 EEDIV0

Register (EEDIVLNVR)

W:

0

EEDIV Divider High

$FE1A

R:

W:

EEDIV

SECD

EEDIV10 EEDIV9 EEDIV8

Register (EEDIVH)

R:

W:

R:

W:

R:

W:

R:

W:

R:

EEDIV Divider Low

$FE1B

EEDIV7 EEDIV6 EEDIV5

EEDIV4 EEDIV3 EE2DIV EEDIV1 EEDIV0

EEPRTCT EEPB3 EEPB2 EEPB1 EEPB0

Register (EEDIVL)

$FE1C

$FE1D

$FE1F

$FFFF

EENVR

EECR

R

0

R

EEOFF EERAS1 EERAS0

ELAT

AUTO EEPGM

R

EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0

EEACR

LOW BYTE OF RESET VECTOR

WRITING TO $FFFF CLEARS COP COUNTER

COP Control Register

(COPCTL)

W:

= Unimplemented

R

= Reserved

Figure 2-3. Additional Status and Control Registers

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

49

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

2.5 Vector Addresses and Priority

Addresses in the range $FFCC to $FFFF contain the user-specified

vector locations. The vector addresses are shown in Table 2-1.

Table 2-1. Vector addresses ⁽¹⁾

Address

$FFCC

$FFCD

$FFCE

$FFCF

$FFD0

$FFD1

$FFD2

$FFD3

$FFD4

$FFD5

$FFD6

$FFD7

$FFD8

$FFD9

$FFDA

$FFDB

$FFDC

$FFDD

$FFDE

$FFDF

$FFE0

$FFE1

Vector

Lowest Priority

TIMA Channel 5 Vector (high)

TIMA Channel 5 Vector (low)

TIMA Channel 4 Vector (high)

TIMA Channel 4 Vector (low)

ADC Vector (high)

ADC Vector (low)

Keyboard Vector (high)

Keyboard Vector (low)

SCI Transmit Vector (high)

SCI Transmit Vector (Low)

SCI Receive Vector (High)

SCI Receive Vector (Low)

SCI Error Vector (High)

SCI Error Vector (Low)

MSCAN08 Transmit Vector (High)

MSCAN08 Transmit Vector (Low)

MSCAN08 Receive Vector (High)

MSCAN08 Receive Vector (Low)

MSCAN08 Error Vector (High)

MSCAN08 Error Vector (Low)

MSCAN08 Wakeup Vector (High)

MSCAN08 Wakeup Vector (Low)

Technical Data

50

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Table 2-1. Vector addresses (Continued)⁽¹⁾

Address

$FFE2

$FFE3

$FFE4

$FFE5

$FFE6

$FFE7

$FFE8

$FFE9

$FFEA

$FFEB

$FFEC

$FFED

$FFEE

$FFEF

$FFF0

$FFF1

$FFF2

$FFF3

$FFF4

$FFF5

$FFF6

$FFF7

$FFF8

$FFF9

$FFFA

$FFFB

$FFFC

$FFFD

$FFFE

$FFFF

Vector

SPI Transmit Vector (High)

SPI Transmit Vector (Low)

SPI Receive Vector (High)

SPI Receive Vector (Low)

TIMB Overflow Vector (High)

TIMB Overflow Vector (Low)

TIMB CH1 Vector (High)

TIMB CH1 Vector (Low)

TIMB CH0 Vector (High)

TIMB CH0 Vector (Low)

TIMA Overflow Vector (High)

TIMA Overflow Vector (Low)

TIMA CH3 Vector (High)

TIMA CH3 Vector (Low)

TIMA CH2 Vector (High)

TIMA CH2 Vector (Low)

TIMA CH1 Vector (High)

TIMA CH1 Vector (Low)

TIMA CH0 Vector (High)

TIMA CH0 Vector (Low)

PIT Vector (High)

PIT Vector (Low)

PLL Vector (High)

PLL Vector (Low)

IRQ Vector (High)

IRQ Vector (Low)

SWI Vector (High)

SWI Vector (Low)

Reset Vector (High)

Reset Vector (Low)

Highest Priority

1. All available ROM locations not defined by the user will by

default be filled with the software interrupt (SWI, opcode 83)

instruction – see Central Processor Unit (CPU). Take this into

account when defining vector addresses. It is recommended that

ALL vector addresses are defined.

Technical Data

51

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Memory Map

Technical Data

52

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Memory Map

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 3. RAM

3.1 Contents

3.2

3.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.2 Introduction

This section describes the 1024 bytes of RAM.

3.3 Functional Description

Addresses $0050 through $044F are RAM locations. The location of the

stack RAM is programmable. The 16-bit stack pointer allows the stack to

be anywhere in the 64K byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM

locations.

Within page zero there are 176 bytes of RAM. Because the location of

the stack RAM is programmable, all page zero RAM locations can be

used for I/O control and user data or code. When the stack pointer is

moved from its reset location at $00FF, direct addressing mode

instructions can efficiently access all page zero RAM locations. Page

zero RAM, therefore, provides an ideal location for frequently accessed

global variables.

Before processing an interrupt, the CPU uses 5 bytes of the stack to

save the contents of the CPU registers.

NOTE: For M6805 compatibility, the H register is not stacked.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

53

RAM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

RAM

During a subroutine call, the CPU uses 2 bytes of the stack to store the

return address. The stack pointer decrements during pushes and

increments during pulls.

NOTE: Care should be taken when using nested subroutines. The CPU may

overwrite data in the RAM during a subroutine or during the interrupt

stacking operation.

Technical Data

54

MC68HC08AZ32A — Rev 1.0

RAM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 4. ROM

4.1 Contents

4.2

4.3

4.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4.2 Introduction

This section describes the operation of the embedded ROM memory.

4.3 Functional Description

The user ROM consists of up to 32, 256 bytes from addresses

$8000–$FDFF. The monitor ROM and vectors are located from

$FE20–$FF5F.

Fifty-two user vectors, $FFCC–$FFFF, are dedicated to user-defined

reset and interrupt vectors.

4.4 Security

Security has been incorporated into the MC68HC08AZ32A to prevent

external viewing of the ROM contents⁽¹⁾. This feature is selected by a

mask option and ensures that customer-developed software remains

propriety. See Mask Options on page 145.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the ROM difficult for unauthorized users.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

55

ROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ROM

Technical Data

56

MC68HC08AZ32A — Rev 1.0

MOTOROLA

ROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 5. EEPROM

5.1 Contents

5.2

5.3

5.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .59

5.5

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .60

EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . .60

EEPROM Program/Erase Protection . . . . . . . . . . . . . . . .61

EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . .62

EEPROM Programming and Erasing . . . . . . . . . . . . . . . .62

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.6

EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . .67

EEPROM Control Register. . . . . . . . . . . . . . . . . . . . . . . . .67

EEPROM Array Configuration Register . . . . . . . . . . . . . .69

EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . .71

EEPROM Timebase Divider Register . . . . . . . . . . . . . . . .72

EEPROM Timebase Divider Non-Volatile Register . . . . .74

5.6.1

5.6.2

5.6.3

5.6.4

5.6.5

5.7

5.7.1

5.7.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

5.2 Introduction

This section describes the 512 bytes of electrically erasable

programmable read-only memory (EEPROM) residing at address range

$0800 to $09FF.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

57

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.3 Features

Features of the EEPROM include the following:

• 512 bytes Non-Volatile Memory

• Byte, Block, or Bulk Erasable

• Non-Volatile EEPROM Configuration and Block Protection

Options

• On-Chip Charge Pump for Programming/Erasing

• Program/Erase Protection Option

• Read Protection Option

• AUTO Bit Driven Programming/Erasing Time Feature

Technical Data

58

MC68HC08AZ32A — Rev 1.0

MOTOROLA

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEPROM Register Summary

5.4 EEPROM Register Summary

The EEPROM Register Summary is shown in Figure 5-1.

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

EEDIV Non-volatile

EEDIVSECD

R

EEDIV10 EEDIV9 EEDIV8

$FE10

Register High Write:

(EEDIVHNVR)*

Reset:

Unaffected by reset; $FF when blank

Read:

EEDIV Non-volatile

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Unaffected by reset; $FF when blank

$FE11

$FE1A

$FE1B

$FE1C

$FE1D

$FE1F

Register Low Write:

(EEDIVLNVR)*

Reset:

Read:

0

EEDIVSECD

EEDIV10 EEDIV9 EEDIV8

EE Divider Register High

Write:

(EEDIVH)

Reset:

Read:

Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0

EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0

Contents of EEDIVLNVR ($FE11)

EE Divider Register Low

Write:

(EEDIVL)

Reset:

Read:

EEPROM Non-volatile

UNUSED UNUSED UNUSED EEPRTCT EEBP3

EEBP2

EEBP1

EEBP0

Register Write:

(EENVR)*

Reset:

Unaffected by reset; $FF when blank; factory programmed $F0

0

Read:

EEPROM Control

UNUSED

0

EEOFF EERAS1 EERAS0 EELAT

AUTO

EEPGM

Register Write:

(EECR)

Reset:

0

Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3

EEBP2

EEBP1

EEBP0

EEPROM Array

Configuration Register Write:

(EEACR)

Reset:

Contents of EENVR ($FE1C)

* Non-volatile EEPROM register; write by programming.

= Unimplemented

R

= Reserved

UNUSED = Unused

Figure 5-1. EEPROM Register Summary

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

59

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.5 Functional Description

The 512 bytes of EEPROM are located at $0800-$09FF and can be

programmed or erased without an additional external high voltage

supply. The program and erase operations are enabled through the use

of an internal charge pump. For each byte of EEPROM, the write/erase

endurance is 10,000 cycles.

5.5.1 EEPROM Configuration

The 8-bit EEPROM Non-Volatile Register (EENVR) and the 16-bit

EEPROM Timebase Divider Non-Volatile Register (EEDIVNVR) contain

the default settings for the following EEPROM configurations:

• EEPROM Timebase Reference

• EEPROM Program/Erase Protection

• EEPROM Block Protection

EENVR and EEDIVNVR are non-volatile EEPROM registers. They are

programmed and erased in the same way as EEPROM bytes. The

contents of these registers are loaded into their respective volatile

registers during a MCU reset. The values in these read/write volatile

registers define the EEPROM configurations.

For EENVR, the corresponding volatile register is the EEPROM Array

Configuration Register (EEACR). For the EEDIVNVR (two 8-bit

registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile

register is the EEPROM Divider Register (EEDIV: EEDIVH and EE

DIVL).

5.5.2 EEPROM Timebase Requirements

A 35µs timebase is required by the EEPROM control circuit for program

and erase of EEPROM content. This timebase is derived from dividing

the CGMXCLK or bus clock (selected by EEDIVCLK bit in Mask Option

Register B) using a timebase divider circuit controlled by the 16-bit

EEPROM Timebase Divider EEDIV Register (EEDIVH and EEDIVL).

Technical Data

60

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

Functional Description

As the CGMXCLK or bus clock is user selected, the EEPROM Timebase

Divider Register must be configured with the appropriate value to obtain

the 35 µs. The timebase divider value is calculated by using the following

formula:

EEDIV= INT[Reference Frequency(Hz) x 35 x10^-6+0.5]

This value is written to the EEPROM Timebase Divider Register

(EEDIVH and EEDIVL) or programmed into the EEPROM Timebase

Divider Non-Volatile Register prior to any EEPROM program or erase

operations(see EEPROM Configuration on page 60 and EEPROM

Timebase Requirements on page 60).

5.5.3 EEPROM Program/Erase Protection

The EEPROM has a special feature that designates the 16 bytes of

addresses from $08F0 to $08FF to be permanently secured. This

program/erase protect option is enabled by programming the EEPRTCT

bit in the EEPROM Non-Volatile Register (EENVR) to a logic zero.

Once the EEPRTCT bit is programmed to 0 for the first time:

• Programming and erasing of secured locations $08F0 to $08FF is

permanently disabled.

• Secured locations $08F0 to $08FF can be read as normal.

• Programming and erasing of EENVR is permanently disabled.

• Bulk and Block Erase operations are disabled for the unprotected

locations $0800-$08EF, $0900-$09FF.

• Single byte program and erase operations are still available for

locations $0800-$08EF and $0900-$09FF for all bytes that are not

protected by the EEPROM Block Protect EEBPx bits (see

EEPROM Block Protection on page 62 and EEPROM Array

Configuration Register on page 69).

NOTE: Once armed, the protect option is permanently enabled. As a

consequence, all functions in the EENVR will remain in the state they

were in immediately before the security was enabled.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

61

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.5.4 EEPROM Block Protection

The 512 bytes of EEPROM are divided into four 128-byte blocks. Each

of these blocks can be protected from erase/program operations by

setting the EEBPx bit in the EENVR. Table 5-1 shows the address

ranges for the blocks.

Table 5-1. EEPROM Array Address Blocks

Block Number (EEBPx)

Address Range

$0800–$087F

$0880–$08FF

$0900–$097F

$0980–$09FF

EEBP0

EEBP1

EEBP2

EEBP3

These bits are effective after a reset or a upon read of the EENVR

register. The block protect configuration can be modified by

erasing/programming the corresponding bits in the EENVR register and

then reading the EENVR register. Please see EEPROM Array

Configuration Register on page 69 for more information.

NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a

system reset, the EEDIV security feature is permanently enabled

because the EEDIVSECD bit in the EEDIVH is always loaded with 0

thereafter. Once this security feature is armed, erase and program mode

are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the

EEDIVH and EEDIVL registers are also disabled. Therefore, be cautious

on programming a value into the EEDIVHNVR.

5.5.5 EEPROM Programming and Erasing

The unprogrammed or erase state of an EEPROM bit is a logic 1. The

factory default for all bytes within the EEPROM array is $FF.

The programming operation changes an EEPROM bit from logic 1 to

logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a

single programming operation, the minimum EEPROM programming

size is one bit; the maximum is eight bits (one byte).

Technical Data

62

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

Functional Description

The erase operation changes an EEPROM bit from logic 0 to logic 1. In

a single erase operation, the minimum EEPROM erase size is one byte;

the maximum is the entire EEPROM array.

The EEPROM can be programmed such that one or multiple bits are

programmed (written to a logic 0) at a time. However, the user may never

program the same bit location more than once before erasing the entire

byte. In other words, the user is not allowed to program a logic 0 to a bit

that is already programmed (bit state is already logic 0).

For some applications it might be advantageous to track more than 10K

events with a single byte of EEPROM by programming one bit at a time.

For that purpose, a special selective bit programming technique is

available. An example of this technique is illustrated in Table 5-2.

Table 5-2. Example Selective Bit Programming Description

Program Data

in Binary

Result

in Binary

Description

Original state of byte (erased)

n/a

1111:1111

1111:1110

1111:1100

1111:1000

1111:0000

First event is recorded by programming bit position 0

Second event is recorded by programming bit position 1

Third event is recorded by programming bit position 2

Fourth event is recorded by programming bit position 3

Events five through eight are recorded in a similar fashion

1111:1110

1111:1101

1111:1011

1111:0111

Note that none of the bit locations are actually programmed more than

once although the byte was programmed eight times.

When this technique is utilized, a program/erase cycle is defined as

multiple program sequences (up to eight) to a unique location followed

by a single erase operation.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

63

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.5.5.1 Program/Erase Using AUTO Bit

An additional feature available for EEPROM program and erase

operations is the AUTO mode. When enabled, AUTO mode will activate

an internal timer that will automatically terminate the program/erase

cycle and clear the EEPGM bit. Please see EEPROM Programming on

page 64, EEPROM Erasing on page 65 and EEPROM Control

Register on page 67 for more information.

5.5.5.2 EEPROM Programming

The unprogrammed or erase state of an EEPROM bit is a logic 1.

Programming changes the state to a logic 0. Only EEPROM bytes in the

non-protected blocks and the EENVR register can be programmed.

Use the following procedure to program a byte of EEPROM:

1. Clear EERAS1 and EERAS0 and set EELAT in the EECR.^(A)

NOTE: If using the AUTO mode, also set the AUTO bit during Step 1.

2. Write the desired data to the desired EEPROM address.^(B)

3. Set the EEPGM bit.^(C)Go to Step 7 if AUTO is set.

4. Wait for time, t_EEPGM, to program the byte.

5. Clear EEPGM bit.

6. Wait for time, t_EEFPV, for the programming voltage to fall. Go to

Step 8.

7. Poll the EEPGM bit until it is cleared by the internal timer.^(D)

8. Clear EELAT bits.^(E)

NOTE: A. EERAS1 and EERAS0 must be cleared for programming. Setting the

EELAT bit configures the address and data buses to latch data for

programming the array. Only data with a valid EEPROM address will be

latched. If EELAT is set, other writes to the EECR will be allowed after a

valid EEPROM write.

B. If more than one valid EEPROM write occurs, the last address and

data will be latched overriding the previous address and data. Once data

Technical Data

64

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

Functional Description

is written to the desired address, do not read EEPROM locations other

than the written location. (Reading an EEPROM location returns the

latched data and causes the read address to be latched).

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-

valid EEPROM address is latched. This is to ensure proper

programming sequence. Once EEPGM is set, do not read any EEPROM

locations; otherwise, the current program cycle will be unsuccessful.

When EEPGM is set, the on-board programming sequence will be

activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less

than t_EEPGM. However, on other MCUs, this delay time may be different.

For forward compatibility, software should not make any dependency on

this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single

instruction will only clear EEPGM. This is to allow time for removal of

high voltage from the EEPROM array.

5.5.5.3 EEPROM Erasing

The programmed state of an EEPROM bit is logic 0. Erasing changes

the state to a logic 1. Only EEPROM bytes in the non-protected blocks

and the EENVR register can be erased.

Use the following procedure to erase a byte, block or the entire

EEPROM array:

1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set

EELAT in EECR.^(A)

NOTE: If using the AUTO mode, also set the AUTO bit in Step 1.

2. Byte erase: write any data to the desired address.^(B)

Block erase: write any data to an address within the desired

block.^(B)

Bulk erase: write any data to an address within the array.^(B)

3. Set the EEPGM bit.^(C)Go to Step 7 if AUTO is set.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

65

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

4. Wait for a time: t_EEBYTEfor byte erase; t_EEBLOCKfor block erase;

t

_EEBULK.for bulk erase.

5. Clear EEPGM bit.

6. Wait for a time, t_EEFPV, for the erasing voltage to fall. Go to Step 8.

7. Poll the EEPGM bit until it is cleared by the internal timer.^(D)

8. Clear EELAT bits.^(E)

NOTE: A. Setting the EELAT bit configures the address and data buses to latch

data for erasing the array. Only valid EEPROM addresses will be

latched. If EELAT is set, other writes to the EECR will be allowed after a

valid EEPROM write.

B. If more than one valid EEPROM write occurs, the last address and

data will be latched overriding the previous address and data. Once data

is written to the desired address, do not read EEPROM locations other

than the written location. (Reading an EEPROM location returns the

latched data and causes the read address to be latched).

C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-

valid EEPROM address is latched. This is to ensure proper

programming sequence. Once EEPGM is set, do not read any EEPROM

locations; otherwise, the current program cycle will be unsuccessful.

When EEPGM is set, the on-board programming sequence will be

activated.

D. The delay time for the EEPGM bit to be cleared in AUTO mode is less

than t_EEBYTE/t_{EEBLOCK EEBULK}. However, on other MCUs, this delay

/t

time may be different. For forward compatibility, software should not

make any dependency on this delay time.

E. Any attempt to clear both EEPGM and EELAT bits with a single

instruction will only clear EEPGM. This is to allow time for removal of

high voltage from the EEPROM array.

Technical Data

66

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEPROM Register Descriptions

5.6 EEPROM Register Descriptions

Four I/O registers and three non-volatile registers control program, erase

and options of the EEPROM array.

5.6.1 EEPROM Control Register

This read/write register controls programming/erasing of the array.

Address: $FE1D

Bit 7

UNUSED

0

6

0

5

4

3

2

1

AUTO

0

Bit 0

EEPGM

0

Read:

Write:

Reset:

EEOFF EERAS1 EERAS0 EELAT

0

= Unimplemented

Figure 5-2. EEPROM Control Register (EECR)

Bit 7— Unused bit

This read/write bit is software programmable but has no functionality.

EEOFF — EEPROM Power Down

This read/write bit disables the EEPROM module for lower power

consumption. Any attempts to access the array will give unpredictable

results. Reset clears this bit.

1 = Disable EEPROM array

0 = Enable EEPROM array

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

67

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EERAS1 and EERAS0 — Erase/Program Mode Select Bits

These read/write bits set the erase modes. Reset clears these bits.

Table 5-3. EEPROM Program/Erase Mode Select

EEBPx

EERAS1

EERAS0

MODE

Byte Program

Byte Erase

0

1

X

0

1

0

1

X

0

Block Erase

Bulk Erase

0

1

No Erase/Program

X = don’t care

EELAT — EEPROM Latch Control

This read/write bit latches the address and data buses for

programming the EEPROM array. EELAT cannot be cleared if

EEPGM is still set. Reset clears this bit.

1 = Buses configured for EEPROM programming or erase

operation

0 = Buses configured for normal operation

AUTO — Automatic Termination of Program/Erase Cycle

When AUTO is set, EEPGM is cleared automatically after the

program/erase cycle is terminated by the internal timer.

(See note D for EEPROM Programming on page 64, EEPROM

Erasing on page 65 and EEPROM Memory Characteristics on

page 435)

1 = Automatic clear of EEPGM is enabled

0 = Automatic clear of EEPGM is disabled

EEPGM — EEPROM Program/Erase Enable

This read/write bit enables the internal charge pump and applies the

programming/erasing voltage to the EEPROM array if the EELAT bit

is set and a write to a valid EEPROM location has occurred. Reset

clears the EEPGM bit.

1 = EEPROM programming/erasing power switched on

0 = EEPROM programming/erasing power switched off

Technical Data

68

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEPROM Register Descriptions

NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single

instruction will clear EEPGM only to allow time for the removal of high

voltage.

5.6.2 EEPROM Array Configuration Register

The EEPROM array configuration register configures EEPROM security

and EEPROM block protection.

This read-only register is loaded with the contents of the EEPROM non-

volatile register (EENVR) after a reset.

Address: $FE1F

Bit 7

6

5

4

3

2

1

Bit 0

Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3

Write:

EEBP2

EEBP1

EEBP0

Reset:

Contents of EENVR ($FE1C)

Figure 5-3. EEPROM Array Configuration Register (EEACR)

Bit 7:5 — Unused Bits

These read/write bits are software programmable but have no

functionality.

EEPRTCT — EEPROM Protection Bit

The EEPRTCT bit is used to enable the security feature in the

EEPROM (see EEPROM Program/Erase Protection on page 61).

1 = EEPROM security disabled

0 = EEPROM security enabled

This feature is a write-once feature. Once the protection is enabled it

may not be disabled.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

69

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEBP[3:0] — EEPROM Block Protection Bits

These bits prevent blocks of EEPROM array from being programmed

or erased.

1 = EEPROM array block is protected

0 = EEPROM array block is unprotected

Block Number (EEBPx)

Address Range

T$0800–$087F

$0880–$08FF

$0900–$097F

$0980–$09FF

EEBP0

EEBP1

EEBP2

EEBP3

Table 5-4. EEPROM Block Protect and Security Summary

Address Range

EEBPx

EEPRTCT = 1

EEPRTCT = 0

Byte Programming

Available

Bulk, Block and Byte Only Byte Erasing

Byte Programming

Available

EEBP0 = 0

EEBP0 = 1

EEBP1 = 0

EEBP1 = 1

EEBP1 = 0

EEBP1 = 1

EEBP2 = 0

EEBP2 = 1

$0800 - $087F

Erasing Available

Available

Protected

Byte Programming

Available

Bulk, Block and Byte Only Byte Erasing

Byte Programming

Available

$0880 - $08EF

$08F0 - $08FF

$0900 - $097F

Erasing Available

Available

Protected

Byte Programming

Available

Bulk, Block and Byte

Erasing Available

Secured

(No Programming

or Erasing)

Protected

Byte Programming

Available

Bulk, Block and Byte Only Byte Erasing

Byte Programming

Available

Erasing Available

Available

Protected

Technical Data

70

MC68HC08AZ32A — Rev 1.0

MOTOROLA

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEPROM Register Descriptions

Table 5-4. EEPROM Block Protect and Security Summary

Address Range

EEBPx

EEPRTCT = 1

EEPRTCT = 0

Byte Programming

Available

Bulk, Block and Byte Only Byte Erasing

Byte Programming

Available

EEBP3 = 0

EEBP3 = 1

$0980 - $09FF

Available

Protected

5.6.3 EEPROM Nonvolatile Register

The contents of this register is loaded into the EEPROM array

configuration register (EEACR) after a reset.

This register is erased and programmed in the same way as an

EEPROM byte. (See EEPROM Control Register on page 67 for

individual bit descriptions).

Address: $FE1C

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

UNUSED UNUSED UNUSED EEPRTCT EEBP3

PV

EEBP2

EEBP1

EEBP0

= Unimplemented

PV = Programmed value or 1 in the erased state.

Figure 5-4. EEPROM Nonvolatile Register (EENVR)

NOTE: The EENVR will leave the factory programmed with $F0 such that the full

array is available and unprotected.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

71

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.6.4 EEPROM Timebase Divider Register

The 16-bit EEPROM timebase divider register consists of two 8-bit

registers: EEDIVH and EEDIVL. The 11-bit value in this register is used

to configure the timebase divider circuit to obtain the 35 µs timebase for

EEPROM control.

These two read/write registers are respectively loaded with the contents

of the EEPROM timebase divider on-volatile registers (EEDIVHNVR and

EEDIVLNVR) after a reset.

Address: $FE1A

Bit 7

6

0

5

0

4

0

3

0

2

1

Bit 0

Read:

Write:

Reset:

EEDIVSECD

EEDIV10 EEDIV9 EEDIV8

Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0

= Unimplemented

Figure 5-5. EEDIV Divider High Register (EEDIVH)

Address: $FE1B

Bit 7

6

5

4

3

2

1

Bit 0

Read:

EEDIV7 EEDIV6 EEDIV5

EEDIV4

EEDIV3 EEDIV2 EEDIV1 EEDIV0

Write:

Reset:

Contents of EEDIVLNVR ($FE11)

Figure 5-6. EEDIV Divider Low Register (EEDIVL)

Technical Data

72

MC68HC08AZ32A — Rev 1.0

MOTOROLA

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

EEPROM Register Descriptions

EEDIVSECD — EEPROM Divider Security Disable

This bit enables/disables the security feature of the EEDIV registers.

When EEDIV security feature is enabled, the state of the registers

EEDIVH and EEDIVL are locked (including EEDIVSECD bit). The

EEDIVHNVR and EEDIVLNVR non-volatile memory registers are

also protected from being erased/programmed.

1 = EEDIV security feature disabled

0 = EEDIV security feature enabled

EEDIV[10:0] — EEPROM Timebase Prescaler

These prescaler bits store the value of EEDIV which is used as the

divisor to derive a timebase of 35µs from the selected reference clock

source (CGMXCLK or bus block in the CONFIG-2 register) for the

EEPROM related internal timer and circuits. EEDIV[10:0] bits are

readable at any time. They are writable when EELAT = 0 and

EEDIVSECD = 1.

The EEDIV value is calculated by the following formula:

EEDIV= INT[Reference Frequency(Hz) x 35 x10^-6+0.5]

Where the result inside the bracket is rounded down to the nearest

integer value

For example, if the reference frequency is 4.9152MHz, the EEDIV value

is 172

NOTE: Programming/erasing the EEPROM with an improper EEDIV value may

result in data lost and reduce endurance of the EEPROM device.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

73

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

5.6.5 EEPROM Timebase Divider Non-Volatile Register

The 16-bit EEPROM timebase divider non-volatile register consists of

two 8-bit registers: EEDIVHNVR and EEDIVLNVR. The contents of

these two registers are respectively loaded into the EEPROM timebase

divider registers, EEDIVH and EEDIVL, after a reset.

These two registers are erased and programmed in the same way as an

EEPROM byte.

Address: $FE10

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

EEDIVSECD

R

EEDIV10 EEDIV9 EEDIV8

Unaffected by reset; $FF when blank

=Reserved

R

Figure 5-7. EEPROM Divider Non-Volatile Register High

(EEDIVHNVR))

Address: $FE11

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

EEDIV7 EEDIV6 EEDIV5

EEDIV4

EEDIV3 EEDIV2 EEDIV1 EEDIV0

Unaffected by reset; $FF when blank

Figure 5-8. EEPROM Divider Non-Volatile Register Low (EEDIVLNVR)

These two registers are protected from erase and program operations if

the EEDIVSECD is set to logic 1 in the EEDIVH (see EEPROM

Timebase Divider Register) or programmed to a logic 1 in the

EEDIVHNVR.

NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a

system reset, the EEDIV security feature is permanently enabled

because the EEDIVSECD bit in the EEDIVH is always loaded with 0

Technical Data

74

MC68HC08AZ32A — Rev 1.0

EEPROM

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

Low-Power Modes

thereafter. Once this security feature is armed, erase and program mode

are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the

EEDIVH and EEDIVL registers are also disabled. Therefore, care should

be taken before programming a value into the EEDIVHNVR.

5.7 Low-Power Modes

The WAIT and STOP instructions can put the MCU in low power-

consumption standby modes.

5.7.1 Wait Mode

5.7.2 Stop Mode

The WAIT instruction does not affect the EEPROM. It is possible to start

the program or erase sequence on the EEPROM and put the MCU in

wait mode.

The STOP instruction reduces the EEPROM power consumption to a

minimum. The STOP instruction should not be executed while a

programming or erasing sequence is in progress.

If stop mode is entered while EELAT and EEPGM are set, the

programming sequence will be stopped and the programming voltage to

the EEPROM array removed. The programming sequence will be

restarted after leaving stop mode; access to the EEPROM is only

possible after the programming sequence has completed.

If stop mode is entered while EELAT and EEPGM is cleared, the

programming sequence will be terminated abruptly.

In either case, the data integrity of the EEPROM is not guaranteed.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

75

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EEPROM

Technical Data

76

MC68HC08AZ32A — Rev 1.0

MOTOROLA

EEPROM

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 6. Central Processor Unit (CPU)

6.1 Contents

6.2

6.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

6.4

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . .81

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.5

6.6

6.7

6.8

6.9

Arithmetic/Logic Unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . .83

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .84

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

6.2 Introduction

This section describes the central processor unit (CPU8). The M68HC08

CPU is an enhanced and fully object-code-compatible version of the

M68HC05 CPU. The CPU08 Reference Manual (Motorola document

number CPU08RM/AD) contains a description of the CPU instruction

set, addressing modes, and architecture.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

77

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

6.3 Features

Features of the CPU include the following:

• Full upward, object-code compatibility with M68HC05 family

• 16-bit stack pointer with stack manipulation instructions

• 16-bit index register with X-register manipulation instructions

• 8.4MHz CPU internal bus frequency

• 64K byte program/data memory space

• 16 addressing modes

• Memory-to-memory data moves without using accumulator

• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

• Enhanced binary-coded decimal (BCD) data handling

• Low-power STOP and WAIT Modes

6.4 CPU registers

Figure 6-1 shows the five CPU registers. CPU registers are not part of

the memory map.

7

0

ACCUMULATOR (A)

15

H

X

INDEX REGISTER (H:X)

STACK POINTER (SP)

PROGRAM COUNTER (PC)

7

V

1

1 H

I

N Z C CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG

ZERO FLAG

NEGATIVE FLAG

INTERRUPT MASK

HALF-CARRY FLAG

TWO’S COMPLEMENT OVERFLOW FLAG

Figure 6-1. CPU Registers

Technical Data

78

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

CPU registers

6.4.1 Accumulator (A)

The accumulator is a general-purpose 8-bit register. The CPU uses the

accumulator to hold operands and the results of arithmetic/logic

operations.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

A

Write:

Reset:

Unaffected by reset

Figure 6-2. Accumulator (A)

6.4.2 Index Register (H:X)

The 16-bit index register allows indexed addressing of a 64K byte

memory space. H is the upper byte of the index register and X is the

lower byte. H:X is the concatenated 16-bit index register.

In the indexed addressing modes, the CPU uses the contents of the

index register to determine the conditional address of the operand.

Bit

0

15 14 13 12 11 10

9

0

8

0

7

6

5

4

3

2

1

Read:

Write:

Reset:

H:X

0

X

X = Indeterminate

Figure 6-3. Index Register (H:X)

The index register can also be used as a temporary data storage

location.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

79

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

6.4.3 Stack Pointer (SP)

The stack pointer is a 16-bit register that contains the address of the next

location on the stack. During a reset, the stack pointer is preset to

$00FF. The reset stack pointer (RSP) instruction sets the least

significant byte to $FF and does not affect the most significant byte. The

stack pointer decrements as data is pushed onto the stack and

increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the

stack pointer can function as an index register to access data on the

stack. The CPU uses the contents of the stack pointer to determine the

conditional address of the operand.

Bit

0

15 14 13 12 11 10

9

0

8

0

7

1

6

1

5

1

4

1

3

1

2

1

Read:

Write:

Reset:

SP

0

1

Figure 6-4. Stack Pointer (SP)

NOTE: The location of the stack is arbitrary and may be relocated anywhere in

RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct

address (page zero) space. For correct operation, the stack pointer must

point only to RAM locations.

6.4.4 Program Counter (PC)

The program counter is a 16-bit register that contains the address of the

next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next

sequential memory location every time an instruction or operand is

fetched. Jump, branch, and interrupt operations load the program

counter with an address other than that of the next sequential location.

Technical Data

80

MC68HC08AZ32A — Rev 1.0

Central Processor Unit (CPU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

CPU registers

During reset, the program counter is loaded with the reset vector

address located at $FFFE and $FFFF. The vector address is the

address of the first instruction to be executed after exiting the reset state.

Bit

0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Read:

Write:

Reset:

PC

Loaded with vector from $FFFE and $FFFF

Figure 6-5. Program Counter (PC)

6.4.5 Condition Code Register (CCR)

The 8-bit condition code register contains the interrupt mask and five

flags that indicate the results of the instruction just executed. Bits 6 and

5 are set permanently to ‘1’. The following paragraphs describe the

functions of the condition code register.

Bit 7

V

6

1

5

1

4

3

I

2

1

Z

X

Bit 0

C

Read:

Write:

Reset:

CCR

H

X

N

X

1

X

X = Indeterminate

Figure 6-6. Condition Code Register (CCR)

V — Overflow Flag

The CPU sets the overflow flag when a two's complement overflow

occurs. The signed branch instructions BGT, BGE, BLE, and BLT use

the overflow flag.

1 = Overflow

0 = No overflow

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Central Processor Unit (CPU)

81

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between

accumulator bits 3 and 4 during an ADD or ADC operation. The half-

carry flag is required for binary-coded decimal (BCD) arithmetic

operations. The DAA instruction uses the states of the H and C flags

to determine the appropriate correction factor.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt Mask

When the interrupt mask is set, all maskable CPU interrupts are

disabled. CPU interrupts are enabled when the interrupt mask is

cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but

before the interrupt vector is fetched.

1 = Interrupts disabled

0 = Interrupts enabled

NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)

is not stacked automatically. If the interrupt service routine modifies H,

then the user must stack and unstack H using the PSHH and PULH

instructions.

After the I bit is cleared, the highest-priority interrupt request is

serviced first.

A return from interrupt (RTI) instruction pulls the CPU registers from the

stack and restores the interrupt mask from the stack. After any reset, the

interrupt mask is set and can only be cleared by the clear interrupt mask

software instruction (CLI).

Technical Data

82

MC68HC08AZ32A — Rev 1.0

Central Processor Unit (CPU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Arithmetic/Logic Unit (ALU)

N — Negative Flag

The CPU sets the negative flag when an arithmetic operation, logic

operation, or data manipulation produces a negative result, setting bit

7 of the result.

1 = Negative result

0 = Non-negative result

Z — Zero Flag

The CPU sets the zero flag when an arithmetic operation, logic

operation, or data manipulation produces a result of $00.

1 = Zero result

0 = Non-zero result

C — Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation

produces a carry out of bit 7 of the accumulator or when a subtraction

operation requires a borrow. Some instructions - such as bit test and

branch, shift, and rotate - also clear or set the carry/borrow flag.

1 = Carry out of bit 7

0 = No carry out of bit 7

6.5 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the

instruction set.

Refer to the CPU08 Reference Manual (Motorola document number

CPU08RM/AD) for a description of the instructions and addressing

modes and more detail about CPU architecture.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

83

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

6.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low--power

consumption standby modes.

6.6.1 WAIT Mode

The WAIT instruction:

• clears the interrupt mask (I bit) in the condition code register,

enabling interrupts. After exit from WAIT mode by interrupt, the I

bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

6.6.2 STOP Mode

The STOP instruction:

• clears the interrupt mask (I bit) in the condition code register,

enabling external interrupts. After exit from STOP mode by

external interrupt, the I bit remains clear. After exit by reset, the I

bit is set.

• Disables the CPU clock

After exiting STOP mode, the CPU clock begins running after the

oscillator stabilization delay.

6.7 CPU During Break Interrupts

If the break module is enabled, a break interrupt causes the CPU to

execute the software interrupt instruction (SWI) at the completion of the

current CPU instruction. See Break Module on page 149. The program

counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).

A return from interrupt instruction (RTI) in the break routine ends the

break interrupt and returns the MCU to normal operation if the break

interrupt has been deasserted.

Technical Data

84

MC68HC08AZ32A — Rev 1.0

Central Processor Unit (CPU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Instruction Set Summary

6.8 Instruction Set Summary

Table 6-1 provides a summary of the M68HC08 instruction set.

Table 6-1. Instruction Set Summary

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

ii

A9

B9

C9

D9

E9

F9

9E

E9

9E

D9

dd

hh

ll

ADC #opr

ADC opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

ADC opr

ee

ff

ADC opr,X

ADC ,X

ADC opr,SP

Add with Carry

A ← (A) + (M) + (C)

↕ ↕ – ↕ ↕ ↕

IX1

IX

SP1

SP2

ff

ee

ff

ii

AB

BB

CB

DB

EB

FB

9E

EB

9E

DB

dd

hh

ll

ADD #opr

ADD opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

ADD opr

ee

ff

ADD opr,X

ADD ,X

ADD opr,SP

Add without Carry

A ← (A) + (M)

↕ ↕ – ↕ ↕ ↕

IX1

IX

SP1

SP2

ff

ee

ff

Add Immediate Value (Signed) to

SP

AIS #opr

AIX #opr

–

IMM

A7

AF

ii

2

SP ← (SP) + (16 « M)

H:X ← (H:X) + (16 « M)

Add Immediate Value (Signed) to

H:X

ii

A4

B4

C4

D4

E4

F4

9E

E4

9E

D4

dd

hh

ll

AND #opr

AND opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

AND opr

ee

ff

AND opr,X

AND ,X

AND opr,SP

Logical AND

A ← (A) & (M)

0

–

↕ ↕ –

IX1

IX

SP1

SP2

ff

ee

ff

38

48

58

68

78

9E

68

ASL opr

ASLA

DIR

INH

IX1

IX

dd

4

1

4

3

5

ASLX

Arithmetic Shift Left

(Same as LSL)

C

0

↕ –

–

↕ ↕ ↕

ASL opr,X

ASL ,X

ASL opr,SP

ff

b7

b0

SP1

37

47

57

67

77

9E

67

ASR opr

ASRA

ASRX

ASR opr,X

ASR opr,SP

DIR

INH

IX1

IX

dd

4

1

4

3

5

C

Arithmetic Shift Right

↕ –

↕ ↕ ↕

ff

SP1

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

85

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

BCC rel

Branch if Carry Bit Clear

PC ← (PC) + 2 + rel ? (C) = 0

–

REL

24

rr

3

DIR

(b0)

DIR

(b1)

DIR

(b2)

DIR

(b3)

DIR

(b4)

DIR

(b5)

DIR

(b6)

DIR

(b7)

11

13

15

17

19

1B

1D

1F

dd

4

BCLR n, opr

Clear Bit n in M

Mn ← 0

–

Branch if Carry Bit Set (Same as

BLO)

BCS rel

BEQ rel

BGE opr

PC ← (PC) + 2 + rel ? (C) = 1

PC ← (PC) + 2 + rel ? (Z) = 1

PC ← (PC) + 2 + rel ? (N V) = 0

–

REL

25

27

90

rr

3

Branch if Equal

Branch if Greater Than or Equal

To (Signed Operands)

Branch if Greater Than (Signed

Operands)

PC ← (PC) + 2 + rel ? (Z) | (N V) =

BGT opr

–

REL

92

rr

3

0

BHCC rel

BHCS rel

BHI rel

Branch if Half Carry Bit Clear

Branch if Half Carry Bit Set

Branch if Higher

PC ← (PC) + 2 + rel ? (H) = 0

PC ← (PC) + 2 + rel ? (H) = 1

PC ← (PC) + 2 + rel ? (C) | (Z) = 0

–

REL

28

29

22

rr

3

Branch if Higher or Same

(Same as BCC)

BHS rel

PC ← (PC) + 2 + rel ? (C) = 0

–

REL

24

rr

3

BIH rel

BIL rel

Branch if IRQ Pin High

Branch if IRQ Pin Low

PC ← (PC) + 2 + rel ? IRQ = 1

PC ← (PC) + 2 + rel ? IRQ = 0

–

REL

2F

2E

rr

3

ii

A5

B5

C5

D5

E5

F5

9E

E5

9E

D5

dd

hh

ll

BIT #opr

BIT opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

BIT opr

ee

ff

BIT opr,X

BIT ,X

BIT opr,SP

Bit Test

(A) & (M)

0

–

↕ ↕ –

IX1

IX

SP1

SP2

ff

ee

ff

Branch if Less Than or Equal To

(Signed Operands)

PC ← (PC) + 2 + rel ? (Z) | (N V) =

BLE opr

–

REL

93

rr

3

1

BLO rel

BLS rel

Branch if Lower (Same as BCS)

Branch if Lower or Same

PC ← (PC) + 2 + rel ? (C) = 1

–

REL

25

23

rr

3

PC ← (PC) + 2 + rel ? (C) | (Z) = 1

Branch if Less Than (Signed

Operands)

BLT opr

–

REL

91

rr

3

PC ← (PC) + 2 + rel ? (N

V) =1

Technical Data

86

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Instruction Set Summary

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

BMC rel

Branch if Interrupt Mask Clear

Branch if Minus

PC ← (PC) + 2 + rel ? (I) = 0

PC ← (PC) + 2 + rel ? (N) = 1

PC ← (PC) + 2 + rel ? (I) = 1

PC ← (PC) + 2 + rel ? (Z) = 0

PC ← (PC) + 2 + rel ? (N) = 0

PC ← (PC) + 2 + rel

–

REL

2C

2B

2D

26

2A

20

rr

3

BMI rel

BMS rel

BNE rel

BPL rel

BRA rel

Branch if Interrupt Mask Set

Branch if Not Equal

Branch if Plus

Branch Always

DIR

(b0)

DIR

(b1)

DIR

(b2)

DIR

(b3)

DIR

(b4)

DIR

(b5)

DIR

(b6)

DIR

(b7)

dd

rr

dd

rr

dd

rr

dd

rr

dd

rr

dd

rr

01

03

05

07

09

0B

0D

0F

5

BRCLR

Branch if Bit n in M Clear

PC ← (PC) + 3 + rel ? (Mn) = 0

–

↕

n,opr,rel

dd

rr

dd

rr

BRN rel

Branch Never

PC ← (PC) + 2

–

REL

21

rr

3

DIR

(b0)

DIR

(b1)

DIR

(b2)

DIR

(b3)

DIR

(b4)

DIR

(b5)

DIR

(b6)

DIR

(b7)

dd

rr

dd

rr

dd

rr

dd

rr

dd

rr

dd

rr

dd

rr

00

02

04

06

08

0A

0C

0E

5

BRSET

n,opr,rel

Branch if Bit n in M Set

PC ← (PC) + 3 + rel ? (Mn) = 1

↕

dd

rr

DIR

(b0)

DIR

(b1)

DIR

(b2)

DIR

(b3)

DIR

(b4)

DIR

(b5)

DIR

(b6)

DIR

(b7)

10

12

14

16

18

1A

1C

1E

dd

4

BSET n,opr

Set Bit n in M

Mn ← 1

–

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

87

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

PC ← (PC) + 2; push (PCL)

SP ← (SP) – 1; push (PCH)

SP ← (SP) – 1

BSR rel

Branch to Subroutine

–

REL

AD

rr

4

PC ← (PC) + rel

CBEQ opr,rel

CBEQA

31

41

51

61

71

9E

61

dd

rr

#opr,rel

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 3 + rel ? (X) – (M) = $00

PC ← (PC) + 3 + rel ? (A) – (M) = $00

PC ← (PC) + 2 + rel ? (A) – (M) = $00

PC ← (PC) + 4 + rel ? (A) – (M) = $00

DIR

IMM

IX1+

IX+

5

4

5

4

6

CBEQX

ii rr

ff rr

rr

#opr,rel

Compare and Branch if Equal

–

CBEQ

opr,X+,rel

CBEQ X+,rel

CBEQ

SP1

ff rr

opr,SP,rel

CLC

CLI

Clear Carry Bit

C ← 0

I ← 0

–

0

–

0

–

INH

98

9A

1

2

Clear Interrupt Mask

3F

4F

5F

8C

6F

7F

9E

6F

CLR opr

CLRA

M ← $00

A ← $00

X ← $00

H ← $00

M ← $00

DIR

INH

IX1

IX

dd

3

1

3

2

4

CLRX

CLRH

Clear

0

–

0

1

–

CLR opr,X

CLR ,X

ff

CLR opr,SP

SP1

ii

A1

B1

C1

D1

E1

F1

9E

E1

9E

D1

dd

hh

ll

CMP #opr

CMP opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

CMP opr

ee

ff

CMP opr,X

CMP ,X

CMP opr,SP

Compare A with M

(A) – (M)

↕ –

–

↕ ↕ ↕

IX1

IX

SP1

SP2

ff

ee

ff

33

43

53

63

73

9E

63

COM opr

COMA

M ← (M) = $FF – (M)

A ← (A) = $FF – (M)

X ← (X) = $FF – (M)

M ← (M) = $FF – (M)

DIR

INH

IX1

IX

dd

4

1

4

3

5

COMX

Complement (One’s

Complement)

0

–

↕ ↕ 1

COM opr,X

COM ,X

COM opr,SP

ff

SP1

ii

ii+1

dd

CPHX #opr

CPHX opr

IMM

DIR

65

75

3

4

Compare H:X with M

Compare X with M

(H:X) – (M:M + 1)

↕ –

↕ ↕ ↕

ii

A3

B3

C3

D3

E3

F3

9E

E3

9E

D3

dd

hh

ll

CPX #opr

CPX opr

CPX ,X

CPX opr,X

CPX opr,SP

IMM

DIR

EXT

IX2

IX1

IX

2

3

4

3

2

4

5

ee

ff

(X) – (M)

↕ –

–

↕ ↕ ↕

SP1

SP2

ff

ee

ff

Technical Data

88

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Instruction Set Summary

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

(A)

DAA

Decimal Adjust A

U –

–

↕ ↕ ↕ INH

72

2

10

A ← (A) – 1 or M ← (M) – 1 or X ← (X) –

1

DBNZ opr,rel

DBNZA rel

DBNZX rel

DBNZ

3B

4B

5B

6B

7B

9E

6B

dd

rr

5

3

5

4

6

DIR

INH

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 3 + rel ? (result) ≠ 0

PC ← (PC) + 2 + rel ? (result) ≠ 0

PC ← (PC) + 4 + rel ? (result) ≠ 0

Decrement and Branch if Not

Zero

rr

–

INH

IX1

IX

rr

opr,X,rel

ff rr

rr

DBNZ X,rel

DBNZ

opr,SP,rel

SP1

ff rr

3A

4A

5A

6A

7A

9E

6A

DEC opr

DECA

M ← (M) – 1

A ← (A) – 1

X ← (X) – 1

M ← (M) – 1

DIR

INH

IX1

IX

dd

4

1

4

3

5

DECX

Decrement

Divide

↕ –

–

↕ ↕ –

DEC opr,X

DEC ,X

DEC opr,SP

ff

SP1

A ← (H:A)/(X)

H ← Remainder

DIV

–

0

–

↕ ↕ INH

52

7

ii

A8

B8

C8

D8

E8

F8

9E

E8

9E

D8

dd

hh

ll

EOR #opr

EOR opr

EOR opr,X

EOR ,X

EOR opr,SP

IMM

DIR

EXT

IX2

IX1

IX

2

3

4

3

2

4

5

ee

ff

Exclusive OR M with A

–

↕ ↕ –

A ← (A

M)

SP1

SP2

ff

ee

ff

3C

4C

5C

6C

7C

9E

6C

INC opr

INCA

M ← (M) + 1

A ← (A) + 1

X ← (X) + 1

M ← (M) + 1

DIR

INH

IX1

IX

dd

4

1

4

3

5

INCX

Increment

↕ –

–

↕ ↕ –

INC opr,X

INC ,X

INC opr,SP

ff

SP1

dd

hh

ll

ee

ff

JMP opr

JMP opr,X

JMP ,X

DIR

EXT

IX2

IX1

IX

BC

CC

DC

EC

FC

2

3

4

3

2

Jump

PC ← Jump Address

–

dd

hh

ll

ee

ff

JSR opr

JSR opr,X

JSR ,X

DIR

EXT

IX2

IX1

IX

BD

CD

DD

ED

FD

4

5

6

5

4

PC ← (PC) + n (n = 1, 2, or 3)

Push (PCL); SP ← (SP) – 1

Push (PCH); SP ← (SP) – 1

PC ← Unconditional Address

Jump to Subroutine

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

89

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

ii

A6

B6

C6

D6

E6

F6

9E

E6

9E

D6

dd

hh

ll

LDA #opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

LDA opr

ee

ff

LDA opr,X

LDA ,X

Load A from M

A ← (M)

H:X ← (M:M + 1)

X ← (M)

0

–

↕ ↕ –

IX1

IX

SP1

SP2

LDA opr,SP

ff

ee

ff

LDHX #opr

LDHX opr

IMM

DIR

45

55

ii jj

dd

3

4

Load H:X from M

Load X from M

ii

AE

BE

CE

DE

EE

FE

9E

EE

9E

DE

dd

hh

ll

LDX #opr

LDX opr

LDX opr,X

LDX ,X

LDX opr,SP

IMM

DIR

EXT

IX2

IX1

IX

2

3

4

3

2

4

5

ee

ff

SP1

SP2

ff

ee

ff

38

48

58

68

78

9E

68

LSL opr

LSLA

DIR

INH

IX1

IX

dd

4

1

4

3

5

LSLX

Logical Shift Left

(Same as ASL)

C

0

↕ –

–

↕ ↕ ↕

LSL opr,X

LSL ,X

LSL opr,SP

ff

b7

b0

SP1

34

44

54

64

74

9E

64

LSR opr

LSRA

LSRX

LSR opr,X

LSR ,X

LSR opr,SP

DIR

INH

IX1

IX

dd

4

1

4

3

5

0

C

Logical Shift Right

↕ –

0 ↕ ↕

ff

b7

b0

SP1

dd

ii

dd

MOV opr,opr

MOV opr,X+

MOV #opr,opr

MOV X+,opr

DD

4E

5E

6E

7E

5

4

(M)

← (M)

Source

Destination

DIX+

IMD

IX+D

Move

0

–

0

–

↕ ↕ –

H:X ← (H:X) + 1 (IX+D, DIX+)

MUL

Unsigned multiply

X:A ← (X) × (A)

–

0

INH

42

5

30

40

50

60

70

9E

60

NEG opr

NEGA

DIR

INH

IX1

IX

dd

4

1

4

3

5

M ← –(M) = $00 – (M)

A ← –(A) = $00 – (A)

X ← –(X) = $00 – (X)

M ← –(M) = $00 – (M)

NEGX

Negate (Two’s Complement)

↕ –

–

↕ ↕ ↕

NEG opr,X

NEG ,X

NEG opr,SP

ff

SP1

NOP

NSA

No Operation

None

–

INH

9D

62

1

3

Nibble Swap A

A ← (A[3:0]:A[7:4])

Technical Data

90

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Instruction Set Summary

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

ii

AA

BA

CA

DA

EA

FA

9E

EA

9E

DA

dd

hh

ll

ORA #opr

ORA opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

ORA opr

ee

ff

ORA opr,X

ORA ,X

ORA opr,SP

Inclusive OR A and M

A ← (A) | (M)

0

–

↕ ↕ –

IX1

IX

SP1

SP2

ff

ee

ff

PSHA

PSHH

PSHX

PULA

PULH

PULX

Push A onto Stack

Push H onto Stack

Push X onto Stack

Pull A from Stack

Pull H from Stack

Pull X from Stack

Push (A); SP ← (SP) – 1

Push (H); SP ← (SP) – 1

Push (X); SP ← (SP) – 1

SP ← (SP + 1); Pull (A)

SP ← (SP + 1); Pull (H)

SP ← (SP + 1); Pull (X)

–

INH

87

8B

89

86

8A

88

2

39

49

59

69

79

9E

69

ROL opr

ROLA

DIR

INH

IX1

IX

dd

4

1

4

3

5

ROLX

C

Rotate Left through Carry

Rotate Right through Carry

↕ –

–

↕ ↕ ↕

ROL opr,X

ROL ,X

ROL opr,SP

ff

b7

b0

SP1

36

46

56

66

76

9E

66

ROR opr

RORA

RORX

ROR opr,X

ROR ,X

ROR opr,SP

DIR

INH

IX1

IX

dd

4

1

4

3

5

C

↕ –

–

↕ ↕ ↕

ff

b7

b0

SP1

RSP

RTI

Reset Stack Pointer

Return from Interrupt

SP ← $FF

–

INH

9C

1

SP ← (SP) + 1; Pull (CCR)

SP ← (SP) + 1; Pull (A)

SP ← (SP) + 1; Pull (X)

SP ← (SP) + 1; Pull (PCH)

SP ← (SP) + 1; Pull (PCL)

↕ ↕ ↕ ↕ ↕ ↕ INH

80

7

SP ← SP + 1; Pull (PCH)

SP ← SP + 1; Pull (PCL)

RTS

Return from Subroutine

–

INH

81

4

ii

A2

B2

C2

D2

E2

F2

9E

E2

9E

D2

dd

hh

ll

SBC #opr

SBC opr

IMM

DIR

EXT

IX2

2

3

4

3

2

4

5

SBC opr

ee

ff

SBC opr,X

SBC ,X

SBC opr,SP

Subtract with Carry

Set Carry Bit

A ← (A) – (M) – (C)

↕ –

–

↕ ↕ ↕

IX1

IX

SP1

SP2

ff

ee

ff

SEC

C ← 1

–

1

INH

99

1

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

91

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

SEI

Set Interrupt Mask

I ← 1

–

1

–

INH

9B

2

dd

hh

ll

ee

ff

B7

C7

D7

E7

F7

9E

E7

9E

D7

STA opr

DIR

EXT

IX2

3

4

3

2

4

5

STA opr

STA opr,X

STA ,X

STA opr,SP

Store A in M

M ← (A)

0

–

↕ ↕ – IX1

IX

SP1

SP2

ff

ee

ff

STHX opr

Store H:X in M

(M:M + 1) ← (H:X)

0

–

0

↕ ↕ – DIR

35

8E

dd

4

1

STOP

Enable IRQ Pin; Stop Oscillator

I ← 0; Stop Oscillator

–

INH

dd

hh

ll

ee

ff

BF

CF

DF

EF

FF

9E

EF

9E

DF

STX opr

DIR

EXT

IX2

3

4

3

2

4

5

STX opr

STX opr,X

STX ,X

STX opr,SP

Store X in M

M ← (X)

0

–

↕ ↕ – IX1

IX

SP1

SP2

ff

ee

ff

ii

A0

B0

C0

D0

E0

F0

9E

E0

9E

D0

dd

hh

ll

SUB #opr

SUB opr

IMM

DIR

EXT

2

3

4

3

2

4

5

SUB opr

ee

ff

SUB opr,X

SUB ,X

SUB opr,SP

IX2

↕ ↕ ↕

IX1

Subtract

A ← (A) – (M)

↕ – –

IX

SP1

SP2

ff

ee

ff

PC ← (PC) + 1; Push (PCL)

SP ← (SP) – 1; Push (PCH)

SP ← (SP) – 1; Push (X)

SP ← (SP) – 1; Push (A)

SP ← (SP) – 1; Push (CCR)

SP ← (SP) – 1; I ← 1

SWI

Software Interrupt

–

1

–

INH

83

9

PCH ← Interrupt Vector High Byte

PCL ← Interrupt Vector Low Byte

TAP

TAX

TPA

Transfer A to CCR

Transfer A to X

CCR ← (A)

X ← (A)

↕ ↕ ↕ ↕ ↕ ↕ INH

84

97

85

2

1

–

INH

Transfer CCR to A

A ← (CCR)

3D

4D

5D

6D

7D

9E

6D

TST opr

TSTA

DIR

INH

IX1

IX

dd

3

1

3

2

4

TSTX

Test for Negative or Zero

Transfer SP to H:X

(A) – $00 or (X) – $00 or (M) – $00

0

–

↕ ↕ –

TST opr,X

TST ,X

TST opr,SP

ff

SP1

TSX

H:X ← (SP) + 1

–

INH

95

2

Technical Data

92

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Opcode Map

1

Table 6-1. Instruction Set Summary (Continued)

Effect on

CCR

Source

Form

Operation

Description

V H I N Z C

TXA

TXS

A Accumulatorn

Transfer X to A

Transfer H:X to SP

A ← (X)

–

INH

9F

94

1

2

(SP) ← (H:X) – 1

Any bit

C Carry/borrow bitopr

CCRCondition code registerPC

ddDirect address of operandPCH

dd rrDirect address of operand and relative offset of branch instructionPCL

DDDirect to direct addressing modeREL

Operand (one or two bytes)

Program counter

Program counter high byte

Program counter low byte

Relative addressing mode

DIRDirect addressing moderel

Relative program counter offset byte

Stack pointer, 8-bit offset addressing mode

DIX+Direct to indexed with post increment addressing moderr

ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1

EXTExtended addressing modeSP2

Stack pointer 16-bit offset addressing mode

ff Offset byte in indexed, 8-bit offset addressingSP

H Half-carry bitU

Stack pointer

Undefined

H Index register high byteV

hh llHigh and low bytes of operand address in extended addressingX

I Interrupt maskZ

Overflow bit

Index register low byte

Zero bit

ii Immediate operand byte&

IMDImmediate source to direct destination addressing mode|

Logical AND

Logical OR

IMMImmediate addressing mode

INHInherent addressing mode( )

Logical EXCLUSIVE OR

Contents of

IXIndexed, no offset addressing mode–( )

IX+Indexed, no offset, post increment addressing mode#

Negation (two’s complement)

Immediate value

IX+DIndexed with post increment to direct addressing mode«

IX1Indexed, 8-bit offset addressing mode←

IX1+Indexed, 8-bit offset, post increment addressing mode?

IX2Indexed, 16-bit offset addressing mode:

MMemory location↕

Sign extend

Loaded with

If

Concatenated with

Set or cleared

Not affected

N Negative bit—

6.9 Opcode Map

MC68HC08AZ32A — Rev 1.0

Technical Data

93

MOTOROLA

Central Processor Unit (CPU)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 7. System Integration Module (SIM)

7.1 Contents

7.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

7.3

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . .98

BusTiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Clock Start-Up From POR or LVI Reset . . . . . . . . . . . . . .99

Clocks in STOP and WAIT Mode. . . . . . . . . . . . . . . . . . . .99

7.3.1

7.3.2

7.3.3

7.4

7.4.1

7.4.2

Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . .99

External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Active Resets From Internal Sources. . . . . . . . . . . . . . .101

7.4.2.1

7.4.2.2

7.4.2.3

7.4.2.4

7.4.2.5

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Computer Operating Properly (COP) Reset. . . . . . . .103

Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . .103

Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . .103

Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . .104

7.5

SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

SIM Counter During Power-On Reset. . . . . . . . . . . . . . .104

SIM Counter During STOP Mode Recovery . . . . . . . . . .105

SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . .105

7.5.1

7.5.2

7.5.3

7.6

7.6.1

Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

7.6.1.1

7.6.1.2

7.6.2

Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .107

SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

7.7

7.7.1

Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Status Flag Protection in Break Mode . . . . . . . . . . . . . .108

7.8

7.8.1

7.8.2

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

STOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

System Integration Module (SIM)

95

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

7.9

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . .112

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . .114

SIM Break Flag Control Register (SBFCR). . . . . . . . . . .115

7.9.1

7.9.2

7.9.3

7.2 Introduction

This section describes the system integration module, which supports up

to 24 external and/or internal interrupts. Together with the CPU, the SIM

controls all MCU activities. A block diagram of the SIM is shown in

Figure 7-1. Table 7-1 is a summary of the SIM I/O registers. The SIM is

a system state controller that coordinates CPU and exception timing.

The SIM is responsible for:

• Bus clock generation and control for CPU and peripherals

– STOP/WAIT/reset/break entry and recovery

– Internal clock control

• Master reset control, including power-on reset (POR) and COP

timeout

• Interrupt control:

– Acknowledge timing

– Arbitration control timing

– Vector address generation

• CPU enable/disable timing

Technical Data

96

MC68HC08AZ32A — Rev 1.0

System Integration Module (SIM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Introduction

MODULE STOP

MODULE WAIT

CPU STOP (FROM CPU)

CPU WAIT (FROM CPU)

STOP/WAIT

CONTROL

SIMOSCEN (TO CGM)

SIM

COUNTER

COP CLOCK

CGMXCLK (FROM CGM)

CGMOUT (FROM CGM)

÷ 2

CLOCK

CONTROL

CLOCK GENERATORS

INTERNAL CLOCKS

LVI (FROM LVI MODULE)

RESET

PIN LOGIC

POR CONTROL

RESET PIN CONTROL

MASTER

RESET

CONTROL

ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS

MAP DECODERS)

SIM RESET STATUS REGISTER

COP (FROM COP MODULE)

RESET

INTERRUPT SOURCES

CPU INTERFACE

INTERRUPT CONTROL

AND PRIORITY DECODE

Figure 7-1. SIM Block Diagram

Table 7-1. SIM I/O Register Summary

Register Name

Bit 7

6

5

4

3

2

R

0

1

BW

0

Bit 0 Addr.

R:

SIM Break Status Register (SBSR)

SIM Reset Status Register (SRSR)

R

0

$FE00

W:

R: POR

W:

COP ILOP ILAD

LVI

$FE01

$FE03

SIM Break Flag Control Register

(SBFCR)

BCFE

R

= Reserved for factory test

= Unimplemented

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

97

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Table 7-2 shows the internal signal names used in this section.

Table 7-2. Signal Naming Conventions

Signal Name

CGMXCLK

CGMVCLK

Description

Buffered Version of OSC1 from Clock Generator Module (CGM)

PLL Output

PLL-based or OSC1-based clock output from CGM Module

(Bus Clock = CGMOUT divided by two)

CGMOUT

IAB

IDB

Internal Address Bus

Internal Data Bus

PORRST

IRST

Signal from the Power-on Reset Module to the SIM

Internal Reset Signal

R/W

Read/WriteSignal

7.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and

peripherals on the MCU. The system clocks are generated from an

incoming clock, CGMOUT, as shown in Figure 7-2. This clock can come

from either an external oscillator or from the on-chip PLL. See Clock

Generator Module (CGM) on page 117.

CGMXCLK

OSC1

SIM COUNTER

CLOCK

SELECT

CIRCUIT

A

B

CGMOUT

BUS CLOCK

GENERATORS

÷ 2

CGMVCLK

PLL

S*

*When S = 1,

CGMOUT = B

BCS

SIM

PTC3

MONITOR MODE

USER MODE

CGM

Figure 7-2. CGM Clock Signals

Technical Data

98

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Reset and System Initialization

7.3.1 BusTiming

In user mode, the internal bus frequency is either the crystal oscillator

output (CGMXCLK) divided by four or the PLL output (CGMVCLK)

divided by four. See Clock Generator Module (CGM) on page 117.

7.3.2 Clock Start-Up From POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module

generates a reset, the clocks to the CPU and peripherals are inactive

and held in an inactive phase until after the 4096 CGMXCLK cycle POR

timeout has been completed. The RST pin is driven low by the SIM

during this entire period. The bus clocks start upon completion of the

timeout.

7.3.3 Clocks in STOP and WAIT Mode

Upon exit from STOP mode (by an interrupt, break, or reset), the SIM

allows CGMXCLK to clock the SIM counter. The CPU and peripheral

clocks do not become active until after the STOP delay timeout. This

timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP mode

on page 111.

In WAIT mode, the CPU clocks are inactive. The SIM also produces two

sets of clocks for other modules. Refer to the WAIT mode subsection of

each module to see if the module is active or inactive in WAIT mode.

Some modules can be programmed to be active in WAIT mode.

7.4 Reset and System Initialization

The MCU has the following reset sources:

• Power-on reset module (POR)

• External reset pin (RST)

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

99

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

• Illegal opcode

• Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes

all registers to be returned to their default values and all modules to be

returned to their reset states.

An internal reset clears the SIM counter, see SIM Counter on page 104,

but an external reset does not. Each of the resets sets a corresponding

bit in the SIM reset status register (SRSR). See SIM Registers on page

112.

7.4.1 External Pin Reset

Pulling the asynchronous RST pin low halts all processing. The PIN bit

of the SIM reset status register (SRSR) is set as long as RST is held low

for a minimum of 67 CGMXCLK cycles, assuming that neither the POR

nor the LVI was the source of the reset. See Table 7-3 for details. Figure

7-3 shows the relative timing.

Table 7-3. PIN Bit Set Timing

Reset type

POR/LVI

Number of cycles required to set PIN

4163 (4096 + 64 + 3)

All others

67 (64 + 3)

CGMOUT

RST

IAB

VECT H

VECT L

PC

Figure 7-3. External Reset Timing

Technical Data

100

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Reset and System Initialization

7.4.2 Active Resets From Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK

cycles to allow for resetting of external peripherals. The internal reset

signal IRST continues to be asserted for an additional 32 cycles. See

Figure 7-4. An internal reset can be caused by an illegal address, illegal

opcode, COP timeout, LVI, or POR. See Figure 7-5. Note that for LVI or

POR resets, the SIM cycles through 4096 CGMXCLK cycles, during

which the SIM forces the RST pin low. The internal reset signal then

follows the sequence from the falling edge of RST as shown in Figure

7-4.

IRST

RST PULLED LOW BY MCU

RST

32 CYCLES

CGMXCLK

IAB

VECTOR HIGH

Figure 7-4. Internal Reset Timing

The COP reset is asynchronous to the bus clock.

ILLEGAL ADDRESS RST

ILLEGAL OPCODE RST

INTERNAL RESET

COPRST

LVI

POR

Figure 7-5. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

101

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

7.4.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module

(POR) generates a pulse to indicate that power-on has occurred. The

external reset pin (RST) is held low while the SIM counter counts out

4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and

memories are released from reset to allow the reset vector sequence to

occur.

At power-on, the following events occur:

• A POR pulse is generated

• The internal reset signal is asserted

• The SIM enables CGMOUT

• Internal clocks to the CPU and modules are held inactive for 4096

CGMXCLK cycles to allow the oscillator to stabilize

• The RST pin is driven low during the oscillator stabilization time

• The POR bit of the SIM reset status register (SRSR) is set and all

other bits in the register are cleared

OSC1

PORRST

4096

CYCLES

32

CYCLES

32

CYCLES

CGMXCLK

CGMOUT

RST

IAB

$FFFE

$FFFF

Figure 7-6. POR Recovery

Technical Data

102

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Reset and System Initialization

7.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of

the COP counter causes an internal reset and sets the COP bit in the

SIM reset status register (SRSR). The SIM actively pulls down the RST

pin for all internal reset sources.

To prevent a COP module timeout, a value (any value) should be written

to location $FFFF. Writing to location $FFFF clears the COP counter and

bits 12 through 4 of the SIM counter. The SIM counter output, which

occurs at least every 2¹³– 2⁴CGMXCLK cycles, drives the COP

counter. The COP should be serviced as soon as possible out of reset

to guarantee the maximum amount of time before the first timeout.

The COP module is disabled if the RST pin or the IRQ pin is held at

V_DD+ V_HIwhile the MCU is in monitor mode. The COP module can be

disabled only through combinational logic conditioned with the high

voltage signal on the RST or the IRQ pin. This prevents the COP from

becoming disabled as a result of external noise. During a break state,

V_DD+ V_HIon the RST pin disables the COP module.

7.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An

illegal instruction sets the ILOP bit in the SIM reset status register

(SRSR) and causes a reset.

If the STOP enable bit, STOP, in the mask option register is logic ‘0’, the

SIM treats the STOP instruction as an illegal opcode and causes an

illegal opcode reset. The SIM actively pulls down the RST pin for all

internal reset sources.

7.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal

address reset. The SIM verifies that the CPU is fetching an opcode prior

to asserting the ILAD bit in the SIM reset status register SRSR) and

resetting the MCU. A data fetch from an unmapped address does not

generate a reset. The SIM actively pulls down the RST pin for all internal

reset sources.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

103

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

NOTE: Extra care should be exercised if code in this part has been taken

from another HC08 with a different memory map since some legal

addresses could become illegal addresses on a smaller ROM. It is

the user’s responsibility to check their code for illegal addresses.

Older HC08s may have a different illegal address reset

specification.

7.4.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when

the V_DDvoltage falls to the LVI_TRIPFvoltage. The LVI bit in the SIM reset

status register (SRSR) is set, and the external reset pin (RST) is held low

while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK

cycles later, the CPU is released from reset to allow the reset vector

sequence to occur. The SIM actively pulls down the RST pin for all

internal reset sources.

7.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in

STOP mode recovery to allow the oscillator time to stabilize before

enabling the internal bus (IBUS) clocks. The SIM counter also serves as

a prescaler for the computer operating properly (COP) module. The SIM

counter overflow supplies the clock for the COP module. The SIM

counter is 13 bits long and is clocked by the falling edge of CGMXCLK.

7.5.1 SIM Counter During Power-On Reset

The power-on reset (POR) module detects power applied to the MCU.

At power-on, the POR circuit asserts the signal PORRST. Once the SIM

is initialized, it enables the clock generation module (CGM) to drive the

bus clock state machine.

Technical Data

104

MC68HC08AZ32A — Rev 1.0

System Integration Module (SIM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Exception Control

7.5.2 SIM Counter During STOP Mode Recovery

The SIM counter is also used for STOP mode recovery. The STOP

instruction clears the SIM counter. After an interrupt or reset, the SIM

senses the state of the short STOP recovery bit, SSREC, in the mask

option register. If the SSREC bit is a logic ‘1’, then the STOP recovery is

reduced from the normal delay of 4096 CGMXCLK cycles down to 32

CGMXCLK cycles. This is ideal for applications using canned oscillators

that do not require long start-up times from STOP mode. External crystal

applications should use the full STOP recovery time, that is, with SSREC

cleared.

7.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See STOP mode on

page 111 for details). The SIM counter is free-running after all reset

states, see Active Resets From Internal Sources on page 101 for

counter control and internal reset recovery sequences.

7.6 Exception Control

Normal, sequential program execution can be changed in three different

ways:

• Interrupts

– Maskable hardware CPU interrupts

– Non-maskable software interrupt instruction (SWI)

• Reset

• Break interrupts

7.6.1 Interrupts

At the beginning of an interrupt, the CPU saves the CPU register

contents onto the stack and sets the interrupt mask (I-bit) to prevent

additional interrupts. At the end of an interrupt, the RTI instruction

recovers the CPU register contents from the stack so that normal

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

105

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

processing can resume. Figure 7-7 shows interrupt entry timing, and

Figure 7-8 shows interrupt recovery timing.

.

MODULE

INTERRUPT

I-bit

IAB

VECT L

START ADDRESS

DUMMY

SP

SP – 1

SP – 2

SP – 3

SP – 4

VECT H

PC –1[7:0]

V DATA H

V DATA L

IDB

R/W

DUMMY

PC–1[15:8]

X

A

CCR

OPCODE

Figure 7-7. Interrupt Entry

Interrupts are latched, and arbitration is performed in the SIM at the start

of interrupt processing. The arbitration result is a constant that the CPU

uses to determine which vector to fetch. Once an interrupt is latched by

the SIM, no other interrupt may take precedence, regardless of priority,

until the latched interrupt is serviced (or the I-bit is cleared). See Figure

7-8.

MODULE

INTERRUPT

I-BIT

IAB

SP – 2

SP – 4

SP – 3

SP – 1

SP

PC

PC + 1

IDB

OPCODE

CCR

A

X

PC –1[7:0] PC–1[15:8]

OPERAND

R/W

Figure 7-8. Interrupt Recovery

Technical Data

106

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Exception Control

7.6.1.1 Hardware Interrupts

Processing of a hardware interrupt begins after completion of the current

instruction. When the instruction is complete, the SIM checks all pending

hardware interrupts. If interrupts are not masked (I-bit clear in the

condition code register), and if the corresponding interrupt enable bit is

set, the SIM proceeds with interrupt processing; otherwise, the next

instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction

execution, the highest priority interrupt is serviced first. Figure 7-8

demonstrates what happens when two interrupts are pending. If an

interrupt is pending upon exit from the original interrupt service routine,

the pending interrupt is serviced before the LDA instruction is executed.

CLI

LDA #$FF

BACKGROUND ROUTINE

INT1

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

INT2

PSHH

INT2 INTERRUPT SERVICE ROUTINE

PULH

RTI

Figure 7-9. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI

instructions. However, in the case of the INT1 RTI prefetch, this is a

redundant operation.

NOTE: To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

107

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

modifies the H register or uses the indexed addressing mode, software

should save the H register and then restore it prior to exiting the routine.

7.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I-bit) in the

condition code register.

NOTE: A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware interrupt does.

7.6.2 Reset

All reset sources always have equal and highest priority and cannot be

arbitrated.

7.7 Break Interrupts

The break module can stop normal program flow at a software-

programmable break point by asserting its break interrupt output. See

Break Module on page 149. The SIM puts the CPU into the break state

by forcing it to the SWI vector location. Refer to the break interrupt

subsection of each module to see how each module is affected by the

break state.

7.7.1 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can

be cleared during break mode. The user can select whether flags are

protected from being cleared by properly initializing the break clear flag

enable bit (BCFE) in the SIM break flag control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared

while in break mode. This protection allows registers to be freely read

and written during break mode without losing status flag information.

Technical Data

108

MC68HC08AZ32A — Rev 1.0

System Integration Module (SIM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Low-Power Modes

Setting the BCFE bit enables the clearing mechanisms. Once cleared in

break mode, a flag remains cleared even when break mode is exited.

Status flags with a two-step clearing mechanism — for example, a read

of one register followed by the read or write of another — are protected,

even when the first step is accomplished prior to entering break mode.

Upon leaving break mode, execution of the second step will clear the flag

as normal.

7.8 Low-Power Modes

Executing the STOP/WAIT instruction puts the MCU in a low-power-

consumption mode for standby situations. The SIM holds the CPU in a

non-clocked state. The operation of each of these modes is described

below. Both STOP and WAIT clear the interrupt mask (I) in the condition

code register, allowing interrupts to occur.

7.8.1 WAIT Mode

In WAIT mode, the CPU clocks are inactive while the peripheral clocks

continue to run. Figure 7-10 shows the timing for WAIT mode entry.

A module that is active during WAIT mode can wake up the CPU with an

interrupt if the interrupt is enabled. Stacking for the interrupt begins one

cycle after the WAIT instruction during which the interrupt occurred. In

WAIT mode, the CPU clocks are inactive. Refer to the WAIT mode

subsection of each module to see if the module is active or inactive in

WAIT mode. Some modules can be programmed to be active in WAIT

mode.

WAIT mode can also be exited by a reset or break. A break interrupt

during WAIT mode sets the SIM break WAIT bit, BW, in the SIM break

status register (SBSR). If the COP disable bit, COPD, in the mask option

register is ‘0’, then the computer operating properly (COP) module is

enabled and remains active in WAIT mode.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

109

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

IAB

WAIT ADDR

WAIT ADDR + 1

SAME

IDB

PREVIOUS DATA

SAME

NEXT OPCODE

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

Figure 7-10. WAIT Mode Entry Timing

Figure 7-10 and Figure 7-12 show the timing for WAIT recovery.

IAB

IDB

$6E0B

$A6

$6E0C

$00FF

$00FE

$00FD

$00FC

$A6

$01

$0B

$6E

EXITSTOPWAIT

NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt

Figure 7-11. WAIT Recovery From Interrupt or Break

32

Cycles

32

Cycles

IAB

$6E0B

$A6

RST VCT L

RST VCT H

IDB $A6

RST

$A6

CGMXCLK

Figure 7-12. WAIT Recovery From Internal Reset

Technical Data

110

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Low-Power Modes

7.8.2 STOP mode

In STOP mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from

STOP mode. Stacking for interrupts begins after the selected STOP

recovery time has elapsed. Reset also causes an exit from STOP mode.

The SIM disables the clock generator module outputs (CGMOUT and

CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP

recovery time is selectable using the SSREC bit in the mask option

register (MOR). If SSREC is set, STOP recovery is reduced from the

normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for

applications using canned oscillators that do not require long start-up

times from STOP mode.

NOTE: External crystal applications should use the full STOP recovery time by

clearing the SSREC bit.

The break module is inactive in STOP mode. The STOP instruction does

not affect break module register states.

The SIM counter is held in reset from the execution of the STOP

instruction until the beginning of STOP recovery. It is then used to time

the recovery period. Figure 7-13 shows STOP mode entry timing.

CPUSTOP

IAB

IDB

R/W

STOP ADDR

STOP ADDR + 1

SAME

PREVIOUS DATA

NEXT OPCODE

SAME

NOTE: Previous data can be operand data or the STOP opcode, depending on the last

instruction.

Figure 7-13. STOP Mode Entry Timing

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

System Integration Module (SIM)

111

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

STOP RECOVERY PERIOD

CGMXCLK

INT/BREAK

IAB

STOP + 2 STOP + 2

SP

SP – 1

SP – 2

SP – 3

STOP +1

Figure 7-14. STOP Mode Recovery From Interrupt

7.9 SIM Registers

The SIM has three memory mapped registers. Table 7-4 shows the

mapping of these registers.

Table 7-4. SIM Registers

Address

$FE00

$FE01

$FE03

Register

SBSR

Access mode

User

SRSR

User

SBFCR

User

7.9.1 SIM Break Status Register (SBSR)

The SIM break status register contains a flag to indicate that a break

caused an exit from STOP or WAIT mode.

Bit 7

R

6

5

4

3

2

1

BW

Note⁽¹⁾

0

Bit 0

R

Read:

Write:

Reset:

SBSR

$FE00

R

= Reserved for factory test

1. Writing a logic ‘0’ clears BW.

Figure 7-15. SIM Break Status Register (SBSR)

Technical Data

112

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

SIM Registers

BW — SIM Break WAIT

This status bit is useful in applications requiring a return to WAIT

mode after exiting from a break interrupt. BW can be cleared by

writing a logic ‘0’ to it. Reset clears BW.

1 = WAIT mode was exited by break interrupt

0 = WAIT mode was not exited by break interrupt

BW can be read within the break state SWI routine. The user can modify

the return address on the stack by subtracting one from it. The following

code is an example of this.

; This code works if the H register has been pushed onto the stack in the break

; service routine software. This code should be executed at the end of the

; break service routine software.

HIBYTE EQU

LOBYTE EQU

5

6

;

If not BW, do RTI

BRCLR BW,SBSR, RETURN

; See if WAIT mode was exited by break.

;

TST

BNE

DEC

LOBYTE,SP

DOLO

; If RETURNLO is not ‘0’,

; then just decrement low byte.

; Else deal with high byte, too.

; Point to WAIT opcode.

HIBYTE,SP

LOBYTE,SP

DOLO

RETURN PULH

RTI

; Restore H register.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

113

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

7.9.2 SIM Reset Status Register (SRSR)

This register contains six flags that show the source of the last reset. The

SIM reset status register can be cleared by reading it. A power-on reset

sets the POR bit and clears all other bits in the register.

Bit 7

6

5

4

3

2

1

Bit 0

0

Read:

Write:

POR:

POR

COP

ILOP

ILAD

0

LVI

SRSR

$FE01

1

0

= Unimplemented

Figure 7-16. SIM Reset Status Register (SRSR)

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset was caused by the LVI circuit

0 = POR or read of SRSR

Technical Data

114

MC68HC08AZ32A — Rev 1.0

System Integration Module (SIM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

SIM Registers

7.9.3 SIM Break Flag Control Register (SBFCR)

The SIM break control register contains a bit that enables software to

clear status bits while the MCU is in a break state.

Bit 7

6

5

4

3

2

1

Bit 0

R

Read:

Write:

Reset:

SBFCR

$FE03

BCFE

R

0

R

= Reserved for factory test

Figure 7-17. SIM Break Flag Control Register (SBFCR)

BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing

status registers while the MCU is in a break state. To clear status bits

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not clearable during break

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

System Integration Module (SIM)

115

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

System Integration Module (SIM)

Technical Data

116

MC68HC08AZ32A — Rev 1.0

MOTOROLA

System Integration Module (SIM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 8. Clock Generator Module (CGM)

8.1 Contents

8.2

8.3

8.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

8.4.1

8.4.2

Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .119

Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . .121

8.4.2.1

8.4.2.2

8.4.2.3

8.4.2.4

8.4.2.5

8.4.3

Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Acquisition and Tracking Modes . . . . . . . . . . . . . . . .123

Manual and Automatic PLL Bandwidth Modes . . . . .123

Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . .125

Special Programming Exceptions . . . . . . . . . . . . . . .127

Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . .127

8.4.4

CGM External Connections. . . . . . . . . . . . . . . . . . . . . . .128

8.5

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . .129

Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . .129

External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . .129

Analog Power Pin (V_DDA). . . . . . . . . . . . . . . . . . . . . . . . .130

Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . .130

Crystal Output Frequency Signal (CGMXCLK) . . . . . . .130

CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .130

CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . .130

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.6

8.5.7

8.5.8

8.6

CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . .133

PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . .135

8.6.1

8.6.2

8.6.3

8.7

8.8

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Clock Generator Module (CGM)

117

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

8.8.1

8.8.2

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

8.9

CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .138

8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . .138

8.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . .138

8.10.2 Parametric Influences on Reaction Time. . . . . . . . . . . .140

8.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . .141

8.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . .141

8.2 Introduction

The CGM generates the crystal clock signal, CGMXCLK, which operates

at the frequency of the crystal. The CGM also generates the base clock

signal, CGMOUT, from which the system clocks are derived. CGMOUT

is based on either the crystal clock divided by two or the phase-locked

loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency

generator designed for use with 1-MHz to 16-MHz crystals or ceramic

resonators. The PLL can generate an 8-MHz bus frequency without

using high frequency crystals.

8.3 Features

Features of the CGM include:

• Phase-Locked Loop with Output Frequency in Integer Multiples of

the Crystal Reference

• Programmable Hardware Voltage-Controlled Oscillator (VCO) for

Low-Jitter Operation

• Automatic Bandwidth Control Mode for Low-Jitter Operation

• Automatic Frequency Lock Detector

• CPU Interrupt on Entry or Exit from Locked Condition

Technical Data

118

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Functional Description

8.4 Functional Description

The CGM consists of three major submodules:

• Crystal oscillator circuit — The crystal oscillator circuit generates

the constant crystal frequency clock, CGMXCLK.

• Phase-locked loop (PLL) — The PLL generates the

programmable VCO frequency clock CGMVCLK.

• Base clock selector circuit — This software-controlled circuit

selects either CGMXCLK divided by two or the VCO clock,

CGMVCLK, divided by two as the base clock, CGMOUT. The

system clocks are derived from CGMOUT.

Figure 8-1 shows the structure of the CGM.

8.4.1 Crystal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an

external crystal. The OSC1 pin is the input to the amplifier and the OSC2

pin is the output. The SIMOSCEN signal enables the crystal oscillator

circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and

runs at a rate equal to the crystal frequency. CGMXCLK is then buffered

to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other modules which require precise timing

for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%

and depends on external factors, including the crystal and related

external components.

An externally generated clock also can feed the OSC1 pin of the crystal

oscillator circuit. Connect the external clock to the OSC1 pin and let the

OSC2 pin float.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

119

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

CGMXCLK

CGMOUT

OSC1

CLOCK

SELECT

CIRCUIT

A

B

÷ 2

S*

*When S = 1,

CGMOUT = B

CGMRDV

CGMRCLK

BCS

PTC3

V

CGMXFC

V

SS

DDA

MONITOR MODE

VRS7–VRS4

USER MODE

VOLTAGE

CONTROLLED

OSCILLATOR

PHASE

DETECTOR

LOOP

FILTER

PLL ANALOG

CGMINT

LOCK

DETECTOR

BANDWIDTH

CONTROL

INTERRUPT

CONTROL

LOCK

AUTO

ACQ

PLLIE

PLLF

MUL7–MUL4

CGMVDV

CGMVCLK

FREQUENCY

DIVIDER

Figure 8-1. CGM Block Diagram

Technical Data

120

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Functional Description

Register Name

Bit 7

PLLIE

0

6

5

PLLON

1

4

BCS

0

3

2

1

Bit 0

Read:

PLLF

1

PLL Control Register (PCTL) Write:

Reset:

0

1

0

1

0

1

0

1

0

Read:

LOCK

AUTO

0

ACQ

0

XLD

0

PLL Bandwidth Control Register

Write:

(PBWC)

Reset:

0

Read:

PLL Programming Register (PPG) Write:

Reset:

MUL7

0

MUL6

1

MUL5

1

MUL4

0

VRS7

0

VRS6

1

VRS5

1

VRS4

0

= Unimplemented

Figure 8-2. I/O Register Summary

Table 8-1. I/O Register Address Summary

Register

Address

PCTL

PBWC

$001D

PPG

$001C

$001E

8.4.2 Phase-Locked Loop Circuit (PLL)

The PLL is a frequency generator that can operate in either acquisition

mode or tracking mode, depending on the accuracy of the output

frequency. The PLL can change between acquisition and tracking

modes either automatically or manually.

8.4.2.1 Circuits

The PLL consists of these circuits:

• Voltage-controlled oscillator (VCO)

• Modulo VCO frequency divider

• Phase detector

• Loop filter

• Lock detector

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

121

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

The operating range of the VCO is programmable for a wide range of

frequencies and for maximum immunity to external noise, including

supply and CGMXFC noise. The VCO frequency is bound to a range

from roughly one-half to twice the center-of-range frequency, f_CGMVRS

Modulating the voltage on the CGMXFC pin changes the frequency

.

within this range. By design, f_CGMVRSis equal to the nominal center-of-

range frequency, f_NOM, (4.9152 MHz) times a linear factor L or (L)f_NOM

.

CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.

CGMRCLK runs at a frequency, f_CGMRCLK, and is fed to the PLL through

a buffer. The buffer output is the final reference clock, CGMRDV,

running at a frequency f_CGMRDV= f_CGMRCLK

.

The VCO’s output clock, CGMVCLK, running at a frequency f_CGMVCLK

,

is fed back through a programmable modulo divider. The modulo divider

reduces the VCO clock by a factor, N. The divider’s output is the VCO

feedback clock, CGMVDV, running at a frequency

f

_CGMVDV= f_CGMVCLK/N. See Programming the PLL on page 125 for

more information.

The phase detector then compares the VCO feedback clock, CGMVDV,

with the final reference clock, CGMRDV. A correction pulse is generated

based on the phase difference between the two signals. The loop filter

then slightly alters the dc voltage on the external capacitor connected to

CGMXFC based on the width and direction of the correction pulse. The

filter can make fast or slow corrections depending on its mode, as

described in Acquisition and Tracking Modes on page 123. The value

of the external capacitor and the reference frequency determines the

speed of the corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock,

CGMVDV, and the final reference clock, CGMRDV. Therefore, the

speed of the lock detector is directly proportional to the final reference

frequency, f_CGMRDV. The circuit determines the mode of the PLL and the

lock condition based on this comparison.

Technical Data

122

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Functional Description

8.4.2.2 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two

operating modes:

• Acquisition mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL

startup or when the PLL has suffered a severe noise hit and the

VCO frequency is far off the desired frequency. When in

acquisition mode, the ACQ bit is clear in the PLL bandwidth control

register. See PLL Bandwidth Control Register on page 133.

• Tracking mode — In tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct, such as when the PLL is selected as the base clock

source. See Base Clock Selector Circuit on page 127. The PLL

is automatically in tracking mode when it’s not in acquisition mode

or when the ACQ bit is set.

8.4.2.3 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, CGMVCLK, is safe to use as the source for the base clock,

CGMOUT. See PLL Bandwidth Control Register on page 133. If PLL

CPU interrupt requests are enabled, the software can wait for a PLL

CPU interrupt request and then check the LOCK bit. If CPU interrupts

are disabled, software can poll the LOCK bit continuously (during PLL

startup, usually) or at periodic intervals. In either case, when the LOCK

bit is set, the VCO clock is safe to use as the source for the base clock.

See Base Clock Selector Circuit on page 127. If the VCO is selected

as the source for the base clock and the LOCK bit is clear, the PLL has

suffered a severe noise hit and the software must take appropriate

action, depending on the application. See Interrupts on page 137.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

123

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

These conditions apply when the PLL is in automatic bandwidth control

mode:

• The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a

read-only indicator of the mode of the filter. See Acquisition and

Tracking Modes on page 123.

• The ACQ bit is set when the VCO frequency is within a certain

tolerance,

∆_trk, and is cleared when the VCO frequency is out of a

certain tolerance,

∆_unt. See Electrical Specifications on page 423.

• The LOCK bit is a read-only indicator of the locked state of the

PLL.

• The LOCK bit is set when the VCO frequency is within a certain

tolerance,

∆_Lock, and is cleared when the VCO frequency is out of a

certain tolerance,

∆_unl. See Electrical Specifications on page 423.

• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s

lock condition changes, toggling the LOCK bit. See PLL Control

Register on page 131.

The PLL also can operate in manual mode (AUTO = 0). Manual mode is

used by systems that do not require an indicator of the lock condition for

proper operation. Such systems typically operate well below f_busmaxand

require fast startup. The following conditions apply when in manual

mode:

• ACQ is a writable control bit that controls the mode of the filter.

Before turning on the PLL in manual mode, the ACQ bit must be

clear.

• Before entering tracking mode (ACQ = 1), software must wait a

given time, t_acq(see Electrical Specifications on page 423), after

turning on the PLL by setting PLLON in the PLL control register

(PCTL).

• Software must wait a given time, t_al, after entering tracking mode

before selecting the PLL as the clock source to CGMOUT

(BCS = 1).

• The LOCK bit is disabled.

• CPU interrupts from the CGM are disabled.

Technical Data

124

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Functional Description

8.4.2.4 Programming the PLL

Use this 9-step procedure to program the PLL. The table below lists the

variables used and their meaning (Please also reference Figure 8-1).

Table 8-2. Variable Definitions

Variable

Definition

Desired Bus Clock Frequency

f_BUSDES

f_VCLKDES

f_CGMRCLK

f_CGMVCLK

f_BUS

Desired VCO Clock Frequency

Chosen Reference Crystal Frequency

Calculated VCO Clock Frequency

Calculated Bus Clock Frequency

Nominal VCO Center Frequency

Shifted VCO Center Frequency

f_NOM

f_CGMVRS

1. Choose the desired bus frequency, f_BUSDES

.

Example: f_BUSDES= 8 MHz

2. Calculate the desired VCO frequency, f_VCLKDES

f_VCLKDES= 4 × f_BUSDES

.

Example: f_VCLKDES= 4 × 8 MHz = 32 MHz

3. Using a reference frequency, f_RCLK, equal to the crystal frequency,

calculate the VCO frequency multiplier, N. Round the result to the

nearest integer.

f_VCLKDES

N = -------------------------

f_CGMRCLK

32 MHz

Example: N = -------------------- = 8

4 MHz

4. Calculate the VCO frequency, f_CGMVCLK

.

f_CGMVCLK= N × f_CGMRCLK

Example: f_CGMVCLK= 8 × 4 MHz = 32 MHz

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

125

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

5. Calculate the bus frequency, f_BUS, and compare f_BUSwith

f_BUSDES

.

f_CGMVCLK

f_BUS= -----------------------

4

32 MHz

Example: f_BUS= -------------------- = 8 MHz

4

6. If the calculated f_busis not within the tolerance limits of your

application, select another f_BUSDESor another f_RCLK

.

7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear

range multiplier, L. The linear range multiplier controls the

frequency range of the PLL.

f_CGMVCLK

L = round -----------------------

f_NOM

32 MHz

4.9152 MHz

Example: L =

= 7

-------------------------------

8. Calculate the VCO center-of-range frequency, f_CGMVRS. The

center-of-range frequency is the midpoint between the minimum

and maximum frequencies attainable by the PLL.

f_CGMVRS= L × f_NOM

Example: f_CGMVRS= 7 × 4.9152 MHz = 34.4 MHz

f_NOM

NOTE: For proper operation,

.

----------------

f_CGMVRS– f_CGMVCLK

≤

2

Exceeding the recommended maximum bus frequency or VCO

frequency can crash the MCU.

9. Program the PLL registers accordingly:

a. In the upper four bits of the PLL programming register (PPG),

program the binary equivalent of N.

b. In the lower four bits of the PLL programming register (PPG),

program the binary equivalent of L.

Technical Data

126

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Functional Description

8.4.2.5 Special Programming Exceptions

The programming method described in Programming the PLL on page

125, does not account for two possible exceptions. A value of 0 for N or

L is meaningless when used in the equations given. To account for these

exceptions:

• A 0 value for N is interpreted the same as a value of 1.

• A 0 value for L disables the PLL and prevents its selection as the

source for the base clock. See Base Clock Selector Circuit on

page 127.

8.4.3 Base Clock Selector Circuit

This circuit is used to select either the crystal clock, CGMXCLK, or the

VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The

two input clocks go through a transition control circuit that waits up to

three CGMXCLK cycles and three CGMVCLK cycles to change from

one clock source to the other. During this time, CGMOUT is held in

stasis. The output of the transition control circuit is then divided by two

to correct the duty cycle. Therefore, the bus clock frequency, which is

one-half of the base clock frequency, is one-fourth the frequency of the

selected clock (CGMXCLK or CGMVCLK).

The BCS bit in the PLL control register (PCTL) selects which clock drives

CGMOUT. The VCO clock cannot be selected as the base clock source

if the PLL is not turned on. The PLL cannot be turned off if the VCO clock

is selected. The PLL cannot be turned on or off simultaneously with the

selection or deselection of the VCO clock. The VCO clock also cannot

be selected as the base clock source if the factor L is programmed to a

0. This value would set up a condition inconsistent with the operation of

the PLL, so that the PLL would be disabled and the crystal clock would

be forced as the source of the base clock.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

127

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

8.4.4 CGM External Connections

In its typical configuration, the CGM requires seven external

components. Five of these are for the crystal oscillator and two are for

the PLL.

The crystal oscillator is normally connected in a Pierce oscillator

configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical

representation of the internal components and may not represent actual

circuitry. The oscillator configuration uses five components:

• Crystal, X₁

• Fixed capacitor, C₁

• Tuning capacitor, C₂(can also be a fixed capacitor)

• Feedback resistor, R_B

• Series resistor, R_S(optional)

The series resistor (R_S) may not be required for all ranges of operation,

especially with high-frequency crystals. Refer to the crystal

manufacturer’s data for more information.

Figure 8-3 also shows the external components for the PLL:

• Bypass capacitor, C_BYP

• Filter capacitor, C_F

Routing should be done with great care to minimize signal cross talk and

noise. (See Acquisition/Lock Time Specifications on page 138 for

routing information and more information on the filter capacitor’s value

and its effects on PLL performance).

Technical Data

128

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

I/O Signals

SIMOSCEN

CGMXCLK

V

DD

*

R

C

S

F

C

R

BYP

B

X

1

C

2

1

*R can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.

S

Figure 8-3. CGM External Connections

8.5 I/O Signals

The following paragraphs describe the CGM input/output (I/O) signals.

8.5.1 Crystal Amplifier Input Pin (OSC1)

The OSC1 pin is an input to the crystal oscillator amplifier.

8.5.2 Crystal Amplifier Output Pin (OSC2)

The OSC2 pin is the output of the crystal oscillator inverting amplifier.

8.5.3 External Filter Capacitor Pin (CGMXFC)

The CGMXFC pin is required by the loop filter to filter out phase

corrections. A small external capacitor is connected to this pin.

NOTE: To prevent noise problems, C_Fshould be placed as close to the

CGMXFC pin as possible with minimum routing distances and no routing

of other signals across the C_Fconnection.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

129

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

8.5.4 Analog Power Pin (V_DDA

)

V

_DDAis a power pin used by the analog portions of the PLL. Connect the

V_DDApin to the same voltage potential as the V_DDpin.

NOTE: Route V_DDAcarefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

8.5.5 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal enables the oscillator and PLL.

8.5.6 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed

of the crystal (f_CGMXCLK) and comes directly from the crystal oscillator

circuit. Figure 8-3 shows only the logical relation of CGMXCLK to OSC1

and OSC2 and may not represent the actual circuitry. The duty cycle of

CGMXCLK is unknown and may depend on the crystal and other

external factors. Also, the frequency and amplitude of CGMXCLK can be

unstable at startup.

8.5.7 CGM Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal is used to generate

the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the

bus frequency. CGMOUT is software programmable to be either the

oscillator output, CGMXCLK, divided by two or the VCO clock,

CGMVCLK, divided by two.

8.5.8 CGM CPU Interrupt (CGMINT)

CGMINT is the CPU interrupt signal generated by the PLL lock detector.

Technical Data

130

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

CGM Registers

8.6 CGM Registers

Three registers control and monitor operation of the CGM:

• PLL control register (PCTL)

• PLL bandwidth control register (PBWC)

• PLL programming register (PPG)

8.6.1 PLL Control Register

The PLL control register contains the interrupt enable and flag bits, the

on/off switch, and the base clock selector bit.

Address: $001C

Bit 7

PLLIE

0

6

5

PLLON

1

4

BCS

0

3

1

2

1

Bit 0

1

Read:

Write:

Reset:

PLLF

0

1

= Unimplemented

Figure 8-4. PLL Control Register (PCTL)

PLLIE — PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate a CPU interrupt

request when the LOCK bit toggles, setting the PLL flag, PLLF. When

the AUTO bit in the PLL bandwidth control register (PBWC) is clear,

PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE

bit.

1 = PLL CPU interrupt requests enabled

0 = PLL CPU interrupt requests disabled

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Clock Generator Module (CGM)

131

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

PLLF — PLL Flag Bit

This read-only bit is set whenever the LOCK bit toggles. PLLF

generates a CPU interrupt request if the PLLIE bit also is set. PLLF

always reads as logic 0 when the AUTO bit in the PLL bandwidth

control register (PBWC) is clear. Clear the PLLF bit by reading the

PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition

0 = No change in lock condition

NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or read-

modify-write operation on the PLL control register clears the PLLF bit.

PLLON — PLL On Bit

This read/write bit activates the PLL and enables the VCO clock,

CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the

base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit

on page 127. Reset sets this bit so that the loop can stabilize as the

MCU is powering up.

1 = PLL on

0 = PLL off

BCS — Base Clock Select Bit

This read/write bit selects either the crystal oscillator output,

CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM

output, CGMOUT. CGMOUT frequency is one-half the frequency of

the selected clock. BCS cannot be set while the PLLON bit is clear.

After toggling BCS, it may take up to three CGMXCLK and three

CGMVCLK cycles to complete the transition from one source clock to

the other. During the transition, CGMOUT is held in stasis. See Base

Clock Selector Circuit on page 127. Reset and the STOP instruction

clear the BCS bit.

1 = CGMVCLK divided by two drives CGMOUT

0 = CGMXCLK divided by two drives CGMOUT

NOTE: PLLON and BCS have built-in protection that prevents the base clock

selector circuit from selecting the VCO clock as the source of the base

clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS

is set, and BCS cannot be set when PLLON is clear. If the PLL is off

Technical Data

132

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

CGM Registers

(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control

register. See 8.4.3 on page 127.

PCTL3–PCTL0 — Unimplemented

These bits provide no function and always read as logic 1s.

8.6.2 PLL Bandwidth Control Register

The PLL bandwidth control register:

• Selects automatic or manual (software-controlled) bandwidth

control mode

• Indicates when the PLL is locked

• In automatic bandwidth control mode, indicates when the PLL is in

acquisition or tracking mode

• In manual operation, forces the PLL into acquisition or tracking

mode

Address: $001D

Bit 7

AUTO

0

6

5

ACQ

0

4

XLD

0

3

0

2

0

1

0

Bit 0

0

Read:

Write:

Reset:

LOCK

0

= Unimplemented

Figure 8-5. PLL Bandwidth Control Register (PBWC)

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

133

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

AUTO — Automatic Bandwidth Control Bit

This read/write bit selects automatic or manual bandwidth control.

When initializing the PLL for manual operation (AUTO = 0), clear the

ACQ bit before turning on the PLL. Reset clears the AUTO bit.

1 = Automatic bandwidth control

0 = Manual bandwidth control

LOCK — Lock Indicator Bit

When the AUTO bit is set, LOCK is a read-only bit that becomes set

when the VCO clock, CGMVCLK, is locked (running at the

programmed frequency). When the AUTO bit is clear, LOCK reads as

logic 0 and has no meaning. Reset clears the LOCK bit.

1 = VCO frequency correct or locked

0 = VCO frequency incorrect or unlocked

ACQ — Acquisition Mode Bit

When the AUTO bit is set, ACQ is a read-only bit that indicates

whether the PLL is in acquisition mode or tracking mode. When the

AUTO bit is clear, ACQ is a read/write bit that controls whether the

PLL is in acquisition or tracking mode.

In automatic bandwidth control mode (AUTO = 1), the last-written

value from manual operation is stored in a temporary location and is

recovered when manual operation resumes. Reset clears this bit,

enabling acquisition mode.

1 = Tracking mode

0 = Acquisition mode

XLD — Crystal Loss Detect Bit

When the VCO output, CGMVCLK, is driving CGMOUT, this

read/write bit can indicate whether the crystal reference frequency is

active or not.

1 = Crystal reference not active

0 = Crystal reference active

Technical Data

134

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

CGM Registers

To check the status of the crystal reference, do the following:

1. Write a logic 1 to XLD.

2. Wait N × 4 cycles. N is the VCO frequency multiplier.

3. Read XLD.

The crystal loss detect function works only when the BCS bit is set,

selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD

always reads as logic 0.

Bits 3–0 — Reserved for Test

These bits enable test functions not available in user mode. To ensure

software portability from development systems to user applications,

software should write 0s to bits 3–0 when writing to PBWC.

8.6.3 PLL Programming Register

The PLL programming register contains the programming information for

the modulo feedback divider and the programming information for the

hardware configuration of the VCO.

Address: $001E

Bit 7

MUL7

0

6

MUL6

1

5

MUL5

1

4

MUL4

0

3

VRS7

0

2

VRS6

1

VRS5

1

Bit 0

VRS4

0

Read:

Write:

Reset:

Figure 8-6. PLL Programming Register (PPG)

MUL7–MUL4 — Multiplier Select Bits

These read/write bits control the modulo feedback divider that selects

the VCO frequency multiplier, N. (See Circuits on page 121 and

Programming the PLL on page 125). A value of $0 in the multiplier

select bits configures the modulo feedback divider the same as a

value of $1. Reset initializes these bits to $6 to give a default multiply

value of 6.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Clock Generator Module (CGM)

135

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Table 8-3. VCO Frequency Multiplier (N) Selection

MUL7:MUL6:MUL5:MUL4

VCO Frequency Multiplier (N)

0000

0001

0010

0011

1

2

3

1101

1110

1111

13

14

15

NOTE: The multiplier select bits have built-in protection that prevents them from

being written when the PLL is on (PLLON = 1).

VRS7–VRS4 — VCO Range Select Bits

These read/write bits control the hardware center-of-range linear

multiplier L, which controls the hardware center-of-range frequency,

f_VRS. (See Circuits on page 121, Programming the PLL on page

125, and PLL Control Register on page 131.) VRS7–VRS4 cannot

be written when the PLLON bit in the PLL control register (PCTL) is

set. See Special Programming Exceptions on page 127. A value of

$0 in the VCO range select bits disables the PLL and clears the BCS

bit in the PCTL. (See Base Clock Selector Circuit on page 127 and

Special Programming Exceptions on page 127 for more

information.) Reset initializes the bits to $6 to give a default range

multiply value of 6.

NOTE: The VCO range select bits have built-in protection that prevents them

from being written when the PLL is on (PLLON = 1) and prevents

selection of the VCO clock as the source of the base clock (BCS = 1) if

the VCO range select bits are all clear.

The VCO range select bits must be programmed correctly. Incorrect

programming can result in failure of the PLL to achieve lock.

Technical Data

136

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Interrupts

8.7 Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC),

the PLL can generate a CPU interrupt request every time the LOCK bit

changes state. The PLLIE bit in the PLL control register (PCTL) enables

CPU interrupt requests from the PLL. PLLF, the interrupt flag in the

PCTL, becomes set whether CPU interrupt requests are enabled or not.

When the AUTO bit is clear, CPU interrupt requests from the PLL are

disabled and PLLF reads as logic 0.

Software should read the LOCK bit after a PLL CPU interrupt request to

see if the request was due to an entry into lock or an exit from lock. When

the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be

selected as the CGMOUT source by setting BCS in the PCTL. When the

PLL exits lock, the VCO clock frequency is corrupt, and appropriate

precautions should be taken. If the application is not frequency sensitive,

CPU interrupt requests should be disabled to prevent PLL interrupt

service routines from impeding software performance or from exceeding

stack limitations.

NOTE: Software can select the CGMVCLK divided by two as the CGMOUT

source even if the PLL is not locked (LOCK = 0). Therefore, software

should make sure the PLL is locked before setting the BCS bit.

8.8 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumption standby modes.

8.8.1 Wait Mode

The CGM remains active in wait mode. Before entering wait mode,

software can disengage and turn off the PLL by clearing the BCS and

PLLON bits in the PLL control register (PCTL). Less power-sensitive

applications can disengage the PLL without turning it off. Applications

that require the PLL to wake the MCU from wait mode also can deselect

the PLL output without turning off the PLL.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

137

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

8.8.2 Stop Mode

The STOP instruction disables the CGM and holds low all CGM outputs

(CGMXCLK, CGMOUT, and CGMINT).

If CGMOUT is being driven by CGMVCLK and a STOP instruction is

executed; the PLL will clear the BCS bit in the PLL control register,

causing CGMOUT to be driven by CGMXCLK. When the MCU recovers

from STOP, the crystal clock divided by two drives CGMOUT and BCS

remains clear.

8.9 CGM During Break Interrupts

The BCFE bit in the break flag control register (BFCR) enables software

to clear status bits during the break state. See Break Module on page

149).

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

the PLL control register during the break state without affecting the PLLF

bit.

8.10 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the

most critical PLL design parameters. Proper design and use of the PLL

ensures the highest stability and lowest acquisition/lock times.

8.10.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the

reaction time, within specified tolerances, of the system to a step input.

In a PLL, the step input occurs when the PLL is turned on or when it

suffers a noise hit. The tolerance is usually specified as a percent of the

Technical Data

138

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Acquisition/Lock Time Specifications

step input or when the output settles to the desired value plus or minus

a percent of the frequency change. Therefore, the reaction time is

constant in this definition, regardless of the size of the step input. For

example, consider a system with a 5% acquisition time tolerance. If a

command instructs the system to change from 0 Hz to 1 MHz, the

acquisition time is the time taken for the frequency to reach

1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is

operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time

is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%

of the 100-kHz step input.

Other systems refer to acquisition and lock times as the time the system

takes to reduce the error between the actual output and the desired

output to within specified tolerances. Therefore, the acquisition or lock

time varies according to the original error in the output. Minor errors may

not even be registered. Typical PLL applications prefer to use this

definition because the system requires the output frequency to be within

a certain tolerance of the desired frequency regardless of the size of the

initial error.

The discrepancy in these definitions makes it difficult to specify an

acquisition or lock time for a typical PLL. Therefore, the definitions for

acquisition and lock times for this module are:

• Acquisition time, t_acq, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the tracking mode entry tolerance, ∆_trk.

Acquisition time is based on an initial frequency error,

(f_des– f_orig)/f_des, of not more than ±100%. In automatic bandwidth

control mode (see Manual and Automatic PLL Bandwidth

Modes on page 123), acquisition time expires when the ACQ bit

becomes set in the PLL bandwidth control register (PBWC).

• Lock time, t_Lock, is the time the PLL takes to reduce the error

between the actual output frequency and the desired output

frequency to less than the lock mode entry tolerance, ∆_Lock. Lock

time is based on an initial frequency error, (f_des– f_orig)/f_des, of not

more than ±100%. In automatic bandwidth control mode, lock time

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

139

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

expires when the LOCK bit becomes set in the PLL bandwidth

control register (PBWC). (See Manual and Automatic PLL

Bandwidth Modes on page 123).

Obviously, the acquisition and lock times can vary according to how

large the frequency error is and may be shorter or longer in many cases.

8.10.2 Parametric Influences on Reaction Time

Acquisition and lock times are designed to be as short as possible while

still providing the highest possible stability. These reaction times are not

constant, however. Many factors directly and indirectly affect the

acquisition time.

The most critical parameter which affects the reaction times of the PLL

is the reference frequency, f_CGMRDV(please reference Figure 8-1 on

page 120). This frequency is the input to the phase detector and controls

how often the PLL makes corrections. For stability, the corrections must

be small compared to the desired frequency, so several corrections are

required to reduce the frequency error. Therefore, the slower the

reference the longer it takes to make these corrections. This parameter

is also under user control via the choice of crystal frequency f_CGMXCLK

.

Another critical parameter is the external filter capacitor. The PLL

modifies the voltage on the VCO by adding or subtracting charge from

this capacitor. Therefore, the rate at which the voltage changes for a

given frequency error (thus a change in charge) is proportional to the

capacitor size. The size of the capacitor also is related to the stability of

the PLL. If the capacitor is too small, the PLL cannot make small enough

adjustments to the voltage and the system cannot lock. If the capacitor

is too large, the PLL may not be able to adjust the voltage in a

reasonable time. See Choosing a Filter Capacitor on page 141.

Also important is the operating voltage potential applied to V_DDA. The

power supply potential alters the characteristics of the PLL. A fixed value

is best. Variable supplies, such as batteries, are acceptable if they vary

within a known range at very slow speeds. Noise on the power supply is

not acceptable, because it causes small frequency errors which

continually change the acquisition time of the PLL.

Technical Data

140

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Acquisition/Lock Time Specifications

Temperature and processing also can affect acquisition time because

the electrical characteristics of the PLL change. The part operates as

specified as long as these influences stay within the specified limits.

External factors, however, can cause drastic changes in the operation of

the PLL. These factors include noise injected into the PLL through the

filter capacitor, filter capacitor leakage, stray impedances on the circuit

board, and even humidity or circuit board contamination.

8.10.3 Choosing a Filter Capacitor

As described in Parametric Influences on Reaction Time on page

140, the external filter capacitor, C_F, is critical to the stability and reaction

time of the PLL. The PLL is also dependent on reference frequency and

supply voltage. The value of the capacitor must, therefore, be chosen

with supply potential and reference frequency in mind. For proper

operation, the external filter capacitor must be chosen according to this

equation:

V_DDA

C_F= C_fact------------------

f

CGMRDV

For acceptable values of C_fact, (see Electrical Specifications on page

423). For the value of V_DDA, choose the voltage potential at which the

MCU is operating. If the power supply is variable, choose a value near

the middle of the range of possible supply values.

This equation does not always yield a commonly available capacitor

size, so round to the nearest available size. If the value is between two

different sizes, choose the higher value for better stability. Choosing the

lower size may seem attractive for acquisition time improvement, but the

PLL may become unstable. Also, always choose a capacitor with a tight

tolerance (±20% or better) and low dissipation.

8.10.4 Reaction Time Calculation

The actual acquisition and lock times can be calculated using the

equations below. These equations yield nominal values under the

following conditions:

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

141

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

• Correct selection of filter capacitor, C_F(see Choosing a Filter

Capacitor on page 141).

• Room temperature operation

• Negligible external leakage on CGMXFC

• Negligible noise

The K factor in the equations is derived from internal PLL parameters.

K_acqis the K factor when the PLL is configured in acquisition mode, and

K_trkis the K factor when the PLL is configured in tracking mode. (See

Acquisition and Tracking Modes on page 123).

V_DDA

t_acq= ------------------- ------------

f_CGMRDVK_ACQ

8

V_DDA

4

t_al= ------------------- -----------

f_CGMRDVK_TRK

t_Lock= t_ACQ+ t_AL

Note the inverse proportionality between the lock time and the reference

frequency.

In automatic bandwidth control mode, the acquisition and lock times are

quantized into units based on the reference frequency. (See Manual

and Automatic PLL Bandwidth Modes on page 123). A certain

number of clock cycles, n_ACQ, is required to ascertain that the PLL is

within the tracking mode entry tolerance, ∆_TRK, before exiting acquisition

mode. A certain number of clock cycles, n_TRK, is required to ascertain

that the PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the

acquisition time, t_ACQ, is an integer multiple of n_{ACQ CGMRDV}

acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_CGMRDV

/f

, and the

. Also,

since the average frequency over the entire measurement period must

be within the specified tolerance, the total time usually is longer than

t_Lockas calculated above.

Technical Data

142

MC68HC08AZ32A — Rev 1.0

Clock Generator Module (CGM)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Acquisition/Lock Time Specifications

In manual mode, it is usually necessary to wait considerably longer than

t

_Lockbefore selecting the PLL clock (see Base Clock Selector Circuit

on page 127), because the factors described in Parametric Influences

on Reaction Time on page 140, may slow the lock time considerably.

When defining a limit in software for the maximum lock time, the value

must allow for variation due to all of the factors mentioned in this section,

especially due to the C_Fcapacitor and application specific influences.

The calculated lock time is only an indication and it is the customer’s

responsibility to allow enough of a guard band for their application. Prior

to finalizing any software and while determining the maximum lock time,

take into account all device to device differences. Typically, applications

set the maximum lock time as an order of magnitude higher than the

measured value. This is considered sufficient for all such device to

device variation.

Motorola recommends measuring the lock time of the application system

by utilizing dedicated software, running in FLASH, EEPROM or RAM.

This should toggle a port pin when the PLL is first configured and

switched on, then again when it goes from acquisition to lock mode and

finally again when the PLL lock bit is set. The resultant waveform can be

captured on an oscilloscope and used to determine the typical lock time

for the microcontroller and the associated external application circuit.

e.g.

t_LOCK

t_ACQ

t_AL

Init. low

Signal on port pin

t_TRKComplete and Lock Set

t_ACQComplete

PLL Configured and switched on

NOTE: The filter capacitor should be fully discharged prior to making any

measurements.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

143

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Clock Generator Module (CGM)

Technical Data

144

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Clock Generator Module (CGM)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 9. Mask Options

9.1 Contents

9.2

9.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.2 Introduction

This section describes the mask options and the mask option registers.

The mask options are hardwired connections specified at the same time

as the ROM code, which allow the user to customize the MCU. The

options control the enable or disable of the following functions:

• Resets caused by the LVI module

• Power to the LVI module

• Stop mode recovery time (32 CGMXCLK cycles or 4096

CGMXCLK cycles)

• ROM security⁽¹⁾

• STOP instruction

• Computer operating properly (COP) module enable

• EEPROM read protection⁽¹⁾

• COP time-out period

• EEPROM reference clock source

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the ROM/EEPROM data difficult for unauthorized users

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

145

Mask Options

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mask Options

9.3 Functional Description

Bit 7

6

5

4

3

2

1

Bit 0

COPD

R

Read: LVISTOP ROMSEC LVIRST LVIPWR SSREC COPRS STOP

MORA

$001F

Write:

R

Reset:

Unaffected by reset

Figure 9-1. Mask Option Register A (MORA)

LVISTOP — LVI Stop Mode Enable Bit

LVISTOP enables the LVI module in stop mode. See Low Voltage

Inhibit (LVI) on page 173.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

ROMSEC — ROM Security Bit

ROMSEC enables the ROM security feature. Setting the ROMSEC bit

prevents access to the ROM contents.

1 = ROM security enabled

0 = ROM security disabled

LVIRST — LVI Reset Enable Bit

LVIRST enables the reset signal from the LVI module. See Low

Voltage Inhibit (LVI) on page 173.

1 = LVI module resets enabled

0 = LVI module resets disabled

LVIPWR — LVI Power Enable Bit

LVIPWR enables the LVI module. See Low Voltage Inhibit (LVI) on

page 173.

1 = LVI module power enabled

0 = LVI module power disabled

Technical Data

146

MC68HC08AZ32A — Rev 1.0

Mask Options

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mask Options

Functional Description

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32

CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.

1 = STOP mode recovery after 32 CGMXCLK cycles

0 = STOP mode recovery after 4096 CGMXCLK cycles

If using an external crystal oscillator, the SSREC bit should not be set.

COPRS — COP Rate Select

COPRS is similar to COPL (please note that the logic is reversed) as

it determines the timeout period for the COP.

1 = COP timeout period is 2¹³— 2⁴CGMXCLK cycles.

0 = COP timeout period is 2¹⁸— 2⁴CGMXCLK cycles.

STOP — STOP Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module. See Computer Operating

Properly (COP) on page 167.

1 = COP module disabled

0 = COP module enabled

NOTE: Extra care should be taken when selecting MOR options since not all

HC08 family devices have the same options. In particular refer to the

appendix on differences of previous versions of MC68HC08AZ32. It is

the user’s responsibility to correctly define the mask option registers.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

147

Mask Options

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Mask Options

Bit 7

6

5

4

3

2

1

Bit 0

Read: EEDIVCLK

EESEC EEMONSEC AZ32A

MORB

$FE09

R

Write:

R

Reset:

Unaffected by reset

= Reserved

= Unimplemented

R

Figure 9-2. Mask Option Register B (MORB)

EEDIVCLK — EEPROM Timebase Divider Clock Select Bit

EEDIVCLK selects the reference clock source for the EEPROM

timebase divider. See EEPROM Timebase Divider Register on

page 72.

1 = CPU bus clock drives the EEPROM timebase divider

0 = CGMXCLK drives the EEPROM timebase divider

EESEC — This read/write bit has no function.

1 = N/A

0 = N/A

EEMONSEC — EEPROM Read Protection in Monitor Mode Bit

When EEMONSEC is set the entire EEPROM aray cannot be

acessed in monitor mode unless a valid security code is entered.

1 = EEPROM read protection in monitor mode enabled.

0 = EEPROM read protection in monitor mode disabled.

AZ32A — Device Indicator

This bit is used to distinguish a MC68HC08AZ32A from older non-’A’

suffix versions

1 = ‘A’ version

0 = Non-’A’ version

Extra care should be exercised when selecting mask option

registers since other HC08 family parts may have different options.

If in doubt, check with your local field applications representative.

Technical Data

148

MC68HC08AZ32A — Rev 1.0

Mask Options

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 10. Break Module

10.1 Contents

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . .151

10.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . .152

10.4.3 TIM and PIT During Break Interrupts . . . . . . . . . . . . . . .152

10.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . .152

10.5 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .152

10.5.1 Break Status and Control Register (BRKSCR) . . . . . . .153

10.5.2 Break Address Registers (BRKH and BRKL) . . . . . . . .154

10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

10.2 Introduction

10.3 Features

This section describes the break module. The break module can

generate a break interrupt which stops normal program flow at a defined

address in order to begin execution of a background program.

Features of the break module include the following:

• Accessible I/O registers during the break interrupt

• CPU-generated break Interrupts

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

149

Break Module

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Break Module

• Software-generated break interrupts

• COP disabling during break interrupts

10.4 Functional Description

When the internal address bus matches the value written in the break

address registers, the break module issues a breakpoint signal (BKPT)

to the SIM. The SIM then causes the CPU to load the instruction register

with a software interrupt instruction (SWI) after completion of the current

CPU instruction. The program counter vectors to $FFFC and $FFFD

($FEFC and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

• A CPU-generated address (the address in the program counter)

matches the contents of the break address registers.

• Software writes a ‘1’ to the BRKA bit in the break status and

control register (BRKSCR).

When a CPU-generated address matches the contents of the break

address registers, the break interrupt begins after the CPU completes its

current instruction. A return from interrupt instruction (RTI) in the break

routine ends the break interrupt and returns the MCU to normal

operation. Figure 10-1 shows the structure of the break module.

Technical Data

150

MC68HC08AZ32A — Rev 1.0

Break Module

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Break Module

Functional Description

IAB[15:8]

BREAK ADDRESS REGISTER HIGH

8-BIT COMPARATOR

IAB[15:0]

CONTROL

BKPT

(TO SIM)

8-BIT COMPARATOR

BREAK ADDRESS REGISTER LOW

IAB[7:0]

Figure 10-1. Break Module Block Diagram

Table 10-1. Break I/O Register Summary

Register Name

Bit 7

Bit 15

Bit 7

6

14

6

5

13

5

4

12

4

3

11

3

2

10

2

1

9

1

0

Bit 0 Addr.

Bit 8 $FE0C

Bit 0 $FE0D

Break Address Register High (BRKH)

Break Address Register Low (BRKL)

0

reak Status/Control Register (BRKSCR)

BRKE BRKA

$FE0E

= Unimplemented

10.4.1 Flag Protection During Break Interrupts

The system integration module (SIM) controls whether or not module

status bits can be cleared during the break state. The BCFE bit in the

SIM break flag control register (SBFCR) enables software to clear status

bits during the break state. See System Integration Module (SIM) on

page 95, and the Break Interrupts subsection for each module.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

151

Break Module

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Break Module

10.4.2 CPU During Break Interrupts

The CPU starts a break interrupt by:

• Loading the instruction register with the SWI instruction

• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD

in monitor mode)

The break interrupt begins after completion of the CPU instruction in

progress. If the break address register match occurs on the last cycle of

a CPU instruction, the break interrupt begins immediately.

10.4.3 TIM and PIT During Break Interrupts

A break interrupt stops the timer counter.

10.4.4 COP During Break Interrupts

The COP is disabled during a break interrupt when V_HIis present on the

RST pin.

10.5 Break Module Registers

Three registers control and monitor operation of the break module:

• Break status and control register (BRKSCR)

• Break address register high (BRKH)

• Break address register low (BRKL)

Technical Data

152

MC68HC08AZ32A — Rev 1.0

Break Module

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Break Module

Break Module Registers

10.5.1 Break Status and Control Register (BRKSCR)

The break status and control register contains break module enable and

status bits.

Bit 7

BRKE

0

6

BRKA

0

5

4

3

2

1

Bit 0

0

Read:

Write:

Reset:

0

BRKSCR

$FE0E

0

= Unimplemented

Figure 10-2. Break Status and Control Register (BRKSCR)

BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches.

BRKE is cleared by writing a ‘0’ to bit 7. Reset clears the BRKE bit.

1 = Breaks enabled on 16-bit address match

0 = Breaks disabled on 16-bit address match

BRKA — Break Active Bit

This read/write status and control bit is set when a break address

match occurs. Writing a ‘1’ to BRKA generates a break interrupt.

BRKA is cleared by writing a ‘0’ to it before exiting the break routine.

Reset clears the BRKA bit.

1 = Break address match

0 = No break address match

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

153

Break Module

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Break Module

10.5.2 Break Address Registers (BRKH and BRKL)

The break address registers contain the high and low bytes of the

desired breakpoint address. Reset clears the break address registers.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

BRKH

$FE0C

Bit 15

14

13

12

11

10

9

Bit 8

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 7

Bit 0

Read:

Write:

Reset:

BRKL

$FE0D

Bit 7

0

6

0

5

0

4

0

3

0

2

0

1

0

Bit 0

0

Figure 10-3. Break Address Registers (BRKH and BRKL)

10.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low-power-

consumption standby modes.

10.6.1 Wait Mode

If enabled, the break module is active in wait mode. The SIM break wait

bit (BW) in the SIM break status register indicates whether wait was

exited by a break interrupt. If so, the user can modify the return address

on the stack by subtracting one from it. (See System Integration

Module (SIM) on page 95).

10.6.2 Stop Mode

The break module is inactive in stop mode. The STOP instruction does

not affect break module register states.

Technical Data

154

MC68HC08AZ32A — Rev 1.0

Break Module

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 11. Monitor ROM (MON)

11.1 Contents

11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

11.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

11.4.1 Entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . .158

11.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

11.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

11.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

11.4.4.1

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

11.4.5 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

11.4.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

11.2 Introduction

11.3 Features

This section describes the monitor ROM (MON08). The monitor ROM

allows complete testing of the MCU through a single-wire interface with

a host computer.

Features of the monitor ROM include the following:

• Normal User-Mode Pin Functionality

• One Pin Dedicated to Serial Communication Between Monitor

ROM and Host Computer

• Standard Mark/Space Non-Return-to-Zero (NRZ) Communication

with Host Computer

• Up to 28.8K Baud Communication with Host Computer

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

155

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

• Execution of Code in RAM or ROM

• EEPROM Programming

• ROM Security (Read Protection)⁽¹⁾

• EEPROM Read Protection⁽¹⁾

11.4 Functional description

The monitor ROM receives and executes commands from a host

computer. Figure 11-1 shows a sample circuit used to enter monitor

mode and communicate with a host computer via a standard RS-232

interface.

While simple monitor commands can access any memory address, the

MC68HC08AZ32A has optional ROM/EEPROM read protection

features to prevent external viewing of the contents of ROM/EEPROM

(see Mask Options on page 145). Proper procedures must be followed

to verify ROM/EEPROM content. Access to the ROM/EEPROM is

denied to unauthorized users of customer specified software with read

protection features enabled. See Security on page 164.

In monitor mode, the MCU can execute host-computer code in RAM

while all MCU pins except PTA0 retain normal operating mode functions.

All communication between the host computer and the MCU is through

the PTA0 pin. A level-shifting and multiplexing interface is required

between PTA0 and the host computer. PTA0 is used in a wired-OR

configuration and requires a pull-up resistor.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the ROM/EEPROM data difficult for unauthorized users

Technical Data

156

MC68HC08AZ32A — Rev 1.0

Monitor ROM (MON)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Functional description

V_DD

68HC08

10 kΩ

RST

0.1 µF

V

HI

1 KΩ

IRQ

9.1V

V_DDA

CGMXFC

0.1 µF

10 MΩ

1

20

MC145407

+

10 µF

OSC1

OSC2

3

4

18

17

20 pF

X1

4.9152 MHz

20 pF

V

2

19

SSA

V_SS

DB-25

2

5

6

16

15

3

7

V_DD

0.1 µF

V_DD

14

V_DD

1

2

6

4

MC68HC125

10 kΩ

3

5

PTA0

PTC3

V_DD

10 kΩ

7

10 kΩ

A

PTC0

PTC1

(See

NOTE.)

B

NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4

Position B — Bus clock = CGMXCLK ÷ 2

Figure 11-1. Monitor Mode Circuit

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

157

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

11.4.1 Entering monitor mode

Table 11-1 shows the pin conditions for entering monitor mode.

Table 11-1. Mode Selection

Bus

Frequency

Mode

CGMOUT

CGMXCLK

CGMVCLK

CGMOUT

--------------------------

2

(1)

1

0

1

0

Monitor

----------------------------- or -----------------------------

V_HI

2

CGMOUT

--------------------------

2

CGMXCLK

1. For V_HI, 5.0 Volt DC Electrical Characteristics on page 426, and Maximum Ratings on page 424.

Enter monitor mode by either

• Executing a software interrupt instruction (SWI) or

• Applying a ‘0’ and then a ‘1’ to the RST pin.

Once out of reset, the MCU waits for the host to send eight security bytes

(see Security on page 164). After the security bytes, the MCU sends a

break signal (10 consecutive ‘0’s) to the host computer, indicating that it

is ready to receive a command.

Monitor mode uses alternate vectors for reset, SWI, and break interrupt.

The alternate vectors are in the $FE page instead of the $FF page and

allow code execution from the internal monitor firmware instead of user

code. The COP module is disabled in monitor mode as long as V_HI(see

Electrical Specifications on page 423), is applied to either the IRQ pin

or the RST pin. See System Integration Module (SIM) on page 95 for

more information on modes of operation.

NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass

of a divide-by-two stage at the oscillator. The CGMOUT frequency is

equal to the CGMXCLK frequency, and the OSC1 input directly

generates internal bus clocks. In this case, the OSC1 signal must have

a 50% duty cycle at maximum bus frequency.

Technical Data

158

MC68HC08AZ32A — Rev 1.0

Monitor ROM (MON)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Functional description

Table 11-2 is a summary of the differences between user mode and

monitor mode.

Table 11-2. Mode Differences

Functions

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

Modes

COP

User

Enabled

$FFFE

$FEFE

$FFFF

$FEFF

$FFFC

$FEFC

$FFFD

$FEFD

$FFFC

$FEFC

$FFFD

$FEFD

Disabled⁽¹⁾

Monitor

1. If the high voltage (V_HI) is removed from the IRQ and/or RESET pin while in monitor mode, the SIM as-

serts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration reg-

ister. See 5.0 Volt DC Electrical Characteristics on page 426.

11.4.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. (See Figure 11-2 and Figure 11-3).

BIT

START

BIT

STOP

BIT

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

Figure 11-2. Monitor Data Format

BIT

START

STOP

$A5

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT

STOP

BIT

START

BIT

BREAK

BIT 0

Figure 11-3. Sample Monitor Waveforms

The data transmit and receive rate can be anywhere up to 28.8 KBaud.

Transmit and receive baud rates must be identical.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

159

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

11.4.3 Echoing

The monitor ROM immediately echoes each received byte back to the

PTA0 pin for error checking, as shown in Figure 11-4.

SENT TO

MONITOR

ADDR. LOW

READ

ADDR. HIGH ADDR. HIGH

DATA

ADDR. LOW

ECHO

RESULT

Figure 11-4. Read Transaction

Any result of a command appears after the echo of the last byte of the

command.

11.4.4 Break Signal

A break signal is a start bit followed by nine low bits. This is shown in

Figure 11-4. When the monitor receives a break signal, it drives the

PTA0 pin high for the duration of two bits before echoing the break

signal.

MISSING STOP BIT

TWO-STOP-BIT DELAY BEFORE ZERO ECHO

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Figure 11-5. Break Transaction

Technical Data

160

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Functional description

11.4.4.1 Commands

The monitor ROM uses the following commands:

• READ (read memory)

• WRITE (write memory)

• IREAD (indexed read)

• IWRITE (indexed write)

• READSP (read stack pointer)

• RUN (run user program)

Table 11-3. READ (Read Memory) Command

Description

Operand

Read byte from memory

Specifies 2-byte address in high byte:low byte order

Returns contents of specified address

$4A

Data returned

Opcode

Command sequence

SENT TO

MONITOR

READ

ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW

DATA

ECHO

RESULT

Table 11-4. WRITE (Write Memory) Command

Description

Write byte to memory

Operand

Specifies 2-byte address in high byte:low byte order; low byte followed by data byte

Data returned

Opcode

None

$49

Command sequence

SENT TO

MONITOR

WRITE

ECHO

WRITE

ADDR. HIGH

ADDR. LOW ADDR. LOW

DATA

ADDR. HIGH

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

161

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Table 11-5. IREAD (Indexed Read) Command

Description

Operand

Read next 2 bytes in memory from last address accessed

Specifies 2-byte address in high byte:low byte order

Returns contents of next two addresses

$1A

Data returned

Opcode

Command sequence

SENT TO

MONITOR

IREAD

DATA

RESULT

ECHO

Table 11-6. IWRITE (Indexed Write) Command

Description

Operand

Write to last address accessed + 1

Specifies single data byte

Data returned

Opcode

None

$19

Command sequence

SENT TO

MONITOR

IWRITE

DATA

ECHO

Technical Data

162

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Functional description

A sequence of IREAD or IWRITE commands can sequentially access a

block of memory over the full 64K byte memory map.

Table 11-7. READSP (Read Stack Pointer) Command

Description

Operand

Reads stack pointer

None

Data returned

Opcode

Returns stack pointer in high byte:low byte order

$0C

Command sequence

SENT TO

MONITOR

READSP

SP HIGH

SP LOW

RESULT

ECHO

Table 11-8. RUN (Run User Program) Command

Description

Operand

Executes RTI instruction

None

$28

Data returned

Opcode

Command sequence

SENT TO

MONITOR

RUN

ECHO

11.4.5 Baud Rate

The MC68HC08AZ32A features a monitor mode which is optimised to

operate with either a 4.9152MHz crystal clock source (or multiples of

4.9152MHz) or a 4MHz crystal (or multiples of 4MHz). This supports

designs which use the MSCAN08 module, which is generally clocked

from a 4MHz, 8MHz or 16MHz internal reference clock. The table below

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

163

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

outlines the available baud rates for a range of crystals and how they can

match to a PC baud rate.

Baud rate

Closest PC baud PC

Error %

Clock freq

32kHz

PTC3=0

PTC3=1

28.98

PTC3=0

57.6

PTC3=1

28.8

PTC3=0 PTC3=1

57.97

1811.59

3623.19

7246.37

7597.83

8904.35

14492.72

0.64

1.08

0.49

0.64

0.63

0.64

1.08

0.50

0.64

1MHz

905.80

1800

900

2MHz

1811.59

3623.19

3798.91

4452.17

7246.37

3600

1800

3600

3840

4430

7200

14400

4MHz

7200

4.194MHz

4.9152MHz

8MHz

7680

8861

14400

28800

16MHz

28985.51 14492.75

Care should be taken when setting the baud rate since incorrect

baud rate setting can result in communications failure.

11.4.6 Security

Security features discourage unauthorized reading of ROM/EEPROM

locations while in monitor mode. The host can bypass the security

features at monitor mode entry by sending eight security bytes that

match the byte locations $FFF6–$FFFD. Locations $FFF6–$FFFD

contain user-defined data.

NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, enter

data at locations $FFF6–$FFFD even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for

the host to send the eight security bytes on pin PA0.

If the received bytes match those at locations $FFF6–$FFFD, the host

bypasses the security features and can read all ROM/EEPROM

locations and execute code from ROM. Security remains bypassed until

a power-on reset occurs. After the host bypasses security, any reset

other than a power-on reset requires the host to send another eight

Technical Data

164

MC68HC08AZ32A — Rev 1.0

Monitor ROM (MON)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Functional description

bytes. If the reset was not a power-on reset, security remains bypassed

regardless of the data that the host sends.

If the received bytes do not match the data at locations $FFF6–$FFFD,

the host fails to bypass the security features. The MCU remains in

monitor mode, but reading ROM/EEPROM locations returns undefined

data, and trying to execute code from ROM causes an illegal address

reset. After the host fails to bypass security, any reset other than a

power-on reset causes an endless loop of illegal address resets.

After receiving the eight security bytes from the host, the MCU transmits

a break character signalling that it is ready to receive a command.

NOTE: The MCU does not transmit a break character until after the host sends

the eight security bytes.

V

DD

4096 + 32 CGMXCLK CYCLES

RST

24 BUS CYCLES (MINIMUM)

FROM HOST

FROM MCU

PA0

1

4

1

4

2

1

NOTE: 1 = Echo delay (2 bit times)

2 = Data return delay (2 bit times)

4 = Wait 1 bit time before sending next byte.

Figure 11-6. Monitor Mode Entry Timing

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

165

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Monitor ROM (MON)

Technical Data

166

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 12. Computer Operating Properly (COP)

12.1 Contents

12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

12.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

12.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

12.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

12.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

12.4.3 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12.4.7 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

12.4.8 COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .170

12.5 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . .171

12.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.8.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

12.8.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

12.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . .172

12.2 Introduction

This section describes the computer operating properly (COP) module,

a free-running counter that generates a reset if allowed to overflow. The

COP module helps software recover from runaway code. COP resets

can be prevented by periodically clearing the COP counter.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

167

Computer Operating Properly (COP)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Computer Operating Properly (COP)

12.3 Functional Description

Figure 12-1 shows the structure of the COP module.

12-BIT COP PRESCALER

CGMXCLK

STOP INSTRUCTION

INTERNAL RESET SOURCES

RESET VECTOR FETCH

COPCTL WRITE

RESET

RESET STATUS

REGISTER

6-BIT COP COUNTER

COPD FROM MORA

RESET

CLEAR COP

COUNTER

COPCTL WRITE

COPRS FROM MORA

Figure 12-1. COP Block Diagram

Table 12-1. COP I/O Register Summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

COP Control Register (COPCTL)

$FFFF

The COP counter is a free-running 6-bit counter preceded by a12-bit

prescaler. If not cleared by software, the COP counter overflows and

generates an asynchronous reset after 2¹³– 2⁴, or 2¹⁸– 2⁴CGMXCLK

cycles, depending on the state of the COP rate select bit, COPRS in

Technical Data

168

MC68HC08AZ32A — Rev 1.0

Computer Operating Properly (COP)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Computer Operating Properly (COP)

I/O Signals

MORA. When COPRS = 0, a 4.9152 MHz crystal, gives a COP timeout

period of 53.3ms. Writing any value to location $FFFF before overflow

occurs prevents a COP reset by clearing the COP counter and stages 4

through 12 of the prescaler.

NOTE: Service the COP immediately after reset and before entering or after

exiting stop mode to guarantee the maximum time before the first COP

counter overflow.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the

COP bit in the SIM reset status register (SRSR). See SIM Reset Status

Register (SRSR) on page 114.

In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held

at V_Hi. During the break state, V_Hion the RST pin disables the COP.

NOTE: Place COP clearing instructions in the main program and not in an

interrupt subroutine. Such an interrupt subroutine could keep the COP

from generating a reset even while the main program is not working

properly.

12.4 I/O Signals

The following paragraphs describe the signals shown in Figure 12-1.

12.4.1 CGMXCLK

CGMXCLK is the crystal oscillator output signal. The CGMXCLK

frequency is equal to the crystal frequency.

12.4.2 STOP Instruction

The STOP instruction clears the COP prescaler.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

169

Computer Operating Properly (COP)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Computer Operating Properly (COP)

12.4.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see COP

Control Register (COPCTL) on page 171), clears the COP counter and

clears bits 12 – 4 of the COP prescaler. Reading the COP control

register returns the reset vector.

12.4.4 Power-On Reset

The power-on reset (POR) circuit clears the COP prescaler 4096

CGMXCLK cycles after power-up.

12.4.5 Internal Reset

An internal reset clears the COP prescaler and the COP counter.

12.4.6 Reset Vector Fetch

A reset vector fetch occurs when the vector address appears on the data

bus. A reset vector fetch clears the COP prescaler.

12.4.7 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the

mask option register (MORA). See Mask Options on page 145.

12.4.8 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit, COPRS

in the MORA register (see Figure 9-1 on page 146).

Technical Data

170

MC68HC08AZ32A — Rev 1.0

Computer Operating Properly (COP)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Computer Operating Properly (COP)

COP Control Register (COPCTL)

12.5 COP Control Register (COPCTL)

The COP control register is located at address $FFFF and overlaps the

reset vector. Writing any value to $FFFF clears the COP counter and

starts a new timeout period. Reading location $FFFF returns the low

byte of the reset vector.

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Low byte of reset vector

Clear COP counter

Unaffected by reset

COPCTL

$FFFF

Figure 12-2. COP Control Register (COPCTL)

12.6 Interrupts

The COP does not generate CPU interrupt requests.

12.7 Monitor Mode

The COP is disabled in monitor mode when V_HIis present on the IRQ pin

or on the RST pin.

12.8 Low-Power Modes

The WAIT and STOP instructions put the MCU in low-power-

consumption standby modes.

12.8.1 WAIT Mode

The COP continues to operate during WAIT mode. To prevent a COP

reset during WAIT mode, the COP counter should be cleared

periodically in a CPU interrupt routine.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

171

Computer Operating Properly (COP)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Computer Operating Properly (COP)

12.8.2 STOP Mode

STOP mode turns off the CGMXCLK input to the COP and clears the

COP prescaler. The COP should be serviced immediately before

entering or after exiting STOP mode to ensure a full COP timeout period

after entering or exiting STOP mode.

The STOP bit in the mask option register (MOR) enables the STOP

instruction. To prevent inadvertently turning off the COP with a STOP

instruction, the STOP instruction should be disabled by programming the

STOP bit to ‘0’.

12.9 COP Module During Break Interrupts

The COP is disabled during a break interrupt when V_HIis present on the

RST pin.

Technical Data

172

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Computer Operating Properly (COP)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 13. Low Voltage Inhibit (LVI)

13.1 Contents

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

13.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

13.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

13.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

13.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . .175

13.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . .176

13.5 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . .176

13.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

13.7.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

13.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

13.2 Introduction

13.3 Features

This section describes the low-voltage inhibit module, which monitors

the voltage on the V_DDpin and can force a reset when the V_DDvoltage

falls to the LVI trip voltage.

Features of the LVI module include the following:

• Programmable LVI reset

• Programmable power consumption

• Digital filtering of VDD pin level

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

173

Low Voltage Inhibit (LVI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Low Voltage Inhibit (LVI)

NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM

memory, then adequate programming time may not have been allowed

to ensure the integrity and retention of the data. It is the responsibility of

the user to ensure that in the event of an LVI any addresses being

programmed receive specification programming conditions.

13.4 Functional Description

Figure 13-1 shows the structure of the LVI module. The LVI is enabled

out of reset. The LVI module contains a bandgap reference circuit and

comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V_DD

voltage. The LVI reset bit, LVIRST, enables the LVI module to generate

a reset when V_DDfalls below a voltage, LVI_TRIPF, and remains at or below

that level for 9 or more consecutive CPU cycles.

Note that short V_DDspikes may not trip the LVI. It is the user’s

responsibility to ensure a clean V_DDsignal within the specified

operating voltage range if normal microcontroller operation is to be

guaranteed.

LVISTOP enables the LVI module during stop mode. This will ensure

when the STOP instruction is implemented the LVI will continue to

monitor the voltage level on V_DD.

LVIPWR, LVIRST and LVISTOP are mask options. See Mask Options

on page 145. Once an LVI reset occurs, the MCU remains in reset until

V_DDrises above a voltage, LVI_TRIPR. V_DDmust be above LVI_TRIPRfor only

one CPU cycle to bring the MCU out of reset. The output of the

comparator controls the state of the LVIOUT flag in the LVI status

register (LVISR).

Technical Data

174

MC68HC08AZ32A — Rev 1.0

Low Voltage Inhibit (LVI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Low Voltage Inhibit (LVI)

Functional Description

An LVI reset also drives the RST pin low to provide low-voltage

protection to external peripheral devices.

V

DD

LVIPWR

FROM MORA

CPU CLOCK

LVIRST

V

_DD> LVI_TRIP= 0

DD

LVI RESET

LOW V

DD

DIGITAL FILTER

DETECTOR

V_DD< LVI_TRIP= 1

Stop Mode

Filter Bypass

ANLGTRIP

LVIOUT

LVISTOP

FROM MORA

Figure 13-1. LVI Module Block Diagram

Table 13-1. LVI I/O Register Summary

Register Name

Bit 7

6

5

4

3

2

1

Bit 0 Addr.

$FE0F

LVI Status Register (LVISR) LVIOUT

= Unimplemented

13.4.1 Polled LVI Operation

In applications that can operate at V_DDlevels below the LVI_TRIPFlevel,

software can monitor V_DDby polling the LVIOUT bit. In the mask option

register, the LVIPWR bit must be at logic ‘1’ to enable the LVI module

and the LVIRST bit must be at logic ‘0’ to disable LVI resets.

13.4.2 Forced Reset Operation

In applications that require V_DDto remain above the LVI_TRIPFlevel,

enabling LVI resets allows the LVI module to reset the MCU when V_DD

falls to the LVI_TRIPFlevel and remains at or below that level for 9 or more

consecutive CPU cycles. In the mask option register, the LVIPWR and

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

175

Low Voltage Inhibit (LVI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Low Voltage Inhibit (LVI)

LVIRST bits must be at ‘1’ to enable the LVI module and to enable LVI

resets.

13.4.3 False Reset Protection

The V_DDpin level is digitally filtered to reduce false resets due to power

supply noise. In order for the LVI module to reset the MCU,V_DDmust

remain at or below the LVI_TRIPFlevel for 9 or more consecutive CPU

cycles. V_DDmust be above LVI_TRIPRfor only one CPU cycle to bring the

MCU out of reset.

13.5 LVI Status Register (LVISR)

The LVI status register flags V_DDvoltages below the LVI_TRIPFlevel.

Bit 7

Read: LVIOUT

Write:

6

5

4

3

2

1

Bit 0

0

LVISR

$FE0F

Reset:

0

= Unimplemented

Figure 13-2. LVI Status Register (LVISR)

LVIOUT — LVI Output Bit

This read-only flag becomes set when V_DDfalls below the LVI_TRIPF

voltage for 32-40 CGMXCLK cycles. (See Table 13-2). Reset clears

the LVIOUT bit.

Technical Data

176

MC68HC08AZ32A — Rev 1.0

Low Voltage Inhibit (LVI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Low Voltage Inhibit (LVI)

LVI Interrupts

Table 13-2. LVIOUT Bit Indication

V_DD

for number of CGMXCLK

cycles:

LVIOUT

at level:

V_DD> LVI_TRIPR

ANY

0

V

_DD< LVI_TRIPF

< 32 CGMXCLK cycles

between 32 & 40 CGMXCLK

cycles

0 or 1

> 40 CGMXCLK cycles

1

LVI_TRIPF< V_DD< LVI_TRIPR

ANY

Previous Value

13.6 LVI Interrupts

The LVI module does not generate interrupt requests.

13.7 Low-Power Modes

The WAIT instruction puts the MCU in low-power-consumption standby

mode.

13.7.1 WAIT Mode

When the LVIPWR mask option is programmed to ‘1’, the LVI module is

active after a WAIT instruction.

When the LVIRST mask option is programmed to ‘1’, the LVI module can

generate a reset and bring the MCU out of WAIT mode.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

177

Low Voltage Inhibit (LVI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Low Voltage Inhibit (LVI)

13.7.2 Stop Mode

With LVISTOP=1 and LVIPWR=1 in the MORA register, the LVI module

will be active after a STOP instruction. Because CPU clocks are disabled

during stop mode, the LVI trip must bypass the digital filter to generate a

reset and bring the MCU out of stop.

With the LVIPWR bit in the MORA register at a logic 1 and the LVISTOP

bit at a logic 0, the LVI module will be inactive after a STOP instruction.

Note that the LVI feature is intended to provide the safe shutdown

of the microcontroller and thus protection of related circuitry prior

to any application V_DDvoltage collapsing completely to an unsafe

level. Is is not intended that users operate the microcontroller at

lower than the specified operating voltage, V_DD

.

Technical Data

178

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Low Voltage Inhibit (LVI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 14. External Interrupt Module (IRQ)

14.1 Contents

14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

14.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

14.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

14.4.1 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . .184

14.6 IRQ Status and Control Register (ISCR). . . . . . . . . . . . . . .184

14.2 Introduction

14.3 Features

The IRQ module provides the nonmaskable interrupt input.

Features of the IRQ module include the following:

• Dedicated external interrupt pins (IRQ)

• IRQ interrupt control bit

• Hysteresis buffer

• Programmable edge-only or edge and level interrupt sensitivity

• Automatic interrupt acknowledge

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

179

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

14.4 Functional Description

A ‘0’ applied to any of the external interrupt pins can latch a CPU

interrupt request. Figure 14-1 shows the structure of the IRQ module.

Interrupt signals on the IRQ pin are latched into the IRQ latch. An

interrupt latch remains set until one of the following occurs:

• Vector fetch — a vector fetch automatically generates an interrupt

acknowledge signal which clears the latch that caused the vector

fetch.

• Software clear — software can clear an interrupt latch by writing

to the appropriate acknowledge bit in the interrupt status and

control register (ISCR). Writing a logic ‘1’ to the ACK bit clears the

IRQ latch.

• Reset — a reset automatically clears the interrupt latch.

ACK

TO CPU FOR

BIL/BIH

INSTRUCTIONS

VECTOR

FETCH

DECODER

V_DD

IRQF

CLR

D

Q

SYNCHRO-

NIZER

IRQ

INTERRUPT

REQUEST

CK

IRQ

LATCH

IMASK

MODE

TO MODE

SELECT

LOGIC

HIGH

VOLTAGE

DETECT

Figure 14-1. IRQ Module Block Diagram

The external interrupt pin is falling-edge-triggered and is software-

configurable to be both falling-edge and low-level-triggered. The MODE

bit in the ISCR controls the triggering sensitivity of the IRQ pin.

Technical Data

180

MC68HC08AZ32A — Rev 1.0

External Interrupt Module (IRQ)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

Functional Description

When an interrupt pin is edge-triggered only, the interrupt latch remains

set until a vector fetch, software clear, or reset occurs.

When an interrupt pin is both falling-edge and low-level-triggered, the

interrupt latch remains set until both of the following occur:

• Vector fetch or software clear

• Return of the interrupt pin to ‘1’

The vector fetch or software clear may occur before or after the interrupt

pin returns to ‘1’. As long as the pin is low, the interrupt request remains

pending. A reset will clear the latch and the MODE control bit, thereby

clearing the interrupt even if the pin stays low.

Table 14-1. IRQ I/O Register Summary

Register Name

Bit 7

6

0

5

0

4

0

3

IRQF

R

2

0

1

Bit 0 Addr.

Read:

Write:

0

IRQ Status/Control Register (ISCR)

IMASK MODE $001A

R

ACK

R

=Reserved

When set, the IMASK bit in the ISCR masks all external interrupt

requests. A latched interrupt request is not presented to the interrupt

priority logic unless the corresponding IMASK bit is clear.

NOTE: The interrupt mask (I) in the condition code register (CCR) masks all

interrupt requests, including external interrupt requests. See Figure 14-

2.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

181

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

.

FROM RESET

YES

I BIT SET?

NO

YES

INTERRUPT?

NO

STACK CPU REGISTERS.

SET I BIT.

LOAD PC WITH INTERRUPT VECTOR.

FETCH NEXT

INSTRUCTION.

YES

SWI

INSTRUCTION?

NO

RTI

UNSTACK CPU REGISTERS.

EXECUTE INSTRUCTION.

INSTRUCTION?

NO

Figure 14-2. IRQ Interrupt Flowchart

Technical Data

182

MC68HC08AZ32A — Rev 1.0

MOTOROLA

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

Functional Description

14.4.1 IRQ Pin

A ‘0’ on the IRQ pin can latch an interrupt request into the IRQ latch. A

vector fetch, software clear, or reset clears the IRQ latch.

If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-

level-sensitive. With MODE set, both of the following actions must occur

to clear the IRQ latch:

• Vector fetch or software clear — a vector fetch generates an

interrupt acknowledge signal to clear the latch. Software may

generate the interrupt acknowledge signal by writing a logic ‘1’ to

the ACK bit in the interrupt status and control register (ISCR). The

ACK bit is useful in applications that poll the IRQ pin and require

software to clear the IRQ latch. Writing to the ACK bit can also

prevent spurious interrupts due to noise. Setting ACK does not

affect subsequent transitions on the IRQ pin. A falling edge that

occurs after writing to the ACK bit latches another interrupt

request. If the IRQ mask bit, IMASK, is clear, the CPU loads the

program counter with the vector address at locations $FFFA and

$FFFB.

• Return of the IRQ pin to logic ‘1’ — as long as the IRQ pin is at

logic ‘0’, the IRQ latch remains set.

The vector fetch or software clear and the return of the IRQ pin to logic

‘1’ may occur in any order. The interrupt request remains pending as

long as the IRQ pin is at logic ‘0’. A reset will clear the latch and the

MODE control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With

MODE clear, a vector fetch or software clear immediately clears the IRQ

latch.

The IRQF bit in the ISCR register can be used to check for pending

interrupts. The IRQF bit is not affected by the IMASK bit, which makes it

useful in applications where polling is preferred.

The BIH or BIL instruction is used to read the logic level on the IRQ pin.

NOTE: When using the level-sensitive interrupt trigger, false interrupts can be

avoided by masking interrupt requests in the interrupt routine.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

183

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

14.5 IRQ Module During Break Interrupts

The system integration module (SIM) controls whether the IRQ interrupt

latch can be cleared during the break state. The BCFE bit in the SIM

break flag control register (SBFCR) enables software to clear the latches

during the break state. See SIM Break Flag Control Register (SBFCR)

on page 115.

To allow software to clear the IRQ latch during a break interrupt, write a

logic ’1’ to the BCFE bit. If a latch is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the latches during the break state, write a logic ‘0’ to the BCFE

bit. With BCFE at logic ‘0’ (its default state), writing to the ACK bit in the

IRQ status and control register during the break state has no effect on

the IRQ latch.

14.6 IRQ Status and Control Register (ISCR)

The IRQ status and control register (ISCR) controls and monitors

operation of the IRQ module. The ISCR performs the following functions:

• Indicates the state of the IRQ interrupt flag

• Clears the IRQ interrupt latch

• Masks IRQ interrupt requests

• Controls triggering sensitivity of the IRQ interrupt pin

Address: $001A

Bit 7

0

6

5

0

4

0

3

IRQF

R

2

0

1

IMASK

0

Bit 0

MODE

0

Read:

Write:

Reset:

0

R

0

R

0

ACK

0

R

=Reserved

Figure 14-3. IRQ Status and Control Register (ISCR)

Technical Data

184

MC68HC08AZ32A — Rev 1.0

MOTOROLA

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

IRQ Status and Control Register (ISCR)

IRQF — IRQ Flag Bit

This read-only status bit is high when the IRQ interrupt is pending.

1 = IRQ interrupt pending

0 = IRQ interrupt not pending

ACK — IRQ Interrupt Request Acknowledge Bit

Writing a logic ‘1’ to this write-only bit clears the IRQ latch. ACK

always reads as logic ‘0’. Reset clears ACK.

IMASK — IRQ Interrupt Mask Bit

Writing a logic ‘1’ to this read/write bit disables IRQ interrupt requests.

Reset clears IMASK.

1 = IRQ interrupt requests disabled

0 = IRQ interrupt requests enabled

MODE — IRQ Edge/Level Select Bit

This read/write bit controls the triggering sensitivity of the IRQ pin.

Reset clears MODE.

1 = IRQ interrupt requests on falling edges and low levels

0 = IRQ interrupt requests on falling edges only

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

185

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

External Interrupt Module (IRQ)

Technical Data

186

MC68HC08AZ32A — Rev 1.0

MOTOROLA

External Interrupt Module (IRQ)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 15. Serial Communications Interface (SCI)

15.1 Contents

15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

15.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

15.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

15.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

15.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

15.5.2.1

15.5.2.2

15.5.2.3

15.5.2.4

15.5.2.5

15.5.2.6

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Character Transmission . . . . . . . . . . . . . . . . . . . . . . .192

Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

Inversion of Transmitted Output . . . . . . . . . . . . . . . .197

Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .197

15.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

15.5.3.1

15.5.3.2

15.5.3.3

15.5.3.4

15.5.3.5

15.5.3.6

15.5.3.7

15.5.3.8

Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . .200

Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . .203

Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

15.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

15.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

15.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

15.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . .208

15.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

15.8.1 PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . .209

15.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . .209

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

187

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

15.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

15.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .209

15.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .212

15.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .215

15.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

15.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .221

15.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

15.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .223

15.2 Introduction

15.3 Features

The SCI allows asynchronous communications with peripheral devices

and other MCUs.

The SCI module’s features include:

• Full Duplex Operation

• Standard Mark/Space Non-Return-to-Zero (NRZ) Format

• 32 Programmable Baud Rates

• Programmable 8-Bit or 9-Bit Character Length

• Separately Enabled Transmitter and Receiver

• Separate Receiver and Transmitter CPU Interrupt Requests

• Programmable Transmitter Output Polarity

• Two Receiver Wakeup Methods:

– Idle Line Wakeup

– Address Mark Wakeup

• Interrupt-Driven Operation with Eight Interrupt Flags:

– Transmitter Empty

– Transmission Complete

– Receiver Full

Technical Data

188

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Pin Name Conventions

– Idle Receiver Input

– Receiver Overrun

– Noise Error

– Framing Error

– Parity Error

• Receiver Framing Error Detection

• Hardware Parity Checking

• 1/16 Bit-Time Noise Detection

15.4 Pin Name Conventions

The generic names of the SCI input/output (I/O) pins are:

• RxD (receive data)

• TxD (transmit data)

SCI I/O lines are implemented by sharing parallel I/O port pins. The full

name of an SCI input or output reflects the name of the shared port pin.

Table 15-1 shows the full names and the generic names of the SCI I/O

pins.The generic pin names appear in the text of this section.

Table 15-1. Pin Name Conventions

Generic Pin Names

Full Pin Names

RxD

TxD

PTE1/RxD

PTE0/TxD

15.5 Functional Description

Figure 15-1 shows the structure of the SCI module. The SCI allows full-

duplex, asynchronous, NRZ serial communication between the MCU

and remote devices, including other MCUs. The transmitter and receiver

of the SCI operate independently, although they use the same baud rate

generator. During normal operation, the CPU monitors the status of the

SCI, writes the data to be transmitted, and processes received data.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

189

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

INTERNAL BUS

SCI DATA

REGISTER

SCI DATA

REGISTER

RECEIVE

SHIFT REGISTER

TRANSMIT

SHIFT REGISTER

RxD

TxD

TXINV

SCTIE

R8

T8

TCIE

SCRIE

ILIE

TE

SCTE

TC

RE

RWU

SBK

SCRF

IDLE

OR

NF

FE

PE

ORIE

NEIE

FEIE

PEIE

LOOPS

ENSCI

LOOPS

RECEIVE

CONTROL

FLAG

CONTROL

TRANSMIT

CONTROL

WAKEUP

CONTROL

M

BKF

RPF

ENSCI

WAKE

ILTY

PEN

PTY

PRE-

BAUD RATE

÷ 4

CGMXCLK

SCALER GENERATOR

DATA SELECTION

CONTROL

÷ 16

Figure 15-1. SCI Module Block Diagram

Technical Data

190

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

Register Name

Bit 7

LOOPS

0

6

ENSCI

0

5

4

M

0

3

WAKE

0

2

ILTY

0

1

PEN

0

Bit 0

PTY

0

Read:

TXINV

SCI Control Register 1 (SCC1) Write:

Reset:

Read:

0

SCRIE

0

SCTIE

TCIE

0

ILIE

0

TE

RE

0

RWU

0

SBK

0

SCI Control Register 2 (SCC2) Write:

Reset:

0

Read:

SCI Control Register 3 (SCC3) Write:

Reset:

R8

T8

R

ORIE

NEIE

FEIE

PEIE

U

0

Read: SCTE

SCI Status Register 1 (SCS1) Write:

Reset:

TC

SCRF

IDLE

OR

NF

FE

PE

1

0

1

0

BKF

0

RPF

Read:

SCI Status Register 2 (SCS2) Write:

Reset:

0

Read:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SCI Data Register (SCDR) Write:

Reset:

Unaffected by Reset

Read:

SCI Baud Rate Register (SCBR) Write:

Reset:

0

SCP1

0

SCP0

0

R

0

SCR2

0

SCR1

0

SCR0

0

= Unimplemented

U = Unaffected

R = Reserved

Figure 15-2. SCI I/O Register Summary

Table 15-2. SCI I/O Register Address Summary

Register

Address

SCC1

$0013

SCC2

$0014

SCC3

$0015

SCS1

$0016

SCS2

$0017

SCDR

$0018

SCBR

$0019

15.5.1 Data Format

The SCI uses the standard non-return-to-zero mark/space data format

illustrated in Figure 15-3.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

191

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

8-BIT DATA FORMAT

(BIT M IN SCC1 CLEAR)

PARITY

OR DATA

BIT

START

BIT

STOP

BIT

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

9-BIT DATA FORMAT

(BIT M IN SCC1 SET)

PARITY

OR DATA

BIT

START

BIT

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP

BIT

Figure 15-3. SCI Data Formats

15.5.2 Transmitter

Figure 15-4 shows the structure of the SCI transmitter.

15.5.2.1 Character Length

The transmitter can accommodate either 8-bit or 9-bit data. The state of

the M bit in SCI control register 1 (SCC1) determines character length.

When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is

the ninth bit (bit 8).

15.5.2.2 Character Transmission

During an SCI transmission, the transmit shift register shifts a character

out to the TxD pin. The SCI data register (SCDR) is the write-only buffer

between the internal data bus and the transmit shift register. To initiate

an SCI transmission:

1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)

in SCI control register 1 (SCC1).

2. Enable the transmitter by writing a logic 1 to the transmitter enable

bit (TE) in SCI control register 2 (SCC2).

3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI

status register 1 (SCS1) and then writing to the SCDR.

4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic automatically

loads the transmit shift register with a preamble of logic 1s. After the

Technical Data

192

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

preamble shifts out, control logic transfers the SCDR data into the

transmit shift register. A logic 0 start bit automatically goes into the least

significant bit position of the transmit shift register. A logic 1 stop bit goes

into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the

SCDR transfers a byte to the transmit shift register. The SCTE bit

indicates that the SCDR can accept new data from the internal data bus.

If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the

SCTE bit generates a transmitter CPU interrupt request.

When the transmit shift register is not transmitting a character, the TxD

pin goes to the idle condition, logic 1. If at any time software clears the

ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver

relinquish control of the port E pins.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

193

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

INTERNAL BUS

PRE-

BAUD

÷ 16

÷ 4

SCI DATA REGISTER

SCALER DIVIDER

SCP1

SCP0

SCR1

SCR2

SCR0

11-BIT

TRANSMIT

SHIFT REGISTER

H

8

7

6

5

4

3

2

1

0

L

TxD

TXINV

M

PEN

PTY

PARITY

GENERATION

T8

TRANSMITTER

CONTROL LOGIC

SCTE

SCTIE

SBK

SCTE

LOOPS

ENSCI

TE

SCTIE

TC

TCIE

Figure 15-4. SCI Transmitter

Technical Data

194

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

Register Name

Bit 7

LOOPS

0

6

ENSCI

0

5

4

M

0

3

WAKE

0

2

ILTY

0

1

PEN

0

Bit 0

PTY

0

Read:

TXINV

SCI Control Register 1 (SCC1) Write:

Reset:

0

SCRIE

0

Read:

SCTIE

TCIE

0

ILIE

0

TE

RE

0

RWU

0

SBK

0

SCI Control Register 2 (SCC2) Write:

Reset:

0

Read:

SCI Control Register 3 (SCC3) Write:

Reset:

R8

T8

R

ORIE

NEIE

FEIE

PEIE

U

0

Read: SCTE

SCI Status Register 1 (SCS1) Write:

Reset:

TC

SCRF

IDLE

OR

NF

FE

PE

1

0

Read:

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SCI Data Register (SCDR) Write:

Reset:

Unaffected by Reset

Read:

SCI Baud Rate Register (SCBR) Write:

Reset:

0

SCP1

0

SCP0

0

R

0

SCR2

0

SCR1

0

SCR0

0

= Unimplemented

U = Unaffected

R = Reserved

Figure 15-5. SCI Transmitter I/O Register Summary

Table 15-3. SCI Transmitter I/O Address Summary

Register

SCC1

SCC2

$0014

SCC3

$0015

SCS1

$0016

SCDR

$0018

SCBR

$0019

Address $0013

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

195

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

15.5.2.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit

shift register with a break character. A break character contains all logic

0s and has no start, stop, or parity bit. Break character length depends

on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic

continuously loads break characters into the transmit shift register. After

software clears the SBK bit, the shift register finishes transmitting the

last break character and then transmits at least one logic 1. The

automatic logic 1 at the end of a break character guarantees the

recognition of the start bit of the next character.

The SCI recognizes a break character when a start bit is followed by

eight or nine logic 0 data bits and a logic 0 where the stop bit should be.

Receiving a break character has the following effects on SCI registers:

• Sets the framing error bit (FE) in SCS1

• Sets the SCI receiver full bit (SCRF) in SCS1

• Clears the SCI data register (SCDR)

• Clears the R8 bit in SCC3

• Sets the break flag bit (BKF) in SCS2

• May set the overrun (OR), noise flag (NF), parity error (PE), or

reception in progress flag (RPF) bits

15.5.2.4 Idle Characters

An idle character contains all logic 1s and has no start, stop, or parity bit.

Idle character length depends on the M bit in SCC1. The preamble is a

synchronizing idle character that begins every transmission.

If the TE bit is cleared during a transmission, the TxD pin becomes idle

after completion of the transmission in progress. Clearing and then

setting the TE bit during a transmission queues an idle character to be

sent after the character currently being transmitted.

NOTE: When a break sequence is followed immediately by an idle character,

this SCI design exhibits a condition in which the break character length

is reduced by one half bit time. In this instance, the break sequence will

Technical Data

196

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

consist of a valid start bit, eight or nine data bits (as defined by the M bit

in SCC1) of logic 0 and one half data bit length of logic 0 in the stop bit

position followed immediately by the idle character. To ensure a break

character of the proper length is transmitted, always queue up a byte of

data to be transmitted while the final break sequence is in progress.

NOTE: When queueing an idle character, return the TE bit to logic 1 before the

stop bit of the current character shifts out to the TxD pin. Setting TE after

the stop bit appears on TxD causes data previously written to the SCDR

to be lost.

A good time to toggle the TE bit for a queued idle character is when the

SCTE bit becomes set and just before writing the next byte to the SCDR.

15.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values, including

idle, break, start, and stop bits, are inverted when TXINV is at logic 1.

(See 15.9.1 SCI Control Register 1.)

15.5.2.6 Transmitter Interrupts

The following conditions can generate CPU interrupt requests from the

SCI transmitter:

• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a character to the transmit shift

register. SCTE can generate a transmitter CPU interrupt request.

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2

enables the SCTE bit to generate transmitter CPU interrupt

requests.

• Transmission complete (TC) — The TC bit in SCS1 indicates that

the transmit shift register and the SCDR are empty and that no

break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

197

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

15.5.3 Receiver

Figure 15-6 shows the structure of the SCI receiver.

INTERNAL BUS

SCR1

SCP1

SCP0

SCR2

SCI DATA REGISTER

SCR0

PRE-

BAUD

÷ 4

÷ 16

SCALER DIVIDER

11-BIT

RECEIVE SHIFT REGISTER

CGMXCLK

DATA

RECOVERY

H

8

7

6

5

4

3

2

1

0

L

RxD

ALL ZEROS

BKF

RPF

M

RWU

SCRF

IDLE

WAKE

ILTY

WAKEUP

LOGIC

PEN

PTY

R8

PARITY

CHECKING

IDLE

ILIE

SCRF

SCRIE

OR

ORIE

NF

NEIE

FE

FEIE

PE

PEIE

Figure 15-6. SCI Receiver Block Diagram

Technical Data

198

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

Register Name

Bit 7

LOOPS

0

6

ENSCI

0

5

4

M

0

3

WAKE

0

2

ILTY

0

1

PEN

0

Bit 0

PTY

0

SCI Control Register 1 (SCC1)

Read:

Write:

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

TXINV

0

SCRIE

0

SCI Control Register 2 (SCC2)

SCI Control Register 3 (SCC3)

SCI Status Register 1 (SCS1)

SCI Status Register 2 (SCS2)

SCI Data Register (SCDR)

SCTIE

TCIE

0

ILIE

0

TE

RE

0

RWU

0

SBK

0

R8

T8

R

ORIE

NEIE

FEIE

PEIE

U

0

Read: SCTE

Write:

TC

SCRF

IDLE

OR

NF

FE

PE

Reset:

Read:

Write:

Reset:

Read:

Write:

Reset:

1

0

1

0

BKF

RPF

0

R7

T7

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

Unaffected by Reset

SCI Baud Rate Register (SCBR) Read:

0

SCP1

0

SCP0

0

R

0

SCR2

0

SCR1

0

SCR0

0

Write:

Reset:

= Unimplemented

U = Unaffected

R

= Reserved

Figure 15-7. SCI I/O Receiver Register Summary

Table 15-4. SCI Receiver I/O Address Summary

Register SCC1

Address $0013

SCC2

$0014

SCC3

$0015

SCS1

$0016

SCS2

$0017

SCDR

$0018

SCBR

$0019

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

199

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

15.5.3.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the

M bit in SCI control register 1 (SCC1) determines character length.

When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the

ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth

bit (bit 7).

15.5.3.2 Character Reception

During an SCI reception, the receive shift register shifts characters in

from the RxD pin. The SCI data register (SCDR) is the read-only buffer

between the internal data bus and the receive shift register.

After a complete character shifts into the receive shift register, the data

portion of the character transfers to the SCDR. The SCI receiver full bit,

SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the

received byte can be read. If the SCI receive interrupt enable bit, SCRIE,

in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt

request.

15.5.3.3 Data Sampling

The receiver samples the RxD pin at the RT clock rate. The RT clock is

an internal signal with a frequency 16 times the baud rate. To adjust for

baud rate mismatch, the RT clock is resynchronized at the following

times (see Figure 15-8):

• After every start bit

• After the receiver detects a data bit change from logic 1 to logic 0

(after the majority of data bit samples at RT8, RT9, and RT10

returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search

for a logic 0 preceded by three logic 1s. When the falling edge of a

possible start bit occurs, the RT clock begins to count to 16.

Technical Data

200

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

START BIT

DATA

LSB

RxD

START BIT

QUALIFICATION

START BIT

SAMPLES

VERIFICATION SAMPLING

RT

CLOCK

RT CLOCK

STATE

RT CLOCK

RESET

Figure 15-8. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes

samples at RT3, RT5, and RT7. Table 15-5 summarizes the results of

the start bit verification samples.

Table 15-5. Start Bit Verification

RT3, RT5, and RT7 Samples

Start Bit Verification

Noise Flag

000

001

010

011

100

101

110

111

Yes

No

0

1

0

1

0

Yes

No

If start bit verification is not successful, the RT clock is reset and a new

search for a start bit begins.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

201

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

To determine the value of a data bit and to detect noise, recovery logic

takes samples at RT8, RT9, and RT10. Table 15-6 summarizes the

results of the data bit samples.

Table 15-6. Data Bit Recovery

RT8, RT9, and RT10 Samples

Data Bit Determination

Noise Flag

000

001

010

011

100

101

110

111

0

1

0

1

0

1

0

NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If

any or all of the RT8, RT9, and RT10 start bit samples are logic 1s

following a successful start bit verification, the noise flag (NF) is set and

the receiver assumes that the bit is a start bit.

To verify a stop bit and to detect noise, recovery logic takes samples at

RT8, RT9, and RT10. Table 15-7 summarizes the results of the stop bit

samples.

Table 15-7. Stop Bit Recovery

RT8, RT9, and RT10 Samples

Framing Error Flag

Noise Flag

000

001

010

011

100

101

110

111

1

0

1

0

1

0

Technical Data

202

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

15.5.3.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit

should be in an incoming character, it sets the framing error bit, FE, in

SCS1. A break character also sets the FE bit because a break character

has no stop bit. The FE bit is set at the same time that the SCRF bit is

set.

15.5.3.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above

the receiver baud rate. Accumulated bit time misalignment can cause

one of the three stop bit data samples to fall outside the actual stop bit.

Then a noise error occurs. If more than one of the samples is outside the

stop bit, a framing error occurs. In most applications, the baud rate

tolerance is much more than the degree of misalignment that is likely to

occur.

As the receiver samples an incoming character, it resynchronizes the RT

clock on any valid falling edge within the character. Resynchronization

within characters corrects misalignments between transmitter bit times

and receiver bit times.

Slow Data Tolerance

Figure 15-9 shows how much a slow received character can be

misaligned without causing a noise error or a framing error. The slow

stop bit begins at RT8 instead of RT1 but arrives in time for the stop

bit data samples at RT8, RT9, and RT10.

MSB

STOP

RECEIVER

RT CLOCK

DATA

SAMPLES

Figure 15-9. Slow Data

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

203

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

For an 8-bit character, data sampling of the stop bit takes the receiver

9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in Figure 15-9, the receiver

counts 154 RT cycles at the point when the count of the transmitting

device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a slow 8-bit character with no errors is

154 – 147

× 100 = 4.54%

-------------------------

154

For a 9-bit character, data sampling of the stop bit takes the receiver

10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned character shown in Figure 15-9, the receiver

counts 170 RT cycles at the point when the count of the transmitting

device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a slow 9-bit character with no errors is

170 – 163

× 100 = 4.12%

-------------------------

170

Fast Data Tolerance

Figure 15-10 shows how much a fast received character can be

misaligned without causing a noise error or a framing error. The fast

stop bit ends at RT10 instead of RT16 but is still there for the stop bit

data samples at RT8, RT9, and RT10.

STOP

IDLE OR NEXT CHARACTER

RECEIVER

RT CLOCK

DATA

SAMPLES

Figure 15-10. Fast Data

Technical Data

204

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Functional Description

For an 8-bit character, data sampling of the stop bit takes the receiver

9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in Figure 15-10, the receiver

counts 154 RT cycles at the point when the count of the transmitting

device is 10 bit times × 16 RT cycles = 160 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a fast 8-bit character with no errors is

154 – 160

× 100 = 3.90%.

-------------------------

154

For a 9-bit character, data sampling of the stop bit takes the receiver

10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned character shown in Figure 15-10, the receiver

counts 170 RT cycles at the point when the count of the transmitting

device is 11 bit times × 16 RT cycles = 176 RT cycles.

The maximum percent difference between the receiver count and the

transmitter count of a fast 9-bit character with no errors is

170 – 176

× 100 = 3.53%.

-------------------------

170

15.5.3.6 Receiver Wakeup

So that the MCU can ignore transmissions intended only for other

receivers in multiple-receiver systems, the receiver can be put into a

standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the

receiver into a standby state during which receiver interrupts are

disabled.

Depending on the state of the WAKE bit in SCC1, either of two

conditions on the RxD pin can bring the receiver out of the standby state:

• Address mark — An address mark is a logic 1 in the most

significant bit position of a received character. When the WAKE bit

is set, an address mark wakes the receiver from the standby state

by clearing the RWU bit. The address mark also sets the SCI

receiver full bit, SCRF. Software can then compare the character

containing the address mark to the user-defined address of the

receiver. If they are the same, the receiver remains awake and

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

205

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

processes the characters that follow. If they are not the same,

software can set the RWU bit and put the receiver back into the

standby state.

• Idle input line condition — When the WAKE bit is clear, an idle

character on the RxD pin wakes the receiver from the standby

state by clearing the RWU bit. The idle character that wakes the

receiver does not set the receiver idle bit, IDLE, or the SCI receiver

full bit, SCRF. The idle line type bit, ILTY, determines whether the

receiver begins counting logic 1s as idle character bits after the

start bit or after the stop bit.

NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been

idle may cause the receiver to wake up immediately.

15.5.3.7 Receiver Interrupts

The following sources can generate CPU interrupt requests from the SCI

receiver:

• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that

the receive shift register has transferred a character to the SCDR.

SCRF can generate a receiver CPU interrupt request. Setting the

SCI receive interrupt enable bit, SCRIE, in SCC2 enables the

SCRF bit to generate receiver CPU interrupts.

• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11

consecutive logic 1s shifted in from the RxD pin. The idle line

interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate

CPU interrupt requests.

15.5.3.8 Error Interrupts

The following receiver error flags in SCS1 can generate CPU interrupt

requests:

• Receiver overrun (OR) — The OR bit indicates that the receive

shift register shifted in a new character before the previous

character was read from the SCDR. The previous character

Technical Data

206

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Low-Power Modes

remains in the SCDR, and the new character is lost. The overrun

interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI

error CPU interrupt requests.

• Noise flag (NF) — The NF bit is set when the SCI detects noise on

incoming data or break characters, including start, data, and stop

bits. The noise error interrupt enable bit, NEIE, in SCC3 enables

NF to generate SCI error CPU interrupt requests.

• Framing error (FE) — The FE bit in SCS1 is set when a logic 0

occurs where the receiver expects a stop bit. The framing error

interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI

error CPU interrupt requests.

• Parity error (PE) — The PE bit in SCS1 is set when the SCI

detects a parity error in incoming data. The parity error interrupt

enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU

interrupt requests.

15.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumption standby modes.

15.6.1 Wait Mode

The SCI module remains active in wait mode. Any enabled CPU

interrupt request from the SCI module can bring the MCU out of wait

mode.

If SCI module functions are not required during wait mode, reduce power

consumption by disabling the module before executing the WAIT

instruction.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

207

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

15.6.2 Stop Mode

The SCI module is inactive in stop mode. The STOP instruction does not

affect SCI register states. Any enabled CPU interrupt request from the

SCI module does not bring the MCU out of Stop mode. SCI module

operation resumes after the MCU exits stop mode.

Because the internal clock is inactive during stop mode, entering stop

mode during an SCI transmission or reception results in invalid data.

15.7 SCI During Break Module Interrupts

The BCFE bit in the break flag control register (BFCR) enables software

to clear status bits during the break state. (See Break Module on page

149).

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

I/O registers during the break state without affecting status bits. Some

status bits have a two-step read/write clearing procedure. If software

does the first step on such a bit before the break, the bit cannot change

during the break state as long as BCFE is at logic 0. After the break,

doing the second step clears the status bit.

15.8 I/O Signals

Port E shares two of its pins with the SCI module. The two SCI I/O pins

are:

• PTE0/TxD — Transmit data

• PTE1/RxD — Receive data

Technical Data

208

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

15.8.1 PTE0/TxD (Transmit Data)

The PTE0/TxD pin is the serial data output from the SCI transmitter. The

SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the

PTE0/TxD pin is an output regardless of the state of the DDRE2 bit in

data direction register E (DDRE).

15.8.2 PTE1/RxD (Receive Data)

The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI

shares the PTE1/RxD pin with port E. When the SCI is enabled, the

PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data

direction register E (DDRE).

15.9 I/O Registers

The following I/O registers control and monitor SCI operation:

• SCI control register 1 (SCC1)

• SCI control register 2 (SCC2)

• SCI control register 3 (SCC3)

• SCI status register 1 (SCS1)

• SCI status register 2 (SCS2)

• SCI data register (SCDR)

• SCI baud rate register (SCBR)

15.9.1 SCI Control Register 1

SCI control register 1:

• Enables loop mode operation

• Enables the SCI

• Controls output polarity

• Controls character length

• Controls SCI wakeup method

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

209

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

• Controls idle character detection

• Enables parity function

• Controls parity type

Address: $0013

Bit 7

6

ENSCI

0

5

TXINV

0

4

M

0

3

WAKE

0

2

ILLTY

0

1

PEN

0

Bit 0

PTY

0

Read:

Write:

Reset:

LOOPS

0

Figure 15-11. SCI Control Register 1 (SCC1)

LOOPS — Loop Mode Select Bit

This read/write bit enables loop mode operation. In loop mode the

RxD pin is disconnected from the SCI, and the transmitter output goes

into the receiver input. Both the transmitter and the receiver must be

enabled to use loop mode. Reset clears the LOOPS bit.

1 = Loop mode enabled

0 = Normal operation enabled

ENSCI — Enable SCI Bit

This read/write bit enables the SCI and the SCI baud rate generator.

Clearing ENSCI sets the SCTE and TC bits in SCI status register 1

and disables transmitter interrupts. Reset clears the ENSCI bit.

1 = SCI enabled

0 = SCI disabled

TXINV — Transmit Inversion Bit

This read/write bit reverses the polarity of transmitted data. Reset

clears the TXINV bit.

1 = Transmitter output inverted

0 = Transmitter output not inverted

NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,

start, and stop bits.

Technical Data

210

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

M — Mode (Character Length) Bit

This read/write bit determines whether SCI characters are eight or

nine bits long. (See Table 15-8).The ninth bit can serve as an extra

stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears

the M bit.

1 = 9-bit SCI characters

0 = 8-bit SCI characters

WAKE — Wakeup Condition Bit

This read/write bit determines which condition wakes up the SCI: a

logic 1 (address mark) in the most significant bit position of a received

character or an idle condition on the RxD pin. Reset clears the WAKE

bit.

1 = Address mark wakeup

0 = Idle line wakeup

ILTY — Idle Line Type Bit

This read/write bit determines when the SCI starts counting logic 1s

as idle character bits. The counting begins either after the start bit or

after the stop bit. If the count begins after the start bit, then a string of

logic 1s preceding the stop bit may cause false recognition of an idle

character. Beginning the count after the stop bit avoids false idle

character recognition, but requires properly synchronized

transmissions. Reset clears the ILTY bit.

1 = Idle character bit count begins after stop bit

0 = Idle character bit count begins after start bit

PEN — Parity Enable Bit

This read/write bit enables the SCI parity function. (See Table 15-8).

When enabled, the parity function inserts a parity bit in the most

significant bit position. (See Table 15-7). Reset clears the PEN bit.

1 = Parity function enabled

0 = Parity function disabled

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

211

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

PTY — Parity Bit

This read/write bit determines whether the SCI generates and checks

for odd parity or even parity. (See Table 15-8). Reset clears the PTY

bit.

1 = Odd parity

0 = Even parity

NOTE: Changing the PTY bit in the middle of a transmission or reception can

generate a parity error.

Table 15-8. Character Format Selection

Control Bits

PEN:PTY

Character Format

Start

Bits

Data

Bits

Stop

Parity

Character

Length

M

Bits

0

1

0

1

0X

10

11

10

11

1

8

9

7

8

None

Even

Odd

1

10 Bits

11 Bits

10 Bits

11 Bits

Even

Odd

15.9.2 SCI Control Register 2

SCI control register 2:

• Enables the following CPU interrupt requests:

– Enables the SCTE bit to generate transmitter CPU interrupt

requests

– Enables the TC bit to generate transmitter CPU interrupt

requests

– Enables the SCRF bit to generate receiver CPU interrupt

requests

– Enables the IDLE bit to generate receiver CPU interrupt

requests

Technical Data

212

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

• Enables the transmitter

• Enables the receiver

• Enables SCI wakeup

• Transmits SCI break characters

Address: $0014

Bit 7

6

TCIE

0

5

SCRIE

0

4

ILIE

0

3

TE

0

2

RE

0

1

Bit 0

Read:

Write:

Reset:

SCTIE

0

RWU

0

SBK

0

Figure 15-12. SCI Control Register 2 (SCC2)

SCTIE — SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter

CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the

SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE

bit.

1 = SCTE enabled to generate CPU interrupt

0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU

interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

SCRIE — SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver

CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the

SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE

bit.

1 = SCRF enabled to generate CPU interrupt

0 = SCRF not enabled to generate CPU interrupt

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

213

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

ILIE — Idle Line Interrupt Enable Bit

This read/write bit enables the IDLE bit to generate SCI receiver CPU

interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests

0 = IDLE not enabled to generate CPU interrupt requests

TE — Transmitter Enable Bit

Setting this read/write bit begins the transmission by sending a

preamble of 10 or 11 logic 1s from the transmit shift register to the

TxD pin. If software clears the TE bit, the transmitter completes any

transmission in progress before the TxD returns to the idle condition

(logic 1). Clearing and then setting TE during a transmission queues

an idle character to be sent after the character currently being

transmitted. Reset clears the TE bit.

1 = Transmitter enabled

0 = Transmitter disabled

NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

RE — Receiver Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit

disables the receiver but does not affect receiver interrupt flag bits.

Reset clears the RE bit.

1 = Receiver enabled

0 = Receiver disabled

NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

RWU — Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state during which

receiver interrupts are disabled. The WAKE bit in SCC1 determines

whether an idle input or an address mark brings the receiver out of the

standby state and clears the RWU bit. Reset clears the RWU bit.

1 = Standby state

0 = Normal operation

Technical Data

214

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

SBK — Send Break Bit

Setting and then clearing this read/write bit transmits a break

character followed by a logic 1. The logic 1 after the break character

guarantees recognition of a valid start bit. If SBK remains set, the

transmitter continuously transmits break characters with no logic 1s

between them. Reset clears the SBK bit.

1 = Transmit break characters

0 = No break characters being transmitted

NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.

Toggling SBK before the preamble begins causes the SCI to send a

break character instead of a preamble.

15.9.3 SCI Control Register 3

SCI control register 3:

• Stores the ninth SCI data bit received and the ninth SCI data bit to

be transmitted.

• Enables the following interrupts:

– Receiver overrun interrupts

– Noise error interrupts

– Framing error interrupts

– Parity error interrupts

Address: $0015

Bit 7

R8

6

T8

U

5

R

0

4

3

2

NEIE

0

1

FEIE

0

Bit 0

PEIE

0

Read:

Write:

Reset:

R

ORIE

U

0

= Unimplemented

R

= Reserved

U = Unaffected

Figure 15-13. SCI Control Register 3 (SCC3)

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

215

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

R8 — Received Bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth

bit (bit 8) of the received character. R8 is received at the same time

that the SCDR receives the other 8 bits.

When the SCI is receiving 8-bit characters, R8 is a copy of the eighth

bit (bit 7). Reset has no effect on the R8 bit.

T8 — Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write

ninth bit (bit 8) of the transmitted character. T8 is loaded into the

transmit shift register at the same time that the SCDR is loaded into

the transmit shift register. Reset has no effect on the T8 bit.

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests

generated by the parity error bit, PE. Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

Technical Data

216

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

15.9.4 SCI Status Register 1

SCI status register 1 contains flags to signal the following conditions:

• Transfer of SCDR data to transmit shift register complete

• Transmission complete

• Transfer of receive shift register data to SCDR complete

• Receiver input idle

• Receiver overrun

• Noisy data

• Framing error

• Parity error

Address: $0016

Bit 7

Read: SCTE

Write:

6

5

4

3

2

1

Bit 0

PE

TC

SCRF

IDLE

OR

NF

FE

Reset:

1

0

= Unimplemented

Figure 15-14. SCI Status Register 1 (SCS1)

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a

character to the transmit shift register. SCTE can generate an SCI

transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,

SCTE generates an SCI transmitter CPU interrupt request. In normal

operation, clear the SCTE bit by reading SCS1 with SCTE set and

then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register

0 = SCDR data not transferred to transmit shift register

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Serial Communications Interface (SCI)

217

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

TC — Transmission Complete Bit

This read-only bit is set when the SCTE bit is set, and no data,

preamble, or break character is being transmitted. TC generates an

SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also

set. TC is cleared automatically when data, preamble, or break is

queued and ready to be sent. There may be up to 1.5 transmitter

clocks of latency between queueing data, preamble, and break and

the transmission actually starting. Reset sets the TC bit.

1 = No transmission in progress

0 = Transmission in progress

SCRF — SCI Receiver Full Bit

This clearable, read-only bit is set when the data in the receive shift

register transfers to the SCI data register. SCRF can generate an SCI

receiver CPU interrupt request. When the SCRIE bit in SCC2 is set

the SCRF generates a CPU interrupt request. In normal operation,

clear the SCRF bit by reading SCS1 with SCRF set and then reading

the SCDR. Reset clears SCRF.

1 = Received data available in SCDR

0 = Data not available in SCDR

IDLE — Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive logic 1s

appear on the receiver input. IDLE generates an SCI error CPU

interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit

by reading SCS1 with IDLE set and then reading the SCDR. After the

receiver is enabled, it must receive a valid character that sets the

SCRF bit before an idle condition can set the IDLE bit. Also, after the

IDLE bit has been cleared, a valid character must again set the SCRF

bit before an idle condition can set the IDLE bit. Reset clears the IDLE

bit.

1 = Receiver input idle

0 = Receiver input active (or idle since the IDLE bit was cleared)

OR — Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the

SCDR before the receive shift register receives the next character.

The OR bit generates an SCI error CPU interrupt request if the ORIE

Technical Data

218

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

bit in SCC3 is also set. The data in the shift register is lost, but the data

already in the SCDR is not affected. Clear the OR bit by reading SCS1

with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift register full and SCRF = 1

0 = No receiver overrun

Software latency may allow an overrun to occur between reads of SCS1

and SCDR in the flag-clearing sequence. Figure 15-15 shows the

normal flag-clearing sequence and an example of an overrun caused by

a delayed flag-clearing sequence. The delayed read of SCDR does not

clear the OR bit because OR was not set when SCS1 was read. Byte 2

caused the overrun and is lost. The next flag-clearing sequence reads

byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is

important to know which byte is lost due to an overrun, the flag-clearing

routine can check the OR bit in a second read of SCS1 after reading the

data register.

NORMAL FLAG CLEARING SEQUENCE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 1

READ SCDR

BYTE 2

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

BYTE 1

BYTE 2

BYTE 3

BYTE 4

READ SCS1

SCRF = 1

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 1

READ SCDR

BYTE 3

Figure 15-15. Flag Clearing Sequence

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

219

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

NF — Receiver Noise Flag Bit

This clearable, read-only bit is set when the SCI detects noise on the

RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in

SCC3 is also set. Clear the NF bit by reading SCS1 and then reading

the SCDR. Reset clears the NF bit.

1 = Noise detected

0 = No noise detected

FE — Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the

stop bit. FE generates an SCI error CPU interrupt request if the FEIE

bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set

and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected

0 = No framing error detected

PE — Receiver Parity Error Bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates a PE CPU interrupt request if the

PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

Technical Data

220

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

15.9.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditions:

• Break character detected

• Incoming data

Address: $0017

Bit 7

0

6

0

5

0

4

0

3

0

2

0

1

Bit 0

RPF

Read:

Write:

Reset:

BKF

0

= Unimplemented

Figure 15-16. SCI Status Register 2 (SCS2)

BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break

character on the RxD pin. In SCS1, the FE and SCRF bits are also

set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.

BKF does not generate a CPU interrupt request. Clear BKF by

reading SCS2 with BKF set and then reading the SCDR. Once

cleared, BKF can become set again only after logic 1s again appear

on the RxD pin followed by another break character. Reset clears the

BKF bit.

1 = Break character detected

0 = No break character detected

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

Serial Communications Interface (SCI)

221

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

RPF — Reception in Progress Flag Bit

This read-only bit is set when the receiver detects a logic 0 during the

RT1 time period of the start bit search. RPF does not generate an

interrupt request. RPF is reset after the receiver detects false start bits

(usually from noise or a baud rate mismatch), or when the receiver

detects an idle character. Polling RPF before disabling the SCI

module or entering stop mode can show whether a reception is in

progress.

1 = Reception in progress

0 = No reception in progress

15.9.6 SCI Data Register

The SCI data register is the buffer between the internal data bus and the

receive and transmit shift registers. Reset has no effect on data in the

SCI data register.

Address: $0018

Bit 7

R7

6

5

4

3

2

1

Bit 0

R0

Read:

Write:

Reset:

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

T7

T0

Unaffected by Reset

Figure 15-17. SCI Data Register (SCDR)

R7/T7:R0/T0 — Receive/Transmit Data Bits

Reading address $0018 accesses the read-only received data bits,

R7:R0. Writing to address $0018 writes the data to be transmitted,

T7:T0. Reset has no effect on the SCI data register.

NOTE: Do not use read-modify-write instructions on the SCI data register.

Technical Data

222

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

15.9.7 SCI Baud Rate Register

The baud rate register selects the baud rate for both the receiver and the

transmitter.

Address: $0019

Bit 7

0

6

0

5

SCP1

0

4

3

2

SCR2

0

1

SCR1

0

Bit 0

SCR0

0

Read:

Write:

Reset:

SCP0

R

0

= Unimplemented

R

= Reserved

Figure 15-18. SCI Baud Rate Register (SCBR)

SCP1 and SCP0 — SCI Baud Rate Prescaler Bits

These read/write bits select the baud rate prescaler divisor as shown

in Table 15-9. Reset clears SCP1 and SCP0.

Table 15-9. SCI Baud Rate Prescaling

SCP[1:0]

Prescaler Divisor (PD)

00

01

10

11

1

3

4

13

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

223

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

SCR2 – SCR0 — SCI Baud Rate Select Bits

These read/write bits select the SCI baud rate divisor as shown in

Table 15-10. Reset clears SCR2–SCR0.

Table 15-10. SCI Baud Rate Selection

SCR[2:1:0]

000

Baud Rate Divisor (BD)

1

2

001

010

4

011

8

100

16

32

64

128

101

110

111

Use the following formula to calculate the SCI baud rate:

f_Crystal

Baud rate = ------------------------------------

64 × PD × BD

where:

f

_Crystal= crystal frequency

PD = prescaler divisor

BD = baud rate divisor

Table 15-11 shows the SCI baud rates that can be generated with a

4.9152-MHz crystal.

Technical Data

224

MC68HC08AZ32A — Rev 1.0

Serial Communications Interface (SCI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

I/O Registers

Table 15-11. SCI Baud Rate Selection Examples

Prescaler

Divisor

(PD)

Baud Rate

Divisor

(BD)

Baud Rate

SCP[1:0]

SCR[2:1:0]

(f

= 4.9152 MHz)

Crystal

00

01

10

11

1

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

1

2

76,800

38,400

19,200

9600

4800

2400

1200

600

1

4

1

8

1

16

32

64

128

1

3

25,600

12,800

6400

3200

1600

800

3

2

3

4

3

8

3

16

32

64

128

1

3

400

3

200

4

19,200

9600

4800

2400

1200

600

4

2

4

8

4

16

32

64

128

1

4

300

4

150

13

5908

2954

1477

739

2

4

8

16

32

64

128

369

185

92

46

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

225

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Communications Interface (SCI)

Technical Data

226

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Communications Interface (SCI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Technical Data — MC68HC08AZ32A

Section 16. Serial Peripheral Interface (SPI)

16.1 Contents

16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

16.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

16.4 Pin Name Conventions and I/O Register Addresses. . . . .229

16.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

16.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

16.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

16.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

16.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . .234

16.6.2 Transmission Format When CPHA = ‘0’. . . . . . . . . . . . .235

16.6.3 Transmission Format When CPHA = ‘1’. . . . . . . . . . . . .236

16.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . .237

16.6.5 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

16.6.6 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

16.6.7 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

16.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

16.8 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . .244

16.9 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

16.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

16.10.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

16.10.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

16.11 SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .247

16.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

16.12.1 MISO (MasterIn/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .249

16.12.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .249

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

227

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

16.12.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . .249

16.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

16.12.5 VSS (Clock Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

16.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

16.13.1 SPI Control Register (SPCR). . . . . . . . . . . . . . . . . . . . . .252

16.13.2 SPI Status and Control Register (SPSCR) . . . . . . . . . . .254

16.13.3 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . .258

16.2 Introduction

16.3 Features

This section describes the serial peripheral interface module (SPI),

which allows full-duplex, synchronous, serial communications with

peripheral devices.

Features of the SPI module include the following:

• Full-duplex operation

• Master and slave modes

• Double-buffered operation with separate transmit and receive

registers

• Four master mode frequencies (maximum = bus frequency ÷ 2)

• Maximum slave mode frequency = bus frequency

• Serial clock with programmable polarity and phase

• Two separately enabled interrupts with CPU service:

– SPRF (SPI receiver full)

– SPTE (SPI transmitter empty)

• Mode fault error flag with CPU interrupt capability

• Overflow error flag with CPU interrupt capability

• Programmable wired-OR mode

• I²C (inter-integrated circuit) compatibility

Technical Data

228

MC68HC08AZ32A — Rev 1.0

Serial Peripheral Interface (SPI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

Pin Name Conventions and I/O Register Addresses

16.4 Pin Name Conventions and I/O Register Addresses

The generic names of the SPI input/output (I/O) pins are:

• SS (slave select)

• SPSCK (SPI serial clock)

• MOSI (master out slave in)

• MISO (master in slave out)

The SPI shares four I/O pins with a parallel I/O port. The full name of an

SPI pin reflects the name of the shared port pin. Table 16-1 shows the

full names of the SPI I/O pins. The generic pin names appear in the text

that follows.:

Table 16-1. Pin Name Conventions

V_SS

SPI Generic Pin Names:

Full SPI Pin Names: SPI

MISO

MOSI

SS

SCK

PTE5/MISO

PTE6/MOSI

PTE4/SS

PTE7/SPSCK CGND

Table 16-2. I/O Register Addresses

Register name

Register address

$0010

SPI Control Register (SPICR)

SPI Status and Control Register (SPISCR)

SPI Data Register (SPIDR)

$0011

$0012

The generic pins names appear in the text that follows.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

229

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

16.5 Functional Description

Figure 16-1 summarizes the SPI I/O registers and Figure 16-2 show the

structure of the SPI module.

Register name

R/W Bit 7

6

5

4

3

2

1

Bit 0

Read:

SPRIE

Write:

SPI Control Register (SPCR)

R

0

SPMSTR CPOL CPHA SPWOM SPE SPTIE

Reset:

0

1

0

1

0

Read: SPRF

Write:

OVRF MODF SPTE

SPI Status and Control Register

(SPSCR)

ERRIE

MODFEN SPR1 SPR0

Reset:

0

1

0

Read: R7

Write: T7

Reset:

R6

T6

R5

T5

R4

T4

R3

T3

R2

T2

R1

T1

R0

T0

SPI Data Register (SPDR)

Unaffected by reset

= Unimplemented

R

= Reserved

Figure 16-1. SPI I/O Register Summary

Technical Data

230

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

Functional Description

INTERNAL BUS

TRANSMIT DATA REGISTER

SHIFT REGISTER

BUS CLOCK

MISO

MOSI

7

6

5

4

3

2

1

0

÷ 2

÷ 8

CLOCK

RECEIVE DATA REGISTER

DIVIDER

÷ 32

CONTROL

LOGIC

÷ 128

CLOCK

SPSCK

SS

SPMSTR

SPE

SELECT

M

CLOCK

LOGIC

S

SPR1

SPR0

SPMSTR CPHA

CPOL

MODFEN

ERRIE

SPTIE

SPWOM

TRANSMITTER CPU INTERRUPT REQUEST

RECEIVER/ERROR CPU INTERRUPT REQUEST

SPI

CONTROL

SPRIE

SPE

SPRF

SPTE

OVRF

MODF

Figure 16-2. SPI Module Block Diagram

The SPI module allows full-duplex, synchronous, serial communication

between the MCU and peripheral devices, including other MCUs.

Software can poll the SPI status flags or SPI operation can be interrupt-

driven. All SPI interrupts can be serviced by the CPU.

The following paragraphs describe the operation of the SPI module.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

231

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

16.5.1 Master Mode

The SPI operates in master mode when the SPI master bit, SPMSTR, is

set.

NOTE: Configure the SPI modules as master and slave before enabling them.

Enable the master SPI before enabling the slave SPI. Disable the slave

SPI before disabling the master SPI. See SPI Control Register (SPCR)

on page 252.

Only a master SPI module can initiate transmissions. Software begins

the transmission from a master SPI module by writing to the SPI data

register. If the shift register is empty, the byte immediately transfers to

the shift register, setting the SPI transmitter empty bit, SPTE. The byte

begins shifting out on the MOSI pin under the control of the serial clock.

See Figure 16-3.

The SPR1 and SPR0 bits control the baud rate generator and determine

the speed of the shift register. See SPI Status and Control Register

(SPSCR) on page 254. Through the SPSCK pin, the baud rate generator

of the master also controls the shift register of the slave peripheral.

As the byte shifts out on the MOSI pin of the master, another byte shifts

in from the slave on the master’s MISO pin. The transmission ends when

the receiver full bit, SPRF, becomes set. At the same time that SPRF

becomes set, the byte from the slave transfers to the receive data

register. In normal operation, SPRF signals the end of a transmission.

Software clears SPRF by reading the SPI status and control register with

Technical Data

232

MC68HC08AZ32A — Rev 1.0

Serial Peripheral Interface (SPI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

Functional Description

SPRF set and then reading the SPI data register. Writing to the SPI data

register clears the SPTIE bit.

MASTER MCU

SLAVE MCU

MISO

MOSI

MISO

MOSI

SHIFT REGISTER

SPSCK

SS

SPSCK

SS

BAUD RATE

GENERATOR

V_DD

Figure 16-3. Full-duplex Master-Slave Connections

16.5.2 Slave Mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave

mode the SPSCK pin is the input for the serial clock from the master

MCU. Before a data transmission occurs, the SS pin of the slave MCU

must be at logic ‘0’. SS must remain low until the transmission is

complete. See Mode Fault Error on page 241.

In a slave SPI module, data enters the shift register under the control of

the serial clock from the master SPI module. After a byte enters the shift

register of a slave SPI, it transfers to the receive data register, and the

SPRF bit is set. To prevent an overflow condition, slave software must

then read the SPI data register before another byte enters the shift

register.

The maximum frequency of the SPSCK for an SPI configured as a slave

is the bus clock speed (which is twice as fast as the fastest master

SPSCK clock that can be generated). The frequency of the SPSCK for

an SPI configured as a slave does not have to correspond to any

particular SPI baud rate. The baud rate only controls the speed of the

SPSCK generated by an SPI configured as a master. Therefore, the

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

233

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

frequency of the SPSCK for an SPI configured as a slave can be any

frequency less than or equal to the bus speed.

When the master SPI starts a transmission, the data in the slave shift

register begins shifting out on the MISO pin. The slave can load its shift

register with a new byte for the next transmission by writing to its transmit

data register. The slave must write to its transmit data register at least

one bus cycle before the master starts the next transmission. Otherwise

the byte already in the slave shift register shifts out on the MISO pin.

Data written to the slave shift register during a a transmission remains in

a buffer until the end of the transmission.

When the clock phase bit (CPHA) is set, the first edge of SPSCK starts

a transmission. When CPHA is clear, the falling edge of SS starts a

transmission. See Transmission Formats on page 234.

If the write to the data register is late, the SPI transmits the data already

in the shift register from the previous transmission.

NOTE: SPSCK must be in the proper idle state before the slave is enabled to

prevent SPSCK from appearing as a clock edge.

16.6 Transmission Formats

During an SPI transmission, data is simultaneously transmitted (shifted

out serially) and received (shifted in serially). A serial clock line

synchronizes shifting and sampling on the two serial data lines. A slave

select line allows individual selection of a slave SPI device; slave

devices that are not selected do not interfere with SPI bus activities. On

a master SPI device, the slave select line can optionally be used to

indicate a multiple-master bus contention.

16.6.1 Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SCK) phase

and polarity using two bits in the SPI control register (SPCR). The clock

polarity is specified by the CPOL control bit, which selects an active high

or low clock and has no significant effect on the transmission format.

Technical Data

234

MC68HC08AZ32A — Rev 1.0

Serial Peripheral Interface (SPI)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

Transmission Formats

The clock phase (CPHA) control bit selects one of two fundamentally

different transmission formats. The clock phase and polarity should be

identical for the master SPI device and the communicating slave device.

In some cases, the phase and polarity are changed between

transmissions to allow a master device to communicate with peripheral

slaves having different requirements.

NOTE: Before writing to the CPOL bit or the CPHA bit, the SPI should be

disabled by clearing the SPI enable bit (SPE).

16.6.2 Transmission Format When CPHA = ‘0’

Figure 16-4 shows an SPI transmission in which CPHA is ‘0’. The figure

should not be used as a replacement for data sheet parametric

information.Two waveforms are shown for SCK: one for CPOL = ‘0’ and

another for CPOL = ‘1’. The diagram may be interpreted as a master or

slave timing diagram since the serial clock (SCK), master in/slave out

(MISO), and master out/slave in (MOSI) pins are directly connected

between the master and the slave. The MISO signal is the output from

the slave, and the MOSI signal is the output from the master. The SS line

is the slave select input to the slave. The slave SPI drives its MISO

output only when its slave select input (SS) is at logic ‘0’, so that only the

selected slave drives to the master. The SS pin of the master is not

shown but is assumed to be inactive. The SS pin of the master must be

high or must be reconfigured as general purpose I/O not affecting the

SPI. See Mode Fault Error on page 241. When CPHA = ‘0’, the first

SPSCK edge is the MSB capture strobe. Therefore the slave must begin

driving its data before the first SPSCK edge, and a falling edge on the

SS pin is used to start the transmission. The SS pin must be toggled high

and then low again between each byte transmitted.

MC68HC08AZ32A — Rev 1.0

MOTOROLA

Technical Data

235

Serial Peripheral Interface (SPI)

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

SCK CYCLE #

(FOR REFERENCE)

1

2

3

4

5

6

7

8

SCK (CPOL =’0’)

SCK (CPOL =1)

MOSI

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

(FROM MASTER)

MISO

(FROM SLAVE)

MSB

SS (TO SLAVE)

CAPTURE STROBE

Figure 16-4. Transmission Format (CPHA = ‘0’)

16.6.3 Transmission Format When CPHA = ‘1’

Figure 16-5 shows an SPI transmission in which CPHA is ‘1’. The figure

should not be used as a replacement for data sheet parametric

information. Two waveforms are shown for SCK: one for CPOL = ‘0’ and