MC68HC08BD24 [MOTOROLA]
HCMOS Microcontroller Unit; HCMOS微控制器单元
| 型号： | MC68HC08BD24 |
| 厂家： | 
MOTOROLA |
| 描述： | HCMOS Microcontroller Unit |
| 文件： | 总244页 (文件大小：2811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MC68HC08BD24/D
REV. 1.0
MC68HC08BD24
HCMOS Mic roc ontrolle r Unit
TECHNICAL DATA
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc.
Te c hnic a l Da ta — MC68HC08BD24
List of Se c tions
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .31
Section 3. Random-Access Memory (RAM) . . . . . . . . . .49
Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . .51
Section 5. Configuration Register (CONFIG) . . . . . . . . .53
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .57
Section 7. System Integration Module (SIM) . . . . . . . . .77
Section 8. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . .101
Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . .105
Section 10. Timer Interface Module (TIM) . . . . . . . . . . .115
Section 11. Pulse Width Modulator (PWM) . . . . . . . . . .137
Section 12. Analog-to-Digital Converter (ADC) . . . . . .143
Section 13. DDC12AB Interface . . . . . . . . . . . . . . . . . . .153
Section 14. Sync Processor. . . . . . . . . . . . . . . . . . . . . .169
Section 15. Input/Output (I/O) Ports . . . . . . . . . . . . . . .189
Section 16. External Interrupt (IRQ) . . . . . . . . . . . . . . .211
Section 17. Computer Operating Properly (COP) . . . .217
Section 18. Break Module (BRK) . . . . . . . . . . . . . . . . . .223
Section 19. Electrical Specifications. . . . . . . . . . . . . . .231
Section 20. Mechanical Specifications . . . . . . . . . . . . .239
MC68HC08BD24 — Rev. 1.0
MOTOROLA
Technical Data
List of Sections
3
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List of Se c tions
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
4
List of Sections
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Te c hnic a l Da ta — MC68HC08BD24
Ta b le of Conte nts
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Section 2. Memory Map
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .31
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .32
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Section 3. Random-Access Memory (RAM)
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 4. Read-Only Memory (ROM)
4.1
4.2
4.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
MC68HC08BD24 — Rev. 1.0
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Section 5. Configuration Register (CONFIG)
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Configuration Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2
5.3
5.4
Section 6. Central Processor Unit (CPU)
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .65
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Section 7. System Integration Module (SIM)
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3
7.3.1
7.3.2
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .81
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .81
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7.3.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .81
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .82
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .83
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Computer Operating Properly (COP) Reset . . . . . . . . . .85
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .86
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .87
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .87
7.5.1
7.5.2
7.5.3
7.6
7.6.1
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .93
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .93
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .94
7.6.1.1
7.6.1.2
7.6.2
7.6.2.1
7.6.2.2
7.6.3
7.6.4
7.6.5
7.7
7.7.1
7.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . .98
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . .99
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .100
7.8.1
7.8.2
7.8.3
Section 8. Oscillator (OSC)
8.1
8.2
8.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . .102
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8.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .103
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .103
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .103
External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . .103
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .104
Section 9. Monitor ROM (MON)
9.1
9.2
9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Section 10. Timer Interface Module (TIM)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
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10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .120
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .121
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .121
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .122
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .123
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .127
10.10.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . .129
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .130
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).131
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .135
Section 11. Pulse Width Modulator (PWM)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.4.1 PWM Data Registers 0 to 15 (0PWM–15PWM). . . . . . . . .140
11.4.2 PWM Control Registers 1 and 2 (PWMCR1:PWMCR2) . .141
Section 12. Analog-to-Digital Converter (ADC)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
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12.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . .148
12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
12.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .148
12.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .151
Section 13. DDC12AB Interface
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
13.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
13.5 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
13.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
13.6.1 DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . .156
13.6.2 DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . .157
13.6.3 DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . .158
13.6.4 DDC Master Control Register (DMCR) . . . . . . . . . . . . . . .159
13.6.5 DDC Status Register (DSR). . . . . . . . . . . . . . . . . . . . . . . .162
13.6.6 DDC Data Transmit Register (DDTR) . . . . . . . . . . . . . . . .164
13.6.7 DDC Data Receive Register (DDRR). . . . . . . . . . . . . . . . .165
13.7 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . .166
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Section 14. Sync Processor
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.5 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
14.5.1 Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
14.5.1.1
14.5.1.2
14.5.1.3
Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . .174
Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . .174
Composite Sync Polarity Detection . . . . . . . . . . . . . . . .174
14.5.2 Sync Signal Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
14.5.3 Polarity Controlled HSYNCO and VSYNCO Outputs. . . . .175
14.5.4 Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
14.5.5 Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . .177
14.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.6.1 Sync Processor Control & Status Register (SPCSR). . . . .177
14.6.2 Sync Processor Input/Output Control Register (SPIOCR) .179
14.6.3 Vertical Frequency Registers (VFRs). . . . . . . . . . . . . . . . .181
14.6.4 Hsync Frequency Registers (HFRs). . . . . . . . . . . . . . . . . .183
14.6.5 Sync Processor Control Register 1 (SPCR1). . . . . . . . . . .185
14.6.6 H&V Sync Output Control Register (HVOCR) . . . . . . . . . .186
14.7 System Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Section 15. Input/Output (I/O) Ports
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .194
15.3.3 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
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15.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .197
15.4.3 Port B Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .200
15.5.3 Port C Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
15.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
15.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . .203
15.6.3 Port D Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . .207
15.7.3 Port E Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Section 16. External Interrupt (IRQ)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
16.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .215
16.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .215
Section 17. Computer Operating Properly (COP)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
17.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
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17.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .220
17.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .222
Section 18. Break Module (BRK)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
18.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .226
18.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .226
18.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .226
18.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .226
18.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
18.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
18.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .227
18.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .228
18.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .228
18.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .230
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Section 19. Electrical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
19.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .232
19.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .233
19.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
19.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .234
19.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
19.10 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .237
19.11 Sync Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
19.12 DDC12AB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
19.12.1 DDC12AB Interface Input Signal Timing . . . . . . . . . . . . . .238
19.12.2 DDC12AB Interface Output Signal Timing . . . . . . . . . . . . .238
Section 20. Mechanical Specifications
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
20.3 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .240
20.4 42-Pin Shrink Dual in-Line Package (SDIP) . . . . . . . . . . . . . .241
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Te c hnic a l Da ta — MC68HC08BD24
List of Fig ure s
Figure
Title
Page
1-1
1-2
1-3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .25
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .26
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .35
5-1
5-2
Configuration Register 0 (CONFIG0) . . . . . . . . . . . . . . . . . . . .54
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .55
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .62
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
OSC Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7-10 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .90
7-11 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .93
7-12 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .93
7-13 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
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Figure
Title
Page
7-14 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .96
7-15 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .96
7-16 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7-17 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .97
7-18 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . .98
7-19 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .99
7-20 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .100
8-1
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . .102
9-1
9-2
9-3
9-4
9-5
Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .109
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
10-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10-2 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .122
10-3 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .127
10-4 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .130
10-5 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .131
10-6 TIM Channel Status and Control Registers (TSC0:TSC1) . . .132
10-7 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
10-8 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .136
11-1 PWM Data Registers 0 to 15 (0PWM–15PWM) . . . . . . . . . . .140
11-2 PWM Control Register 1 and 2 (PWMCR1:PWMCR2). . . . . .141
11-3 8-Bit PWM Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . .142
12-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
12-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .148
12-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .151
13-1 DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . . . .156
13-2 DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . . . .157
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Figure
Title
Page
13-3 DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . . . .158
13-4 DDC Master Control Register (DMCR). . . . . . . . . . . . . . . . . .159
13-5 DDC Status Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . .162
13-6 DDC Data Transmit Register (DDTR). . . . . . . . . . . . . . . . . . .164
13-7 DDC Data Receive Register (DDRR) . . . . . . . . . . . . . . . . . . .165
13-8 Data Transfer Sequences for Master/Slave
Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
14-1 Sync Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . .173
14-2 Clamp Pulse Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . .176
14-3 Sync Processor Control & Status Register (SPCSR) . . . . . . .177
14-4 Sync Processor Input/Output Control Register (SPIOCR) . . .179
14-5 Vertical Frequency High Register. . . . . . . . . . . . . . . . . . . . . .181
14-6 Vertical Frequency Low Register . . . . . . . . . . . . . . . . . . . . . .181
14-7 Hsync Frequency High Register. . . . . . . . . . . . . . . . . . . . . . .183
14-8 Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .183
14-9 Sync Processor Control Register 1 (SPCR1) . . . . . . . . . . . . .185
14-10 H&V Sync Output Control Register (HVOCR) . . . . . . . . . . . .186
15-1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .193
15-2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .194
15-3 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15-4 PWM Control Register 1 (PWMCR1) . . . . . . . . . . . . . . . . . . .195
15-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .196
15-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .197
15-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15-8 PWM Control Register 1 (PWMCR1) . . . . . . . . . . . . . . . . . . .198
15-9 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .199
15-10 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .200
15-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
15-12 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .202
15-13 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .203
15-14 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
15-15 Port D Configuration Register (PDCR) . . . . . . . . . . . . . . . . . .205
15-16 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .206
15-17 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .207
MC68HC08BD24 — Rev. 1.0
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List of Fig ure s
Figure
Title
Page
15-18 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
15-19 Configuration Register 0 (CONFIG0) . . . . . . . . . . . . . . . . . . .209
16-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .213
16-2 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .216
17-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
17-2 Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .220
17-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .221
18-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .225
18-2 Break Status and Control Register (BRKSCR). . . . . . . . . . . .227
18-3 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .228
18-4 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .228
18-5 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .229
18-6 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .230
19-1 ADC Input Voltage vs. Step Readings . . . . . . . . . . . . . . . . . .237
20-1 44-Pin QFP (Case 824E) . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
20-2 42-Pin SDIP (Case 858) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Technical Data
MC68HC08BD24 — Rev. 1.0
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List of Figures
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Te c hnic a l Da ta — MC68HC08BD24
List of Ta b le s
Table
Title
Page
1-1
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2-1
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7-1
7-2
7-3
7-4
7-5
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
SIM Registers Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .111
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .112
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .112
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .113
READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .113
RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .114
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .114
10-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .118
10-3 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10-4 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .134
11-1 PWM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .138
11-2 PWM Channels and Port I/O pins. . . . . . . . . . . . . . . . . . . . . .141
MC68HC08BD24 — Rev. 1.0
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List of Ta b le s
Table
Title
Page
12-1 ADC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12-2 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12-3 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
13-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
13-2 DDC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .155
13-3 Baud Rate Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14-2 Sync Processor I/O Register Summary . . . . . . . . . . . . . . . . .172
14-3 Sync Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
14-4 Sync Output Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
14-5 ATPOL, VINVO, and HINVO setting. . . . . . . . . . . . . . . . . . . .179
14-6 Sample Vertical Frame Frequencies . . . . . . . . . . . . . . . . . . .182
14-7 Clamp Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14-8 HSYNC Polarity Detection Pulse Width . . . . . . . . . . . . . . . . .185
14-9 ATPOL, VINVO, and HINVO setting. . . . . . . . . . . . . . . . . . . .186
14-10 Free-Running HSYNC and VSYNC Options . . . . . . . . . . . . .187
15-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .190
15-2 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .192
15-3 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
15-4 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15-5 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15-6 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
15-7 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
16-1 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .213
18-1 Break Module I/O Register Summary. . . . . . . . . . . . . . . . . . .225
Technical Data
MC68HC08BD24 — Rev. 1.0
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List of Tables
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
1.5
1.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.2 Introd uc tion
The MC68HC08BD24 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
With special modules such as the sync processor, analog-to-digital
converter, pulse modulator module, and DDC12AB interface, the
MC68HC08BD24 is designed specifically for use in digital monitor
systems.
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1.3 Fe a ture s
Features of the MC68HC08BD24 MCU include the following:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and
M68HC05 families
• Low-power design; fully static with stop and wait modes
• 5V operating voltage
• 6MHz internal bus frequency, with 24MHz external crystal
• 24,576 + 512 bytes of on-chip read-only memory (ROM)
• 512 bytes of on-chip random access memory (RAM)
• Sync signal processor with the following features:
– Horizontal and vertical frequency counters
– Low vertical frequency indicator (40.7Hz)
– Polarity controlled Hsync and Vsync outputs from separate
sync or composite sync inputs
– Internal generated free-running Hsync and Vsync pulses
– CLAMP pulse output to the external pre-amp chip
• 6-channel, 8-bit analog-to-digital converter (ADC)
• 16-channel, 8-bit pulse width modulator (PWM)
1
• DDC12AB module with the following:
– DDC1 hardware
2
– Multi-master IIC hardware for DDC2AB; with dual address
• 16-bit, 2-channel timer interface module (TIM) with selectable
input capture, output compare, and PWM capability on one
channel
1. DDC is a VESA bus standard.
2. IIC is a proprietary Philips interface bus.
Technical Data
MC68HC08BD24 — Rev. 1.0
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General Description
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General Description
MCU Block Diagram
• 32 general purpose input/output (I/O) pins, including:
– 32 shared-function I/O pins
– 4 open-drain I/O pins
• System protection features:
– Optional computer operating properly (COP) reset
– Illegal opcode detection with reset
– Illegal address detection with reset
1
• ROM security
• Master reset pin with internal pull-up and power-on reset
• IRQ with programmable pull-up and schmitt-trigger input
• 42-pin SDIP and 44-pin QFP packages
Features of the CPU08 include the following:
• Enhanced HC05 Programming Model
• Extensive Loop Control Functions
• 16 Addressing Modes (Eight More Than the HC05)
• 16-Bit Index Register and Stack Pointer
• Memory-to-Memory Data Transfers
• Fast 8 × 8 Multiply Instruction
• Fast 16/8 Divide Instruction
• Binary-Coded Decimal (BCD) Instructions
• Optimization for Controller Applications
• Third Party C Language Support
1.4 MCU Bloc k Dia g ra m
Figure 1-1 shows the structure of the MC68HC08BD24.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
MC68HC08BD24 — Rev. 1.0
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INTERNAL BUS
M68HC08 CPU
CPU
ARITHMETIC/LOGIC
UNIT (ALU)
PULSE WIDTH MODULATOR
MODULE
PTA7/PWM15–PTA0/PWM8
PTB7/PWM7–PTB0/PWM0
PTC5/ADC5–PTC0/ADC0
REGISTERS
CONTROL AND STATUS REGISTERS — 80 BYTES
USER ROM — 24,576 + 512 BYTES
USER RAM — 512 BYTES
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
MONITOR ROM — 470 BYTES
DDC12AB
INTERFACE MODULE
USER ROM VECTORS — 26 BYTES
OSC1
OSC2
‡
OSCILLATOR
‡
÷2
HSYNC
VSYNC
SYNC PROCESSOR
MODULE
PTD6
PTD5
†
†
SYSTEM INTEGRATION
MODULE
RST
IRQ
2-CHANNEL TIMER INTERFACE
MODULE
PTD4/CLAMP
PTD3/DDCSCL
†
†
EXTERNAL IRQ
MODULE
PTD2/DDCSDA
PTD1
PTD0
‡
‡
MONITOR MODULE
COMPUTER OPERATING
PROPERLY MODULE
SECURITY
MODULE
PTE2/VSYNCO
POWER-ON RESET
MODULE
PTE1/HSYNCO
PTE0/SOG/TCH0
V
V
DD
SS
POWER
MONITOR MODE ENTRY
MODULE
V
DD3
SS1
† Pin is +5V open-drain
‡ Pin is +3.3V
VOLTAGE REGULATOR
V
Figure 1-1. MCU Block Diagram
Freescale Semiconductor, Inc.
General Description
Pin Assignments
1.5 Pin Assig nm e nts
OSC2
1
PTE2/VSYNCO
PTE1/HSYNCO
PTB0/PWM0
PTB1/PWM1
PTB2/PWM2
PTB3/PWM3
PTB4/PWM4
33
OSC1
2
32
31
30
29
28
27
26
25
24
VSS
RST
3
4
PTB7/PWM7
PTB6/PWM6
PTB5/PWM5
PTC5/ADC5
PTC4/ADC4
IRQ
5
6
7
VSS1
8
NC
9
PTD2/DDCSDA
PTD3/DDCSCL
10
PTE0/SOG/TCH0
11
23
NOTE:
1. NC = No Connection
2. PTD0, PTD1, OSC1, OSC2 are 3.3V pins
Figure 1-2. 44-Pin QFP Pin Assignments
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Ge ne ra l De sc rip tion
VSYNC
VDD3
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
HSYNC
2
PTC0/ADC0
PTC1/ADC1
PTC2/ADC2
PTC3/ADC3
PTE2/VSYNCO
PTE1/HSYNCO
PTB0/PWM0
PTB1/PWM1
PTB2/PWM2
PTB3/PWM3
PTB4/PWM4
3
PD1
PD0
4
VDD
5
OSC2
6
OSC1
7
VSS
8
RST
9
PTB7/PWM7
PTB6/PWM6
PTB5/PWM5
PTC5/ADC5
PTC4/ADC4
IRQ
10
11
12
13
14
15
16
17
18
19
20
21
VSS1
PTD2/DDCSDA
PTD3/DDCSCL
PTD4/CLAMP
PTD5
PTE0/SOG/TCH0
PTA7/PWM15
PTA6/PWM14
PTA5/PWM13
PTD6
PTA0/PWM8
PTA1/PWM9
PTA2/PWM10
PTA4/PWM12
PTA3/PWM11
NOTE:
PTD0, PTD1, OSC1, OSC2 are 3.3V pins
Figure 1-3. 42-Pin SDIP Pin Assignments
Technical Data
MC68HC08BD24 — Rev. 1.0
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General Description
Pin Functions
1.6 Pin Func tions
Description of the pin functions are provided in Table 1-1.
Table 1-1. Pin Functions
PIN NAME
VDD
PIN DESCRIPTION
Power supply input to the MCU.
Power supply ground.
VSS
VDD3
VSS1
3.3V regulated output from the MCU.
Power supply ground.
Connections to the on-chip oscillator.
OSC1
OSC2
An external clock can be connected directly to
OSC1; with OSC2 floating. These are 3.3V pins.
See Section 8. Oscillator (OSC) .
A logic 0 on the RST pin forces the MCU to a
known startup state. RST is bidirectional, allowing
a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin
contains an internal pullup resistor.
RST
IRQ
See Section 7. System Integration Module
(SIM).
External IRQ pin; with software programmable
internal pull-up and schmitt trigger input.
This pin is also used for mode entry selection.
See Section 7. System Integration Module
(SIM).
Vsync input to the sync processor.
See Section 14. Sync Processor .
VSYNC
HSYNC
Hsync input to the sync processor.
See Section 14. Sync Processor .
These are shared-function pins. Each pin can be
configured as a standard I/O pin or a PWM output
PTA7/PWM15–PTA0/PWM8 channel.
See Section 15. Input/Output (I/O) Ports and
Section 11. Pulse Width Modulator (PWM) .
These are shared-function pins. Each pin can be
configured as a standard I/O pin or a PWM output
channel.
PTB7/PWM7–PTB0/PWM0
See Section 15. Input/Output (I/O) Ports and
Section 11. Pulse Width Modulator (PWM) .
MC68HC08BD24 — Rev. 1.0
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Ge ne ra l De sc rip tion
Table 1-1. Pin Functions
PIN NAME
PIN DESCRIPTION
These are shared-function pins. Each pin can be
configured as a standard I/O pin or an ADC input
channel.
PTC5/ADC5–PTC0/ADC0
See Section 15. Input/Output (I/O) Ports and
Section 12. Analog-to-Digital Converter (ADC) .
These two are standard I/O pins. These pins are
open-drain when configured as outputs.
PTD6, PTD5
See Section 15. Input/Output (I/O) Ports .
This is a shared function pin. It can be configured
as a standard I/O pin or the clamp output from the
sync processor.
PTD4/CLAMP
See Section 15. Input/Output (I/O) Ports and
Section 14. Sync Processor .
This is a shared function pin. It can be configured
as a standard I/O pin or as the clock line of the
DDC12AB module. This pin is open-drain when
configured as output.
See Section 15. Input/Output (I/O) Ports and
Section 13. DDC12AB Interface .
PTD3/DDCSCL
PTD2/DDCSDA
This is a shared function pin. It can be configured
as a standard I/O pin or the data line of the
DDC12AB module. This pin is open-drain when
configured as output.
See Section 15. Input/Output (I/O) Ports and
Section 13. DDC12AB Interface .
These are 3.3V, standard I/O pins.
See Section 15. Input/Output (I/O) Ports .
PTD1, PTD0
This is a shared function pin. It can be configured
as a standard I/O pin or the Hsync output from the
sync processor.
PTE2/VSYNCO
See Section 15. Input/Output (I/O) Ports and
Section 14. Sync Processor .
This is a shared function pin. It can be configured
as a standard I/O pin or the Vsync output from the
sync processor.
PTE1/HSYNCO
See Section 15. Input/Output (I/O) Ports and
Section 14. Sync Processor .
Technical Data
MC68HC08BD24 — Rev. 1.0
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General Description
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General Description
Pin Functions
Table 1-1. Pin Functions
PIN NAME
PIN DESCRIPTION
This is a shared function pin. It can be configured
as a standard I/O pin, the SOG input to the sync
processor, or the timer channel 0 I/O pin.
See Section 15. Input/Output (I/O) Ports ,
Section 14. Sync Processor , and Section 10.
Timer Interface Module (TIM) .
PTE0/SOG/TCH0
NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V or V ; V or V for 3.3V pins). Although the I/O
DD
SS
DD3
SS
ports of the MC68HC08BD24 do not require termination, termination is
recommended to reduce the possibility of static damage.
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Technical Data
MC68HC08BD24 — Rev. 1.0
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 2. Me m ory Ma p
2.1 Conte nts
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .31
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .32
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.2 Introd uc tion
The CPU08 can address 64 Kbytes of memory space. The memory
map, shown in Figure 2-1, includes:
• 24,576 + 512 bytes of read-only memory (ROM)
• 512 bytes of random-access memory (RAM)
• 26 bytes of user-defined vectors
• 470 bytes of monitor ROM
2.3 Unim p le m e nte d Me m ory Loc a tions
Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map
(Figure 2-1) and in register figures in this document, unimplemented
locations are shaded.
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Me m ory Ma p
2.4 Re se rve d Me m ory Loc a tions
Accessing a reserved location can have unpredictable effects on MCU
operation. In the Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Inp ut/ Outp ut (I/ O) Se c tion
Most of the control, status, and data registers are in the zero page area
of $0000–$005F. Additional I/O registers have these addresses:
• $FE00; SIM Break Status Register, SBSR
• $FE01; SIM Reset Status Register, SRSR
• $FE02; reserved
• $FE03; SIM Break Flag Control Register, SBFCR
• $FE04; Interrupt Status Register 1, INT1
• $FE05; Interrupt Status Register 2, INT2
• $FE06; reserved
• $FE07; reserved
• $FE08; reserved
• $FE09; reserved
• $FE0A; reserved
• $FE0B; reserved
• $FE0C; Break Address Register High, BRKH
• $FE0D; Break Address Register Low, BRKL
• $FE0E; Break Status and Control Register, BRKSCR
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector
locations.
Technical Data
MC68HC08BD24 — Rev. 1.0
32
Memory Map
MOTOROLA
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Input/Output (I/O) Section
$0000
I/O Registers
96 Bytes
↓
$005F
$0060
↓
Unimplemented
32 Bytes
$007F
$0080
↓
RAM
512 Bytes
$027F
$0280
↓
Unimplemented
39,296 Bytes
$9BFF
$9C00
↓
User ROM
24,576 Bytes
$FBFF
$FC00
↓
User ROM
512 Bytes
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
SIM Break Status Register (SBSR)
SIM Reset Status Register (SRSR)
Reserved
SIM Break Flag Control Register (SBFCR)
Interrupt Status Register 1 (INT1)
Interrupt Status Register 2 (INT2)
Reserved
Reserved
Reserved
Reserved
Reserved
Figure 2-1. Memory Map
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
↓
Reserved
Break Address Register High (BRKH)
Break Address Register Low (BRKL)
Break Status and Control Register (BRKSCR)
Reserved
Monitor ROM
470 Bytes
$FFE5
$FFE6
↓
User ROM Vectors
26 Bytes
$FFFF
Figure 2-1. Memory Map (Continued)
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
34
Memory Map
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Memory Map
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
PTB7
0
PTB6
0
PTB5
PTC5
PTD5
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Port C Data Register
(PTC)
0
PTD6
Port D Data Register
(PTD)
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
DDRB7
DDRB6
DDRB5
0
DDRB4
0
DDRB3
0
Data Direction Register B
(DDRB)
0
0
0
0
DDRC5
0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Data Direction Register C
(DDRC)
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
0
0
0
0
0
0
0
0
0
0
PTE2
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
0
0
0
0
0
0
0
0
DDRE2
DDRE1
0
DDRE0
0
Data Direction Register E
(DDRE)
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 12)
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Addr.
Register Name
TIM Status and Control
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
0
$000A
Register Write:
(TSC)
TRST
0
Reset:
0
0
Read:
Unimplemented Write:
Reset:
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
0
0
0
0
0
0
0
0
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register
High Write:
(TCNTH)
Reset:
Read:
Write:
Reset:
Read:
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register Low
(TCNTL)
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
Bit8
1
TIM Counter Modulo
Register High Write:
(TMODH)
Reset:
Read:
TIM Counter Modulo
Bit7
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
1
Register Low Write:
(TMODL)
Reset:
1
CH0F
0
Read:
TIM Channel 0 Status and
CH0MAX
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Control Register Write:
(TSC0)
Reset:
0
Read:
TIM Channel 0
Bit15
Bit7
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Register High Write:
(TCH0H)
Reset:
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
Read:
TIM Channel 0
Bit6
Bit5
Bit2
Bit1
Bit0
Register Low Write:
(TCH0L)
Reset:
Read:
CH1F
0
0
TIM Channel 1 Status and
CH1MAX
0
CH1IE
0
MS1A
0
ELS1B
ELS1A
TOV1
0
Control Register Write:
0
0
(TSC1)
Reset:
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12)
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Input/Output (I/O) Section
Addr.
Register Name
TIM Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$0014
Register High Write:
(TCH1H)
Reset:
Indeterminate after reset
Bit4 Bit3
Indeterminate after reset
Read:
TIM Channel 1
Register Low Write:
Bit7
Bit6
Bit5
Bit2
Bit1
Bit0
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
(TCH1L)
Reset:
Read:
ALIF
0
NAKIF
0
BB
0
MAST
0
MRW
0
BR2
0
BR1
0
BR0
0
DDC Master Control
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Register (DMCR)
EXTAD
DAD7
1
DAD6
0
DAD5
DAD4
DAD3
0
DAD2
0
DAD1
0
DDC Address Register
(DADR)
1
0
0
0
0
0
DEN
DIEN
TXAK
SCLIEN DDC1EN
DDC Control Register
(DCR)
0
RXIF
0
0
TXIF
0
0
0
0
0
0
0
MATCH
SRW
RXAK
SCLIF
TXBE
RXBF
DDC Status Register
(DSR)
0
0
0
0
0
0
1
1
0
DDC
DTD7
DTD6
DTD5
DTD4
DTD3
DTD2
DTD1
DTD0
Data Transmit Register Write:
(DDTR)
Reset:
1
1
1
1
1
1
1
1
DDC Read:
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
Data Receive Register
Write:
(DDRR)
Reset:
Read:
0
D2AD7
0
0
D2AD6
0
0
D2AD5
0
0
0
0
0
0
0
D2AD4
D2AD3
D2AD2
D2AD1
DDC2 Address Register
Write:
(D2ADR)
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
HSYNCOE VSYNCOE
SOGE
Configuration Register 0
Write:
(CONFIG0)
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 12)
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Addr.
Register Name
Bit 7
6
5
4
3
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
0
IRQF
IRQ Status and Control
Register (INTSCR)
$001E
ACK
0
0
0
0
0
0
0
0
0
0
SSREC
0
COPRS
0
STOP
0
COPD
0
Configuration Register 1
$001F
†
(CONFIG1)
0
0
0
0
† One-time writable register after each reset.
Read:
0PWM4
0PWM3
0PWM2
0PWM1
0PWM0
0BRM2
0BRM1
0BRM0
PWM0 Data Register
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
(0PWM)
0
0
0
0
0
0
0
0
1PWM4
1PWM3
1PWM2
1PWM1
1PWM0
1BRM2
1BRM1
1BRM0
PWM1 Data Register
(1PWM)
0
0
0
0
0
0
2BRM2
0
0
0
2PWM4
2PWM3
2PWM2
2PWM1
2PWM0
2BRM1
2BRM0
PWM2 Data Register
(2PWM)
0
0
0
0
0
3PWM0
0
0
0
3PWM4
3PWM3
3PWM2
3PWM1
3BRM2
0
3BRM1
3BRM0
PWM3 Data Register
(3PWM)
0
0
0
0
0
0
4PWM4
4PWM3
4PWM2
4PWM1
4PWM0
0
4BRM2
0
4BRM1
4BRM0
PWM4 Data Register
(4PWM)
0
0
0
0
0
0
5PWM4
5PWM3
5PWM2
5PWM1
5PWM0
0
5BRM2
0
5BRM1
5BRM0
PWM5 Data Register
(5PWM)
0
0
0
0
0
6BRM1
0
0
6BRM0
0
6PWM4
6PWM3
6PWM2
6PWM1
6PWM0
0
6BRM2
0
PWM6 Data Register
(6PWM)
0
7PWM4
0
0
7PWM3
0
0
7PWM2
0
0
7PWM1
0
7PWM0
7BRM2
7BRM1
0
7BRM0
0
PWM7 Data Register
(7PWM)
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12)
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
PWM7E
PWM6E
PWM5E
PWM4E
PWM3E
PWM2E
PWM1E
PWM0E
PWM Control Register 1
(PWMCR1)
$0028
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 12)
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Reserved Write:
Reset:
R
R
R
R
R
R
R
R
$0032
Read:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12)
Technical Data
MC68HC08BD24 — Rev. 1.0
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Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
R
R
R
R
R
R
R
$003C
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
$003D
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
Reserved Write:
Reset:
Read:
R
R
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
Reserved Write:
Reset:
Read:
VSIF
VPOL
HPOL
Sync Processor Control
VSIE
VEDGE
COMP
VINVO
HINVO
and Status Register Write:
0
0
(SPCSR)
Reset:
0
0
0
0
0
0
0
0
Read:
VOF
0
VF12
VF11
VF10
VF9
VF8
Vertical Frequency High
Register Write:
CPW1
0
CPW0
0
(VFHR)
Reset:
0
0
0
0
0
0
Read:
VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Vertical Frequency Low
Register Write:
(VFLR)
Reset:
0
0
0
0
0
0
0
0
Read:
HFH7
HFH6
HFH5
HFH4
HFH3
HFH2
HFH1
HFH0
Hsync Frequency High
Register Write:
(HFHR)
Reset:
0
0
0
0
0
0
0
0
0
0
Read: HOVER
HFL4
HFL3
HFL2
HFL1
HFL0
Hsync Frequency Low
Register Write:
(HFLR)
Reset:
0
0
0
COINV
0
0
R
0
0
0
0
BPOR
0
0
SOUT
0
Read: VSYNCS HSYNCS
Sync Processor I/O
CLAMPOE
SOGSEL
Control Register Write:
(SPIOCR)
Reset:
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 12)
MC68HC08BD24 — Rev. 1.0
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Me m ory Ma p
Addr.
Register Name
Sync Processor Control
Bit 7
6
5
4
3
2
R
0
1
ATPOL
0
Bit 0
FSHF
0
Read:
LVSIF
LVSIE
HPS1
HPS0
R
$0046
Register 1 Write:
(SPCR1)
0
0
0
Reset:
0
R
0
0
0
0
0
0
0
Read:
H&V Sync Output Control
HVOCR2 HVOCR1 HVOCR0
$0047
$0048
$0049
$004A
$004B
$004C
$004D
$004E
$004F
Register Write:
(HVOCR)
Reset:
0
0
0
0
0
0
0
Read:
Unimplemented Write:
Reset:
Read:
0
0
0
0
0
DDCSCLE DDCDATE
CLAMPE
Port D Configuration
Write:
Register (PDCR)
Reset:
Read:
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
R
R
R
Reserved Write:
Reset:
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12)
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
$0050
Unimplemented Write:
Reset:
Read:
8PWM4
8PWM3
8PWM2
8PWM1
8PWM0
8BRM2
8BRM1
8BRM0
PWM8 Data Register
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
(8PWM)
0
9PWM4
0
0
9PWM3
0
0
9PWM2
0
0
9PWM1
0
0
9PWM0
0
0
9BRM2
0
0
9BRM1
0
0
9BRM0
0
PWM9 Data Register
(9PWM)
10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0
PWM10 Data Register
(10PWM)
0
0
0
0
0
0
0
0
11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0
PWM11 Data Register
(11PWM)
0
0
0
0
0
0
0
0
12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0
PWM12 Data Register
(12PWM)
0
0
0
0
0
0
0
0
13PWM4 13PWM3 13PWM2 13PWM1 13PWM0 13BRM2 13BRM1 13BRM0
PWM13 Data Register
(13PWM)
0
14PWM4
0
0
PWM3
0
0
0
0
0
0
0
14PWM2 14PWM1 14PWM0 14BRM2 14BRM1 14BRM0
PWM14 Data Register
(14PWM)
0
0
0
0
0
0
15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0
PWM15 Data Register
(15PWM)
0
0
0
0
0
0
0
0
PWM8E
0
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E
PWM Control Register 2
(PWMCR2)
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 12)
MC68HC08BD24 — Rev. 1.0
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Me m ory Ma p
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Unimplemented Write:
Reset:
$005A
Read:
$005B
$005C
$005D
$005E
$005F
Unimplemented Write:
Reset:
Read:
Unimplemented Write:
Reset:
Read: COCO
Write:
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Status and Control
Register (ADSCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
0
1
1
1
1
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
(ADR)
Unaffected after Reset
0
0
0
0
0
0
0
0
ADIV2
0
ADIV1
0
ADIV0
0
ADC Input Clock Register
(ADICLK)
0
0
Read:
Write:
Reset:
SBSW
Note
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
SIM Break Status Register
(SBSR)
$FE00
Note: Writing a logic 0 clears SBSW.
Read:
Write:
POR:
Read:
POR
PIN
COP
ILOP
ILAD
0
0
0
SIM Reset Status Register
$FE01
(SRSR)
1
R
0
0
R
0
0
R
0
0
R
0
0
0
0
R
0
0
R
0
R
R
$FE02
Reserved Write:
Reset:
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12)
Technical Data
MC68HC08BD24 — Rev. 1.0
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Memory Map
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
0
IF6
R
0
IF5
R
0
IF4
R
0
IF3
R
0
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1)
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
0
0
0
0
0
0
0
0
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2)
R
0
R
0
R
0
R
0
0
0
0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Reserved Write:
Reset:
Read:
R
R
R
R
R
R
R
0
R
0
Reserved Write:
Reset:
0
0
0
0
0
0
Read:
R
R
R
R
R
R
R
0
R
0
Reserved Write:
Reset:
0
0
0
0
0
0
Read:
R
R
R
R
R
R
R
0
R
0
Reserved Write:
Reset:
0
0
0
0
0
0
Read:
R
R
R
R
R
R
R
0
R
0
Reserved Write:
Reset:
0
0
0
0
0
0
Read:
R
R
R
R
R
R
R
0
R
0
Reserved Write:
Reset:
0
0
0
0
0
0
Read:
Bit15
0
Bit14
Bit13
Bit12
0
Bit11
Bit10
Bit9
0
Bit8
0
Break Address High
Write:
Register (BRKH)
Reset:
0
0
0
0
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 12)
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Me m ory Ma p
Addr.
Register Name
Bit 7
Bit7
0
6
Bit6
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Break Address low
Register (BRKL)
$FE0D
0
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
BRKA
0
Break Status and Control
Register (BRKSCR)
$FE0E
$FFFF
0
0
0
0
0
0
Read:
Write:
Reset:
Low byte of reset vector
COP Control Register
(COPCTL)
Writing clears COP counter (any value)
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12)
Technical Data
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Memory Map
Input/Output (I/O) Section
.
Table 2-1. Vector Addresses
VectorPriority Vector Address
Lowest
Vector
$FFE6
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Reserved
Reserved
—
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
—
ADC Interrupt Vector (High)
ADC Interrupt Vector (Low)
Reserved
Reserved
Sync Processor Vector (High)
Sync Processor Vector (Low)
TIM Overflow Vector (High)
TIM Overflow Vector (Low)
TIM Channel 1 Vector (High)
TIM Channel 1 Vector (Low)
TIM Channel 0 Vector (High)
TIM Channel 0 Vector (Low)
Reserved
Reserved
DDC12AB Vector (High)
DDC12AB Vector (Low)
Reserved
Reserved
IRQ Vector (High)
IRQ Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
—
Highest
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Memory Map
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 3. Ra nd om -Ac c e ss Me m ory (RAM)
3.1 Conte nts
3.2
3.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2 Introd uc tion
This section describes the 512 bytes of RAM (random-access memory).
3.3 Func tiona l De sc rip tion
Addresses $0080 through $027F are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 128 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
NOTE: For M6805 compatibility, the H register is not stacked.
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Ra nd om -Ac c e ss Me m ory (RAM)
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
Technical Data
MC68HC08BD24 — Rev. 1.0
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Random-Access Memory (RAM)
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Se c tion 4. Re a d -Only Me m ory (ROM)
4.1 Conte nts
4.2
4.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.2 Introd uc tion
This section describes the 25,088 bytes of ROM (read-only memory).
4.3 Func tiona l De sc rip tion
These addresses are user ROM locations:
$9C00 – $FBFF (24,576 bytes)
$FC00 – $FDFF (512 bytes)
$FFE6 – $FFFF (These locations are reserved for user-defined interrupt
and reset vectors.)
1
NOTE: A security feature prevents viewing of the ROM contents.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM contents difficult for unauthorized users.
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Re a d -Only Me m ory (ROM)
Technical Data
MC68HC08BD24 — Rev. 1.0
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Read-Only Memory (ROM)
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Se c tion 5. Config ura tion Re g iste r (CONFIG)
5.1 Conte nts
5.2
5.3
5.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Configuration Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Configuration Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2 Introd uc tion
This section describes the configuration registers, CONFIG0 and
CONFIG1. The configuration registers enable or disable these options:
• Sync processor HSYNCO output pin
• Sync processor VSYNCO output pin
• Sync processor SOG input pin
• Stop mode recovery time (32 OSCXCLK cycles or 4096
OSCXCLK cycles)
18
4
13
4
• COP timeout period (2 – 2 or 2 – 2 OSCXCLK cycles)
• STOP instruction
• Computer operating properly module (COP)
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Config ura tion Re g iste r (CONFIG)
5.3 Config ura tion Re g iste r 0
The CONFIG0 register is used to select the I/O pins for sync processor
output functions.
Address:
$001D
Bit 7
6
5
SOGE
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
HSYNCOE VSYNCOE
0
0
0
0
0
0
0
= Unimplemented
Figure 5-1. Configuration Register 0 (CONFIG0)
HSYNCOE — VSYNCO Enable
This bit is set to configure the PTE1/HSYNCO pin for HSYNCO output
function. Reset clears this bit.
1 = PTE1/HSYNCO pin configured as HSYNCO pin
0 = PTE1/HSYNCO pin configured as standard I/O pin
VSYNCOE — VSYNCO Enable
This bit is set to configure the PTE2/VSYNCO pin for VSYNCO output
function. Reset clears this bit.
1 = PTE2/VSYNCO pin configured as VSYNCO pin
0 = PTE2/VSYNCO pin configured as standard I/O pin
SOGE — SOG Enable
This bit is set to configure the PTE0/SOG/TCH0 pin for SOG output
function. Reset clears this bit.
1 = PTE0/SOG/TCH0 pin configured as SOG pin
0 = PTE0/SOG/TCH0 pin configured as standard I/O or TCH0 pin.
TCH0 function is configured by ELS0B and ELS0A bits in
TSC0 (bits 3 and 2 in $0010). (See 10.10.4 TIM Channel
Status and Control Registers (TSC0:TSC1).)
Technical Data
MC68HC08BD24 — Rev. 1.0
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Configuration Register (CONFIG)
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Configuration Register (CONFIG)
Configuration Register 1
5.4 Config ura tion Re g iste r 1
The CONFIG1 register is used in the initialization of various MCU
options. It can only be written once after each reset. All of the CONFIG1
register bits are cleared during reset. Since the various options affect the
operation of the MCU, it is recommended that the CONFIG1 register be
written immediately after reset.
Address:
$001F
Bit 7
0
6
0
5
0
4
0
3
SSREC
0
2
COPRS
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
0
0
0
0
Register is write-once after reset.
= Unimplemented
Figure 5-2. Configuration Register 1 (CONFIG1)
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
OSCXCLK cycles instead of a 4096-OSCXCLK cycle delay.
1 = Stop mode recovery after 32 OSCXCLK cycles
0 = Stop mode recovery after 4096 OSCXCLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 17. Computer Operating Properly (COP).)
13
4
1 = COP timeout period = 2 – 2 CGMXCLK cycles
18
4
0 = COP timeout period = 2 – 2 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
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Config ura tion Re g iste r (CONFIG)
COPD — COP Disable Bit
COPD disables the COP module. (See Section 17. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Technical Data
MC68HC08BD24 — Rev. 1.0
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Configuration Register (CONFIG)
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Se c tion 6. Ce ntra l Proc e ssor Unit (CPU)
6.1 Conte nts
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .65
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.2 Introd uc tion
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
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Ce ntra l Proc e ssor Unit (CPU)
6.3 Fe a ture s
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 6-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
6.4 CPU Re g iste rs
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
Technical Data
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Central Processor Unit (CPU)
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Central Processor Unit (CPU)
CPU Registers
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Ac c um ula tor
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
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Ce ntra l Proc e ssor Unit (CPU)
6.4.2 Ind e x Re g iste r
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Sta c k Pointe r
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Technical Data
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Central Processor Unit (CPU)
CPU Registers
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 6-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Prog ra m Counte r
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
Bit
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
6.4.5 Cond ition Cod e Re g iste r
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
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5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
1
1
5
1
1
4
H
X
3
I
2
N
X
1
Z
X
Bit 0
Read:
Write:
Reset:
V
C
X
X
1
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
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CPU Registers
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
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C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithm e tic / Log ic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
6.6.1 Wa it Mod e
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
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CPU During Break Interrupts
6.6.2 Stop Mod e
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Bre a k Inte rrup ts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruc tion Se t Sum m a ry
6.9 Op c od e Ma p
See Table 6-2.
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Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H
I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
SP1
SP2
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
SP1
SP2
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7
AF
ii
ii
2
2
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Logical AND
A ← (A) & (M)
0
–
–
–
↕ ↕ –
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
↕ –
↕ ↕ ↕
C
0
b7
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
4
1
1
4
3
5
C
Arithmetic Shift Right
↕ –
–
–
↕ ↕ ↕
ff
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
–
–
– REL
DIR (b0)
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
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Opcode Map
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
BCS rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25
27
rr
rr
3
3
BEQ rel
BGE opr
Branch if Greater Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (N V) = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90
92
rr
rr
3
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BGT opr
3
3
0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28
29
22
rr
rr
rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24
rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F
2E
rr
rr
3
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Bit Test
(A) & (M)
0
–
–
↕ ↕ –
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BLE opr
–
–
–
–
–
– REL
93
rr
3
1
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25
23
91
2C
2B
2D
26
2A
20
rr
rr
rr
rr
rr
rr
rr
rr
rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N V) =1
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
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Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↕
BRN rel
Branch Never
PC ← (PC) + 2
– REL
DIR (b0)
21
rr
3
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSET n,opr
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD
rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
31
41
51
61
71
dd rr
ii rr
ii rr
ff rr
rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IX1+
Compare and Branch if Equal
–
IX+
SP1
CBEQ opr,SP,rel
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
– INH
IX1
IX
3F
4F
5F
8C
6F
7F
dd
ff
3
1
1
1
3
2
4
Clear
0
–
–
0
1
CLR opr,SP
SP1
9E6F ff
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Opcode Map
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Compare A with M
(A) – (M)
↕ –
–
↕ ↕ ↕
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
4
1
1
4
3
5
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
↕ ↕ 1
SP1
9E63 ff
CPHX #opr
CPHX opr
IMM
DIR
65
75
ii ii+1
dd
3
4
(H:X) – (M:M + 1)
↕ –
↕ ↕ ↕
CPX #opr
CPX opr
CPX opr
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
CPX ,X
Compare X with M
(X) – (M)
↕ –
–
–
–
↕ ↕ ↕
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
(A)
U –
↕ ↕ ↕ INH
72
2
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) –
1
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
– INH
IX1
IX
SP1
3B
4B
5B
6B
7B
dd rr
rr
rr
ff rr
rr
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
Decrement and Branch if Not Zero
–
–
–
–
9E6B ff rr
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
4
1
1
4
3
5
Decrement
Divide
↕ –
–
–
↕ ↕ –
SP1
9E6A ff
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
–
↕ ↕ INH
52
7
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Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Exclusive OR M with A
A ← (A M)
0
–
–
↕ ↕ –
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
4
1
1
4
3
5
Increment
↕ –
–
↕ ↕ –
SP1
9E6C ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
IX
BC
CC
DC
EC
FC
dd
2
3
4
3
2
hh ll
ee ff
ff
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD
CD
DD
ED
FD
dd
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
hh ll
ee ff
ff
Jump to Subroutine
IX
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
DIR
45
55
ii jj
dd
3
4
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
SP1
SP2
9EEE ff
9EDE ee ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
4
1
1
4
3
5
Logical Shift Left
(Same as ASL)
C
0
↕ –
–
↕ ↕ ↕
b7
b0
SP1
9E68 ff
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
70
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
4
1
1
4
3
5
0
C
Logical Shift Right
↕ –
–
0 ↕ ↕
b7
b0
LSR opr,SP
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
4
4
4
(M)
← (M)
Source
Destination
DIX+
IMD
IX+D
Move
0
–
–
0
–
–
↕ ↕ –
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
SP1
9E60 ff
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
1
3
A ← (A[3:0]:A[7:4])
62
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
4
1
1
4
3
5
C
Rotate Left through Carry
↕ –
–
↕ ↕ ↕
b7
b0
SP1
9E69 ff
MC68HC08BD24 — Rev. 1.0
MOTOROLA
Technical Data
Central Processor Unit (CPU)
71
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Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
4
1
1
4
3
5
C
Rotate Right through Carry
↕ –
–
–
↕ ↕ ↕
b7
b0
ROR opr,SP
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕ ↕ ↕ ↕ ↕ ↕ INH
80
81
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
– INH
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
A ← (A) – (M) – (C)
↕ –
↕ ↕ ↕
SP1
SP2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
STA opr
DIR
EXT
IX2
B7
C7
D7
E7
F7
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
STOP
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
↕ ↕ – DIR
35
8E
dd
4
1
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
–
– INH
STX opr
STX opr
DIR
EXT
IX2
BF
CF
DF
EF
FF
dd
3
4
4
3
2
4
5
hh ll
ee ff
ff
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
9EEF ff
9EDF ee ff
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
72
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
I
N Z C
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
2
3
4
4
3
2
4
5
dd
hh ll
ee ff
ff
Subtract
A ← (A) – (M)
↕ –
–
↕ ↕ ↕
SP1
SP2
9EE0 ff
9ED0 ee ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
– INH
– INH
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
3
1
1
3
2
4
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
↕ ↕ –
SP1
9E6D ff
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
MC68HC08BD24 — Rev. 1.0
MOTOROLA
Technical Data
Central Processor Unit (CPU)
73
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Ce ntra l Proc e ssor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
I N Z C
A
C
Accumulator
Carry/borrow bit
n
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DD Direct to direct addressing mode
DIR Direct addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
DIX+ Direct to indexed with post increment addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
ff
H
H
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMD Immediate source to direct destination addressing mode
IMM Immediate addressing mode
INH Inherent addressing mode
( )
IX
Indexed, no offset addressing mode
–( ) Negation (two’s complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
Sign extend
Loaded with
If
IX+D Indexed with post increment to direct addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
«
←
?
IX2
M
N
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
:
↕
—
Concatenated with
Set or cleared
Not affected
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
74
Central Processor Unit (CPU)
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Table 6-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
2
IX1 3 SP1 1 IX
5
1
1
INH
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2 2 IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1 1 IX
3
BRN
REL 3 DIR
3
BHI
REL
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
3
BEQ
REL 2 DIR
3
5
4
4
6
4
4
3
BLT
2
CMP
3
CMP
4
CMP
EXT 3 IX2
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
CMP
5
CMP
SP2 2 IX1
5
SBC
SP2 2 IX1
5
CPX
SP2 2 IX1
5
AND
SP2 2 IX1
5
BIT
SP2 2 IX1
5
LDA
SP2 2 IX1
5
STA
SP2 2 IX1
5
EOR
SP2 2 IX1
3
CMP
4
CMP
SP1 1 IX
4
SBC
SP1 1 IX
4
CPX
SP1 1 IX
4
AND
SP1 1 IX
4
BIT
SP1 1 IX
4
LDA
SP1 1 IX
4
STA
SP1 1 IX
4
EOR
SP1 1 IX
2
CMP
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
CBEQ
RTS
3
DIR
5
2
DIR
4
3
1
IMM 3 IMM 3 IX1+
4
SP1 2 IX+
INH
REL 2 IMM 2 DIR
5
7
3
2
DAA
3
BGT
2
SBC
3
SBC
4
SBC
3
SBC
2
SBC
BRSET1 BSET1
MUL
DIV
INH
NSA
3
DIR
5
2
DIR
4
INH
1
1
2
2
3
2
2
2
2
2
INH
1
INH
3
REL 2 IMM 2 DIR
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
3
BLE
2
CPX
3
CPX
4
CPX
3
CPX
2
CPX
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
COM
SWI
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1 1 IX
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
4
LSR
1
LSRA
INH
1
LSRX
INH
5
LSR
SP1 1 IX
3
LSR
2
2
2
AND
IMM 2 DIR
3
AND
4
AND
3
AND
2
AND
4
BRSET2 BSET2
TAP
TXS
3
DIR
5
2
DIR
4
1
3
1
INH
INH
2
2
2
2
2
2
2
2
4
3
4
4
1
2
2
BIT
3
BIT
4
BIT
3
BIT
2
BIT
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
CPHX
TPA
TSX
3
DIR
5
2
DIR
4
IMM 2 DIR
2
DIR
3
INH
INH
IMM 2 DIR
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
LDA
4
LDA
3
LDA
2
LDA
6
BRSET3 BSET3
RORA
RORX
ROR
SP1 1 IX
5
ASR
SP1 1 IX
5
LSL
SP1 1 IX
5
ROL
SP1 1 IX
ROR
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
3
ASR
1
3
STA
4
STA
3
STA
2
STA
7
BRCLR3 BCLR3
TAX
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INH
4
LSL
3
LSL
1
3
EOR
4
EOR
3
EOR
2
EOR
8
BRSET4 BSET4 BHCC
CLC
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
INH
4
ROL
3
ROL
1
3
ADC
4
ADC
5
ADC
SP2 2 IX1
5
ORA
SP2 2 IX1
5
ADD
SP2 2 IX1
3
ADC
4
ADC
SP1 1 IX
4
ORA
SP1 1 IX
4
ADD
SP1 1 IX
2
ADC
9
BRCLR4 BCLR4 BHCS
SEC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
INH
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
3
BMC
REL 2 DIR
3
BMS
REL 2 DIR
3
BIL
4
DEC
5
DEC
SP1 1 IX
3
DEC
2
CLI
INH
2
SEI
INH
3
ORA
4
ORA
3
ORA
2
ORA
B
C
D
E
F
BRSET5 BSET5
3
DIR
5
2
DIR
4
5
3
3
5
6
4
3
ADD
4
ADD
3
ADD
2
ADD
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
DBNZ
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
INC
IX1
3
TST
IX1
4
MOV
IMD
3
CLR
IX1
SP1 2 IX
4
INC
5
INC
SP1 1 IX
4
TST
SP1 1 IX
3
INC
1
2
JMP
4
JMP
3
JMP
2
BRSET6 BSET6
INCA
INCX
RSP
JMP
3
DIR
5
2
DIR
4
INH
1
TSTA
INH
5
MOV
DD
1
CLRA
INH
INH
1
TSTX
INH
4
MOV
DIX+
1
CLRX
INH
INH
2
DIR
4
2
2
IX1
5
1
1
IX
3
TST
2
TST
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
4
JSR
IX
2
LDX
BRCLR6 BCLR6
NOP
JSR
JSR
3
DIR
5
2
DIR
4
INH
2
2
2
IX1
3
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
LDX
SP2 2 IX1
5
STX
SP2 2 IX1
4
LDX
SP1 1 IX
4
STX
SP1 1 IX
BRSET7 BSET7
MOV
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
BIH
2
IX+D
1
1
4
4
3
3
3
CLR
4
CLR
SP1 1 IX
2
CLR
3
STX
4
STX
3
STX
2
STX
BRCLR7 BCLR7
DIR DIR
3
2
REL 2 DIR
3
1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
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Ce ntra l Proc e ssor Unit (CPU)
Technical Data
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 7. Syste m Inte g ra tion Mod ule (SIM)
7.1 Conte nts
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .81
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .81
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .81
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .82
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .83
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Computer Operating Properly (COP) Reset . . . . . . . . . .85
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .86
7.5
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .86
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .87
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .87
7.5.1
7.5.2
7.5.3
7.6
7.6.1
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .93
Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .93
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .94
7.6.1.1
7.6.1.2
7.6.2
7.6.2.1
7.6.2.2
7.6.3
7.6.4
7.6.5
7.7
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
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Syste m Inte g ra tion Mod ule (SIM)
7.7.1
7.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.8
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . .98
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . .99
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . .100
7.8.1
7.8.2
7.8.3
7.2 Introd uc tion
This section describes the system integration module, which supports up
to 16 external and/or internal interrupts. Together with the CPU, the SIM
controls all MCU activities. A block diagram of the SIM is shown in
Figure 7-1. Table 7-1 shows a summary of the SIM I/O registers. The
SIM is a system state controller that coordinates CPU and exception
timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
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System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
OSCXCLK (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
÷
2
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
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Table 7-1. SIM I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
SBSW
Note
0
Bit 0
Read:
Write:
Reset:
Read:
Write:
POR:
R
R
R
R
R
R
R
SIM Break Status Register
(SBSR)
$FE00
0
0
0
0
0
0
0
0
0
POR
PIN
COP
ILOP
ILAD
0
SIM Reset Status
Register (SRSR)
$FE01
$FE03
$FE04
$FE05
1
0
0
0
0
0
0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
BCFE
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
0
IF6
R
0
IF5
R
0
IF4
R
0
IF3
R
0
IF2
R
IF1
0
R
0
R
Interrupt Status Register 1
(INT1)
R
0
0
0
0
0
0
0
0
IF10
R
IF9
IF8
R
IF7
R
Interrupt Status Register 2
(INT2) Write:
R
0
R
0
R
0
R
0
R
Reset:
0
0
0
0
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Table 7-2 shows the internal signal names used in this section.
Table 7-2. Signal Name Conventions
Signal Name
Description
OSCXCLK
Buffered version of OSC1 from the oscillator
The OSCXCLK frequency divided by two. This signal is again
divided by two in the SIM to generate the internal bus clocks.
(Bus clock = OSCXCLK divided by four)
OSCOUT
IAB
IDB
Internal address bus
Internal data bus
PORRST
IRST
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
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System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3 SIM Bus Cloc k Control a nd Ge ne ra tion
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-2.
From
SIM
OSCXCLK
SIM COUNTER
OSCOUT
BUS CLOCK
÷
2
÷ 2
GENERATORS
SIMOSCEN
OSCILLATOR
SIM
OSC1
OSC2
Figure 7-2. OSC Clock Signals
7.3.1 Bus Tim ing
In user mode, the internal bus frequency is the oscillator frequency
(OSCXCLK) divided by four.
7.3.2 Cloc k Sta rt-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 OSCXCLK cycle POR timeout has completed. The RST is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the timeout.
7.3.3 Cloc ks in Stop Mod e a nd Wa it Mod e
Upon exit from stop mode (by an interrupt, break, or reset), the SIM
allows OSCXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 OSCXCLK cycles. (See 7.7.2 Stop
Mode.)
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In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Re se t a nd Syste m Initia liza tion
The MCU has the following reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR) (see 7.8 SIM Registers).
7.4.1 Exte rna l Pin Re se t
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 OSCXCLK cycles, assuming that the POR was the
source of the reset (see Table 7-3. PIN Bit Set Timing). Figure 7-3
shows the relative timing.
Table 7-3. PIN Bit Set Timing
Reset Type
POR
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
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System Integration Module (SIM)
Reset and System Initialization
OSCOUT
RST
VECT H VECT L
IAB
PC
Figure 7-3. External Reset Timing
7.4.2 Ac tive Re se ts from Inte rna l Sourc e s
SIM module in HC08 has the capability to drive the RST pin low when
internal reset events occur.
All internal reset sources actively pull the RST pin low for 32 OSCXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see Figure 7-
4. Internal Reset Timing). An internal reset can be caused by an illegal
address, illegal opcode, COP timeout, or POR (see Figure 7-5. Sources
of Internal Reset). Note that for POR resets, the SIM cycles through
4096 OSCXCLK cycles during which the SIM forces the RST pin low.
The internal reset signal then follows the sequence from the falling edge
of RST shown in Figure 7-4.
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
OSCXCLK
IAB
VECTOR HIGH
Figure 7-4. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
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Syste m Inte g ra tion Mod ule (SIM)
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
INTERNAL
RESET
POR
Figure 7-5. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.4.2.1 Po we r-On Re se t
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive OSCXCLK.
• Internal clocks to the CPU and modules are held inactive for 4096
OSCXCLK cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
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System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
OSCXCLK
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 7-6. POR Recovery
7.4.2.2 Co m p ute r Op e ra ting Pro p e rly (COP) Re se t
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
12
4
2 – 2 OSCXCLK cycles, drives the COP counter. The COP should be
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ is held at V
TST
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST pin or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
on the
TST
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7.4.2.3 Ille g a l Op c o d e Re se t
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the configure register 1 (CONFIG1) is
logic zero, the SIM treats the STOP instruction as an illegal opcode and
causes an illegal opcode reset. The SIM actively pulls down the RST pin
for all internal reset sources.
7.4.2.4 Ille g a l Ad d re ss Re se t
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
7.5 SIM Counte r
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of OSCXCLK.
7.5.1 SIM Counte r During Powe r-On Re se t
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
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Exception Control
7.5.2 SIM Counte r During Stop Mod e Re c ove ry
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configure register 1 (CONFIG1). If the SSREC bit is a logic one, then the
stop recovery is reduced from the normal delay of 4096 OSCXCLK
cycles down to 32 OSCXCLK cycles. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared.
7.5.3 SIM Counte r a nd Re se t Sta te s
External reset has no effect on the SIM counter (see 7.7.2 Stop Mode).
The SIM counter is free-running after all reset states (see 7.4.2 Active
Resets from Internal Sources for counter control and internal reset
recovery sequences).
7.6 Exc e p tion Control
Normally, sequential program execution can be changed in three
different ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
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Syste m Inte g ra tion Mod ule (SIM)
7.6.1 Inte rrup ts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-9 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-7 shows interrupt entry timing. Figure
7-8 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
IDB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L
START ADDR
DUMMY
PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 7-7.Interrupt Entry
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE
OPERAND
R/W
Figure 7-8. Interrupt Recovery
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Exception Control
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
IRQ
YES
YES
INTERRUPT?
NO
DDC12AB
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(As many interrupts as exist on chip)
FETCH NEXT
INSTRUCTION.
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 7-9. Interrupt Processing
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Syste m Inte g ra tion Mod ule (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). (See Figure
7-9. Interrupt Processing.)
7.6.1.1 Ha rd wa re Inte rrup ts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-10
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-10.Interrupt Recognition Example
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Exception Control
The LDA opcode is pre-fetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI pre-fetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
7.6.1.2 SWI Instruc tio n
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Inte rrup t Sta tus Re g iste rs
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-4 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
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Table 7-4. Interrupt Sources
INTRegister
1
2
Source
Flag
Vector Address
Mask
Priority
Flag
None
None
IF1
Reset
None
None
IRQF
—
None
None
IMASK
—
0
0
1
2
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF8–$FFF9
SWI Instruction
IRQ pin
Reserved
—
ALIF
NAKIF
RXIF
TXIF
SCLIF
—
DIEN
DDC12AB
IF3
3
$FFF6–$FFF7
SCLIEN
—
Reserved
—
4
5
6
7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
$FFEE–$FFEF
TIM channel 0
TIM channel 1
TIM overflow
CH0F
CH1F
TOF
VSIF
LVSIF
—
CH0IE
CH1IE
TOIE
VSIE
LVSIE
—
IF5
IF6
IF7
Sync processor
IF8
8
$FFEC–$FFED
Reserved
—
IF10
—
9
$FFEA–FFEB
$FFE8–$FFE9
$FFE6–$FFE7
ADC conversion complete
Reserved
COCO
—
AIEN
—
10
—
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
2. 0 = highest priority
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Exception Control
7.6.2.1 Inte rrup t Sta tus Re g iste r 1
Address:
$FE04
Bit 7
IF6
R
6
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF5
R
R
0
R
0
0
0
0
0
0
0
R
= Reserved
Figure 7-11. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-4.
1 = Interrupt request present
0 = No interrupt request present
Bit 1and Bit 0 — Always read 0
7.6.2.2 Inte rrup t Sta tus Re g iste r 2
Address:
$FE05
Bit 7
0
6
5
0
4
0
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
0
R
R
R
0
R
0
0
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 2 (INT2)
IF10–IF7 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-4.
1 = Interrupt request present
0 = No interrupt request present
Bit 7 and Bit 4 — Always read 0
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7.6.3 Re se t
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.6.4 Bre a k Inte rrup ts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output (see
Section 18. Break Module (BRK)). The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
7.6.5 Sta tus Fla g Prote c tion in Bre a k Mod e
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the
flag as normal.
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System Integration Module (SIM)
Low-Power Modes
7.7 Low-Powe r Mod e s
Executing the WAIT or STOP instruction puts the MCU in a low-power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
7.7.1 Wa it Mod e
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-13 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in
configuration register 1 (CONFIG1) is logic zero, then the computer
operating properly module (COP) is enabled and remains active in wait
mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 7-13. Wait Mode Entry Timing
Figure 7-14 and Figure 7-15 show the timing for WAIT recovery.
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IAB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-14. Wait Recovery from Interrupt or Break
32
Cycles
32
Cycles
IAB
IDB
$6E0B
$A6
RST VCT H RST VCT L
$A6
$A6
RST
OSCXCLK
Figure 7-15. Wait Recovery from Internal Reset
7.7.2 Stop Mod e
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in configuration register 1 (CONFIG1). If
SSREC is set, stop recovery is reduced from the normal delay of 4096
OSCXCLK cycles down to 32. This is ideal for applications using canned
oscillators that do not require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
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System Integration Module (SIM)
Low-Power Modes
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-16 shows stop mode entry timing.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 7-16. Stop Mode Entry Timing
STOP RECOVERY PERIOD
OSCXCLK
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 7-17. Stop Mode Recovery from Interrupt or Break
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Syste m Inte g ra tion Mod ule (SIM)
7.8 SIM Re g iste rs
The SIM has three memory mapped registers. Table 7-5 shows the
mapping of these registers.
Table 7-5. SIM Registers Summary
Address
$FE00
$FE01
$FE03
Register
SBSR
Access Mode
User
SRSR
User
SBFCR
User
7.8.1 SIM Bre a k Sta tus Re g iste r (SBSR)
The SIM break status register contains a flag to indicate that a break
caused an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
R
0
5
4
3
R
0
2
R
0
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
0
R
R
0
0
0
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 7-18. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
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System Integration Module (SIM)
SIM Registers
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example.
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE
LOBYTE
EQU
EQU
5
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN
PULH
RTI
7.8.2 SIM Re se t Sta tus Re g iste r (SRSR)
This register contains six flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
Address:
$FE01
Bit 7
6
5
4
3
2
0
1
0
Bit 0
0
Read:
Write:
POR:
POR
PIN
COP
ILOP
ILAD
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-19. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
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Syste m Inte g ra tion Mod ule (SIM)
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
7.8.3 SIM Bre a k Fla g Control Re g iste r (SBFCR)
The SIM break flag control register contains a bit that enables software
to clear status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 7-20. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Technical Data
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 8. Osc illa tor (OSC)
8.1 Conte nts
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . .102
8.4
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .103
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . .103
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .103
External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . .103
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.6
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .104
8.2 Introd uc tion
The oscillator circuit is designed for use with crystals or ceramic
resonators. The oscillator circuit generates the crystal clock signal,
OSCXCLK, at the frequency of the crystal. This signal is divided by two
before being passed on to the SIM for bus clock generation. Figure 8-1
shows the structure of the oscillator. The oscillator requires various
external components.
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Osc illa tor (OSC)
8.3 Osc illa tor Exte rna l Conne c tions
In its typical configuration, the oscillator requires five external
components. The crystal oscillator is normally connected in a Pierce
oscillator configuration, as shown in Figure 8-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
• Crystal, X
1
• Fixed capacitor, C
1
• Tuning capacitor, C (can also be a fixed capacitor)
2
• Feedback resistor, R
B
• Series resistor, R (optional)
S
The series resistor (R ) is included in the diagram to follow strict Pierce
S
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
From
SIM
To SIM
To SIM
OSCXCLK
OSCOUT
÷ 2
SIMOSCEN
MCU
OSC1
OSC2
R
B
R *
S
X
1
C
C
2
1
*R can be zero (shorted) when used with
S
higher-frequency crystals. Refer to manufacturer’s data.
Figure 8-1. Oscillator External Connections
Technical Data
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Oscillator (OSC)
I/O Signals
8.4 I/ O Sig na ls
The following paragraphs describe the oscillator I/O signals.
8.4.1 Crysta l Am p lifie r Inp ut Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
An externally generated clock can also feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float. The OSC1 pin is rated at 3.3V.
8.4.2 Crysta l Am p lifie r Outp ut Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
The OSC2 is rated at 3.3V.
8.4.3 Osc illa tor Ena b le Sig na l (SIMOSCEN)
The SIMOSCEN signal comes from the SIM and enables the oscillator.
8.4.4 Exte rna l Cloc k Sourc e (OSCXCLK)
OSCXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f ) and comes directly from the crystal oscillator circuit.
XCLK
Figure 8-1 shows only the logical relation of OSCXCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
OSCXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of OSCXCLK can be
unstable at start-up.
8.4.5 Osc illa tor Out (OSCOUT)
The clock driven to the SIM is the crystal frequency divided by two. This
signal is driven to the SIM for generation of the bus clocks used by the
CPU and other modules on the MCU. OSCOUT will be divided again in
the SIM and results in the internal bus frequency being one fourth of the
OSCXCLK frequency.
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Osc illa tor (OSC)
8.5 Low Powe r Mod e s
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
8.5.1 Wa it Mod e
8.5.2 Stop Mod e
The WAIT instruction has no effect on the oscillator logic. OSCXCLK
continues to drive to the SIM module.
The STOP instruction disables the OSCXCLK output.
8.6 Osc illa tor During Bre a k Mod e
The oscillator continues drive OSCXCLK when the chip enters the break
state.
Technical Data
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 9. Monitor ROM (MON)
9.1 Conte nts
9.2
9.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.2 Introd uc tion
This section describes the monitor ROM. The monitor ROM allows
complete testing of the MCU through a single-wire interface with a host
computer.
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Monitor ROM (MON)
9.3 Fe a ture s
Features of the monitor ROM include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor ROM
and host computer
• Standard mark/space non-return-to-zero (NRZ) communication
with host computer
• 9600 Baud communication with host computer
• Execution of code in RAM
9.4 Func tiona l De sc rip tion
The monitor ROM receives and executes commands from a host
computer. Figure 9-1 shows a sample circuit used to enter monitor
mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute host-computer code in RAM while all MCU
pins retain normal operating mode functions. All communication
between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and
the host computer. PTA0 is used in a wired-OR configuration and
requires a pull-up resistor.
Technical Data
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Monitor ROM (MON)
Functional Description
VDD
68HC08
10 k
Ω
RST
0.1 µF
V
TST
10
Ω
IRQ
1
20
MC145407
+
+
+
10
10
µ
F
F
10
10
µ
F
F
3
4
18
17
OSC1
OSC2
X1
9.83 MHz
VDD
20 pF
10 M
Ω
µ
µ
+
2
19
20 pF
DB-25
2
V
V
SS
5
6
16
15
SS1
3
7
VDD
VDD
0.1 µF
VDD
1
2
6
4
14
3
MC74HC125
VDD
10 k
Ω
5
PTA0
PTC3
VDD
10 k
VDD
Ω
10 k
Ω
7
PTC0
PTC1
A
NOTES:
(See
NOTES)
Position A — Bus clock = OSCXCLK
Position B — Bus clock = OSCXCLK
÷
÷
4
2
B
Figure 9-1. Monitor Mode Circuit
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Monitor ROM (MON)
9.4.1 Ente ring Monitor Mod e
Table 9-1 shows the pin conditions for entering monitor mode.
Table 9-1. Mode Selection
Bus
Frequency
Mode
OSCOUT
OSCXCLK
----------------------------
4
OSCXCLK
----------------------------
2
V
V
1
1
0
0
1
1
1
0
Monitor
Monitor
TST
OSCXCLK
----------------------------
2
OSCXCLK
TST
NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The OSCOUT frequency is
equal to the OSCXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Enter monitor mode with the pin configuration shown above by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU monitor mode firmware then sends a break
signal (10 consecutive logic zeros) to the host computer, indicating that
it is ready to receive a command. The break signal also provides a timing
reference to allow the host to determine the necessary baud rate.
Monitor mode uses different vectors for reset and SWI. The alternate
vectors are in the $FE page instead of the $FF page and allow code
execution from the internal monitor firmware instead of user code.
When the host computer has completed downloading code into the MCU
RAM, This code can be executed by driving PTA0 low while asserting
RST low and then high. The internal monitor ROM firmware will interpret
the low on PTA0 as an indication to jump to RAM, and execution control
will then continue from RAM. Execution of an SWI from the downloaded
code will return program control to the internal monitor ROM firmware.
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Functional Description
Alternatively, the host can send a RUN command, which executes an
RTI, and this can be used to send control to the address on the stack
pointer.
The COP module is disabled in monitor mode as long as V
is applied
TST
to the IRQ or the RST pin. (See Section 7. System Integration Module
(SIM) for more information on modes of operation.)
Table 9-2 is a summary of the differences between user mode and
monitor mode.
Table 9-2. Mode Differences
Functions
Reset
Vector
High
Reset
Vector
Low
SWI
Vector
High
SWI
Vector
Low
Modes
COP
User
Enabled
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
(1)
Disabled
Monitor
Notes:
1. If the high voltage (V
) is removed from the IRQ pin, the SIM asserts its COP enable
TST
output. The COP is a mask option enabled or disabled by the COPD bit in the configuration
register.
9.4.2 Da ta Form a t
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 9-2 and Figure 9-3.)
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 9-2. Monitor Data Format
NEXT
START
BIT
START
BIT
STOP
BIT
$A5
BIT 0
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
STOP
BIT
START
BIT
BREAK
BIT 0
Figure 9-3. Sample Monitor Waveforms
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The data transmit and receive rate can be anywhere from 4800 baud to
28.8 kbaud. Transmit and receive baud rates must be identical.
9.4.3 Ec hoing
As shown in Figure 9-4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW
DATA
ECHO
RESULT
Figure 9-4. Read Transaction
Any result of a command appears after the echo of the last byte of the
command.
9.4.4 Bre a k Sig na l
A start bit followed by nine low bits is a break signal (see Figure 9-5).
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-5. Break Transaction
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Functional Description
9.4.5 Com m a nd s
The monitor ROM uses the following commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
Table 9-3. READ (Read Memory) Command
Description Read byte from memory
Operand Specifies 2-byte address in high byte:low byte order
Data
Returned
Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO
MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
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Table 9-4. WRITE (Write Memory) Command
Description Write byte to memory
Specifics 2-byte address in high byte:low byte order; low byte
followed by data byte
Operand
Data
None
Returned
Opcode
$49
Command Sequence
SENT TO
MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
ECHO
WRITE
Table 9-5. IREAD (Indexed Read) Command
Description Read Next 2 Bytes in Memory from Last Address Accessed
Operand
Specifies 2-byte address in high byte:low byte order
Returns contents of next two addresses
Data
Returned
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
ECHO
RETURN
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Functional Description
Table 9-6. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand
Specifies single data byte
Data
None
$19
Returned
Opcode
Command Sequence
SENT TO
MONITOR
DATA
DATA
IWRITE
IWRITE
ECHO
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-kbyte memory map.
Table 9-7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand
None
Data
Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
Command Sequence
SENT TO
MONITOR
SP
HIGH
SP
LOW
READSP
READSP
ECHO
RETURN
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Table 9-8. RUN (Run User Program) Command
Description Executes RTI instruction
Operand
None
None
$28
Data
Returned
Opcode
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
9.4.6 Ba ud Ra te
The communication baud rate is controlled by crystal frequency and the
state of the PTC3 pin upon entry into monitor mode. When PTC3 is high,
the divide by ratio is 1024. If the PTC3 pin is at logic zero upon entry into
monitor mode, the divide by ratio is 512.
Table 9-9. Monitor Baud Rate Selection
Crystal Frequency
19.66 MHz
PTC3 Pin
Baud Rate
19200 bps
9600 bps
4800 bps
0
0
1
9.83 MHz
9.83 MHz
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 10. Tim e r Inte rfa c e Mod ule (TIM)
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .120
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .121
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .121
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .122
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .123
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.10.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . .127
10.10.2 TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . .129
10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) . . . . . .130
10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1).131
10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . .135
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Tim e r Inte rfa c e Mod ule (TIM)
10.2 Introd uc tion
This section describes the timer interface module (TIM2, Version B). The
TIM is a two-channel timer that provides a timing reference with input
capture, output compare, and pulse-width-modulation functions. Figure
10-1 is a block diagram of the TIM.
10.3 Fe a ture s
Features of the TIM include the following:
• Two Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge, or Any-Edge Input Capture Trigger
– Set, Clear, or Toggle Output Compare Action
• Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
• Programmable TIM Clock Input
– Seven-Frequency Internal Bus Clock Prescaler Selection
• Free-Running or Modulo Up-Count Operation
• Toggle Any Channel Pin on Overflow
• TIM Counter Stop and Reset Bits
• Modular Architecture Expandable to Eight Channels
NOTE: TCH1 (timer channel 1) is not bonded to an external pin on this MCU.
Therefore, any references to the timer TCH1 pin in the following text
should be interpreted as not available — but the internal status and
control registers are still available.
10.4 Pin Na m e Conve ntions
The TIM share one I/O pin with one port E I/O pin. The full name of the
TIM I/O pin is listed in Table 10-1. The generic pin name appear in the
text that follows.
Table 10-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
PTE0/SOG/TCH0
Not Available
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Functional Description
10.5 Func tiona l De sc rip tion
Figure 10-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The two TIM channels are programmable independently as input
capture or output compare channels.
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
TCH1
(Not available)
INTERRUPT
LOGIC
16-BIT LATCH
MS1A
CH1IE
Figure 10-1. TIM Block Diagram
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Table 10-2.TIM I/O Register Summary
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
TIM Status and Control
Register
TOIE
TSTOP
PS2
PS1
PS0
$000A
TRST
0
(TSC)
0
0
1
0
0
0
0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TIM Counter Register High
(TCNTH)
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TIM Counter Register Low
(TCNTL)
0
Bit15
1
0
Bit14
1
0
Bit13
1
0
Bit12
1
0
Bit11
1
0
Bit10
1
0
Bit9
1
0
Bit8
1
TIM Counter Modulo
Register High
(TMODH)
TIM Counter Modulo
Register Low
(TMODL)
Bit7
1
Bit6
1
Bit5
1
Bit4
1
Bit3
1
Bit2
1
Bit1
1
Bit0
1
Read: CH0F
TIM Channel 0
Status/Control Register
(TSC0)
CH0MAX
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
TIM Channel 0
Register High
(TCH0H)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Indeterminate after reset
TIM Channel 0
Register Low
(TCH0L)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Indeterminate after reset
Read: CH1F
0
0
TIM Channel 1
Status/Control Register
(TSC1)
CH1MAX
0
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
Write:
0
0
Reset:
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Functional Description
Read:
TIM Channel 1
Register High
(TCH1H)
Bit15
Bit7
Bit14
Bit6
Bit13
Bit5
Bit12
Bit11
Bit10
Bit2
Bit9
Bit1
Bit8
Bit0
$0014
$0015
Write:
Reset:
Read:
Write:
Reset:
Indeterminate after reset
TIM Channel 1
Register Low
(TCH1L)
Bit4
Bit3
Indeterminate after reset
= Unimplemented
10.5.1 TIM Counte r Pre sc a le r
The TIM clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
(TSC) select the TIM clock source.
10.5.2 Inp ut Ca p ture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
10.5.3 Outp ut Com p a re
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
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10.5.3.1 Unb uffe re d Outp ut Co m p a re
Any output compare channel can generate unbuffered output compare
pulses as described in 10.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable
channel x TIM overflow interrupts and write the new value in the
TIM overflow interrupt routine. The TIM overflow interrupt occurs
at the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
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Functional Description
10.5.3.2 Buffe re d Outp ut Co m p a re
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
10.5.4 Pulse Wid th Mod ula tion (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 10-2 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic one. Program the TIM to set the pin if the state of the PWM
pulse is logic zero.
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Tim e r Inte rfa c e Mod ule (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTDx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 10-2. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is 000 (see 10.10.1 TIM Status and Control Register (TSC)).
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
10.5.4.1 Unb uffe re d PWM Sig na l Ge ne ra tio n
Any output compare channel can generate unbuffered PWM pulses as
described in 10.5.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
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Functional Description
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable channel x TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output
compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffe re d PWM Sig na l Ge ne ra tio n
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
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Tim e r Inte rfa c e Mod ule (TIM)
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
10.5.4.3 PWM Initia liza tio n
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB:MSxA. (See Table 10-4.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See Table 10-4.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
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Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See 10.10.4 TIM
Channel Status and Control Registers (TSC0:TSC1).
10.6 Inte rrup ts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE=1. CHxF and CHxIE are in the TIM
channel x status and control register.
10.7 Wa it Mod e
The WAIT instruction puts the MCU in low-power-consumption standby
mode.
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
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Tim e r Inte rfa c e Mod ule (TIM)
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
10.8 TIM During Bre a k Inte rrup ts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 18.6.4 SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
10.9 I/ O Sig na ls
Port E shares one of its pins with the TIM. The TIM channel I/O pin is
PTE0/SOG/TCH0.
TCH0 pin is programmable independently as an input capture pin or an
output compare pin. It also can be configured as a buffered output
compare or buffered PWM pin.
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I/O Registers
10.10 I/ O Re g iste rs
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
10.10.1 TIM Sta tus a nd Control Re g iste r (TSC)
The TIM status and control register does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address:
$000A
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 10-3. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter resets to $0000 after
reaching the modulo value programmed in the TIM counter modulo
registers. Clear TOF by reading the TIM status and control register
when TOF is set and then writing a logic zero to TOF. If another TIM
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overflow occurs before the clearing sequence is complete, then
writing logic zero to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic one to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic zero. Reset clears
the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the TCLK pin or one of the seven
prescaler outputs as the input to the TIM counter as Table 10-3
shows. Reset clears the PS[2:0] bits.
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Timer Interface Module (TIM)
I/O Registers
Table 10-3. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal Bus Clock ÷ 1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Not available
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
10.10.2 TIM Counte r Re g iste rs (TCNTH:TCNTL)
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
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Address:
$000C
Bit 7
TCNTH
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
0
0
0
0
0
0
0
0
Address:
$000D
Bit 7
TCNTL
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-4. TIM Counter Registers (TCNTH:TCNTL)
10.10.3 TIM Counte r Mod ulo Re g iste rs (TMODH:TMODL)
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next clock. Writing to the high byte (TMODH) inhibits
the TOF bit and overflow interrupts until the low byte (TMODL) is written.
Reset sets the TIM counter modulo registers.
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I/O Registers
Address:
$000E
Bit 7
TMODH
6
5
Bit13
1
4
Bit12
1
3
Bit11
1
2
Bit10
1
1
Bit9
1
Bit 0
Bit8
1
Read:
Write:
Reset:
Bit15
1
Bit14
1
Address:
$000F
Bit 7
TMODL
6
5
Bit5
1
4
Bit4
1
3
Bit3
1
2
Bit2
1
1
Bit1
1
Bit 0
Bit0
1
Read:
Write:
Reset:
Bit7
1
Bit6
1
Figure 10-5. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
10.10.4 TIM Cha nne l Sta tus a nd Control Re g iste rs (TSC0:TSC1)
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
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Tim e r Inte rfa c e Mod ule (TIM)
Address:
$0010
Bit 7
CH0F
0
TSC0
6
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
CH0IE
0
0
Address:
$0013
Bit 7
CH1F
0
TSC1
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1IE
0
0
0
= Unimplemented
Figure 10-6. TIM Channel Status and Control Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE=1), clear
CHxF by reading the TIM channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
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I/O Registers
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See Table 10-4.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin. (See Table 10-4.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port , and pin TCHx is available as a general-purpose port
I/O pin. Table 10-4 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
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Table 10-4. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA
Mode
Configuration
Pin under Port Control;
Initial Output Level High
X
X
0
1
0
0
0
0
Output
Preset
Pin under Port Control;
Initial Output Level Low
0
0
0
0
0
0
1
1
0
0
0
1
1
1
X
X
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compareor
Buffered
PWM
Toggle Output on Compare
Clear Output on Compare
1
X
1
1
Set Output on Compare
NOTE: Before enabling a TIM channel register for input capture operation, make
sure that the PTDx/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-7 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
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I/O Registers
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTDx/TCHx
CHxMAX
OUTPUT
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
COMPARE
Figure 10-7. CHxMAX Latency
10.10.5 TIM Cha nne l Re g iste rs (TCH0H/ L:TCH1H/ L)
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
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Address:
$0011
Bit 7
TCH0H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Indeterminate after reset
Address:
$0012
Bit 7
TCH0L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Indeterminate after reset
Address:
$0014
Bit 7
TCH1H
6
5
4
3
2
1
Bit 0
Bit8
Read:
Write:
Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Indeterminate after reset
Address:
$0015
Bit 7
TCH1L
6
5
4
3
2
1
Bit 0
Bit0
Read:
Write:
Reset:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Indeterminate after reset
Figure 10-8. TIM Channel Registers (TCH0H/L:TCH1H/L)
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 11. Pulse Wid th Mod ula tor (PWM)
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
11.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
11.4.1 PWM Data Registers 0 to 15 (0PWM–15PWM). . . . . . . . .140
11.4.2 PWM Control Registers 1 and 2 (PWMCR1:PWMCR2) . .141
11.2 Introd uc tion
Sixteen 8-bit PWM channels are available on the MC68HC08BD24.
Channels 0 to 7 are shared with port-B I/O pins under the control of the
PWM control register 1. Channels 8 to 15 are shared with port-A I/O pins
under the control of the PWM control register 2.
11.3 Func tiona l De sc rip tion
Each 8-bit PWM channel is composed of an 8-bit register which contains
a 5-bit PWM in MSB portion and a 3-bit binary rate multiplier (BRM) in
LSB portion. There are 16 PWM data registers as shown in Table 11-1.
The value programmed in the 5-bit PWM portion will determine the pulse
length of the output. The clock to the 5-bit PWM portion is the system
clock, the repetition rate of the output is hence 187.5KHz at 6MHz clock.
The 3-bit BRM will generate a number of narrow pulses which are
equally distributed among an 8-PWM-cycle frame. The number of pulses
generated is equal to the number programmed in the 3-bit BRM portion.
Examples of the waveforms are shown in Figure 11-3.
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Pulse Wid th Mod ula tor (PWM)
Combining the 5-bit PWM together with the 3-bit BRM, the average duty
cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit
PWM portion, and N is the content of the 3-bit BRM portion. Using this
mechanism, a true 8-bit resolution PWM type DAC with reasonably high
repetition rate can be obtained.
The value of each PWM Data Register is continuously compared with
the content of an internal counter to determine the state of each PWM
channel output pin. Double buffering is not used in this PWM design.
Table 11-1. PWM I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWM0 Data Register
(0PWM)
$0020
0PWM4
0PWM3
0PWM2
0PWM1
0PWM0
0BRM2
0BRM1
0BRM0
PWM1 Data Register
(1PWM)
$0021
$0022
$0023
$0024
$0025
$0026
$0027
1PWM4
2PWM4
3PWM4
4PWM4
5PWM4
6PWM4
7PWM4
1PWM3
2PWM3
3PWM3
4PWM3
5PWM3
6PWM3
7PWM3
1PWM2
2PWM2
3PWM2
4PWM2
5PWM2
6PWM2
7PWM2
1PWM1
2PWM1
3PWM1
4PWM1
5PWM1
6PWM1
7PWM1
1PWM0
2PWM0
3PWM0
4PWM0
5PWM0
6PWM0
7PWM0
1BRM2
2BRM2
3BRM2
4BRM2
5BRM2
6BRM2
7BRM2
1BRM1
2BRM1
3BRM1
4BRM1
5BRM1
6BRM1
7BRM1
1BRM0
2BRM0
3BRM0
4BRM0
5BRM0
6BRM0
7BRM0
PWM2 Data Register
(2PWM)
PWM3 Data Register
(3PWM)
PWM4 Data Register
(4PWM)
PWM5 Data Register
(5PWM)
PWM6 Data Register
(6PWM)
PWM7 Data Register
(7PWM)
PWM Control Read:
Register 1
(PWMCR1)
$0028
PWM7E
0
PWM6E
0
PWM5E
0
PWM4E
0
PWM3E
0
PWM2E
0
PWM1E
0
PWM0E
0
Write:
Reset:
Technical Data
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Pulse Width Modulator (PWM)
PWM Registers
Table 11-1. PWM I/O Register Summary
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
PWM8 Data Register
(8PWM)
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
8PWM4
9PWM4
8PWM3
9PWM3
8PWM2
9PWM2
8PWM1
9PWM1
8PWM0
9PWM0
8BRM2
9BRM2
8BRM1
9BRM1
8BRM0
9BRM0
PWM9 Data Register
(9PWM)
PWM10 Data Register
(10PWM)
10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0
11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0
12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0
13PWM4 13PWM3 13PWM2 13PWM1 13PWM0 13BRM2 13BRM1 13BRM0
PWM11 Data Register
(11PWM)
PWM12 Data Register
(12PWM)
PWM13 Data Register
(13PWM)
PWM14 Data Register
(14PWM)
14PWM4
PWM3
14PWM2 14PWM1 14PWM0 14BRM2 14BRM1 14BRM0
PWM15 Data Register
(15PWM)
15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0
PWM Control Read:
Register 2
(PWMCR2)
$0059
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E
PWM8E
0
Write:
Reset:
0
0
0
0
0
0
0
11.4 PWM Re g iste rs
The PWM module uses of 18 registers for data and control functions.
• 16 PWM data registers ($0020–$0027 and $0051–$0058)
• 2 PWM control registers ($0028 and $0059)
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Technical Data
Pulse Width Modulator (PWM)
139
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Pulse Wid th Mod ula tor (PWM)
11.4.1 PWM Da ta Re g iste rs 0 to 15 (0PWM–15PWM)
Address:
$0020–$0027 and $0051–$0058
Bit 7
xPWM4
0
6
xPWM3
0
5
xPWM2
0
4
xPWM1
0
3
xPWM0
0
2
xBRM2
0
1
xBRM1
0
Bit 0
xBRM0
0
Read:
Write:
Reset:
Figure 11-1. PWM Data Registers 0 to 15 (0PWM–15PWM)
The output waveform of the 16 PWM channels are each configured by
an 8-bit register, which contains a 5-bit PWM in MSB portion and a 3-bit
binary rate multiplier (BRM) in LSB portion
xPWM4–xPWM0 — PWM Bits
The value programmed in the 5-bit PWM portion will determine the pulse
length of the output. The clock to the 5-bit PWM portion is the system
clock (CPU clock), the repetition rate of the output is hence f ÷ 32.
OP
Examples of PWM output waveforms are shown in Figure 11-3.
xBRM2–xBRM0 — Binary Rate Multiplier Bits
The 3-bit BRM will generate a number of narrow pulses which are
equally distributed among an 8-PWM-cycle frame. The number of pulses
generated is equal to the number programmed in the 3-bit BRM portion.
Examples of PWM output waveforms are shown in Figure 11-3.
Technical Data
MC68HC08BD24 — Rev. 1.0
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Pulse Width Modulator (PWM)
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Pulse Width Modulator (PWM)
PWM Registers
11.4.2 PWM Control Re g iste rs 1 a nd 2 (PWMCR1:PWMCR2)
PWM Control Read:
$0028
$0059
Register 1
(PWMCR1)
PWM7E
PWM6E
PWM5E
PWM4E
PWM3E
PWM2E
PWM1E
PWM0E
Write:
PWM Control Read:
Register 2
(PWMCR2)
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E
PWM8E
0
Write:
Reset:
0
0
0
0
0
0
0
Figure 11-2. PWM Control Register 1 and 2 (PWMCR1:PWMCR2)
PWM15E–PWM0E — PWM Output Enable
Setting a bit to 1 will enable the corresponding PWM channel to use
as PWM output. A zero configures the corresponding PWM pin as a
standard I/O port pin. Reset clears these bits.
1 = Port pin configured as PWM output
0 = Port pin configured as standard I/O port pin.
Table 11-2. PWM Channels and Port I/O pins
PWM
Channel
Control
Bit
PWM
Channel
Control
Bit
Port Pin
Port Pin
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM0E
PWM1E
PWM2E
PWM3E
PWM4E
PWM5E
PWM6E
PWM7E
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PWM8
PWM9
PWM8E
PWM9E
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
PWM10E
PWM11E
PWM12E
PWM13E
PWM14E
PWM15E
MC68HC08BD24 — Rev. 1.0
MOTOROLA
Technical Data
Pulse Width Modulator (PWM)
141
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Pulse Wid th Mod ula tor (PWM)
1 PWM cycle = 32T
M=$00
M=$01
M=$0F
M=$1F
T
31T
16T
16T
31T
Pulse inserted at end of PWM cycle
depends on setting of N.
T
T=1 CPU clock period (0.167
µ
s if CPU clock=6MHz)
M = value set in 5-bit PWM (bit3-bit7)
N = value set in 3-bit BRM (bit0-bit2)
PWM cycles where pulses are Number of inserted pulses
N
inserted in a 8-cycle frame
in a 8-cycle frame
xx1
x1x
1xx
4
1
2
4
2, 6
1, 3, 5, 7
Figure 11-3. 8-Bit PWM Output Waveforms
Technical Data
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Pulse Width Modulator (PWM)
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 12. Ana log -to-Dig ita l Conve rte r (ADC)
12.1 Conte nts
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
12.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
12.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .146
12.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
12.7.1 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . .148
12.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
12.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .148
12.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
12.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .151
12.2 Introd uc tion
This section describes the analog-to-digital converter (ADC). The ADC
is an 8-bit 6-channels analog-to-digital converter.
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Analog-to-Digital Converter (ADC)
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Ana log -to-Dig ita l Conve rte r (ADC)
12.3 Fe a ture s
Features of the ADC module include:
• 6 Channels ADC with Multiplexed Input
• Linear Successive Approximation
• 8-Bit Resolution
• Single or Continuous Conversion
• Conversion Complete Flag or Conversion Complete Interrupt
• Selectable ADC Clock
Table 12-1. ADC Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COCO
ADC Status and Control
$005D
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Register Write:
(ADSCR)
Reset:
0
0
0
1
1
1
1
1
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
$005E
$005F
ADC Data Register
Write:
Reset:
Read:
(ADR)
Indeterminate after Reset
0
0
0
0
0
0
0
0
ADC Input Clock
ADIV2
0
ADIV1
0
ADIV0
0
Register Write:
(ADICLK)
Reset:
0
0
= Unimplemented
12.4 Func tiona l De sc rip tion
Four ADC channels are available for sampling external sources at pins
PTC5–PTC0. An analog multiplexer allows the single ADC converter to
select one of the 6 ADC channels as ADC voltage input (ADCVIN).
ADCVIN is converted by the successive approximation register-based
counters. The ADC resolution is 8 bits. When the conversion is
completed, ADC puts the result in the ADC data register and sets a flag
or generates an interrupt. Figure 12-1 shows a block diagram of the
ADC.
Technical Data
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Analog-to-Digital Converter (ADC)
Functional Description
INTERNAL
DATA BUS
READ DDRC
WRITE DDRC
DISABLE
DDRCx
PTCx
RESET
WRITE PTC
READ PTC
PTCx/ADCx
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC VOLTAGE IN
ADCVIN
CONVERSION
COMPLETE
CHANNEL
SELECT
(1 OF 6 CHANNELS)
INTERRUPT
LOGIC
ADCH[4:0]
ADC
ADC CLOCK
AIEN
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
ADICLK
Figure 12-1. ADC Block Diagram
12.4.1 ADC Port I/ O Pins
PTC5–PTC0 are general-purpose I/O pins that are shared with the ADC
channels. The channel select bits (ADC status control register, $005D),
define which ADC channel/port pin will be used as the input signal. The
ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O
logic and can be used as general-purpose I/O. Writes to the port register
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Ana log -to-Dig ita l Conve rte r (ADC)
or DDR will not have any affect on the port pin that is selected by the
ADC. Read of a port pin which is in use by the ADC will return an
unknown state if the corresponding DDR bit is at logic 0. If the DDR bit
is at logic 1, the value in the port data latch is read.
12.4.2 Volta g e Conve rsion
When the input voltage to the ADC equals ------ V , the ADC converts the
2
3
DD
signal to $FF (full scale). If the input voltage equals V , the ADC
SS
2
3
converts it to $00. Input voltage between ------ V and V are a
DD
SS
straight-line linear conversion. All other input voltages will result in $FF
2
3
if greater than ------ V and $00 if less than V .
DD
SS
NOTE: Input voltage should not exceed the analog supply voltages.
12.4.3 Conve rsion Tim e
Twelve ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1MHz, then one conversion will take 12µs to complete.
With a 1MHz ADC internal clock the maximum sample rate is 83.3kHz.
12 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
12.4.4 Continuous Conve rsion
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status control register,
$005D) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
Technical Data
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Analog-to-Digital Converter (ADC)
Interrupts
12.4.5 Ac c ura c y a nd Pre c ision
The conversion process is monotonic and has no missing codes.
12.5 Inte rrup ts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
12.6 Low-Powe r Mod e s
The following subsections describe the low-power modes.
12.6.1 Wa it Mod e
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register to logic 1’s before executing the WAIT instruction.
12.6.2 Stop Mod e
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
12.7 I/ O Sig na ls
The ADC module has 6 channels that are shared with I/O port C.
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Analog-to-Digital Converter (ADC)
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Ana log -to-Dig ita l Conve rte r (ADC)
12.7.1 ADC Volta g e In (ADCVIN)
ADCVIN is the input voltage signal from one of the 6 ADC channels to
the ADC module.
12.8 I/ O Re g iste rs
Three I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR, $005D)
• ADC data register (ADR, $005E)
• ADC clock register (ADICLK, $005F)
12.8.1 ADC Sta tus a nd Control Re g iste r
The following paragraphs describe the function of the ADC status and
control register.
Address:
$005D
Bit 7
6
AIEN
0
5
ADCO
0
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Read:
Write:
Reset:
COCO
0
= Unimplemented
Figure 12-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
Technical Data
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Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
I/O Registers
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC
channels. The five channel select bits are detailed in the following
table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from
corrupting the analog signal. (See Table 12-2.)
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
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Ana log -to-Dig ita l Conve rte r (ADC)
Table 12-2. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
0
0
0
0
0
0
0
0
:
0
0
0
0
1
1
1
:
0
0
1
1
0
0
1
:
0
1
0
1
0
1
0
:
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
0
0
0
0
0
0
Unused
(see Note 1)
:
—
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
—
—
Reserved
Unused
1
1
V
V
(see Note 2)
(see Note 2)
DDA
SSA
1
1
ADC power off
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
12.8.2 ADC Da ta Re g iste r
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address:
$005E
Bit 7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after Reset
= Unimplemented
Figure 12-3. ADC Data Register (ADR)
Technical Data
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Analog-to-Digital Converter (ADC)
I/O Registers
12.8.3 ADC Inp ut Cloc k Re g iste r
This register selects the clock frequency for the ADC.
Address:
$005F
Bit 7
6
ADIV1
0
5
ADIV0
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
0
0
0
0
0
0
= Unimplemented
Figure 12-4. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 12-3
shows the available clock configurations. The ADC clock should be
set to approximately 1MHz. With an internal bus frequency of 6MHz,
set ADIV[2:0] = 010, for a divide by four ADC clock rate.
Table 12-3. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
0
0
0
1
1
X
0
1
0
1
X
0
0
0
1
X = don’t care
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Technical Data
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 13. DDC12AB Inte rfa c e
13.1 Conte nts
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
13.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
13.5 DDC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
13.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
13.6.1 DDC Address Register (DADR) . . . . . . . . . . . . . . . . . . . . .156
13.6.2 DDC2 Address Register (D2ADR) . . . . . . . . . . . . . . . . . . .157
13.6.3 DDC Control Register (DCR) . . . . . . . . . . . . . . . . . . . . . . .158
13.6.4 DDC Master Control Register (DMCR) . . . . . . . . . . . . . . .159
13.6.5 DDC Status Register (DSR). . . . . . . . . . . . . . . . . . . . . . . .162
13.6.6 DDC Data Transmit Register (DDTR) . . . . . . . . . . . . . . . .164
13.6.7 DDC Data Receive Register (DDRR). . . . . . . . . . . . . . . . .165
13.7 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . .166
13.2 Introd uc tion
This DDC12AB Interface module is used by the digital monitor to show
its identification information to the video controller. It contains DDC1
hardware and a two-wire, bidirectional serial bus which is fully
compatible with multi-master IIC bus protocol to support DDC2AB
interface.
This module not only can be applied in internal communications, but can
also be used as a typical command reception serial bus for factory setup
and alignment purposes. It also provides the flexibility of hooking
additional devices to an existing system for future expansion without
adding extra hardware.
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Technical Data
DDC12AB Interface
153
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DDC12AB Inte rfa c e
This DDC12AB module uses the DDCSCL clock line and the DDCSDA
data line to communicate with external DDC host or IIC interface. These
two pins are shared with port pins PTD3 and PTD2 respectively. The
outputs of DDCSDA and DDCSCL pins are open-drain type — no
clamping diode is connected between the pin and internal V . The
DD
maximum data rate typically is 100k-bps. The maximum communication
length and the number of devices that can be connected are limited by
a maximum bus capacitance of 400pF.
13.3 Fe a ture s
• DDC1 hardware
• Compatibility with multi-master IIC bus standard
• Software controllable acknowledge bit generation
• Interrupt driven byte by byte data transfer
• Calling address identification interrupt
• Auto detection of R/W bit and switching of transmit or receive
mode
• Detection of START, repeated START, and STOP signals
• Auto generation of START and STOP condition in master mode
• Arbitration loss detection and No-ACK awareness in master mode
• 8 selectable baud rate master clocks
• Automatic recognition of the received acknowledge bit
13.4 I/ O Pins
The DDC12AB module uses two I/O pins, shared with standard port I/O
pins. The full name of the DDC12AB I/O pins are listed in Table 13-1.
The generic pin name appear in the text that follows.
Table 13-1. Pin Name Conventions
DDC12AB
Generic Pin Names:
Pin Selected for
DDC Function By:
Full MCU Pin Names:
SDA
SCL
PTD2/DDCSDA
PTD3/DDCSCL
DDCDATE bit in PDCR ($0049)
DDCSCLE bit in PDCR ($0049)
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I/O Pins
Table 13-2. DDC I/O Register Summary
Addr.
Register Name
Bit 7
ALIF
0
6
NAKIF
0
5
4
3
MRW
0
2
BR2
0
1
BR1
0
Bit 0
BR0
0
Read:
DDC Master Control
BB
MAST
0
$0016
Register Write:
(DMCR)
Reset:
0
Read:
EXTAD
DAD7
1
DAD6
0
DAD5
DAD4
DAD3
0
DAD2
0
DAD1
0
DDC Address Register
$0017
$0018
$0019
Write:
Reset:
Read:
(DADR)
1
0
0
0
0
0
DDC
DEN
DIEN
TXAK
SCLIEN DDC1EN
Control Register Write:
(DCR)
Reset:
0
RXIF
0
0
TXIF
0
0
0
0
0
0
0
Read:
DDC
Status Register Write:
MATCH
SRW
RXAK
SCLIF
TXBE
RXBF
0
0
(DSR)
Reset:
0
0
0
0
1
1
0
Read:
DDC
DTD7
DTD6
DTD5
DTD4
DTD3
DTD2
DTD1
DTD0
$001A Data Transmit Register Write:
(DDTR)
Reset:
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Read:
Write:
Reset:
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
DDC
Data Receive Register
(DDRR)
$001B
$001C
0
D2AD7
0
0
D2AD6
0
0
D2AD5
0
0
D2AD4
0
0
D2AD3
0
0
D2AD2
0
0
D2AD1
0
0
0
DDC2 Address Register
(D2ADR)
0
= Unimplemented
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13.5 DDC Protoc ols
In DDC1 protocol communication, the module is in transmit mode. The
data written to the transmit register is continuously clocked out to the
SDA line by the rising edge of the Vsync input signal. During DDC1
communication, a falling transition on the SCL line can be detected to
generate an interrupt to the CPU for mode switching.
In DDC2AB protocol communication, the module can be either in
transmit mode or in receive mode, controlled by the calling master.
In DDC2 protocol communication, the module will act as a standard IIC
module, able to act as a master or a slave device.
13.6 Re g iste rs
Seven registers are associated with the DDC module, they outlined in
the following sections.
13.6.1 DDC Ad d re ss Re g iste r (DADR)
Address:
$0017
Bit 7
6
DAD6
0
5
DAD5
1
4
DAD4
0
3
DAD3
0
2
DAD2
0
1
DAD1
0
Bit 0
EXTAD
0
Read:
Write:
Reset:
DAD7
1
Figure 13-1. DDC Address Register (DADR)
DAD[7:1] — DDC Address
These 7 bits can be the DDC2 interface’s own specific slave address
in slave mode or the calling address when in master mode. Reset sets
a default value of $A0.
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Registers
EXTAD — DDC Expanded Address
This bit is set to expand the calling address of the DDC in slave mode.
When set, the DDC will acknowledge the general call address $00
and the matched 4-bit MSB address, DAD[7:4].
For example, when DAD[7:1] = $A1 and EXTAD = 1, the DDC calling
address is $A0, and it will acknowledge calling addresses $00 and
$A0 to $AF.
Reset clears this bit.
1 = DDC calling address is $DAD[7:4]0
DDC respond address is $00, and $DAD[7:4]0 to $DAD[7:4]F
0 = DDC address id $DAD[7:1]
13.6.2 DDC2 Ad d re ss Re g iste r (D2ADR)
Address:
$001C
Bit 7
6
D2AD6
0
5
D2AD5
0
4
D2AD4
0
3
D2AD3
0
2
D2AD2
0
1
D2AD1
0
Bit 0
0
Read:
Write:
Reset:
D2AD7
0
0
Figure 13-2. DDC2 Address Register (D2ADR)
D2AD[7:1] — DDC2 Address
These 7 bits represent the second slave address for the DDC2BI
protocol. D2AD[7:1] should be set to the same value as DAD[7:1] in
DADR if user application do not use DDC2BI. Reset clears all bits this
register.
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13.6.3 DDC Control Re g iste r (DCR)
Address:
$0018
Bit 7
6
DIEN
0
5
0
4
0
3
TXAK
0
2
1
Bit 0
0
Read:
Write:
Reset:
DEN
0
SCLIEN DDC1EN
0
0
0
0
0
= Unimplemented
Figure 13-3. DDC Control Register (DCR)
DEN — DDC Enable
This bit is set to enable the DDC module. When DEN = 0, module is
disabled and all flags will restore to its power-on default states. Reset
clears this bit.
1 = DDC module enabled
0 = DDC module disabled
DIEN — DDC Interrupt Enable
When this bit is set, the TXIF, RXIF, ALIF, and NAKIF flags are
enabled to generate an interrupt request to the CPU. When DIEN is
cleared, the these flags are prevented from generating an interrupt
request. Reset clears this bit.
1 = TXIF, RXIF, ALIF, and/or NAKIF bit set will generate interrupt
request to CPU
0 = TXIF, RXIF, ALIF, and/or NAKIF bit set will not generate
interrupt request to CPU
TXAK — Transmit Acknowledge Enable
This bit is set to disable the DDC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
TXAK is cleared, an acknowledge signal will be sent at the 9th clock
bit. Reset clears this bit.
1 = DDC does not send acknowledge signals at 9th clock bit
0 = DDC sends acknowledge signal at 9th clock bit
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Registers
SCLIEN — SCL Interrupt Enable
When this bit is set, the SCLIF flag is enabled to generate an interrupt
request to the CPU. When SCLIEN is cleared, SCLIF is prevented
from generating an interrupt request. Reset clears this bit.
1 = SCLIF bit set will generate interrupt request to CPU
0 = SCLIF bit set will not generate interrupt request to CPU
DDC1EN — DDC1 Protocol Enable
This bit is set to enable DDC1 protocol. The DDC1 protocol will use
the Vsync input (from sync processor) as the master clock input to the
DDC module. Vsync rising-edge will continuously clock out the data
to the output circuit. No calling address comparison is performed. The
SRW bit in DDC status register (DSR) will always read as "1". Reset
clears this bit.
1 = DDC1 protocol enabled
0 = DDC1 protocol disabled
13.6.4 DDC Ma ste r Control Re g iste r (DMCR)
Address:
$0016
Bit 7
6
NAKIF
0
5
BB
0
4
MAST
0
3
MRW
0
2
BR2
0
1
BR1
0
Bit 0
BR0
0
Read:
Write:
Reset:
ALIF
0
Figure 13-4. DDC Master Control Register (DMCR)
ALIF — DDC Arbitration Lost Interrupt Flag
The flag is set when software attempt to set MAST but the BB has
been set by detecting the start condition on the lines or when the DDC
is transmitting a "1" to SDA line but detected a "0" from SDA line in
master mode – an arbitration loss. This bit generates an interrupt
request to the CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset.
1 = Lost arbitration in master mode
0 = No arbitration lost
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NAKIF — No Acknowledge Interrupt Flag
The flag is only set in master mode (MAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MAST. NAKIF generates an interrupt
request to CPU if the DIEN bit in DCR is also set. This bit is cleared
by writing "0" to it or by reset.
1 = No acknowledge bit detected
0 = Acknowledge bit detected
BB — Bus Busy Flag
This flag is set after a start condition is detected (bus busy), and is
cleared when a stop condition (bus idle) is detected or the DDC is
disabled. Reset clears this bit.
1 = Start condition detected
0 = Stop condition detected or DDC is disabled
MAST — Master Control Bit
This bit is set to initiate a master mode transfer. In master mode, the
module generates a start condition to the SDA and SCL lines,
followed by sending the calling address stored in DADR.
When the MAST bit is cleared by NAKIF set (no acknowledge) or by
software, the module generates the stop condition to the lines after
the current byte is transmitted.
If an arbitration loss occurs (ALIF = 1), the module reverts to slave
mode by clearing MAST, and releasing SDA and SCL lines
immediately.
This bit is cleared by writing "0" to it or by reset.
1 = Master mode operation
0 = Slave mode operation
MRW — Master Read/Write
This bit will be transmitted out as bit 0 of the calling address when the
module sets the MAST bit to enter master mode. The MRW bit
determines the transfer direction of the data bytes that follows. When
it is "1", the module is in master receive mode. When it is "0", the
module is in master transmit mode. Reset clears this bit.
1 = Master mode receive
0 = Master mode transmit
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Registers
BR2–BR0 — Baud Rate Select
These three bits select one of eight clock rates as the master clock
when the module is in master mode.
Since this master clock is derived the CPU bus clock, the user
program should not execute the WAIT instruction when the DDC
module in master mode. This will cause the SDA and SCL lines to
hang, as the WAIT instruction places the MCU in WAIT mode, with
CPU clock is halted. These bits are cleared upon reset. (See Table
13-3 . Baud Rate Select.)
Table 13-3. Baud Rate Select
BR2
BR1
0
BR0
0
Baud Rate
100k
0
0
0
1
50k
0
1
0
25k
0
1
1
12.5k
6.25k
3.125k
1.56k
0.78k
1
0
0
1
0
1
1
1
1
0
1
1
NOTE:
CPU bus clock is external clock ÷ 4 = 6MHz
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13.6.5 DDC Sta tus Re g iste r (DSR)
Address:
$0019
Bit 7
RXIF
0
6
TXIF
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
MATCH
SRW
RXAK
SCLIF
TXBE
RXBF
0
0
0
0
0
0
1
1
0
= Unimplemented
Figure 13-5. DDC Status Register (DSR)
RXIF — DDC Receive Interrupt Flag
This flag is set after the data receive register (DDRR) is loaded with a
new received data. Once the DDRR is loaded with received data, no
more received data can be loaded to the DDRR register until the CPU
reads the data from the DDRR to clear RXBF flag. RXIF generates an
interrupt request to CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset; or when the DEN = 0.
1 = New data in data receive register (DDRR)
0 = No data received
TXIF — DDC Transmit Interrupt Flag
This flag is set when data in the data transmit register (DDTR) is
downloaded to the output circuit, and that new data can be written to
the DDTR. TXIF generates an interrupt request to CPU if the DIEN bit
in DCR is also set. This bit is cleared by writing "0" to it or when the
DEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MATCH — DDC Address Match
This flag is set when the received data in the data receive register
(DDRR) is an calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DADR register.
1 = Received address matches DADR
0 = Received address does not match
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Registers
SRW — DDC Slave Read/Write
This bit indicates the data direction when the module is in slave mode.
It is updated after the calling address is received from a master
device. SRW = 1 when the calling master is reading data from the
module (slave transmit mode). SRW = 0 when the master is writing
data to the module (receive mode).
1 = Slave mode transmit
0 = Slave mode receive
RXAK — DDC Receive Acknowledge
When this bit is cleared, it indicates an acknowledge signal has been
received after the completion of 8 data bits transmission on the bus.
When RXAK is set, it indicates no acknowledge signal has been
detected at the 9th clock; the module will release the SDA line for the
master to generate "stop" or "repeated start" condition. Reset sets this
bit.
1 = No acknowledge signal received at 9th clock bit
0 = Acknowledge signal received at 9th clock bit
SCLIF — SCL Interrupt Flag
This flag is set when a falling edge is detected on the SCL line, only if
DDC1EN bit is set. SCLIF generates an interrupt request to CPU if the
SCLIEN bit in DCR is also set. SCLIF is cleared by writing "0" to it or
when the DCC1EN = 0, or DEN = 0. Reset clears this bit.
1 = Falling edge detected on SCL line
0 = No falling edge detected on SCL line
TXBE — DDC Transmit Buffer Empty
This flag indicates the status of the data transmit register (DDTR).
When the CPU writes the data to the DDTR, the TXBE flag will be
cleared. TXBE is set when DDTR is emptied by a transfer of its data
to the output circuit. Reset sets this bit.
1 = Data transmit register empty
0 = Data transmit register full
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RXBF — DDC Receive Buffer Full
This flag indicates the status of the data receive register (DDRR).
When the CPU reads the data from the DDRR, the RXBF flag will be
cleared. RXBF is set when DDRR is full by a transfer of data from the
input circuit to the DDRR. Reset clears this bit.
1 = Data receive register full
0 = Data receive register empty
13.6.6 DDC Da ta Tra nsm it Re g iste r (DDTR)
Address:
$001A
Bit 7
6
DTD6
1
5
DTD5
1
4
DTD4
1
3
DTD3
1
2
DTD2
1
1
DTD1
1
Bit 0
DTD0
1
Read:
Write:
Reset:
DTD7
1
Figure 13-6. DDC Data Transmit Register (DDTR)
When the DDC module is enabled, DEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in DDTR will be transferred to the output circuit
when:
• the module detects a matched calling address (MATCH = 1), with
the calling master requesting data (SRW = 1); or
• the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
If the calling master does not return an acknowledge bit (RXAK = 1), the
module will release the SDA line for master to generate a "stop" or
"repeated start" condition. The data in the DDTR will not be transferred
to the output circuit until the next calling from a master. The transmit
buffer empty flag remains cleared (TXBE = 0).
In master mode, the data in DDTR will be transferred to the output circuit
when:
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Registers
• the module receives an acknowledge bit (RXAK = 0), after
setting master transmit mode (MRW = 0), and the calling address
has been transmitted; or
• the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
If the slave does not return an acknowledge bit (RXAK = 1), the master
will generate a "stop" or "repeated start" condition. The data in the DDTR
will not be transferred to the output circuit. The transmit buffer empty flag
remains cleared (TXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in Figure 13-8.
13.6.7 DDC Da ta Re c e ive Re g iste r (DDRR)
Address:
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DRD7
DRD6
DRD5
DRD4
DRD3
DRD2
DRD1
DRD0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-7. DDC Data Receive Register (DDRR)
When the DDC module is enabled, DEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
In slave mode, the data in DDRR is:
• the calling address from the master when the address match flag
is set (MATCH = 1); or
• the last data received when MATCH = 0.
In master mode, the data in the DDRR is:
• the last data received.
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When the DDRR is read by the CPU, the receive buffer full flag is cleared
(RXBF = 0), and the next received data is loaded to the DDRR. Each
time when new data is loaded to the DDRR, the RXIF interrupt flag is set,
indicating that new data is available in DDRR.
The sequence of events for slave receive and master receive are
illustrated in Figure 13-8.
13.7 Prog ra m m ing Consid e ra tions
When the DDC module detects an arbitration loss in master mode, it will
release both SDA and SCL lines immediately. But if there are no further
STOP conditions detected, the module will hang up. Therefore, it is
recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the
BB (Bus Busy) flag in the DMCR and reset the counter on the completion
of one byte transmission. If a time-out occur, software can clear the DEN
bit (disable DDC module) to release the bus, and hence clearing the BB
flag. This is the only way to clear the BB flag by software if the module
hangs up due to a no STOP condition received. The DDC can resume
operation again by setting the DEN bit.
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Programming Considerations
(a) Master Transmit Mode
TX Data1
START
Address
0
ACK
ACK
TX DataN
DataN+2
NAK
STOP
TXBE=0
MRW=0
MAST=1
TXBE=1
TXIF=1
Data2
TXBE=1
TXIF=1
Data3 → DDTR
NAKIF=1
TXBE=1
TXIF=1
MAST=0
TXBE=0
→
DDTR
→
DDTR
Data1
→ DDTR
(b) Master Receive Mode
RX Data1
START
Address
1
ACK
ACK
RX DataN
NAK
STOP
RXBF=0
MRW=1
NAKIF=1
MAST=0
Data1
RXIF=1
RXBF=1
→
DDRR
DataN → DDRR
RXIF=1
RXBF=1
MAST=1
TXBE=0
(dummy data
→ DDTR)
(c) Slave Transmit Mode
TX Data1
START
Address
1
ACK
ACK
TX DataN
DataN+2
NAK
STOP
TXBE=1
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=1
NAKIF=1
TXBE=0
TXBE=1
TXIF=1
Data2
TXBE=1
TXIF=1
→ DDTR
→
DDTR
Data1
→ DDTR
(d) Slave Receive Mode
RX Data1
START
Address
0
ACK
ACK
RX DataN
NAK
STOP
Data1
RXIF=1
RXBF=1
→
DDRR
DataN → DDRR
TXBE=0
RXBF=0
RXIF=1
RXBF=1
MATCH=1
SRW=0
RXIF=1
RXBF=1
KEY: shaded data packets indicate a transmit by the MCU’s DDC module
Figure 13-8. Data Transfer Sequences for Master/Slave Transmit/Receive Modes
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 14. Sync Proc e ssor
14.1 Conte nts
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
14.4 I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.5 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
14.5.1 Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
14.5.1.1
14.5.1.2
14.5.1.3
Hsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . .174
Vsync Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . .174
Composite Sync Polarity Detection . . . . . . . . . . . . . . . .174
14.5.2 Sync Signal Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
14.5.3 Polarity Controlled HSYNCO and VSYNCO Outputs. . . . .175
14.5.4 Clamp Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
14.5.5 Low Vertical Frequency Detect . . . . . . . . . . . . . . . . . . . . .177
14.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.6.1 Sync Processor Control & Status Register (SPCSR). . . . .177
14.6.2 Sync Processor Input/Output Control Register (SPIOCR) .179
14.6.3 Vertical Frequency Registers (VFRs). . . . . . . . . . . . . . . . .181
14.6.4 Hsync Frequency Registers (HFRs). . . . . . . . . . . . . . . . . .183
14.6.5 Sync Processor Control Register 1 (SPCR1). . . . . . . . . . .185
14.6.6 H&V Sync Output Control Register (HVOCR) . . . . . . . . . .186
14.7 System Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
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Sync Proc e ssor
14.2 Introd uc tion
The Sync Processor is designed to detect and process sync signals
inside a digital monitor system — from separated Hsync and Vsync
inputs, or from composite sync inputs such as Sync-On-Green (SOG).
After detection and the necessary polarity correction and/or sync
separation, the corrected sync signals are sent out. The MCU can also
send commands to other monitor circuitry, such as for the geometry
correction and OSD, using the DDC12AB and/or the IIC communication
channels.
The block diagram of the Sync Processor is shown in Figure 14-1.
NOTE: All quoted timings in this section assume an internal bus frequency of
6MHz.
14.3 Fe a ture s
Features of the Sync Processor include the following:
• Polarity detector
• Horizontal frequency counter
• Vertical frequency counter
• Low vertical frequency indicator (40.7Hz)
• Polarity controlled HSYNCO and VSYNCO outputs:
– From separate Hsync and Vsync
– From composite sync on HSYNC or SOG input pin
– From internal selectable free running Hsync and Vsync pulses
• CLAMP pulse output to the external pre-amp chip
• Internal schmitt trigger on HSYNC, VSYNC, and SOG input pins
to improve noise immunity
Technical Data
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Sync Processor
I/O Pins
14.4 I/ O Pins
The Sync Processor uses six I/O pins, with four pins shared with
standard port I/O pins. The full name of the Sync Processor I/O pins are
listed in Table 14-1. The generic pin name appear in the text that
follows.
Table 14-1. Pin Name Conventions
Sync Processor
Generic Pin Names:
Pin Selected for
Sync Processor Function By:
Full MCU Pin Names:
HSYNC
HSYNC
VSYNC
—
VSYNC
—
SOG
PTE0/SOG/TCH0
PTE1/HSYNCO
PTE2/VSYNCO
PTD4/CLAMP
SOGE bit in CONFIG1 ($001D)
HSYNCOE bit in CONFIG 1 ($001D)
VSYNCOE bit in CONFIG 1 ($001D)
CLAMPE bit in PDCR ($0049)
HSYNCO
VSYNCO
CLAMP
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Sync Proc e ssor
Table 14-2. Sync Processor I/O Register Summary
Addr.
Register Name
Bit 7
6
5
VSIF
0
4
3
2
1
Bit 0
Read:
VPOL
HPOL
Sync Processor Control
$0040
VSIE
VEDGE
COMP
VINVO
HINVO
and Status Register Write:
(SPCSR)
Reset:
0
0
0
0
0
0
0
0
0
Read:
VOF
0
VF12
VF11
VF10
VF9
VF8
Vertical Frequency High
$0041
$0042
$0043
$0044
$0045
$0046
$0047
Register Write:
CPW1
0
CPW0
0
(VFHR)
Reset:
0
0
0
0
0
0
Read:
VF7
VF6
VF5
VF4
VF3
VF2
VF1
VF0
Vertical Frequency Low
Register Write:
(VFLR)
Reset:
0
0
0
0
0
0
0
0
Read:
HFH7
HFH6
HFH5
HFH4
HFH3
HFH2
HFH1
HFH0
Hsync Frequency High
Register Write:
(HFHR)
Reset:
0
0
0
0
0
0
0
0
0
0
Read: HOVER
HFL4
HFL3
HFL2
HFL1
HFL0
Hsync Frequency Low
Register Write:
(HFLR)
Reset:
0
0
0
0
R
0
0
0
BPOR
0
0
SOUT
0
Read: VSYNCS HSYNCS
Sync Processor I/O
CLAMPOE
COINV
0
SOGSEL
Control Register Write:
(SPIOCR)
Reset:
0
0
0
0
0
R
0
Read:
LVSIF
Sync Processor Control
LVSIE
HPS1
HPS0
R
ATPOL
0
FSHF
0
Register 1 Write:
0
0
0
(SPCR1)
Reset:
0
R
0
0
0
0
0
0
0
Read:
H&V Sync Output
HVOCR2 HVOCR1 HVOCR0
Control Register Write:
(HVOCR)
Reset:
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Technical Data
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Sync Processor
Functional Blocks
14.5 Func tiona l Bloc ks
EXTRACTED
VSYNC
SVF
VINVO
1
A
VSYNCO
1
A
B
S
VSYNC
B
S
SOUT
COMP
VSIF
POLARITY DETECT
VPOL
VSIE
EDGE DETECT
ONE SHOT
VEDGE
VOF
VFLR
VFHR
INTERNAL (6MHz)
BUS CLOCK
(125kHz)
13-BIT COUNTER
$C00 DETECT
OVERFLOW DETECT
÷ 48
TO INTERRUPT
LOGIC
LVSIF
LVSIE
ONE SHOT
HFLR
HFHR
HOVER
CLK32/32.768
1
HSYNC
SOG
A
13-BIT COUNTER
OVERFLOW DETECT
B
S
SOGSEL
1
POLARITY DETECT
VPOL
A
B
HPOL
S
COMP
EXTRACTED VSYNC
VSYNC EXTRACTOR
BPOR
CLAMP
PULSE GENERATOR
SVF
CLAMP
COINV
B
H/V SYNC
2µs
SHF
1
PULSE GENERATOR
A
S
SOUT
HSYNCO
HVOCR[2:0]
HINVO
Figure 14-1. Sync Processor Block Diagram
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Sync Proc e ssor
14.5.1 Pola rity De te c tion
14.5.1.1 Hsync Po la rity De te c tio n
The Hsync polarity detection circuit measures the length of high and low
period of the HSYNC input. If the length of high is longer than L and the
length of low is shorter than S, the HPOL bit will be "0", indicating a
negative polarity HSYNC input. If the length of low is longer than L and
the length of high is shorter than S, the HPOL bit will be "1", indicating a
positive polarity HSYNC input. The table below shows three possible
cases for HSYNC polarity detection — the conditions are selected by the
HPS[1:0] bits in the Sync Processor Control Register 1 (SPCR1).
Polarity Detection Pulse Width
Long is greater than ( L) Short is less than ( S)
7µs 6µs
SPCR1 ($0046)
HPS1
HPS0
0
1
0
0
X
1
3.5µs
14µs
3µs
12µs
14.5.1.2 Vsync Po la rity De te c tio n
The Vsync polarity detection circuit performs a similar function as for
Hsync. If the length of high is longer than 4ms and the length of low is
shorter than 2ms, the VPOL bit will be "0", indicating a negative polarity
VSYNC input. If the length of low is longer than 4ms and the length of
high is shorter than 2ms, the VPOL bit will be "1", indicating a positive
polarity VSYNC input.
14.5.1.3 Co m p o site Sync Po la rity De te c tio n
When a composite sync signal is the input (COMP = 1 for composite
sync processing), the HPOL bit = VPOL bit, and the polarity is detected
using the VSYNC polarity detection criteria described in section
14.5.1.2.
Technical Data
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Sync Processor
Functional Blocks
14.5.2 Sync Sig na l Counte rs
There are two counters: a 13-bit horizontal frequency counter to count
the number of horizontal sync pulses within a 32ms or 8ms period; and
a 13-bit vertical frequency counter to count the number of system clock
cycles between two vertical sync pulses. These two data can be read by
the CPU to check the signal frequencies and to determine the video
mode.
The 13-bit vertical frequency register encompasses vertical frequency
range from approximately 15Hz to 128kHz. Due to the asynchronous
timing between the incoming VSYNC signal and internal system clock,
there will be ±1 count error on reading the Vertical Frequency
Registers (VFRs) for the same vertical frequency.
The horizontal counter counts the pulses on HSYNC pin input, and is
uploaded to the Hsync Frequency Registers (HFRs) every 32.768ms
or 8.192ms.
14.5.3 Pola rity Controlle d HSYNCO a nd VSYNCO Outp uts
The processed sync signals are output on HSYNCO and VSYNCO when
the corresponding bits in Configuration Register 0 ($001D) are set. The
signal to these output pins depend on SOUT and COMP bits (see Table
14-3), with polarity controlled by ATPOL, HINVO, and VINVO bits as
shown in Table 14-4.
Table 14-3. Sync Output Control
Sync Outputs:
VSYNCO and HSYNCO
SOUT
COMP
1
0
X
0
Free-running pulse with negative polarity
Sync outputs follow sync inputs VSYNC and HSYNC
respectively, with polarity correction shown in Table 14-4 .
HSYNCO follows the composite sync input and VSYNCO
is the extracted Vsync (3 to 14µs delay to composite input),
with polarity correction shown in Table 14-4 .
0
1
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Sync Proc e ssor
Table 14-4. Sync Output Polarity
VINVO
Sync Outputs:
VSYNCO/HSYNCO
ATPOL
SOUT
or
HINVO
X
0
0
1
1
1
0
0
0
0
X
0
1
0
1
Free-running pulse with negative polarity
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
When the SOUT bit is set, the HSYNCO output is a free-running pulse
with 2µs width. Both HSYNCO and VSYNCO outputs are negative
polarity, with frequencies selected by the H & V Sync Output Control
Register (HVOCR).
14.5.4 Cla m p Pulse Outp ut
When the CLAMPOE bit in SPIOCR is set to "1", a clamp signal is output
on the CLAMP pin. This clamp pulse is triggered either on the leading
edge or the trailing edge of HSYNC, controlled by BPOR bit, with the
polarity controlled by the COINV bit. See Figure 14-2 . Clamp Pulse
Output Timing.
HSYNC
(HPOL = 1)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
HSYNC
(HPOL = 0)
CLAMP
(BPOR = 0)
Pulse width = 0.33~2.1µs
CLAMP
(BPOR = 1)
Pulse width = 0.33~2.1µs
Figure 14-2. Clamp Pulse Output Timing
Technical Data
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Sync Processor
Registers
14.5.5 Low Ve rtic a l Fre q ue nc y De te c t
Logic monitors the value of the Vsync Frequency Register (VFR), and
sets the low vertical frequency flag (LVSIF) when the value of VFR is
higher than $C00 (frequency below 40.7Hz). LVSIF bit can generate an
interrupt request to the CPU when the LVSIE bit is set and I-bit in the
Condition Code Register is "0". The LVSIF bit can help the system to
detect video off mode fast.
14.6 Re g iste rs
Eight registers are associated with the Sync Processor, they outlined in
the following sections.
14.6.1 Sync Proc e ssor Control & Sta tus Re g iste r (SPCSR)
Address:
$0040
Bit 7
6
VEDGE
0
5
VSIF
0
4
COMP
0
3
VINVO
0
2
HINVO
0
1
Bit 0
Read:
Write:
Reset:
VPOL
HPOL
VSIE
0
0
0
0
= Unimplemented
Figure 14-3. Sync Processor Control & Status Register (SPCSR)
VSIE — VSync Interrupt Enable
When this bit is set, the VSIF flag is enabled to generate an interrupt
request to the CPU. When VSIE is cleared, the VSIF flag is prevented
from generating an interrupt request to the CPU. Reset clears this bit.
1 = VSIF bit set will generate interrupt request to CPU
0 = VSIF bit set does not generate interrupt request to CPU
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VEDGE — VSync Interrupt Edge Select
This bit specifies the triggering edge of Vsync interrupt. When it is "0",
the rising edge of internal Vsync signal which is either from the
VSYNC pin or extracted from the composite input signal will set VSIF
flag. When it is "1", the falling edge of internal Vsync signal will set
VSIF flag. Reset clears this bit.
1 = VSIF bit will be set by rising edge of Vsync
0 = VSIF bit will be set by falling edge of Vsync
VSIF — VSync Interrupt Flag
This flag is only set by the specified edge of the internal Vsync signal,
which is either from the VSYNC input pin or extracted from the
composite sync input signal. The triggering edge is specified by the
VEDGE bit. VSIF generates an interrupt request to the CPU if the
VSIE bit is also set. This bit is cleared by writing a "0" to it or by a reset.
1 = A valid edge is detected on the Vsync
0 = No valid Vsync is detected
COMP — Composite Sync Input Enable
This bit is set to enable the separator circuit which extracts the Vsync
pulse from the composite sync input on HSYNC or SOG pin (select by
SOGSEL bit). The extracted Vsync signal is used as it were from the
VSYNC input. Reset clears this bit.
1 = Composite Sync Input Enabled
0 = Composite Sync Input Disabled
VINVO — VSYNCO Signal Polarity
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the VSYNCO signal (see Table 14-5).
HINVO — HSYNCO Signal Polarity
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the HSYNCO signal (see Table 14-5).
Technical Data
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Registers
Table 14-5. ATPOL, VINVO, and HINVO setting
Sync Outputs:
VINVO / HINVO
ATPOL
VSYNCO/HSYNCO
0
0
1
1
0
1
0
1
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
VPOL — Vsync Input Polarity
This bit indicates the polarity of the VSYNC input, or the extracted
Vsync from a composite sync input (COMP=1). Reset clears this bit.
1 = Vsync is positive polarity
0 = Vsync is negative polarity
HPOL — Hsync Input Polarity
This bit indicates the polarity of the HSYNC input. This bit equals the
VPOL bit when the COMP bit is set. Reset clears this bit.
1 = Hsync is positive polarity
0 = Hsync is negative polarity
14.6.2 Sync Proc e ssor Inp ut/ Outp ut Control Re g iste r (SPIOCR)
Address:
$0045
Bit 7
6
5
COINV
0
4
R
0
3
2
1
BPOR
0
Bit 0
SOUT
0
Read: VSYNCS HSYNCS
Write:
CLAMPOE
SOGSEL
Reset:
0
0
0
0
= Unimplemented
R
= Reserved
Figure 14-4. Sync Processor Input/Output Control Register (SPIOCR)
VSYNCS — VSYNC Input State
This read-only bit reflects the logical state of the VSYNC input.
HSYNCS — HSYNC Input State
This read-only bit reflects the logical state of the HSYNC input.
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COINV — Clamp Output Invert
This bit is set to invert the clamp pulse output to negative. Reset
clears this bit.
1 = clamp output is set for negative pulses
0 = clamp output is set for positive pulses
SOGSEL — SOG Select
This bit selects either the HSYNC pin or SOG pin as the composite
sync signal input pin. Reset clears this bit.
1 = SOG pin is used as the composite sync input
0 = HSYNC pin is used as the composite sync input
CLAMPOE — Clamp Output Enable
This bit is set to enable the clamp pulse output circuitry. Reset clears
this bit.
1 = Clamp pulse circuit enabled
0 = Clamp pulse circuit disabled
BPOR — Back Porch
This bit defines the triggering edge of the clamp pulse output relative
to the HSYNC input. Reset clears this bit.
1 = Clamp pulse is generated on the trailing edge of HSYNC
0 = Clamp pulse is generated on the leading edge of HSYNC
SOUT — Sync Output Enable
This bit will select the output signals for the VSYNCO and HSYNCO
pins. Reset clears this bit.
1 = VSYNCO and HSYNCO outputs are internally generated
free-running sync pulses with frequencies determined by
HVCOR[2:0] bits in HVCOR.
0 = VSYNCO and HSYNCO outputs are processed VSYNC and
HSYNC inputs respectively
Technical Data
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Registers
14.6.3 Ve rtic a l Fre q ue nc y Re g iste rs (VFRs)
This register pair contains the 13-bit vertical frequency count value, an
overflow bit, and the clamp pulse width selection bits.
Address:
$0041
Bit 7
6
5
4
3
2
1
Bit 0
VF8
Read:
Write:
Reset:
VOF
0
CPW1
0
0
CPW0
0
VF12
VF11
VF10
VF9
0
0
0
0
0
0
Figure 14-5. Vertical Frequency High Register
Address:
$0042
Bit 7
VF7
6
5
4
3
2
1
Bit 0
VF0
Read:
Write:
Reset:
VF6
VF5
VF4
VF3
VF2
VF1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-6. Vertical Frequency Low Register
VF[12:0] — Vertical Frame Frequency\
This read-only 13-bit contains information of the vertical frame
frequency. An internal 13-bit counter counts the number of 8µs
periods between two Vsync pulses. The most significant 5 bits of the
counted value is transferred to the high byte register, and the least
significant 8 bits is transferred to an intermediate buffer. When the
high byte register is read, the 8-bit counted value stored in the
intermediate buffer will be uploaded to the low byte register.
Therefore, user program must read the high byte register first, then
low byte register in order to get the complete counted value of one
vertical frame. If the counter overflows, the overflow flag, VOF, will be
set, indicating the counter value stored in the VFRs is meaningless.
The data corresponds to the period of one vertical frame. This register
can be read to determine if the frame frequency is valid, and to
determine the video mode.
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The frame frequency is calculated by:
1
Vertical Frame Frequency = --------------------------------------------------
VFR ± 1 × 48 × tCYC
1
= -------------------------------------
VFR ± 1 × 8µs
for internal bus clock of 6 MHz
Table 14-6 shows examples for the Vertical Frequency Register, all VFR
numbers are in hexadecimal.
Table 14-6. Sample Vertical Frame Frequencies
VFR
Max Freq.
186.20 Hz
130.34 Hz
130.21 Hz
130.07 Hz
100.08 Hz
100.00 Hz
99.92 Hz
70.07 Hz
70.03 Hz
69.99 Hz
Min Freq.
185.70 Hz
130.07 Hz
129.94 Hz
129.80 Hz
99.92 Hz
99.84 Hz
99.76 Hz
69.99 Hz
69.95 Hz
69.91 Hz
VFR
Max Freq.
65.10 Hz
60.04 Hz
60.01 Hz
59.98 Hz
50.02 Hz
50.00 Hz
49.98 Hz
15.266 Hz
15.264 Hz
15.262 Hz
Min Freq.
65.00 Hz
$02A0
$03C0
$03C1
$03C2
$04E2
$04E3
$04E4
$06F9
$06FA
$06FB
$0780
$0823
$0824
$0825
$09C4
$09C5
$09C6
$1FFD
$1FFE
$1FFF
59.98 Hz
59.95 Hz
59.92 Hz
49.98 Hz
49.96 Hz
49.94 Hz
15.262 Hz
15.260 Hz
15.258 Hz
VOF — Vertical Frequency Counter Overflow
This read-only bit is set when an overflow has occurred on the 13-bit
vertical frequency counter. Reset clears this bit, and will be updated
every vertical frame.
An overflow occurs when the period of Vsync frame exceeds
64.768ms (a vertical frame frequency lower than 15.258Hz).
1 = A vertical frequency counter overflow has occurred
0 = No vertical frequency counter overflow has occurred
Technical Data
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Registers
CPW[1:0] — Clamp Pulse Width
The CPW1 and CPW0 bits are used to select the output clamp pulse
width. Reset clears these bits, selecting a default clamp pulse width
between 0.33µs and 0.375µs. These bits always read as Zeros.
Table 14-7. Clamp Pulse Width
CPW1
CPW0
Clamp Pulse Width
0.33µs to 0.375µs
0.5µs to 0.542µs
0.75µs to 0.792µs
2µs to 2.042µs
0
0
1
1
0
1
0
1
14.6.4 Hsync Fre q ue nc y Re g iste rs (HFRs)
This register pair contains the 13-bit Hsync frequency count value and
an overflow bit.
Address:
$0043
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
HFH7
HFH6
HFH5
HFH4
HFH3
HFH2
HFH1
HFH0
0
0
0
0
0
0
0
0
Figure 14-7. Hsync Frequency High Register
Address:
$0044
Bit 7
6
0
5
0
4
3
2
1
Bit 0
Read: HOVER
Write:
HFL4
HFL3
HFL2
HFL1
HFL0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-8. Hsync Frequency Low Register
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HFH[7:0], HFL[4:0] — Horizontal Line Frequency
This read-only 13-bit contains the number of horizontal lines in a
32ms window. An internal 13-bit counter counts the Hsync pulses
within a 32ms window in every 32.768ms period. If the FSHF bit in
SPCR1 is set, only the most 11-bits (HFH[7:0] & HFL[4:2]) will be
updated by the counter. Thus, providing a Hsync pulse count in a 8ms
window in every 8.192ms.
The most significant 8 bits of counted value is transferred to the high
byte register, and the least significant 5 bits is transferred to an
intermediate buffer. When the high byte register is read, the 5-bit
counted value stored in the intermediate buffer will be uploaded to the
low byte register. Therefore, user the program must read the high byte
register first then low byte register in order to get the complete
counted value of Hsync pulses. If the counter overflows, the overflow
flag, HOVER, will be set, indicating the number of Hsync pulses in
13
32ms are more than 8191 (2 –1), i.e. a Hsync frequency greater
than 256kHz.
For the 32ms window, the HFHR and HFLR are such that the
frequency step unit in the 5-bit of HFLR is 0.03125kHz, and the step
unit in the 8-bit HFHR is 1kHz. Therefore, the Hsync frequency can
be easily calculated by:
Hsync Frequency = [HFH + (HFL × 0.03125)]kHz
where: HFH is the value of HFH[7:0]
HFL is the value of HFL[4:0]
HOVER — Hsync Frequency Counter Overflow
This read-only bit is set when an overflow has occurred on the 13-bit
Hsync frequency counter. Reset clears this bit, and will be updated
every count period.
An overflow occurs when the number Hsync pulses exceed 8191, a
Hsync frequency greater than 256kHz.
1 = A Hsync frequency counter overflow has occurred
0 = No Hsync frequency counter overflow has occurred
Technical Data
MC68HC08BD24 — Rev. 1.0
184
Sync Processor
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Sync Processor
Registers
14.6.5 Sync Proc e ssor Control Re g iste r 1 (SPCR1)
Address:
$0046
Bit 7
6
LVSIF
0
5
HPS1
0
4
HPS0
0
3
2
1
ATPOL
0
Bit 0
FSHF
0
Read:
Write:
Reset:
LVSIE
0
R
R
0
0
0
= Unimplemented
R
= Reserved
Figure 14-9. Sync Processor Control Register 1 (SPCR1)
LVSIE — Low VSync Interrupt Enable
When this bit is set, the LVSIF flag is enabled to generate an interrupt
request to the CPU. When LVSIE is cleared, the LVSIF flag is
prevented from generating an interrupt request to the CPU. Reset
clears this bit.
1 = Low Vsync interrupt enabled
0 = Low Vsync interrupt disabled
LVSIF — Low VSync Interrupt Flag
This read-only bit is set when the value of VFR is higher than $C00
(vertical frame frequency below 40.7Hz). LVSIF generates an
interrupt request to the CPU if the LVSIE is also set. This bit is cleared
by writing a "0" to it or reset.
1 = Vertical frequency is below 40.7Hz
0 = Vertical frequency is higher than 40.7Hz
HPS[1:0] — HSYNC input Detection Pulse Width
These two bits control the detection pulse width of HSYNC input.
Reset clears these two bits, setting a default middle frequency of
HSYNC input.
Table 14-8. HSYNC Polarity Detection Pulse Width
HPS1
HPS0
Polarity Detection Pulse Width
Long > 7µs and Short < 6µs
Long > 3.5µs and Short < 3µs
Long > 14µs and Short < 12µs
0
1
0
0
X
1
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Sync Processor
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Sync Proc e ssor
ATPOL — Auto Polarity
This bit, together with the VINVO or HINVO bits in SPCSR controls
the output polarity of the VSYNCO or HSYNCO signals respectively.
Reset clears this bit (see Table 14-9).
Table 14-9. ATPOL, VINVO, and HINVO setting
Sync Outputs:
ATPOL
VINVO / HINVO
VSYNCO/HSYNCO
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
0
0
1
1
0
1
0
1
FSHF — Fast Horizontal Frequency Count
This bit is set to shorten the measurement cycle of the horizontal
frequency. If it is set, only HFH[7:0] and HFL[4:2] will be updated by
the Hsync counter, providing a count in a 8ms window in every
8.192ms, with HFL[1:0] reading as zeros. Therefore, user can
determine the horizontal frequency change within 8.192ms to protect
critical circuitry. Reset clears this bit.
1 = Number of Hsync pulses is counted in an 8ms window
0 = Number of Hsync pulses is counted in a 32ms window
14.6.6 H&V Sync Outp ut Control Re g iste r (HVOCR)
Address:
$0047
Bit 7
6
0
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
R
0
HVOCR2 HVOCR1 HVOCR0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 14-10. H&V Sync Output Control Register (HVOCR)
Technical Data
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Sync Processor
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Sync Processor
System Operation
HVOCR[2:0] — H&V Output Select Bits
These three bits select the frequencies of the internal generated
free-running sync pulses for output to HSYNCO and VSYNCO pins,
when the SOUT bit is set in the SPIOCR. Reset clears these bits,
setting a default horizontal frequency of 31.25kHz and a vertical
frequency of 60Hz, a video mode of 640×480.
Table 14-10. Free-Running HSYNC and VSYNC Options
HSYNCO
Pulse width
VSYNCO
Pulse width
HVOCR
Video Mode
Frequency
31.25kHz
43.48kHz
48.78kHz
54.05kHz
60.61kHz
80.00kHz
90.91kHz
105.26kHz
Frequency
59.98 Hz
84.92 Hz
60.00 Hz
84.98 Hz
75.01 Hz
74.98 Hz
84.96 Hz
85.02 Hz
000
001
010
011
100
101
110
111
Negative 2µs
Negative 2µs
Negative 2µs
Negative 2µs
Negative 2µs
Negative 2µs
Negative 2µs
Negative 2µs
Negative 192µs
Negative 138µs
Negative 123µs
Negative 111µs
Negative 99µs
Negative 75µs
Negative 66µs
Negative 57µs
640 × 480
640 × 480
1024 × 768
800 × 600
1024 × 768
1280 × 1024
1280 × 1024
1600 × 1200
14.7 Syste m Op e ra tion
This Sync Processor is designed to assist in determining the video mode
of incoming HSYNC and VSYNC of various frequencies and polarities,
and DPMS modes. In the DPMS standard, a no sync pulses definition
can be detected when the value of the Hsync Frequency Register (the
number of Hsync pulses) is less than one or when the VOF bit is set.
Since the Hsync Frequency Register is updated repeatedly in every
32.768ms, and a valid Vsync must have a frequency greater than
40.7Hz, a valid Vsync pulse will arrive within the 32.768ms window.
Therefore, the user should read the Hsync Frequency Register every
32.768ms to determine the presence of Hsync and/or Vsync pulses.
MC68HC08BD24 — Rev. 1.0
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Sync Processor
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Sync Proc e ssor
Technical Data
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Sync Processor
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 15. Inp ut/ Outp ut (I/ O) Ports
15.1 Conte nts
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . .194
15.3.3 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
15.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
15.4.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . .197
15.4.3 Port B Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.5.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
15.5.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . .200
15.5.3 Port C Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
15.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
15.6.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
15.6.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . .203
15.6.3 Port D Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
15.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.7.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
15.7.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . .207
15.7.3 Port E Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
MC68HC08BD24 — Rev. 1.0
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Technical Data
Input/Output (I/O) Ports
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Inp ut/ Outp ut (I/ O) Ports
15.2 Introd uc tion
Thirty-two (32) bidirectional input-output (I/O) pins form four parallel
ports. All I/O pins are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either V or
DD
V . Although the I/O ports do not require termination for proper
SS
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Table 15-1. I/O Port Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Port A Data Register
(PTA)
$0000
Unaffected by reset
PTB7
0
PTB6
0
PTB5
PTC5
PTD5
PTB4
PTB3
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
Port B Data Register
(PTB)
$0001
$0002
$0003
$0004
$0005
Unaffected by reset
PTC4
PTC3
Port C Data Register
(PTC)
Unaffected by reset
0
PTD6
PTD4
PTD3
Port D Data Register
(PTD)
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Data Direction Register A
(DDRA)
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
(DDRB)
= Unimplemented
Technical Data
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Input/Output (I/O) Ports
Introduction
Table 15-1. I/O Port Register Summary (Continued)
Addr.
Register Name
Bit 7
6
5
4
3
2
DDRC2
0
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
DDRC5
0
DDRC4
0
DDRC3
0
Data Direction Register C
(DDRC)
$0006
0
0
0
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
0
DDRD1
0
DDRD0
0
Data Direction Register D
(DDRD)
$0007
$0008
$0009
$001D
$0028
$0049
$0059
0
0
0
0
0
0
0
0
0
0
PTE2
PTE1
PTE0
Port E Data Register
(PTE)
Unaffected by reset
0
0
0
0
0
0
0
DDRE2
DDRE1
DDRE0
Data Direction Register E
(DDRE)
0
SOGE
0
0
0
0
0
0
0
0
0
0
0
HSYNCOE VSYNCOE
Configuration Register 0
(CONFIG0)
0
0
0
0
PWM3E
0
0
PWM2E
0
0
0
PWM7E
PWM6E
PWM5E
PWM4E
PWM1E
PWM0E
PWM Control Register 1
(PWMCR1)
0
0
0
0
0
0
0
CLAMPE
0
0
0
0
0
DDCSCLE DDCDATE
Port D Configuration
Register (PDCR)
0
0
0
0
0
0
0
PWM8E
0
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E
PWM Control Register 2
(PWMCR2)
0
0
0
0
0
0
0
= Unimplemented
MC68HC08BD24 — Rev. 1.0
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Technical Data
Input/Output (I/O) Ports
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Inp ut/ Outp ut (I/ O) Ports
Table 15-2. Port Control Register Bits Summary
Module Control
DDR
Port
Bit
Pin
Module
Register
Control Bit
PWM8E
PWM9E
PWM10E
PWM11E
PWM12E
PWM13E
PWM14E
PWM15E
PWM0E
PWM1E
PWM2E
PWM3E
PWM4E
PWM5E
PWM6E
PWM7E
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
0
1
2
3
4
5
6
0
1
2
DDRA0
DDRA1
DDRA2
DDRA3
DDRA4
DDRA5
DDRA6
DDRA7
DDRB0
DDRB1
DDRB2
DDRB3
DDRB4
DDRB5
DDRB6
DDRB7
DDRC0
DDRC1
DDRC2
DDRC3
DDRC4
DDRC5
DDRD0
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRE0
DDRE1
DDRE2
PTA0/PWM8
PTA1/PWM9
PTA2/PWM10
PTA3/PWM11
PTA4/PWM12
PTA5/PWM13
PTA6/PWM14
PTA7/PWM15
PTB0/PWM0
PTB1/PWM1
PTB2/PWM2
PTB3/PWM3
PTB4/PWM4
PTB5/PWM5
PTB6/PWM6
PTB7/PWM7
PTC0/ADC0
PTC1/ADC1
PTC2/ADC2
PTC3/ADC3/
PTC4/ADC4
PTC5/ADC5
PTD0
PWMCR2
$0059
A
PWM
PWMCR1
$0028
B
PWM
ADSCR
$005D
C
ADC
ADCH[4:0]
—
—
—
—
—
—
PTD1
DDCDATE
DDCSCLE
CLAMPE
—
PTD2/DDCSDA
PTD3/DDCSCL
PTD4/CLAMP
PTD5
DDC12AB
PDCR
$0049
D
E
SYNC
—
—
—
—
—
PTD6
SYNC/TIM
SOGE
PTE0/SOG/TCH0
PTE1/HSYNCO
PTE2/VSYNCO
CONFIG0
$001D
HSYNCOE
VSYNCOE
SYNC
Technical Data
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Port A
15.3 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with
the pulse width modulator (PWM).
15.3.1 Port A Da ta Re g iste r
The port A data register (PTA) contains a data latch for each of the eight
port A pins.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by reset
PWM12 PWM11
Alternate
Function:
PWM15
PWM14
PWM13
PWM10
PWM9
PWM8
Figure 15-1. Port A Data Register (PTA)
PTA7–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
PWM15–PWM8 — PWM Outputs 15–8
The PWM output enable bits PWM15E–PWM8E, in PWM control
register 2 (PWMCR2) enable port A pins as PWM output pins. (See
15.3.3 Port A Options.)
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15.3.2 Da ta Dire c tion Re g iste r A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address:
$0004
Bit 7
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
DDRA7
0
Figure 15-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA7–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-3 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 15-3. Port A I/O Circuit
Technical Data
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Port A
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-3 summarizes
the operation of the port A pins.
Table 15-3. Port A Pin Functions
Accesses
Accesses to PTA
to DDRA
PTAPUE Bit
DDRA Bit PTA Bit I/O Pin Mode
Read/Write
Read
Pin
Write
(1)
(2)
(3)
0
X
0
1
X
Input, Hi-Z
Output
DDRA7–DDRA0
DDRA7–DDRA0
PTA7–PTA0
X
PTA7–PTA0
PTA7–PTA0
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
15.3.3 Port A Op tions
The PWM control register 2 (PWMCR2) selects the port A pins for PWM
function or as standard I/O function. See 11.4.2 PWM Control
Registers 1 and 2 (PWMCR1:PWMCR2).
Address:
$0059
Bit 7
6
5
4
3
2
1
Bit 0
PWM8E
0
Read:
Write:
Reset:
PWM15E PWM14E PWM13E PWM12E PWM11E PWM10E PWM9E
0
0
0
0
0
0
0
Figure 15-4. PWM Control Register 1 (PWMCR1)
PWM15E–PWM8E — PWM Output Enable 15–8
Setting a bit to "1" will configure the corresponding PTAx/PWMx pin
for PWM output function. Reset clears these bits.
1 = PTAx/PWMx pin configured as PWMx output pin
0 = PTAx/PWMx pin configured as standard I/O pin
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15.4 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with
the pulse width modulator (PWM).
15.4.1 Port B Da ta Re g iste r
The port B data register (PTB) contains a data latch for each of the eight
port pins.
Address:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
PWM4 PWM3
Alternate
Function:
PWM7
PWM6
PWM5
PWM2
PWM1
PWM0
Figure 15-5. Port B Data Register (PTB)
PTB7–PTB0 — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
PWM7–PWM0 — PWM Outputs 7–0
The PWM output enable bits PWM7E–PWM0E, in PWM control
register 1 (PWMCR1) enable port B pins as PWM output pins. (See
15.4.3 Port B Options.)
Technical Data
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Port B
15.4.2 Da ta Dire c tion Re g iste r B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address:
$0005
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 15-6. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB7–DDRB0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 15-7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
RESET
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 15-7. Port B I/O Circuit
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When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-4 summarizes
the operation of the port B pins.
Table 15-4. Port B Pin Functions
Accesses
to DDRB
Accesses to PTB
DDRB Bit
PTB Bit
I/O Pin Mode
Read/Write
Read
Pin
Write
(1)
(2)
(3)
0
1
X
Input, Hi-Z
Output
DDRB7–DDRB0
DDRB7–DDRB0
PTB7–PTB0
X
PTB7–PTB0
PTB7–PTB0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
15.4.3 Port B Op tions
The PWM control register 1 (PWMCR1) selects the port B pins for PWM
function or as standard I/O function. See 11.4.2 PWM Control
Registers 1 and 2 (PWMCR1:PWMCR2).
Address:
$0028
Bit 7
6
PWM6E
0
5
PWM5E
0
4
PWM4E
0
3
PWM3E
0
2
PWM2E
0
1
PWM1E
0
Bit 0
PWM0E
0
Read:
Write:
Reset:
PWM7E
0
Figure 15-8. PWM Control Register 1 (PWMCR1)
PWM7E–PWM0E — PWM Output Enable 7–0
Setting a bit to "1" will configure the corresponding PTBx/PWMx pin
for PWM output function. Reset clears these bits.
1 = PTBx/PWMx pin configured as PWMx output pin
0 = PTBx/PWMx pin configured as standard I/O pin
Technical Data
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Port C
15.5 Port C
Port C is an 6-bit special-function port that shares all six of its pins with
the analog-to-digital converter (ADC) module.
15.5.1 Port C Da ta Re g iste r
The port C data register (PTC) contains a data latch for each of the
seven port C pins.
Address:
$0002
Bit 7
0
6
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
Unaffected by reset
ADC4 ADC3
Alternate
Function:
ADC5
ADC2
ADC1
ADC0
= Unimplemented
Figure 15-9. Port C Data Register (PTC)
PTC5–PTC0 — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
ADC5–ADC0 — Analog-to-Digital Input Bits
ADC5–ADC0 are pins used for the input channels to the analog-to-
digital converter module. The channel select bits in the ADC Status
and Control Register define which port C pin will be used as an ADC
input and overrides any control from the port I/O logic by forcing that
pin as the input to the analog circuitry.
NOTE: Care must be taken when reading port C while applying analog voltages
to ADC5–ADC0 pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTCx/ADCx pin, while PTC is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.
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15.5.2 Da ta Dire c tion Re g iste r C
Data direction register C (DDRC) determines whether each port C pin is
an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address:
$0006
Bit 7
0
6
DDRC6
0
5
DDRC5
0
4
DDRC4
0
3
DDRC3
0
2
DDRC2
0
1
DDRC1
0
Bit 0
DDRC0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 15-10. Data Direction Register C (DDRC)
DDRC6–DDRC0 — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC6–DDRC0, configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 15-11 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
RESET
WRITE PTC ($0002)
PTCx
PTCx
READ PTC ($0002)
Figure 15-11. Port C I/O Circuit
Technical Data
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Port C
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-5 summarizes
the operation of the port C pins.
Table 15-5. Port C Pin Functions
Accesses to DDRC
Read/Write
Accesses to PTC
Read Write
PTC6–PTC0
PTC6–PTC0
PTCPUE Bit DDRC Bit PTC Bit I/O Pin Mode
(2)
(3)
0
X
0
1
X
X
Input, Hi-Z
Output
DDRC6–DDRC0
DDRC6–DDRC0
Pin
PTC6–PTC0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
15.5.3 Port C Op tions
The ADCH4–ADCH0 bits in the ADC Status and Control Register
(ADSCR) defines which PTCx/ADCx pin is used as an ADC input and
overrides any control from the port I/O logic by forcing that pin as the
input to the analog circuitry. See 12.8.1 ADC Status and Control
Register.
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15.6 Port D
Port D is an 7-bit special-function port that shares one of its pins with the
sync processor and two of its pins with the DDC12AB module.
NOTE: PTD1 and PTD0 are 3.3V pins.
15.6.1 Port D Da ta Re g iste r
The port D data register (PTD) contains a data latch for each of the eight
port D pins.
Address:
$0003
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset
CLAMP DDCSCL DDCSDA
Alternate
Function:
—
—
—
—
= Unimplemented
Figure 15-12. Port D Data Register (PTD)
PTD6–PTD0 — Port D Data Bits
These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
CLAMP — Sync Processor Clamp pulse output pin
The PTD4/CLAMP pin is the sync processor clamp pulse output pin.
When the CLAMPE bit in the port D configuration register (PDCR) is
clear, the PTD4/CLAMP pin is available for general-purpose I/O. See
15.6.3 Port D Options.
Technical Data
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Port D
DDCSCL, DDCSDA — DDC12AB Data and Clock pins
The PTD3/DDCSCL and PTD2/DDCSDA pins are DDC12AB clock
and data pins respectively. When the DDCSCLE and DDCDATE bits
in the port D configuration register (PDCR) is clear, the
PTD3/DDCSCL and PTD2/DDCSDA pins are available for general-
purpose I/O. See 15.6.3 Port D Options.
15.6.2 Da ta Dire c tion Re g iste r D
Data direction register D (DDRD) determines whether each port D pin is
an input or an output. Writing a logic 1 to a DDRD bit enables the output
buffer for the corresponding port D pin; a logic 0 disables the output
buffer.
Address:
$0007
Bit 7
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Bit 0
DDRD0
0
Read:
Write:
Reset:
0
Figure 15-13. Data Direction Register D (DDRD)
DDRD6–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD6–DDRD0, configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 15-14 shows the port D I/O logic.
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READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
PTDx
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
Figure 15-14. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-6 summarizes
the operation of the port D pins.
Table 15-6. Port D Pin Functions
Accesses to DDRD
Read/Write
Accesses to PTD
Read Write
PTD7–PTD0
PTD7–PTD0
PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode
(2)
(3)
0
X
0
1
X
X
Input, Hi-Z
Output
DDRD7–DDRD0
DDRD7–DDRD0
Pin
PTD7–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Technical Data
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Port D
15.6.3 Port D Op tions
The port D configuration register (PDCR) selects the port D pins for
module function or as standard I/O function.
Address:
$0049
Bit 7
0
6
0
5
0
4
CLAMPE
0
3
2
1
0
Bit 0
0
Read:
Write:
Reset:
DDCSCLE DDCDATE
0
0
0
0
0
0
0
= Unimplemented
Figure 15-15. Port D Configuration Register (PDCR)
CLAMP — CLAMP Pin Enable
This bit is set to configure the PTD4/CLAMP pin for sync processor
clamp pulse output. Reset clears this bit.
1 = PTD4/CLAMP pin configured as CLAMP pin
0 = PTD4/CLAMP pin configured as standard I/O pin
DDCSCLE — DDC Clock Pin Enable
This bit is set to configure the PTD3/DDCSCL pin for DDCSCL
function. Reset clears this bit.
1 = PTD3/DDCSCL pin configured as DDCSCL pin
0 = PTD3/DDCSCL pin configured as standard I/O port
DDCDATE — DDC Data Pin Enable
This bit is set to configure the PTD2/DDCSDA pin for DDCSDA
function. Reset clears this bit.
1 = PTD2/DDCSDA pin configured as DDCSDA pin
0 = PTD2/DDCSDA pin configured as standard I/O port
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15.7 Port E
Port E is a 3-bit special-function port that shares all of its pins with the
sync processor.
15.7.1 Port E Da ta Re g iste r
The port E data register contains a data latch for each of the two port E
pins.
Address:
$0008
Bit 7
0
6
0
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
PTE2
PTE1
PTE0
Unaffected by reset
Alternate
Function:
SOG or
TCH0
VSYNCO HSYNCO
= Unimplemented
Figure 15-16. Port E Data Register (PTE)
PTE2 and PTE0 — Port E Data Bits
PTE2–PTE0 are read/write, software programmable bits. Data
direction of each port E pin is under the control of the corresponding
bit in data direction register E.
VSYNCO — Vsync Output
The PTE2/VSYNCO pin is the Vsync output from the sync processor.
When the VSYNCOE is clear, the PTE2/VSYNCO pin is available for
general-purpose I/O. See 15.7.3 Port E Options.
HSYNC — Hsync Output
The PTE1/HSYNCO pin is the Hsync output from the sync processor.
When the HSYNCOE is clear, the PTE1/HSYNCO pin is available for
general-purpose I/O. See 15.7.3 Port E Options.
Technical Data
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Port E
SOG/TCH0 — SOG Output or TCH0 Input
The PTE0/SOG/TCH0 pin is the SOG input for the sync processor or
the input capture of the TIM channel 0. See 15.7.3 Port E Options.
15.7.2 Da ta Dire c tion Re g iste r E
Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.
Address:
$000C
Bit 7
0
6
0
5
0
4
0
3
0
2
DDRE2
0
1
DDRE1
0
Bit 0
DDRE0
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 15-17. Data Direction Register E (DDRE)
DDRE2–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE2–DDRE0, configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15-18 shows the port E I/O logic.
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READ DDRE ($0009)
WRITE DDRE ($0009)
DDREx
PTEx
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
Figure 15-18. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 15-7 summarizes
the operation of the port E pins.
Table 15-7. Port E Pin Functions
Accesses to DDRE
Read/Write
Accesses to PTE
DDRE Bit
PTE Bit
I/O Pin Mode
Read
Write
(1)
(2)
(3)
0
1
X
Input, Hi-Z
DDRE1–DDRE0
DDRE1–DDRE0]
Pin
PTE1–PTE0
X
Output
PTE1–PTE0
PTE1–PTE0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Technical Data
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Port E
15.7.3 Port E Op tions
The configuration register 0 (CONFIG0) selects the port E pins for
module function or as standard I/O function.
Address:
$001D
Bit 7
6
5
SOGE
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
HSYNCOE VSYNCOE
0
0
0
0
0
0
0
= Unimplemented
Figure 15-19. Configuration Register 0 (CONFIG0)
HSYNCOE — VSYNCO Enable
This bit is set to configure the PTE1/HSYNCO pin for HSYNCO output
function. Reset clears this bit.
1 = PTE1/HSYNCO pin configured as HSYNCO pin
0 = PTE1/HSYNCO pin configured as standard I/O pin
VSYNCOE — VSYNCO Enable
This bit is set to configure the PTE2/VSYNCO pin for VSYNCO output
function. Reset clears this bit.
1 = PTE2/VSYNCO pin configured as VSYNCO pin
0 = PTE2/VSYNCO pin configured as standard I/O pin
SOGE — SOG Enable
This bit is set to configure the PTE0/SOG/TCH0 pin for SOG output
function. Reset clears this bit.
1 = PTE0/SOG/TCH0 pin configured as SOG pin
0 = PTE0/SOG/TCH0 pin configured as standard I/O or TCH0 pin.
TCH0 function is configured by ELS0B and ELS0A bits in
TSC0 (bits 3 and 2 in $0010).
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Technical Data
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 16. Exte rna l Inte rrup t (IRQ)
16.1 Conte nts
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
16.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .215
16.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .215
16.2 Introd uc tion
16.3 Fe a ture s
The IRQ (external interrupt) module provides a maskable interrupt input.
Features of the IRQ module include:
• A dedicated external interrupt pin (IRQ)
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Internal pullup resistor
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Exte rna l Inte rrup t (IRQ)
16.4 Func tiona l De sc rip tion
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 16-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
• Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (INTSCR). Writing a logic 1 to the ACK bit clears
the IRQ latch.
• Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level-
triggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt remains set
until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
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External Interrupt (IRQ)
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External Interrupt (IRQ)
Functional Description
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
ACK
RESET
TO CPU FOR
VECTOR
BIL/BIH
FETCH
INSTRUCTIONS
DECODER
V
DD
INTERNAL
PULLUP
DEVICE
V
DD
IRQF
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
CK
IRQ
IRQ
FF
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 16-1. IRQ Module Block Diagram
Table 16-1. IRQ I/O Register Summary
Addr
Register Name
Bit 7
6
5
4
3
2
0
1
IMASK
0
Bit 0
Read:
Write:
Reset:
0
0
0
0
IRQF
MODE
0
IRQ Status and Control
Register (INTSCR)
$001E
ACK
0
0
0
0
0
0
= Unimplemented
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Exte rna l Inte rrup t (IRQ)
16.5 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-
level-sensitive. With MODE set, both of the following actions must occur
to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ pin. A falling edge that occurs after writing
to the ACK bit another interrupt request. If the IRQ mask bit,
IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
Technical Data
MC68HC08BD24 — Rev. 1.0
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External Interrupt (IRQ)
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External Interrupt (IRQ)
IRQ Module During Break Interrupts
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
16.6 IRQ Mod ule During Bre a k Inte rrup ts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Section 18. Break
Module (BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
16.7 IRQ Sta tus a nd Control Re g iste r
The IRQ status and control register (INTSCR) controls and monitors
operation of the IRQ module. The INTSCR:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
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External Interrupt (IRQ)
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Exte rna l Inte rrup t (IRQ)
Address:
$001E
Bit 7
6
5
4
0
3
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
IRQF
ACK
0
0
0
0
0
= Unimplemented
Figure 16-2. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Technical Data
MC68HC08BD24 — Rev. 1.0
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External Interrupt (IRQ)
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 17. Com p ute r Op e ra ting Prop e rly (COP)
17.1 Conte nts
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
17.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.4.5 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .220
17.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .222
17.2 Introd uc tion
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG register.
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Technical Data
Computer Operating Properly (COP)
217
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Com p ute r Op e ra ting Prop e rly (COP)
17.3 Func tiona l De sc rip tion
Figure 17-1 shows the structure of the COP module.
RESET CIRCUIT
12-BIT COP PRESCALER
OSCXCLK
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG1)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
Figure 17-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
18
4
13
4
and generates an asynchronous reset after 2 – 2 or 2 – 2
OSCXCLK cycles, depending on the state of the COP rate select bit,
18
4
COPRS, in configuration register 1. With a 2 – 2 OSCXCLK cycle
overflow option, a 24MHz crystal gives a COP timeout period of
10.922ms. Writing any value to location $FFFF before an overflow
occurs prevents a COP reset by clearing the COP counter and stages
12 through 5 of the prescaler.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Technical Data
MC68HC08BD24 — Rev. 1.0
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Computer Operating Properly (COP)
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Computer Operating Properly (COP)
I/O Signals
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V
. During the break state, V
on the RST pin disables the COP.
TST
TST
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
17.4 I/ O Sig na ls
The following paragraphs describe the signals shown in Figure 17-1.
17.4.1 OSCXCLK
OSCXCLK is the crystal oscillator output signal. OSCXCLK frequency is
equal to the crystal frequency.
17.4.2 STOP Instruc tion
The STOP instruction clears the COP prescaler.
17.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 17.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
17.4.4 Powe r-On Re se t
The power-on reset (POR) circuit clears the COP prescaler 4096
OSCXCLK cycles after power-up.
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Technical Data
Computer Operating Properly (COP)
219
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Com p ute r Op e ra ting Prop e rly (COP)
17.4.5 Inte rna l Re se t
An internal reset clears the COP prescaler and the COP counter.
17.4.6 Re se t Ve c tor Fe tc h
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
17.4.7 COPD (COP Disa b le )
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register 1 (see Figure 17-2).
17.4.8 COPRS (COP Ra te Se le c t)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1(see Figure 17-2).
Address:
$001F
Bit 7
0
6
0
5
0
4
0
3
SSREC
0
2
COPRS
0
1
STOP
0
Bit 0
COPD
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 17-2. Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
13
4
1 = COP timeout period = 2 – 2 OSCXCLK cycles
18
4
0 = COP timeout period = 2 – 2 OSCXCLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Technical Data
MC68HC08BD24 — Rev. 1.0
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Computer Operating Properly (COP)
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Computer Operating Properly (COP)
COP Control Register
17.5 COP Control Re g iste r
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 17-3. COP Control Register (COPCTL)
17.6 Inte rrup ts
The COP does not generate CPU interrupt requests.
17.7 Monitor Mod e
When monitor mode is entered with V
on the IRQ pin, the COP is
TST
disabled as long as V
remains on the IRQ pin or the RST pin. When
TST
monitor mode is entered by having blank reset vectors and not having
on the IRQ pin, the COP is automatically disabled until a POR
V
TST
occurs.
17.8 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
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Technical Data
Computer Operating Properly (COP)
221
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Com p ute r Op e ra ting Prop e rly (COP)
17.8.1 Wa it Mod e
The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.
17.8.2 Stop Mod e
Stop mode turns off the OSCXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a
configuration option is available that disables the STOP instruction.
When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an
illegal opcode reset.
17.9 COP Mod ule During Bre a k Mod e
The COP is disabled during a break interrupt when V
is present on
TST
the RST pin.
Technical Data
MC68HC08BD24 — Rev. 1.0
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 18. Bre a k Mod ule (BRK)
18.1 Conte nts
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
18.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .226
18.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .226
18.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .226
18.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .226
18.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
18.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
18.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
18.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .227
18.6.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .228
18.6.3 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .228
18.6.4 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .230
18.2 Introd uc tion
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
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Break Module (BRK)
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Bre a k Mod ule (BRK)
18.3 Fe a ture s
Features of the break module include:
• Accessible input/output (I/O) registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
18.4 Func tiona l De sc rip tion
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 18-1 shows the structure of the break module.
Technical Data
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Break Module (BRK)
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Break Module (BRK)
Functional Description
IAB15–IAB8
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
CONTROL
IAB15–IAB0
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB7–IAB0
Figure 18-1. Break Module Block Diagram
Table 18-1. Break Module I/O Register Summary
Addr.
Register Name
Bit 7
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
R
0
SIM Break Status Register
(SBSR)
$FE00
0
BCFE
0
R
R
R
R
R
R
R
SIM Break Flag Control
Register (SBFCR)
$FE03
$FE0C
$FE0D
$FE0E
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
Break Address Register
High (BRKH)
0
Bit 7
0
6
5
4
3
2
Bit 0
Break Address Register
Low (BRKL)
0
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
Break Status and Control
Register (BRKSCR)
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
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Bre a k Mod ule (BRK)
18.4.1 Fla g Prote c tion During Bre a k Inte rrup ts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
18.4.2 CPU During Bre a k Inte rrup ts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
18.4.3 TIM During Bre a k Inte rrup ts
A break interrupt stops the timer counters.
18.4.4 COP During Bre a k Inte rrup ts
The COP is disabled during a break interrupt when V
the RST pin.
is present on
TST
18.5 Low-Powe r Mod e s
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
18.5.1 Wa it Mod e
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see Section 7. System Integration Module (SIM)). Clear the
SBSW bit by writing logic 0 to it.
Technical Data
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Break Module (BRK)
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Break Module (BRK)
Break Module Registers
18.5.2 Stop Mod e
A break interrupt causes exit from stop mode and sets the SBSW bit in
the break status register.
18.6 Bre a k Mod ule Re g iste rs
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• SIM Break status register (SBSR)
• SIM Break flag control register (SBFCR)
18.6.1 Bre a k Sta tus a nd Control Re g iste r
The break status and control register (BRKSCR) contains break module
enable and status bits.
Address: $FE0E
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 18-2. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
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Break Module (BRK)
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Bre a k Mod ule (BRK)
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
18.6.2 Bre a k Ad d re ss Re g iste rs
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Address: $FE0C
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 18-3. Break Address Register High (BRKH)
Address: $FE0D
Bit 7
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 18-4. Break Address Register Low (BRKL)
18.6.3 SIM Bre a k Sta tus Re g iste r
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Technical Data
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Break Module (BRK)
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Break Module (BRK)
Break Module Registers
Address:
$FE00
Bit 7
6
R
0
5
4
3
R
0
2
R
0
1
SBSW
Note
0
Bit 0
R
Read:
Write:
Reset:
R
0
R
R
0
0
0
Note: Writing a logic 0 clears SBSW.
R
= Reserved
Figure 18-5. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example.
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE
LOBYTE
EQU
EQU
5
6
;
If not SBSW, do RTI
BRCLR
SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN
PULH
RTI
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Bre a k Mod ule (BRK)
18.6.4 SIM Bre a k Fla g Control Re g iste r
The SIM break flag control register (SBFCR) contains a bit that enables
software to clear status bits while the MCU is in a break state.
Address:
$FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 18-6. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
Technical Data
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Break Module (BRK)
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 19. Ele c tric a l Sp e c ific a tions
19.1 Conte nts
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
19.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .232
19.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .233
19.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
19.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .234
19.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
19.10 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . .237
19.11 Sync Processor Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
19.12 DDC12AB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
19.12.1 DDC12AB Interface Input Signal Timing . . . . . . . . . . . . . .238
19.12.2 DDC12AB Interface Output Signal Timing . . . . . . . . . . . . .238
19.2 Introd uc tion
This section contains electrical and timing specifications.
MC68HC08BD24 — Rev. 1.0
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Technical Data
Electrical Specifications
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Ele c tric a l Sp e c ific a tions
19.3 Ab solute Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 19.6 DC Electrical Characteristics for guaranteed
operating conditions.
Characteristic
Supply Voltage
Symbol
Value
Unit
V
V
–0.3 to +5.5
DD
Input Voltage
V
V
–0.3 to V +0.3
V
IN
SS
DD
Maximum Current Per Pin
I
±25
mA
Excluding V and V
DD
SS
Storage Temperature
T
–55 to +150
100
°C
mA
mA
STG
Maximum Current Out of V
I
SS
MVSS
MVDD
Maximum Current Into V
I
100
DD
NOTE:
1. Voltages referenced to V
.
SS
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that V and V
be constrained to the
IN
OUT
range V ≤ (V or V
) ≤ V . Reliability of operation is enhanced if
DD
SS
IN
OUT
unused inputs are connected to an appropriate logic voltage level (for
example, either V or V .)
SS
DD
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Electrical Specifications
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Electrical Specifications
Functional Operating Range
19.4 Func tiona l Op e ra ting Ra ng e
Characteristic
Symbol
Value
Unit
°C
Operating Temperature Range
Operating Voltage Range
T
0 to 85
A
V
4.5 to 5.5
V
DD
19.5 The rm a l Cha ra c te ristic s
Characteristic
Thermal Resistance
Symbol
Value
Unit
QFP (44 Pins)
SDIP (42 Pins)
θJA
95
60
°C/W
I/O Pin Power Dissipation
P
User Determined
W
W
I/O
P = (I × V ) + P =
I/O
(1)
D
DD
DD
Power Dissipation
P
D
K/(T + 273 °C)
J
P × (T + 273 °C)
(2)
D
A
Constant
K
W/°C
2
+ P × θJA
D
Average Junction Temperature
Maximum Junction Temperature
NOTES:
T
T + (P × θJA)
°
°
C
C
J
A
D
T
100
JM
1. Power dissipation is a function of temperature.
2. K is a constant unique to the device. K can be determined for a known T and measured
A
P
With this value of K, P and T can be determined for any value of T .
D.
D J A
MC68HC08BD24 — Rev. 1.0
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Electrical Specifications
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Ele c tric a l Sp e c ific a tions
19.6 DC Ele c tric a l Cha ra c te ristic s
(2)
Characteristic
Symbol
Min
Max
Unit
Typ
Output High Voltage (I
All I/O Pins (except PTD0, PTD1, OSC2)
= –2.0mA)
LOAD
V
– 0.8
—
—
—
—
DD
V
V
OH
2
3
PTD0, PTD1, OSC2
-- V – 0.8
DD
Output Low Voltage (I
= 1.6mA)
LOAD
All I/O Pins (except PTD0, PTD1, OSC2)
PTD0, PTD1, OSC2
V
—
—
—
—
0.4
0.4
V
V
OL
Input High Voltage
All ports (except PTD0, PTD1), IRQ, RST
VSYNC, HSYNC
V
0.7 × V
—
—
DD
DD
V
2.0
DD
V
IH
2
3
2
3
PTD0, PTD1, OSC1
—
0.7 × -- V
-- V
DD
DD
Input Low Voltage
All ports (except PTD0, PTD1), IRQ, RST
VSYNC, HSYNC
V
V
—
—
0.2 × V
SS
DD
0.8
SS
V
V
IL
2
3
PTD0, PTD1, OSC1
V
—
0.2 × -- V
SS
DD
V
Supply Current
DD
(3)
—
—
—
8
4
2
12
8
5
mA
mA
mA
Run
Wait
Stop
I
DD
(4)
(5)
0°C to 85°C
I/O Ports Hi-Z Leakage Current
Input Current
I
—
—
—
—
±10
±1
µA
µA
IL
I
IN
Capacitance
Ports (as Input or Output)
C
C
—
—
—
—
12
8
OUT
pF
IN
(6)
POR ReArm Voltage
V
R
0
—
—
—
100
—
8
mV
V/ms
V
POR
POR
(7)
POR Rise Time Ramp Rate
0.035
Monitor Mode Entry Voltage
V
V
+ 2.5
TST
DD
Pull-up Resistor
RST, IRQ
R
20
45
65
kΩ
PU
Low-Voltage Inhibit, trip falling voltage
Low-Voltage Inhibit, trip rising voltage
Low-Voltage Inhibit Reset/Recover Hysteresis
RAM data retention voltage
V
3.4
3.6
—
2
3.6
3.8
200
—
3.8
4.0
—
V
V
TRIPF
V
TRIPR
V
mV
V
HYS
V
—
RDR
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
234
Electrical Specifications
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Electrical Specifications
Control Timing
(2)
Characteristic
Symbol
Min
Max
Unit
Typ
NOTES:
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all
DD
outputs. C = 15 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I . Measured with all modules
L
DD
enabled.
4. Wait I measured using external square wave clock source (f
= 24MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF
OSCXCLK
DD
on all outputs. C = 15pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait I
.
DD
L
5. STOP I measured with OSC1 grounded; no port pins sourcing current.
DD
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
is not reached before the internal POR reset is released, RST must be driven low externally until minimum V is
DD
DD
reached.
19.7 Control Tim ing
Characteristic
Symbol
Min
—
Max
6
Unit
MHz
ns
(2)
Internal Operating Frequency
f
OP
IRL
(3)
RST Input Pulse Width Low
NOTES:
t
50
—
1. V = 5.0 Vdc ± 10%, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted.
DD
SS
DD
DD
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
19.8 Osc illa tor Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
fOSCXCLK
24
MHz
Crystal Frequency
—
—
External Clock
Reference Frequency
fOSCXCLK
dc
—
24
MHz
pF
(1), (2)
(3)
Crystal Load Capacitance
Crystal Fixed Capacitance
C
C
C
—
—
—
—
—
15
2 × C
2 × C
10
—
—
—
—
—
L
1
2
B
S
(3)
(3)
L
L
Crystal Tuning Capacitance
Feedback Bias Resistor
R
R
MΩ
(3), (4)
Series Resistor
—
NOTES:
1. The sync processor module is designed to function at f
The values given here are oscillator specifications.
= 24MHz.
OSCXCLK
2. No more than 10% duty cycle deviation from 50%
3. Consult crystal vendor data sheet
4. Not Required for high frequency crystals
MC68HC08BD24 — Rev. 1.0
Technical Data
MOTOROLA
Electrical Specifications
235
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Ele c tric a l Sp e c ific a tions
19.9 ADC Cha ra c te ristic s
(1)
Symbol
Min
Max
Unit
Comments
Characteristic
4.5
(V
5.5
(V
V
Supply voltage
Input voltages
V
DDAD
DD
DD
min)
max)
2
3
V
0
V
------ V
ADIN
DD
B
Resolution
8
8
Bits
LSB
AD
Absolute accuracy
A
—
± 2
Includes quantization
AD
(V = 0 V, V = 5 V ± 10%)
SS
DD
t
= 1/f
, tested
ADIC
AIC
f
ADC internal clock
Conversion range
0.375
6
MHz
V
ADIC
only at 1.5 MHz
2
3
R
V
------ V
AD
SS
DD
t
t
t
cycles
Power-up time
16
12
ADPU
AIC
AIC
t
cycles
Conversion time
13
—
ADC
t
AIC
(2)
t
Sample time
4
ADS
cycles
Hex
Hex
pF
(3)
Z
Zero input reading
00
FD
—
02
FF
8
ADI
(3)
F
Full-scale reading
ADI
C
Input capacitance
Not tested
ADI
(4)
Input leakage
—
—
± 1
µA
Port C
NOTES:
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
4. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
236
Electrical Specifications
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Electrical Specifications
Timer Interface Module Characteristics
3.5
3.4
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
V
= 5V @ 25°C, ADC Clock = 1.5MHz
DD
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Offset is typically 22mV
0
Steps
Figure 19-1. ADC Input Voltage vs. Step Readings
19.10 Tim e r Inte rfa c e Mod ule Cha ra c te ristic s
Characteristic
Input Capture Pulse Width
Symbol
Min
Max
—
Unit
ns
t
t
125
TIH, TIL
Input Clock Pulse Width
t
t
(1/f ) + 5
—
ns
TCH, TCL
OP
19.11 Sync Proc e ssor Tim ing
Characteristic
VSYNC input sync pulse
Symbol
Min
8
Max
Unit
t
2048
6
µs
µs
µs
µs
VI.SP
t
HSYNC input sync pulse
0.1
30
30
HI.SP
t
VSYNC to VSYNCO delay (8pF loading)
40
VVd
t
HSYNC to HSYNCO delay (8pF loading)
NOTES:
40
HHd
1. V = 5.0 Vdc ± 10%, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted.
DD
SS
DD
DD
MC68HC08BD24 — Rev. 1.0
MOTOROLA
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Electrical Specifications
237
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Ele c tric a l Sp e c ific a tions
19.12 DDC12AB Tim ing
SDA
SCL
t
t
t
t
t
t
t
SU.STO
HD.STA
LOW
HIGH
SU.DAT
HD.DAT
SU.STA
19.12.1 DDC12AB Inte rfa c e Inp ut Sig na l Tim ing
Characteristic
START condition hold time
Clock low period
Symbol
Min
Max
Unit
t
t
2
4
—
—
—
—
—
HD.STA
CYC
t
t
t
LOW
CYC
t
Clock high period
4
HIGH
CYC
t
Data set-up time
250
0
ns
SU.DAT
t
Data hold time
ns
HD.DAT
START condition set-up time
(for repeated START condition only)
t
t
t
2
2
—
—
SU.STA
CYC
t
STOP condition set-up time
NOTES:
SU.STO
CYC
1. V = 5.0 Vdc ± 10%, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted.
DD
SS
DD
DD
19.12.2 DDC12AB Inte rfa c e Outp ut Sig na l Tim ing
Characteristic
Symbol
Min
Max
1
Unit
µs
(2)
t
—
—
SDA/SCL rise time
R
t
SDA/SCL fall time
Data set-up time
300
—
ns
F
t
t
LOW
ns
SU.DAT
t
Data hold time
NOTES:
0
—
ns
HD.DAT
1. V = 5.0 Vdc ± 10%, V = 0 Vdc; timing shown with respect to 20% V and 70% V , unless otherwise noted.
DD
SS
DD
DD
2. With 200pF loading on the SDA/SCL pins.
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
238
Electrical Specifications
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Te c hnic a l Da ta — MC68HC08BD24
Se c tion 20. Me c ha nic a l Sp e c ific a tions
20.1 Conte nts
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
20.3 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . .240
20.4 42-Pin Shrink Dual in-Line Package (SDIP) . . . . . . . . . . . . . .241
20.2 Introd uc tion
This section gives the dimensions for:
• 44-pin plastic quad flat pack (case 824E-02)
• 42-pin shrink dual in-line package (case 858-01)
The following figures show the latest package drawings at the time of
this publication. To make sure that you have the latest package
specifications, contact one of the following:
• Local Motorola Sales Office
• World Wide Web at http://www.motorola.com/semiconductors/
Follow the World Wide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC08BD24 — Rev. 1.0
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Technical Data
Mechanical Specifications
239
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Me c ha nic a l Sp e c ific a tions
20.3 44-Pin Pla stic Qua d Fla t Pa c k (QFP)
S
M
S
S
S
S
0.20 (0.008)
T
L-M
N
N
-L-, -M-, -N-
A
M
0.20 (0.008)
H L-M
PIN 1
IDENT
0.05 (0.002) L-M
J1
J1
G
44
34
33
1
VIEW Y
3 PL
-L-
-M-
F
PLATING
BASE METAL
J
B1
VIEW Y
D
M
S
S
N
0.20 (0.008)
T
L-M
11
23
G
40X
12
22
SECTION J1-J1
44 PL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-N-
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT
DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
M
VIEW P
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE -H-.
E
DATUM
PLANE
C
-H-
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE D DIMENSION TO EXCEED 0.530
(0.021).
0.01 (0.004)
W
-T-
Y
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.90
9.90
2.00
0.30
2.00
0.30
MAX
10.10
10.10
2.21
MIN
MAX
0.398
0.398
0.087
0.390
0.390
0.079
q1
0.45 0.0118 0.0177
2.10
0.40
E
F
0.079
0.012
0.083
0.016
R
R1
G
0.80 BSC
0.031 BSC
J
K
M
0.13
0.65
0.23
0.95
10
0.005
0.026
0.009
0.037
10°
DATUM
PLANE
-H-
R
R2
5
°
°
5
°
S
V
W
Y
A1
B1
C1
R1
R2
q1
q2
12.95
12.95
0.000
13.45
13.45
0.210
0.510
0.510
0.000
10
0.018 REF
0.005
0.063 REF
0.005
0.005
0.530
0.530
0.008
K
5
°
5
°
10
°
°
q2
A1
0.450 REF
0.130
1.600 REF
0.130
0.170
0.007
C1
0.300
0.300
0.012
0.012
10°
0.130
VIEW P
5
0
°
°
10
°
5
0
°
°
7
°
7°
Figure 20-1. 44-Pin QFP (Case 824E)
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
240
Mechanical Specifications
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Mechanical Specifications
42-Pin Shrink Dual in-Line Package (SDIP)
20.4 42-Pin Shrink Dua l in-Line Pa c ka g e (SDIP)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
42
1
22
21
–B–
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
1.465
0.560
0.200
0.022
0.046
MIN
36.45
13.72
3.94
0.36
0.81
MAX
37.21
14.22
5.08
0.56
1.17
L
1.435
0.540
0.155
0.014
0.032
H
C
K
G
H
J
K
L
0.070 BSC
0.300 BSC
1.778 BSC
7.62 BSC
0.008
0.115
0.015
0.135
0.20
2.92
0.38
3.43
–T–
SEATING
PLANE
0.600 BSC
15.24 BSC
N
G
M
N
0°
0.020
15°
0.040
0 °
0.51
15°
1.02
M
F
J 42 PL
0.25 (0.010)
D 42 PL
M
S
T
B
M
S
0.25 (0.010)
T A
Figure 20-2. 42-Pin SDIP (Case 858)
MC68HC08BD24 — Rev. 1.0
MOTOROLA
Technical Data
Mechanical Specifications
241
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Me c ha nic a l Sp e c ific a tions
Technical Data
MC68HC08BD24 — Rev. 1.0
MOTOROLA
242
Mechanical Specifications
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including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
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of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334
Technical Information Center: 1-800-521-6274
HOME PAGE: http://www.motorola.com/semiconductors/
© Motorola, Inc., 2000
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