MC68HC11E9CB3_技术文档

Freescale Semiconductor, Inc.

M68HC11E Family

Data Sheet

M68HC11

Microcontrollers

M68HC11E/D

Rev. 5

6/2003

MOTOROLA.COM/SEMICONDUCTORS

For More Information On This Product,

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Freescale Semiconductor, Inc.

MC68HC11E Family

Data Sheet

To provide the most up-to-date information, the revision of our documents on the

World Wide Web will be the most current. Your printed copy may be an earlier

revision. To verify you have the latest information available, refer to:

http://www.motorola.com/semiconductors/

The following revision history table summarizes changes contained in this

document. For your convenience, the page number designators have been linked

to the appropriate location.

Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc.

M68HC11E Family — Rev. 5

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3

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Revision History

Revision

Level

Page

Number(s)

Date

Description

2.3.3.1 System Configuration Register — Addition to NOCOP bit

description

49

May, 2001

June, 2001

3.1

Added 10.21 EPROM Characteristics

191

10.21 EPROM Characteristics — For clarity, addition to note 2 following the

table

3.2

3.3

December,

2001

7.7.2 Serial Communications Control Register 1 — SCCR1 bit 4 (M)

description corrected

123

169

170

173

179

183

185

10.7 MC68L11E9/E20 DC Electrical Characteristics — Title changed to

include the MC68L11E20

10.8 MC68L11E9/E20 Supply Currents and Power Dissipation — Title

changed to include the MC68L11E20

10.10 MC68L11E9/E20 Control Timing — Title changed to include the

MC68L11E20

10.12 MC68L11E9/E20 Peripheral Port Timing — Title changed to include

the MC68L11E20

July, 2002

4

10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics —

Title changed to include the MC68L11E20

10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics — Title

changed to include the MC68L11E20

10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics — Title

changed to include the MC68L11E20

188

191

— Title changed to include the MC68L11E20

11.4 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)

— Updated table to include MC68L1120

197

Format updated to current publications standards

Throughout

26

1.4.6 Non-Maskable Interrupt (XIRQ/VPPE) — Added Caution note

pertaining to EPROM programming of the MC68HC711E9 device only.

June, 2003

5

10.21 EPROM Characteristics — Added note pertaining to EPROM

programming of the MC68HC711E9 device only.

191

Data Sheet

4

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Revision History

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Data Sheet — M68HC11E Family

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Section 2. Operating Modes and On-Chip Memory . . . . . . . . . . . . . . .33

Section 3. Analog-to-Digital (A/D) Converter . . . . . . . . . . . . . . . . . . . .63

Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . .73

Section 5. Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . .109

Section 7. Serial Communications Interface (SCI). . . . . . . . . . . . . . .117

Section 8. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . .133

Section 9. Timing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Section 10. Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . .165

Section 11. Ordering Information

and Mechanical Specifications . . . . . . . . . . . . . . . . . . .193

Appendix A. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . .203

Appendix B. EVBU Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

AN1060 — M68HC11 Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . .209

EB184 — Enabling the Security Feature

on the MC68HC711E9 Devices with PCbug11

on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

EB188 — Enabling the Security Feature

on M68HC811E2 Devices with PCbug11

on the M68HC711E9PGMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

EB296 — Programming MC68HC711E9 Devices

with PCbug11 and the M68HC11EVBU . . . . . . . . . . . . . . . . . . . . .263

M68HC11E Family — Rev. 5

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List of Sections

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List of Sections

Data Sheet

6

M68HC11E Family — Rev. 5

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List of Sections

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Technical Data — M68HC11E Family

Table of Contents

Section 1. General Description

1.1

1.2

1.3

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4

1.4.1

1.4.2

1.4.3

V_DDand V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Crystal Driver and External Clock Input

(XTAL and EXTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

E-Clock Output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Non-Maskable Interrupt (XIRQ/V_PPE). . . . . . . . . . . . . . . . . . . . . . . . 26

MODA and MODB (MODA/LIR and MODB/V_STBY) . . . . . . . . . . . . . 26

1.4.4

1.4.5

1.4.6

1.4.7

1.4.7.1

1.4.8

1.4.9

1.4.10

1.4.10.1

1.4.10.2

1.4.10.3

1.4.10.4

1.4.10.5

V_RLand V_RH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

STRA/AS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

STRB/R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Section 2. Operating Modes and On-Chip Memory

2.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.2

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.1

2.2.2

2.2.3

2.2.4

2.3

2.3.1

2.3.2

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

RAM and Input/Output Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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2.3.3

System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

System Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . 50

System Configuration Options Register . . . . . . . . . . . . . . . . . . . . 51

2.3.3.1

2.3.3.2

2.3.3.3

2.4

EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Programming an Individual EPROM Address. . . . . . . . . . . . . . . . . . 53

Programming the EPROM with Downloaded Data. . . . . . . . . . . . . . 54

EPROM and EEPROM Programming Control Register . . . . . . . . . . 54

2.4.1

2.4.2

2.4.3

2.5

2.5.1

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

EEPROM and CONFIG Programming and Erasure. . . . . . . . . . . . . 57

Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

EPROM and EEPROM Programming Control Register . . . . . . . . 58

EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

CONFIG Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 61

EEPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.5.1.1

2.5.1.2

2.5.1.3

2.5.1.4

2.5.1.5

2.5.1.6

2.5.2

Section 3. Analog-to-Digital (A/D) Converter

3.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.2

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

A/D Converter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.3

3.4

3.5

3.6

3.7

3.8

3.9

A/D Converter Power-Up and Clock Select . . . . . . . . . . . . . . . . . . . . . . 66

Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Channel Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Single-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Multiple-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Operation in Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A/D Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.10 A/D Converter Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Section 4. Central Processor Unit (CPU)

4.1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Accumulators A, B, and D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2.1

4.2.2

4.2.3

Data Sheet

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5.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Interrupt Recognition and Register Stacking . . . . . . . . . . . . . . . . . 100

Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . . . . . . . . . 100

Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.6

5.6.1

5.6.2

Low-Power Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Section 6. Parallel Input/Output (I/O) Ports

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Parallel I/O Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Section 7. Serial Communications Interface (SCI)

7.1

7.2

7.3

7.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.5

7.5.1

7.5.2

Wakeup Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Address-Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.6

SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.7

SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Serial Communications Data Register . . . . . . . . . . . . . . . . . . . . . . 122

Serial Communications Control Register 1. . . . . . . . . . . . . . . . . . . 123

Serial Communications Control Register 2. . . . . . . . . . . . . . . . . . . 124

Serial Communication Status Register. . . . . . . . . . . . . . . . . . . . . . 125

Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

7.8

7.9

Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Receiver Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Data Sheet

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Section 8. Serial Peripheral Interface (SPI)

8.1

8.2

8.3

8.4

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

8.5

SPI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Master In/Slave Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Master Out/Slave In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Serial Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

8.5.1

8.5.2

8.5.3

8.5.4

8.6

SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.7

SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 138

Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . 140

8.7.1

8.7.2

8.7.3

Section 9. Timing System

9.1

9.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Timer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.3

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Timer Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . 148

9.3.1

9.3.2

9.3.3

9.4

Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Timer Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 149

Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Output Compare Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Output Compare Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Timer Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Timer Interrupt Mask 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Timer Interrupt Flag 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Timer Interrupt Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Timer Interrupt Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.4.9

9.4.10

9.5

Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Timer Interrupt Mask Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Timer Interrupt Flag Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 159

9.5.1

9.5.2

9.5.3

9.6

Computer Operating Properly (COP) Watchdog Function . . . . . . . . . . 159

9.7

Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 161

Pulse Accumulator Count Register. . . . . . . . . . . . . . . . . . . . . . . . . 162

Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . 162

9.7.1

9.7.2

9.7.3

M68HC11E Family — Rev. 5

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Table of Contents

Section 10. Electrical Characteristics

10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

10.2 Maximum Ratings for Standard

and Extended Voltage Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

10.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

10.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

10.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

10.6 Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 168

10.7 MC68L11E9/E20 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 169

10.8 MC68L11E9/E20 Supply Currents

and Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

10.9 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

10.10 MC68L11E9/E20 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.11 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

10.12 MC68L11E9/E20 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . 179

10.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . 182

10.14 MC68L11E9/E20 Analog-to-Digital

Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

10.15 Expansion Bus Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 184

10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics. . . . . . . . . . . 185

10.17 Serial Peripheral Interface Timing Characteristics . . . . . . . . . . . . . . . . 187

10.18 MC68L11E9/E20 Serial Peripheral Interface Characteristics. . . . . . . . 188

10.19 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

10.20 MC68L11E9/E20 EEPROM Characteristics. . . . . . . . . . . . . . . . . . . . . 191

10.21 EPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Section 11. Ordering Information

and Mechanical Specifications

11.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

11.2 Standard Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . 193

11.3 Custom ROM Device Ordering Information . . . . . . . . . . . . . . . . . . . . . 196

11.4 Extended Voltage Device Ordering Information

(3.0 Vdc to 5.5 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

11.5 52-Pin Plastic-Leaded Chip Carrier (Case 778) . . . . . . . . . . . . . . . . . . 198

11.6 52-Pin Windowed Ceramic-Leaded Chip Carrier

(Case 778B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

11.7 64-Pin Quad Flat Pack (Case 840C) . . . . . . . . . . . . . . . . . . . . . . . . . . 200

11.8 52-Pin Thin Quad Flat Pack (Case 848D) . . . . . . . . . . . . . . . . . . . . . . 201

Data Sheet

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Table of Contents

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Table of Contents

Data Sheet

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Data Sheet — M68HC11E Family

Section 1. General Description

1.1 Introduction

This document contains a detailed description of the M68HC11 E series of 8-bit

microcontroller units (MCUs). These MCUs all combine the M68HC11 central

processor unit (CPU) with high-performance, on-chip peripherals.

The E series is comprised of many devices with various configurations of:

•

Random-access memory (RAM)

Read-only memory (ROM)

Erasable programmable read-only memory (EPROM)

Electrically erasable programmable read-only memory (EEPROM)

Several low-voltage devices are also available.

With the exception of a few minor differences, the operation of all E-series MCUs

is identical. A fully static design and high-density complementary metal-oxide

semiconductor (HCMOS) fabrication process allow the E-series devices to operate

at frequencies from 3 MHz to dc with very low power consumption.

1.2 Features

Features of the E-series devices include:

•

M68HC11 CPU

Power-saving stop and wait modes

Low-voltage devices available (3.0–5.5 Vdc)

0, 256, 512, or 768 bytes of on-chip RAM, data retained during standby

0, 12, or 20 Kbytes of on-chip ROM or EPROM

0, 512, or 2048 bytes of on-chip EEPROM with block protect for security

2048 bytes of EEPROM with selectable base address in the MC68HC811E2

Asynchronous non-return-to-zero (NRZ) serial communications interface

(SCI)

•

Additional baud rates available on MC68HC(7)11E20

Synchronous serial peripheral interface (SPI)

8-channel, 8-bit analog-to-digital (A/D) converter

M68HC11E Family — Rev. 5

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General Description

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General Description

•

16-bit timer system:

–

Three input capture (IC) channels

Four output compare (OC) channels

One additional channel, selectable as fourth IC or fifth OC

•

8-bit pulse accumulator

Real-time interrupt circuit

Computer operating properly (COP) watchdog system

38 general-purpose input/output (I/O) pins:

–

16 bidirectional I/O pins

11 input-only pins

11 output-only pins

•

Several packaging options:

–

52-pin plastic-leaded chip carrier (PLCC)

52-pin windowed ceramic leaded chip carrier (CLCC)

52-pin plastic thin quad flat pack, 10 mm x 10 mm (TQFP)

64-pin quad flat pack (QFP)

48-pin plastic dual in-line package (DIP), MC68HC811E2 only

56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP)

1.3 Structure

See Figure 1-1 for a functional diagram of the E-series MCUs. Differences among

devices are noted in the table accompanying Figure 1-1.

Data Sheet

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M68HC11E Family — Rev. 5

General Description

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General Description

Structure

MODA/ MODB/

LIR V_STBY

XTAL EXTAL

E

IRQ XIRQ/V_PPE*RESET

OSC

INTERRUPT

LOGIC

MODE CONTROL

ROM OR EPROM

(SEE TABLE)

CLOCK LOGIC

TIMER

SYSTEM

EEPROM

(SEE TABLE)

M68HC11 CPU

RAM

(SEE TABLE)

SERIAL

COMMUNICATION

SERIAL

PERIPHERAL

INTERFACE

SPI

BUS EXPANSION

ADDRESS

ADDRESS/DATA

V_DD

V_SS

INTERFACE

SCI

V_RH

V_RL

STROBE AND HANDSHAKE

PARALLEL I/O

A/D CONVERTER

CONTROL

PORT A

PORT B

PORT C

PORT D

PORT E

DEVICE

RAM

ROM

EPROM EEPROM

MC68HC11E0

MC68HC11E1

MC68HC11E9

MC68HC711E9

MC68HC11E20

MC68HC711E20

MC68HC811E2

512

768

256

—

12 K

—

20 K

—

12 K

—

20 K

—

512

2048

* V_PPEapplies only to devices with EPROM/OTPROM.

Figure 1-1. M68HC11 E-Series Block Diagram

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General Description

1.4 Pin Descriptions

M68HC11 E-series MCUs are available packaged in:

•

52-pin plastic-leaded chip carrier (PLCC)

52-pin windowed ceramic leaded chip carrier (CLCC)

52-pin plastic thin quad flat pack, 10 mm x 10 mm (TQFP)

64-pin quad flat pack (QFP)

48-pin plastic dual in-line package (DIP), MC68HC811E2 only

56-pin plastic shrink dual in-line package, .070-inch lead spacing (SDIP)

Most pins on these MCUs serve two or more functions, as described in the

following paragraphs. Refer to Figure 1-2, Figure 1-3, Figure 1-4, Figure 1-5, and

Figure 1-6 which show the M68HC11 E-series pin assignments for the

PLCC/CLCC, QFP, TQFP, SDIP, and DIP packages.

46 PE5/AN5

PE1/AN1

45

XTAL

8

9

PC0/ADDR0/DATA0

PC1/ADDR1/DATA1 10

44 PE4/AN4

43 PE0/AN0

42 PB0/ADDR8

11

12

13

14

15

16

PC2/ADDR2/DATA2

PC3/ADDR3/DATA3

PC4/ADDR4/DATA4

PC5/ADDR5/DATA5

PC6/ADDR6/DATA6

PC7/ADDR7/DATA7

PB1/ADDR9

40 PB2/ADDR10

41

M68HC11 E SERIES

PB3/ADDR11

PB4/ADDR12

39

38

37 PB5/ADDR13

36 PB6/ADDR14

RESET 17

18

19

20

* XIRQ/V_PPE

IRQ

PB7/ADDR15

35

34 PA0/IC3

PD0/RxD

* V_PPEapplies only to devices with EPROM/OTPROM.

Figure 1-2. Pin Assignments for 52-Pin PLCC and CLCC

Data Sheet

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General Description

Pin Descriptions

1

2

PA0/IC3

NC

48

47

46

45

44

43

42

41

40

39

38

37

36

PD0/RxD

IRQ

NC

3

(1)

NC

XIRQ/V_PPE

NC

4

5

6

7

8

PB7/ADDR15

PB6/ADDR14

PB5/ADDR13

PB4/ADDR12

RESET

PC7/ADDR7/DATA7

PC6/ADDR6/DATA6

PC5/ADDR5/DATA5

PC4/ADDR4/DATA4

PC3/ADDR3/DATA3

PC2/ADDR2/DATA2

PC1/ADDR1/DATA1

NC

M68HC11 E SERIES

PB3/ADDR11

PB2/ADDR10

PB1/ADDR9

PB0/ADDR8

PE0/AN0

9

10

11

12

13

14

15

16

PE4/AN4

35

34

33

PE1/AN1

PC0/ADDR0/DATA0

XTAL

PE5/AN5

1. V_PPEapplies only to devices with EPROM/OTPROM.

Figure 1-3. Pin Assignments for 64-Pin QFP

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General Description

1

2

PA0/IC3

PB7/ADDR15

PB6/ADDR14

PB5/ADDR13

PB4/ADDR12

PB3/ADDR11

PB2/ADDR10

PB1/ADDR9

PB0/ADDR8

PE0/AN0

PD0/RxD

IRQ

39

38

37

36

35

34

33

32

31

30

29

28

27

(1)

3

XIRQ/V_PPE

RESET

4

5

6

7

8

PC7/ADDR7/DATA7

PC6/ADDR6/DATA6

PC5/ADDR5/DATA5

M68HC11 E SERIES

PC4/ADDR4/DATA4

PC3/ADDR3/DATA3

PC2/ADDR2/DATA2

PC1/ADDR1/DATA1

PC0/ADDR0/DATA0

XTAL

9

10

11

12

13

PE4/AN4

PE1/AN1

PE5/AN5

1. V_PPEapplies only to devices with EPROM/OTPROM.

Figure 1-4. Pin Assignments for 52-Pin TQFP

Data Sheet

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General Description

Pin Descriptions

V_SS

EV_SS

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

MODB/V_STBY

V_RH

MODA/LIR

STRA/AS

V_RL

PE7/AN7

PE3/AN3

PE6/AN6

PE2/AN2

PE5/AN5

PE1/AN1

PE4/AN4

PE0/AN0

PB0/ADDR8

PB1/ADDR9

PB2/ADDR10

PB3/ADDR11

PB4/ADDR12

PB5/ADDR13

PB6/ADDR14

E

STRB/R/W

EXTAL

XTAL

PC0/ADDR0/DATA0

PC1/ADDR1/DATA1

PC2/ADDR2/DATA2

PC3/ADDR3/DATA3

PC4/ADDR4/DATA4

PC5/ADDR5/DATA5

PC6/ADDR6/DATA6

PC7/ADDR7/DATA7

RESET

9

10

11

12

13

14

15

16

17

M68HC11 E SERIES

* XIRQ/V_PPE

18

19

20

21

IRQ

PD0/RxD

EV_SS

PB7/ADDR15

PA0/IC3

PA1/IC2

PA2/IC1

PD1/TxD

PD2/MISO

PD3/MOSI

PD4/SCK

PD5/SS

V_DD

22

23

24

25

26

27

28

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

EV_DD

V_SS

* V_PPEapplies only to devices with EPROM/OTPROM.

Figure 1-5. Pin Assignments for 56-Pin SDIP

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General Description

PA7/PAI/OC1

PA6/OC2/OC1

PA5/OC3/OC1

PA4/OC4/OC1

PA3/OC5/IC4/OC1

PA2/IC1

48 V_DD

1

PD5/SS

47

2

46 PD4/SCK

3

PD3/MOSI

44 PD2/MISO

PD1/TxD

42 PD0/RxD

IRQ

40 XIRQ

45

4

5

43

6

PA1/IC2

7

PA0/IC3

41

8

PB7/ADDR15

PB6/ADDR14

PB5/ADDR13

PB4/ADDR12

PB3/ADDR11

PB2/ADDR10

PB1/ADDR9

PB0/ADDR8

PE0/AN0

9

RESET

39

10

11

12

13

14

15

16

17

38 PC7/ADDR7/DATA7

37 PC6/ADDR6/DATA6

36 PC5/ADDR5/DATA5

35 PC4/ADDR4/DATA4

34 PC3/ADDR3/DATA3

MC68HC811E2

PC2/ADDR2/DATA2

PC1/ADDR1/DATA1

PC0/ADDR0/DATA0

33

32

31

PE1/AN1

18

19

20

21

PE2/AN2

30 XTAL

PE3/AN3

29 EXTAL

28 STRB/R/W

V_RL

V_RH

22

23

24

27

E

V_SS

26 STRA/AS

25 MODA/LIR

MODB/V_STBY

Figure 1-6. Pin Assignments for 48-Pin DIP (MC68HC811E2)

Data Sheet

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General Description

Pin Descriptions

1.4.1 V_DDand V_SS

Power is supplied to the MCU through V_DDand V_SS. V_DDis the power supply, V_SS

is ground. The MCU operates from a single 5-volt (nominal) power supply.

Low-voltage devices in the E series operate at 3.0–5.5 volts.

Very fast signal transitions occur on the MCU pins. The short rise and fall times

place high, short duration current demands on the power supply. To prevent noise

problems, provide good power supply bypassing at the MCU. Also, use bypass

capacitors that have good

high-frequency characteristics and situate them as close to the MCU as possible.

Bypass requirements vary, depending on how heavily the MCU pins are loaded.

V

DD

2

4.7 kΩ

IN

1

TO RESET

OF M68HC11

RESET

MC34(0/1)64

GND

3

Figure 1-7. External Reset Circuit

V

DD

IN

4.7 kΩ

TO RESET

OF M68HC11

RESET

MC34064

V

DD

GND

4.7 kΩ

1.0 µF

MANUAL

RESET SWITCH

4.7 kΩ

IN

RESET

MC34164

GND

OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH

Figure 1-8. External Reset Circuit with Delay

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General Description

1.4.2 RESET

A bidirectional control signal, RESET, acts as an input to initialize the MCU to a

known startup state. It also acts as an open-drain output to indicate that an internal

failure has been detected in either the clock monitor or computer operating properly

(COP) watchdog circuit. The CPU distinguishes between internal and external

reset conditions by sensing whether the reset pin rises to a logic 1 in less than two

E-clock cycles after a reset has occurred. See Figure 1-7 and Figure 1-8.

CAUTION:

Do not connect an external resistor capacitor (RC) power-up delay circuit to the

reset pin of M68HC11 devices because the circuit charge time constant can cause

the device to misinterpret the type of reset that occurred.

Because the CPU is not able to fetch and execute instructions properly when V_DD

falls below the minimum operating voltage level, reset must be controlled. A

low-voltage inhibit (LVI) circuit is required primarily for protection of EEPROM

contents. However, since the configuration register (CONFIG) value is read from

the EEPROM, protection is required even if the EEPROM array is not being used.

Presently, there are several economical ways to solve this problem. For example,

two good external components for LVI reset are:

1. The Seiko S0854HN (or other S805 series devices):

a. Extremely low power (2 µA)

a. TO-92 package

a. Limited temperature range, –20°C to +70°C

a. Available in various trip-point voltage ranges

2. The Motorola MC34064:

a. TO-92 or SO-8 package

a. Draws about 300 µA

a. Temperature range –40°C to 85°C

a. Well controlled trip point

a. Inexpensive

Refer to Section 5. Resets and Interrupts for further information.

1.4.3 Crystal Driver and External Clock Input (XTAL and EXTAL)

These two pins provide the interface for either a crystal or a CMOS- compatible

clock to control the internal clock generator circuitry. The frequency applied to

these pins is four times higher than the desired E-clock rate.

The XTAL pin must be left unterminated when an external CMOS- compatible clock

input is connected to the EXTAL pin. The XTAL output is normally intended to drive

only a crystal. Refer to Figure 1-9 and Figure 1-10.

Data Sheet

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General Description

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General Description

Pin Descriptions

CAUTION:

In all cases, use caution around the oscillator pins. Load capacitances shown in the

oscillator circuit are specified by the crystal manufacturer and should include all

stray layout capacitances.

C_L

EXTAL

10 MΩ

4 x E

CRYSTAL

MCU

C_L

XTAL

Figure 1-9. Common Parallel Resonant Crystal Connections

4 x E

CMOS-COMPATIBLE

EXTERNAL OSCILLATOR

EXTAL

MCU

XTAL

NC

Figure 1-10. External Oscillator Connections

1.4.4 E-Clock Output (E)

E is the output connection for the internally generated E clock. The signal from E

is used as a timing reference. The frequency of the E-clock output is one fourth that

of the input frequency at the XTAL and EXTAL pins. When E-clock output is low,

an internal process is taking place. When it is high, data is being accessed.

All clocks, including the E clock, are halted when the MCU is in stop mode. To

reduce RFI emissions, the E-clock output of most E-series devices can be disabled

while operating in single-chip modes.

The E-clock signal is always enabled on the MC68HC811E2.

1.4.5 Interrupt Request (IRQ)

The IRQ input provides a means of applying asynchronous interrupt requests to the

MCU. Either negative edge-sensitive triggering or level-sensitive triggering is

program selectable (OPTION register). IRQ is always configured to level-sensitive

triggering at reset. When using IRQ in a level-sensitive wired-OR configuration,

connect an external pullup resistor, typically 4.7 kΩ, to V_DD

.

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General Description

1.4.6 Non-Maskable Interrupt (XIRQ/V_PPE

)

The XIRQ input provides a means of requesting a non-maskable interrupt after

reset initialization. During reset, the X bit in the condition code register (CCR) is set

and any interrupt is masked until MCU software enables it. Because the XIRQ input

is level-sensitive, it can be connected to a multiple-source wired-OR network with

an external pullup resistor to V_DD. XIRQ is often used as a power loss detect

interrupt.

Whenever XIRQ or IRQ is used with multiple interrupt sources each source must

drive the interrupt input with an open-drain type of driver to avoid contention

between outputs.

NOTE:

IRQ must be configured for level-sensitive operation if there is more than one

source of IRQ interrupt.

There should be a single pullup resistor near the MCU interrupt input pin (typically

4.7 kΩ). There must also be an interlock mechanism at each interrupt source so

that the source holds the interrupt line low until the MCU recognizes and

acknowledges the interrupt request. If one or more interrupt sources are still

pending after the MCU services a request, the interrupt line will still be held low and

the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is

cleared (normally upon return from an interrupt). Refer to Section 5. Resets and

Interrupts.

V_PPEis the input for the 12-volt nominal programming voltage required for

EPROM/OTPROM programming. On devices without EPROM/OTPROM, this pin

is only an XIRQ input.

CAUTION:

During EPROM programming of the MC68HC711E9 device, the V_PPEpin circuitry

may latch-up and be damaged if the input current is not limited to 10 mA. For more

information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set

Errata 3 (Motorola document order number 68HC711E9MSE3.

1.4.7 MODA and MODB (MODA/LIR and MODB/V_STBY

)

During reset, MODA and MODB select one of the four operating modes:

•

Single-chip mode

Expanded mode

Test mode

Bootstrap mode

Refer to Section 2. Operating Modes and On-Chip Memory.

After the operating mode has been selected, the load instruction register (LIR) pin

provides an open-drain output to indicate that execution of an instruction has

begun. A series of E-clock cycles occurs during execution of each instruction. The

LIR signal goes low during the first E-clock cycle of each instruction (opcode fetch).

This output is provided for assistance in program debugging.

Data Sheet

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M68HC11E Family — Rev. 5

General Description

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Pin Descriptions

The V_STBYpin is used to input random-access memory (RAM) standby power.

When the voltage on this pin is more than one MOS threshold (about 0.7 volts)

above the V_DDvoltage, the internal RAM and part of the reset logic are powered

from this signal rather than the V_DDinput. This allows RAM contents to be retained

without V_DDpower applied to the MCU. Reset must be driven low before V_DDis

removed and must remain low until V_DDhas been restored to a valid level.

1.4.7.1 V_RLand V_RH

These two inputs provide the reference voltages for the analog-to-digital (A/D)

converter circuitry:

•

V

_RLis the low reference, typically 0 Vdc.

_RHis the high reference.

V

For proper A/D converter operation:

•

V

_RHshould be at least 3 Vdc greater than V_RL.

_RLand V_RHshould be between V_SSand V_DD

V

.

1.4.8 STRA/AS

The strobe A (STRA) and address strobe (AS) pin performs either of two separate

functions, depending on the operating mode:

•

In single-chip mode, STRA performs an input handshake (strobe input)

function.

•

In the expanded multiplexed mode, AS provides an address strobe function.

AS can be used to demultiplex the address and data signals at port C. Refer to

Section 2. Operating Modes and On-Chip Memory.

1.4.9 STRB/R/W

The strobe B (STRB) and read/write (R/W) pin act as either an output strobe or as

a data bus direction indicator, depending on the operating mode.

In single-chip operating mode, STRB acts as a programmable strobe for

handshake with other parallel devices. Refer to Section 6. Parallel Input/Output

(I/O) Ports for further information.

In expanded multiplexed operating mode, R/W is used to indicate the direction of

transfers on the external data bus. A low on the R/W pin indicates data is being

written to the external data bus. A high on this pin indicates that a read cycle is in

progress. R/W stays low during consecutive data bus write cycles, such as a

double-byte store. It is possible for data to be driven out of port C, if internal read

visibility (IRV) is enabled and an internal address is read, even though R/W is in a

high-impedance state. Refer to Section 2. Operating Modes and On-Chip

Memory for more information about IRVNE (internal read visibility not E).

M68HC11E Family — Rev. 5

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General Description

1.4.10 Port Signals

Port pins have different functions in different operating modes. Pin functions for

port A, port D, and port E are independent of operating modes. Port B and port C,

however, are affected by operating mode. Port B provides eight general-purpose

output signals in single-chip operating modes. When the microcontroller is in

expanded multiplexed operating mode, port B pins are the eight high-order address

lines.

Port C provides eight general-purpose input/output signals when the MCU is in the

single-chip operating mode. When the microcontroller is in the expanded

multiplexed operating mode, port C pins are a multiplexed address/data bus.

Refer to Table 1-1 for a functional description of the 40 port signals within different

operating modes. Terminate unused inputs and input/output (I/O) pins configured

as inputs high or low.

1.4.10.1 Port A

In all operating modes, port A can be configured for three timer input capture (IC)

functions and four timer output compare (OC) functions. An additional pin can be

configured as either the fourth IC or the fifth OC. Any port A pin that is not currently

being used for a timer function can be used as either a general-purpose input or

output line. Only port A pins PA7 and PA3 have an associated data direction

control bit that allows the pin to be selectively configured as input or output. Bits

DDRA7 and DDRA3 located in PACTL register control data direction for PA7 and

PA3, respectively. All other port A pins are fixed as either input or output.

PA7 can function as general-purpose I/O or as timer output compare for OC1. PA7

is also the input to the pulse accumulator, even while functioning as a

general-purpose I/O or an OC1 output.

PA6–PA4 serve as either general-purpose outputs, timer input captures, or timer

output compare 2–4. In addition, PA6–PA4 can be controlled by OC1.

PA3 can be a general-purpose I/O pin or a timer IC/OC pin. Timer functions

associated with this pin include OC1 and IC4/OC5. IC4/OC5 is software selectable

as either a fourth input capture or a fifth output compare. PA3 can also be

configured to allow OC1 edges to trigger IC4 captures.

PA2–PA0 serve as general-purpose inputs or as IC1–IC3.

PORTA can be read at any time. Reads of pins configured as inputs return the logic

level present on the pin. Pins configured as outputs return the logic level present

at the pin driver input. If written, PORTA stores the data in an internal latch, bits 7

and 3. It drives the pins only if they are configured as outputs. Writes to PORTA do

not change the pin state when pins are configured for timer input captures or output

compares. Refer to Section 6. Parallel Input/Output (I/O) Ports.

Data Sheet

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M68HC11E Family — Rev. 5

General Description

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General Description

Pin Descriptions

Table 1-1. Port Signal Functions

Single-Chip and

Port/Bit

Expanded and

Test Modes

Bootstrap Modes

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

—

PA0/IC3

PA1/IC2

PA2/IC1

PA3/OC5/IC4/OC1

PA4/OC4/OC1

PA5/OC3/OC1

PA6/OC2/OC1

PA7/PAI/OC1

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR0/DATA0

ADDR1/DATA1

ADDR2/DATA2

ADDR3/DATA3

ADDR4/DATA4

ADDR5/DATA5

ADDR6/DATA6

ADDR7/DATA7

PD0/RxD

PD1/TxD

PD2/MISO

PD3/MOSI

PD4/SCK

PD5/SS

STRA

STRB

AS

—

R/W

PE0

PE1

PE2

PE3

PE4

PE5

PE6

PE7

PE0/AN0

PE1/AN1

PE3/AN2

PE3/AN3

PE4/AN4

PE5/AN5

PE6/AN6

PE7/AN7

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1.4.10.2 Port B

During single-chip operating modes, all port B pins are general-purpose output

pins. During MCU reads of this port, the level sensed at the input side of the port B

output drivers is read. Port B can also be used in simple strobed output mode. In

this mode, an output pulse appears at the STRB signal each time data is written to

port B.

In expanded multiplexed operating modes, all of the port B pins act as high order

address output signals. During each MCU cycle, bits 15–8 of the address bus are

output on the PB7–PB0 pins. The PORTB register is treated as an external

address in expanded modes.

1.4.10.3 Port C

While in single-chip operating modes, all port C pins are general-purpose I/O pins.

Port C inputs can be latched into an alternate PORTCL register by providing an

input transition to the STRA signal. Port C can also be used in full handshake

modes of parallel I/O where the STRA input and STRB output act as handshake

control lines.

When in expanded multiplexed modes, all port C pins are configured as

multiplexed address/data signals. During the address portion of each MCU cycle,

bits 7–0 of the address are output on the PC7–PC0 pins. During the data portion

of each MCU cycle (E high), PC7–PC0 are bidirectional data signals,

DATA7–DATA0. The direction of data at the port C pins is indicated by the R/W

signal.

The CWOM control bit in the PIOC register disables the port C P-channel output

driver. CWOM simultaneously affects all eight bits of port C. Because the

N-channel driver is not affected by CWOM, setting CWOM causes port C to

become an open-drain type output port suitable for wired-OR operation.

In wired-OR mode:

•

When a port C bit is at logic level 0, it is driven low by the N-channel driver.

When a port C bit is at logic level 1, the associated pin has high-impedance,

as neither the N-channel nor the P-channel devices are active.

It is customary to have an external pullup resistor on lines that are driven by

open-drain devices. Port C can only be configured for wired-OR operation when

the MCU is in single-chip mode. Refer to Section 6. Parallel Input/Output (I/O)

Ports for additional information about port C functions.

Data Sheet

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M68HC11E Family — Rev. 5

General Description

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Pin Descriptions

1.4.10.4 Port D

Pins PD5–PD0 can be used for general-purpose I/O signals. These pins alternately

serve as the serial communication interface (SCI) and serial peripheral interface

(SPI) signals when those subsystems are enabled.

•

PD0 is the receive data input (RxD) signal for the SCI.

PD1 is the transmit data output (TxD) signal for the SCI.

PD5–PD2 are dedicated to the SPI:

–

PD2 is the master in/slave out (MISO) signal.

PD3 is the master out/slave in (MOSI) signal.

PD4 is the serial clock (SCK) signal.

PD5 is the slave select (SS) input.

1.4.10.5 Port E

Use port E for general-purpose or analog-to-digital (A/D) inputs.

CAUTION:

If high accuracy is required for A/D conversions, avoid reading port E during

sampling, as small disturbances can reduce the accuracy of that result.

M68HC11E Family — Rev. 5

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General Description

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Data Sheet — M68HC11E Family

Section 2. Operating Modes and On-Chip Memory

2.1 Introduction

This section contains information about the operating modes and the on-chip

memory for M68HC11 E-series MCUs. Except for a few minor differences,

operation is identical for all devices in the E series. Differences are noted where

necessary.

2.2 Operating Modes

The values of the mode select inputs MODB and MODA during reset determine the

operating mode. Single-chip and expanded multiplexed are the normal modes.

•

In single-chip mode only on-chip memory is available.

Expanded mode, however, allows access to external memory.

Each of the two normal modes is paired with a special mode:

•

Bootstrap, a variation of the single-chip mode, is a special mode that

executes a bootloader program in an internal bootstrap ROM.

•

Test is a special mode that allows privileged access to internal resources.

2.2.1 Single-Chip Mode

In single-chip mode, ports B and C and strobe pins A (STRA) and B (STRB) are

available for general-purpose parallel input/output (I/O). In this mode, all software

needed to control the MCU is contained in internal resources. If present, read-only

memory (ROM) and/or erasable, programmable read-only memory (EPROM) will

always be enabled out of reset, ensuring that the reset and interrupt vectors will be

available at locations $FFC0–$FFFF.

NOTE:

For the MC68HC811E2, the vector locations are the same; however, they are

contained in the 2048-byte EEPROM array.

2.2.2 Expanded Mode

In expanded operating mode, the MCU can access the full 64-Kbyte address

space. The space includes:

•

The same on-chip memory addresses used for single-chip mode

Addresses for external peripherals and memory devices

M68HC11E Family — Rev. 5

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Operating Modes and On-Chip Memory

The expansion bus is made up of ports B and C, and control signals AS (address

strobe) and R/W (read/write). R/W and AS allow the low-order address and the

8-bit data bus to be multiplexed on the same pins. During the first half of each bus

cycle address information is present. During the second half of each bus cycle the

pins become the bidirectional data bus. AS is an active-high latch enable signal for

an external address latch. Address information is allowed through the transparent

latch while AS is high and is latched when AS drives low.

The address, R/W, and AS signals are active and valid for all bus cycles, including

accesses to internal memory locations. The E clock is used to enable external

devices to drive data onto the internal data bus during the second half of a read bus

cycle (E clock high). R/W controls the direction of data transfers. R/W drives low

when data is being written to the internal data bus. R/W will remain low during

consecutive data bus write cycles, such as when a double-byte store occurs.

Refer to Figure 2-1.

NOTE:

The write enable signal for an external memory is the NAND of the E clock and the

inverted R/W signal.

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

HC373

Q1

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

D1

D2

D3

D4

D5

D6

D7

D8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

Q2

Q3

Q4

Q5

Q6

Q7

Q8

LE

OE

AS

R/W

E

WE

OE

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

MCU

Figure 2-1. Address/Data Demultiplexing

2.2.3 Test Mode

Test mode, a variation of the expanded mode, is primarily used during Motorola’s

internal production testing; however, it is accessible for programming the

Data Sheet

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M68HC11E Family — Rev. 5

Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

Memory Map

configuration (CONFIG) register, programming calibration data into electrically

erasable, programmable read-only memory (EEPROM), and supporting emulation

and debugging during development.

2.2.4 Bootstrap Mode

When the MCU is reset in special bootstrap mode, a small on-chip read-only

memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a

bootloader program and a special set of interrupt and reset vectors. The MCU

fetches the reset vector, then executes the bootloader.

Bootstrap mode is a special variation of the single-chip mode. Bootstrap mode

allows special-purpose programs to be entered into internal random-access

memory (RAM). When bootstrap mode is selected at reset, a small bootstrap ROM

becomes present in the memory map. Reset and interrupt vectors are located in

this ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which

initializes the serial communications interface (SCI) and allows the user to

download a program into on-chip RAM. The size of the downloaded program can

be as large as the size of the on-chip RAM. After a 4-character delay, or after

receiving the character for the highest address in RAM, control passes to the

loaded program at $0000. Refer to Figure 2-2, Figure 2-3, Figure 2-4, Figure 2-5,

and Figure 2-6.

Use of an external pullup resistor is required when using the SCI transmitter pin

because port D pins are configured for wired-OR operation by the bootloader. In

bootstrap mode, the interrupt vectors are directed to RAM. This allows the use of

interrupts through a jump table. Refer to the application note AN1060 entitled

M68HC11 Bootstrap Mode, that is included in this data book.

2.3 Memory Map

The operating mode determines memory mapping and whether external

addresses can be accessed. Refer to Figure 2-2, Figure 2-3, Figure 2-4,

Figure 2-5, and Figure 2-6, which illustrate the memory maps for each of the three

families comprising the M68HC11 E series of MCUs.

Memory locations for on-chip resources are the same for both expanded and

single-chip modes. Control bits in the configuration (CONFIG) register allow

EPROM and EEPROM (if present) to be disabled from the memory map. The RAM

is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary ($x000)

by writing an appropriate value to the RAM and I/O map register (INIT). The 64-byte

register block is mapped to $1000 after reset and also can be placed at any 4-Kbyte

boundary ($x000) by writing an appropriate value to the INIT register. If RAM and

registers are mapped to the same boundary, the first 64 bytes of RAM will be

inaccessible.

Refer to Figure 2-7, which details the MCU register and control bit assignments.

Reset states shown are for single-chip mode only.

M68HC11E Family — Rev. 5

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Operating Modes and On-Chip Memory

$0000

$1000

0000

512 BYTES RAM

EXT

01FF

1000

64-BYTE REGISTER BLOCK

103F

$B600

$D000

$FFFF

EXT

BOOT

ROM

BFC0

BFFF

BF00

BFFF

SPECIAL MODES

INTERRUPT

VECTORS

NORMAL

MODES

INTERRUPT

VECTORS

FFC0

FFFF

EXPANDED

BOOTSTRAP

SPECIAL

TEST

Figure 2-2. Memory Map for MC68HC11E0

0000

$0000

$1000

512 BYTES RAM

EXT

01FF

1000

64-BYTE REGISTER BLOCK

103F

EXT

B600

512 BYTES EEPROM

$B600

$D000

$FFFF

B7FF

BF00

BOOT

ROM

BFC0

BFFF

SPECIAL MODES

INTERRUPT

VECTORS

EXT

BFFF

NORMAL

MODES

INTERRUPT

VECTORS

FFC0

FFFF

EXPANDED

BOOTSTRAP

SPECIAL

TEST

Figure 2-3. Memory Map for MC68HC11E1

Data Sheet

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M68HC11E Family — Rev. 5

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Memory Map

0000

$0000

$1000

512 BYTES RAM

EXT

01FF

1000

64-BYTE REGISTER BLOCK

103F

B600

512 BYTES EEPROM

$B600

$D000

$FFFF

B7FF

BF00

BOOT

ROM

BFC0

BFFF

SPECIAL MODES

INTERRUPT

VECTORS

EXT

BFFF

D000

12 KBYTES ROM/EPROM

FFC0

NORMAL

MODES

INTERRUPT

VECTORS

FFFF

SINGLE

CHIP

EXPANDED

BOOTSTRAP

SPECIAL

TEST

Figure 2-4. Memory Map for MC68HC(7)11E9

0000

$0000

$1000

768 BYTES RAM

EXT

02FF

1000

64-BYTE REGISTER BLOCK

103F

9000

8 KBYTES ROM/EPROM *

512 BYTES EEPROM

$9000

$B600

AFFF

B600

EXT

B7FF

BF00

BOOT

BFC0

ROM

SPECIAL MODES

INTERRUPT

VECTORS

BFFF

D000

$D000

$FFFF

12 KBYTES ROM/EPROM *

FFC0

NORMAL

MODES

INTERRUPT

FFFF

FFFF VECTORS

SINGLE

CHIP

EXPANDED

BOOTSTRAP

SPECIAL

TEST

* 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each.

Figure 2-5. Memory Map for MC68HC(7)11E20

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$0000

$1000

0000

00FF

256 BYTES RAM

EXT

1000

103F

64-BYTE REGISTER BLOCK

EXT

BOOT

ROM

BFC0

BFFF

SPECIAL MODES

INTERRUPT

VECTORS

BF00

BFFF

2048 BYTES EEPROM

$F800

$FFFF

F800

FFFF

NORMAL

MODES

INTERRUPT

FFC0

FFFF VECTORS

SINGLE

CHIP

EXPANDED

BOOTSTRAP

SPECIAL

TEST

Figure 2-6. Memory Map for MC68HC811E2

Addr.

$1000

$1001

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

(PORTA) Write:

Port A Data Register

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

See page 110.

Reset:

I

0

I

Reserved

R

Read:

Parallel I/O Control Register

STAF

0

STAI

0

CWOM

0

HNDS

0

OIN

0

PLS

U

EGA

1

INVB

1

$1002

$1003

$1004

(PIOC) Write:

See page 115.

Reset:

Read:

Port C Data Register

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

(PORTC) Write:

See page 111.

Reset:

Read:

Indeterminate after reset

Port B Data Register

PB7

0

PB6

0

PB5

0

PB4

PB3

PB2

0

PB1

0

PB0

0

(PORTB) Write:

See page 111.

Reset:

0

= Unimplemented

I = Indeterminate after reset

R

= Reserved

U = Unaffected

Figure 2-7. Register and Control Bit Assignments (Sheet 1 of 6)

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Memory Map

Addr.

$1005

$1006

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Port C Latched Register

PCL7

PCL6

PCL5

PCL4

PCL3

PCL2

PCL1

PCL0

(PORTCL) Write:

See page 112.

Reset:

Indeterminate after reset

Reserved

R

Read:

Port C Data Direction Register

DDRC7 DDRC6

DDRC5

DDRC4

DDRC3

DDRC2

DDRC1 DDRC0

$1007

$1008

$1009

$100A

$100B

$100C

$100D

$100E

$100F

$1010

$1011

(DDRC) Write:

See page 112.

Reset:

Read:

0

PD5

I

0

PD4

I

0

PD3

I

0

PD2

I

0

PD1

I

0

PD0

I

Port D Data Register

(PORTD) Write:

See page 112.

Reset:

Read:

U

Port D Data Direction Register

DDRD5

0

DDRD4

0

DDRD3

0

DDRD2

0

DDRD1 DDRD0

(DDRD) Write:

See page 113.

Reset:

Read:

0

Port E Data Register

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

(PORTE) Write:

See page 113.

Reset:

Read:

Indeterminate after reset

Timer Compare Force Register

FOC1

0

FOC2

0

FOC3

0

FOC4

0

FOC5

0

(CFORC) Write:

See page 151.

Reset:

Read:

0

Output Compare 1 Mask Register

OC1M7 OC1M6

OC1M5

0

OC1M4

0

OC1M3

0

(OC1M) Write:

See page 152.

Reset:

Read:

0

Output Compare 1 Data Register

OC1D7 OC1D6

OC1D5

OC1D4

OC1D3

(OC1D) Write:

See page 152.

Reset:

Read: Bit 15

(TCNTH) Write:

0

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Timer Counter Register High

See page 153.

Reset:

0

Read: Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Timer Counter Register Low

(TCNTL) Write:

See page 153.

Reset:

Read:

0

Timer Input Capture 1 Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

High (TIC1H) Write:

See page 147.

Reset:

Indeterminate after reset

Bit 4 Bit 3

Read:

Timer Input Capture 1 Register

Bit 7

Bit 6

Bit 5

Bit 2

Bit 1

Bit 0

Low (TIC1L) Write:

See page 147.

Reset:

Indeterminate after reset

= Reserved

= Unimplemented

I = Indeterminate after reset

R

U = Unaffected

Figure 2-7. Register and Control Bit Assignments (Sheet 2 of 6)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

39

Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Timer Input Capture 2 Register

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

$1012

High (TIC2H) Write:

See page 147.

Reset:

Indeterminate after reset

Bit 4 Bit 3

Indeterminate after reset

Bit 12 Bit 11

Indeterminate after reset

Bit 4 Bit 3

Indeterminate after reset

Read:

TImer Input Capture 2 Register

Bit 7

Bit 15

Bit 7

Bit 6

Bit 14

Bit 6

Bit 5

Bit 13

Bit 5

Bit 2

Bit 10

Bit 2

Bit 1

Bit 9

Bit 1

Bit 0

Bit 8

Bit 0

$1013

$1014

$1015

$1016

$1017

$1018

$1019

$101A

$101B

$101C

$101D

Low (TIC2L) Write:

See page 147.

Reset:

Read:

Timer Input Capture 3 Register

High (TIC3H) Write:

See page 147.

Reset:

Read:

Timer Input Capture 3 Register

Low (TIC3L) Write:

See page 147.

Reset:

Read:

Timer Output Compare 1 Register

Bit 15

1

Bit 14

1

Bit 13

1

Bit 12

1

Bit 11

1

Bit 10

1

Bit 9

1

Bit 8

1

High (TOC1H) Write:

See page 149.

Reset:

Read:

Timer Output Compare 1 Register

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

Low (TOC1L) Write:

See page 149.

Reset:

Read:

Timer Output Compare 2 Register

Bit 15

1

Bit 14

1

Bit 13

1

Bit 12

1

Bit 11

1

Bit 10

1

Bit 9

1

Bit 8

1

High (TOC2H) Write:

See page 150.

Reset:

Read:

Timer Output Compare 2 Register

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

Low (TOC2L) Write:

See page 150.

Reset:

Read:

Timer Output Compare 3 Register

Bit 15

1

Bit 14

1

Bit 13

1

Bit 12

1

Bit 11

1

Bit 10

1

Bit 9

1

Bit 8

1

High (TOC3H) Write:

See page 150.

Reset:

Read:

Timer Output Compare 3 Register

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

Low (TOC3L) Write:

See page 150.

Reset:

Read:

Timer Output Compare 4 Register

Bit 15

1

Bit 14

1

Bit 13

1

Bit 12

1

Bit 11

1

Bit 10

1

Bit 9

1

Bit 8

1

High (TOC4H) Write:

See page 150.

Reset:

Read:

Timer Output Compare 4 Register

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

Bit 3

Bit 2

1

Bit 1

1

Bit 0

1

Low (TOC4L) Write:

See page 150.

Reset:

1

= Unimplemented

I = Indeterminate after reset

R

= Reserved

U = Unaffected

Figure 2-7. Register and Control Bit Assignments (Sheet 3 of 6)

Data Sheet

40

M68HC11E Family — Rev. 5

MOTOROLA

Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

Memory Map

Addr.

Register Name

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 0

Bit 8

1

Read:

Timer Input Capture 4/Output

Compare 5 Register High Write:

Bit 9

1

$101E

(TI4/O5) See page 148.

Reset:

Read:

Timer Input Capture 4/Output

Compare 5 Register Low Write:

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

$101F

$1020

$1021

$1022

$1023

$1024

$1025

$1026

$1027

$1028

$1029

(TI4/O5) See page 148.

Reset:

Read:

Timer Control Register 1

OM2

0

OL2

0

OM3

0

OL3

0

OM4

0

OL4

0

OM5

0

OL5

0

(TCTL1) Write:

See page 153.

Reset:

Read:

Timer Control Register 2

EDG4B EDG4A

EDG1B

0

EDG1A

0

EDG2B

0

EDG2A

0

EDG3B EDG3A

(TCTL2) Write:

See page 146.

Reset:

0

OC1I

0

OC2I

0

IC2I

0

IC3I

0

Read:

Timer Interrupt Mask 1 Register

OC3I

0

OC4I

0

I4/O5I

0

IC1I

0

(TMSK1) Write:

See page 154.

Reset:

Read:

Timer Interrupt Flag 1

OC1F

0

OC2F

0

OC3F

0

OC4F

0

I4/O5F

0

IC1F

0

IC2F

0

IC3F

0

(TFLG1) Write:

See page 154.

Reset:

Read:

Timer Interrupt Mask 2 Register

TOI

0

RTII

0

PAOVI

0

PAII

0

PR1

0

PR0

0

(TMSK2) Write:

See page 155.

Reset:

0

Read:

Timer Interrupt Flag 2

TOF

0

RTIF

0

PAOVF

0

PAIF

0

(TFLG2) Write:

See page 158.

Reset:

0

DDRA3

0

Read:

Pulse Accumulator Control

DDRA7

0

PAEN

0

PAMOD

0

PEDGE

0

I4/O5

0

RTR1

0

RTR0

0

Register (PACTL) Write:

See page 159.

Reset:

Read:

Pulse Accumulator Count

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register (PACNT) Write:

See page 162.

Reset:

Indeterminate after reset

Read:

Serial Peripheral Control Register

SPIE

0

SPE

DWOM

0

MSTR

0

CPOL

0

CPHA

1

SPR1

U

SPR0

U

(SPCR) Write:

See page 138.

Reset:

0

WCOL

0

Read:

Serial Peripheral Status Register

SPIF

0

MODF

(SPSR) Write:

See page 139.

Reset:

0

= Unimplemented

I = Indeterminate after reset

R

= Reserved

U = Unaffected

Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

41

Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

Addr.

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Serial Peripheral Data I/O

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$102A

Register (SPDR) Write:

See page 140.

Reset:

Indeterminate after reset

Read:

Baud Rate Register

TCLR

SCP2⁽¹⁾

SCP1

0

SCP0

RCKB

SCR2

U

SCR1

U

SCR0

U

$102B

$102C

$102D

$102E

(BAUD) Write:

See page 126.

Reset:

0

R8

I

0

T8

I

0

M

0

WAKE

0

Read:

Serial Communications Control

Register 1 (SCCR1) Write:

See page 123.

Reset:

0

RIE

0

RE

0

RWU

0

SBK

0

Read:

Serial Communications Control

TIE

0

TCIE

0

ILIE

0

TE

0

Register 2 (SCCR2) Write:

See page 124.

Reset:

Read:

Serial Communications Status

TDRE

1

TC

1

RDRF

0

IDLE

0

OR

0

NF

0

FE

0

Register (SCSR) Write:

See page 125.

Reset:

0

1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.

Read:

Serial Communications Data

R7/T7

R6/T6

R5/T5

R4/T4

R3/T3

R2/T2

CC

R1/T1

R0/T0

$102F

$1030

$1031

$1032

$1033

$1034

$1035

Register (SCDR) Write:

See page 122.

Reset:

Indeterminate after reset

Read: CCF

Register (ADCTL) Write:

See page 69.

Analog-to-Digital Control Status

SCAN

MULT

CD

CB

CA

Reset:

0

Indeterminate after reset

Read: Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Analog-to-Digital Results

Register 1 (ADR1) Write:

See page 71.

Reset:

Indeterminate after reset

Bit 4 Bit 3

Read: Bit 7

Bit 6

Bit 5

Bit 1

Bit 0

Analog-to-Digital Results

Register 2 (ADR2) Write:

See page 71.

Reset:

Indeterminate after reset

Bit 4 Bit 3

Read: Bit 7

Analog-to-Digital Results

Register 3 (ADR3) Write:

See page 71.

Reset:

Indeterminate after reset

Bit 4 Bit 3

Read: Bit 7

Analog-to-Digital Results

Register 4 (ADR4) Write:

See page 71.

Reset:

Read:

Indeterminate after reset

Block Protect Register

PTCON

BPRT3

BPRT2

1

BPRT1

1

BPRT0

1

(BPROT) Write:

See page 58.

Reset:

0

1

= Unimplemented

I = Indeterminate after reset

R

= Reserved

U = Unaffected

Figure 2-7. Register and Control Bit Assignments (Sheet 5 of 6)

Data Sheet

42

M68HC11E Family — Rev. 5

MOTOROLA

Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

Memory Map

Addr.

$1036

$1037

Register Name

Bit 7

6

5

4

3

2

1

Bit 0

Read:

EPROM Programming Control

MBE

ELAT

EXCOL

EXROW

T1

T0

PGM

Register (EPROG)⁽¹⁾Write:

See page 59.

Reset:

0

Reserved

R

1. MC68HC711E20 only

$1038

Reserved

R

Read:

System Configuration Options

ADPU

CSEL

0

IRQE⁽¹⁾

DLY⁽¹⁾

CME

0

CR1⁽¹⁾

0

CR0⁽¹⁾

0

$1039

$103A

$103B

Register (OPTION) Write:

See page 51.

Reset:

0

Bit 7

0

Bit 5

0

1

Bit 4

0

Bit 2

0

Read:

Arm/Reset COP Timer Circuitry

Bit 6

0

Bit 3

0

Bit 1

0

Bit 0

0

Register (COPRST) Write:

See page 91.

Reset:

Read:

EPROM and EEPROM

Programming Control Register Write:

ODD

0

EVEN

0

ELAT⁽²⁾

0

BYTE

0

ROW

0

ERASE

0

EELAT

0

EPGM

0

(PPROG) See page 54.

Reset:

Read:

Highest Priority I Bit Interrupt and

$103C Miscellaneous Register (HPRIO) Write:

RBOOT

0

SMOD

0

MDA

0

IRV(NE)

0

PSEL3

0

PSEL2

1

PSEL1

1

PSEL0

0

See page 46.

Reset:

Read:

RAM and I/O Mapping Register

RAM3

RAM2

RAM1

RAM0

REG3

REG2

REG1

REG0

$103D

$103E

(INIT) Write:

See page 50.

Reset:

0

1

Reserved

R

Read:

System Configuration Register

NOSEC

NOCOP ROMON

EEON

U

$103F

(CONFIG) Write:

See page 48.

Reset:

0

EE3

1

0

EE2

1

0

EE1

1

0

EE0

1

U

NOSEC

U

NOCOP

U

1

Read:

System Configuration Register

EEON

1

(CONFIG)⁽³⁾Write:

See page 48.

Reset:

1

1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.

2. MC68HC711E9 only

3. MC68HC811E2 only

= Unimplemented

R

= Reserved

U = Unaffected

I = Indeterminate after reset

Figure 2-7. Register and Control Bit Assignments (Sheet 6 of 6)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Operating Modes and On-Chip Memory

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Operating Modes and On-Chip Memory

2.3.1 RAM and Input/Output Mapping

Hardware priority is built into RAM and I/O mapping. Registers have priority over

RAM and RAM has priority over ROM. When a lower priority resource is mapped

at the same location as a higher priority resource, a read/write of a location results

in a read/write of the higher priority resource only. For example, if both the register

block and the RAM are mapped to the same location, only the register block will be

accessed. If RAM and ROM are located at the same position, RAM has priority.

The fully static RAM can be used to store instructions, variables, and temporary

data. The direct addressing mode can access RAM locations using a 1-byte

address operand, saving program memory space and execution time, depending

on the application.

RAM contents can be preserved during periods of processor inactivity by two

methods, both of which reduce power consumption. They are:

1. In the software-based stop mode, the clocks are stopped while V_DDpowers

the MCU. Because power supply current is directly related to operating

frequency in CMOS integrated circuits, only a very small amount of leakage

exists when the clocks are stopped.

2. In the second method, the MODB/V_STBYpin can supply RAM power from a

battery backup or from a second power supply. Figure 2-8 shows a typical

standby voltage circuit for a standard 5-volt device. Adjustments to the

circuit must be made for devices that operate at lower voltages. Using the

MODB/V_STBYpin may require external hardware, but can be justified when

a significant amount of external circuitry is operating from V_DD. If V_STBYis

used to maintain RAM contents, reset must be held low whenever V_DDis

below normal operating level. Refer to Section 5. Resets and Interrupts.

V_DD

MAX

690

V_DD

4.7 k

TO MODB/V_STBY

V_OUT

OF M68HC11

V_BATT

4.8-V

NiCd

+

Figure 2-8. RAM Standby MODB/V_STBYConnections

The bootloader program is contained in the internal bootstrap ROM. This ROM,

which appears as internal memory space at locations $BF00–$BFFF, is enabled

only if the MCU is reset in special bootstrap mode.

Data Sheet

44

M68HC11E Family — Rev. 5

Operating Modes and On-Chip Memory

MOTOROLA

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Operating Modes and On-Chip Memory

Memory Map

In expanded modes, the ROM/EPROM/OTPROM (if present) is enabled out of

reset and located at the top of the memory map if the ROMON bit in the CONFIG

register is set. ROM or EPROM is enabled out of reset in single-chip and bootstrap

modes, regardless of the state of ROMON.

For devices with 512 bytes of EEPROM, the EEPROM is located at $B600–$B7FF

and has the same read cycle time as the internal ROM. The 512 bytes of EEPROM

cannot be remapped to other locations.

For the MC68HC811E2, EEPROM is located at $F800–$FFFF and can be

remapped to any 4-Kbyte boundary. EEPROM mapping control bits (EE[3:0] in

CONFIG) determine the location of the 2048 bytes of EEPROM and are present

only on the MC68HC811E2. Refer to 2.3.3.1 System Configuration Register for

a description of the MC68HC811E2 CONFIG register.

EEPROM can be programmed or erased by software and an on-chip charge pump,

allowing EEPROM changes using the single V_DDsupply.

2.3.2 Mode Selection

The four mode variations are selected by the logic states of the MODA and MODB

pins during reset. The MODA and MODB logic levels determine the logic state of

SMOD and the MDA control bits in the highest priority I-bit interrupt and

miscellaneous (HPRIO) register.

After reset is released, the mode select pins no longer influence the MCU operating

mode. In single-chip operating mode, the MODA pin is connected to a logic level 0.

In expanded mode, MODA is normally connected to V_DDthrough a pullup resistor

of 4.7 kΩ. The MODA pin also functions as the load instruction register LIR pin

when the MCU is not in reset. The open-drain active low LIR output pin drives low

during the first E cycle of each instruction. The MODB pin also functions as standby

power input (V_STBY), which allows RAM contents to be maintained in absence of

V_DD

.

Refer to Table 2-1, which is a summary of mode pin operation, the mode control

bits, and the four operating modes.

Table 2-1. Hardware Mode Select Summary

Input Levels

at Reset

Control Bits in HPRIO

(Latched at Reset)

Mode

MODB

MODA

RBOOT

SMOD

MDA

1

0

1

0

1

Single chip

Expanded

Bootstrap

0

1

0

1

0

1

0

1

Special test

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Operating Modes and On-Chip Memory

A normal mode is selected when MODB is logic 1 during reset. One of three reset

vectors is fetched from address $FFFA–$FFFF, and program execution begins

from the address indicated by this vector. If MODB is logic 0 during reset, the

special mode reset vector is fetched from addresses $BFFA–$BFFF, and software

has access to special test features. Refer to Section 5. Resets and Interrupts.

Address:

$103C

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

RBOOT⁽¹⁾SMOD⁽¹⁾

MDA⁽¹⁾

IRV(NE)⁽¹⁾

PSEL3

PSEL2

PSEL1

PSEL0

Resets:

Single chip:

Expanded:

Bootstrap:

Test:

0

1

0

1

0

1

0

1

0

1

0

1

0

1. The reset values depend on the mode selected at the RESET pin rising edge.

Figure 2-9. Highest Priority I-Bit Interrupt and Miscellaneous

Register (HPRIO)

RBOOT — Read Bootstrap ROM Bit

Valid only when SMOD is set (bootstrap or special test mode); can be written

only in special modes

0 = Bootloader ROM disabled and not in map

1 = Bootloader ROM enabled and in map at $BE00–$BFFF

SMOD and MDA — Special Mode Select and Mode Select A Bits

The initial value of SMOD is the inverse of the logic level present on the MODB

pin at the rising edge of reset. The initial value of MDA equals the logic level

present on the MODA pin at the rising edge of reset. These two bits can be read

at any time. They can be written anytime in special modes. MDA can be written

only once in normal modes. SMOD cannot be set once it has been cleared.

Input

Latched at Reset

Mode

MODB

MODA

SMOD

MDA

1

0

1

0

1

Single chip

Expanded

Bootstrap

0

1

0

1

0

1

Special test

Data Sheet

46

M68HC11E Family — Rev. 5

MOTOROLA

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Operating Modes and On-Chip Memory

Memory Map

IRV(NE) — Internal Read Visibility (Not E) Bit

IRVNE can be written once in any mode. In expanded modes, IRVNE

determines whether IRV is on or off. In special test mode, IRVNE is reset to 1.

In all other modes, IRVNE is reset to 0. For the MC68HC811E2, this bit is IRV

and only controls the internal read visibility function.

0 = No internal read visibility on external bus

1 = Data from internal reads is driven out the external data bus.

In single-chip modes this bit determines whether the E clock drives out from the

chip. For the MC68HC811E2, this bit has no meaning or effect in single-chip and

bootstrap modes.

0 = E is driven out from the chip.

1 = E pin is driven low. Refer to the following table.

IRVNE Out

of Reset

E Clock Out

of Reset

IRV Out

of Reset

IRVNE

Affects Only

IRVNE Can

Be Written

Mode

Single chip

Expanded

Bootstrap

0

1

On

Off

On

E

Once

IRV

E

Special test

IRV

PSEL[3:0] — Priority Select Bits

Refer to Section 5. Resets and Interrupts.

2.3.3 System Initialization

Registers and bits that control initialization and the basic operation of the MCU are

protected against writes except under special circumstances. Table 2-2 lists

registers that can be written only once after reset or that must be written within the

first 64 cycles after reset.

Table 2-2. Write Access Limited Registers

Operating Register

Must be Written

in First 64 Cycles

Write

Anytime

Register Name

Mode

Address

SMOD = 0

$x024 Timer interrupt mask 2 (TMSK2)

$x035 Block protect register (BPROT)

$x039 System configuration options (OPTION)

Bits [1:0], once only

Clear bits, once only

Bits [5:4], bits [2:0], once only Bits [7:6], bit 3

Bits [7:2]

Set bits only

Highest priority I-bit interrupt

$x03C

See HPRIO description

and miscellaneous (HPRIO)

$x03D RAM and I/O map register (INIT)

$x024 Timer interrupt mask 2 (TMSK2)

$x035 Block protect register (BPROT)

$x039 System configuration options (OPTION)

Yes, once only

—

All, set or clear

SMOD = 1

—

Highest priority I-bit interrupt and

$x03C

See HPRIO description

—

See HPRIO description

All, set or clear

miscellaneous (HPRIO)

$x03D RAM and I/O map register (INIT)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Operating Modes and On-Chip Memory

2.3.3.1 System Configuration Register

The system configuration register (CONFIG) consists of an EEPROM byte and

static latches that control the startup configuration of the MCU. The contents of the

EEPROM byte are transferred into static working latches during reset sequences.

The operation of the MCU is controlled directly by these latches and not by

CONFIG itself. In normal modes, changes to CONFIG do not affect operation of the

MCU until after the next reset sequence. When programming, the CONFIG register

itself is accessed. When the CONFIG register is read, the static latches are

accessed. See 2.5.1 EEPROM and CONFIG Programming and Erasure for

information on modifying CONFIG.

To take full advantage of the MCU’s functionality, customers can program the

CONFIG register in bootstrap mode. This can be accomplished by setting the

mode pins to logic 0 and downloading a small program to internal RAM. For more

information, Motorola application note AN1060 entitled M68HC11 Bootstrap

Mode has been included at the back of this document. The downloadable talker

will consist of:

•

Bulk erase

Byte programming

Communication server

All of this functionality is provided by PCbug11 which can be found on the Motorola

Web site at http://www.motorola.com/semiconductors/. For more information

on using PCbug11 to program an E-series device, Motorola engineering bulletin

EB296 entitled Programming MC68HC711E9 Devices with PCbug11 and the

M68HC11EVBU has been included at the back of this document.

NOTE:

The CONFIG register on the 68HC11 is an EEPROM cell and must be

programmed accordingly.

Operation of the CONFIG register in the MC68HC811E2 differs from other devices

in the M68HC11 E series. See Figure 2-10 and Figure 2-11.

Address: $103F

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

NOSEC

NOCOP

ROMON

EEON

Resets:

Single chip:

Bootstrap:

Expanded:

Test:

0

U

1

U

1

U

U(L)

U

1

U(L)

= Unimplemented

U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,

but the function of COP is controlled by the DISR bit in TEST1 register.

Figure 2-10. System Configuration Register (CONFIG)

Data Sheet

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Memory Map

Address:

$103F

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

EE3

EE2

EE1

EE0

NOSEC

NOCOP

EEON

Resets:

Single chip:

Bootstrap:

Expanded:

Test:

1

U

1

U

1

U(L)

U

0

1

U(L)

= Unimplemented

U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset,

but the function of COP is controlled by the DISR bit in TEST1 register.

Figure 2-11. MC68HC811E2 System Configuration Register (CONFIG)

EE[3:0] — EEPROM Mapping Bits

EE[3:0] apply only to MC68HC811E2 and allow the 2048 bytes of EEPROM to

be remapped to any 4-Kbyte boundary. See Table 2-3.

Table 2-3. EEPROM Mapping

EE[3:0]

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

EEPROM Location

$0800–$0FFF

$1800–$1FFF

$2800–$2FFF

$3800–$3FFF

$4800–$4FFF

$5800–$5FFF

$6800–$6FFF

$7800–$7FFF

$8800–$8FFF

$9800–$9FFF

$A800–$AFFF

$B800–$BFFF

$C800–$CFFF

$D800–$DFFF

$E800–$EFFF

$F800–$FFFF

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NOSEC — Security Disable Bit

NOSEC is invalid unless the security mask option is specified before the MCU

is manufactured. If the security mask option is omitted NOSEC always reads 1.

The enhanced security feature is available in the MC68S711E9 MCU. The

enhancement to the standard security feature protects the EPROM as well as

RAM and EEPROM.

0 = Security enabled

1 = Security disabled

NOCOP — COP System Disable Bit

Refer to Section 5. Resets and Interrupts.

1 = COP disabled

0 = COP enabled

ROMON — ROM/EPROM/OTPROM Enable Bit

When this bit is 0, the ROM or EPROM is disabled and that memory space

becomes externally addressed. In single-chip mode, ROMON is forced to 1 to

enable ROM/EPROM regardless of the state of the ROMON bit.

0 = ROM disabled from the memory map

1 = ROM present in the memory map

EEON — EEPROM Enable Bit

When this bit is 0, the EEPROM is disabled and that memory space becomes

externally addressed.

0 = EEPROM removed from the memory map

1 = EEPROM present in the memory map

2.3.3.2 RAM and I/O Mapping Register

The internal registers used to control the operation of the MCU can be relocated

on 4-Kbyte boundaries within the memory space with the use of the RAM and I/O

mapping register (INIT). This 8-bit special-purpose register can change the default

locations of the RAM and control registers within the MCU memory map. It can be

written only once within the first 64 E-clock cycles after a reset in normal modes,

and then it becomes a read-only register.

Address: $103D

Bit 7

RAM3

0

6

RAM2

0

5

RAM1

0

4

RAM0

0

3

REG3

0

2

REG2

0

1

REG1

0

Bit 0

REG0

1

Read:

Write:

Reset:

Figure 2-12. RAM and I/O Mapping Register (INIT)

RAM[3:0] — RAM Map Position Bits

These four bits, which specify the upper hexadecimal digit of the RAM address,

control position of RAM in the memory map. RAM can be positioned at the

beginning of any 4-Kbyte page in the memory map. It is initialized to address

$0000 out of reset. Refer to Table 2-4.

Data Sheet

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Memory Map

REG[3:0] — 64-Byte Register Block Position

These four bits specify the upper hexadecimal digit of the address for the

64-byte block of internal registers. The register block, positioned at the

beginning of any 4-Kbyte page in the memory map, is initialized to address

$1000 out of reset. Refer to Table 2-5.

Table 2-4. RAM Mapping

Table 2-5. Register Mapping

RAM[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Address

REG[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Address

$0000–$0xFF

$1000–$1xFF

$2000–$2xFF

$3000–$3xFF

$4000–$4xFF

$5000–$5xFF

$6000–$6xFF

$7000–$7xFF

$8000–$8xFF

$9000–$9xFF

$A000–$AxFF

$B000–$BxFF

$C000–$CxFF

$D000–$DxFF

$E000–$ExFF

$F000–$FxFF

$0000–$003F

$1000–$103F

$2000–$203F

$3000–$303F

$4000–$403F

$5000–$503F

$6000–$603F

$7000–$703F

$8000–$803F

$9000–$903F

$A000–$A03F

$B000–$B03F

$C000–$C03F

$D000–$D03F

$E000–$E03F

$F000–$F03F

2.3.3.3 System Configuration Options Register

The 8-bit, special-purpose system configuration options register (OPTION) sets

internal system configuration options during initialization. The time protected

control bits, IRQE, DLY, and CR[1:0], can be written only once after a reset and

then they become read-only. This minimizes the possibility of any accidental

changes to the system configuration.

Address: $1039

Bit 7

ADPU

0

6

CSEL

0

5

IRQE⁽¹⁾

0

4

DLY⁽¹⁾

1

3

CME

0

2

1

CR1⁽¹⁾

0

Bit 0

CR0⁽¹⁾

0

Read:

Write:

Reset:

0

1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during

special modes.

= Unimplemented

Figure 2-13. System Configuration Options Register (OPTION)

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ADPU — Analog-to-Digital Converter Power-Up Bit

Refer to Section 3. Analog-to-Digital (A/D) Converter.

CSEL — Clock Select Bit

Selects alternate clock source for on-chip EEPROM charge pump. Refer to

2.5.1 EEPROM and CONFIG Programming and Erasure for more information

on EEPROM use.

CSEL also selects the clock source for the A/D converter, a function discussed

in Section 3. Analog-to-Digital (A/D) Converter.

IRQE — Configure IRQ for Edge-Sensitive Only Operation Bit

Refer to Section 5. Resets and Interrupts.

DLY — Enable Oscillator Startup Delay Bit

0 = The oscillator startup delay coming out of stop mode is bypassed and the

MCU resumes processing within about four bus cycles.

1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is

started up from the stop power-saving mode. This delay allows the

crystal oscillator to stabilize.

CME — Clock Monitor Enable Bit

Refer to Section 5. Resets and Interrupts.

Bit 2 — Not implemented

Always reads 0

CR[1:0] — COP Timer Rate Select Bits

The internal E clock is divided by 2¹⁵before it enters the COP watchdog system.

These control bits determine a scaling factor for the watchdog timer. Refer to

Section 5. Resets and Interrupts.

2.4 EPROM/OTPROM

Certain devices in the M68HC11 E series include on-chip EPROM/OTPROM. For

instance:

•

The MC68HC711E9 devices contain 12 Kbytes of on-chip EPROM

(OTPROM in non-windowed package).

The MC68HC711E20 has 20 Kbytes of EPROM (OTPROM in

non-windowed package).

The MC68HC711E32 has 32 Kbytes of EPROM (OTPROM in

non-windowed package).

Standard MC68HC71E9 and MC68HC711E20 devices are shipped with the

EPROM/OTPROM contents erased (all 1s). The programming operation programs

zeros. Windowed devices must be erased using a suitable ultraviolet light source

before reprogramming. Depending on the light source, erasing can take from 15 to

45 minutes.

Data Sheet

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EPROM/OTPROM

Using the on-chip EPROM/OTPROM programming feature requires an external

12-volt nominal power supply (V_PPE). Normal programming is accomplished using

the EPROM/OTPROM programming register (PPROG).

PPROG is the combined EPROM/OTPROM and EEPROM programming register

on all devices with EPROM/OTPROM except the MC68HC711E20. For the

MC68HC711E20, there is a separate register for EPROM/OTPROM programming

called the EPROG register.

As described in the following subsections, these two methods of programming and

verifying EPROM are possible:

1. Programming an individual EPROM address

2. Programming the EPROM with downloaded data

2.4.1 Programming an Individual EPROM Address

In this method, the MCU programs its own EPROM by controlling the PPROG

register (EPROG in MC68HC711E20). Use these procedures to program the

EPROM through the MCU with:

•

The ROMON bit set in the CONFIG register

The 12-volt nominal programming voltage present on the XIRQ/V_PPEpin

The IRQ pin must be pulled high.

NOTE:

Any operating mode can be used.

This example applies to all devices with EPROM/OTPROM except for the

MC68HC711E20.

EPROG

LDAB

STAB

#$20

$103B Set ELAT bit in (EPGM = 0) to enable

EPROM latches.

STAA

LDAB

STAB

$0,X

#$21

Store data to EPROM address

$103B Set EPGM bit with ELAT = 1 to enable

EPROM programming voltage

JSR

CLR

DLYEP Delay 2–4 ms

$103B Turn off programming voltage and set

to READ mode

This example applies only to MC68HC711E20.

EPROG

LDAB

STAB

#$20

$1036 Set ELAT bit (EPGM = 0) to enable

EPROM latches.

STAA

LDAB

STAB

$0,X

#$21

Store data to EPROM address

$1036 Set EPGM bit with ELAT = 1 to enable

EPROM programming voltage

JSR

CLR

DLYEP Delay 2–4 ms

$1036 Turn off programming voltage and set

to READ mode

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2.4.2 Programming the EPROM with Downloaded Data

When using this method, the EPROM is programmed by software while in the

special test or bootstrap modes. User-developed software can be uploaded

through the SCI or a ROM-resident EPROM programming utility can be used. The

12-volt nominal programming voltage must be present on the XIRQ/V_PPEpin. To

use the resident utility, bootload a 3-byte program consisting of a single jump

instruction to $BF00. $BF00 is the starting address of a resident EPROM

programming utility. The utility program sets the X and Y index registers to default

values, then receives programming data from an external host, and puts it in

EPROM. The value in IX determines programming delay time. The value in IY is a

pointer to the first address in EPROM to be programmed (default = $D000).

When the utility program is ready to receive programming data, it sends the host

the $FF character. Then it waits. When the host sees the $FF character, the

EPROM programming data is sent, starting with the first location in the EPROM

array. After the last byte to be programmed is sent and the corresponding

verification data is returned, the programming operation is terminated by resetting

the MCU.

For more information, Motorola application note AN1060 entitled M68HC11

Bootstrap Mode has been included at the back of this document.

2.4.3 EPROM and EEPROM Programming Control Register

The EPROM and EEPROM programming control register (PPROG) enables the

EPROM programming voltage and controls the latching of data to be programmed.

•

For MC68HC711E9, PPROG is also the EEPROM programming control

register.

•

For the MC68HC711E20, EPROM programming is controlled by the

EPROG register and EEPROM programming is controlled by the PPROG

register.

Address: $103B

Bit 7

ODD

0

6

EVEN

0

5

ELAT⁽¹⁾

0

4

BYTE

0

3

ROW

0

2

ERASE

0

1

EELAT

0

Bit 0

EPGM

0

Read:

Write:

Reset:

1. MC68HC711E9 only

Figure 2-14. EPROM and EEPROM Programming

Control Register (PPROG)

ODD — Program Odd Rows in Half of EEPROM (Test) Bit

Refer to 2.5 EEPROM.

EVEN — Program Even Rows in Half of EEPROM (Test) Bit

Refer to 2.5 EEPROM.

Data Sheet

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EPROM/OTPROM

ELAT — EPROM/OTPROM Latch Control Bit

When ELAT = 1, writes to EPROM cause address and data to be latched and

the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can

be written any time except when EPGM = 1; then the write to ELAT is disabled.

0 = EPROM address and data bus configured for normal reads

1 = EPROM address and data bus configured for programming

For the MC68HC711E9:

a. EPGM enables the high voltage necessary for both EEPROM and

EPROM/OTPROM programming.

b. ELAT and EELAT are mutually exclusive and cannot both equal 1.

BYTE — Byte/Other EEPROM Erase Mode Bit

Refer to 2.5 EEPROM.

ROW — Row/All EEPROM Erase Mode Bit

Refer to 2.5 EEPROM.

ERASE — Erase Mode Select Bit

Refer to 2.5 EEPROM.

EELAT — EEPROM Latch Control Bit

Refer to 2.5 EEPROM.

EPGM —EPROM/OTPROM/EEPROM Programming Voltage Enable Bit

EPGM can be read any time and can be written only when ELAT = 1 (for

EPROM/OTPROM programming) or when EELAT = 1 (for EEPROM

programming).

0 = Programming voltage to EPROM/OTPROM/EEPROM array

disconnected

1 = Programming voltage to EPROM/OTPROM/EEPROM array connected

Address: $1036

Bit 7

MBE

0

6

5

ELAT

0

4

EXCOL

0

3

EXROW

0

2

T1

0

1

T0

0

Bit 0

PGM

0

Read:

Write:

Reset:

0

= Unimplemented

Figure 2-15. MC68HC711E20 EPROM Programming

Control Register (EPROG)

MBE — Multiple-Byte Programming Enable Bit

When multiple-byte programming is enabled, address bit 5 is considered a don’t

care so that bytes with address bit 5 = 0 and address bit 5 = 1 both get

programmed. MBE can be read in any mode and always reads 0 in normal

modes. MBE can be written only in special modes.

0 = EPROM array configured for normal programming

1 = Program two bytes with the same data

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Bit 6 — Unimplemented

Always reads 0

ELAT — EPROM/OTPROM Latch Control Bit

When ELAT = 1, writes to EPROM cause address and data to be latched and

the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can

be written any time except when PGM = 1; then the write to ELAT is disabled.

0 = EPROM/OTPROM address and data bus configured for normal reads

1 = EPROM/OTPROM address and data bus configured for programming

EXCOL — Select Extra Columns Bit

0 = User array selected

1 = User array is disabled and extra columns are accessed at bits [7:0].

Addresses use bits [13:5] and bits [4:0] are don’t care. EXCOL can be

read and written only in special modes and always returns 0 in normal

modes.

EXROW — Select Extra Rows Bit

0 = User array selected

1 = User array is disabled and two extra rows are available. Addresses use

bits [7:0] and bits [13:8] are don’t care. EXROW can be read and written

only in special modes and always returns 0 in normal modes.

T[1:0] — EPROM Test Mode Select Bits

These bits allow selection of either gate stress or drain stress test modes. They

can be read and written only in special modes and always read 0 in normal

modes.

T1

0

T0

0

Function Selected

Normal mode

Reserved

0

1

0

Gate stress

1

Drain stress

PGM — EPROM Programming Voltage Enable Bit

PGM can be read any time and can be written only when ELAT = 1.

0 = Programming voltage to EPROM array disconnected

1 = Programming voltage to EPROM array connected

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EEPROM

2.5 EEPROM

Some E-series devices contain 512 bytes of on-chip EEPROM. The

MC68HC811E2 contains 2048 bytes of EEPROM with selectable base address. All

E-series devices contain the EEPROM-based CONFIG register.

2.5.1 EEPROM and CONFIG Programming and Erasure

The erased state of an EEPROM bit is 1. During a read operation, bit lines are

precharged to 1. The floating gate devices of programmed bits conduct and pull the

bit lines to 0. Unprogrammed bits remain at the precharged level and are read as

ones. Programming a bit to 1 causes no change. Programming a bit to 0 changes

the bit so that subsequent reads return 0.

When appropriate bits in the BPROT register are cleared, the PPROG register

controls programming and erasing the EEPROM. The PPROG register can be read

or written at any time, but logic enforces defined programming and erasing

sequences to prevent unintentional changes to EEPROM data. When the EELAT

bit in the PPROG register is cleared, the EEPROM can be read as if it were a ROM.

The on-chip charge pump that generates the EEPROM programming voltage from

V_DDuses MOS capacitors, which are relatively small in value. The efficiency of this

charge pump and its drive capability are affected by the level of V_DDand the

frequency of the driving clock. The load depends on the number of bits being

programmed or erased and capacitances in the EEPROM array.

The clock source driving the charge pump is software selectable. When the clock

select (CSEL) bit in the OPTION register is 0, the E clock is used; when CSEL is 1,

an on-chip resistor-capacitor (RC) oscillator is used.

The EEPROM programming voltage power supply voltage to the EEPROM array

is not enabled until there has been a write to PPROG with EELAT set and PGM

cleared. This must be followed by a write to a valid EEPROM location or to the

CONFIG address, and then a write to PPROG with both the EELAT and EPGM bits

set. Any attempt to set both EELAT and EPGM during the same write operation

results in neither bit being set.

2.5.1.1 Block Protect Register

This register prevents inadvertent writes to both the CONFIG register and

EEPROM. The active bits in this register are initialized to 1 out of reset and can be

cleared only during the first 64 E-clock cycles after reset in the normal modes.

When these bits are cleared, the associated EEPROM section and the CONFIG

register can be programmed or erased. EEPROM is only visible if the EEON bit in

the CONFIG register is set. The bits in the BPROT register can be written to 1 at

any time to protect EEPROM and the CONFIG register. In test or bootstrap modes,

write protection is inhibited and BPROT can be written repeatedly. Address ranges

for protected areas of EEPROM differ significantly for the MC68HC811E2. Refer to

Figure 2-16.

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Address: $1035

Bit 7

6

5

0

4

PTCON

1

3

BPRT3

1

2

BPRT2

1

BPRT1

1

Bit 0

BPRT0

1

Read:

Write:

Reset:

0

= Unimplemented

Figure 2-16. Block Protect Register (BPROT)

Bits [7:5] — Unimplemented

Always read 0

PTCON — Protect CONFIG Register Bit

0 = CONFIG register can be programmed or erased normally.

1 = CONFIG register cannot be programmed or erased.

BPRT[3:0] — Block Protect Bits for EEPROM

When set, these bits protect a block of EEPROM from being programmed or

electronically erased. Ultraviolet light, however, can erase the entire

EEPROM contents regardless of BPRT[3:0] (windowed packages only). Refer

to Table 2-6 and Table 2-7.

When cleared, BPRT[3:0] allow programming and erasure of the associated

block.

Table 2-6. EEPROM Block Protect

Bit Name

BPRT0

BPRT1

BPRT2

BPRT3

Block Protected

$B600–$B61F

$B620–$B65F

$B660–$B6DF

$B6E0–$B7FF

Block Size

32 bytes

64 bytes

128 bytes

288 bytes

Table 2-7. EEPROM Block Protect in MC68HC811E2 MCUs

Bit Name

BPRT0

BPRT1

BPRT2

BPRT3

Block Protected

$x800–$x9FF⁽¹⁾

$xA00–$xBFF⁽¹⁾

$xC00–$xDFF⁽¹⁾

$xE00–$xFFF⁽¹⁾

Block Size

512 bytes

1. x is determined by the value of EE[3:0] in CONFIG register. Refer to Figure 2-13.

2.5.1.2 EPROM and EEPROM Programming Control Register

The EPROM and EEPROM programming control register (PPROG) selects and

controls the EEPROM programming function. Bits in PPROG enable the

programming voltage, control the latching of data to be programmed, and select

the method of erasure (for example, byte, row, etc.).

Data Sheet

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EEPROM

Address: $103B

Bit 7

6

EVEN

0

5

ELAT⁽¹⁾

0

4

BYTE

0

3

ROW

0

2

ERASE

0

1

EELAT

0

Bit 0

EPGM

0

Read:

Write:

ODD

Reset:

0

1. MC68HC711E9 only

Figure 2-17. EPROM and EEPROM Programming

Control Register (PPROG)

ODD — Program Odd Rows in Half of EEPROM (Test) Bit

EVEN — Program Even Rows in Half of EEPROM (Test) Bit

ELAT — EPROM/OTPROM Latch Control Bit

For the MC68HC711E9, EPGM enables the high voltage necessary for both

EPROM/OTPROM and EEPROM programming.

For MC68HC711E9, ELAT and EELAT are mutually exclusive and cannot both

equal 1.

0 = EPROM address and data bus configured for normal reads

1 = EPROM address and data bus configured for programming

BYTE — Byte/Other EEPROM Erase Mode Bit

This bit overrides the ROW bit.

0 = Row or bulk erase

1 = Erase only one byte

ROW — Row/All EEPROM Erase Mode Bit

If BYTE is 1, ROW has no meaning.

0 = Bulk erase

1 = Row erase

Table 2-8. EEPROM Erase

BYTE

ROW

Action

Bulk erase (entire array)

Row erase (16 bytes)

Byte erase

0

1

0

1

0

1

Byte erase

ERASE — Erase Mode Select Bit

0 = Normal read or program mode

1 = Erase mode

EELAT — EEPROM Latch Control Bit

0 = EEPROM address and data bus configured for normal reads and cannot

be programmed

1 = EEPROM address and data bus configured for programming or erasing

and cannot be read

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EPGM — EPROM/OTPROM/EEPROM Programming Voltage Enable Bit

0 = Programming voltage to EEPROM array switched off

1 = Programming voltage to EEPROM array switched on

During EEPROM programming, the ROW and BYTE bits of PPROG are not used.

If the frequency of the E clock is 1 MHz or less, set the CSEL bit in the OPTION

register. Recall that 0s must be erased by a separate erase operation before

programming. The following examples of how to program an EEPROM byte

assume that the appropriate bits in BPROT are cleared.

PROG

LDAB

STAB

STAA

#$02

EELAT = 1

$103B Set EELAT bit

$XXXX Store data to EEPROM address

(for valid EEPROM address see memory

map for each device)

LDAB

STAB

JSR

#$03

EELAT = 1, EPGM = 1

$103B Turn on programming voltage

DLY10 Delay 10 ms

CLR

$103B Turn off high voltage and set

to READ mode

2.5.1.3 EEPROM Bulk Erase

This is an example of how to bulk erase the entire EEPROM. The CONFIG register

is not affected in this example.

BULKE

LDAB

STAB

STAA

#$06

EELAT = 1, ERASE = 1

$103B Set to BULK erase mode

$XXXX Store data to any EEPROM address (for

valid EEPROM address see memory map

for each device)

LDAB

STAB

JSR

#$07

EELAT = 1, EPGM = 1, ERASE = 1

$103B Turn on high voltage

DLY10 Delay 10 ms

CLR

$103B Turn off high voltage and set

to READ mode

2.5.1.4 EEPROM Row Erase

This example shows how to perform a fast erase of large sections of EEPROM.

ROWE

LDAB

STAB

LDAB

STAB

JSR

#$0E

ROW = 1, ERASE = 1, EELAT = 1

$103B Set to ROW erase mode

0,X

#$0F

Write any data to any address in ROW

ROW = 1, ERASE = 1, EELAT = 1, EPGM = 1

$103B Turn on high voltage

DLY10 Delay 10 ms

CLR

$103B Turn off high voltage and set

to READ mode

Data Sheet

60

M68HC11E Family — Rev. 5

MOTOROLA

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Operating Modes and On-Chip Memory

For further information, these engineering bulletins have been included at the back

of this data book:

•

EB183 — Enabling the Security Feature on the MC68HC711E9 Devices

with PCbug11 on the M68HC711E9PGMR

•

EB188 — Enabling the Security Feature on M68HC811E2 Devices with

PCbug11 on the M68HC711E9PGMR

Data Sheet

62

M68HC11E Family — Rev. 5

Operating Modes and On-Chip Memory

MOTOROLA

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Data Sheet — M68HC11E Family

Section 3. Analog-to-Digital (A/D) Converter

3.1 Introduction

3.2 Overview

The analog-to-digital (A/D) system, a successive approximation converter, uses an

all-capacitive charge redistribution technique to convert analog signals to digital

values.

The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The converter

does not require external sample and hold circuits because of the type of charge

redistribution technique used. A/D converter timing can be synchronized to the

system E clock or to an internal resistor capacitor (RC) oscillator.

The A/D converter system consists of four functional blocks: multiplexer, analog

converter, digital control, and result storage. Refer to Figure 3-1.

3.2.1 Multiplexer

The multiplexer selects one of 16 inputs for conversion. Input selection is controlled

by the value of bits CD:CA in the ADCTL register. The eight port E pins are

fixed-direction analog inputs to the multiplexer, and additional internal analog

signal lines are routed to it.

Port E pins also can be used as digital inputs. Digital reads of port E pins are not

recommended during the sample portion of an A/D conversion cycle, when the

gate signal to the N-channel input gate is on. Because no P-channel devices are

directly connected to either input pins or reference voltage pins, voltages above

V_DDdo not cause a latchup problem, although current should be limited according

to maximum ratings. Refer to Figure 3-2, which is a functional diagram of an

input pin.

M68HC11E Family — Rev. 5

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Data Sheet

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

PE0

AN0

V_RH

8-BIT CAPACITIVE DAC

WITH SAMPLE AND HOLD

V_Rl

PE1

AN1

PE2

AN2

SUCCESSIVE APPROXIMATION

REGISTER AND CONTROL

PE3

AN3

RESULT

ANALOG

MUX

PE4

AN4

PE5

AN5

INTERNAL

DATA BUS

PE6

AN6

PE7

AN7

ADCTL A/D CONTROL

RESULT REGISTER INTERFACE

ADR1 A/D RESULT 1

ADR2 A/D RESULT 2

ADR3 A/D RESULT 3

ADR4 A/D RESULT 4

Figure 3-1. A/D Converter Block Diagram

DIFFUSION/POLY

COUPLER

ANALOG

INPUT

*

~ 20 pF

+ ~20 V

– ~0.7 V

+ ~12V

– ~0.7V

ð 4 kΩ

< 2 pF

400 nA

JUNCTION

LEAKAGE

DAC

CAPACITANCE

DUMMY N-CHANNEL

OUTPUT DEVICE

INPUT

PROTECTION

DEVICE

V_RL

* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.

Figure 3-2. Electrical Model of an A/D Input Pin (Sample Mode)

Data Sheet

64

M68HC11E Family — Rev. 5

MOTOROLA

Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

Overview

3.2.2 Analog Converter

Conversion of an analog input selected by the multiplexer occurs in this block. It

contains a digital-to-analog capacitor (DAC) array, a comparator, and a successive

approximation register (SAR). Each conversion is a sequence of eight comparison

operations, beginning with the most significant bit (MSB). Each comparison

determines the value of a bit in the successive approximation register.

The DAC array performs two functions. It acts as a sample and hold circuit during

the entire conversion sequence and provides comparison voltage to the

comparator during each successive comparison.

The result of each successive comparison is stored in the SAR. When a conversion

sequence is complete, the contents of the SAR are transferred to the appropriate

result register.

A charge pump provides switching voltage to the gates of analog switches in the

multiplexer. Charge pump output must stabilize between 7 and 8 volts within up to

100 µs before the converter can be used. The charge pump is enabled by the

ADPU bit in the OPTION register.

3.2.3 Digital Control

All A/D converter operations are controlled by bits in register ADCTL. In addition to

selecting the analog input to be converted, ADCTL bits indicate conversion status

and control whether single or continuous conversions are performed. Finally, the

ADCTL bits determine whether conversions are performed on single or multiple

channels.

3.2.4 Result Registers

Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can

be accessed by the processor in the CPU. The conversion complete flag (CCF)

indicates when valid data is present in the result registers. The result registers are

written during a portion of the system clock cycle when reads do not occur, so there

is no conflict.

3.2.5 A/D Converter Clocks

The CSEL bit in the OPTION register selects whether the A/D converter uses the

system E clock or an internal RC oscillator for synchronization. When E-clock

frequency is below 750 kHz, charge leakage in the capacitor array can cause

errors, and the internal oscillator should be used. When the RC clock is used,

additional errors can occur because the comparator is sensitive to the additional

system clock noise.

M68HC11E Family — Rev. 5

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Data Sheet

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

3.2.6 Conversion Sequence

A/D converter operations are performed in sequences of four conversions each. A

conversion sequence can repeat continuously or stop after one iteration. The

conversion complete flag (CCF) is set after the fourth conversion in a sequence to

show the availability of data in the result registers. Figure 3-3 shows the timing of

a typical sequence. Synchronization is referenced to the system E clock.

E CLOCK

MSB

4

CYCLES

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

2

CYC CYC CYC CYC CYC CYC CYC END

2

CYC

2

12 E CYCLES

SAMPLE ANALOG INPUT

SUCCESSIVE APPROXIMATION SEQUENCE

CONVERT FIRST

CHANNEL, UPDATE

ADR1

CONVERT SECOND

CHANNEL, UPDATE

ADR2

CONVERT THIRD

CHANNEL, UPDATE

ADR3

CONVERT FOURTH

CHANNEL, UPDATE

ADR4

0

32

64

96

128 — E CYCLES

Figure 3-3. A/D Conversion Sequence

3.3 A/D Converter Power-Up and Clock Select

Bit 7 of the OPTION register controls A/D converter power-up. Clearing ADPU

removes power from and disables the A/D converter system. Setting ADPU

enables the A/D converter system. Stabilization of the analog bias voltages

requires a delay of as much as 100 µs after turning on the A/D converter. When the

A/D converter system is operating with the MCU E clock, all switching and

comparator operations are inherently synchronized to the main MCU clocks. This

allows the comparator output to be sampled at relatively quiet times during MCU

clock cycles. Since the internal RC oscillator is asynchronous to the MCU clock,

there is more error attributable to internal system clock noise. A/D converter

accuracy is reduced slightly while the internal RC oscillator is being used

(CSEL = 1).

Address: $1039

Bit 7

ADPU

0

6

CSEL

0

5

IRQE⁽¹⁾

0

4

DLY⁽¹⁾

1

3

CME

0

2

0

1

CR1⁽¹⁾

0

Bit 0

CR0⁽¹⁾

0

Read:

Write:

Reset:

1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes

= Unimplemented

Figure 3-4. System Configuration Options Register (OPTION)

Data Sheet

66

M68HC11E Family — Rev. 5

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

Conversion Process

ADPU — A/D Power-Up Bit

0 = A/D powered down

1 = A/D powered up

CSEL — Clock Select Bit

0 = A/D and EEPROM use system E clock.

1 = A/D and EEPROM use internal RC clock.

IRQE — Configure IRQ for Edge-Sensitive Only Operation

Refer to Section 5. Resets and Interrupts.

DLY — Enable Oscillator Startup Delay Bit

0 = The oscillator startup delay coming out of stop is bypassed and the MCU

resumes processing within about four bus cycles.

1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is

started up from the stop power-saving mode. This delay allows the

crystal oscillator to stabilize.

CME — Clock Monitor Enable Bit

Refer to Section 5. Resets and Interrupts.

Bit 2 — Not implemented

Always reads 0

CR[1:0] — COP Timer Rate Select Bits

Refer to Section 5. Resets and Interrupts and Section 9. Timing System.

3.4 Conversion Process

The A/D conversion sequence begins one E-clock cycle after a write to the A/D

control/status register, ADCTL. The bits in ADCTL select the channel and the mode

of conversion.

An input voltage equal to V_RLconverts to $00 and an input voltage equal to V_RH

converts to $FF (full scale), with no overflow indication. For ratiometric conversions

of this type, the source of each analog input should use V_RHas the supply voltage

and be referenced to V_RL.

3.5 Channel Assignments

The multiplexer allows the A/D converter to select one of 16 analog signals. Eight

of these channels correspond to port E input lines to the MCU, four of the channels

are internal reference points or test functions, and four channels are reserved.

Refer to Table 3-1.

M68HC11E Family — Rev. 5

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Data Sheet

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

Table 3-1. Converter Channel Assignments

Channel

Number

Channel

Signal

Result in ADRx

if MULT = 1

1

AN0

AN1

ADR1

ADR2

ADR3

ADR4

ADR1

ADR2

ADR3

ADR4

—

2

3

AN2

4

AN3

5

AN4

6

AN5

7

8

AN6

AN7

9 – 12

Reserved

(1)

13

ADR1

ADR2

ADR3

ADR4

V_RH

(1)

14

V_RL

(V_RH)/2⁽¹⁾

15

Reserved⁽¹⁾

16

1. Used for factory testing

3.6 Single-Channel Operation

The two types of single-channel operation are:

1. When SCAN = 0, the single selected channel is converted four consecutive

times. The first result is stored in A/D result register 1 (ADR1), and the fourth

result is stored in ADR4. After the fourth conversion is complete, all

conversion activity is halted until a new conversion command is written to

the ADCTL register.

2. When SCAN = 1, conversions continue to be performed on the selected

channel with the fifth conversion being stored in register ADR1 (overwriting

the first conversion result), the sixth conversion overwriting ADR2, and so

on.

3.7 Multiple-Channel Operation

The two types of multiple-channel operation are:

1. When SCAN = 0, a selected group of four channels is converted one time

each. The first result is stored in A/D result register 1 (ADR1), and the fourth

result is stored in ADR4. After the fourth conversion is complete, all

conversion activity is halted until a new conversion command is written to

the ADCTL register.

2. When SCAN = 1, conversions continue to be performed on the selected

group of channels with the fifth conversion being stored in register ADR1

(replacing the earlier conversion result for the first channel in the group), the

sixth conversion overwriting ADR2, and so on.

Data Sheet

68

M68HC11E Family — Rev. 5

Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

Operation in Stop and Wait Modes

3.8 Operation in Stop and Wait Modes

If a conversion sequence is in progress when either the stop or wait mode is

entered, the conversion of the current channel is suspended. When the MCU

resumes normal operation, that channel is resampled and the conversion

sequence is resumed. As the MCU exits wait mode, the A/D circuits are stable and

valid results can be obtained on the first conversion. However, in stop mode, all

analog bias currents are disabled and it is necessary to allow a stabilization period

when leaving stop mode. If stop mode is exited with a delay (DLY = 1), there is

enough time for these circuits to stabilize before the first conversion. If stop mode

is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for the A/D

circuitry to stabilize to avoid invalid results.

3.9 A/D Control/Status Register

All bits in this register can be read or written, except bit 7, which is a read-only

status indicator, and bit 6, which always reads as 0. Write to ADCTL to initiate a

conversion. To quit a conversion in progress, write to this register and a new

conversion sequence begins immediately.

Address: $1030

Bit 7

CCF

6

5

4

3

2

1

Bit 0

CA

Read:

Write:

Reset:

SCAN

MULT

CD

CC

CB

0

Indeterminate after reset

= Unimplemented

Figure 3-5. A/D Control/Status Register (ADCTL)

CCF — Conversion Complete Flag

A read-only status indicator, this bit is set when all four A/D result registers

contain valid conversion results. Each time the ADCTL register is overwritten,

this bit is automatically cleared to 0 and a conversion sequence is started. In the

continuous mode, CCF is set at the end of the first conversion sequence.

Bit 6 — Unimplemented

Always reads 0

SCAN — Continuous Scan Control Bit

When this control bit is clear, the four requested conversions are performed

once to fill the four result registers. When this control bit is set, conversions are

performed continuously with the result registers updated as data becomes

available.

MULT — Multiple Channel/Single Channel Control Bit

When this bit is clear, the A/D converter system is configured to perform four

consecutive conversions on the single channel specified by the four channel

select bits CD:CA (bits [3:0] of the ADCTL register). When this bit is set, the A/D

M68HC11E Family — Rev. 5

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

system is configured to perform a conversion on each of four channels where

each result register corresponds to one channel.

NOTE:

When the multiple-channel continuous scan mode is used, extra care is needed in

the design of circuitry driving the A/D inputs. The charge on the capacitive DAC

array before the sample time is related to the voltage on the previously converted

channel. A charge share situation exists between the internal DAC capacitance

and the external circuit capacitance. Although the amount of charge involved is

small, the rate at which it is repeated is every 64 µs for an E clock of 2 MHz. The

RC charging rate of the external circuit must be balanced against this charge

sharing effect to avoid errors in accuracy. Refer to M68HC11 Reference Manual,

Motorola document order number M68HC11RM/AD, for further information.

CD:CA — Channel Selects D:A Bits

Refer to Table 3-2. When a multiple channel mode is selected (MULT = 1), the

two least significant channel select bits (CB and CA) have no meaning and the

CD and CC bits specify which group of four channels is to be converted.

Table 3-2. A/D Converter Channel Selection

Channel Select

Result in ADRx

Control Bits

CD:CC:CB:CA

0000

Channel Signal

if MULT = 1

AN0

AN1

ADR1

ADR2

ADR3

ADR4

ADR1

ADR2

ADR3

ADR4

—

0001

0010

AN2

0011

AN3

0100

AN4

0101

AN5

0110

AN6

0111

AN7

10XX

Reserved

(1)

1100

1101

1110

1111

ADR1

ADR2

ADR3

ADR4

V_RH

(1)

V_RL

(V_RH)/2⁽¹⁾

Reserved⁽¹⁾

1. Used for factory testing

Data Sheet

70

M68HC11E Family — Rev. 5

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Analog-to-Digital (A/D) Converter

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Analog-to-Digital (A/D) Converter

A/D Converter Result Registers

3.10 A/D Converter Result Registers

These read-only registers hold an 8-bit conversion result. Writes to these registers

have no effect. Data in the A/D converter result registers is valid when the CCF flag

in the ADCTL register is set, indicating a conversion sequence is complete. If

conversion results are needed sooner, refer to Figure 3-3, which shows the A/D

conversion sequence diagram.

Register name: Analog-to-Digital Converter Result Register 1 Address: $1031

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Indeterminate after reset

Register name: Analog-to-Digital Converter Result Register 2 Address: $1032

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Indeterminate after reset

Register name: Analog-to-Digital Converter Result Register 3 Address: $1033

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Indeterminate after reset

Register name: Analog-to-Digital Converter Result Register 4 Address: $1034

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Indeterminate after reset

= Unimplemented

Figure 3-6. Analog-to-Digital Converter

Result Registers (ADR1–ADR4)

M68HC11E Family — Rev. 5

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Analog-to-Digital (A/D) Converter

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Data Sheet

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Data Sheet — M68HC11E Family

Section 4. Central Processor Unit (CPU)

4.1 Introduction

Features of the M68HC11 Family include:

•

Central processor unit (CPU) architecture

Data types

Addressing modes

Instruction set

Special operations such as subroutine calls and interrupts

The CPU is designed to treat all peripheral, input/output (I/O), and memory

locations identically as addresses in the 64-Kbyte memory map. This is referred to

as memory-mapped I/O. There are no special instructions for I/O that are separate

from those used for memory. This architecture also allows accessing an operand

from an external memory location with no execution time penalty.

4.2 CPU Registers

M68HC11 CPU registers are an integral part of the CPU and are not addressed as

if they were memory locations. The seven registers, discussed in the following

paragraphs, are shown in Figure 4-1.

M68HC11E Family — Rev. 5

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Data Sheet

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Central Processor Unit (CPU)

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Central Processor Unit (CPU)

8-BIT ACCUMULATORS A & B

7

A

0

7

B

0

15

D

OR 16-BIT DOUBLE ACCUMULATOR D

IX

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

IY

SP

PC

PROGRAM COUNTER

CONDITION CODES

7

0

S

X

H

I

N

Z

V

C

CARRY/BORROW FROM MSB

OVERFLOW

ZERO

NEGATIVE

I-INTERRUPT MASK

HALF CARRY (FROM BIT 3)

X-INTERRUPT MASK

STOP DISABLE

Figure 4-1. Programming Model

4.2.1 Accumulators A, B, and D

Accumulators A and B are general-purpose 8-bit registers that hold operands and

results of arithmetic calculations or data manipulations. For some instructions,

these two accumulators are treated as a single double-byte (16-bit) accumulator

called accumulator D. Although most instructions can use accumulators A or B

interchangeably, these exceptions apply:

•

The ABX and ABY instructions add the contents of 8-bit accumulator B to

the contents of 16-bit register X or Y, but there are no equivalent instructions

that use A instead of B.

The TAP and TPA instructions transfer data from accumulator A to the

condition code register or from the condition code register to accumulator A.

However, there are no equivalent instructions that use B rather than A.

The decimal adjust accumulator A (DAA) instruction is used after

binary-coded decimal (BCD) arithmetic operations, but there is no

equivalent BCD instruction to adjust accumulator B.

The add, subtract, and compare instructions associated with both A and B

(ABA, SBA, and CBA) only operate in one direction, making it important to

plan ahead to ensure that the correct operand is in the correct accumulator.

Data Sheet

74

M68HC11E Family — Rev. 5

Central Processor Unit (CPU)

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Central Processor Unit (CPU)

CPU Registers

4.2.2 Index Register X (IX)

The IX register provides a 16-bit indexing value that can be added to the 8-bit offset

provided in an instruction to create an effective address. The IX register can also

be used as a counter or as a temporary storage register.

4.2.3 Index Register Y (IY)

The 16-bit IY register performs an indexed mode function similar to that of the IX

register. However, most instructions using the IY register require an extra byte of

machine code and an extra cycle of execution time because of the way the opcode

map is implemented. Refer to 4.4 Opcodes and Operands for further information.

4.2.4 Stack Pointer (SP)

The M68HC11 CPU has an automatic program stack. This stack can be located

anywhere in the address space and can be any size up to the amount of memory

available in the system. Normally, the SP is initialized by one of the first instructions

in an application program. The stack is configured as a data structure that grows

downward from high memory to low memory. Each time a new byte is pushed onto

the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP

is incremented. At any given time, the SP holds the 16-bit address of the next free

location in the stack. Figure 4-2 is a summary of SP operations.

When a subroutine is called by a jump-to-subroutine (JSR) or branch-to-

subroutine (BSR) instruction, the address of the instruction after the JSR or BSR

is automatically pushed onto the stack, least significant byte first. When the

subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The

RTS pulls the previously stacked return address from the stack and loads it into the

program counter. Execution then continues at this recovered return address.

When an interrupt is recognized, the current instruction finishes normally, the

return address (the current value in the program counter) is pushed onto the stack,

all of the CPU registers are pushed onto the stack, and execution continues at the

address specified by the vector for the interrupt.

At the end of the interrupt service routine, an return-from interrupt (RTI) instruction

is executed. The RTI instruction causes the saved registers to be pulled off the

stack in reverse order. Program execution resumes at the return address.

Certain instructions push and pull the A and B accumulators and the X and Y index

registers and are often used to preserve program context. For example, pushing

accumulator A onto the stack when entering a subroutine that uses accumulator A

and then pulling accumulator A off the stack just before leaving the subroutine

ensures that the contents of a register will be the same after returning from the

subroutine as it was before starting the subroutine.

M68HC11E Family — Rev. 5

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Data Sheet

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Central Processor Unit (CPU)

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Central Processor Unit (CPU)

JSR, JUMP TO SUBROUTINE

MAIN PROGRAM

RTI, RETURN FROM INTERRUPT

STACK

7

0

INTERRUPT ROUTINE

PC

SP

SP+1

$9D = JSR

dd

$3B = RTI

DIRECT

INDEXED, X

INDEXED, Y

CCR

ACCB

ACCA

IX_H

RTN

SP+2

NEXT MAIN INSTR.

SP+3

MAIN PROGRAM

SP+4

PC

$AD = JSR

SP+5

IX_L

STACK

ff

7

0

SP+6

IY_H

RTN

NEXT MAIN INSTR.

SP+7

➩ SP–2

SP–1

SP

IY_L

SP+8

RTN_H

RTN_L

RTN_H

RTN_L

MAIN PROGRAM

➩ SP+9

PC

$18 = PRE

$AD = JSR

ff

SWI, SOFTWARE INTERRUPT

RTN

STACK

7

0

MAIN PROGRAM

NEXT MAIN INSTR.

PC

➩ SP–9

SP–8

SP–7

SP–6

SP–5

SP–4

SP–3

SP–2

SP–1

SP

$3F = SWI

CCR

ACCB

ACCA

IX_H

MAIN PROGRAM

PC

$BD = PRE

hh

INDEXED, Y

RTN

ll

WAI, WAIT FOR INTERRUPT

IX_L

NEXT MAIN INSTR.

MAIN PROGRAM

IY_H

PC

IY_L

$3E = WAI

RTN_H

RTN_L

BSR, BRANCH TO SUBROUTINE

STACK

7

0

MAIN PROGRAM

PC

➩ SP–2

SP–1

SP

$8D = BSR

LEGEND:

RTN_H

RTN_L

RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO

BE EXECUTED UPON RETURN FROM SUBROUTINE

RTN = MOST SIGNIFICANT BYTE OF RETURN ADDRESS

H

RTN = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS

L

RTS, RETURN FROM

SUBROUTINE

➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE

dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED

TO BE $00)

ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX

hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS

ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS

rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET

RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE

OFFSET BYTE)

STACK

7

0

MAIN PROGRAM

PC

SP

SP+1

$39 = RTS

RTN_H

RTN_L

➩ SP+2

Figure 4-2. Stacking Operations

4.2.5 Program Counter (PC)

The program counter, a 16-bit register, contains the address of the next instruction

to be executed. After reset, the program counter is initialized from one of six

possible vectors, depending on operating mode and the cause of reset. See

Table 4-1.

Table 4-1. Reset Vector Comparison

Mode

Normal

POR or RESET Pin

$FFFE, F

Clock Monitor

$FFFC, D

COP Watchdog

$FFFA, B

Test or Boot

$BFFE, F

$BFFC, D

$BFFA, B

Data Sheet

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CPU Registers

4.2.6 Condition Code Register (CCR)

This 8-bit register contains:

•

Five condition code indicators (C, V, Z, N, and H),

Two interrupt masking bits (IRQ and XIRQ)

A stop disable bit (S)

In the M68HC11 CPU, condition codes are updated automatically by most

instructions. For example, load accumulator A (LDAA) and store accumulator A

(STAA) instructions automatically set or clear the N, Z, and V condition code flags.

Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange

instructions do not affect the condition codes. Refer to Table 4-2, which shows

what condition codes are affected by a particular instruction.

4.2.6.1 Carry/Borrow (C)

The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during

an arithmetic operation. The C bit also acts as an error flag for multiply and divide

operations. Shift and rotate instructions operate with and through the carry bit to

facilitate multiple-word shift operations.

4.2.6.2 Overflow (V)

4.2.6.3 Zero (Z)

The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the

V bit is cleared.

The Z bit is set if the result of an arithmetic, logic, or data manipulation operation

is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied

subtraction and the condition codes, including Z, reflect the results of that

subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no

other condition flags. For these operations, only = and ≠ conditions can be

determined.

4.2.6.4 Negative (N)

The N bit is set if the result of an arithmetic, logic, or data manipulation operation

is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative

if its most significant bit (MSB) is a 1. A quick way to test whether the contents of a

memory location has the MSB set is to load it into an accumulator and then check

the status of the N bit.

4.2.6.5 Interrupt Mask (I)

The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable

interrupt sources. While the I bit is set, interrupts can become pending, but the

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operation of the CPU continues uninterrupted until the I bit is cleared. After any

reset, the I bit is set by default and can only be cleared by a software instruction.

When an interrupt is recognized, the I bit is set after the registers are stacked, but

before the interrupt vector is fetched. After the interrupt has been serviced, a

return-from-interrupt instruction is normally executed, restoring the registers to the

values that were present before the interrupt occurred. Normally, the I bit is 0 after

a return from interrupt is executed. Although the I bit can be cleared within an

interrupt service routine, "nesting" interrupts in this way should only be done when

there is a clear understanding of latency and of the arbitration mechanism. Refer

to Section 5. Resets and Interrupts.

4.2.6.6 Half Carry (H)

The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic

unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half

carry is used during BCD operations.

4.2.6.7 X Interrupt Mask (X)

The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is

set by default and must be cleared by a software instruction. When an XIRQ

interrupt is recognized, the X and I bits are set after the registers are stacked, but

before the interrupt vector is fetched. After the interrupt has been serviced, an RTI

instruction is normally executed, causing the registers to be restored to the values

that were present before the interrupt occurred. The X interrupt mask bit is set only

by hardware (RESET or XIRQ acknowledge). X is cleared only by program

instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value

loaded into the CCR from the stack has been cleared). There is no hardware action

for clearing X.

4.2.6.8 STOP Disable (S)

Setting the STOP disable (S) bit prevents the STOP instruction from putting the

M68HC11 into a low-power stop condition. If the STOP instruction is encountered

by the CPU while the S bit is set, it is treated as a no-operation (NOP) instruction,

and processing continues to the next instruction. S is set by reset; STOP is

disabled by default.

4.3 Data Types

The M68HC11 CPU supports four data types:

1. Bit data

2. 8-bit and 16-bit signed and unsigned integers

3. 16-bit unsigned fractions

4. 16-bit addresses

Data Sheet

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Opcodes and Operands

A byte is eight bits wide and can be accessed at any byte location. A word is

composed of two consecutive bytes with the most significant byte at the lower

value address. Because the M68HC11 is an 8-bit CPU, there are no special

requirements for alignment of instructions or operands.

4.4 Opcodes and Operands

The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode

identifies a particular instruction and associated addressing mode to the CPU.

Several opcodes are required to provide each instruction with a range of

addressing capabilities. Only 256 opcodes would be available if the range of values

were restricted to the number able to be expressed in 8-bit binary numbers.

A 4-page opcode map has been implemented to expand the number of

instructions. An additional byte, called a prebyte, directs the processor from page

0 of the opcode map to one of the other three pages. As its name implies, the

additional byte precedes the opcode.

A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two,

or three operands. The operands contain information the CPU needs for executing

the instruction. Complete instructions can be from one to five bytes long.

4.5 Addressing Modes

Six addressing modes can be used to access memory:

•

Immediate

Direct

Extended

Indexed

Inherent

Relative

These modes are detailed in the following paragraphs. All modes except inherent

mode use an effective address. The effective address is the memory address from

which the argument is fetched or stored or the address from which execution is to

proceed. The effective address can be specified within an instruction, or it can be

calculated.

4.5.1 Immediate

In the immediate addressing mode, an argument is contained in the byte(s)

immediately following the opcode. The number of bytes following the opcode

matches the size of the register or memory location being operated on. There are

2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective

address is the address of the byte following the instruction.

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4.5.2 Direct

In the direct addressing mode, the low-order byte of the operand address is

contained in a single byte following the opcode, and the high-order byte of the

address is assumed to be $00. Addresses $00–$FF are thus accessed directly,

using 2-byte instructions. Execution time is reduced by eliminating the additional

memory access required for the high-order address byte. In most applications, this

256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the

memory map can be configured for combinations of internal registers, RAM, or

external memory to occupy these addresses.

4.5.3 Extended

4.5.4 Indexed

In the extended addressing mode, the effective address of the argument is

contained in two bytes following the opcode byte. These are 3-byte instructions (or

4-byte instructions if a prebyte is required). One or two bytes are needed for the

opcode and two for the effective address.

In the indexed addressing mode, an 8-bit unsigned offset contained in the

instruction is added to the value contained in an index register (IX or IY). The sum

is the effective address. This addressing mode allows referencing any memory

location in the 64-Kbyte address space. These are 2- to 5-byte instructions,

depending on whether or not a prebyte is required.

4.5.5 Inherent

In the inherent addressing mode, all the information necessary to execute the

instruction is contained in the opcode. Operations that use only the index registers

or accumulators, as well as control instructions with no arguments, are included in

this addressing mode. These are

1- or 2-byte instructions.

4.5.6 Relative

The relative addressing mode is used only for branch instructions. If the branch

condition is true, an 8-bit signed offset included in the instruction is added to the

contents of the program counter to form the effective branch address. Otherwise,

control proceeds to the next instruction. These are usually 2-byte instructions.

4.6 Instruction Set

Refer to Table 4-2, which shows all the M68HC11 instructions in all possible

addressing modes. For each instruction, the table shows the operand construction,

the number of machine code bytes, and execution time in CPU E-clock cycles.

Data Sheet

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Instruction Set

Table 4-2. Instruction Set (Sheet 1 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

ABA

Add

A + B ⇒ A

INH

1B

—

2

—

∆

—

∆

Accumulators

ABX

ABY

ADCA (opr)

Add B to X

Add B to Y

Add with Carry

to A

IX + (00 : B) ⇒ IX

IY + (00 : B) ⇒ IY

A + M + C ⇒ A

INH

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

3A

89

99

—

3

4

2

3

4

5

2

3

4

5

—

∆

—

∆

—

∆

—

∆

—

∆

18

A

B

ii

dd

B9 hh ll

A9

C9 ii

D9 dd

F9 hh ll

E9

ff

ADCB (opr)

ADDA (opr)

ADDB (opr)

ADDD (opr)

ANDA (opr)

ANDB (opr)

Add with Carry

to B

B + M + C ⇒ B

A + M ⇒ A

—

∆

—

∆

0

∆

IND,X

IND,Y

ff

ii

dd

Add Memory to

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

8B

9B

2

3

4

5

2

3

4

5

4

5

6

7

BB hh ll

AB ff

CB ii

DB dd

FB hh ll

EB ff

C3 jj kk

D3 dd

F3 hh ll

Add Memory to

B

B + M ⇒ B

∆

Add 16-Bit to D D + (M : M + 1) ⇒ D

—

∆

E3

ff

ii

dd

AND A with

Memory

A • M ⇒ A

B • M ⇒ B

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

84

94

2

3

4

5

2

3

4

5

—

B4 hh ll

A4

C4 ii

D4 dd

F4 hh ll

E4

ff

AND B with

Memory

ff

18

ASL (opr)

ASLA

Arithmetic Shift

Left

EXT

IND,X

IND,Y

78

68

hh ll

ff

6

7

—

∆

0

ff

b7

b0

C

Arithmetic Shift

Left A

A

B

INH

48

58

05

—

2

3

0

b7

b0

C

ASLB

ASLD

Arithmetic Shift

Left B

—

∆

Arithmetic Shift

Left D

0

b7 A b0 b7 B b0

C

ASR

Arithmetic Shift

Right

EXT

IND,X

IND,Y

77

67

hh ll

ff

6

7

18

ff

b7

b0

C

ASRA

ASRB

BCC (rel)

Arithmetic Shift

Right A

A

B

INH

REL

47

—

2

3

C

Arithmetic Shift

Right B

57

Branch if Carry

Clear

Clear Bit(s)

? C = 0

24

15

rr

—

0

—

BCLR (opr)

(msk)

M • (mm) ⇒ M

DIR

IND,X

IND,Y

dd mm

6

7

8

∆

1D ff mm

18

BCS (rel)

Branch if Carry

Set

? C = 1

REL

25

rr

3

—

M68HC11E Family — Rev. 5

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Table 4-2. Instruction Set (Sheet 2 of 7)

Addressing

Mode

REL

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

BEQ (rel)

BGE (rel)

BGT (rel)

BHI (rel)

Branch if = Zero

Branch if ∆ Zero

Branch if > Zero

? Z = 1

? N ⊕ V = 0

? Z + (N ⊕ V) = 0

? C + Z = 0

27

rr

3

—

REL

2C rr

2E

22

rr

Branch if

Higher

REL

BHS (rel)

Branch if

Higher or Same

Bit(s) Test A

with Memory

? C = 0

A • M

REL

24

rr

3

—

0

—

BITA (opr)

A

IMM

DIR

EXT

IND,X

IND,Y

85

95

ii

dd

2

3

4

5

∆

B5 hh ll

A5

ff

18

BITB (opr)

Bit(s) Test B

with Memory

B • M

B

IMM

DIR

EXT

IND,X

IND,Y

C5 ii

D5 dd

F5 hh ll

E5

2

3

4

5

—

∆

0

—

ff

BLE (rel)

BLO (rel)

BLS (rel)

Branch if ∆ Zero

? Z + (N ⊕ V) = 1

? C = 1

? C + Z = 1

REL

2F

25

23

rr

3

—

Branch if Lower

or Same

BLT (rel)

BMI (rel)

BNE (rel)

Branch if < Zero

Branch if Minus

Branch if not =

Zero

? N ⊕ V = 1

? N = 1

? Z = 0

REL

2D rr

3

—

2B

26

rr

BPL (rel)

BRA (rel)

Branch if Plus

Branch Always

? N = 0

? 1 = 1

REL

2A

20

rr

dd mm

rr

ff mm

rr

3

—

BRCLR(opr)

(msk)

Branch if

Bit(s) Clear

? M • mm = 0

DIR

IND,X

IND,Y

13

1F

6

7

8

(rel)

18

ff mm

rr

BRN (rel)

BRSET(opr)

(msk)

Branch Never

Branch if Bit(s)

Set

? 1 = 0

? (M) • mm = 0

REL

DIR

IND,X

IND,Y

21

rr

dd mm

rr

ff mm

rr

ff mm

rr

3

—

12

1E

6

7

8

(rel)

18

BSET (opr)

(msk)

Set Bit(s)

M + mm ⇒ M

DIR

IND,X

IND,Y

14

dd mm

6

7

8

—

∆

0

—

1C ff mm

BSR (rel)

BVC (rel)

BVS (rel)

Branch to

Subroutine

Branch if

Overflow Clear

See Figure 3–2

? V = 0

REL

8D rr

6

3

—

28

29

rr

Branch if

? V = 1

Overflow Set

CBA

CLC

CLI

Compare A to B

Clear Carry Bit

Clear Interrupt

Mask

A – B

0 ⇒ C

0 ⇒ I

INH

11

0C

0E

—

2

—

0

∆

0

—

CLR (opr)

Clear Memory

Byte

0 ⇒ M

EXT

IND,X

IND,Y

7F

6F

hh ll

ff

6

7

—

0

1

0

18

CLRA

CLRB

CLV

Clear

Accumulator A

Clear

Accumulator B

Clear Overflow

Flag

0 ⇒ A

0 ⇒ B

0 ⇒ V

A

B

INH

4F

5F

0A

—

2

—

0

1

0

—

Data Sheet

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Instruction Set

Table 4-2. Instruction Set (Sheet 3 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

CMPA (opr)

Compare A to

Memory

A – M

A

IMM

DIR

EXT

IND,X

IND,Y

81

91

ii

dd

2

3

4

5

—

∆

B1 hh ll

A1

ff

18

CMPB (opr)

Compare B to

Memory

B – M

B

IMM

DIR

EXT

IND,X

IND,Y

EXT

IND,X

IND,Y

C1 ii

D1 dd

F1 hh ll

2

3

4

5

6

7

—

∆

E1

ff

18

COM (opr)

COMA

Ones

Complement

Memory Byte

Ones

Complement

A

Ones

Complement

B

$FF – M ⇒ M

$FF – A ⇒ A

$FF – B ⇒ B

D – M : M + 1

73

63

hh ll

ff

—

∆

0

∆

1

∆

A

B

INH

43

—

2

COMB

INH

53

2

CPD (opr)

Compare D to

Memory 16-Bit

IMM

DIR

EXT

IND,X

IND,Y

1A

CD

83

93

B3

A3

jj kk

dd

hh ll

ff

5

6

7

ff

CPX (opr)

CPY (opr)

Compare X to

Memory 16-Bit

IX – M : M + 1

IY – M : M + 1

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

8C jj kk

9C dd

BC hh ll

AC ff

8C jj kk

9C dd

BC hh ll

AC ff

4

5

6

7

5

6

7

—

∆

CD

Compare Y to

Memory 16-Bit

18

1A

18

DAA

Decimal Adjust Adjust Sum to BCD

A

INH

19

—

2

—

∆

DEC (opr)

Decrement

M – 1 ⇒ M

A – 1 ⇒ A

B – 1 ⇒ B

EXT

IND,X

IND,Y

7A

6A

hh ll

ff

6

7

—

Memory Byte

18

ff

DECA

DECB

Decrement

Accumulator

A

B

INH

4A

—

2

—

∆

—

Decrement

Accumulator

B

INH

5A

2

DES

DEX

Decrement

Stack Pointer

SP – 1 ⇒ SP

IX – 1 ⇒ IX

INH

34

09

—

3

—

Decrement

Index Register

X

∆

DEY

Decrement

Index Register

Y

IY – 1 ⇒ IY

A ⊕ M ⇒ A

INH

18

09

—

4

—

∆

—

0

—

EORA (opr)

Exclusive OR A

with Memory

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

88

98

ii

dd

2

3

4

5

2

3

4

5

∆

B8 hh ll

A8

C8 ii

D8 dd

F8 hh ll

E8

ff

18

EORB (opr)

Exclusive OR B

with Memory

B ⊕ M ⇒ B

—

∆

0

—

ff

FDIV

IDIV

Fractional

Divide 16 by 16

D / IX ⇒ IX; r ⇒ D

INH

03

02

—

41

—

∆

Integer Divide

16 by 16

INH

41

0

M68HC11E Family — Rev. 5

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Table 4-2. Instruction Set (Sheet 4 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

INC (opr)

Increment

Memory Byte

M + 1 ⇒ M

EXT

IND,X

IND,Y

7C hh ll

6C ff

6

7

—

∆

—

18

INCA

INCB

Increment

Accumulator

A

A + 1 ⇒ A

B + 1 ⇒ B

A

B

INH

4C

—

2

—

∆

—

Increment

Accumulator

B

INH

5C

2

INS

INX

Increment

Stack Pointer

Increment

Index Register

X

SP + 1 ⇒ SP

IX + 1 ⇒ IX

INH

31

08

—

3

—

∆

INY

Increment

Index Register

Y

IY + 1 ⇒ IY

See Figure 3–2

INH

18

08

—

4

—

∆

—

JMP (opr)

JSR (opr)

Jump

EXT

IND,X

IND,Y

DIR

EXT

7E

6E

hh ll

ff

3

4

5

6

7

—

18

ff

Jump to

Subroutine

9D dd

BD hh ll

AD ff

IND,X

IND,Y

AD ff

LDAA (opr)

LDAB (opr)

LDD (opr)

LDS (opr)

LDX (opr)

LDY (opr)

Load

Accumulator

A

M ⇒ A

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

86

96

ii

dd

2

3

4

5

2

3

4

5

3

4

5

6

—

∆

0

—

B6 hh ll

A6

C6 ii

D6 dd

F6 hh ll

E6

CC jj kk

DC dd

FC hh ll

EC ff

8E

9E

BE hh ll

AE ff

CE jj kk

DE dd

FE hh ll

EE ff

ff

18

CD

Load

Accumulator

B

M ⇒ B

ff

Load Double

Accumulator

D

M ⇒ A,M + 1 ⇒ B

M : M + 1 ⇒ SP

M : M + 1 ⇒ IX

M : M + 1 ⇒ IY

Load Stack

Pointer

IMM

DIR

EXT

IND,X

IND,Y

jj kk

dd

3

4

5

6

Load Index

Register

X

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

3

4

5

6

4

5

6

EE ff

CE jj kk

DE dd

FE hh ll

EE ff

Load Index

Register

Y

18

1A

18

LSL (opr)

LSLA

Logical Shift

Left

EXT

IND,X

IND,Y

78

68

hh ll

ff

6

7

—

∆

0

18

b7

b0

C

Logical Shift

Left A

A

B

INH

48

58

05

—

2

3

0

LSLB

Logical Shift

Left B

LSLD

Logical Shift

Left Double

0

b7 A b0 b7 B b0

C

Data Sheet

84

M68HC11E Family — Rev. 5

MOTOROLA

Central Processor Unit (CPU)

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Central Processor Unit (CPU)

Instruction Set

Table 4-2. Instruction Set (Sheet 5 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

LSR (opr)

Logical Shift

Right

EXT

IND,X

IND,Y

74

64

hh ll

ff

6

7

—

0

∆

0

18

b7

b0

C

LSRA

LSRB

LSRD

Logical Shift

Right A

A

B

INH

44

54

04

3D

—

2

—

0

∆

Logical Shift

Right B

2

Logical Shift

Right Double

3

0

b7 A b0 b7 B b0

A ∗ B ⇒ D

C

MUL

NEG (opr)

Multiply 8 by 8

10

—

∆

—

∆

—

∆

Two’s

Complement

Memory Byte

0 – M ⇒ M

EXT

IND,X

IND,Y

70

60

hh ll

ff

6

7

18

NEGA

NEGB

Two’s

Complement

A

Two’s

Complement

B

0 – A ⇒ A

0 – B ⇒ B

A

B

INH

40

50

01

—

2

—

∆

NOP

No operation

No Operation

—

0

—

ORAA (opr)

OR

Accumulator

A (Inclusive)

A + M ⇒ A

A

B

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

8A

9A

ii

dd

2

3

4

5

2

3

4

5

∆

BA hh ll

AA ff

CA ii

DA dd

FA hh ll

EA ff

18

ORAB (opr)

OR

Accumulator

B (Inclusive)

B + M ⇒ B

—

∆

0

—

PSHA

PSHB

PSHX

Push A onto

Stack

A ⇒ Stk,SP = SP – 1

B ⇒ Stk,SP = SP – 1

A

INH

36

37

3C

—

3

4

—

Push B onto

Stack

Push X onto IX ⇒ Stk,SP = SP – 2

B

Stack (Lo

First)

PSHY

Push Y onto IY ⇒ Stk,SP = SP – 2

INH

18

3C

—

5

—

Stack (Lo

First)

PULA

PULB

PULX

Pull A from

Stack

Pull B from

Stack

SP = SP + 1, A ⇐ Stk A

SP = SP + 1, B ⇐ Stk B

INH

32

33

38

—

4

5

—

Pull X From SP = SP + 2, IX ⇐ Stk

Stack (Hi

First)

PULY

ROL (opr)

ROLA

Pull Y from

Stack (Hi

First)

SP = SP + 2, IY ⇐ Stk

INH

18

38

—

6

—

∆

—

∆

—

∆

—

∆

Rotate Left

Rotate Left A

Rotate Left B

Rotate Right

EXT

IND,X

IND,Y

79

69

hh ll

ff

6

7

ff

b7

b0

C

A

B

INH

49

—

2

∆

C

ROLB

INH

59

2

∆

C

ROR (opr)

EXT

IND,X

IND,Y

76

66

hh ll

ff

6

7

∆

b7

b0

C

18

ff

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

85

Central Processor Unit (CPU)

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Freescale Semiconductor, Inc.

Central Processor Unit (CPU)

Table 4-2. Instruction Set (Sheet 6 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

RORA

Rotate Right A

A

B

INH

46

—

2

—

∆

b7

b0

C

RORB

Rotate Right B

INH

56

—

∆

RTI

RTS

Return from

Interrupt

See Figure 3–2

A – B ⇒ A

INH

3B

39

10

—

12

5

∆

↓

∆

—

∆

—

∆

—

∆

—

∆

Return from

Subroutine

Subtract B from

A

Subtract with

Carry from A

—

SBA

2

SBCA (opr)

A – M – C ⇒ A

A

IMM

DIR

EXT

IND,X

IND,Y

82

92

ii

dd

2

3

4

5

∆

B2 hh ll

A2

ff

18

SBCB (opr)

Subtract with

Carry from B

B – M – C ⇒ B

B

IMM

DIR

EXT

IND,X

IND,Y

C2 ii

D2 dd

F2 hh ll

E2

2

3

4

5

—

∆

ff

SEC

SEI

Set Carry

1 ⇒ C

1 ⇒ I

INH

0D

0F

—

2

—

1

—

1

Set Interrupt

Mask

—

SEV

Set Overflow

Flag

Store

Accumulator

A

1 ⇒ V

INH

0B

—

2

—

1

0

—

STAA (opr)

A ⇒ M

A

B

DIR

EXT

IND,X

IND,Y

DIR

EXT

IND,X

IND,Y

97

B7

A7 ff

D7 dd

F7

E7 ff

DD dd

FD hh ll

ED ff

dd

3

4

5

3

4

5

∆

hh ll

18

STAB (opr)

STD (opr)

Store

Accumulator

B

B ⇒ M

—

∆

0

—

hh ll

Store

Accumulator

D

A ⇒ M, B ⇒ M + 1

DIR

EXT

IND,X

IND,Y

4

5

6

ED ff

STOP

Stop Internal

Clocks

—

INH

CF

—

2

—

0

—

STS (opr)

Store Stack

Pointer

SP ⇒ M : M + 1

DIR

EXT

IND,X

IND,Y

9F

dd

4

5

6

∆

BF hh ll

AF ff

18

STX (opr)

STY (opr)

SUBA (opr)

Store Index

Register X

IX ⇒ M : M + 1

IY ⇒ M : M + 1

A – M ⇒ A

DIR

EXT

IND,X

IND,Y

DIR

EXT

IND,X

IND,Y

DF dd

4

5

6

5

6

—

∆

0

∆

—

∆

FF

hh ll

EF ff

DF dd

CD

Store Index

Register Y

18

1A

18

FF

hh ll

EF ff

Subtract

Memory from

A

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

IMM

DIR

EXT

IND,X

IND,Y

80

90

ii

dd

2

3

4

5

2

3

4

5

4

5

6

7

B0 hh ll

A0

ff

18

SUBB (opr)

SUBD (opr)

Subtract

Memory from

B

B – M ⇒ B

C0 ii

D0 dd

F0 hh ll

—

∆

E0

ff

Subtract

Memory from

D

D – M : M + 1 ⇒ D

83

93

jj kk

dd

B3 hh ll

A3

ff

Data Sheet

86

M68HC11E Family — Rev. 5

MOTOROLA

Central Processor Unit (CPU)

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Central Processor Unit (CPU)

Instruction Set

Table 4-2. Instruction Set (Sheet 7 of 7)

Addressing

Mode

Instruction

Operand Cycles

Condition Codes

Mnemonic

Operation

Description

Opcode

S

X

H

I

N

Z

V

C

SWI

Software

Interrupt

See Figure 3–2

INH

3F

—

14

—

1

—

TAB

TAP

Transfer A to B

A ⇒ B

INH

16

06

—

2

—

∆

0

—

Transfer A to

CC Register

A ⇒ CCR

∆

↓

∆

TBA

Transfer B to A

B ⇒ A

INH

17

00

—

2

*

—

∆

0

—

TEST

TEST (Only in Address Bus Counts

Test Modes)

—

TPA

Transfer CC

Register to A

Test for Zero or

Minus

CCR ⇒ A

INH

07

—

2

—

0

—

0

TST (opr)

M – 0

EXT

IND,X

IND,Y

7D hh ll

6D ff

6

7

∆

18

TSTA

TSTB

TSX

Test A for Zero

or Minus

A – 0

B – 0

A

B

INH

4D

5D

30

35

3E

8F

—

2

3

4

3

4

**

3

4

—

∆

0

Test B for Zero

or Minus

Transfer Stack

Pointer to X

Transfer Stack

Pointer to Y

∆

0

SP + 1 ⇒ IX

SP + 1 ⇒ IY

IX – 1 ⇒ SP

IY – 1 ⇒ SP

Stack Regs & WAIT

IX ⇒ D, D ⇒ IX

IY ⇒ D, D ⇒ IY

—

TSY

18

TXS

Transfer X to

Stack Pointer

Transfer Y to

Stack Pointer

Wait for

Interrupt

TYS

WAI

XGDX

XGDY

Exchange D

with X

Exchange D

with Y

18

Cycle

*

Infinity or until reset occurs

**

12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock

cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).

Operands

dd

ff

hh

ii

jj

kk

ll

mm

rr

= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)

= 8-bit positive offset $00 (0) to $FF (255) (is added to index)

= High-order byte of 16-bit extended address

= One byte of immediate data

= High-order byte of 16-bit immediate data

= Low-order byte of 16-bit immediate data

= Low-order byte of 16-bit extended address

= 8-bit mask (set bits to be affected)

= Signed relative offset $80 (–128) to $7F (+127)

(offset relative to address following machine code offset byte))

Operators

Condition Codes

( )

⇐

⇑

Contents of register shown inside parentheses

—

0

Bit not changed

Is transferred to

Bit always cleared

Is pulled from stack

Is pushed onto stack

Boolean AND

1

Bit always set

⇓

∆

↓

Bit cleared or set, depending on operation

Bit can be cleared, cannot become set

•

+

Arithmetic addition symbol except where used as inclusive-OR symbol

in Boolean formula

⊕

∗

:

Exclusive-OR

Multiply

Concatenation

–

Arithmetic subtraction symbol or negation symbol (two’s complement)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

87

Central Processor Unit (CPU)

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Central Processor Unit (CPU)

Data Sheet

88

M68HC11E Family — Rev. 5

MOTOROLA

Central Processor Unit (CPU)

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Data Sheet — M68HC11E Family

Section 5. Resets and Interrupts

5.1 Introduction

Resets and interrupt operations load the program counter with a vector that points

to a new location from which instructions are to be fetched. A reset immediately

stops execution of the current instruction and forces the program counter to a

known starting address. Internal registers and control bits are initialized so the

MCU can resume executing instructions. An interrupt temporarily suspends normal

program execution while an interrupt service routine is being executed. After an

interrupt has been serviced, the main program resumes as if there had been no

interruption.

5.2 Resets

The four possible sources of reset are:

•

Power-on reset (POR)

External reset (RESET)

Computer operating properly (COP) reset

Clock monitor reset

POR and RESET share the normal reset vector. COP reset and the clock monitor

reset each has its own vector.

5.2.1 Power-On Reset (POR)

A positive transition on V_DDgenerates a power-on reset (POR), which is used only

for power-up conditions. POR cannot be used to detect drops in power supply

voltages. A 4064 t_CYC(internal clock cycle) delay after the oscillator becomes

active allows the clock generator to stabilize. If RESET is at logical 0 at the end of

4064 t_CYC, the CPU remains in the reset condition until RESET goes to logical 1.

The POR circuit only initializes internal circuitry during cold starts. Refer to

Figure 1-7. External Reset Circuit.

NOTE:

It is important to protect the MCU during power transitions. Most M68HC11

systems need an external circuit that holds the RESET pin low whenever V_DDis

below the minimum operating level. This external voltage level detector, or other

external reset circuits, are the usual source of reset in a system.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Resets and Interrupts

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Resets and Interrupts

5.2.2 External Reset (RESET)

The CPU distinguishes between internal and external reset conditions by sensing

whether the reset pin rises to a logic 1 in less than two E-clock cycles after an

internal device releases reset. When a reset condition is sensed, the RESET pin is

driven low by an internal device for four E-clock cycles, then released. Two E-clock

cycles later it is sampled. If the pin is still held low, the CPU assumes that an

external reset has occurred. If the pin is high, it indicates that the reset was initiated

internally by either the COP system or the clock monitor.

CAUTION:

Do not connect an external resistor capacitor (RC) power-up delay circuit to the

reset pin of M68HC11 devices because the circuit charge time constant can cause

the device to misinterpret the type of reset that occurred.

5.2.3 Computer Operating Properly (COP) Reset

The MCU includes a COP system to help protect against software failures. When

the COP is enabled, the software is responsible for keeping a free-running

watchdog timer from timing out. When the software is no longer being executed in

the intended sequence, a system reset is initiated.

The state of the NOCOP bit in the CONFIG register determines whether the COP

system is enabled or disabled. To change the enable status of the COP system,

change the contents of the CONFIG register and then perform a system reset. In

the special test and bootstrap operating modes, the COP system is initially

inhibited by the disable resets (DISR) control bit in the TEST1 register. The DISR

bit can subsequently be written to 0 to enable COP resets.

The COP timer rate control bits CR[1:0] in the OPTION register determine the COP

timeout period. The system E clock is divided by 2¹⁵and then further scaled by a

factor shown in Table 5-1. After reset, these bits are 0, which selects the fastest

timeout period. In normal operating modes, these bits can be written only once

within 64 bus cycles after reset.

Table 5-1. COP Timer Rate Select

XTAL = 4.0 MHz

Timeout

XTAL = 8.0 MHz XTAL = 12.0 MHz XTAL = 16.0 MHz

Timeout Timeout Timeout

Divide

E/2¹⁵By

CR[1:0]

– 0 ms, + 32.8 ms – 0 ms, + 16.4 ms – 0 ms, + 10.9 ms – 0 ms, + 8.2 ms

0 0

0 1

1 0

1 1

1

4

32.768 ms

131.072 ms

524.28 ms

2.098 s

16.384 ms

65.536 ms

262.14 ms

1.049 s

10.923 ms

43.691 ms

174.76 ms

699.05 ms

3.0 MHz

8.19 ms

32.8 ms

131 ms

524 ms

4.0 MHz

16

64

E =

1.0 MHz

2.0 MHz

Data Sheet

90

M68HC11E Family — Rev. 5

MOTOROLA

Resets and Interrupts

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Resets and Interrupts

Resets

Address

$103A

Bit 7

6

BIT 6

0

5

BIT 5

0

4

BIT 4

0

3

BIT 3

0

2

BIT 2

0

1

BIT 1

0

Bit 0

BIT 0

0

Read:

Write:

Reset:

BIT 7

0

Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST)

Complete this 2-step reset sequence to service the COP timer:

1. Write $55 to COPRST to arm the COP timer clearing mechanism.

2. Write $AA to COPRST to clear the COP timer.

Performing instructions between these two steps is possible as long

as both steps are completed in the correct sequence before the timer times out.

5.2.4 Clock Monitor Reset

The clock monitor circuit is based on an internal resistor capacitor (RC) time delay.

If no MCU clock edges are detected within this RC time delay, the clock monitor

can optionally generate a system reset. The clock monitor function is enabled or

disabled by the CME control bit in the OPTION register. The presence of a timeout

is determined by the RC delay, which allows the clock monitor to operate without

any MCU clocks.

Clock monitor is used as a backup for the COP system. Because the COP needs

a clock to function, it is disabled when the clock stops. Therefore, the clock monitor

system can detect clock failures not detected by the COP system.

Semiconductor wafer processing causes variations of the RC timeout values

between individual devices. An E-clock frequency below 10 kHz is detected as a

clock monitor error. An E-clock frequency of 200 kHz or more prevents clock

monitor errors. Using the clock monitor function when the E-clock is below 200 kHz

is not recommended.

Special considerations are needed when a STOP instruction is executed and the

clock monitor is enabled. Because the STOP function causes the clocks to be

halted, the clock monitor function generates a reset sequence if it is enabled at the

time the stop mode was initiated. Before executing a STOP instruction, clear the

CME bit in the OPTION register to 0 to disable the clock monitor. After recovery

from STOP, set the CME bit to logic 1 to enable the clock monitor. Alternatively,

executing a STOP instruction with the CME bit set to logic 1 can be used as a

software initiated reset.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Resets and Interrupts

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Resets and Interrupts

5.2.5 System Configuration Options Register

Address:

$1039

Bit 7

6

CSEL

0

5

IRQE⁽¹⁾

0

4

DLY⁽¹⁾

1

3

CME

0

2

1

CR1⁽¹⁾

0

Bit 0

CR0⁽¹⁾

0

Read:

Write:

Reset:

ADPU

0

1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes

= Unimplemented

Figure 5-2. System Configuration Options Register (OPTION)

ADPU — Analog-to-Digital Converter Power-Up Bit

Refer to Section 3. Analog-to-Digital (A/D) Converter.

CSEL — Clock Select Bit

Refer to Section 3. Analog-to-Digital (A/D) Converter.

IRQE — Configure IRQ for Edge-Sensitive-Only Operation Bit

0 = IRQ is configured for level-sensitive operation.

1 = IRQ is configured for edge-sensitive-only operation.

DLY — Enable Oscillator Startup Delay Bit

Refer to Section 2. Operating Modes and On-Chip Memory and Section 3.

Analog-to-Digital (A/D) Converter.

CME — Clock Monitor Enable Bit

This control bit can be read or written at any time and controls whether or not

the internal clock monitor circuit triggers a reset sequence when the system

clock is slow or absent. When it is clear, the clock monitor circuit is disabled, and

when it is set, the clock monitor circuit is enabled. Reset clears the CME bit.

0 = Clock monitor circuit disabled

1 = Slow or stopped clocks cause reset

Bit 2 — Unimplemented

Always reads 0

CR[1:0] — COP Timer Rate Select Bit

The internal E clock is first divided by 2¹⁵before it enters the COP watchdog

system. These control bits determine a scaling factor for the watchdog timer.

See Table 5-1 for specific timeout settings.

Data Sheet

92

M68HC11E Family — Rev. 5

Resets and Interrupts

MOTOROLA

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Resets and Interrupts

Effects of Reset

5.2.6 Configuration Control Register

Address:

$103F

Bit 7

6

EE2

0

5

EE1

0

4

EE0

0

3

NOSEC

1

2

NOCOP

1

ROMON

1

Bit 0

EEON

1

Read:

Write:

Reset:

EE3

0

Figure 5-3. Configuration Control Register (CONFIG)

EE[3:0] — EEPROM Mapping Bits

EE[3:0] apply only to MC68HC811E2. Refer to Section 2. Operating Modes

and On-Chip Memory.

NOSEC — Security Mode Disable Bit

Refer to Section 2. Operating Modes and On-Chip Memory.

NOCOP — COP System Disable Bit

0 = COP enabled (forces reset on timeout)

1 = COP disabled (does not force reset on timeout)

ROMON — ROM (EPROM) Enable Bit

Refer to Section 2. Operating Modes and On-Chip Memory.

EEON — EEPROM Enable Bit

Refer to Section 2. Operating Modes and On-Chip Memory.

5.3 Effects of Reset

When a reset condition is recognized, the internal registers and control bits are

forced to an initial state. Depending on the cause of the reset and the operating

mode, the reset vector can be fetched from any of six possible locations. Refer to

Table 5-2.

Table 5-2. Reset Cause, Reset Vector, and Operating Mode

Normal Mode

Vector

Special Test

or Bootstrap

Cause of Reset

POR or RESET pin

Clock monitor failure

COP Watchdog Timeout

$FFFE, FFFF

$FFFC, FFFD

$FFFA, FFFB

$BFFE, $BFFF

$BFFC, $BFFD

$BFFA, $BFFB

These initial states then control on-chip peripheral systems to force them to known

startup states, as described in the following subsections.

M68HC11E Family — Rev. 5

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Resets and Interrupts

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Resets and Interrupts

5.3.1 Central Processor Unit (CPU)

After reset, the central processor unit (CPU) fetches the restart vector from the

appropriate address during the first three cycles and begins executing instructions.

The stack pointer and other CPU registers are indeterminate immediately after

reset; however, the X and I interrupt mask bits in the condition code register (CCR)

are set to mask any interrupt requests. Also, the S bit in the CCR is set to inhibit

stop mode.

5.3.2 Memory Map

After reset, the INIT register is initialized to $01, mapping the RAM at $00 and the

control registers at $1000.

For the MC68HC811E2, the CONFIG register resets to $FF. EEPROM mapping

bits (EE[3:0]) place the EEPROM at $F800. Refer to the memory map diagram for

MC68HC811E2 in Section 2. Operating Modes and On-Chip Memory.

5.3.3 Timer

During reset, the timer system is initialized to a count of $0000. The prescaler bits

are cleared, and all output compare registers are initialized to $FFFF. All input

capture registers are indeterminate after reset. The output compare 1 mask

(OC1M) register is cleared so that successful OC1 compares do not affect any I/O

pins. The other four output compares are configured so that they do not affect any

I/O pins on successful compares. All input capture edge-detector circuits are

configured for capture disabled operation. The timer overflow interrupt flag and all

eight timer function interrupt flags are cleared. All nine timer interrupts are disabled

because their mask bits have been cleared.

The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as

OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5

does not control the PA3 pin.

5.3.4 Real-Time Interrupt (RTI)

The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are

masked. The rate control bits are cleared after reset and can be initialized by

software before the real-time interrupt (RTI) system is used.

5.3.5 Pulse Accumulator

The pulse accumulator system is disabled at reset so that the pulse accumulator

input (PAI) pin defaults to being a general-purpose input pin.

Data Sheet

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M68HC11E Family — Rev. 5

Resets and Interrupts

MOTOROLA

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Resets and Interrupts

Effects of Reset

5.3.6 Computer Operating Properly (COP)

The COP watchdog system is enabled if the NOCOP control bit in the CONFIG

register is cleared and disabled if NOCOP is set. The COP rate is set for the

shortest duration timeout.

5.3.7 Serial Communications Interface (SCI)

The reset condition of the SCI system is independent of the operating mode. At

reset, the SCI baud rate control register (BAUD) is initialized to $04. All transmit

and receive interrupts are masked and both the transmitter and receiver are

disabled so the port pins default to being general-purpose I/O lines. The SCI frame

format is initialized to an 8-bit character size. The send break and receiver wakeup

functions are disabled. The TDRE and TC status bits in the SCI status register

(SCSR) are both 1s, indicating that there is no transmit data in either the transmit

data register or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF,

and RAF receive-related status bits in the SCI control register 2 (SCCR2) are

cleared.

5.3.8 Serial Peripheral Interface (SPI)

The SPI system is disabled by reset. The port pins associated with this function

default to being general-purpose I/O lines.

5.3.9 Analog-to-Digital (A/D) Converter

The analog-to-digital (A/D) converter configuration is indeterminate after reset. The

ADPU bit is cleared by reset, which disables the A/D system. The conversion

complete flag is indeterminate.

5.3.10 System

The EEPROM programming controls are disabled, so the memory system is

configured for normal read operation. PSEL[3:0] are initialized with the value

%0110, causing the external IRQ pin to have the highest I-bit interrupt priority. The

IRQ pin is configured for level-sensitive operation (for wired-OR systems). The

RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status of the

MODB and MODA inputs at the rising edge of reset. MODA and MODB inputs

select one of the four operating modes. After reset, writing SMOD and MDA in

special modes causes the MCU to change operating modes. Refer to the

description of HPRIO register in Section 2. Operating Modes and On-Chip

Memory for a detailed description of SMOD and MDA. The DLY control bit is set

to specify that an oscillator startup delay is imposed upon recovery from stop

mode. The clock monitor system is disabled because CME is cleared.

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5.4 Reset and Interrupt Priority

Resets and interrupts have a hardware priority that determines which reset or

interrupt is serviced first when simultaneous requests occur. Any maskable

interrupt can be given priority over other maskable interrupts.

The first six interrupt sources are not maskable. The priority arrangement for these

sources is:

1. POR or RESET pin

2. Clock monitor reset

3. COP watchdog reset

4. XIRQ interrupt

5. Illegal opcode interrupt

6. Software interrupt (SWI)

The maskable interrupt sources have this priority arrangement:

1. IRQ

2. Real-time interrupt

3. Timer input capture 1

4. Timer input capture 2

5. Timer input capture 3

6. Timer output compare 1

7. Timer output compare 2

8. Timer output compare 3

9. Timer output compare 4

10. Timer input capture 4/output compare 5

11. Timer overflow

12. Pulse accumulator overflow

13. Pulse accumulator input edge

14. SPI transfer complete

15. SCI system (refer to Figure 5-7)

Any one of these interrupts can be assigned the highest maskable interrupt priority

by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise,

the priority arrangement remains the same. An interrupt that is assigned highest

priority is still subject to global masking by the I bit in the CCR, or by any associated

local bits. Interrupt vectors are not affected by priority assignment. To avoid race

conditions, HPRIO can be written only while I-bit interrupts are inhibited.

Data Sheet

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Reset and Interrupt Priority

5.4.1 Highest Priority Interrupt and Miscellaneous Register

Address:

$103C

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

RBOOT⁽¹⁾SMOD⁽¹⁾

MDA⁽¹⁾

IRVNE

PSEL2

PSEL1

PSEL0

Reset:

Single chip:

Expanded:

Bootstrap:

0

1

0

1

0

1

0

1

0

1

0

1

0

Special test:

1. The values of the RBOOT, SMOD, and MDA reset bits depend on the mode selected at the

RESET pin rising edge. Refer to Table 2-1. Hardware Mode Select Summary.

Figure 5-4. Highest Priority I-Bit Interrupt

and Miscellaneous Register (HPRIO)

RBOOT — Read Bootstrap ROM Bit

Has meaning only when the SMOD bit is a 1 (bootstrap mode or special test

mode). At all other times this bit is clear and cannot be written. Refer to Section

2. Operating Modes and On-Chip Memory for more information.

SMOD — Special Mode Select Bit

This bit reflects the inverse of the MODB input pin at the rising edge of reset.

Refer to Section 2. Operating Modes and On-Chip Memory for more

information.

MDA — Mode Select A Bit

The mode select A bit reflects the status of the MODA input pin at the rising

edge of reset. Refer to Section 2. Operating Modes and On-Chip Memory for

more information.

IRVNE — Internal Read Visibility/Not E Bit

The IRVNE control bit allows internal read accesses to be available on the

external data bus during operation in expanded modes. In single-chip and

bootstrap modes, IRVNE determines whether the E clock is driven out an

external pin. For the MC68HC811E2, this bit is IRV and only controls internal

read visibility. Refer to Section 2. Operating Modes and On-Chip Memory for

more information.

PSEL[3:0] — Priority Select Bits

These bits select one interrupt source to be elevated above all other I-bit-related

sources and can be written only while the I bit in the CCR is set (interrupts

disabled).

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Table 5-3. Highest Priority Interrupt Selection

PSEL[3:0]

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Interrupt Source Promoted

Timer overflow

Pulse accumulator overflow

Pulse accumulator input edge

SPI serial transfer complete

SCI serial system

Reserved (default to IRQ)

IRQ (external pin or parallel I/O)

Real-time interrupt

Timer input capture 1

Timer input capture 2

Timer input capture 3

Timer output compare 1

Timer output compare 2

Timer output compare 3

Timer output compare 4

Timer input capture 4/output compare 5

5.5 Interrupts

The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15

maskable interrupts are generated by on-chip peripheral systems. These interrupts

are recognized when the global interrupt mask bit (I) in the condition code register

(CCR) is clear. The three non-maskable interrupt sources are illegal opcode trap,

software interrupt, and XIRQ pin. Refer to Table 5-4, which shows the interrupt

sources and vector assignments for each source.

For some interrupt sources, such as the SCI interrupts, the flags are automatically

cleared during the normal course of responding to the interrupt requests. For

example, the RDRF flag in the SCI system is cleared by the automatic clearing

mechanism consisting of a read of the SCI status register while RDRF is set,

followed by a read of the SCI data register. The normal response to an RDRF

interrupt request would be to read the SCI status register to check for receive

errors, then to read the received data from the SCI data register. These steps

satisfy the automatic clearing mechanism without requiring special instructions.

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Table 5-4. Interrupt and Reset Vector Assignments

CCR

Mask Bit

Local

Mask

Vector Address

Interrupt Source

FFC0, C1 – FFD4, D5 Reserved

SCI serial system

—

• SCI receive data register full

• SCI receiver overrun

• SCI transmit data register empty

• SCI transmit complete

RIE

TIE

TCIE

ILIE

FFD6, D7

I

• SCI idle line detect

FFD8, D9

FFDA, DB

FFDC, DD

FFDE, DF

FFE0, E1

FFE2, E3

FFE4, E5

FFE6, E7

FFE8, E9

FFEA, EB

FFEC, ED

FFEE, EF

FFF0, F1

FFF2, F3

FFF4, F5

FFF6, F7

FFF8, F9

FFFA, FB

FFFC, FD

FFFE, FF

SPI serial transfer complete

Pulse accumulator input edge

Pulse accumulator overflow

Timer overflow

I

SPIE

PAII

I

PAOVI

TOI

I

Timer input capture 4/output compare 5

Timer output compare 4

Timer output compare 3

Timer output compare 2

Timer output compare 1

Timer input capture 3

Timer input capture 2

Timer input capture 1

Real-time interrupt

I

I4/O5I

OC4I

OC3I

OC2I

OC1I

IC3I

I

IC2I

I

IC1I

I

RTII

IRQ (external pin)

I

None

NOCOP

CME

None

XIRQ pin

X

Software interrupt

None

Illegal opcode trap

COP failure

Clock monitor fail

RESET

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5.5.1 Interrupt Recognition and Register Stacking

An interrupt can be recognized at any time after it is enabled by its local mask, if

any, and by the global mask bit in the CCR. Once an interrupt source is recognized,

the CPU responds at the completion of the instruction being executed. Interrupt

latency varies according to the number of cycles required to complete the current

instruction. When the CPU begins to service an interrupt, the contents of the CPU

registers are pushed onto the stack in the order shown in Table 5-5. After the CCR

value is stacked, the I bit and the X bit, if XIRQ is pending, are set to inhibit further

interrupts. The interrupt vector for the highest priority pending source is fetched

and execution continues at the address specified by the vector. At the end of the

interrupt service routine, the return-from-interrupt instruction is executed and the

saved registers are pulled from the stack in reverse order so that normal program

execution can resume. Refer to Section 4. Central Processor Unit (CPU).

Table 5-5. Stacking Order on Entry to Interrupts

Memory Location

SP

CPU Registers

PCL

SP–1

PCH

SP–2

IYL

SP–3

IYH

SP–4

IXL

SP–5

IXH

SP–6

ACCA

ACCB

CCR

SP–7

SP–8

5.5.2 Non-Maskable Interrupt Request (XIRQ)

Non-maskable interrupts are useful because they can always interrupt CPU

operations. The most common use for such an interrupt is for serious system

problems, such as program runaway or power failure. The XIRQ input is an

updated version of the NMI (non-maskable interrupt) input of earlier MCUs.

Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable

interrupts and XIRQ. After minimum system initialization, software can clear the X

bit by a TAP instruction, enabling XIRQ interrupts. Thereafter, software cannot set

the X bit. Thus, an XIRQ interrupt is a non-maskable interrupt. Because the

operation of the I-bit-related interrupt structure has no effect on the X bit, the

internal XIRQ pin remains unmasked. In the interrupt priority logic, the XIRQ

interrupt has a higher priority than any source that is maskable by the I bit. All

I-bit-related interrupts operate normally with their own priority relationship.

When an I-bit-related interrupt occurs, the I bit is automatically set by hardware

after stacking the CCR byte. The X bit is not affected. When an X-bit-related

interrupt occurs, both the X and I bits are automatically set by hardware after

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Interrupts

stacking the CCR. A return-from-interrupt instruction restores the X and I bits to

their pre-interrupt request state.

5.5.3 Illegal Opcode Trap

Because not all possible opcodes or opcode sequences are defined, the MCU

includes an illegal opcode detection circuit, which generates an interrupt request.

When an illegal opcode is detected and the interrupt is recognized, the current

value of the program counter is stacked. After interrupt service is complete,

reinitialize the stack pointer so repeated execution of illegal opcodes does not

cause stack underflow. Left uninitialized, the illegal opcode vector can point to a

memory location that contains an illegal opcode. This condition causes an infinite

loop that causes stack underflow. The stack grows until the system crashes.

The illegal opcode trap mechanism works for all unimplemented opcodes on all

four opcode map pages. The address stacked as the return address for the illegal

opcode interrupt is the address of the first byte of the illegal opcode. Otherwise, it

would be almost impossible to determine whether the illegal opcode had been one

or two bytes. The stacked return address can be used as a pointer to the illegal

opcode so the illegal opcode service routine can evaluate the offending opcode.

5.5.4 Software Interrupt (SWI)

SWI is an instruction, and thus cannot be interrupted until complete. SWI is not

inhibited by the global mask bits in the CCR. Because execution of SWI sets the I

mask bit, once an SWI interrupt begins, other interrupts are inhibited until SWI is

complete, or until user software clears the I bit in the CCR.

5.5.5 Maskable Interrupts

The maskable interrupt structure of the MCU can be extended to include additional

external interrupt sources through the IRQ pin. The default configuration of this pin

is a low-level sensitive wired-OR network. When an event triggers an interrupt, a

software accessible interrupt flag is set. When enabled, this flag causes a constant

request for interrupt service. After the flag is cleared, the service request is

released.

5.5.6 Reset and Interrupt Processing

Figure 5-5 and Figure 5-6 illustrate the reset and interrupt process. Figure 5-5

illustrates how the CPU begins from a reset and how interrupt detection relates to

normal opcode fetches. Figure 5-6 is an expansion of a block in Figure 5-5 and

illustrates interrupt priorities. Figure 5-7 shows the resolution of interrupt sources

within the SCI subsystem.

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HIGHEST

PRIORITY

POWER-ON RESET

(POR)

DELAY 4064 E CYCLES

EXTERNAL RESET

CLOCK MONITOR FAIL

(WITH CME = 1)

LOWEST

PRIORITY

COP WATCHDOG

TIMEOUT

(WITH NOCOP = 0)

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFE, $FFFF

(VECTOR FETCH)

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFC, $FFFD

LOAD PROGRAM COUNTER

WITH CONTENTS OF

$FFFA, $FFFB

(VECTOR FETCH)

SET BITS S, I, AND X

RESET MCU

HARDWARE

BEGIN INSTRUCTION

SEQUENCE

1A

BIT X IN

CCR = 1?

Y

N

XIRQ

PIN LOW?

Y

STACK CPU

REGISTERS

N

SET BITS I AND X

FETCH VECTOR

$FFF4, $FFF5

2A

Figure 5-5. Processing Flow Out of Reset (Sheet 1 of 2)

Data Sheet

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Interrupts

2A

Y

BIT I IN

CCR = 1?

N

ANY I-BIT

INTERRUPT

PENDING?

Y

STACK CPU

REGISTERS

N

FETCH OPCODE

Y

ILLEGAL

OPCODE?

STACK CPU

REGISTERS

N

SET BIT I IN CCR

WAI

INSTRUCTION?

FETCH VECTOR

$FFF8, $FFF9

Y

STACK CPU

REGISTERS

N

SWI

INSTRUCTION?

Y

ANY

INTERRUPT

PENDING?

STACK CPU

REGISTERS

N

SET BIT I IN CCR

Y

FETCH VECTOR

$FFF6, $FFF7

SET BIT I IN CCR

RTI

INSTRUCTION?

RESOLVE INTERRUPT

PRIORITY AND FETCH

VECTOR FOR HIGHEST

PENDING SOURCE

SEE FIGURE 5–2

N

RESTORE CPU

REGISTERS

FROM STACK

EXECUTE THIS

INSTRUCTION

1A

Figure 5-5. Processing Flow Out of Reset (Sheet 2 of 2)

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BEGIN

X BIT

IN CCR

SET ?

YES

XIRQ PIN

LOW ?

SET X BIT IN CCR

FETCH VECTOR

$FFF4, FFF5

NO

HIGHEST

PRIORITY

INTERRUPT

?

FETCH VECTOR

NO

FETCH VECTOR

$FFF2, FFF3

IRQ ?

NO

YES

REAL-TIME

INTERRUPT

?

FETCH VECTOR

$FFF0, FFF1

RTII = 1 ?

NO

FETCH VECTOR

$FFEE, FFEF

TIMER

IC1F ?

IC1I = 1 ?

NO

FETCH VECTOR

$FFEC, FFED

TIMER

IC2F ?

IC2I = 1 ?

NO

YES

FETCH VECTOR

$FFEA, FFEB

TIMER

IC3F ?

IC3I = 1 ?

NO

FETCH VECTOR

$FFE8, FFE9

TIMER

OC1F ?

OC1I = 1 ?

NO

2A

2B

Figure 5-6. Interrupt Priority Resolution (Sheet 1 of 2)

Data Sheet

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Interrupts

2A

2B

Y

FLAG

OC2F = 1?

FETCH VECTOR

$FFE6, $FFE7

OC2I = 1?

N

Y

FLAG

OC3F = 1

FETCH VECTOR

$FFE4, $FFE5

OC3I = 1?

N

FLAG

OC4F = 1?

FETCH VECTOR

$FFE2, $FFE3

OC4I = 1?

N

Y

FLAG

I4/O5IF = 1?

FETCH VECTOR

$FFE0, $FFE1

I4/O5I = 1?

N

FLAG

TOF = 1?

FETCH VECTOR

$FFDE, $FFDF

TOI = 1?

N

Y

FLAG

PAOVF = 1

FETCH VECTOR

$FFDC, $FFDD

PAOVI = 1?

N

FLAG

PAIF = 1?

FETCH VECTOR

$FFDA, $FFDB

PAII = 1?

N

FLAGS

SPIF = 1? OR

MODF = 1?

Y

FETCH VECTOR

$FFD8, $FFD9

SPIE = 1?

N

SCI

FETCH VECTOR

$FFD6, $FFD7

INTERRUPT?

SEE FIGURE

5–3

FETCH VECTOR

$FFF2, $FFF3

N

END

Figure 5-6. Interrupt Priority Resolution (Sheet 2 of 2)

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Resets and Interrupts

BEGIN

Y

FLAG

RDRF = 1?

N

Y

OR = 1?

N

RIE = 1?

N

RE = 1?

N

Y

TDRE = 1?

N

TE = 1?

N

TIE = 1?

N

TC = 1?

N

TCIE = 1?

N

Y

IDLE = 1?

RE = 1?

N

ILIE = 1?

N

NO

VALID SCI REQUEST

Figure 5-7. Interrupt Source Resolution Within SCI

Data Sheet

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Low-Power Operation

5.6 Low-Power Operation

Both stop mode and wait mode suspend CPU operation until a reset or interrupt

occurs. Wait mode suspends processing and reduces power consumption to an

intermediate level. Stop mode turns off all on-chip clocks and reduces power

consumption to an absolute minimum while retaining the contents of the entire

RAM array.

5.6.1 Wait Mode

The WAI opcode places the MCU in wait mode, during which the CPU registers are

stacked and CPU processing is suspended until a qualified interrupt is detected.

The interrupt can be an external IRQ, an XIRQ, or any of the internally generated

interrupts, such as the timer or serial interrupts. The on-chip crystal oscillator

remains active throughout the wait standby period.

The reduction of power in the wait condition depends on how many internal clock

signals driving on-chip peripheral functions can be shut down. The CPU is always

shut down during wait. While in the wait state, the address/data bus repeatedly

runs read cycles to the address where the CCR contents were stacked. The MCU

leaves the wait state when it senses any interrupt that has not been masked.

The free-running timer system is shut down only if the I bit is set to 1 and the COP

system is disabled by NOCOP being set to 1. Several other systems also can be

in a reduced power-consumption state depending on the state of

software-controlled configuration control bits. Power consumption by the

analog-to-digital (A/D) converter is not affected significantly by the wait condition.

However, the A/D converter current can be eliminated by writing the ADPU bit to 0.

The SPI system is enabled or disabled by the SPE control bit. The SCI transmitter

is enabled or disabled by the TE bit, and the SCI receiver is enabled or disabled by

the RE bit. Therefore, the power consumption in wait is dependent on the particular

application.

5.6.2 Stop Mode

Executing the STOP instruction while the S bit in the CCR is equal to 0 places the

MCU in stop mode. If the S bit is not 0, the stop opcode is treated as a no-op (NOP).

Stop mode offers minimum power consumption because all clocks, including the

crystal oscillator, are stopped while in this mode. To exit stop and resume normal

processing, a logic low level must be applied to one of the external interrupts (IRQ

or XIRQ) or to the RESET pin. A pending edge-triggered IRQ can also bring the

CPU out of stop.

Because all clocks are stopped in this mode, all internal peripheral functions also

stop. The data in the internal RAM is retained as long as V_DDpower is maintained.

The CPU state and I/O pin levels are static and are unchanged by stop. Therefore,

when an interrupt comes to restart the system, the MCU resumes processing as if

there were no interruption. If reset is used to restart the system, a normal reset

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sequence results in which all I/O pins and functions are also restored to their initial

states.

To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must

be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from

stop regardless of the state of the X bit in the CCR, although the recovery sequence

depends on the state of the X bit. If X is set to 0 (XIRQ not masked), the MCU starts

up, beginning with the stacking sequence leading to normal service of the XIRQ

request. If X is set to 1 (XIRQ masked or inhibited), then processing continues with

the instruction that immediately follows the STOP instruction, and no XIRQ

interrupt service is requested or pending.

Because the oscillator is stopped in stop mode, a restart delay may be imposed to

allow oscillator stabilization upon leaving stop. If the internal oscillator is being

used, this delay is required; however, if a stable external oscillator is being used,

the DLY control bit can be used to bypass this startup delay. The DLY control bit is

set by reset and can be optionally cleared during initialization. If the DLY equal to

0 option is used to avoid startup delay on recovery from stop, then reset should not

be used as the means of recovering from stop, as this causes DLY to be set again

by reset, imposing the restart delay. This same delay also applies to power-on

reset, regardless of the state of the DLY control bit, but does not apply to a reset

while the clocks are running.

Data Sheet

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Data Sheet — M68HC11E Family

Section 6. Parallel Input/Output (I/O) Ports

6.1 Introduction

All M68HC11 E-series MCUs have five input/output (I/O) ports and up to 38 I/O

lines, depending on the operating mode. Refer to Table 6-1 for a summary of the

ports and their shared functions.

Table 6-1. Input/Output Ports

Input

Pins

Output

Pins

Bidirectional

Pins

Port

Shared Functions

Port A

Port B

Port C

3

8

2

—

8

Timer

—

High-order address

—

Low-order address and data bus

Serial communications interface (SCI)

and serial peripheral interface (SPI)

Port D

Port E

—

8

—

6

—

Analog-to-digital (A/D) converter

Port pin function is mode dependent. Do not confuse pin function with the electrical

state of the pin at reset. Port pins are either driven to a specified logic level or are

configured as high-impedance inputs. I/O pins configured as high-impedance

inputs have port data that is indeterminate.

In port descriptions, an I indicates this condition. Port pins that are driven to a

known logic level during reset are shown with a value of either 1 or 0. Some control

bits are unaffected by reset. Reset states for these bits are indicated with a U.

6.2 Port A

Port A shares functions with the timer system and has:

•

Three input-only pins

Three output-only pins

Two bidirectional I/O pins

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Parallel Input/Output (I/O) Ports

Address:

$1000

Bit 7

6

5

4

3

2

1

Bit 0

PA0

Read:

Write:

PA7

PA6

PA5

PA4

PA3

PA2

PA1

Reset:

I

0

I

Alternate function:

And/or:

PAI

OC1

OC2

OC1

OC3

OC1

OC4

OC1

IC4/OC5

OC1

IC1

—

IC2

—

IC3

—

I = Indeterminate after reset

Figure 6-1. Port A Data Register (PORTA)

Address:

$1026

Bit 7

DDRA7

0

6

PAEWN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

Read:

Write:

Reset:

Figure 6-2. Pulse Accumulator Control Register (PACTL)

DDRA7 — Data Direction for Port A Bit 7

Overridden if an output compare function is configured to control the PA7 pin

0 = Input

1 = Output

The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also

be used as general-purpose I/O or as an output compare.

NOTE:

Even when port A bit 7 is configured as an output, the pin still drives the input to

the pulse accumulator.

PAEN — Pulse Accumulator System Enable Bit

Refer to Section 9. Timing System.

PAMOD — Pulse Accumulator Mode Bit

Refer to Section 9. Timing System.

PEDGE — Pulse Accumulator Edge Control Bit

Refer to Section 9. Timing System.

DDRA3 — Data Direction for Port A Bit 3

This bit is overridden if an output compare function is configured to control the

PA3 pin.

0 = Input

1 = Output

I4/O5 — Input Capture 4/Output Compare 5 Bit

Refer to Section 9. Timing System.

RTR[1:0] — RTI Interrupt Rate Select Bits

Refer to Section 9. Timing System.

Data Sheet

110

M68HC11E Family — Rev. 5

Parallel Input/Output (I/O) Ports

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Port B

6.3 Port B

In single-chip or bootstrap modes, port B pins are general-purpose outputs. In

expanded or special test modes, port B pins are high-order address outputs.

Address:

$1004

Bit 7

6

5

4

3

2

1

Bit 0

Single-chip or bootstrap modes:

Read:

PB7

0

PB6

PB5

0

PB4

0

PB3

0

PB2

0

PB1

0

PB0

0

Write:

Reset:

0

Expanded or special test modes:

Read:

ADDR15

0

ADDR14

ADDR13

0

ADDR12

0

ADDR11

0

ADDR10

0

ADDR9

0

ADDR8

0

Write:

Reset:

0

Figure 6-3. Port B Data Register (PORTB)

6.4 Port C

In single-chip and bootstrap modes, port C pins reset to high-impedance inputs.

(DDRC bits are set to 0.) In expanded and special test modes, port C pins are

multiplexed address/data bus and the port C register address is treated as an

external memory location.

Address:

$1003

Bit 7

6

5

4

3

2

1

Bit 0

PC0

Single-chip or bootstrap modes:

Read:

PC7

PC6

PC5

PC4

PC3

PC2

PC1

Write:

Reset:

Indeterminate after reset

Expanded or special test modes:

Read:

ADDR7

DATA7

ADDR6

DATA6

ADDR5

DATA5

ADDR4

DATA4

ADDR3

DATA3

ADDR2

DATA2

ADDR1

DATA1

ADDR0

DATA0

Write:

Reset:

Indeterminate after reset

Figure 6-4. Port C Data Register (PORTC)

M68HC11E Family — Rev. 5

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Data Sheet

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Parallel Input/Output (I/O) Ports

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Parallel Input/Output (I/O) Ports

Address:

$1005

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

PCL7

PCL6

PCL5

PCL4

PCL3

PCL2

PCL1

PCL0

Indeterminate after reset

Figure 6-5. Port C Latched Register (PORTCL)

PORTCL is used in the handshake clearing mechanism. When an active edge

occurs on the STRA pin, port C data is latched into the PORTCL register. Reads

of this register return the last value latched into PORTCL and clear STAF flag

(following a read of PIOC with STAF set).

Address:

$1007

Bit 7

6

DDRC6

0

5

DDRC5

0

4

DDRC4

0

3

DDRC3

0

2

DDRC2

0

1

DDRC1

0

Bit 0

DDRC0

0

Read:

Write:

Reset:

DDRC7

0

Figure 6-6. Port C Data Direction Register (DDRC)

DDRC[7:0] — Port C Data Direction Bits

In handshake output mode, DDRC bits select the 3-stated output option

(DDCx = 1).

0 = Input

1 = Output

6.5 Port D

In all modes, port D bits [5:0] can be used either for general-purpose I/O or with the

serial communications interface (SCI) and serial peripheral interface (SPI)

subsystems. During reset, port D pins PD[5:0] are configured as high-impedance

inputs (DDRD bits cleared).

Address:

$1008

Bit 7

6

0

5

PD5

I

4

PD4

I

3

PD3

I

2

PD2

I

1

PD1

I

Bit 0

PD0

I

Read:

Write:

Reset:

0

—

PD5

SS

PD4

SCK

PD3

MOSI

PD2

MISO

PD1

Tx

PD0

RxD

Alternate Function:

I = Indeterminate after reset

Figure 6-7. Port D Data Register (PORTD)

Data Sheet

112

M68HC11E Family — Rev. 5

MOTOROLA

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Port E

Address:

$1009

Bit 7

6

0

5

DDRD5

0

4

DDRD4

0

3

DDRD3

0

2

DDRD2

0

1

DDRD1

0

Bit 0

Read:

Write:

Reset:

DDRD0

0

= Unimplemented

Figure 6-8. Port D Data Direction Register (DDRD)

Bits [7:6] — Unimplemented

Always read 0

DDRD[5:0] — Port D Data Direction Bits

When DDRD bit 5 is 1 and MSTR = 1 in SPCR, PD5/SS is a general-purpose

output and mode fault logic is disabled.

0 = Input

1 = Output

6.6 Port E

Port E is used for general-purpose static inputs or pins that share functions with the

analog-to-digital (A/D) converter system. When some port E pins are being used

for general-purpose input and others are being used as A/D inputs, PORTE should

not be read during the sample portion of an A/D conversion.

Address:

$100A

Bit 7

6

5

4

3

2

1

Bit 0

PE0

Read:

Write:

PE7

PE6

PE5

PE4

PE3

PE2

PE1

Reset:

Indeterminate after reset

AN4 AN3

Alternate Function:

AN7

AN6

AN5

AN2

AN1

AN0

Figure 6-9. Port E Data Register (PORTE)

6.7 Handshake Protocol

Simple and full handshake input and output functions are available on ports B and

C pins in single-chip mode. In simple strobed mode, port B is a strobed output port

and port C is a latching input port. The two activities are available simultaneously.

The STRB output is pulsed for two E-clock periods each time there is a write to the

PORTB register. The INVB bit in the PIOC register controls the polarity of STRB

pulses. Port C levels are latched into the alternate port C latch (PORTCL) register

on each assertion of the STRA input. STRA edge select, flag, and interrupt enable

bits are located in the PIOC register. Any or all of the port C lines can still be used

as general-purpose I/O while in strobed input mode.

M68HC11E Family — Rev. 5

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Data Sheet

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Parallel Input/Output (I/O) Ports

Full handshake modes use port C pins and the STRA and STRB lines. Input and

output handshake modes are supported, and output handshake mode has a

3-stated variation. STRA is an edge-detecting input and STRB is a handshake

output. Control and enable bits are located in the PIOC register.

In full input handshake mode, the MCU asserts STRB to signal an external system

that it is ready to latch data. Port C logic levels are latched into PORTCL when the

STRA line is asserted by the external system. The MCU then negates STRB. The

MCU reasserts STRB after the PORTCL register is read. In this mode, a mix of

latched inputs, static inputs, and static outputs is allowed on port C, differentiated

by the data direction bits and use of the PORTC and PORTCL registers.

In full output handshake mode, the MCU writes data to PORTCL which, in turn,

asserts the STRB output to indicate that data is ready. The external system reads

port C data and asserts the STRA input to acknowledge that data has been

received.

In the 3-state variation of output handshake mode, lines intended as 3-state

handshake outputs are configured as inputs by clearing the corresponding DDRC

bits. The MCU writes data to PORTCL and asserts STRB. The external system

responds by activating the STRA input, which forces the MCU to drive the data in

PORTC out on all of the port C lines. After the trailing edge of the active signal on

STRA, the MCU negates the STRB signal. The 3-state mode variation does not

allow part of port C to be used for static inputs while other port C pins are being

used for handshake outputs. Refer to the 6.8 Parallel I/O Control Register for

further information.

6.8 Parallel I/O Control Register

The parallel handshake functions are available only in the single-chip operating

mode. PIOC is a read/write register except for bit 7, which is read only. Table 6-2

shows a summary of handshake operations.

Table 6-2. Parallel I/O Control

STAF

Clearing

Sequence

HNDS OIN

PLS

EGA

Port B

Port C

Read

Inputs latched into

PORTCL on any

active edge on

STRA

Simple

strobed

mode

PIOC with

STAF = 1

then read

PORTCL

STRB pulses

on writes

to PORTB

0

1

0

1

X

0

X

Read

Full-input

hand-

shake

0 = STRB

active level

1 = STRB

active pulse

Inputs latched into Normal output

PIOC with

STAF = 1

then read

PORTCL

1

0

PORTCL on any

active edge on

STRA

port, unaffected

in handshake

modes

mode

Data Sheet

114

M68HC11E Family — Rev. 5

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Parallel Input/Output (I/O) Ports

Parallel I/O Control Register

Table 6-2. Parallel I/O Control (Continued)

STAF

Clearing

Sequence

HNDS OIN

PLS

EGA

Port B

Port C

Driven as outputs if

STRA at active

level; follows

DDRC

if STRA not at

active level

Full-

Read

0 = STRB

active level

1 = STRB

active pulse

0

1

Normal output

port, unaffected

in handshake

modes

output

hand-

shake

mode

PIOC with

STAF = 1

then write

PORTCL

Port C

Driven

1

STRA

Active Edge

Follow

DDRC

Follow

DDRC

Address:

$1002

Bit 7

STAF

0

6

STAI

0

5

CWOM

0

4

HNDS

0

3

2

PLS

U

1

EGA

1

Bit 0

INVB

1

Read:

Write:

Reset:

OIN

0

U = Unaffected

Figure 6-10. Parallel I/O Control Register (PIOC)

STAF — Strobe A Interrupt Status Flag

STAF is set when the selected edge occurs on strobe A. This bit can be cleared

by a read of PIOC with STAF set followed by a read of PORTCL (simple strobed

or full input handshake mode) or a write to PORTCL (output handshake mode).

0 = No edge on strobe A

1 = Selected edge on strobe A

STAI — Strobe A Interrupt Enable Mask Bit

0 = STAF does not request interrupt

1 = STAF requests interrupt

CWOM — Port C Wired-OR Mode Bit (affects all eight port C pins)

It is customary to have an external pullup resistor on lines that are driven by

open-drain devices.

0 = Port C outputs are normal CMOS outputs.

1 = Port C outputs are open-drain outputs.

HNDS — Handshake Mode Bit

0 = Simple strobe mode

1 = Full input or output handshake mode

OIN — Output or Input Handshake Select Bit

HNDS must be set to 1 for this bit to have meaning.

0 = Input handshake

1 = Output handshake

M68HC11E Family — Rev. 5

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Data Sheet

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Parallel Input/Output (I/O) Ports

PLS — Pulsed/Interlocked Handshake Operation Bit

HNDS must be set to 1 for this bit to have meaning. When interlocked

handshake is selected, strobe B is active until the selected edge of strobe A is

detected.

0 = Interlocked handshake

1 = Pulsed handshake (Strobe B pulses high for two E-clock cycles.)

EGA — Active Edge for Strobe A Bit

0 = STRA falling edge selected, high level activates port C outputs (output

handshake)

1 = STRA rising edge selected, low level activates port C outputs (output

handshake)

INVB — Invert Strobe B Bit

0 = Active level is logic 0.

1 = Active level is logic 1.

Data Sheet

116

M68HC11E Family — Rev. 5

Parallel Input/Output (I/O) Ports

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Data Sheet — M68HC11E Family

Section 7. Serial Communications Interface (SCI)

7.1 Introduction

The serial communications interface (SCI) is a universal asynchronous receiver

transmitter (UART), one of two independent serial input/output (I/O) subsystems in

the M68HC11 E series of microcontrollers. It has a standard non-return-to-zero

(NRZ) format (one start bit , eight or nine data bits, and one stop bit). Several baud

rates are available. The SCI transmitter and receiver are independent, but use the

same data format and bit rate.

All members of the E series contain the same SCI, with one exception. The SCI

system in the MC68HC11E20 and MC68HC711E20 MCUs have an enhanced SCI

baud rate generator. A divide-by-39 stage has been added that is enabled by an

extra bit in the BAUD register. This increases the available SCI baud rate

selections. Refer to Figure 7-8 and 7.7.5 Baud Rate Register.

7.2 Data Format

The serial data format requires these conditions:

1. An idle line in the high state before transmission or reception of a message

2. A start bit, logic 0, transmitted or received, that indicates the start of each

character

3. Data that is transmitted and received least significant bit (LSB) first

4. A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a

start bit, a character of eight or nine data bits, and a stop bit.

5. A break, defined as the transmission or reception of a logic 0 for some

multiple number of frames

Selection of the word length is controlled by the M bit of SCI control register

(SCCR1).

7.3 Transmit Operation

The SCI transmitter includes a parallel transmit data register (SCDR) and a serial

shift register. The contents of the serial shift register can be written only through

the SCDR. This double buffered operation allows a character to be shifted out

serially while another character is waiting in the SCDR to be transferred into the

M68HC11E Family — Rev. 5

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Data Sheet

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Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

serial shift register. The output of the serial shift register is applied to TxD as long

as transmission is in progress or the transmit enable (TE) bit of serial

communication control register 2 (SCCR2) is set. The block diagram, Figure 7-1,

shows the transmit serial shift register and the buffer logic at the top of the figure.

WRITE ONLY

TRANSMITTER

BAUD RATE

CLOCK

SCDR Tx BUFFER

DDD1

10 (11) - BIT Tx SHIFT REGISTER

(8) 7 L

SEE NOTE

PD1

TxD

PIN BUFFER

AND CONTROL

H

6

5

4

3

2

1

0

8

FORCE PIN

DIRECTION (OUT)

TRANSMITTER

CONTROL LOGIC

8

SCSR

INTERRUPT STATUS

SCCR1 SCI CONTROL 1

8

TDRE

TIE

TC

TCIE

SCCR2 SCI CONTROL 2

SCI Rx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting TxD to a PC.

Figure 7-1. SCI Transmitter Block Diagram

Data Sheet

118

M68HC11E Family — Rev. 5

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Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

Receive Operation

7.4 Receive Operation

During receive operations, the transmit sequence is reversed. The serial shift

register receives data and transfers it to a parallel receive data register (SCDR) as

a complete word. This double buffered operation allows a character to be shifted

in serially while another character is already in the SCDR. An advanced data

recovery scheme distinguishes valid data from noise in the serial data stream. The

data input is selectively sampled to detect receive data, and a majority voting circuit

determines the value and integrity of each bit. See Figure 7-2.

7.5 Wakeup Feature

The wakeup feature reduces SCI service overhead in multiple receiver systems.

Software for each receiver evaluates the first character of each message. The

receiver is placed in wakeup mode by writing a 1 to the RWU bit in the SCCR2

register. While RWU is 1, all of the receiver-related status flags (RDRF, IDLE, OR,

NF, and FE) are inhibited (cannot become set). Although RWU can be cleared by

a software write to SCCR2, to do so would be unusual. Normally, RWU is set by

software and is cleared automatically with hardware. Whenever a new message

begins, logic alerts the sleeping receivers to wake up and evaluate the initial

character of the new message.

Two methods of wakeup are available:

•

Idle-line wakeup

Address-mark wakeup

During idle-line wakeup, a sleeping receiver awakens as soon as the RxD line

becomes idle. In the address-mark wakeup, logic 1 in the most significant bit (MSB)

of a character wakes up all sleeping receivers.

7.5.1 Idle-Line Wakeup

To use the receiver wakeup method, establish a software addressing scheme to

allow the transmitting devices to direct a message to individual receivers or to

groups of receivers. This addressing scheme can take any form as long as all

transmitting and receiving devices are programmed to understand the same

scheme. Because the addressing information is usually the first frame(s) in a

message, receivers that are not part of the current task do not become burdened

with the entire set of addressing frames. All receivers are awake (RWU = 0) when

each message begins. As soon as a receiver determines that the message is not

intended for it, software sets the RWU bit (RWU = 1), which inhibits further flag

setting until the RxD line goes idle at the end of the message. As soon as an idle

line is detected by receiver logic, hardware automatically clears the RWU bit so that

the first frame of the next message can be received. This type of receiver wakeup

requires a minimum of one idle-line frame time between messages and no idle time

between frames in a message.

M68HC11E Family — Rev. 5

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Data Sheet

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Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

RECEIVER

BAUD RATE

CLOCK

DDD0

÷16

10 (11) - BIT

Rx SHIFT REGISTER

SEE NOTE

PIN BUFFER

AND CONTROL

DATA

RECOVERY

PD0

RxD

(8)

7

6

5

4

3

2

1

0

MSB

ALL 1s

DISABLE

DRIVER

RE

M

WAKEUP

LOGIC

RWU

8

SCCR1 SCI CONTROL 1

SCSR SCI STATUS 1

SCDR Rx BUFFER

READ ONLY

8

RDRF

RIE

IDLE

ILIE

OR

RIE

8

SCCR2 SCI CONTROL 2

SCI Tx

REQUESTS

SCI INTERRUPT

REQUEST

INTERNAL

DATA BUS

Note: Refer to Figure B-1. EVBU Schematic Diagram for an example of connecting RxD to a PC.

Figure 7-2. SCI Receiver Block Diagram

Data Sheet

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Serial Communications Interface (SCI)

SCI Error Detection

7.5.2 Address-Mark Wakeup

The serial characters in this type of wakeup consist of seven (eight if M = 1)

information bits and an MSB, which indicates an address character (when set to 1,

or mark). The first character of each message is an addressing character (MSB =

1). All receivers in the system evaluate this character to determine if the remainder

of the message is directed toward this particular receiver. As soon as a receiver

determines that a message is not intended for it, the receiver activates the RWU

function by using a software write to set the RWU bit. Because setting RWU inhibits

receiver-related flags, there is no further software overhead for the rest of this

message.

When the next message begins, its first character has its MSB set, which

automatically clears the RWU bit and enables normal character reception. The first

character whose MSB is set is also the first character to be received after wakeup

because RWU gets cleared before the stop bit for that frame is serially received.

This type of wakeup allows messages to include gaps of idle time, unlike the

idle-line method, but there is a loss of efficiency because of the extra bit time for

each character (address bit) required for all characters.

7.6 SCI Error Detection

Three error conditions – SCDR overrun, received bit noise, and framing – can

occur during generation of SCI system interrupts. Three bits (OR, NF, and FE) in

the serial communications status register (SCSR) indicate if one of these error

conditions exists.

The overrun error (OR) bit is set when the next byte is ready to be transferred from

the receive shift register to the SCDR and the SCDR is already full (RDRF bit is

set). When an overrun error occurs, the data that caused the overrun is lost and

the data that was already in SCDR is not disturbed. The OR is cleared when the

SCSR is read (with OR set), followed by a read of the SCDR.

The noise flag (NF) bit is set if there is noise on any of the received bits, including

the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit

is cleared when the SCSR is read (with FE equal to 1) followed by a read of the

SCDR.

When no stop bit is detected in the received data character, the framing error (FE)

bit is set. FE is set at the same time as the RDRF. If the byte received causes both

framing and overrun errors, the processor only recognizes the overrun error. The

framing error flag inhibits further transfer of data into the SCDR until it is cleared.

The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read

of the SCDR.

M68HC11E Family — Rev. 5

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Data Sheet

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Serial Communications Interface (SCI)

7.7 SCI Registers

Five addressable registers are associated with the SCI:

•

Four control and status registers:

–

Serial communications control register 1 (SCCR1)

Serial communications control register 2 (SCCR2)

Baud rate register (BAUD)

Serial communications status register (SCSR)

•

One data register:

Serial communications data register (SCDR)

–

The SCI registers are the same for all M68HC11 E-series devices with one

exception. The SCI system for MC68HC(7)11E20 contains an extra bit in the

BAUD register that provides a greater selection of baud prescaler rates. Refer to

7.7.5 Baud Rate Register, Figure 7-8, and Figure 7-9.

7.7.1 Serial Communications Data Register

SCDR is a parallel register that performs two functions:

•

The receive data register when it is read

The transmit data register when it is written

Reads access the receive data buffer and writes access the transmit data buffer.

Receive and transmit are double buffered.

Address:

$102F

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

R7/T7

R6/T6

R5/T5

R4/T4

R3/T3

R2/T2

R1/T1

R0/T0

Indeterminate after reset

Figure 7-3. Serial Communications Data Register (SCDR)

Data Sheet

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Serial Communications Interface (SCI)

SCI Registers

7.7.2 Serial Communications Control Register 1

The SCCR1 register provides the control bits that determine word length and select

the method used for the wakeup feature.

Address:

$102C

Bit 7

6

T8

I

5

0

4

M

0

3

WAKE

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

R8

I

0

I = Indeterminate after reset

= Unimplemented

Figure 7-4. Serial Communications Control Register 1 (SCCR1)

R8 — Receive Data Bit 8

If M bit is set, R8 stores the ninth bit in the receive data character.

T8 — Transmit Data Bit 8

If M bit is set, T8 stores the ninth bit in the transmit data character.

Bit 5 — Unimplemented

Always reads 0

M — Mode Bit (select character format)

0 = Start bit, 8 data bits, 1 stop bit

1 = Start bit, 9 data bits, 1 stop bit

WAKE — Wakeup by Address Mark/Idle Bit

0 = Wakeup by IDLE line recognition

1 = Wakeup by address mark (most significant data bit set)

Bits [2:0] — Unimplemented

Always read 0

M68HC11E Family — Rev. 5

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Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

7.7.3 Serial Communications Control Register 2

The SCCR2 register provides the control bits that enable or disable individual SCI

functions.

Address:

$102D

Bit 7

6

TCIE

0

5

RIE

0

4

ILIE

0

3

TE

0

2

RE

0

1

RWU

0

Bit 0

SBK

0

Read:

Write:

Reset:

TIE

0

Figure 7-5. Serial Communications Control Register 2 (SCCR2)

TIE — Transmit Interrupt Enable Bit

0 = TDRE interrupts disabled

1 = SCI interrupt requested when TDRE status flag is set

TCIE — Transmit Complete Interrupt Enable Bit

0 = TC interrupts disabled

1 = SCI interrupt requested when TC status flag is set

RIE — Receiver Interrupt Enable Bit

0 = RDRF and OR interrupts disabled

1 = SCI interrupt requested when RDRF flag or the OR status flag is set

ILIE — Idle-Line Interrupt Enable Bit

0 = IDLE interrupts disabled

1 = SCI interrupt requested when IDLE status flag is set

TE — Transmitter Enable Bit

When TE goes from 0 to 1, one unit of idle character time (logic 1) is queued as

a preamble.

0 = Transmitter disabled

1 = Transmitter enabled

RE — Receiver Enable Bit

0 = Receiver disabled

1 = Receiver enabled

RWU — Receiver Wakeup Control Bit

0 = Normal SCI receiver

1 = Wakeup enabled and receiver interrupts inhibited

SBK — Send Break

At least one character time of break is queued and sent each time SBK is written

to 1. As long as the SBK bit is set, break characters are queued and sent. More

than one break may be sent if the transmitter is idle at the time the SBK bit is

toggled on and off, as the baud rate clock edge could occur between writing

the 1 and writing the 0 to SBK.

0 = Break generator off

1 = Break codes generated

Data Sheet

124

M68HC11E Family — Rev. 5

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

SCI Registers

7.7.4 Serial Communication Status Register

The SCSR provides inputs to the interrupt logic circuits for generation of the SCI

system interrupt.

Address:

$102E

Bit 7

6

TC

1

5

RDRF

0

4

IDLE

0

3

OR

0

2

NF

0

1

FE

0

Bit 0

Read:

Write:

Reset:

TDRE

1

0

= Unimplemented

Figure 7-6. Serial Communications Status Register (SCSR)

TDRE — Transmit Data Register Empty Flag

This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with

TDRE set and then writing to SCDR.

0 = SCDR busy

0 = SCDR empty

TC — Transmit Complete Flag

This flag is set when the transmitter is idle (no data, preamble, or break

transmission in progress). Clear the TC flag by reading SCSR with TC set and

then writing to SCDR.

0 = Transmitter busy

1 = Transmitter idle

RDRF — Receive Data Register Full Flag

This flag is set if a received character is ready to be read from SCDR. Clear the

RDRF flag by reading SCSR with RDRF set and then reading SCDR.

0 = SCDR empty

1 = SCDR full

IDLE — Idle Line Detected Flag

This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until

the RxD line has been active and becomes idle again. The IDLE flag is inhibited

when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading

SCDR.

0 = RxD line active

1 = RxD line idle

OR — Overrun Error Flag

OR is set if a new character is received before a previously received character

is read from SCDR. Clear the OR flag by reading SCSR with OR set and then

reading SCDR.

0 = No overrun

1 = Overrun detected

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Serial Communications Interface (SCI)

NF — Noise Error Flag

NF is set if majority sample logic detects anything other than a unanimous

decision. Clear NF by reading SCSR with NF set and then reading SCDR.

0 = Unanimous decision

1 = Noise detected

FE — Framing Error Flag

FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag

by reading SCSR with FE set and then reading SCDR.

0 = Stop bit detected

1 = Zero detected

Bit 0 — Unimplemented

Always reads 0

7.7.5 Baud Rate Register

Use this register to select different baud rates for the SCI system. The SCP[1:0]

(SCP[2:0] in MC68HC(7)11E20) bits function as a prescaler for the SCR[2:0] bits.

Together, these five bits provide multiple baud rate combinations for a given crystal

frequency. Normally, this register is written once during initialization. The prescaler

is set to its fastest rate by default out of reset and can be changed at any time.

Refer to Table 7-1 for normal baud rate selections.

Address:

$102B

Bit 7

6

SCP2

0

5

SCP1

0

4

SCP0

0

3

RCKB

0

2

SCR2

U

1

SCR1

U

Bit 0

SCR0

U

Read:

Write:

Reset:

TCLR

0

U = Unaffected

Figure 7-7. Baud Rate Register (BAUD)

TCLR — Clear Baud Rate Counter Bit (Test)

SCP[2:0] — SCI Baud Rate Prescaler Select Bits

NOTE:

SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must equal 0s.

Any other values for SCP[1:0] are not decoded in the prescaler and the results are

unpredictable. Refer to Figure 7-8 and Figure 7-9.

RCKB — SCI Baud Rate Clock Check Bit (Test)

Data Sheet

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M68HC11E Family — Rev. 5

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

SCI Registers

Table 7-1. Baud Rate Values

Crystal Frequency (MHz)

Baud

4.00 4.9152

Prescale

8.00

Bus Frequency (MHz)

2.00 2.50 3.00

10.00

12.00

16.00

4.00

Set

Divide

Prescaler Selects

Divide

SCP2 SCP1 SCP0 SCR2 SCR1 SCR0

1.00

1.23

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

62500 76800 125000 156250 187500 250000

31250 38400 62500

15625 19200 31250

78125

39063

19531

9766

93750

46875

23438

11719

5859

125000

62500

31250

15625

7813

8

7813

3906

1953

977

9600

4800

2400

1200

600

15625

7813

3906

1953

977

16

32

64

128

4883

2441

2930

3906

488

1221

1465

1953

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

1

2

4

20833 25600 41667

10417 12800 20833

52083

26042

13021

6510

3255

1628

814

62500

31250

15625

7813

3906

1953

977

83333

41667

20833

10417

5208

2604

1302

651

5208

2604

1302

651

6400

3200

1600

800

10417

5208

2604

1302

651

8

16

32

64

128

326

400

163

200

326

407

488

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

1

2

4

15625 19200 31250

39063

19531

9766

4883

2441

1221

610

46875

23438

11719

5859

2930

1465

732

62500

31250

15625

7813

3906

1953

977

7813

3906

1953

977

9600

4800

2400

1200

600

15625

7813

3906

1953

977

8

16

32

64

128

488

244

300

488

122

150

244

305

366

488

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

13

1

2

4

4808

2404

1202

601

300

150

75

5908

2954

1477

738

369

185

92

9615

4808

2404

1202

601

300

150

75

12019

6010

3005

1502

751

376

188

94

14423

7212

3606

1803

901

451

225

113

19231

9615

4808

2404

1202

601

8

16

32

64

128

300

150

38

46

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

39

1

2

4

1603

801

401

200

100

50

1969

985

492

246

123

62

3205

1603

801

401

200

100

50

4006

2003

1002

501

250

125

63

4808

2404

1202

601

300

150

75

6410

3205

1603

801

401

200

100

50

8

16

32

64

128

25

13

31

15

25

31

38

Shaded areas reflect standard baud rates.

On MC68HC(7)11E20 do not set SCP1 or SCP0 when SCP2 is 1.

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Serial Communications Interface (SCI)

SCR[2:0] — SCI Baud Rate Select Bits

Selects receiver and transmitter bit rate based on output from baud rate

prescaler stage. Refer to Figure 7-8 and Figure 7-9.

The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0]

bits select an additional binary submultiple (÷1, ÷2, ÷4, through ÷128) of this

highest baud rate. The result of these two dividers in series is the 16X receiver

baud rate clock. The SCR[2:0] bits are not affected by reset and can be changed

at any time, although they should not be changed when any SCI transfer is in

progress.

Figure 7-8 and Figure 7-9 illustrate the SCI baud rate timing chain. The

prescaler select bits determine the highest baud rate. The rate select bits

determine additional divide by two stages to arrive at the receiver timing (RT)

clock rate. The baud rate clock is the result of dividing the RT clock by 16.

EXTAL

OSCILLATOR

INTERNAL BUS CLOCK (PH2)

AND

CLOCK GENERATOR

(÷4)

XTAL

÷ 3

÷ 4

÷ 13

SCP[1:0]

1:1

E

0:0

0:1

1:0

AS

SCR[2:0]

0:0:0

0:0:1

÷ 2

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 16

SCI

TRANSMIT

BAUD RATE

(1X)

SCI

RECEIVE

BAUD RATE

(16X)

Figure 7-8. SCI Baud Rate Generator Block Diagram

Data Sheet

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Serial Communications Interface (SCI)

Status Flags and Interrupts

EXTAL

XTAL

OSCILLATOR

AND

CLOCK GENERATOR

(÷4)

INTERNAL BUS CLOCK (PH2)

÷ 3

÷ 4

÷ 13

÷ 39

SCP[2:0]*

1:0:0

E

0:0:0

0:0:1

0:1:0

0:1:1

AS

SCR[2:0]

0:0:0

0:0:1

÷ 2

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 16

SCI

TRANSMIT

BAUD RATE

(1X)

SCI

RECEIVE

BAUD RATE

(16X)

*SCP2 is present only on MC68HC(7)11E20.

Figure 7-9. MC68HC(7)11E20 SCI Baud Rate

Generator Block Diagram

7.8 Status Flags and Interrupts

The SCI transmitter has two status flags. These status flags can be read by

software (polled) to tell when the corresponding condition exists. Alternatively, a

local interrupt enable bit can be set to enable each of these status conditions to

generate interrupt requests when the corresponding condition is present. Status

flags are automatically set by hardware logic conditions, but must be cleared by

software, which provides an interlock mechanism that enables logic to know when

software has noticed the status indication. The software clearing sequence for

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Serial Communications Interface (SCI)

these flags is automatic. Functions that are normally performed in response to the

status flags also satisfy the conditions of the clearing sequence.

TDRE and TC flags are normally set when the transmitter is first enabled (TE set

to 1). The TDRE flag indicates there is room in the transmit queue to store another

data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When

TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an interrupt is

requested.

The TC flag indicates the transmitter has completed the queue. The TCIE bit is the

local interrupt mask for TC. When TCIE is 0, TC must be polled. When TCIE is 1

and TC is 1, an interrupt is requested.

Writing a 0 to TE requests that the transmitter stop when it can. The transmitter

completes any transmission in progress before actually shutting down. Only an

MCU reset can cause the transmitter to stop and shut down immediately. If TE is

written to 0 when the transmitter is already idle, the pin reverts to its

general-purpose I/O function (synchronized to the bit-rate clock). If anything is

being transmitted when TE is written to 0, that character is completed before the

pin reverts to general-purpose I/O, but any other characters waiting in the transmit

queue are lost. The TC and TDRE flags are set at the completion of this last

character, even though TE has been disabled.

7.9 Receiver Flags

The SCI receiver has five status flags, three of which can generate interrupt

requests. The status flags are set by the SCI logic in response to specific conditions

in the receiver. These flags can be read (polled) at any time by software. Refer to

Figure 7-10, which shows SCI interrupt arbitration.

When an overrun takes place, the new character is lost, and the character that was

in its way in the parallel RDR is undisturbed. RDRF is set when a character has

been received and transferred into the parallel RDR. The OR flag is set instead of

RDRF if overrun occurs. A new character is ready to be transferred into RDR

before a previous character is read from RDR.

The NF and FE flags provide additional information about the character in the RDR,

but do not generate interrupt requests.

The last receiver status flag and interrupt source come from the IDLE flag. The RxD

line is idle if it has constantly been at logic 1 for a full character time. The IDLE flag

is set only after the RxD line has been busy and becomes idle, which prevents

repeated interrupts for the whole time RxD remains idle.

Data Sheet

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Serial Communications Interface (SCI)

Receiver Flags

BEGIN

Y

FLAG

RDRF = 1?

N

Y

OR = 1?

N

RIE = 1?

N

RE = 1?

N

Y

TDRE = 1?

N

TE = 1?

N

TIE = 1?

N

TC = 1?

N

TCIE = 1?

N

Y

IDLE = 1?

RE = 1?

N

ILIE = 1?

N

NO

VALID SCI REQUEST

Figure 7-10. Interrupt Source Resolution Within SCI

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Data Sheet

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Data Sheet — M68HC11E Family

Section 8. Serial Peripheral Interface (SPI)

8.1 Introduction

The serial peripheral interface (SPI), an independent serial communications

subsystem, allows the MCU to communicate synchronously with peripheral

devices, such as:

•

Frequency synthesizers

Liquid crystal display (LCD) drivers

Analog-to-digital (A/D) converter subsystems

Other microprocessors

The SPI is also capable of inter-processor communication in a multiple master

system. The SPI system can be configured as either a master or a slave device.

When configured as a master, data transfer rates can be as high as one-half the

E-clock rate (1.5 Mbits per second for a 3-MHz bus frequency). When configured

as a slave, data transfers can be as fast as the E-clock rate (3 Mbits per second for

a 3-MHz bus frequency).

8.2 Functional Description

The central element in the SPI system is the block containing the shift register and

the read data buffer. The system is single buffered in the transmit direction and

double buffered in the receive direction. This means that new data for transmission

cannot be written to the shifter until the previous transfer is complete; however,

received data is transferred into a parallel read data buffer so the shifter is free to

accept a second serial character. As long as the first character is read out of the

read data buffer before the next serial character is ready to be transferred, no

overrun condition occurs. A single MCU register address is used for reading data

from the read data buffer and for writing data to the shifter.

The SPI status block represents the SPI status functions (transfer complete, write

collision, and mode fault) performed by the serial peripheral status register (SPSR).

The SPI control block represents those functions that control the SPI system

through the serial peripheral control register (SPCR).

Refer to Figure 8-1, which shows the SPI block diagram.

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Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

S

MISO

PD2

INTERNAL

MCU CLOCK

M

MSB

LSB

M

S

MOSI

PD3

8--BIT SHIFT REGISTER

DIVIDER

READ DATA BUFFER

÷2 ÷4 ÷16 ÷32

CLOCK

LOGIC

SELECT

S

SCK

PD4

M

SS

PD5

MSTR

SPE

SPI CONTROL

SPI STATUS REGISTER

SPI CONTROL REGISTER

SPI INTERRUPT

REQUEST

INTERNAL

DATA BUS

Figure 8-1. SPI Block Diagram

8.3 SPI Transfer Formats

During an SPI transfer, data is simultaneously transmitted and received. A serial

clock line synchronizes shifting and sampling of the information on the two serial

data lines. A slave select line allows individual selection of a slave SPI device;

slave devices that are not selected do not interfere with SPI bus activities. On a

master SPI device, the select line can optionally be used to indicate a multiple

master bus contention. Refer to Figure 8-2.

Data Sheet

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Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

Clock Phase and Polarity Controls

SCK CYCLE #

1

2

3

4

5

6

7

8

SCK (CPOL = 0)

SCK (CPOL = 1)

SAMPLE INPUT

MSB

6

5

4

3

2

1

LSB

(CPHA = 0)

DATA OUT

SAMPLE INPUT

(CPHA = 1) DATA OUT

SS (TO SLAVE)

MSB

6

5

4

3

2

1

LSB

SLAVE CPHA = 1 TRANSFER IN PROGRESS

MASTER TRANSFER IN PROGRESS

3

2

4

SLAVE CPHA = 0 TRANSFER IN PROGRESS

1

5

1. SS ASSERTED

2. MASTER WRITES TO SPDR

3. FIRST SCK EDGE

4. SPIF SET

5. SS NEGATED

Figure 8-2. SPI Transfer Format

8.4 Clock Phase and Polarity Controls

Software can select one of four combinations of serial clock phase and polarity

using two bits in the SPI control register (SPCR). The clock polarity is specified by

the CPOL control bit, which selects an active high or active low clock, and has no

significant effect on the transfer format. The clock phase (CPHA) control bit selects

one of two different transfer formats. The clock phase and polarity should be

identical for the master SPI device and the communicating slave device. In some

cases, the phase and polarity are changed between transfers to allow a master

device to communicate with peripheral slaves having different requirements.

When CPHA equals 0, the SS line must be negated and reasserted between each

successive serial byte. Also, if the slave writes data to the SPI data register (SPDR)

while SS is low, a write collision error results.

When CPHA equals 1, the SS line can remain low between successive transfers.

8.5 SPI Signals

This subsection contains descriptions of the four SPI signals:

•

Master in/slave out (MISO)

Master out/slave in (MOSI)

Serial clock (SCK)

Slave select (SS)

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Serial Peripheral Interface (SPI)

Any SPI output line must have its corresponding data direction bit in DDRD register

set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes

a general-purpose input. All SPI input lines are forced to act as inputs regardless

of the state of the corresponding DDR bits in DDRD register.

8.5.1 Master In/Slave Out

MISO is one of two unidirectional serial data signals. It is an input to a master

device and an output from a slave device. The MISO line of a slave device is placed

in the high-impedance state if the slave device is not selected.

8.5.2 Master Out/Slave In

The MOSI line is the second of the two unidirectional serial data signals. It is an

output from a master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge that the slave

device uses to latch the data.

8.5.3 Serial Clock

SCK, an input to a slave device, is generated by the master device and

synchronizes data movement in and out of the device through the MOSI and MISO

lines. Master and slave devices are capable of exchanging a byte of information

during a sequence of eight clock cycles.

Four possible timing relationships can be chosen by using control bits CPOL and

CPHA in the serial peripheral control register (SPCR). Both master and slave

devices must operate with the same timing. The SPI clock rate select bits,

SPR[1:0], in the SPCR of the master device, select the clock rate. In a slave device,

SPR[1:0] have no effect on the operation of the SPI.

8.5.4 Slave Select

The slave select (SS) input of a slave device must be externally asserted before a

master device can exchange data with the slave device. SS must be low before

data transactions and must stay low for the duration of the transaction.

The SS line of the master must be held high. If it goes low, a mode fault error flag

(MODF) is set in the serial peripheral status register (SPSR). To disable the mode

fault circuit, write a 1 in bit 5 of the port D data direction register. This sets the SS

pin to act as a general-purpose output rather than the dedicated input to the slave

select circuit, thus inhibiting the mode fault flag. The other three lines are dedicated

to the SPI whenever the serial peripheral interface is on.

The state of the master and slave CPHA bits affects the operation of SS. CPHA

settings should be identical for master and slave. When CPHA = 0, the shift clock

is the OR of SS with SCK. In this clock phase mode, SS must go high between

successive characters in an SPI message. When CPHA = 1, SS can be left low

Data Sheet

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Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

SPI System Errors

between successive SPI characters. In cases where there is only one SPI slave

MCU, its SS line can be tied to V_SSas long as only CPHA = 1 clock mode is used.

8.6 SPI System Errors

Two system errors can be detected by the SPI system. The first type of error arises

in a multiple-master system when more than one SPI device simultaneously tries

to be a master. This error is called a mode fault. The second type of error, write

collision, indicates that an attempt was made to write data to the SPDR while a

transfer was in progress.

When the SPI system is configured as a master and the SS input line goes to active

low, a mode fault error has occurred — usually because two devices have

attempted to act as master at the same time. In cases where more than one device

is concurrently configured as a master, there is a chance of contention between

two pin drivers. For push-pull CMOS drivers, this contention can cause permanent

damage. The mode fault mechanism attempts to protect the device by disabling the

drivers. The MSTR control bit in the SPCR and all four DDRD control bits

associated with the SPI are cleared and an interrupt is generated subject to

masking by the SPIE control bit and the I bit in the CCR.

Other precautions may need to be taken to prevent driver damage. If two devices

are made masters at the same time, mode fault does not help protect either one

unless one of them selects the other as slave. The amount of damage possible

depends on the length of time both devices attempt to act as master.

A write collision error occurs if the SPDR is written while a transfer is in progress.

Because the SPDR is not double buffered in the transmit direction, writes to SPDR

cause data to be written directly into the SPI shift register. Because this write

corrupts any transfer in progress, a write collision error is generated. The transfer

continues undisturbed, and the write data that caused the error is not written to the

shifter.

A write collision is normally a slave error because a slave has no control over when

a master initiates a transfer. A master knows when a transfer is in progress, so

there is no reason for a master to generate a write-collision error, although the SPI

logic can detect write collisions in both master and slave devices.

The SPI configuration determines the characteristics of a transfer in progress. For

a master, a transfer begins when data is written to SPDR and ends when SPIF is

set. For a slave with CPHA equal to 0, a transfer starts when SS goes low and ends

when SS returns high. In this case, SPIF is set at the middle of the eighth SCK

cycle when data is transferred from the shifter to the parallel data register, but the

transfer is still in progress until SS goes high. For a slave with CPHA equal to 1,

transfer begins when the SCK line goes to its active level, which is the edge at the

beginning of the first SCK cycle. The transfer ends in a slave in which CPHA

equals 1 when SPIF is set.

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Serial Peripheral Interface (SPI)

8.7 SPI Registers

The three SPI registers are:

•

Serial peripheral control register (SPCR)

Serial peripheral status register (SPSR)

Serial peripheral data register (SPDR)

These registers provide control, status, and data storage functions.

8.7.1 Serial Peripheral Control Register

Address:

$1028

Bit 7

6

SPE

0

5

DWOM

0

4

MSTR

0

3

CPOL

0

2

CPHA

1

SPR1

U

Bit 0

SPR0

U

Read:

Write:

Reset:

SPIE

0

U = Unaffected

Figure 8-3. Serial Peripheral Control Register (SPCR)

SPIE — Serial Peripheral Interrupt Enable Bit

Set the SPE bit to 1 to request a hardware interrupt sequence each time the

SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or

if the I bit in the condition code register is 1.

0 = SPI system interrupts disabled

1 = SPI system interrupts enabled

SPE — Serial Peripheral System Enable Bit

When the SPE bit is set, the port D bit 2, 3, 4, and 5 pins are dedicated to the

SPI function. If the SPI is in the master mode and DDRD bit 5 is set, then the

port D bit 5 pin becomes a general-purpose output instead of the SS input.

0 = SPI system disabled

1 = SPI system enabled

DWOM — Port D Wired-OR Mode Bit

DWOM affects all port D pins.

0 = Normal CMOS outputs

1 = Open-drain outputs

MSTR — Master Mode Select Bit

It is customary to have an external pullup resistor on lines that are driven by

open-drain devices.

0 = Slave mode

1 = Master mode

Data Sheet

138

M68HC11E Family — Rev. 5

Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

SPI Registers

CPOL — Clock Polarity Bit

When the clock polarity bit is cleared and data is not being transferred, the SCK

pin of the master device has a steady state low value. When CPOL is set, SCK

idles high. Refer to Figure 8-2 and 8.4 Clock Phase and Polarity Controls.

CPHA — Clock Phase Bit

The clock phase bit, in conjunction with the CPOL bit, controls the clock-data

relationship between master and slave. The CPHA bit selects one of two

different clocking protocols. Refer to Figure 8-2 and 8.4 Clock Phase and

Polarity Controls.

SPR[1:0] — SPI Clock Rate Select Bits

These two bits select the SPI clock (SCK) rate when the device is configured as

master. When the device is configured as slave, these bits have no effect. Refer

to Table 8-1.

Table 8-1. SPI Clock Rates

Frequency at

E = 1 MHz

(Baud)

Frequency at

E = 2 MHz

(Baud)

Frequency at

E = 3 MHz (

Baud)

Frequency at

E = 4 MHz

(Baud)

Divide

E Clock By

SPR[1:0]

0 0

0 1

1 0

1 1

2

4

500 kHz

250 kHz

62.5 kHz

31.3 kHz

1.0 MHz

500 kHz

125 kHz

62.5 kHz

1.5 MHz

750 kHz

2 MHz

1 MHz

16

32

187.5 kHz

93.8 kHz

250 kHz

125 kHz

8.7.2 Serial Peripheral Status Register

Address:

$1029

Bit 7

6

5

4

MODF

0

3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

SPIF

0

WCOL

0

= Unimplemented

Figure 8-4. Serial Peripheral Status Register (SPSR)

SPIF — SPI Interrupt Complete Flag

SPIF is set upon completion of data transfer between the processor and the

external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt

is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access

the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR

are inhibited.

M68HC11E Family — Rev. 5

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Serial Peripheral Interface (SPI)

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Serial Peripheral Interface (SPI)

WCOL — Write Collision Bit

Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set)

followed by an access of SPDR. Refer to 8.5.4 Slave Select and 8.6 SPI

System Errors.

0 = No write collision

1 = Write collision

Bit 5 — Unimplemented

Always reads 0

MODF — Mode Fault Bit

To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR.

Refer to 8.5.4 Slave Select and 8.6 SPI System Errors.

0 = No mode fault

1 = Mode fault

Bits [3:0] — Unimplemented

Always read 0

8.7.3 Serial Peripheral Data I/O Register

The SPDR is used when transmitting or receiving data on the serial bus. Only a

write to this register initiates transmission or reception of a byte, and this only

occurs in the master device. At the completion of transferring a byte of data, the

SPIF status bit is set in both the master and slave devices.

A read of the SPDR is actually a read of a buffer. To prevent an overrun and the

loss of the byte that caused the overrun, the first SPIF must be cleared by the time

a second transfer of data from the shift register to the read buffer is initiated.

Address:

$102A

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Indeterminate after reset

Figure 8-5. Serial Peripheral Data I/O Register (SPDR)

SPI is double buffered in and single buffered out.

Data Sheet

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Data Sheet — M68HC11E Family

Section 9. Timing System

9.1 Introduction

The M68HC11 timing system is composed of five clock divider chains. The main

clock divider chain includes a 16-bit free-running counter, which is driven by a

programmable prescaler. The main timer’s programmable prescaler provides one

of the four clocking rates to drive the 16-bit counter. Two prescaler control bits

select the prescale rate.

The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this main

clocking chain drive circuitry that generates the slower clocks used by the pulse

accumulator, the real-time interrupt (RTI), and the computer operating properly

(COP) watchdog subsystems, also described in this section. Refer to Figure 9-1.

All main timer system activities are referenced to this free-running counter. The

counter begins incrementing from $0000 as the MCU comes out of reset and

continues to the maximum count, $FFFF. At the maximum count, the counter rolls

over to $0000, sets an overflow flag, and continues to increment. As long as the

MCU is running in a normal operating mode, there is no way to reset, change, or

interrupt the counting. The capture/compare subsystem features three input

capture channels, four output compare channels, and one channel that can be

selected to perform either input capture or output compare. Each of the three input

capture functions has its own 16-bit input capture register (time capture latch) and

each of the output compare functions has its own 16-bit compare register. All timer

functions, including the timer overflow and RTI, have their own interrupt controls

and separate interrupt vectors.

The pulse accumulator contains an 8-bit counter and edge select logic. The pulse

accumulator can operate in either event counting mode or gated time accumulation

mode. During event counting mode, the pulse accumulator’s 8-bit counter

increments when a specified edge is detected on an input signal. During gated time

accumulation mode, an internal clock source increments the 8-bit counter while an

input signal has a predetermined logic level.

The real-time interrupt (RTI) is a programmable periodic interrupt circuit that

permits pacing the execution of software routines by selecting one of four interrupt

rates.

M68HC11E Family — Rev. 5

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Timing System

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Timing System

OSCILLATOR AND

CLOCK GENERATOR

(DIVIDE BY FOUR)

AS

E CLOCK

INTERNAL BUS CLOCK (PH2)

SPI

PRESCALER

(÷ 2, 4, 16, 32)

SPR[1:0]

PRESCALER

(÷ 1, 2, 4,....128)

SCR[2:0]

PRESCALER

(÷ 1, 3, 4, 13)

SCP[1:0]

÷39

SCI RECEIVER CLOCK

SCI TRANSMIT CLOCK

PULSE ACCUMULATOR

SCP2^*

÷16

E ÷ 2⁶

PRESCALER

(÷÷ 1, 2, 4, 8)

RTR[1:0]

E ÷ 2¹³

REAL-TIME INTERRUPT

÷ 4

E÷2¹⁵

PRESCALER

(÷ 1, 4, 8, 16)

PR[1:0]

PRESCALER

(÷1, 4, 16, 64)

CR[1:0]

TOF

TCNT

FF1

FF2

S

R

Q

S

R

Q

FORCE

COP

RESET

IC/OC

CLEAR COP

TIMER

SYSTEM

RESET

E SERIES TIM DIV CHAIN

* SCP2 present on MC68HC(7)11E20 only

Figure 9-1. Timer Clock Divider Chains

Data Sheet

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Timing System

Timer Structure

The COP watchdog clock input (E ÷ 2¹⁵) is tapped off of the free-running counter

chain. The COP automatically times out unless it is serviced within a specific time

by a program reset sequence. If the COP is allowed to time out, a reset is

generated, which drives the RESET pin low to reset the MCU and the external

system. Refer to Table 9-1 for crystal-related frequencies and periods.

Table 9-1. Timer Summary

XTAL Frequencies

4.0 MHz

1.0 MHz

1000 ns

8.0 MHz

2.0 MHz

500 ns

12.0 MHz

3.0 MHz

333 ns

Other Rates

(E)

Control Bits

PR1, PR0

(1/E)

Main Timer Count Rates

0 0

1 count —

overflow —

(E/1)

(E/2¹⁶

1000 ns

65.536 ms

500 ns

32.768 ms

333 ns

21.845 ms

)

0 1

1 count —

overflow —

(E/4)

(E/2¹⁸

4.0 µs

262.14 ms

2.0 µs

131.07 ms

1.333 µs

87.381 ms

1 0

1 count —

overflow —

(E/8)

(E/2¹⁹

8.0 µs

524.29 ms

4.0 µs

262.14 ms

2.667 µs

174.76 ms

1 1

1 count —

overflow —

(E/16)

(E/2²⁰

16.0 µs

1.049 s

8.0 µs

524.29 ms

5.333 µs

349.52 ms

)

9.2 Timer Structure

Figure 9-2 shows the capture/compare system block diagram. The port A pin

control block includes logic for timer functions and for general-purpose I/O. For pins

PA3, PA2, PA1, and PA0, this block contains both the edge-detection logic and the

control logic that enables the selection of which edge triggers an input capture. The

digital level on PA[3:0] can be read at any time (read PORTA register), even if the

pin is being used for the input capture function. Pins PA[6:3] are used for either

general-purpose I/O, or as output compare pins. When one of these pins is being

used for an output compare function, it cannot be written directly as if it were a

general-purpose output. Each of the output compare functions (OC[5:2]) is related

to one of the port A output pins. Output compare one (OC1) has extra control logic,

allowing it optional control of any combination of the PA[7:3] pins. The PA7 pin can

be used as a general-purpose I/O pin, as an input to the pulse accumulator, or as

an OC1 output pin.

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Timing System

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Timing System

PRESCALER

DIVIDE BY

TCNT (HI)

TCNT (LO)

TOI

9

1, 4, 8, OR 16

MCU

16-BIT FREE-RUNNING

COUNTER

TOF

PR1

PR0

E CLK

TAPS FOR RTI,

COP WATCHDOG, AND

PULSE ACCUMULATOR

INTERRUPT REQUESTS

(FURTHER QUALIFIED BY

I BIT IN CCR)

16-BIT TIMER BUS

TO PULSE

ACCUMULATOR

OC1I

FUNCTIONS

8

16-BIT COMPARATOR =

OC1F

OC2F

OC3F

PA7/OC1/

PAI

TOC1 (HI) TOC1 (LO)

BIT 7

BIT 6

FOC1

FOC2

FOC3

FOC4

FOC5

OC2I

OC3I

OC4I

I4/O5I

7

6

5

4

16-BIT COMPARATOR =

PA6/OC2/

OC1

TOC2 (HI) TOC2 (LO)

16-BIT COMPARATOR =

PA5/OC3/

OC1

BIT 5

BIT 4

BIT 3

TOC3 (HI) TOC3 (LO)

16-BIT COMPARATOR =

OC4F

OC5

PA4/OC4/

OC1

TOC4 (HI) TOC4 (LO)

16-BIT COMPARATOR =

TI4/O5 (HI) TI4/O5 (LO)

16-BIT LATCH CLK

PA3/OC5/

IC4/OC1

I4/O5F

IC4

CFORC

FORCE OUTPUT

COMPARE

I4/O5

IC1I

IC2I

IC3I

3

2

1

CLK

TIC1 (LO)

BIT 2

BIT 1

BIT 0

16-BIT LATCH

IC1F

PA2/IC1

PA1/IC2

PA0/IC3

TIC1 (HI)

CLK

16-BIT LATCH

IC2F

IC3F

TIC2 (HI)

TIC2 (LO)

CLK

16-BIT LATCH

TIC3 (HI)

TIC3 (LO)

TFLG 1

STATUS

FLAGS

TMSK 1

INTERRUPT

ENABLES

PORT A

PIN CONTROL

Figure 9-2. Capture/Compare Block Diagram

Data Sheet

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Timing System

Input Capture

9.3 Input Capture

The input capture function records the time an external event occurs by latching

the value of the free-running counter when a selected edge is detected at the

associated timer input pin. Software can store latched values and use them to

compute the periodicity and duration of events. For example, by storing the times

of successive edges of an incoming signal, software can determine the period and

pulse width of a signal. To measure period, two successive edges of the same

polarity are captured. To measure pulse width, two alternate polarity edges are

captured.

In most cases, input capture edges are asynchronous to the internal timer counter,

which is clocked relative to an internal clock (PH2). These asynchronous capture

requests are synchronized to PH2 so that the latching occurs on the opposite half

cycle of PH2 from when the timer counter is being incremented. This

synchronization process introduces a delay from when the edge occurs to when

the counter value is detected. Because these delays offset each other when the

time between two edges is being measured, the delay can be ignored. When an

input capture is being used with an output compare, there is a similar delay

between the actual compare point and when the output pin changes state.

The control and status bits that implement the input capture functions are

contained in:

•

Pulse accumulator control register (PACTL)

Timer control 2 register (TCTL2)

Timer interrupt mask 1 register (TMSK1)

Timer interrupt flag 2 register (TFLG1)

To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL

register. Note that this bit is cleared out of reset. To enable PA3 as the fourth input

capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a

fifth output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is

set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause

edges on the pin to result in input captures. Writing to TI4/O5 has no effect when

the TI4/O5 register is acting as IC4.

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Timing System

9.3.1 Timer Control Register 2

Use the control bits of this register to program input capture functions to detect a

particular edge polarity on the corresponding timer input pin. Each of the input

capture functions can be independently configured to detect rising edges only,

falling edges only, any edge (rising or falling), or to disable the input capture

function. The input capture functions operate independently of each other and can

capture the same TCNT value if the input edges are detected within the same timer

count cycle.

Address:

$1021

Bit 7

6

EDG4A

0

5

EDG1B

0

4

EDG1A

0

3

EDG2B

0

2

EDG2A

0

1

EDG3B

0

Bit 0

EDG3A

0

Read:

Write:

Reset:

EDG4B

0

Figure 9-3. Timer Control Register 2 (TCTL2)

EDGxB and EDGxA — Input Capture Edge Control Bits

There are four pairs of these bits. Each pair is cleared to 0 by reset and must be

encoded to configure the corresponding input capture edge detector circuit. IC4

functions only if the I4/O5 bit in the PACTL register is set. Refer to Table 9-2 for

timer control configuration.

Table 9-2. Timer Control Configuration

EDGxB

EDGxA

Configuration

Capture disabled

0

1

0

1

0

1

Capture on rising edges only

Capture on falling edges only

Capture on any edge

9.3.2 Timer Input Capture Registers

When an edge has been detected and synchronized, the 16-bit free-running

counter value is transferred into the input capture register pair as a single 16-bit

parallel transfer. Timer counter value captures and timer counter incrementing

occur on opposite half-cycles of the phase 2 clock so that the count value is stable

whenever a capture occurs. The timer input capture registers are not affected by

reset. Input capture values can be read from a pair of 8-bit read-only registers. A

read of the high-order byte of an input capture register pair inhibits a new capture

transfer for one bus cycle. If a double-byte read instruction, such as load double

accumulator D (LDD), is used to read the captured value, coherency is assured.

When a new input capture occurs immediately after a high-order byte read, transfer

is delayed for an additional cycle but the value is not lost.

Data Sheet

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M68HC11E Family — Rev. 5

Timing System

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Timing System

Input Capture

Register name: Timer Input Capture 1 Register (High) Address: $1010

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Indeterminate after reset

Register name: Timer Input Capture 1 Register (Low) Address: $1011

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Indeterminate after reset

Figure 9-4. Timer Input Capture 1 Register Pair (TIC1)

Register name: Timer Input Capture 2 Register (High) Address: $1012

Bit 7

6

5

4

3

2

1

Bit 0

Bit 8

Read:

Write:

Reset:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Indeterminate after reset

Register name: Timer Input Capture 2 Register (Low) Address: $1013

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Indeterminate after reset

Figure 9-5. Timer Input Capture 2 Register Pair (TIC2)

Register name: Timer Input Capture 3 Register (High) Address: $1014

Bit 7

6

5

4

3

2

1

Bit 0

Bit 8

Read:

Write:

Reset:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Indeterminate after reset

Register name: Timer Input Capture 3 Register (Low) Address: $1015

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Indeterminate after reset

Figure 9-6. Timer Input Capture 3 Register Pair (TIC3)

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Timing System

9.3.3 Timer Input Capture 4/Output Compare 5 Register

Use TI4/O5 as either an input capture register or an output compare register,

depending on the function chosen for the PA3 pin. To enable it as an input capture

pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic

level 1. To use it as an output compare register, set the I4/O5 bit to a logic level 0.

Refer to 9.7 Pulse Accumulator.

Register name: Timer Input Capture 4/Output Compare 5 (High) Address: $101E

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 9

1

Bit 0

Bit 8

1

Read:

Write:

Reset:

Register name: Timer Input Capture 4/Output Compare 5 (Low) Address: $101F

Bit 7

1

6

Bit 6

1

5

Bit 5

1

4

Bit 4

1

3

Bit 3

1

2

Bit 2

1

Bit 1

1

Bit 0

1

Read:

Write:

Reset:

Figure 9-7. Timer Input Capture 4/Output

Compare 5 Register Pair (TI4/O5)

9.4 Output Compare

Use the output compare (OC) function to program an action to occur at a specific

time — when the 16-bit counter reaches a specified value. For each of the five

output compare functions, there is a separate 16-bit compare register and a

dedicated 16-bit comparator. The value in the compare register is compared to the

value of the free-running counter on every bus cycle. When the compare register

matches the counter value, an output compare status flag is set. The flag can be

used to initiate the automatic actions for that output compare function.

To produce a pulse of a specific duration, write a value to the output compare

register that represents the time the leading edge of the pulse is to occur. The

output compare circuit is configured to set the appropriate output either high or low,

depending on the polarity of the pulse being produced. After a match occurs, the

output compare register is reprogrammed to change the output pin back to its

inactive level at the next match. A value representing the width of the pulse is

added to the original value, and then written to the output compare register.

Because the pin state changes occur at specific values of the free-running counter,

the pulse width can be controlled accurately at the resolution of the free-running

counter, independent of software latencies. To generate an output signal of a

specific frequency and duty cycle, repeat this pulse-generating procedure.

The five 16-bit read/write output compare registers are: TOC1, TOC2, TOC3, and

TOC4, and the TI4/O5. TI4/O5 functions under software control as either IC4 or

OC5. Each of the OC registers is set to $FFFF on reset. A value written to an OC

Data Sheet

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Timing System

Output Compare

register is compared to the free-running counter value during each E-clock cycle.

If a match is found, the particular output compare flag is set in timer interrupt flag

register 1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask

register 1 (TMSK1), an interrupt is generated. In addition to an interrupt, a specified

action can be initiated at one or more timer output pins. For OC[5:2], the pin action

is controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output

action is taken on each successful compare, regardless of whether or not the OCxF

flag in the TFLG1 register was previously cleared.

OC1 is different from the other output compares in that a successful OC1 compare

can affect any or all five of the OC pins. The OC1 output action taken when a match

is found is controlled by two 8-bit registers with three bits unimplemented: the

output compare 1 mask register, OC1M, and the output compare 1 data register,

OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies

what data is placed on these port pins.

9.4.1 Timer Output Compare Registers

All output compare registers are 16-bit read-write. Each is initialized to $FFFF at

reset. If an output compare register is not used for an output compare function, it

can be used as a storage location. A write to the high-order byte of an output

compare register pair inhibits the output compare function for one bus cycle. This

inhibition prevents inappropriate subsequent comparisons. Coherency requires a

complete 16-bit read or write. However, if coherency is not needed, byte accesses

can be used.

For output compare functions, write a comparison value to output compare

registers TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison

value, specified pin actions occur.

Register name: Timer Output Compare 1 Register (High) Address: $1016

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 9

1

Bit 0

Bit 8

1

Read:

Write:

Reset:

Register name: Timer Output Compare 1 Register (Low) Address: $1017

Bit 7

1

6

Bit 6

1

5

Bit 5

1

4

Bit 4

1

3

Bit 3

1

2

Bit 2

1

Bit 1

1

Bit 0

1

Read:

Write:

Reset:

Figure 9-8. Timer Output Compare 1 Register Pair (TOC1)

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Timing System

Register name: Timer Output Compare 2 Register (High) Address: $1018

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 9

1

Bit 0

Bit 8

1

Read:

Write:

Reset:

Register name: Timer Output Compare 2 Register (Low) Address: $1019

Bit 7

1

6

Bit 6

1

5

Bit 5

1

4

Bit 4

1

3

Bit 3

1

2

Bit 2

1

Bit 1

1

Bit 0

1

Read:

Write:

Reset:

Figure 9-9. Timer Output Compare 2 Register Pair (TOC2)

Register name: Timer Output Compare 3 Register (High) Address: $101A

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 9

1

Bit 0

Bit 8

1

Read:

Write:

Reset:

Register name: Timer Output Compare 3 Register (Low) Address: $101B

Bit 7

1

6

Bit 6

1

5

Bit 5

1

4

Bit 4

1

3

Bit 3

1

2

Bit 2

1

Bit 1

1

Bit 0

1

Read:

Write:

Reset:

Figure 9-10. Timer Output Compare 3 Register Pair (TOC3)

Register name: Timer Output Compare 4 Register (High) Address: $101C

Bit 7

Bit 15

1

6

Bit 14

1

5

Bit 13

1

4

Bit 12

1

3

Bit 11

1

2

Bit 10

1

Bit 9

1

Bit 0

Bit 8

1

Read:

Write:

Reset:

Register name: Timer Output Compare 4 Register (Low) Address: $101D

Bit 7

1

6

Bit 6

1

5

Bit 5

1

4

Bit 4

1

3

Bit 3

1

2

Bit 2

1

Bit 1

1

Bit 0

1

Read:

Write:

Reset:

Figure 9-11. Timer Output Compare 4 Register Pair (TOC4)

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9.4.2 Timer Compare Force Register

The CFORC register allows forced early compares. FOC[1:5] correspond to the

five output compares. These bits are set for each output compare that is to be

forced. The action taken as a result of a forced compare is the same as if there

were a match between the OCx register and the free-running counter, except that

the corresponding interrupt status flag bits are not set. The forced channels trigger

their programmed pin actions to occur at the next timer count transition after the

write to CFORC.

The CFORC bits should not be used on an output compare function that is

programmed to toggle its output on a successful compare because a normal

compare that occurs immediately before or after the force can result in an

undesirable operation.

Address:

$100B

Bit 7

6

FOC2

0

5

FOC3

0

4

FOC4

0

3

FOC5

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

FOC1

0

= Unimplemented

Figure 9-12. Timer Compare Force Register (CFORC)

FOC[1:5] — Force Output Comparison Bit

When the FOC bit associated with an output compare circuit is set, the output

compare circuit immediately performs the action it is programmed to do when

an output match occurs.

0 = Not affected

1 = Output x action occurs

Bits [2:0] — Unimplemented

Always read 0

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9.4.3 Output Compare Mask Register

Use OC1M with OC1 to specify the bits of port A that are affected by a successful

OC1 compare. The bits of the OC1M register correspond to PA[7:3].

Address:

$100C

Bit 7

6

OC1M6

0

5

OC1M5

0

4

OC1M4

0

3

OC1M3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

OC1M7

0

= Unimplemented

Figure 9-13. Output Compare 1 Mask Register (OC1M)

OC1M[7:3] — Output Compare Masks

0 = OC1 disabled

1 = OC1 enabled to control the corresponding pin of port A

Bits [2:0] — Unimplemented

Always read 0

9.4.4 Output Compare Data Register

Use this register with OC1 to specify the data that is to be stored on the affected

pin of port A after a successful OC1 compare. When a successful OC1 compare

occurs, a data bit in OC1D is stored in the corresponding bit of port A for each bit

that is set in OC1M.

Address:

$100D

Bit 7

6

OC1D6

0

5

OC1D5

0

4

OC1D4

0

3

OC1D3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

OC1D7

0

= Unimplemented

Figure 9-14. Output Compare 1 Data Register (OC1D)

If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1

compares.

Bits [2:0] — Unimplemented

Always read 0

9.4.5 Timer Counter Register

The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer.

A full counter read addresses the most significant byte (MSB) first. A read of this

address causes the least significant byte (LSB) to be latched into a buffer for the

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next CPU cycle so that a double-byte read returns the full 16-bit state of the counter

at the time of the MSB read cycle.

Register name: Timer Counter Register (High) Address: $100E

Bit 7

6

5

4

3

2

1

Bit 0

Bit 8

Read:

Write:

Reset:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

0

Register name: Timer Counter Register (Low) Address: $100F

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0

= Unimplemented

Figure 9-15. Timer Counter Register (TCNT)

9.4.6 Timer Control Register 1

The bits of this register specify the action taken as a result of a successful OCx

compare.

Address:

$1020

Bit 7

6

OL2

0

5

OM3

0

4

OL3

0

3

OM4

0

2

OL4

0

1

OM5

0

Bit 0

OL5

0

Read:

Write:

Reset:

OM2

0

Figure 9-16. Timer Control Register 1 (TCTL1)

OM[2:5] — Output Mode Bits

OL[2:5] — Output Level Bits

These control bit pairs are encoded to specify the action taken after a successful

OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear.

Refer to Table 9-3 for the coding.

Table 9-3. Timer Output Compare Actions

OMx

OLx

Action Taken on Successful Compare

Timer disconnected from output pin logic

Toggle OCx output line

0

1

0

1

0

1

Clear OCx output line to 0

Set OCx output line to 1

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9.4.7 Timer Interrupt Mask 1 Register

Use this 8-bit register to enable or inhibit the timer input capture and output

compare interrupts.

Address:

$1022

Bit 7

6

OC2I

0

5

OC3I

0

4

OC4I

0

3

I4/O5I

0

2

IC1I

0

1

IC2I

0

Bit 0

IC3I

0

Read:

Write:

Reset:

OC1I

0

Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)

OC1I–OC4I — Output Compare x Interrupt Enable Bits

If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt

sequence is requested.

I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit

When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit.

When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit.

IC1I–IC3I — Input Capture x Interrupt Enable Bits

If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt

sequence is requested.

NOTE:

Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in TMSK1 enable

the corresponding interrupt sources.

9.4.8 Timer Interrupt Flag 1 Register

Bits in this register indicate when timer system events have occurred. Coupled with

the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either

a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in

TMSK1 in the same position.

Address:

$1023

Bit 7

6

OC2F

0

5

OC3F

0

4

OC4F

0

3

I4/O5F

0

2

IC1F

0

1

IC2F

0

Bit 0

IC3F

0

Read:

Write:

Reset:

OC1F

0

Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1)

Clear flags by writing a 1 to the corresponding bit position(s).

OC1F–OC4F — Output Compare x Flag

Set each time the counter matches output compare x value

I4/O5F — Input Capture 4/Output Compare 5 Flag

Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL

IC1F–IC3F — Input Capture x Flag

Set each time a selected active edge is detected on the ICx input line

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9.4.9 Timer Interrupt Mask 2 Register

Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts.

The timer prescaler control bits are included in this register.

Address:

$1024

Bit 7

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

Read:

Write:

Reset:

TOI

0

= Unimplemented

Figure 9-19. Timer Interrupt Mask 2 Register (TMSK2)

TOI — Timer Overflow Interrupt Enable Bit

0 = TOF interrupts disabled

1 = Interrupt requested when TOF is set to 1

RTII — Real-Time Interrupt Enable Bit

Refer to 9.5 Real-Time Interrupt (RTI).

PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit

Refer to 9.7.3 Pulse Accumulator Status and Interrupt Bits.

PAII — Pulse Accumulator Input Edge Interrupt Enable Bit

Refer to 9.7.3 Pulse Accumulator Status and Interrupt Bits.

Bits [3:2] — Unimplemented

Always read 0

PR[1:0] — Timer Prescaler Select Bits

These bits are used to select the prescaler divide-by ratio. In normal modes,

PR[1:0] can be written only once, and the write must be within 64 cycles after

reset. Refer to Table 9-1 and Table 9-4 for specific timing values.

Table 9-4. Timer Prescale

PR[1:0]

0 0

Prescaler

1

4

0 1

1 0

8

1 1

16

NOTE:

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable

the corresponding interrupt sources.

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9.4.10 Timer Interrupt Flag Register 2

Bits in this register indicate when certain timer system events have occurred.

Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer

subsystem to operate in either a polled or interrupt driven system. Each bit of

TFLG2 corresponds to a bit in TMSK2 in the same position.

Address:

$1025

Bit 7

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

TOF

0

= Unimplemented

Figure 9-20. Timer Interrupt Flag 2 Register (TFLG2)

Clear flags by writing a 1 to the corresponding bit position(s).

TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time (Periodic) Interrupt Flag

Refer to 9.5 Real-Time Interrupt (RTI).

PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9.7 Pulse Accumulator.

PAIF — Pulse Accumulator Input Edge Interrupt Flag

Refer to 9.7 Pulse Accumulator.

Bits [3:0] — Unimplemented

Always read 0

9.5 Real-Time Interrupt (RTI)

The real-time interrupt (RTI) feature, used to generate hardware interrupts at a

fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the

pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register

enables the interrupt capability. The four different rates available are a product of

the MCU oscillator frequency and the value of bits RTR[1:0]. Refer to Table 9-5,

which shows the periodic real-time interrupt rates.

Table 9-5. RTI Rates

RTR[1:0]

0 0

E = 3 MHz

2.731 ms

5.461 ms

10.923 ms

21.845 ms

E = 2 MHz

4.096 ms

8.192 ms

16.384 ms

32.768 ms

E = 1 MHz

8.192 ms

E = X MHz

(E/2¹³

(E/2¹⁴

(E/2¹⁵

(E/2¹⁶

)

0 1

16.384 ms

32.768 ms

65.536 ms

1 0

1 1

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Real-Time Interrupt (RTI)

The clock source for the RTI function is a free-running clock that cannot be stopped

or interrupted except by reset. This clock causes the time between successive RTI

timeouts to be a constant that is independent of the software latencies associated

with flag clearing and service. For this reason, an RTI period starts from the

previous timeout, not from when RTIF is cleared.

Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt

request is generated. After reset, one entire RTI period elapses before the RTIF

is set for the first time. Refer to the 9.4.9 Timer Interrupt Mask 2 Register,

9.5.2 Timer Interrupt Flag Register 2, and 9.5.3 Pulse Accumulator Control

Register.

9.5.1 Timer Interrupt Mask Register 2

This register contains the real-time interrupt enable bits.

Address:

$1024

Bit 7

6

RTI

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

Read:

Write:

Reset:

TOI

0

= Unimplemented

Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2)

TOI — Timer Overflow Interrupt Enable Bit

0 = TOF interrupts disabled

1 = Interrupt requested when TOF is set to 1

RTII — Real-Time Interrupt Enable Bit

0 = RTIF interrupts disabled

1 = Interrupt requested when RTIF set to 1

PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit

Refer to 9.7 Pulse Accumulator.

PAII — Pulse Accumulator Input Edge Bit

Refer to 9.7 Pulse Accumulator.

Bits [3:2] — Unimplemented

Always read 0

PR[1:0] — Timer Prescaler Select Bits

Refer to Table 9-4.

NOTE:

Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable

the corresponding interrupt sources.

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9.5.2 Timer Interrupt Flag Register 2

Bits of this register indicate the occurrence of timer system events. Coupled with

the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to

operate in either a polled or interrupt driven system. Each bit of TFLG2

corresponds to a bit in TMSK2 in the same position.

Address:

$1025

Bit 7

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

TOF

0

= Unimplemented

Figure 9-22. Timer Interrupt Flag 2 Register (TFLG2)

Clear flags by writing a 1 to the corresponding bit position(s).

TOF — Timer Overflow Interrupt Flag

Set when TCNT changes from $FFFF to $0000

RTIF — Real-Time Interrupt Flag

The RTIF status bit is automatically set to 1 at the end of every RTI period. To

clear RTIF, write a byte to TFLG2 with bit 6 set.

PAOVF — Pulse Accumulator Overflow Interrupt Flag

Refer to 9.7 Pulse Accumulator.

PAIF — Pulse Accumulator Input Edge Interrupt Flag

Refer to 9.7 Pulse Accumulator.

Bits [3:0] — Unimplemented

Always read 0

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Computer Operating Properly (COP) Watchdog Function

9.5.3 Pulse Accumulator Control Register

Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits

control the pulse accumulator and IC4/OC5 functions.

Address:

$1026

Bit 7

6

PAEN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

Read:

Write:

Reset:

DDRA7

0

Figure 9-23. Pulse Accumulator Control Register (PACTL)

DDRA7 — Data Direction for Port A Bit 7

Refer to Section 6. Parallel Input/Output (I/O) Ports.

PAEN — Pulse Accumulator System Enable Bit

Refer to 9.7 Pulse Accumulator.

PAMOD — Pulse Accumulator Mode Bit

Refer to 9.7 Pulse Accumulator.

PEDGE — Pulse Accumulator Edge Control Bit

Refer to 9.7 Pulse Accumulator.

DDRA3 — Data Direction for Port A Bit 3

Refer to Section 6. Parallel Input/Output (I/O) Ports.

I4/O5 — Input Capture 4/Output Compare Bit

Refer to 9.7 Pulse Accumulator.

RTR[1:0] — RTI Interrupt Rate Select Bits

These two bits determine the rate at which the RTI system requests interrupts.

The RTI system is driven by an E divided by 2¹³rate clock that is compensated

so it is independent of the timer prescaler. These two control bits select an

additional division factor. Refer to Table 9-5.

9.6 Computer Operating Properly (COP) Watchdog Function

The clocking chain for the COP function, tapped off of the main timer divider chain,

is only superficially related to the main timer system. The CR[1:0] bits in the

OPTION register and the NOCOP bit in the CONFIG register determine the status

of the COP function. One additional register, COPRST, is used to arm and clear

the COP watchdog reset system. Refer to Section 5. Resets and Interrupts for a

more detailed discussion of the COP function.

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9.7 Pulse Accumulator

The M68HC11 Family of MCUs has an 8-bit counter that can be configured to

operate either as a simple event counter or for gated time accumulation, depending

on the state of the PAMOD bit in the PACTL register. Refer to the pulse

accumulator block diagram, Figure 9-24. In the event counting mode, the 8-bit

counter is clocked to increasing values by an external pin. The maximum clocking

rate for the external event counting mode is the E clock divided by two. In gated

time accumulation mode, a free-running E-clock divide-by-64 signal drives the 8-bit

counter, but only while the external PAI pin is activated. Refer to Table 9-6. The

pulse accumulator counter can be read or written at any time.

PAOVI

PAOVF

1

INTERRUPT

REQUESTS

PAII

PAIF

2

E ÷ 64 CLOCK

FROM MAIN TIMER

TMSK2 INT ENABLES

TFLG2 INTERRUPT STATUS

PAI EDGE

PAEN

DISABLE

FLAG SETTING

OVERFLOW

MCU PIN

CLOCK

PAEN

2 1

:

MUX

PA7/

PAI/

OC1

INPUT BUFFER

AND

EDGE DETECTOR

PACNT 8-BIT COUNTER

ENABLE

DATA

BUS

OUTPUT

BUFFER

FROM

MAIN TIMER

OC1

FROM

DDRA7

PACTL CONTROL

INTERNAL

DATA BUS

Figure 9-24. Pulse Accumulator

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Pulse Accumulator

Table 9-6. Pulse Accumulator Timing

Crystal

Frequency

PACNT

Overflow

E Clock

Cycle Time

E ÷ 64

4.0 MHz

1 MHz

2 MHz

3 MHz

1000 ns

500 ns

333 ns

64 µs

32 µs

16.384 ms

8.192 ms

5.461 ms

8.0 MHz

12.0 MHz

21.33 µs

Pulse accumulator control bits are also located within two timer registers, TMSK2

and TFLG2, as described in the following paragraphs.

9.7.1 Pulse Accumulator Control Register

Four of this register’s bits control an 8-bit pulse accumulator system. Another bit

enables either the OC5 function or the IC4 function, while two other bits select the

rate for the real-time interrupt system.

Address:

$1026

Bit 7

6

PAEN

0

5

PAMOD

0

4

PEDGE

0

3

DDRA3

0

2

I4/O5

0

1

RTR1

0

Bit 0

RTR0

0

Read:

Write:

Reset:

DDRA7

0

Figure 9-25. Pulse Accumulator Control Register (PACTL)

DDRA7 — Data Direction for Port A Bit 7

Refer to Section 6. Parallel Input/Output (I/O) Ports.

PAEN — Pulse Accumulator System Enable Bit

0 = Pulse accumulator disabled

1 = Pulse accumulator enabled

PAMOD — Pulse Accumulator Mode Bit

0 = Event counter

1 = Gated time accumulation

PEDGE — Pulse Accumulator Edge Control Bit

This bit has different meanings depending on the state of the PAMOD bit, as

shown in Table 9-7.

Table 9-7. Pulse Accumulator Edge Control

PAMOD

PEDGE

Action on Clock

PAI falling edge increments the counter.

PAI rising edge increments the counter.

A 0 on PAI inhibits counting.

0

1

0

1

0

1

A 1 on PAI inhibits counting.

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DDRA3 — Data Direction for Port A Bit 3

Refer to Section 6. Parallel Input/Output (I/O) Ports.

I4/O5 — Input Capture 4/Output Compare 5 Bit

0 = Output compare 5 function enable (no IC4)

1 = Input capture 4 function enable (no OC5)

RTR[1:0] — RTI Interrupt Rate Select Bits

Refer to 9.5 Real-Time Interrupt (RTI).

9.7.2 Pulse Accumulator Count Register

This 8-bit read/write register contains the count of external input events at the PAI

input or the accumulated count. The PACNT is readable even if PAI is not active in

gated time accumulation mode. The counter is not affected by reset and can be

read or written at any time. Counting is synchronized to the internal PH2 clock so

that incrementing and reading occur during opposite half cycles.

Address:

$1027

Bit 7

6

5

4

3

2

1

Bit 0

Read:

Write:

Reset:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Indeterminate after reset

Figure 9-26. Pulse Accumulator Count Register (PACNT)

9.7.3 Pulse Accumulator Status and Interrupt Bits

The pulse accumulator control bits, PAOVI and PAII, PAOVF and PAIF, are located

within timer registers TMSK2 and TFLG2.

Address:

$1024

Bit 7

6

RTII

0

5

PAOVI

0

4

PAII

0

3

0

2

0

1

PR1

0

Bit 0

PR0

0

Read:

Write:

Reset:

TOI

0

= Unimplemented

Figure 9-27. Timer Interrupt Mask 2 Register (TMSK2)

Address:

$1025

Bit 7

TOF

0

6

RTIF

0

5

PAOVF

0

4

PAIF

0

3

0

2

0

1

0

Bit 0

Read:

Write:

Reset:

0

= Unimplemented

Figure 9-28. Timer Interrupt Flag 2 Register (TFLG2)

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PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag

The PAOVF status bit is set each time the pulse accumulator count rolls over

from $FF to $00. To clear this status bit, write a 1 in the corresponding data bit

position (bit 5) of the TFLG2 register. The PAOVI control bit allows configuring

the pulse accumulator overflow for polled or interrupt-driven operation and does

not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow

interrupts are inhibited, and the system operates in a polled mode, which

requires that PAOVF be polled by user software to determine when an overflow

has occurred. When the PAOVI control bit is set, a hardware interrupt request

is generated each time PAOVF is set. Before leaving the interrupt service

routine, software must clear PAOVF by writing to the TFLG2 register.

PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable Bit and Flag

The PAIF status bit is automatically set each time a selected edge is detected

at the PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with

a 1 in the corresponding data bit position (bit 4). The PAII control bit allows

configuring the pulse accumulator input edge detect for polled or

interrupt-driven operation but does not affect setting or clearing the PAIF bit.

When PAII is 0, pulse accumulator input interrupts are inhibited, and the system

operates in a polled mode. In this mode, the PAIF bit must be polled by user

software to determine when an edge has occurred. When the PAII control bit is

set, a hardware interrupt request is generated each time PAIF is set. Before

leaving the interrupt service routine, software must clear PAIF by writing to the

TFLG2 register.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

163

Timing System

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Timing System

Data Sheet

164

M68HC11E Family — Rev. 5

MOTOROLA

Timing System

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Data Sheet — M68HC11E Family

Section 10. Electrical Characteristics

10.1 Introduction

This section contains electrical specifications for the M68HC11 E-series devices.

10.2 Maximum Ratings for Standard and Extended Voltage Devices

Maximum ratings are the extreme limits to which the MCU can be exposed without

permanently damaging it.

NOTE:

This device is not guaranteed to operate properly at the maximum ratings.

Refer to 10.5 DC Electrical Characteristics, 10.6 Supply Currents and Power

Dissipation, 10.7 MC68L11E9/E20 DC Electrical Characteristics, and

10.8 MC68L11E9/E20 Supply Currents and Power Dissipation for guaranteed

operating conditions.

Rating

Symbol

Value

Unit

V

V_DD

Supply voltage

Input voltage

–0.3 to +7.0

V_In

V

Current drain per pin⁽¹⁾excluding V_DD, V_SS, AV_DD

,

I_D

25

mA

V_RH, V_RL, and XIRQ/V_PPE

T_STG

Storage temperature

–55 to +150

°C

1. One pin at a time, observing maximum power dissipation limits

NOTE:

This device contains circuitry to protect the inputs against damage due to high

static voltages or electric fields; however, it is advised that normal precautions be

taken to avoid application of any voltage higher than maximum-rated voltages to

this high-impedance circuit. For proper operation, it is recommended that V_Inand

V_Outbe constrained to the range V_SS≤ (V_Inor V_Out) ≤ V_DD. Reliability of operation

is enhanced if unused inputs are connected to an appropriate logic voltage level

(for example, either V_SSor V_DD).

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

165

Electrical Characteristics

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Electrical Characteristics

10.3 Functional Operating Range

Rating

Symbol

Value

Unit

°C

T_Lto T_H

Operating temperature range

MC68HC(7)11Ex

MC68HC(7)11ExC

MC68HC(7)11ExV

MC68HC(7)11ExM

MC68HC811E2

0 to +70

–40 to +85

–40 to +105

–40 to +125

0 to +70

T_A

MC68HC811E2C

MC68HC811E2V

MC68HC811E2M

MC68L11Ex

–40 to +85

–40 to +105

–40 to +125

–20 to +70

V_DD

Operating voltage range

5.0 ± 10%

V

10.4 Thermal Characteristics

Characteristic

Average junction temperature

Ambient temperature

Symbol

Value

Unit

°C

T_J

T_A+ (P_D× Θ_JA)

T_A

User-determined

°C

Package thermal resistance (junction-to-ambient)

48-pin plastic DIP (MC68HC811E2 only)

56-pin plastic SDIP

52-pin plastic leaded chip carrier

52-pin plastic thin quad flat pack (TQFP)

64-pin quad flat pack

50

85

Θ_JA

°C/W

P

_INT+ P_I/O

Total power dissipation⁽¹⁾

P_D

W

K / T_J+ 273°C

P_INT

P_I/O

I

_DD× V_DD

Device internal power dissipation

I/O pin power dissipation⁽²⁾

W

User-determined

P

_D× (T_A+ 273°C)

A constant⁽³⁾

K

W/°C

2

+ Θ_JA× P_D

1. This is an approximate value, neglecting P_I/O

.

2. For most applications, P_I/O≤ P_INTand can be neglected.

3. K is a constant pertaining to the device. Solve for K with a known T_Aand a measured P_D(at equilibrium). Use this value

of K to solve for P_Dand T_Jiteratively for any value of T_A.

Data Sheet

166

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

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Electrical Characteristics

DC Electrical Characteristics

10.5 DC Electrical Characteristics

Characteristics⁽¹⁾

Symbol

Min

Max

Unit

Output voltage⁽²⁾

I_Load= ±±10.0 µA

V_OL, V_OH

V

—

0.1

—

All outputs except XTAL

All outputs except XTAL, RESET, and MODA

V_DD–0.1

Output high voltage⁽²⁾

I_Load= –0.8 mA, V_DD= 4.5 V

V_OH

V_DD–0.8

—

V

All outputs except XTAL, RESET, and MODA

Output low voltage

I

_Load= 1.6 mA

V_OL

—

0.4

All outputs except XTAL

Input high voltage

All inputs except RESET

RESET

0.7 × V

V_DD+ 0.3

DD

V_IH

V_IL

V

0.8 × V

DD

V_SS–0.3

—

0.2 × V_DD

Input low voltage, all inputs

I/O ports, 3-state leakage

V_In= V_IHor V_IL

I_OZ

±10

µA

PA7, PA3, PC[7:0], PD[5:0], AS/STRA,

MODA/LIR, RESET

Input leakage current⁽³⁾

V_In= V_DDor V_SS

I_In

—

±1

±10

PA[2:0], IRQ, XIRQ

MODB/V_STBY(XIRQ on EPROM-based devices)

V_SB

I_SB

V_DD

10

RAM standby voltage, power down

RAM standby current, power down

4.0

—

V

µA

Input capacitance

C_In

C_L

PA[2:0], PE[7:0], IRQ, XIRQ, EXTAL

PA7, PA3, PC[7:0], PD[5:0], AS/STRA, MODA/LIR, RESET

—

8

12

pF

Output load capacitance

All outputs except PD[4:1]

PD[4:1]

—

90

100

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= T_Lto T_H, unless otherwise noted

2. V_OHspecification for RESET and MODA is not applicable because they are open-drain pins. V_OHspecification not

applicable to ports C and D in wired-OR mode.

3. Refer to 10.13 Analog-to-Digital Converter Characteristics and 10.14 MC68L11E9/E20 Analog-to-Digital Converter

Characteristics for leakage current for port E.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

167

Electrical Characteristics

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Electrical Characteristics

10.6 Supply Currents and Power Dissipation

Characteristics⁽¹⁾

Symbol

Min

Max

Unit

Run maximum total supply current⁽²⁾

Single-chip mode2 MHz

3 MHz

Expanded multiplexed mode2 MHz

3 MHz

—

15

27

35

I_DD

mA

Wait maximum total supply current⁽²⁾

(all peripheral functions shut down)

Single-chip mode2 MHz

3 MHz

Expanded multiplexed mode2 MHz

3 MHz

—

6

W_IDD

15

10

20

mA

Stop maximum total supply current⁽²⁾

Single-chip mode, no clocks–40°C to +85°C

> +85°C to +105°C

—

25

50

100

S_IDD

µA

> +105°C to +125°C

Maximum power dissipation

Single-chip mode2 MHz

3 MHz

Expanded multiplexed mode2 MHz

3 MHz

—

85

P_D

150

195

mW

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= T_Lto T_H, unless otherwise noted

2. EXTAL is driven with a square wave, and

t_CYC= 500 ns for 2 MHz rating

t

V

_CYC= 333 ns for 3 MHz rating

_IL≤ 0.2 V

V_IH≥ V_DD– 0.2 V

no dc loads

Data Sheet

168

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

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Electrical Characteristics

MC68L11E9/E20 DC Electrical Characteristics

10.7 MC68L11E9/E20 DC Electrical Characteristics

Characteristics⁽¹⁾

Symbol

Min

Max

Unit

Output voltage⁽²⁾

I_Load= ±±10.0 µA

V _OL, V_OH

—

0.1

—

V

All outputs except XTAL

All outputs except XTAL, RESET, and MODA

V_DD–0.1

Output high voltage⁽²⁾

I_Load= –0.5 mA, V_DD= 3.0 V

V_OH

V_DD–0.8

—

V

I_Load= –0.8 mA, V_DD= 4.5 V

All outputs except XTAL, RESET, and MODA

Output low voltage

I

_Load= 1.6 mA, V_DD= 5.0 V

V_OL

—

0.4

I_Load= 1.0 mA, V_DD= 3.0 V

All outputs except XTAL

Input high voltage

All inputs except RESET

RESET

V_DD+ 0.3

0.7 × V

V_IH

V_IL

V

DD

0.8 × V

DD

V_SS–0.3

—

0.2 × V_DD

Input low voltage, all inputs

I/O ports, 3-state leakage

V_In= V_IHor V_IL

I_OZ

±10

µA

PA7, PA3, PC[7:0], PD[5:0], AS/STRA,

MODA/LIR, RESET

Input leakage current⁽³⁾

V_In= V_DDor V_SS

I_In

—

±1

±10

PA[2:0], IRQ, XIRQ

MODB/V_STBY(XIRQ on EPROM-based devices)

V_SB

I_SB

V_DD

10

RAM standby voltage, power down

RAM standby current, power down

2.0

—

V

µA

Input capacitance

PA[2:0], PE[7:0], IRQ, XIRQ, EXTAL

PA7, PA3, PC[7:0], PD[5:0], AS/STRA, MODA/LIR, RESET

l

—

8

12

pF

Output load capacitance

All outputs except PD[4:1]

PD[4:1]

C_L

—

90

100

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, unless otherwise noted

2. V_OHspecification for RESET and MODA is not applicable because they are open-drain pins. V_OHspecification not

applicable to ports C and D in wired-OR mode.

3. Refer to 10.13 Analog-to-Digital Converter Characteristics and 10.14 MC68L11E9/E20 Analog-to-Digital Converter

Characteristics for leakage current for port E.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Electrical Characteristics

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Electrical Characteristics

10.8 MC68L11E9/E20 Supply Currents and Power Dissipation

Characteristic⁽¹⁾

Run maximum total supply current⁽²⁾

Symbol

1 MHz

2 MHz

Unit

Single-chip mode

V_DD= 5.5 V

8

4

15

8

I_DD

V_DD= 3.0 V

mA

Expanded multiplexed mode

V_DD= 5.5 V

14

7

27

14

V_DD= 5.5 V

Wait maximum total supply current⁽²⁾

(all peripheral functions shut down)

Single-chip mode

V

_DD= 5.5 V

3

1.5

6

3

W_IDD

mA

V_DD= 3.0 V

Expanded multiplexed mode

V_DD= 5.5 V

5

2.5

10

5

V_DD= 3.0 V

Stop maximum total supply current⁽²⁾

Single-chip mode, no clocks

V_DD= 5.5 V

S_IDD

µA

50

25

50

25

V_DD= 3.0 V

Maximum power dissipation

Single-chip mode

2 MHz

3 MHz

44

12

85

24

P_D

mW

Expanded multiplexed mode

2 MHz

3 MHz

77

21

150

42

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, unless otherwise noted

2. EXTAL is driven with a square wave, and

t_CYC= 500 ns for 2 MHz rating

t

V

_CYC= 333 ns for 3 MHz rating

_IL≤ 0.2 V

V_IH≥ V_DD– 0.2 V

no dc loads

Data Sheet

170

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

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Electrical Characteristics

MC68L11E9/E20 Supply Currents and Power Dissipation

V

~ DD

CLOCKS,

STROBES

V

– 0.8 VOLTS

NOM

DD

0.4 VOLTS

NOM

~V

SS

70% of V

20% of V

DD

INPUTS

DD

NOMINAL TIMING

V

~

DD

V

– 0.8 Volts

DD

OUTPUTS

0.4 Volts

~V

SS

DC TESTING

~V

DD

70% of V

SPEC

CLOCKS,

STROBES

DD

20% of V

SPEC

DD

V

~ SS

(NOTE 2)

V

– 0.8 VOLTS

DD

70% of V

DD

INPUTS

20% of V

DD

0.4 VOLTS

SPEC TIMING

V

~ DD

70% of V

20% of V

DD

OUTPUTS

V

~ SS

AC TESTING

Notes:

1. Full test loads are applied during all dc electrical tests and ac timing measurements.

2. During ac timing measurements, inputs are driven to 0.4 volts and V_DD– 0.8 volts while timing

measurements are taken at 20% and 70% of V_DDpoints.

Figure 10-1. Test Methods

M68HC11E Family — Rev. 5

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Data Sheet

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Electrical Characteristics

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Electrical Characteristics

10.9 Control Timing

1.0 MHz

2.0 MHz

3.0 MHz

Characteristic^{(1) (2)}

Symbol

Unit

Min Max Min Max Min Max

f_o

Frequency of operation

E-clock period

dc

1000

—

1.0

—

dc

500

—

2.0

—

dc

333

—

3.0

—

MHz

ns

t_CYC

f_XTAL

4 f_o

Crystal frequency

4.0

8.0

12.0

MHz

External oscillator frequency

dc

Processor control setup time

t_PCSU= 1/4 t_CYC+ 50 ns

t_PCSU

300

—

175

—

133

—

ns

Reset input pulse width

PW_RSTL

t_CYC

To guarantee external reset vector

Minimum input time (can be pre-empted by internal reset)

8

1

—

8

1

—

8

1

—

t_MPS

t_MPH

t_CYC

ns

Mode programming setup time

Mode programming hold time

2

—

2

—

2

—

10

Interrupt pulse width, IRQ edge-sensitive mode

PW_IRQ= t_CYC+ 20 ns

PW_IRQ

t_WRS

1020

—

4

520

—

4

353

—

4

ns

t_CYC

Wait recovery startup time

Timer pulse width input capture pulse accumulator input

PW_TIM= t_CYC+ 20 ns

PW_TIM

1020

—

520

—

353

—

ns

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,

releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 5.

Resets and Interrupts for further detail.

Data Sheet

172

M68HC11E Family — Rev. 5

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Electrical Characteristics

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Electrical Characteristics

MC68L11E9/E20 Control Timing

10.10 MC68L11E9/E20 Control Timing

1.0 MHz

2.0 MHz

Characteristic^{(1) (2)}

Symbol

Unit

Min

Max

1.0

—

Min

Max

2.0

—

f_o

Frequency of operation

E-clock period

dc

1000

—

dc

500

—

MHz

ns

t_CYC

f_XTAL

4 f_o

Crystal frequency

4.0

8.0

MHz

External oscillator frequency

dc

Processor control setup time

t_PCSU= 1/4 t_CYC+ 75 ns

t_PCSU

325

—

200

—

ns

Reset input pulse width

PW_RSTL

t_CYC

To guarantee external reset vector

Minimum input time (can be pre-empted by internal reset)

8

1

—

8

1

—

t_MPS

t_MPH

t_CYC

ns

Mode programming setup time

Mode programming hold time

2

—

2

—

10

Interrupt pulse width, IRQ edge-sensitive mode

PW_IRQ= t_CYC+ 20 ns

PW_IRQ

t_WRS

1020

—

4

520

—

4

ns

t_CYC

Wait recovery startup time

Timer pulse width input capture pulse accumulator input

PW_TIM= t_CYC+ 20 ns

PW_TIM

1020

—

520

—

ns

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,

releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 5.

Resets and Interrupts for further detail.

(1)

PA[2:0]

(2)

PA[2:0]

(1) (3)

PA7

PW

TIM

(2) (3)

PA7

Notes:

1. Rising edge sensitive input

2. Falling edge sensitive input

3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.

Figure 10-2. Timer Inputs

M68HC11E Family — Rev. 5

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Electrical Characteristics

Data Sheet

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Electrical Characteristics

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MC68L11E9/E20 Control Timing

M68HC11E Family — Rev. 5

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Data Sheet

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Electrical Characteristics

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Electrical Characteristics

Data Sheet

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MC68L11E9/E20 Control Timing

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Electrical Characteristics

10.11 Peripheral Port Timing

1.0 MHz

2.0 MHz

3.0 MHz

Characteristic^{(1) (2)}

Symbol

Unit

Min

Max

1.0

—

Min

Max

2.0

—

Min

Max

3.0

—

Frequency of operation

E-clock frequency

f_o

dc

MHz

ns

t_CYC

t_PDSU

t_PDH

E-clock period

1000

100

500

100

333

100

Peripheral data setup time

MCU read of ports A, C, D, and E

—

ns

Peripheral data hold time

MCU read of ports A, C, D, and E

50

—

50

—

50

—

ns

Delay time, peripheral data write

t_PWD= 1/4 t_CYC+ 100 ns

t_PWD

—

200

350

—

200

225

—

200

183

MCU writes to port A

MCU writes to ports B, C, and D

t_IS

t_IH

Port C input data setup time

Port C input data hold time

60

—

60

—

60

—

ns

100

Delay time, E fall to STRB

t_DEB= 1/4 t_CYC+ 100 ns

t_DEB

—

350

—

225

—

183

ns

Setup time, STRA asserted to E fall⁽³⁾

Delay time, STRA asserted to port C data output valid

Hold time, STRA negated to port C data

3-state hold time

t_AES

t_PCD

t_PCH

t_PCZ

0

—

100

—

0

—

100

—

0

—

100

—

ns

—

10

—

10

—

10

—

150

1. V_DD= 5.0 Vdc ± 10%, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers,

respectively.)

3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.

Data Sheet

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Electrical Characteristics

MC68L11E9/E20 Peripheral Port Timing

10.12 MC68L11E9/E20 Peripheral Port Timing

1.0 MHz

2.0 MHz

Characteristic^{(1) (2)}

Symbol

Unit

Min

Max

1.0

—

Min

Max

2.0

—

Frequency of operation

E-clock frequency

f_o

dc

MHz

ns

t_CYC

t_PDSU

t_PDH

E-clock period

1000

100

500

100

Peripheral data setup time

MCU read of ports A, C, D, and E

—

ns

Peripheral data hold time

MCU read of ports A, C, D, and E

50

—

50

—

ns

Delay time, peripheral data write

t_PWD= 1/4 t_CYC+ 150 ns

t_PWD

—

250

400

—

250

275

MCU writes to port A

MCU writes to ports B, C, and D

t_IS

t_IH

Port C input data setup time

Port C input data hold time

60

—

60

—

ns

100

Delay time, E fall to STRB

t_DEB= 1/4 t_CYC+ 150 ns

t_DEB

—

400

—

275

ns

Setup time, STRA asserted to E fall⁽³⁾

Delay time, STRA asserted to port C data output valid

Hold time, STRA negated to port C data

3-state hold time

t_AES

t_PCD

t_PCH

t_PCZ

0

—

100

—

0

—

100

—

ns

—

10

—

10

—

150

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Ports C and D timing is valid for active drive. (CWOM and DWOM bits are not set in PIOC and SPCR registers,

respectively.)

3. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one more cycle.

Figure 10-7. Port Read Timing Diagram

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Electrical Characteristics

Figure 10-8. Port Write Timing Diagram

Figure 10-9. Simple Input Strobe Timing Diagram

MCU WRITE TO PORT B

E

t

PWD

NEW DATA VALID

PORT B

PREVIOUS PORT DATA

t^t_D_DE

E

B

STRB (OUT)

Figure 10-10. Simple Output Strobe Timing Diagram

(1)

1

READ PORTCL

E

tt_D_D_E_E_B_B

tt_D_DE_E_B_B

“READY”

"READY"

STRB (OUT)

STRB (0UT)

t

AES

STRA (IN)

tt_I_I_S_S

tt_I_I_H

PORT C (IN)

NOTES:

Notes:

1. After reading PIOC with STAF set

2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).

PORT C INPUT HNDSHK TIM

Figure 10-11. Port C Input Handshake Timing Diagram

Data Sheet

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Electrical Characteristics

MC68L11E9/E20 Peripheral Port Timing

1

(1)

WRITE PORTCL

E

t

PWD

PORT C (OUT)

PREVIOUS PORT DATA

NEW DATA VALID

t

DEB

“READY”

"READY"

STRB (IN)

STRB (OUT)

t

AES

STRA (IN)

NOTES:

Notes:

1. After reading PIOC with STAF set

2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).

PORT C OUTPUT HNDSHK TIM

Figure 10-12. Port C Output Handshake Timing Diagram

(1)

1

READ PORTCL

E

t

PWD

PORT C (OUT)

(DDR = 1)

DDR = 1

t

t_D_DE_E_B_B

DEB

“READY”

"READY"

STRB (OUT)

t

t_AE

A

E

S

STRA (IN)

t

PCD

t

PCH

PORT C (OUT)

OLD DATA

NEW DATA VALID

(DDR = 0)

DDR = 0

t

t_P_P

C

Z

a) STRA ACTIVE BEFORE PORTCL WRITE

STRA (IN)

t

PCH

t

PCD

PORT C (OUT)

NEW DATA VALID

(DDR = 0)

DDR = 0

t

PCZ

b) STRA ACTIVE AFTER PORTCL WRITE

NOTES:

Notes:

1. After reading PIOC with STAF set

2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).

Figure 10-13. 3-State Variation of Output Handshake Timing Diagram

(STRA Enables Output Buffer)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

181

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

10.13 Analog-to-Digital Converter Characteristics

2.0 MHz 3.0 MHz

Characteristic⁽¹⁾

Parameter⁽²⁾

Min

Absolute

Unit

Max

Resolution

Number of bits resolved by A/D converter

—

8

—

Bits

Maximum deviation from the ideal A/D transfer

characteristics

Non-linearity

—

±1/2

±1

LSB

Difference between the output of an ideal and an

actual for 0 input voltage

Zero error

—

LSB

Difference between the output of an ideal and an

actual A/D for full-scale input voltage

Full scale error

±1

Total unadjusted

error

Maximum sum of non-linearity, zero error, and

full-scale error

±1/2

Quantization

error

Uncertainty because of converter resolution

Difference between the actual input voltage and the

full-scale weighted equivalent of the binary output

code, all error sources included

Absolute

accuracy

—

±1

±2

LSB

V

Conversion

range

V_RL

V_RH

Analog input voltage range

Maximum analog reference voltage⁽³⁾

Minimum analog reference voltage⁽²⁾

V_RH

V_RL

∆V_R

V_RL

V_DD+0.1 V_DD+0.1

—

V

V_SS–0.1

V_RH

—

V_RH

—

(2)

3

Minimum difference between V_RHand V_RL

Total time to perform a single A/D conversion:

E clock

Internal RC oscillator

Conversion

time

—

t_CYC

—

32

—

t_CYC+32 t_CYC+32

µs

Conversion result never decreases with an

increase in input voltage; has no missing codes

Monotonicity

—

00

—

Guaranteed

—

Conversion result when V_In= V_RL

Conversion result when V_In= V_RH

Zero input reading

—

Hex

Full scale

reading

FF

Analog input acquisition sampling time:

E clock

Internal RC oscillator

Sample acquisition

time

t_CYC

—

12

—

12

—

12

µs

Sample/hold

capacitance

Input capacitance during sample

PE[7:0]

—

20 typical

—

pF

Input leakage on A/D pins

PE[7:0]

V_RL, V_RH

Input leakage

—

400

1.0

400

1.0

nA

µA

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= T_Lto T_H,750 kHz ≤ E ≤ 3.0 MHz, unless otherwise noted

2. Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage.

3. Performance verified down to 2.5 V ∆V_R, but accuracy is tested and guaranteed at ∆V_R= 5 V ±10%.

Data Sheet

182

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

MC68L11E9/E20 Analog-to-Digital Converter Characteristics

10.14 MC68L11E9/E20 Analog-to-Digital Converter Characteristics

Characteristic⁽¹⁾

Parameter⁽²⁾

Min

Absolute

Max

Unit

Resolution

Number of bits resolved by A/D converter

—

8

—

Bits

Maximum deviation from the ideal A/D transfer

characteristics

Non-linearity

Zero error

—

±1

LSB

Difference between the output of an ideal and an

actual for 0 input voltage

Difference between the output of an ideal and an

actual A/D for full-scale input voltage

Full scale error

Total unadjusted

error

Maximum sum of non-linearity, zero error, and

full-scale error

—

±1/2

LSB

Quantization error

Uncertainty because of converter resolution

Difference between the actual input voltage and the

full-scale weighted equivalent of the binary output

code, all error sources included

Absolute accuracy

—

±2

LSB

V_RL

V_RH

V_DD+ 0.1

V_RH

Conversion range

Analog input voltage range

—

V

V_RH

V_RL

∆V_R

Maximum analog reference voltage

Minimum analog reference voltage

Minimum difference between V_RHand V_RL

V_SS–0.1

3.0

—

Total time to perform a single

analog-to-digital conversion:

E clock

Conversion time

Monotonicity

—

t_CYC+ 32

t_CYC

—

32

—

Internal RC oscillator

µs

Conversion result never decreases with an

increase in input voltage and has no missing

codes

—

Guaranteed

—

Conversion result when V_In= V_RL

Conversion result when V_In= V_RH

Zero input reading

Full scale reading

00

—

Hex

FF

Analog input acquisition sampling time:

E clock

Internal RC oscillator

Sample acquisition

time

t_CYC

—

12

—

12

µs

Sample/hold

capacitance

Input capacitance during sample

PE[7:0]

—

20 typical

—

pF

Input leakage on A/D pins

PE[7:0]

Input leakage

—

400

1.0

nA

µA

V_RL, V_RH

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H,750 kHz ≤ E ≤ 2.0 MHz, unless otherwise noted

2. Source impedances greater than 10 kΩ affect accuracy adversely because of input leakage.

M68HC11E Family — Rev. 5

Data Sheet

183

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

10.15 Expansion Bus Timing Characteristics

1.0 MHz

2.0 MHz

3.0 MHz

Characteristic⁽¹⁾

Num

Symbol

Unit

Min

dc

Max Min Max Min Max

f_o

Frequency of operation (E-clock frequency)

1.0

—

dc

2.0

—

dc

3.0 MHz

t_CYC

PW_EL

1

2

3

Cycle time

1000

500

227

333

146

—

ns

Pulse width, E low⁽²⁾, PW_EL= 1/2 t_CYC–23 ns

Pulse width, E high⁽²⁾, PW_EH= 1/2 t_CYC–28 ns

477

—

PW_EH

472

—

20

—

222

—

20

—

141

—

20

15

—

ns

t_r

t_f

4a E and AS rise time

4b E and AS fall time

—

Address hold time^{(2) (3)a}, t_AH= 1/8 t_CYC–29.5 ns

9

t_AH

95.5

33

26

Non-multiplexed address valid time to E rise

t_AV= PW_EL–(t_ASD+ 80 ns)^{(2) (3)a}

t_AV

12

281.5

—

94

—

54

—

ns

t_DSR

t_DHR

t_DDW

17 Read data setup time

30

0

—

30

0

—

83

30

0

—

51

71

ns

Read data hold time, max = t_MAD

18

19

21

145.5

190.5

Write data delay time, t_DDW= 1/8 t_CYC+ 65.5 ns^{(2) (3)a}

Write data hold time, t_DHW= 1/8 t_CYC–29.5 ns^{(2) (3)a}

—

128

t_DHW

t_AVM

95.5

—

33

84

—

26

54

—

ns

Multiplexed address valid time to E rise

t_AVM= PW_EL–(t_ASD+ 90 ns)^{(2) (3)a}

22

24

25

271.5

Multiplexed address valid time to AS fall

t_ASL

151

—

26

33

—

13

31

—

ns

t

_ASL= PW_ASH–70 ns⁽²⁾

Multiplexed address hold time

_AHL= 1/8 t_CYC–29.5 ns^{(2) (3)b}

t_AHL

95.5

t

Delay time, E to AS rise, t_ASD= 1/8 t_CYC–9.5 ns^{(2) (3)a}

Pulse width, AS high, PW_ASH= 1/4 t_CYC–29 ns⁽²⁾

Delay time, AS to E rise, t_ASED= 1/8 t_CYC–9.5 ns^{(2) (3)b}

t_ASD

PW_ASH

t_ASED

26

27

28

115.5

221

—

53

96

53

—

31

63

31

—

ns

115.5

MPU address access time^(3)a

t_ACCA= t_CYC–(PW_EL–t_AVM) –t_DSR–t_f

t_ACCA

t_ACCE

t_MAD

29

35

36

744.5

—

442

—

307

—

192

—

196

—

111

—

ns

MPU access time, t_ACCE= PW_EH–t_DSR

Multiplexed address delay (Previous cycle MPU read)

t_MAD= t_ASD+ 30 ns^{(2) (3)a}

145.5

83

51

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Formula only for dc to 2 MHz

3. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle

are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place

of 1/8 t_CYCin the above formulas, where applicable:

(a) (1–dc) × 1/4 t_CYC

(b) dc × 1/4 t_CYC

Where:

dc is the decimal value of duty cycle percentage (high time)

Data Sheet

184

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

MC68L11E9/E20 Expansion Bus Timing Characteristics

10.16 MC68L11E9/E20 Expansion Bus Timing Characteristics

1.0 MHz

2.0 MHz

Characteristic⁽¹⁾

Num

Symbol

Unit

Min

Max

1.0

—

Min

Max

2.0

—

f_o

t_CYC

PW_EL

PW_EH

t_r

Frequency of operation (E-clock frequency)

Cycle time

dc

1000

475

470

—

dc

500

225

220

—

MHz

ns

1

2

3

Pulse width, E low, PW_EL= 1/2 t_CYC–25 ns

Pulse width, E high, PW_EH= 1/2 t_CYC–30 ns

—

ns

—

ns

4a E and AS rise time

4b E and AS fall time

25

ns

t_f

—

25

—

25

ns

Address hold time^{(2) (2)a}, t_AH= 1/8 t_CYC–30 ns

9

t_AH

95

—

33

—

ns

Non-multiplexed address valid time to E rise

t_AV

12

275

88

ns

t_AV= PW_EL–(t_ASD+ 80 ns)^(2)a

t_DSR

t_DHR

t_DDW

17 Read data setup time

30

0

—

30

0

—

88

ns

Read data hold time , max = t_MAD

18

19

21

150

195

Write data delay time, t_DDW= 1/8 t_CYC+ 70 ns^(2)a

Write data hold time, t_DHW= 1/8 t_CYC–30 ns^(2)a

—

133

t_DHW

t_AVM

95

—

33

78

—

ns

Multiplexed address valid time to E rise

t_AVM= PW_EL–(t_ASD+ 90 ns)^(2)a

22

24

268

Multiplexed address valid time to AS fall

t_ASL= PW_ASH–70 ns

t_ASL

150

—

25

—

ns

Multiplexed address hold time, t_AHL= 1/8 t_CYC–30 ns^(2)b

t_AHL

t_ASD

25

26

27

28

95

—

33

58

95

58

—

ns

Delay time, E to AS rise, t_ASD= 1/8 t_CYC–5 ns^(2)a

Pulse width, AS high, PW_ASH= 1/4 t_CYC–30 ns

120

220

120

PW_ASH

t_ASED

Delay time, AS to E rise, t_ASED= 1/8 t_CYC–5 ns^(2)b

MPU address access time^(3)a

t_ACCA= t_CYC–(PW_EL–t_AVM) –t_DSR–t_f

t_ACCA

t_ACCE

t_MAD

29

35

36

735

—

440

—

298

—

190

—

ns

MPU access time, t_ACCE= PW_EH–t_DSR

Multiplexed address delay (Previous cycle MPU read)

t_MAD= t_ASD+ 30 ns^(2)a

150

88

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle

are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place

of 1/8 t_CYCin the above formulas, where applicable:

(a) (1–dc) × 1/4 t_CYC

(b) dc × 1/4 t_CYC

Where:

dc is the decimal value of duty cycle percentage (high time).

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

185

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

1

22

33

4B

E

4A

12

9

R/W, ADDRESS

ON-MUX)

NON-MU(NLTIPLEXED

22

17

35

36

18

29

READ

ADDRESS

DATA

ADDRESS/DATA

(MUMLUTLITPILPELXEXEEDD)

1

9

2211

W

R

I

T

E

A

D

R

E

S

DATA

25

4A

24

4B

AS

28

26

27

NOTE: Measurement points shown are 20% and 70% of V

Note: Measurement points shown are 20% and 70% of V_DD

.

DD

MUX BUS TIM

Figure 10-14. Multiplexed Expansion Bus Timing Diagram

Data Sheet

186

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

Serial Peripheral Interface Timing Characteristics

10.17 Serial Peripheral Interface Timing Characteristics

E9

E20

Characteristic⁽¹⁾

Num

Symbol

Unit

Min

dc

Max

3.0

—

Min

dc

Max

3.0

—

Frequency of operation

E clock

f_o

MHz

ns

t_CYC

E-clock period

333

Operating frequency

Master

Slave

f_op(m)

f_op(s)

f_o/2

f_o

f_o/2

f_o

f_o/32

dc

f_o/128

dc

MHz

t_CYC

Cycle time

Master

Slave

t_CYC(m)

t_CYC(s)

1

2

1

32

—

2

1

128

—

Enable lead time⁽²⁾

Slave

t_lead(s)

t_CYC

2

3

1

—

1

—

Enable lag time⁽²⁾

Slave

t_lag(s)

t_CYC

Clock (SCK) high time

Master

Slave

t_w(SCKH)m

t_w(SCKH)s

t_CYC–25

16 t_CYC

—

64 t_CYC

—

4

5

6

7

ns

1/2 t_CYC–25

Clock (SCK) low time

Master

Slave

t_w(SCKL)m

t_w(SCKL)s

t_CYC–25

16 t_CYC

—

64 t_CYC

—

1/2 t_CYC–25

Data setup time (inputs)

Master

Slave

t_su(m)

t_su(s)

30

—

30

—

Data hold time (inputs)

Master

Slave

t_h(m)

t_h(s)

30

—

30

—

Slave access time

CPHA = 0

CPHA = 1

t_a

8

9

0

40

0

40

ns

Disable time (hold time

to high-impedance state)

Slave

t_dis

—

50

—

50

Data valid⁽³⁾(after enable edge)

t_v

10

11

—

0

50

—

0

50

—

ns

Data hold time (outputs)

(after enable edge)

t_ho

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Time to data active from high-impedance state

3. Assumes 200 pF load on SCK, MOSI, and MISO pins

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

187

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics

E9

E20

Characteristic⁽¹⁾

Num

Symbol

Unit

Min

dc

Max

2.0

—

Min

dc

Max

2.0

—

Frequency of operation

E clock

f_o

MHz

ns

t_CYC

E-clock period

500

Operating frequency

Master

Slave

f_op(m)

f_op(s)

f_o/2

f_o

f_o/2

f_o

f_o/32

dc

f_o/128

dc

MHz

t_CYC

Cycle time

Master

Slave

t_CYC(m)

t_CYC(s)

1

2

1

32

—

2

1

128

—

Enable lead time⁽²⁾

Slave

t_lead(s)

t_CYC

2

3

1

—

1

—

Enable lag time⁽²⁾

Slave

t_lag(s)

t_CYC

Clock (SCK) high time

Master

Slave

t_w(SCKH)m

t_w(SCKH)s

t_CYC–30

16 t_CYC

—

64 t_CYC

—

4

5

6

7

ns

1/2 t_CYC–30

Clock (SCK) low time

Master

Slave

t_w(SCKL)m

t_w(SCKL)s

t_CYC–30

16 t_CYC

—

64 t_CYC

—

1/2 t_CYC–30

Data setup time (inputs)

Master

Slave

t_su(m)

t_su(s)

40

—

40

—

Data hold time (inputs)

Master

Slave

t_h(m)

t_h(s)

40

—

40

—

Slave access time

CPHA = 0

CPHA = 1

t_a

8

9

0

50

0

50

ns

Disable time (hold time

to high-impedance state)

Slave

t_dis

—

60

—

60

Data valid⁽³⁾(after enable edge)

t_v

10

11

—

0

60

—

0

60

—

ns

Data hold time (outputs)

(after enable edge)

t_ho

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H, all timing is shown with respect to 20% V_DDand 70% V_DD, unless

otherwise noted

2. Time to data active from high-impedance state

3. Assumes 100 pF load on SCK, MOSI, and MISO pins

Data Sheet

188

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

MC68L11E9/E20 Serial Peirpheral Interface Characteristics

SS

INPUT

SS IS HELD HIGH ON MASTER.

1

SCK

CPOL = 0

INPUT

5

4

SEE NOTE

4

5

SCK

CPOL = 1

OUTPUT

6

7

MISO

INPUT

BIT 6 . . . 1

11

MSB IN

LSB IN

11 (REF)

10

MOSI

OUTPUT

BIT 6 . . . 1

MASTER MSB OUT

MASTER LSB OUT

Note: This first clock edge is generated internally but is not seen at the SCK pin.

A) SPI Master Timing (CPHA = 0)

SS

SS IS HELD HIGH ON MASTER.

INPUT

1

SCK

CPOL = 0

INPUT

5

SEE NOTE

4

5

SCK

CPOL = 1

OUTPUT

SEE NOTE

7

4

6

MISO

INPUT

BIT 6 . . . 1

11

MSB IN

LSB IN

11 (REF)

10

10 (REF)

MOSI

OUTPUT

BIT 6 . . . 1

MASTER MSB OUT

MASTER LSB OUT

Note: This first clock edge is generated internally but is not seen at the SCK pin.

B) SPI Master Timing (CPHA = 1)

Figure 10-15. SPI Timing Diagram (Sheet 1 of 2)

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

189

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

SS

INPUT

1

3

SCK

CPOL = 0

INPUT

5

4

5

2

SCK

CPOL = 1

INPUT

8

4

9

MISO

OUTPUT

SEE

NOTE

BIT 6 . . . 1

SLAVE LSB OUT

MSB OUT

7

SLAVE

6

10

11

MOSI

INPUT

BIT 6 . . . 1

MSB IN

LSB IN

Note: Not defined but normally MSB of character just received

A) SPI Slave Timing (CPHA = 0)

SS

INPUT

1

3

SCK

CPOL = 0

INPUT

5

4

5

2

SCK

CPOL = 1

INPUT

8

10

SLAVE

6

4

MSB OUT

7

9

MISO

OUTPUT

SEE

NOTE

BIT 6 . . . 1

10

SLAVE LSB OUT

11

MOSI

INPUT

BIT 6 . . . 1

MSB IN

LSB IN

Note: Not defined but normally LSB of character previously transmitted

B) SPI Slave Timing (CPHA = 1)

Figure 11-15. SPI Timing Diagram (Sheet 2 of 2)

Data Sheet

190

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Electrical Characteristics

EEPROM Characteristics

10.19 EEPROM Characteristics

Temperature Range

Characteristic⁽¹⁾

Unit

–40 to 85°C

–40 to 105°C

–40 to 125°C

Programming time⁽²⁾

< 1.0 MHz, RCO enabled

1.0 to 2.0 MHz, RCO disabled

≥ 2.0 MHz (or anytime RCO enabled)

10

20

10

15

Must use RCO

15

20

ms

Must use RCO

20

Erase time⁽²⁾

Byte, row, and bulk

10

ms

Write/erase endurance

10,000

10

10,000

10

10,000

10

Cycles

Years

Data retention

1. V_DD= 5.0 Vdc ±10%, V_SS= 0 Vdc, T_A= T_Lto T_H

2. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and

erasure when the E-clock frequency is below 1.0 MHz.

10.20 MC68L11E9/E20 EEPROM Characteristics

Temperature Range

Characteristic⁽¹⁾

Unit

–20 to 70°C

Programming time⁽²⁾

3 V, E ≤ 2.0 MHz, RCO enabled

5 V, E ≤ 2.0 MHz, RCO enabled

25

10

ms

Erase time⁽²⁾(byte, row, and bulk)

3 V, E ≤ 2.0 MHz, RCO enabled

5 V, E ≤ 2.0 MHz, RCO enabled

25

10

Write/erase endurance

10,000

10

Cycles

Years

Data retention

1. V_DD= 3.0 Vdc to 5.5 Vdc, V_SS= 0 Vdc, T_A= T_Lto T_H

2. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and

erasure.

10.21 EPROM Characteristics

Characteristics⁽¹⁾

Programming voltage⁽²⁾

Symbol

Min

11.75

—

Typ

12.25

3

Max

12.75

10

Unit

V

V_PPE

Programming current⁽³⁾

Programming time

I_PPE

mA

ms

t_EPROG

2

4

1. V_DD= 5.0 Vdc ± 10%

2. During EPROM programming of the MC68HC711E9 device, the V_PPEpin circuitry may latch-up and be damaged if the

input current is not limited to 10 mA. For more information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask

Set Errata 3 (Motorola document order number 68HC711E9MSE3.

3. Typically, a 1-kΩ series resistor is sufficient to limit the programming current for the MC68HC711E9. A 100-Ω series

resistor is sufficient to limit the programming current for the MC68HC711E20.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

191

Electrical Characteristics

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Electrical Characteristics

Data Sheet

192

M68HC11E Family — Rev. 5

MOTOROLA

Electrical Characteristics

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Data Sheet — M68HC11E Family

Section 11. Ordering Information and Mechanical Specifications

11.1 Introduction

This section provides ordering information for the E-series devices grouped by:

•

Standard devices

Custom ROM devices

Extended voltage devices

In addition, mechanical specifications for the following packaging options:

•

52-pin plastic-leaded chip carrier (PLCC)

52-pin windowed ceramic-leaded chip carrier (CLCC)

64-pin quad flat pack (QFP)

52-pin thin quad flat pack (TQFP)

56-pin shrink dual in-line package with .070-inch lead spacing (SDIP)

48-pin plastic DIP (.100-inch lead spacing), MC68HC811E2 only

11.2 Standard Device Ordering Information

Description

CONFIG

Temperature

Frequency

MC Order Number

52-pin plastic leaded chip carrier (PLCC)

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9BCFN2

MC68HC11E9BCFN3

MC68HC11E1CFN2

MC68HC11E1CFN3

MC68HC11E1VFN2

MC68HC11E1MFN2

MC68HC11E0CFN2

MC68HC11E0CFN3

MC68HC11E0VFN2

MC68HC11E0MFN2

BUFFALO ROM

No ROM

$0F

$0D

–40°C to +85°C

–40°C to +105°C

–40°C to +125°C

–40°C to +85°C

No ROM, no EEPROM

$0C

–40°C to +105°C

–40°C to +125°C

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

193

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

Description

CONFIG

Temperature

Frequency

MC Order Number

52-pin plastic leaded chip carrier (PLCC) (Continued)

2 MHz

3 MHz

2 MHz

MC68HC711E9CFN2

MC68HC711E9CFN3

MC68HC711E9VFN2

MC68HC711E9MFN2

–40°C to +85°C

OTPROM

$0F

–40°C to +105°C

–40°C to +125°C

OTPROM, enhanced security

feature

–40°C to +85°C

0°C to +70°C

2 MHz

MC68S711E9CFN2

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC711E20FN3

MC68HC711E20CFN2

MC68HC711E20CFN3

MC68HC711E20VFN2

MC68HC711E20MFN2

MC68HC811E2FN2

–40°C to +85°C

20 Kbytes OTPROM

$0F

$FF

–40°C to +105°C

–40°C to +125°C

0°C to +70°C

–40°C to +85°C

–40°C to +105°C

–40°C to +125°C

MC68HC811E2CFN2

MC68HC811E2VFN2

MC68HC811E2MFN2

No ROM, 2 Kbytes EEPROM

64-pin quad flat pack (QFP)

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9BCFU2

MC68HC11E9BCFU3

MC68HC11E1CFU2

MC68HC11E1CFU3

MC68HC11E1VFU2

MC68HC11E0CFU2

MC68HC11E0VFU2

MC68HC711E20FU3

MC68HC711E20CFU2

MC68HC711E20CFU3

MC68HC711E20VFU2

MC68HC711E20MFU2

BUFFALO ROM

$0F

$0D

$0C

–40°C to +85°C

No ROM

–40°C to +105°C

–40°C to +85°C

–40°C to +105°C

0°C to +70°°C

No ROM, no EEPROM

–40°C to +85°C

20 Kbytes OTPROM

$0F

–40°C to +105°C

–40°C to +125°C

52-pin thin quad flat pack (TQFP)

2 MHz

3 MHz

MC68HC11E9BCPB2

MC68HC11E9BCPB3

BUFFALO ROM

–40°C to +85°C

Data Sheet

194

M68HC11E Family — Rev. 5

MOTOROLA

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

Standard Device Ordering Information

Description

CONFIG

Temperature

Frequency

MC Order Number

52-pin windowed ceramic leaded chip carrier (CLCC)

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC711E9CFS2

MC68HC711E9CFS3

MC68HC711E9VFS2

MC68HC711E20FS3

MC68HC711E20CFS2

MC68HC711E20CFS3

MC68HC711E20VFS2

MC68HC711E20MFS2

–40°C to +85°C

EPROM

$0F

–40°C to +105°C

–40°C to +125°C

0°C o +70°°C

–40°C to +85°C

20 Kbytes EPROM

–40°C to +105°C

–40°C to +125°C

48-pin dual in-line package (DIP) — MC68HC811E2 only

0°C to +70°°C

2 MHz

MC68HC811E2P2

MC68HC811E2CP2

MC68HC811E2VP2

MC68HC811E2MP2

–40°C to +85°C

–40°C to +105°C

–40°C to +125°C

No ROM, 2 Kbytes EEPROM

$FF

56-pin dual in-line package with 0.70-inch lead spacing (SDIP)

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9BCB2

MC68HC11E9BCB3

MC68HC11E1CB2

MC68HC11E1CB3

MC68HC11E1VB2

MC68HC11E1MB2

MC68HC11E0CB2

MC68HC11E0CB3

MC68HC11E0VB2

MC68HC11E0MB2

BUFFALO ROM

$0F

–40°C to +85°C

No ROM

$0D

–40°C to +105°C

–40°C to +125°C

–40°C to +85°C

No ROM, no EEPROM

$0C

–40°C to +105°C

–40°C to +125°C

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

195

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

11.3 Custom ROM Device Ordering Information

Description

Temperature

Frequency

MC Order Number

52-pin plastic leaded chip carrier (PLCC)

0°C to +70°°C

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9FN3

MC68HC11E9CFN2

MC68HC11E9CFN3

MC68HC11E9VFN2

MC68HC11E9MFN2

MC68HC11E20FN3

MC68HC11E20CFN2

MC68HC11E20CFN3

MC68HC11E20VFN2

MC68HC11E20MFN2

–40°C to +85°C

Custom ROM

–40°C to +105°C

–40°C to +125°C

0°C to +70°°C

–40°C to +85°C

20 Kbytes custom ROM

64-pin quad flat pack (QFP)

Custom ROM

–40°C to +105°C

–40°C to +125°C

0°C to +70°°C

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9FU3

MC68HC11E9CFU2

MC68HC11E9CFU3

MC68HC11E9VFU2

MC68HC11E9MFU2

–40°C to +85°C

–40°C to +105°C

–40°C to +125°C

64-pin quad flat pack (continued)

20 Kbytes Custom ROM

0°C to +70°°C

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E20FU3

MC68HC11E20CFU2

MC68HC11E20CFU3

MC68HC11E20VFU2

MC68HC11E20MFU2

–40°C to +85°C

–40°C to +105°C

–40°C to +125°C

52-pin thin quad flat pack (10 mm x 10 mm)

0°C to +70°°C

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9PB3

MC68HC11E9CPB2

MC68HC11E9CPB3

MC68HC11E9VPB2

MC68HC11E9MPB2

–40°C to +85°C

Custom ROM

–40°C to +105°C

–40°C to +125°C

56-pin dual in-line package with 0.70-inch lead spacing (SDIP)

0°C to +70°°C

3 MHz

2 MHz

3 MHz

2 MHz

MC68HC11E9B3

MC68HC11E9CB2

MC68HC11E9CB3

MC68HC11E9VB2

MC68HC11E9MB2

–40°C to +85°C

Custom ROM

–40°C to +105°C

–40°C to +125°C

Data Sheet

M68HC11E Family — Rev. 5

MOTOROLA

196

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)

11.4 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)

Description

Temperature

Frequency

MC Order Number

52-pin plastic leaded chip carrier (PLCC)

MC68L11E9FN2

MC68L11E20FN2

Custom ROM

2 MHz

–20°C to +70°C

No ROM

2 MHz

MC68L11E1FN2

MC68L11E0FN2

No ROM, no EEPROM

64-pin quad flat pack (QFP)

MC68L11E9FU2

MC68L11E20FU2

Custom ROM

2 MHz

–20°C to +70°C

No ROM

2 MHz

MC68L11E1FU2

MC68L11E0FU2

No ROM, no EEPROM

52-pin thin quad flat pack (10 mm x 10 mm)

Custom ROM

2 MHz

MC68L11E9PB2

MC68L11E1PB2

MC68L11E0PB2

No ROM

No ROM, no EEPROM

56-pin dual in-line package with 0.70-inch lead spacing (SDIP)

Custom ROM

2 MHz

MC68L11E9B2

MC68L11E1B2

MC68L11E0B2

No ROM

–20°C to +70°C

No ROM, no EEPROM

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

197

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

11.5 52-Pin Plastic-Leaded Chip Carrier (Case 778)

M

S

0.007 (0.18)

T

L–M

N

B

Y ^BRK

–N–

M

S

0.007 (0.18)

T

L–M

N

U

D

Z

–M–

–L–

W

D

G1

52

1

X

S

0.010 (0.25)

T

L–M

N

V

VIEW D–D

NOTES:

M

S

1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE

TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT

MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE MEASURED

AT DATUM –T–, SEATING PLANE.

0.007 (0.18)

T

L–M

N

A

R

Z

S

N

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD

FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)

PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

E

C

0.004 (0.100)

6. THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM BY UP TO 0.012 (0.300).

DIMENSIONS R AND U ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE

BURRS AND INTERLEAD FLASH, BUT INCLUDING

ANY MISMATCH BETWEEN THE TOP AND BOTTOM

OF THE PLASTIC BODY.

–T– ^SEATING

J

G

PLANE

VIEW S

G1

S

0.010 (0.25)

T

L–M

N

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037 (0.940).

THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE

H DIMENSION TO BE SMALLER THAN 0.025 (0.635).

M

S

H

F

0.007 (0.18)

T

L–M

N

INCHES

MILLIMETERS

K1

K

DIM

A

B

C

E

MIN

MAX

0.795

0.180

0.110

0.019

MIN

19.94

4.20

2.29

0.33

MAX

20.19

4.57

2.79

0.48

0.785

0.165

0.090

0.013

M

S

T

L–M

N

F

G

H

J

K

R

U

V

W

X

Y

0.050 BSC

1.27 BSC

VIEW S

0.026

0.020

0.025

0.750

0.042

–––

0.032

–––

0.756

0.048

0.056

0.020

10

0.66

0.51

0.64

19.05

1.07

–––

0.81

–––

19.20

1.21

1.42

0.50

10

Z

2

G1

K1

0.710

0.040

0.730

–––

18.04

1.02

18.54

–––

Data Sheet

198

M68HC11E Family — Rev. 5

MOTOROLA

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B)

11.6 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B)

NOTES:

-A-

R

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION R AND N DO NOT INCLUDE

GLASS PROTRUSION. GLASS PROTRUSION

TO BE 0.25 (0.010) MAXIMUM.

M

S

B

0.51 (0.020)

T A

4. ALL DIMENSIONS AND TOLERANCES

INCLUDE LEAD TRIM OFFSET AND LEAD

INCHES

DIM MIN MAX

MILLIMETERS

MIN

19.94

4.20

MAX

20.19

5.08

A

B

C

D

F

0.785

0.165

0.017

0.026

0.795

0.200

0.021

0.032

N

-B-

0.44

0.67

0.53

0.81

G

H

J

K

N

R

S

0.050 BSC

1.27 BSC

0.090

0.006

0.035

0.735

0.690

0.130

0.010

0.045

0.756

0.730

2.29

0.16

3.30

0.25

0.89

1.14

18.67

17.53

19.20

18.54

M

S

0.51 (0.020)

T A

B

F

K

H

0.15 (0.006)

C

G

-T- SEATING

PLANE

J

D 52 PL

M

S

B

0.18 (0.007)

T A

S

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

199

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

11.7 64-Pin Quad Flat Pack (Case 840C)

B

L

–A–, –B–, –D–

33

48

32

49

P

B

L

V

DETAIL A

F

BASE

METAL

DETAIL A

J

N

17

64

D

16

1

M

S

D

0.20 (0.008)

C A–B

–D–

SECTION B–B

A

NOTES:

M

S

0.20 (0.008)

H A–B

D

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

0.05 (0.002) A–B

S

M

S

C A–B

0.20 (0.008)

4. DATUMS A–B AND –D– TO BE DETERMINED AT

DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –C–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25

(0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

–H–

DATUM PLANE

C

E

H

DETERMINED AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED 0.53

(0.021). DAMBAR CANNOT BE LOCATED ON THE

LOWER RADIUS OR THE FOOT.

0.10 (0.004)

SEATING PLANE

–C–

G

DETAIL C

8. DIMENSION K IS TO BE MEASURED FROM THE

THEORETICAL INTERSECTION OF LEAD FOOT

AND LEG CENTERLINES.

U

MILLIMETERS

INCHES

M

DIM MIN

MAX

14.10

2.46

MIN

MAX

0.555

0.097

0.018

0.094

–––

T

A

B

C

D

E

F

13.90

2.07

0.30

2.00

0.30

0.547

0.081

0.012

0.079

0.45

2.40

R

––– 0.012

G

H

J

K

L

M

N

P

Q

R

S

T

0.80 BSC

0.031 BSC

0.067

0.130

0.50

0.250

0.230

0.66

0.003

0.005

0.020

0.010

0.090

0.026

Q

12.00 REF

0.472 REF

SEATING PLANE

5

0.130

10

0.170

5

0.005

10

0.007

K

0.40 BSC

0.016 BSC

2

0.13

16.20

8

0.30

16.60

8

0.005

0.638

0.012

0.654

X

M

0.20 REF

0.008 REF

U

V

X

0

16.20

1.10

–––

16.60

1.30

0

–––

0.654

0.051

0.638

0.043

DETAIL C

Data Sheet

200

M68HC11E Family — Rev. 5

MOTOROLA

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

52-Pin Thin Quad Flat Pack (Case 848D)

11.8 52-Pin Thin Quad Flat Pack (Case 848D)

4X

4X TIPS

0.20 (0.008) H L–M

N

0.20 (0.008) T L–M N

–X–

X=L, M, N

52

40

C

1

39

L

AB

G

3X VIEW Y

–L–

–M–

B1

B

V

VIEW Y

F

BASE METAL

PLATING

V1

13

27

J

U

14

26

–N–

D

A1

M

S

0.13 (0.005)

T

L–M

N

S1

SECTION AB–AB

A

ROTATED 90 CLOCKWISE

S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –L–, –M– AND –N– TO BE DETERMINED

AT DATUM PLANE –H–.

4X θ2

4X θ3

C

0.10 (0.004)

T

–H–

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –T–.

–T–

SEATING

PLANE

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.25 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE -H-.

VIEW AA

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46

(0.018). MINIMUM SPACE BETWEEN

PROTRUSION AND ADJACENT LEAD OR

PROTRUSION 0.07 (0.003).

S

0.05 (0.002)

MILLIMETERS

DIM MIN MAX

10.00 BSC

INCHES

MIN MAX

0.394 BSC

0.197 BSC

0.394 BSC

0.197 BSC

W

2 X R R1

θ1

A

A1

B

5.00 BSC

10.00 BSC

5.00 BSC

0.25 (0.010)

C2

B1

C

θ

–––

0.05

1.30

0.20

0.45

0.22

1.70

–––

0.002

0.051

0.008

0.018

0.009

0.067

GAGE PLANE

C1

C2

D

E

F

0.20

1.50

0.40

0.75

0.35

0.008

0.059

0.016

0.030

0.014

K

E

C1

G

J

0.65 BSC

0.026 BSC

0.07

0.20

0.003

0.008

Z

K

R1

S

S1

U

0.50 REF

0.020 REF

0.08

0.20

0.003

0.008

VIEW AA

12.00 BSC

6.00 BSC

0.09 0.16

0.472 BSC

0.236 BSC

0.004 0.006

V

12.00 BSC

6.00 BSC

0.20 REF

1.00 REF

0.472 BSC

0.236 BSC

0.008 REF

0.039 REF

V1

W

Z

θ

0

12

7

–––

0

12

7

–––

θ1

θ2

θ3

REF

13

REF

13

5

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

201

Ordering Information and Mechanical Specifications

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Ordering Information and Mechanical Specifications

11.9 56-Pin Dual in-Line Package (Case 859)

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

56

29

28

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

FLASH. MAXIMUM MOLD FLASH 0.25 (0.010)

–B–

INCHES

DIM MIN MAX

MILLIMETERS

1

MIN

51.69

13.72

3.94

MAX

52.45

14.22

5.08

A

B

C

D

E

F

2.035

0.540

0.155

0.014

2.065

0.560

0.200

0.022

L

0.36

0.56

H

C

0.035 BSC

0.89 BSC

0.032

0.046

0.81

1.17

G

H

J

K

L

0.070 BSC

0.300 BSC

1.778 BSC

7.62 BSC

–T–

SEATING

PLANE

K

0.008

0.115

0.015

0.135

0.20

2.92

0.38

3.43

0.600 BSC

15.24 BSC

N

G

M

F

M

N

0

0.020

15

0.040

0

0.51

15

1.02

E

J 56 PL

D 56 PL

0.25 (0.010)

M

S

T A

M

S

T B

0.25 (0.010)

11.10 48-Pin Plastic DIP (Case 767)

NOTE:

The MC68HC811E2 is the only member of the E series that is offered in a 48-pin

plastic dual in-line package.

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

-A-

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED

PARALLEL.

48

1

25

4. DIMENSIONSAANDBDONOTINCLUDEMOLDFLASH.

MAXIMUM MOLD FLASH 0.25 (0.010).

-B-

TIP TAPER

INCHES

DIM MIN MAX

MILLIMETERS

MIN

61.34

13.72

3.94

MAX

62.10

14.22

5.08

24

A

B

C

D

F

2.415

0.540

0.155

0.014

0.040

2.445

0.560

0.200

0.022

0.060

DETAIL X

L

0.36

1.02

0.55

1.52

C

G

H

J

K

L

0.100 BSC

0.070 BSC

2.54 BSC

1.79 BSC

0.008

0.115

0.015

0.150

0.20

2.92

0.38

3.81

0.600 BSC

15.24 BSC

15

0.51

-T-

SEATING

PLANE

K

M

N

0

0.020

15

×

0.040

0

×

1.01

M 48 PL

N

DETAIL X

G

F

J 48 PL

D 32 PL

M

S

T B

0.25 (0.010)

M

S

T A

0.51 (0.020)

Data Sheet

202

M68HC11E Family — Rev. 5

MOTOROLA

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Data Sheet — M68HC11E Family

Appendix A. Development Support

A.1 Introduction

This section provides information on the development support offered for the

E-series devices.

A.2 Motorola M68HC11 E-Series Development Tools

SPGMR

Programming

Adapter⁽³⁾

Emulation

Module^{(1) (2)}

Flex

Cable^{(1) (2)}

MMDS11

Target Head^{(1) (2)}

Device

Package

52 FN

52 PB

56 B

M68EM11E20

M68CBL11C

M68CBL11B

M68CBL11C

M68CBL11B

M68CBL11C

M68TC11E20FN52

M68TC11E20PB52

M68TC11E20B56

M68TC11E20FU64

M68TC11E20FN52

M68TC11E20FU64

M68TB11E20P48

M68TC11E20FN52

M68PA11E20FN52

M68PA11E20PB52

M68PA11E20B56

M68PA11E20FU64

M68PA11E20FN52

M68PA11E20FU64

M68PA11A8P48

MC68HC11E9

MC68HC711E9

64 FU

52 FN

64 FU

48 P

MC68HC11E20

MC68HC711E20

MC68HC811E2

52 FN

M68PA11E20FN52

1. Each MMDS11 system consists of a system console (M68MMDS11), an emulation module, a flex cable, and a target head.

2. A complete EVS consists of a platform board (M68HC11PFB), an emulation module, a flex cable, and a target head.

3. Each SPGMR system consists of a universal serial programmer (M68SPGMR11) and a programming adapter. It can be

used alone or in conjunction with the MMDS11.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Development Support

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Development Support

A.3 EVS — Evaluation System

The EVS is an economical tool for designing, debugging, and evaluating target

systems based on the M68HC11. EVS features include:

•

Monitor/debugger firmware

One-line assembler/disassembler

Host computer download capability

Dual memory maps:

–

64-Kbyte monitor map that includes 16 Kbytes of monitor EPROM

M68HC11 E-series user map that includes 64 Kbytes of emulation RAM

•

MCU extension input/output (I/O) port for single-chip, expanded, and

special-test operation modes

•

RS-232C terminal and host I/O ports

Logic analyzer connector

A.4 Motorola Modular Development System (MMDS11)

The M68MMDS11 Motorola modular development system (MMDS11) is an

emulator system for developing embedded systems based on an M68HC11

microcontroller unit (MCU). The MMDS11 provides a bus state analyzer (BSA) and

real-time memory windows. The unit's integrated development environment

includes an editor, an assembler, user interface, and source-level debug. These

features significantly reduce the time necessary to develop and debug an

embedded MCU system. The unit's compact size requires a minimum of desk

space.

The MMDS11 is one component of Motorola's modular approach to MCU-based

product development. This modular approach allows easy configuration of the

MMDS11 to fit a wide range of requirements. It also reduces development system

cost by allowing the user to purchase only the modular components necessary to

support the particular MCU derivative.

MMDS11 features include:

•

Real-time, non-intrusive, in-circuit emulation at the MCU’s operating

frequency

•

Real-time bus state analyzer

–

8 K x 64 real-time trace buffer

Display of real-time trace data as raw data, disassembled instructions,

raw data and disassembled instructions, or assembly-language source

code

–

Four hardware triggers for commencing trace and to provide breakpoints

Nine triggering modes

As many as 8190 pre- or post-trigger points for trace data

Data Sheet

204

M68HC11E Family — Rev. 5

Development Support

MOTOROLA

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Development Support

–

16 general-purpose logic clips, four of which can be used to trigger the

bus state analyzer sequencer

16-bit time tag or an optional 24-bit time tag that reduces the logic clips

traced from 16 to eight

•

Four data breakpoints (hardware breakpoints)

Hardware instruction breakpoints over either the 64-Kbyte M68HC11

memory map or over a 1-Mbyte bank switched memory map

•

32 real-time variables, nine of which can be displayed in the variables

window. These variables may be read or written while the MCU is running

32 bytes of real-time memory can be displayed in the memory window. This

memory may be read or written while the MCU is running

•

64 Kbytes of fast emulation memory (SRAM)

Current-limited target input/output connections

Six software-selectable oscillator clock sources: five internally generated

frequencies and an external frequency via a bus analyzer logic clip

•

Command and response logging to MS-DOS^®disk files to save session

history

SCRIPT command for automatic execution of a sequence of MMDS11

commands

Assembly or C-language source-level debugging with global variable

viewing

Host/emulator communications speeds as high as 57,600 baud for quick

program loading

Extensive on-line MCU information via the CHIPINFO command. View

memory map, vectors, register, and pinout information pertaining to the

device being emulated

•

Host software supports:

–

An editor

An assembler and user interface

Source-level debug

Bus state analysis

IBM^®mouse

^®IBM is a registered trademark of International Business Machines Corporation.

^®MS-DOS is a registered trademark of Microsoft Corporation.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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Development Support

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Development Support

A.5 SPGMR11 — Serial Programmer for M68HC11 MCUs

The SPGMR11 is a modular EPROM/EEPROM programming tool for all M68HC11

devices. The programmer features interchangeable adapters that allow

programming of various M68HC11 package types.

Programmer features include:

•

Programs M68HC11 Family devices that contain an EPROM or EEPROM

array.

•

Can be operated as a stand-alone programmer connected to a host

computer or connected between a host computer and the M68HC11

modular development system (MMDS11) station module

•

Uses plug-in programming adapters to accommodate a variety of MCU

devices and packages

On-board programming voltage circuit eliminates the need for an external

12-volt supply.

•

Includes programming software and a user’s manual

Includes a +5-volt power cable and a DB9 to DB25 connector adapter

Data Sheet

206

M68HC11E Family — Rev. 5

Development Support

MOTOROLA

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Data Sheet — M68HC11E Family

Appendix B. EVBU Schematic

Refer to Figure B-1 for a schematic diagram of the M68HC11EVBU Universal

Evaluation Board. This diagram is included for reference only.

M68HC11E Family — Rev. 5

MOTOROLA

Data Sheet

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EVBU Schematic

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EVBU Schematic

T E N 1 O

Data Sheet

208

M68HC11E Family — Rev. 5

MOTOROLA

EVBU Schematic

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Order this document

by AN1060/D

Rev. 1.0

Motorola Semiconductor Application Note

AN1060

M68HC11 Bootstrap Mode

By Jim Sibigtroth, Mike Rhoades, and John Langan

Austin, Texas

Introduction

The M68HC11 Family of MCUs (microcontroller units) has a bootstrap

mode that allows a user-defined program to be loaded into the internal

random-access memory (RAM) by way of the serial communications

interface (SCI); the M68HC11 then executes this loaded program. The

loaded program can do anything a normal user program can do as well

as anything a factory test program can do because protected control bits

are accessible in bootstrap mode. Although the bootstrap mode is a

single-chip mode of operation, expanded mode resources are

accessible because the mode control bits can be changed while

operating in the bootstrap mode.

This application note explains the operation and application of the

M68HC11 bootstrap mode. Although basic concepts associated with this

mode are quite simple, the more subtle implications of these functions

require careful consideration. Useful applications of this mode are

overlooked due to an incomplete understanding of bootstrap mode.

Also, common problems associated with bootstrap mode could be

avoided by a more complete understanding of its operation and

implications.

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Application Note

Topics discussed in this application note include:

•

Basic operation of the M68HC11 bootstrap mode

General discussion of bootstrap mode uses

Detailed explanation of on-chip bootstrap logic

Detailed explanation of bootstrap firmware

Bootstrap firmware vs. EEPROM security

Incorporating the bootstrap mode into a system

Driving bootstrap mode from another M68HC11

Driving bootstrap mode from a personal computer

Common bootstrap mode problems

Variations for specific versions of M68HC11

Commented listings for selected M68HC11 bootstrap ROMs

Basic Bootstrap Mode

This section describes only basic functions of the bootstrap mode. Other

functions of the bootstrap mode are described in detail in the remainder

of this application note.

When an M68HC11 is reset in bootstrap mode, the reset vector is

fetched from a small internal read-only memory (ROM) called the

bootstrap ROM or boot ROM. The firmware program in this boot ROM

then controls the bootloading process, in this manner:

•

First, the on-chip SCI (serial communications interface) is

initialized. The first character received ($FF) determines which of

two possible baud rates should be used for the remaining

characters in the download operation.

•

Next, a binary program is received by the SCI system and is stored

in RAM.

Finally, a jump instruction is executed to pass control from the

bootloader firmware to the user’s loaded program.

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Bootstrap mode is useful both at the component level and after the MCU

has been embedded into a finished user system.

At the component level, Motorola uses bootstrap mode to control a

monitored burn-in program for the on-chip electrically erasable

programmable read-only memory (EEPROM). Units to be tested are

loaded into special circuit boards that each hold many MCUS. These

boards are then placed in burn-in ovens. Driver boards outside the

ovens download an EEPROM exercise and diagnostic program to all

MCUs in parallel. The MCUs under test independently exercise their

internal EEPROM and monitor programming and erase operations. This

technique could be utilized by an end user to load program information

into the EPROM or EEPROM of an M68HC11 before it is installed into

an end product. As in the burn-in setup, many M68HC11s can be gang

programmed in parallel. This technique can also be used to program the

EPROM of finished products after final assembly.

Motorola also uses bootstrap mode for programming target devices on

the M68HC11 evaluation modules (EVM). Because bootstrap mode is a

privileged mode like special test, the EEPROM-based configuration

register (CONFIG) can be programmed using bootstrap mode on the

EVM.

The greatest benefits from bootstrap mode are realized by designing the

finished system so that bootstrap mode can be used after final

assembly. The finished system need not be a single-chip mode

application for the bootstrap mode to be useful because the expansion

bus can be enabled after resetting the MCU in bootstrap mode. Allowing

this capability requires almost no hardware or design cost and the

addition of this capability is invisible in the end product until it is needed.

The ability to control the embedded processor through downloaded

programs is achieved without the disassembly and chip-swapping

usually associated with such control. This mode provides an easy way

to load non-volatile memories such as EEPROM with calibration tables

or to program the application firmware into a one-time programmable

(OTP) MCU after final assembly.

Another powerful use of bootstrap mode in a finished assembly is for

final test. Short programs can be downloaded to check parts of the

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Application Note

system, including components and circuitry external to the embedded

MCU. If any problems appear during product development, diagnostic

programs can be downloaded to find the problems, and corrected

routines can be downloaded and checked before incorporating them into

the main application program.

Bootstrap mode can also be used to interactively calibrate critical analog

sensors. Since this calibration is done in the final assembled system, it

can compensate for any errors in discrete interface circuitry and cabling

between the sensor and the analog inputs to the MCU. Note that this

calibration routine is a downloaded program that does not take up space

in the normal application program.

Bootstrap Mode Logic

In the M68HC11 MCUs, very little logic is dedicated to the bootstrap

mode. Consequently, this mode adds almost no extra cost to the MCU

system. The biggest piece of circuitry for bootstrap mode is the small

boot ROM. This ROM is 192 bytes in the original MC68HC11A8, but

some of the newest members of the M68HC11 Family, such as the

MC68HC711K4, have as much as 448 bytes to accommodate added

features. Normally, this boot ROM is present in the memory map only

when the MCU is reset in bootstrap mode to prevent interference with

the user’s normal memory space. The enable for this ROM is controlled

by the read boot ROM (RBOOT) control bit in the highest priority

interrupt (HPRIO) register. The RBOOT bit can be written by software

whenever the MCU is in special test or special bootstrap modes; when

the MCU is in normal modes, RBOOT reverts to 0 and becomes a read-

only bit. All other logic in the MCU would be present whether or not there

was a bootstrap mode.

Figure 1 shows the composite memory map of the MC68HC711E9 in its

four basic modes of operation, including bootstrap mode. The active

mode is determined by the mode A (MDA) and special mode (SMOD)

control bits in the HPRIO control register. These control bits are in turn

controlled by the state of the mode A (MODA) and mode B (MODB) pins

during reset. Table 1 shows the relationship between the state of these

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Application Note

pins during reset, the selected mode, and the state of the MDA, SMOD,

and RBOOT control bits. Refer to the composite memory map and

information in Table 1 for the following discussion.

The MDA control bit is determined by the state of the MODA pin as the

MCU leaves reset. MDA selects between single-chip and expanded

operating modes. When MDA is 0, a single-chip mode is selected, either

normal single-chip mode or special bootstrap mode. When MDA is 1, an

expanded mode is selected, either normal expanded mode or special

test mode.

The SMOD control bit is determined by the inverted state of the MODB

pin as the MCU leaves reset. SMOD controls whether a normal mode or

a special mode is selected. When SMOD is 0, one of the two normal

modes is selected, either normal single-chip mode or normal expanded

mode. When SMOD is 1, one of the two special modes is selected, either

special bootstrap mode or special test mode. When either special mode

is in effect (SMOD = 1), certain privileges are in effect, for instance, the

ability to write to the mode control bits and fetching the reset and

interrupt vectors from $BFxx rather than $FFxx.

Table 1. Mode Selection Summary

Input Pins

Control Bits in HPRIO

Mode Selected

MODB

MODA

RBOOT

SMOD

MDA

1

0

1

Normal single chip

Normal expanded

Special bootstrap

Special test

0

1

0

1

0

1

0

1

The alternate vector locations are achieved by simply driving address bit

A14 low during all vector fetches if SMOD = 1. For special test mode, the

alternate vector locations assure that the reset vector can be fetched

from external memory space so the test system can control MCU

operation. In special bootstrap mode, the small boot ROM is enabled in

the memory map by RBOOT = 1 so the reset vector will be fetched from

this ROM and the bootloader firmware will control MCU operation.

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RBOOT is reset to 1 in bootstrap mode to enable the small boot ROM.

In the other three modes, RBOOT is reset to 0 to keep the boot ROM out

of the memory map. While in special test mode, SMOD = 1, which allows

the RBOOT control bit to be written to 1 by software to enable the boot

ROM for testing purposes.

Boot ROM Firmware

The main program in the boot ROM is the bootloader, which is

automatically executed as a result of resetting the MCU in bootstrap

mode. Some newer versions of the M68HC11 Family have additional

utility programs that can be called from a downloaded program. One

utility is available to program EPROM or OTP versions of the M68HC11.

A second utility allows the contents of memory locations to be uploaded

to a host computer. In the MC68HC711K4 boot ROM, a section of code

is used by Motorola for stress testing the on-chip EEPROM. These test

and utility programs are similar to self-test ROM programs in other

MCUs except that the boot ROM does not use valuable space in the

normal memory map.

Bootstrap firmware is also involved in an optional EEPROM security

function on some versions of the M68HC11. This EEPROM security

feature prevents a software pirate from seeing what is in the on-chip

EEPROM. The secured state is invoked by programming the no security

(NOSEC) EEPROM bit in the CONFIG register. Once this NOSEC bit is

programmed to 0, the MCU will ignore the mode A pin and always come

out of reset in normal single-chip mode or special bootstrap mode,

depending on the state of the mode B pin. Normal single-chip mode is

the usual way a secured part would be used. Special bootstrap mode is

used to disengage the security function (only after the contents of

EEPROM and RAM have been erased). Refer to the M68HC11

Reference Manual, Motorola document order number M68HC11RM/AD,

for additional information on the security mode and complete listings of

the boot ROMs that support the EEPROM security functions.

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Automatic Selection of Baud Rate

The bootloader program in the MC68HC711E9 accommodates either of

two baud rates.

•

The higher of these baud rates (7812 baud at a 2-MHz E-clock

rate) is used in systems that operate from a binary frequency

crystal such as 2 Hz (8.389 MHz). At this crystal frequency, the

23

baud rate is 8192 baud, which was used extensively in automotive

applications.

•

The second baud rate available to the M68HC11 bootloader is

1200 baud at a 2-MHz E-clock rate. Some of the newest versions

of the M68HC11, including the MC68HC11F1 and

MC68HC117K4, accommodate other baud rates using the same

differentiation technique explained here. Refer to the reference

numbers in square brackets in Figure 2 during the following

explanation.

NOTE: Software can change some aspects of the memory map after reset.

Figure 2 shows how the bootloader program differentiates between the

default baud rate (7812 baud at a 2-MHz E-clock rate) and the alternate

baud rate (1200 baud at a 2-MHz E-clock rate). The host computer

sends an initial $FF character, which is used by the bootloader to

determine the baud rate that will be used for the downloading operation.

The top half of Figure 2 shows normal reception of $FF. Receive data

samples at [1] detect the falling edge of the start bit and then verify the

start bit by taking a sample at the center of the start bit time. Samples

are then taken at the middle of each bit time [2] to reconstruct the value

of the received character (all 1s in this case). A sample is then taken at

the middle of the stop bit time as a framing check (a 1 is expected) [3].

Unless another character immediately follows this $FF character, the

receive data line will idle in the high state as shown at [4].

The bottom half of Figure 2 shows how the receiver will incorrectly

receive the $FF character that is sent from the host at 1200 baud.

Because the receiver is set to 7812 baud, the receive data samples are

taken at the same times as in the upper half of Figure 2. The start bit at

1200 baud [5] is 6.5 times as long as the start bit at 7812 baud [6].

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$0000

$01FF

(MAY BE REMAPPED

TO ANY 4K BOUNDARY)

512-BYTE

RAM

EXTERNAL

$1000

$103F

(MAY BE REMAPPED

TO ANY 4K BOUNDARY)

64-BYTE

REGISTER

BLOCK

EXTERNAL

(MAY BE DISABLED

BY AN EEPROM BIT)

512-BYTE

EEPROM

$B600

$B7FF

$BFC0

BOOT

ROM

SPECIAL

MODE

VECTORS

EXTERNAL

$BF00

$BFC0

$BFFF

(MAY BE DISABLED

BY AN EEPROM BIT)

$D000

12K USER

EPROM

(or OTP)

$FFC0

NORMAL

MODE

VECTORS

$FFC0

$FFFF

SINGLE

CHIP

$FFFF

EXPANDED

MULTIPLEXED

SPECIAL

BOOTSTRAP

SPECIAL

TEST

MODA = 0

MODB = 1

MODA = 1

MODB = 1

MODA = 0

MODB = 0

MODA = 1

MODB = 0

NOTE: Software can change some aspects of the memory map after reset.

Figure 1. MC68HC711E9 Composite Memory Map

[4]

START BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP Tx DATA LINE IDLES HIGH

[6]

$FF CHARACTER

@ 7812 BAUD

Rx DATA SAMPLES

[3]

S

0

1

[2]

[1]

$FF

[5]

$FF CHARACTER

@ 1200 BAUD

START

BIT 0

BIT 1

Rx DATA SAMPLES

( FOR 7812 BAUD )

[8]

0

[12]

[11]

S

0

[7]

0

?

1

[9]

$C0

or $E0 [10]

Figure 2. Automatic Detection of Baud Rate

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Samples taken at [7] detect the failing edge of the start bit and verify it is

a logic 0. Samples taken at the middle of what the receiver interprets as

the first five bit times [8] detect logic 0s. The sample taken at the middle

of what the receiver interprets as bit 5 [9] may detect either a 0 or a 1

because the receive data has a rising transition at about this time. The

samples for bits 6 and 7 detect 1s, causing the receiver to think the

received character was $C0 or $E0 [10] at 7812 baud instead of the $FF

which was sent at 1200 baud. The stop bit sample detects a 1 as

expected [11], but this detection is actually in the middle of bit 0 of the

1200 baud $FF character. The SCI receiver is not confused by the rest

of the 1200 baud $FF character because the receive data line is high [12]

just as it would be for the idle condition. If a character other than $FF is

sent as the first character, an SCI receive error could result.

Main Bootloader Program

Figure 3 is a flowchart of the main bootloader program in the

MC68HC711E9. This bootloader demonstrates the most important

features of the bootloaders used on all M68HC11 Family members. For

complete listings of other M68HC11 versions, refer to Listing 3.

MC68HC711E9 Bootloader ROM at the end of this application note,

and to Appendix B of the M68HC11 Reference Manual, Motorola

document order number M68HC11RM/AD.

The reset vector in the boot ROM points to the start [1] of this program.

The initialization block [2] establishes starting conditions and sets up the

SCI and port D. The stack pointer is set because there are push and pull

instructions in the bootloader program. The X index register is pointed at

the start of the register block ($1000) so indexed addressing can be

used. Indexed addressing takes one less byte of ROM space than

extended instructions, and bit manipulation instructions are not available

in extended addressing forms. The port D wire-OR mode (DWOM) bit in

the serial peripheral interface control register (SPCR) is set to configure

port D for wired-OR operation to minimize potential conflicts with

external systems that use the PD1/TxD pin as an input. The baud rate

for the SCI is initially set to 7812 baud at a 2-MHz E-clock rate but can

automatically switch to 1200 baud based on the first character received.

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Application Note

The SCI receiver and transmitter are enabled. The receiver is required

by the bootloading process, and the transmitter is used to transmit data

back to the host computer for optional verification. The last item in the

initialization is to set an intercharacter delay constant used to terminate

the download when the host computer stops sending data to the

MC68HC711E9. This delay constant is stored in the timer output

compare 1 (TOC1) register, but the on-chip timer is not used in the

bootloader program. This example illustrates the extreme measures

used in the bootloader firmware to minimize memory usage. However,

such measures are not usually considered good programming technique

because they are misleading to someone trying to understand the

program or use it as an example.

After initialization, a break character is transmitted [3] by the SCI. By

connecting the TxD pin to the RxD pin (with a pullup because of port D

wired-OR mode), this break will be received as a $00 character and

cause an immediate jump [4] to the start of the on-chip EEPROM ($B600

in the MC68HC711E9). This feature is useful to pass control to a

program in EEPROM essentially from reset. Refer to Common

Bootstrap Mode Problems before using this feature.

If the first character is received as $FF, the baud rate is assumed to be

the default rate (7812 baud at a 2-MHz E-clock rate). If $FF was sent at

1200 baud by the host, the SCI will receive the character as $E0 or $C0

because of the baud rate mismatch, and the bootloader will switch to

1200 baud [5] for the rest of the download operation. When the baud rate

is switched to 1200 baud, the delay constant used to monitor the

intercharacter delay also must be changed to reflect the new character

time.

At [6], the Y index register is initialized to $0000 to point to the start of

on-chip RAM. The index register Y is used to keep track of where the

next received data byte will be stored in RAM. The main loop for loading

begins at [7].

The number of data bytes in the downloaded program can be any

number between 0 and 512 bytes (the size of on-chip RAM). This

procedure is called "variable-length download" and is accomplished by

ending the download sequence when an idle time of at least four

character times occurs after the last character to be downloaded. In

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Application Note

M68HC11 Family members which have 256 bytes of RAM, the download

length is fixed at exactly 256 bytes plus the leading $FF character.

The intercharacter delay counter is started [8] by loading the delay

constant from TOC1 into the X index register. The 19-E-cycle wait loop

is executed repeatedly until either a character is received [9] or the

allowed intercharacter delay time expires [10]. For 7812 baud, the delay

constant is 10,241 E cycles (539 x 19 E cycles per loop). Four character

times at 7812 baud is 10,240 E cycles (baud prescale of 4 x baud divider

of 4 x 16 internal SCI clocks/bit time x 10 bit times/character x 4

character times). The delay from reset to the initial $FF character is not

critical since the delay counter is not started until after the first character

($FF) is received.

To terminate the bootloading sequence and jump to the start of RAM

without downloading any data to the on-chip RAM, simply send $FF and

nothing else. This feature is similar to the jump to EEPROM at [4] except

the $FF causes a jump to the start of RAM. This procedure requires that

the RAM has been loaded with a valid program since it would make no

sense to jump to a location in uninitialized memory.

After receiving a character, the downloaded byte is stored in RAM [11].

The data is transmitted back to the host [12] as an indication that the

download is progressing normally. At [13], the RAM pointer is

incremented to the next RAM address. If the RAM pointer has not

passed the end of RAM, the main download loop (from [7] to [14]) is

repeated.

When all data has been downloaded, the bootloader goes to [16]

because of an intercharacter delay timeout [10] or because the entire

512-byte RAM has been filled [15]. At [16], the X and Y index registers

are set up for calling the PROGRAM utility routine, which saves the user

from having to do this in a downloaded program. The PROGRAM utility

is fully explained in EPROM Programming Utility. The final step of the

bootloader program is to jump to the start of RAM [17], which starts the

user’s downloaded program.

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FROM RESET

IN BOOT MODE

[1]

START

[2]

INITIALIZATION:

SP = TOP OF RAM ($01FF)

X = START OF REGS ($1000)

SPCR = $20 (SET DWOM BIT)

BAUD = $A2 (÷ 4; ÷ 4) (7812.5 BAUD @ 2 MHz)

SCCR2 = $C0 (Tx & Rx ON)

TOC1 = DELAY CONSTANT (539 = 4 SCI CHARACTER TIMES)

[3]

SEND BREAK

NO

RECEIVED FIRST CHAR YET ?

YES

[4]

JUMP TO START

OF EEPROM ($B600)

YES

FIRST CHAR = $00 ?

NO

NOTZERO

NOTE THAT A BREAK

CHARACTER IS ALSO

RECEIVED AS $00

YES

FIRST CHAR = $FF ?

NO

[5]

SWITCH TO SLOWER SCI RATE...

BAUD = $33 (÷13; ÷ 8) (1200 BAUD @ 2 MHz)

CHANGE DELAY CONSTANT...

TOC1 = 3504 (4 SCI CHARACTER TIMES)

BAUDOK

[6]

POINT TO START OF RAM ( Y = $0000 )

[7]

WAIT

[8]

INITIALIZE TIMEOUT COUNT

WTLOOP

[9]

YES

RECEIVE DATA READY ?

NO

LOOP =

19

CYCLES

DECREMENT TIMEOUT COUNT

NO

TIMED OUT YET ?

[10]

YES

[11]

STORE RECEIVED DATA TO RAM ( ,Y )

TRANSMIT (ECHO) FOR VERIFY

POINT AT NEXT RAM LOCATION

[12]

[13]

[14]

NO

PAST END OF RAM ?

YES

[15]

STAR

SET UP FOR PROGRAM UTILITY:

X = PROGRAMMING TIME CONSTANT

Y = START OF EPROM

[16]

JUMP TO START

OF RAM ($0000)

[17]

Figure 3. MC68HC711E9 Bootloader Flowchart

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Application Note

UPLOAD Utility

The UPLOAD utility subroutine transfers data from the MCU to a host

computer system over the SCI serial data link.

NOTE: Only EPROM versions of the M68HC11 include this utility.

Verification of EPROM contents is one example of how the UPLOAD

utility could be used. Before calling this program, the Y index register is

loaded (by user firmware) with the address of the first data byte to be

uploaded. If a baud rate other than the current SCI baud rate is to be

used for the upload process, the user’s firmware must also write to the

baud register. The UPLOAD program sends successive bytes of data

out the SCI transmitter until a reset is issued (the upload loop is infinite).

For a complete commented listing example of the UPLOAD utility, refer

to Listing 3. MC68HC711E9 Bootloader ROM.

EPROM Programming Utility

The EPROM programming utility is one way of programming data into

the internal EPROM of the MC68HC711E9 MCU. An external 12-V

programming power supply is required to program on-chip EPROM. The

simplest way to use this utility program is to bootload a 3-byte program

consisting of a single jump instruction to the start of the PROGRAM utility

program ($BF00). The bootloader program sets the X and Y index

registers to default values before jumping to the downloaded program

(see [16] at the bottom of Figure 3). When the host computer sees the

$FF character, data to be programmed into the EPROM is sent, starting

with the character for location $D000. After the last byte to be

programmed is sent to the MC68HC711E9 and the corresponding

verification data is returned to the host, the programming operation is

terminated by resetting the MCU.

The number of bytes to be programmed, the first address to be

programmed, and the programming time can be controlled by the user if

values other than the default values are desired.

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Application Note

To understand the detailed operation of the EPROM programming utility,

refer to Figure 4 during the following discussion. Figure 4 is composed

of three interrelated parts. The upper-left portion shows the flowchart of

the PROGRAM utility running in the boot ROM of the MCU. The upper-

right portion shows the flowchart for the user-supplied driver program

running in the host computer. The lower portion of Figure 4 is a timing

sequence showing the relationship of operations between the MCU and

the host computer. Reference numbers in the flowcharts in the upper

half of Figure 4 have matching numbers in the lower half to help the

reader relate the three parts of the figure.

The shaded area [1] refers to the software and hardware latency in the

MCU leading to the transmission of a character (in this case, the $FF).

The shaded area [2] refers to a similar latency in the host computer (in

this case, leading to the transmission of the first data character to the

MCU).

The overall operation begins when the MCU sends the first character

($FF) to the host computer, indicating that it is ready for the first data

character. The host computer sends the first data byte [3] and enters its

main loop. The second data character is sent [4], and the host then waits

[5] for the first verify byte to come back from the MCU.

After the MCU sends $FF [8], it enters the WAIT1 loop [9] and waits for

the first data character from the host. When this character is received

[10], the MCU programs it into the address pointed to by the Y index

register. When the programming time delay is over, the MCU reads the

programmed data, transmits it to the host for verification [11], and

returns to the top of the WAIT1 loop to wait for the next data character

[12]. Because the host previously sent the second data character, it is

already waiting in the SCI receiver of the MCU. Steps [13], [14], and [15]

correspond to the second pass through the WAIT1 loop.

Back in the host, the first verify character is received, and the third data

character is sent [6]. The host then waits for the second verify character

[7] to come back from the MCU. The sequence continues as long as the

host continues to send data to the MCU. Since the WAIT1 loop in the

PROGRAM utility is an indefinite loop, reset is used to end the process

in the MCU after the host has finished sending data to be programmed.

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Application Note

PROGRAM Utility in MCU

Driver Program in HOST

INITIALIZE...

X = PROGRAM TIME

Y = FIRST ADDRESS

HOST NORMALLY WAITS FOR $FF

FROM MCU BEFORE SENDING DATA

FOR EPROM PROGRAMMING

START

$BF00 - PROGRAM

START

INDICATES READY

TO HOST

[8]

[3]

SEND $FF

[9]

SEND FIRST DATA BYTE

DATA_LOOP

WAIT1

NO

MORE DATA TO SEND ?

NO

ANY DATA RECEIVED ?

YES

SEND NEXT DATA [4] [6]

PROGRAM BYTE [10] [13]

[5] [7]

NO

READ PROGRAMMED DATA

AND SEND TO VERIFY

VERIFY DATA RECEIVED ?

YES

[11] [14]

NO

VERIFY DATA CORRECT ?

YES

INDICATE ERROR

POINT TO NEXT LOCATION

TO BE PROGRAMMED

[12] [15]

YES

MORE TO VERIFY ?

NO

PROGRAM CONTINUES

AS LONG AS DATA

IS RECEIVED

DONE

VERIFY DATA TO HOST

(SAME AS MCU Tx DATA)

$FF

[3]

V1

[6]

V2

D3

V3

V4

D5

[4]

HOST SENDING

DATA FOR

MCU EPROM

[5]

[1]

[7]

D4

MCU RECEIVE DATA (FROM HOST)

EPROM PROGRAMMING

D1

D2

[2]

[10]

[13]

MC68HC711E9

EXECUTING

"PROGRAM" LOOP

P1

P2

[12]

V1

P3

P4

[14]

[9]

[11]

[15]

[8]

MCU TRANSMIT DATA (VERIFY)

$FF

V2

V3

V4

Figure 4. Host and MCU Activity during EPROM PROGRAM Utility

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Application Note

Allowing for Bootstrap Mode

Since bootstrap mode requires few connections to the MCU, it is easy to

design systems that accommodate bootstrap mode.

Bootstrap mode is useful for diagnosing or repairing systems that have

failed due to changes in the CONFIG register or failures of the expansion

address/data buses, (rendering programs in external memory useless).

Bootstrap mode can also be used to load information into the EPROM or

EEPROM of an M68HC11 after final assembly of a module. Bootstrap

mode is also useful for performing system checks and calibration

routines. The following paragraphs explain system requirements for use

of bootstrap mode in a product.

Mode Select Pins

It must be possible to force the MODA and MODB pins to logic 0, which

implies that these two pins should be pulled up to V through resistors

DD

rather than being tied directly to V . If mode pins are connected directly

DD

to V , it is not possible to force a mode other than the one the MCU is

DD

hard wired for. It is also good practice to use pulldown resistors to V

SS

rather than connecting mode pins directly to V because it is

SS

sometimes a useful debug aid to attempt reset in modes other than the

one the system was primarily designed for. Physically, this requirement

sometimes calls for the addition of a test point or a wire connected to one

or both mode pins. Mode selection only uses the mode pins while

RESET is active.

RESET

It must be possible to initiate a reset while the mode select pins are held

low. In systems where there is no provision for manual reset, it is usually

possible to generate a reset by turning power off and back on.

RxD Pin

It must be possible to drive the PD0/RxD pin with serial data from a host

computer (or another MCU). In many systems, this pin is already used

for SCI communications; thus no changes are required.

In systems where the PD0/RxD pin is normally used as a general-

purpose output, a serial signal from the host can be connected to the pin

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Application Note

without resulting in output driver conflicts. It may be important to

consider what the existing logic will do with the SCI serial data instead of

the signals that would have been produced by the PD0 pin. In systems

where the PD0 pin is used normally as a general-purpose input, the

driver circuit that drives the PD0 pin must be designed so that the serial

data can override this driver, or the driver must be disconnected during

the bootstrap download. A simple series resistor between the driver and

the PD0 pin solves this problem as shown in Figure 5. The serial data

from the host computer can then be connected to the PD0/RxD pin, and

the series resistor will prevent direct conflict between the host driver and

the normal PD0 driver.

CONNECTED ONLY DURING

BOOTLOADING

FROM

HOST

SYSTEM

RS232

LEVEL

SHIFTER

MC68HC11

EXISTING

CONTROL

SIGNAL

RxD/PD0

(BEING USED

AS INPUT)

SERIES

RESISTOR

EXISTING

DRIVER

Figure 5. Preventing Driver Conflict

TxD Pin

The bootloader program uses the PD1/TxD pin to send verification data

back to the host computer. To minimize the possibility of conflicts with

circuitry connected to this pin, port D is configured for wire-OR mode by

the bootloader program during initialization. Since the wire-OR

configuration prevents the pin from driving active high levels, a pullup

resistor to V is needed if the TxD signal is used.

DD

In systems where the PD1/TxD pin is normally used as a general-

purpose output, there are no output driver conflicts. It may be important

to consider what the existing logic will do with the SCI serial data instead

of the signals that would have been produced by the PD1 pin.

In systems where the PD1 pin is normally used as a general-purpose

input, the driver circuit that drives the PD1 pin must be designed so that

the PD1/TxD pin driver in the MCU can override this driver. A simple

series resistor between the driver and the PD1 pin can solve this

problem. The TxD pin can then be configured as an output, and the

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Application Note

series resistor will prevent direct conflict between the internal TxD driver

and the external driver connected to PD1 through the series resistor.

Other

The bootloader firmware sets the DWOM control bit, which configures all

port D pins for wire-OR operation. During the bootloading process, all

port D pins except the PD1/TxD pin are configured as high-impedance

inputs. Any port D pin that normally is used as an output should have a

pullup resistor so it does not float during the bootloading process.

Driving Boot Mode from Another M68HC11

A second M68HC11 system can easily act as the host to drive bootstrap

loading of an M68HC11 MCU. This method is used to examine and

program non-volatile memories in target M68HC11s in Motorola EVMs.

The following hardware and software example will demonstrate this and

other bootstrap mode features.

The schematic in Figure 6 shows the circuitry for a simple EPROM

duplicator for the MC68HC711E9. The circuitry is built in the wire-wrap

area of an M68HC11EVBU evaluation board to simplify construction.

The schematic shows only the important portions of the EVBU circuitry

to avoid confusion. To see the complete EVBU schematic, refer to the

M68HC11EVBU Universal Evaluation Board User’s Manual, Motorola

document order number M68HC11EVBU/D.

The default configuration of the EVBU must be changed to make the

appropriate connections to the circuitry in the wire-wrap area and to

configure the master MCU for bootstrap mode. A fabricated jumper must

be installed at J6 to connect the XTAL output of the master MCU to the

wire-wrap connector P5, which has been wired to the EXTAL input of the

target MCU. Cut traces that short across J8 and J9 must be cut on the

solder side of the printed circuit board to disconnect the normal SCI

connections to the RS232 level translator (U4) of the EVBU. The J8 and

J9 connections can be restored easily at a later time by installing

fabricated jumpers on the component side of the board. A fabricated

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Application Note

jumper must be installed across J3 to configure the master MCU for

bootstrap mode.

One MC68HC711E9 is first programmed by other means with a desired

12-Kbyte program in its EPROM and a small duplicator program in its

EEPROM. Alternately, the ROM program in an MC68HC11E9 can be

copied into the EPROM of a target MC68HC711E9 by programming only

the duplicator program into the EEPROM of the master MC68HC11E9.

The master MCU is installed in the EVBU at socket U3. A blank

MC68HC711E9 to be programmed is placed in the socket in the wire-

wrap area of the EVBU (U6).

With the V power switch off, power is applied to the EVBU system. As

PP

power is applied to the EVBU, the master MCU (U3) comes out of reset

in bootstrap mode. Target MCU (U6) is held in reset by the PB7 output

of master MCU (U3). The PB7 output of U3 is forced to 0 when U3 is

reset. The master MCU will later release the reset signal to the target

MCU under software control. The RxD and TxD pins of the target MCU

(U6) are high-impedance inputs while U6 is in reset so they will not affect

the TxD and RxD signals of the master MCU (U3) while U3 is coming out

of reset. Since the target MCU is being held in reset with MODA and

MODB at 0, it is configured for the PROG EPROM emulation mode, and

PB7 is the output enable signal for the EPROM data I/O (input/output)

pins. Pullup resistor R7 causes the port D pins, including RxD and TxD,

to remain in the high-impedance state so they do not interfere with the

RxD and TxD pins of the master MCU as it comes out of reset.

As U3 leaves reset, its mode pins select bootstrap mode so the

bootloader firmware begins executing. A break is sent out the TxD pin of

U3. Pullup resistor R10 and resistor R9 cause the break character to be

seen at the RxD pin of U3. The bootloader performs a jump to the start

of EEPROM in the master MCU (U3) and starts executing the duplicator

program. This sequence demonstrates how to use bootstrap mode to

pass control to the start of EEPROM after reset.

The complete listing for the duplicator program in the EEPROM of the

master MCU is provided in Listing 1. MCU-to-MCU Duplicator

Program.

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Application Note

COM +12.25V

M68HC11EVBU

PREWIRED AREA

WIRE-WRAP AREA

ON

V

R11

100

P4

50

P5

PP

+

OFF

C18

R14

15K

S2

20 µF

50

PE7

R15

10K

MASTER

MCU

U3

MC68HC711E9

18

17

XIRQ/V

RESET

PPE

R8

35

PB7

3.3K

V

DD

D5

41

42

41

42

26

1

PB1

V

DD

RED

C17

0.1 µF

R12 1K

R13 1K

D6

42

PB0

V

SS

GREEN

TARGET

MCU

U6

J6

J3

8

7

XTAL

EXTAL

V

DD

2

MODB

35

20

PB7

RxD

R7

10K

R10

15K

21

20

21

20

TxD

R9

[1]

10K

20

21

RxD

TxD

[2]

3

2

MODA

MODB

J8

J9

TO/FROM

RS232 LEVEL

TRANSLATOR

U4

Figure 6. MCU-to-MCU EPROM Duplicator Schematic

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Application Note

The duplicator program in EEPROM clears the DWOM control bit to

change port D (thus, TxD) of U3 to normal driven outputs. This

configuration will prevent interference due to R9 when TxD from the

target MCU (U6) becomes active. Series resistor R9 demonstrates how

TxD of U3 can drive RxD of U3[1] and later TxD of U6 can drive RxD of

U3 without a destructive conflict between the TxD output buffers.

As the target MCU (U6) leaves reset, its mode pins select bootstrap

mode so the bootloader firmware begins executing. A break is sent out

the TxD pin of U6. At this time, the TxD pin of U3 is at a driven high so

R9 acts as a pullup resistor for TxD of the target MCU (U6). The break

character sent from U6 is received by U3 so the duplicator program that

is running in the EEPROM of the master MCU knows that the target

MCU is ready to accept a bootloaded program.

The master MCU sends a leading $FF character to set the baud rate in

the target MCU. Next, the master MCU passes a 3-instruction program

to the target MCU and pauses so the bootstrap program in the target

MCU will stop the loading process and jump to the start of the

downloaded program. This sequence demonstrates the variable-length

download feature of the MC68HC711E9 bootloader.

The short program downloaded to the target MCU clears the DWOM bit

to change its TxD pin to a normal driven CMOS output and jumps to the

EPROM programming utility in the bootstrap ROM of the target MCU.

Note that the small downloaded program did not have to set up the SCI

or initialize any parameters for the EPROM programming process. The

bootstrap software that ran prior to the loaded program left the SCI

turned on and configured in a way that was compatible with the SCI in

the master MCU (the duplicator program in the master MCU also did not

have to set up the SCI for the same reason). The programming time and

starting address for EPROM programming in the target MCU were also

set to default values by the bootloader software before jumping to the

start of the downloaded program.

Before the EPROM in the target MCU can be programmed, the V

PP

power supply must be available at the XIRQ/V

pin of the target MCU.

PPE

The duplicator program running in the master MCU monitors this voltage

(for presence or absence, not level) at PE7 through resistor divider

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Application Note

R14–Rl5. The PE7 input was chosen because the internal circuitry for

port E pins can tolerate voltages slightly higher than V ; therefore,

DD

resistors R14 and R15 are less critical. No data to be programmed is

passed to the target MCU until the master MCU senses that V has

PP

been stable for about 200 ms.

When V is ready, the master MCU turns on the red LED (light-emitting

PP

diode) and begins passing data to the target MCU. EPROM

Programming Utility explains the activity as data is sent from the

master MCU to the target MCU and programmed into the EPROM of the

target. The master MCU in the EVBU corresponds to the HOST in the

programming utility description and the "PROGRAM utility in MCU" is

running in the bootstrap ROM of the target MCU.

Each byte of data sent to the target is programmed and then the

programmed location is read and sent back to the master for verification.

If any byte fails, the red and green LEDs are turned off, and the

programming operation is aborted. If the entire 12 Kbytes are

programmed and verified successfully, the red LED is turned off, and the

green LED is turned on to indicate success. The programming of all 12

Kbytes takes about 30 seconds.

After a programming operation, the V switch (S2) should be turned off

PP

before the EVBU power is turned off.

V

CUT TRACE

AS SHOWN

DD

RN1D

47K

TO MCU

X IR Q /V

XIRQ/V_PPE

PPE

1

3

1

7

+

P4-18

P5-18

47

J7

48

46

44

9

8

10

1

FROM OC5 PIN

OF MCU

2

45

41

15

REMOVE J7

JUMPER

38

13

25

28 19

27

J14

20

34

35

1

21

33

TO

MC68HC68T1

BE SURE NO

JUMPER IS

ON J14

Figure 7. Isolating EVBU XIRQ Pin

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Application Note

Listing 1. MCU-to-MCU Duplicator Program

1

2

**************************************************

* 68HC711E9 Duplicator Program for AN1060

3

**************************************************

4

5

*****

6

* Equates - All reg addrs except INIT are 2-digit

7

*

for direct addressing

8

*****

INIT

SPCR

PORTB

9 103D

10 0028

11 0004

12

EQU

$103D

$28

$04

RAM, Reg mapping

DWOM in bit-5

Red LED = bit-1, Grn = bit-0

* Reset of prog socket = bit-7

13 0080

14 0002

15 0001

16 000A

17 002E

18

RESET

RED

GREEN

PORTE

SCSR

EQU

%10000000

%00000010

%00000001

$0A

Vpp Sense in bit-7, 1=ON

SCI status register

$2E

* TDRE, TC, RDRF, IDLE; OR, NF, FE, -

19 0080

20 0020

21 002F

22 BF00

23 D000

24

TDRE

RDRF

SCDR

PROGRAM

EPSTRT

EQU

%10000000

%00100000

$2F

$BF00

$D000

SCI data register

EPROM prog utility in boot ROM

Starting address of EPROM

25 B600

26

ORG

$B600

Start of EEPROM

27

28

**************************************************

*

29 B600 7F103D

30 B603 8604

31 B605 9728

32 B607 8680

33 B609 9704

BEGIN

CLR

INIT

#$04

SPCR

#RESET

PORTB

Moves Registers to $0000-3F

Pattern for DWOM off, no SPI

Turns off DWOM in EVBU MCU

LDAA

STAA

LDAA

STAA

Release reset to target MCU

34 B60B 132E20FC WT4BRK

35 B60F 86FF

36 B611 972F

BRCLR SCSR RDRF WT4BRK Loop till char received

LDAA

STAA

LDX

#$FF

SCDR

#BLPROG

SEND1

Leading char for bootload ...

to target MCU

Point at program for target

Bootload to target

37 B613 CEB675

38 B616 8D53

39 B618 8CB67D

40 B61B 26F9

41

BLLOOP

*****

BSR

CPX

BNE

#ENDBPR

BLLOOP

Past end ?

Continue till all sent

42

43

44

* Delay for about 4 char times to allow boot related

* SCI communications to finish before clearing

* Rx related flags

45 B61D CE06A7

46 B620 09

47 B621 26FD

48 B623 962E

49 B625 962F

LDX

DEX

BNE

LDAA

#1703

# of 6 cyc loops

[3]

[3] Total loop time = 6 cyc

Read status (RDRF will be set)

Read SCI data reg to clear RDRF

DLYLP

SCSR

SCDR

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Application Note

50

51

52

*****

* Now wait for character from target to indicate it's ready for

* data to be programmed into EPROM

53 B627 132E20FC WT4FF

54 B62B 962F

55 B62D CED000

BRCLR SCSR RDRF WT4FF Wait for RDRF

LDAA

LDX

SCDR

#EPSTRT

Clear RDRF, don't need data

Point at start of EPROM

56

* Handle turn-on of Vpp

57 B630 18CE523D WT4VPP

58 B634 150402

LDY

#21053

PORTB RED

PORTE

WT4VPP

PORTB RED

Delay counter (about 200ms)

Turn off RED LED

[3] Wait for Vpp to be ON

[3] Vpp sense is on port E MSB

[6] Turn on RED LED

BCLR

LDAA

BPL

BSET

DEY

59 B637 960A

60 B639 2AF5

61 B63B 140402

62 B63E 1809

63 B640 26F5

64

DLYLP2

[4]

BNE

DLYLP2

[3] Total loop time = 19 cyc

* Vpp has been stable for 200ms

65

66 B642 18CED000

67 B646 8D23

68 B648 8C0000

69 B64B 2702

70 B64D 8D1C

71 B64F 132E20FC VERF

72 B653 962F

73 B655 18A100

74 B658 2705

75 B65A 150403

76 B65D 2007

77 B65F

LDY

BSR

CPX

BEQ

BSR

#EPSTRT

SEND1

#0

VERF

SEND1

X=Tx pointer, Y=verify pointer

Send first data to target

X points at $0000 after last

Skip send if no more

Send another data char

Wait for Rx ready

Get char and clr RDRF

Does char verify ?

Skip error if OK

DATALP

BRCLR SCSR RDRF VERF

LDAA

CMPA

BEQ

BCLR

BRA

SCDR

0,Y

VERFOK

PORTB (RED+GREEN) Turn off LEDs

DUNPRG

Done (programming failed)

78 B65F 1808

79 B661 26E5

80 B663

VERFOK

INY

BNE

Advance verify pointer

Continue till all done

DATALP

81 B663 140401

82 B666

BSET

PORTB GREEN

Grn LED ON

83 B666 150482

84 B669 20FE

85 B66B

DUNPRG

BCLR

BRA

PORTB (RESET+RED) Red OFF, apply reset

Done so just hang

*

86

87

**************************************************

* Subroutine to get & send an SCI char. Also

88

89

*

advances pointer (X).

**************************************************

SEND1 LDAA 0,X Get a character

BRCLR SCSR TDRE TRDYLP Wait for TDRE

90 B66B A600

91 B66D 132E80FC TRDYLP

92 B671 972F

93 B673 08

STAA

INX

SCDR

Send character

Advance pointer

** Return **

94 B674 39

RTS

95

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Application Note

96

97

**************************************************

* Program to be bootloaded to target '711E9

98

**************************************************

99 B675 8604

100 B677 B71028

101

BLPROG

LDAA

STAA

#$04

$1028

Pattern for DWOM off, no SPI

Turns off DWOM in target MCU

* NOTE: Can't use direct addressing in target MCU because

102

*

regs are located at $1000.

103 B67A 7EBF00

104 B67D

JMP

EQU

PROGRAM

*

Jumps to EPROM prog routine

ENDBPR

Symbol Table:

Symbol Name

Value Def.# Line Number Cross Reference

BEGIN

BLLOOP

BLPROG

DATALP

DLYLP

DLYLP2

DUNPRG

ENDBPR

EPSTRT

GREEN

INIT

B600 *00029

B616 *00038 00040

B675 *00099 00037

B648 *00068 00079

B620 *00046 00047

B637 *00059 00063

B666 *00083 00076

B67D *00104 00039

D000 *00023 00055 00066

0001 *00015 00075 00081

103D *00009 00029

PORTB

PORTE

PROGRAM

RDRF

RED

RESET

SCDR

SCSR

SEND1

SPCR

0004 *00011 00033 00058 00061 00075 00081 00083

000A *00016 00059

BF00 *00022 00103

0020 *00020 00034 00053 00071

0002 *00014 00058 00061 00075 00083

0080 *00013 00032 00083

002F *00021 00036 00049 00054 00072 00092

002E *00017 00034 00048 00053 00071 00091

B66B *00090 00038 00067 00070

0028 *00010 00031

TDRE

0080 *00019 00091

TRDYLP

VERF

VERFOK

WT4BRK

WT4FF

WT4VPP

B66D *00091 00091

B64F *00071 00069 00071

B65F *00078 00074

B60B *00034 00034

B627 *00053 00053

B630 *00057 00060

Errors: None

Labels: 28

Last Program Address: $B67C

Last Storage Address: $0000

Program Bytes: $007D 125

Storage Bytes: $0000

0

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Application Note

Driving Boot Mode from a Personal Computer

In this example, a personal computer is used as the host to drive the

bootloader of an MC68HC711E9. An M68HC11 EVBU is used for the

target MC68HC711E9. A large program is transferred from the personal

computer into the EPROM of the target MC68HC711E9.

Hardware

Figure 7 shows a small modification to the EVBU to accommodate the

12-volt (nominal) EPROM programming voltage. The XIRQ pin is

connected to a pullup resistor, two jumpers, and the 60-pin connectors,

P4 and P5. The object of the modification is to isolate the XIRQ pin and

then connect it to the programming power supply. Carefully cut the trace

on the solder side of the EVBU as indicated in Figure 7. This

disconnects the pullup resistor RN1 D from XIRQ but leaves P4–18,

P5–18, and jumpers J7 and J14 connected so the EVBU can still be

used for other purposes after programming is done. Remove any

fabricated jumpers from J7 and J14. The EVBU normally has a jumper

at J7 to support the trace function

Figure 8 shows a small circuit that is added to the wire-wrap area of the

EVBU. The 3-terminal jumper allows the XIRQ line to be connected to

either the programming power supply or to a substitute pullup resistor for

XIRQ. The 100-ohm resistor is a current limiter to protect the 12-volt

input of the MCU. The resistor and LED connected to P5 pin 9 (port C

bit 0) is an optional indicator that lights when programming is complete.

Software

BASIC was chosen as the programming language due to its readability



and availability in parallel versions on both the IBM PC and the



Macintosh . The program demonstrates several programming

techniques for use with an M68HC11 and is not necessarily intended to

be a finished, commercial program. For example, there is little error

checking, and the user interface is elementary. A complete listing of the

BASIC program is included in Listing 2. BASIC Program for Personal

Computer with moderate comments. The following paragraphs include

^IBM is a registered trademark of International Business Machines.

^Macintosh is a registered trademark of Apple Computers, Inc.

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Application Note

a more detailed discussion of the program as it pertains to

communicating with and programming the target MC68HC711E9. Lines

25–45 initialize and define the variables and array used in the program.

Changes to this section would allow for other programs to be

downloaded.

V

DD

47K

NORMAL EVBU

OPERATION

TO P5-18

(XIRQ/V

)

100

PPE

PROGRAM

EPROM

+12.25 V

+

JUMPER

20 µF

PROGRAMMING

POWER

COMMON

PC0

P5-9

1K

LED

Figure 8. PC-to-MCU Programming Circuit

Lines 50–95 read in the small bootloader from DATA statements at the

end of the listing. The source code for this bootloader is presented in the

DATA statements. The bootloaded code makes port C bit 0 low,

initializes the X and Y registers for use by the EPROM programming

utility routine contained in the boot ROM, and then jumps to that routine.

The hexadecimal values read in from the DATA statements are

converted to binary values by a subroutine. The binary values are then

saved as one string (BOOTCODE$).

The next long section of code (lines 97–1250) reads in the S records

from an external disk file (in this case, BUF34.S19), converts them to

integer, and saves them in an array. The techniques used in this section

show how to convert ASCII S records to binary form that can be sent

(bootloaded) to an M68HC11.

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Application Note

This S-record translator only looks for the S1 records that contain the

actual object code. All other S-record types are ignored.

When an S1 record is found (lines 1000–1024), the next two characters

form the hex byte giving the number of hex bytes to follow. This byte is

converted to integer by the same subroutine that converted the

bootloaded code from the DATA statements. This BYTECOUNT is

adjusted by subtracting 3, which accounts for the address and checksum

bytes and leaves just the number of object-code bytes in the record.

Starting at line 1100, the 2-byte (4-character) starting address is

converted to decimal. This address is the starting address for the object

code bytes to follow. An index into the CODE% array is formed by

subtracting the base address initialized at the start of the program from

the starting address for this S record.

A FOR-NEXT loop starting at line 1130 converts the object code bytes

to decimal and saves them in the CODE% array. When all the object

code bytes have been converted from the current S record, the program

loops back to find the next S1 record.

A problem arose with the BASIC programming technique used. The draft

versions of this program tried saving the object code bytes directly as

binary in a string array. This caused "Out of Memory" or "Out of String

Space" errors on both a 2-Mbyte Macintosh and a 640-Kbyte PC. The

solution was to make the array an integer array and perform the integer-

to-binary conversion on each byte as it is sent to the target part.

The one compromise made to accommodate both Macintosh and PC

versions of BASIC is in lines 1500 and 1505. Use line 1500 and

comment out line 1505 if the program is to be run on a Macintosh, and,

conversely, use line 1505 and comment out line 1500 if a PC is used.

After the COM port is opened, the code to be bootloaded is modified by

adding the $FF to the start of the string. $FF synchronizes the bootloader

in the MC68HC711E9 to 1200 baud. The entire string is simply sent to

the COM port by PRINTing the string. This is possible since the string is

actually queued in BASIC’s COM buffer, and the operating system takes

care of sending the bytes out one at a time. The M68HC11 echoes the

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Application Note

data received for verification. No automatic verification is provided,

though the data is printed to the screen for manual verification.

Once the MCU has received this bootloaded code, the bootloader

automatically jumps to it. The small bootloaded program in turn includes

a jump to the EPROM programming routine in the boot ROM.

Refer to the previous explanation of the EPROM Programming Utility

for the following discussion. The host system sends the first byte to be

programmed through the COM port to the SCI of the MCU. The SCI port

on the MCU buffers one byte while receiving another byte, increasing the

throughput of the EPROM programming operation by sending the

second byte while the first is being programmed.

When the first byte has been programmed, the MCU reads the EPROM

location and sends the result back to the host system. The host then

compares what was actually programmed to what was originally sent. A

message indicating which byte is being verified is displayed in the lower

half of the screen. If there is an error, it is displayed at the top of the

screen.

As soon as the first byte is verified, the third byte is sent. In the

meantime, the MCU has already started programming the second byte.

This process of verifying and queueing a byte continues until the host

finishes sending data. If the programming is completely successful, no

error messages will have been displayed at the top of the screen.

Subroutines follow the end of the program to handle some of the

repetitive tasks. These routines are short, and the commenting in the

source code should be sufficient explanation.

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Application Note

Modifications

This example programmed version 3.4 of the BUFFALO monitor into the

EPROM of an MC68HC711E9; the changes to the BASIC program to

download some other program are minor.

The necessary changes are:

1. In line 30, the length of the program to be downloaded must be

assigned to the variable CODESIZE%.

2. Also in line 30, the starting address of the program is assigned to

the variable ADRSTART.

3. In line 9570, the start address of the program is stored in the third

and fourth items in that DATA statement in hexadecimal.

4. If any changes are made to the number of bytes in the boot code

in the DATA statements in lines 9500–9580, then the new count

must be set in the variable "BOOTCOUNT" in line 25.

Operation

Configure the EVBU for boot mode operation by putting a jumper at J3.

Ensure that the trace command jumper at J7 is not installed because this

would connect the 12-V programming voltage to the OC5 output of the

MCU.

Connect the EVBU to its dc power supply. When it is time to program the

MCU EPROM, turn on the 12-volt programming power supply to the new

circuitry in the wire-wrap area.

Connect the EVBU serial port to the appropriate serial port on the host

system. For the Macintosh, this is the modem port with a modem cable.



For the MS-DOS computer, it is connected to COM1 with a straight

through or modem cable. Power up the host system and start the BASIC

program. If the program has not been compiled, this is accomplished

from within the appropriate BASIC compiler or interpreter. Power up the

EVBU.

Answer the prompt for filename with either a [RETURN] to accept the

default shown or by typing in a new filename and pressing [RETURN].

^MS-DOS is a registered trademark of Microsoft Corporation in the United States and other

countries.

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Application Note

The program will inform the user that it is working on converting the file

from S records to binary. This process will take from 30 seconds to a few

minutes, depending on the computer.

A prompt reading, "Comm port open?" will appear at the end of the file

conversion. This is the last chance to ensure that everything is properly

configured on the EVBU. Pressing [RETURN] will send the bootcode to

the target MC68HC711E9. The program then informs the user that the

bootload code is being sent to the target, and the results of the echoing

of this code are displayed on the screen.

Another prompt reading "Programming is ready to begin. Are you?" will

appear. Turn on the 12-volt programming power supply and press

[RETURN] to start the actual programming of the target EPROM.

A count of the byte being verified will be updated continually on the

screen as the programming progresses. Any failures will be flagged as

they occur.

When programming is complete, a message will be displayed as well as

a prompt requesting the user to press [RETURN] to quit.

Turn off the 12-volt programming power supply before turning off 5 volts

to the EVBU.

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Application Note

Listing 2. BASIC Program for Personal Computer

1 ' ***********************************************************************

2 ' *

3 ' *

4 ' *

5 ' *

6 ' *

7 ' *

8 ' *

9 ' *

10 '*

11 '*

12 '*

14 '*

E9BUF.BAS - A PROGRAM TO DEMONSTRATE THE USE OF THE BOOT MODE

ON THE HC11 BY PROGRAMMING AN HC711E9 WITH

BUFFALO 3.4

REQUIRES THAT THE S-RECORDS FOR BUFFALO (BUF34.S19)

BE AVAILABLE IN THE SAME DIRECTORY OR FOLDER

THIS PROGRAM HAS BEEN RUN BOTH ON A MS-DOS COMPUTER

USING QUICKBASIC 4.5 AND ON A MACINTOSH USING

QUICKBASIC 1.0.

15 '************************************************************************

25 H$ = "0123456789ABCDEF" 'STRING TO USE FOR HEX CONVERSIONS

30 DEFINT B, I: CODESIZE% = 8192: ADRSTART= 57344!

35 BOOTCOUNT = 25

'NUMBER OF BYTES IN BOOT CODE

40 DIM CODE%(CODESIZE%)

45 BOOTCODE$ = ""

'BUFFALO 3.4 IS 8K BYTES LONG

'INITIALIZE BOOTCODE$ TO NULL

49 REM ***** READ IN AND SAVE THE CODE TO BE BOOT LOADED *****

50 FOR I = 1 TO BOOTCOUNT

55 READ Q$

'# OF BYTES IN BOOT CODE

60 A$ = MID$(Q$, 1, 1)

65 GOSUB 7000

70 TEMP = 16 * X

75 A$ = MID$(Q$, 2, 1)

80 GOSUB 7000

'CONVERTS HEX DIGIT TO DECIMAL

'HANG ON TO UPPER DIGIT

85 TEMP = TEMP + X

90 BOOTCODE$ = BOOTCODE$ + CHR$(TEMP)

95 NEXT I

'BUILD BOOT CODE

96 REM ***** S-RECORD CONVERSION STARTS HERE *****

97 FILNAM$="BUF34.S19"

'DEFAULT FILE NAME FOR S-RECORDS

100 CLS

105 PRINT "Filename.ext of S-record file to be downloaded (";FILNAM$;") ";

107 INPUT Q$

110 IF Q$<>"" THEN FILNAM$=Q$

120 OPEN FILNAM$ FOR INPUT AS #1

130 PRINT : PRINT "Converting "; FILNAM$; " to binary..."

999 REM ***** SCANS FOR 'S1' RECORDS *****

1000 GOSUB 6000

'GET 1 CHARACTER FROM INPUT FILE

'FLAG IS EOF FLAG FROM SUBROUTINE

1010 IF FLAG THEN 1250

1020 IF A$ <> "S" THEN 1000

1022 GOSUB 6000

1024 IF A$ <> "1" THEN 1000

1029 REM ***** S1 RECORD FOUND, NEXT 2 HEX DIGITS ARE THE BYTE COUNT *****

1030 GOSUB 6000

1040 GOSUB 7000

'RETURNS DECIMAL IN X

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Application Note

1050 BYTECOUNT = 16 * X

1060 GOSUB 6000

'ADJUST FOR HIGH NIBBLE

1070 GOSUB 7000

1080 BYTECOUNT = BYTECOUNT + X

1090 BYTECOUNT = BYTECOUNT - 3

'ADD LOW NIBBLE

'ADJUST FOR ADDRESS + CHECKSUM

1099 REM ***** NEXT 4 HEX DIGITS BECOME THE STARTING ADDRESS FOR THE DATA *****

1100 GOSUB 6000

1102 GOSUB 7000

'GET FIRST NIBBLE OF ADDRESS

'CONVERT TO DECIMAL

1104 ADDRESS= 4096 * X

1106 GOSUB 6000

'GET NEXT NIBBLE

1108 GOSUB 7000

1110 ADDRESS= ADDRESS+ 256 * X

1112 GOSUB 6000

1114 GOSUB 7000

1116 ADDRESS= ADDRESS+ 16 * X

1118 GOSUB 6000

1120 GOSUB 7000

1122 ADDRESS= ADDRESS+ X

1124 ARRAYCNT = ADDRESS-ADRSTART

'INDEX INTO ARRAY

1129 REM ***** CONVERT THE DATA DIGITS TO BINARY AND SAVE IN THE ARRAY *****

1130 FOR I = 1 TO BYTECOUNT

1140 GOSUB 6000

1150 GOSUB 7000

1160 Y = 16 * X

1170 GOSUB 6000

1180 GOSUB 7000

1190 Y = Y + X

'SAVE UPPER NIBBLE OF BYTE

'ADD LOWER NIBBLE

1200 CODE%(ARRAYCNT) = Y

1210 ARRAYCNT = ARRAYCNT + 1

1220 NEXT I

'SAVE BYTE IN ARRAY

'INCREMENT ARRAY INDEX

1230 GOTO 1000

1250 CLOSE 1

1499 REM ***** DUMP BOOTLOAD CODE TO PART *****

1500 'OPEN "R",#2,"COM1:1200,N,8,1" 'Macintosh COM statement

1505 OPEN "COM1:1200,N,8,1,CD0,CS0,DS0,RS" FOR RANDOM AS #2 'DOS COM statement

1510 INPUT "Comm port open"; Q$

1512 WHILE LOC(2) >0

1513 GOSUB 8020

1514 WEND

'FLUSH INPUT BUFFER

1515 PRINT : PRINT "Sending bootload code to target part..."

1520 A$ = CHR$(255) + BOOTCODE$ 'ADD HEX FF TO SET BAUD RATE ON TARGET HC11

1530 GOSUB 6500

1540 PRINT

1550 FOR I = 1 TO BOOTCOUNT

1560 GOSUB 8000

'# OF BYTES IN BOOT CODE BEING ECHOED

1564 K=ASC(B$):GOSUB 8500

1565 PRINT "Character #"; I; " received = "; HX$

1570 NEXT I

1590 PRINT "Programming is ready to begin.": INPUT "Are you ready"; Q$

1595 CLS

1597 WHILE LOC(2) > 0

'FLUSH INPUT BUFFER

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Application Note

1598 GOSUB 8020

1599 WEND

1600 XMT = 0: RCV = 0

'POINTERS TO XMIT AND RECEIVE BYTES

1610 A$ = CHR$(CODE%(XMT))

1620 GOSUB 6500

1625 FOR I = 1 TO CODESIZE% - 1

1630 A$ = CHR$(CODE%(I))

1635 GOSUB 6500

'SEND FIRST BYTE

'ZERO BASED ARRAY 0 -> CODESIZE-1

'SEND SECOND BYTE TO GET ONE IN QUEUE

'SEND IT

1640 GOSUB 8000

'GET BYTE FOR VERIFICATION

1650 RCV = I - 1

1660 LOCATE 10,1:PRINT "Verifying byte #"; I; "

1664 IF CHR$(CODE%(RCV)) = B$ THEN 1670

1665 K=CODE%(RCV):GOSUB 8500

"

1666 LOCATE 1,1:PRINT "Byte #"; I; "

1668 K=ASC(B$):GOSUB 8500

1669 PRINT " Received "; HX$;

1670 NEXT I

", " - Sent "; HX$;

1680 GOSUB 8000

'GET BYTE FOR VERIFICATION

1690 RCV = CODESIZE% - 1

1700 LOCATE 10,1:PRINT "Verifying byte #"; CODESIZE%; "

1710 IF CHR$(CODE%(RCV)) = B$ THEN 1720

1713 K=CODE(RCV):GOSUB 8500

"

1714 LOCATE 1,1:PRINT "Byte #"; CODESIZE%; "

1715 K=ASC(B$):GOSUB 8500

", " - Sent "; HX$;

1716 PRINT " Received "; HX$;

1720 LOCATE 8, 1: PRINT : PRINT "Done!!!!"

4900 CLOSE

4910 INPUT "Press [RETURN] to quit...", Q$

5000 END

5900 '***********************************************************************

5910 '*

5930 '*

SUBROUTINE TO READ IN ONE BYTE FROM A DISK FILE

RETURNS BYTE IN A$

5940 '***********************************************************************

6000 FLAG = 0

6010 IF EOF(1) THEN FLAG = 1: RETURN

6020 A$ = INPUT$(1, #1)

6030 RETURN

6490 '***********************************************************************

6492 '*

6494 '*

SUBROUTINE TO SEND THE STRING IN A$ OUT TO THE DEVICE

OPENED AS FILE #2.

6496 '***********************************************************************

6500 PRINT #2, A$;

6510 RETURN

6590 '***********************************************************************

6594 '*

SUBROUTINE THAT CONVERTS THE HEX DIGIT IN A$ TO AN INTEGER

6596 '***********************************************************************

7000 X = INSTR(H$, A$)

7010 IF X = 0 THEN FLAG = 1

7020 X = X - 1

7030 RETURN

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Application Note

7990 '**********************************************************************

7992 '*

7994 '*

7996 '*

7998 '*

SUBROUTINE TO READ IN ONE BYTE THROUGH THE COMM PORT OPENED

AS FILE #2. WAITS INDEFINITELY FOR THE BYTE TO BE

RECEIVED. SUBROUTINE WILL BE ABORTED BY ANY

KEYBOARD INPUT. RETURNS BYTE IN B$. USES Q$.

7999 '**********************************************************************

8000 WHILE LOC(2) = 0 'WAIT FOR COMM PORT INPUT

8005 Q$ = INKEY$: IF Q$ <> "" THEN 4900 'IF ANY KEY PRESSED, THEN ABORT

8010 WEND

8020 B$ = INPUT$(1, #2)

8030 RETURN

8490 '************************************************************************

8491 '*

8492 '*

8493 '*

DECIMAL TO HEX CONVERSION

INPUT: K - INTEGER TO BE CONVERTED

OUTPUT: HX$ - TWO CHARACTER STRING WITH HEX CONVERSION

8494 '************************************************************************

8500 IF K > 255 THEN HX$="Too big":GOTO 8530

8510 HX$=MID$(H$,K\16+1,1)

'UPPER NIBBLE

8520 HX$=HX$+MID$(H$,(K MOD 16)+1,1) 'LOWER NIBBLE

8530 RETURN

9499 '******************** BOOT CODE ****************************************

9500 DATA 86, 23

9510 DATA B7, 10, 02

9520 DATA 86, FE

9530 DATA B7, 10, 03

9540 DATA C6, FF

9550 DATA F7, 10, 07

9560 DATA CE, 0F, A0

9570 DATA 18, CE, E0, 00

9580 DATA 7E, BF, 00

'LDAA

'STAA

'LDAA

'STAA

'LDAB

'STAB

'LDX

#$23

OPT2

#$FE

PORTC

#$FF

DDRC

#4000

make port C wire or

light 1 LED on port C bit 0

make port C outputs

2msec at 2MHz

'LDY

'JMP

#$E000 Start of BUFFALO 3.4

$BF00 EPROM routine start address

9590 '***********************************************************************

Common Bootstrap Mode Problems

It is not unusual for a user to encounter problems with bootstrap mode

because it is new to many users. By knowing some of the common

difficulties, the user can avoid them or at least recognize and quickly

correct them.

Reset Conditions

vs. Conditions

as Bootloaded

Program Starts

It is common to confuse the reset state of systems and control bits with

the state of these systems and control bits when a bootloaded program

in RAM starts.

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Application Note

Between these times, the bootloader program is executed, which

changes the states of some systems and control bits:

•

The SCI system is initialized and turned on (Rx and Tx).

The SCI system has control of the PD0 and PD1 pins.

Port D outputs are configured for wire-OR operation.

The stack pointer is initialized to the top of RAM.

Time has passed (two or more SCI character times).

Timer has advanced from its reset count value.

Users also forget that bootstrap mode is a special mode. Thus,

privileged control bits are accessible, and write protection for some

registers is not in effect. The bootstrap ROM is in the memory map. The

DISR bit in the TEST1 control register is set, which disables resets from

the COP and clock monitor systems.

Since bootstrap is a special mode, these conditions can be changed by

software. The bus can even be switched from single-chip mode to

expanded mode to gain access to external memories and peripherals.

Connecting RxD

To force an immediate jump to the start of EEPROM, the bootstrap

firmware looks for the first received character to be $00 (or break). The

data reception logic in the SCI looks for a 1-to-0 transition on the RxD

pin to synchronize to the beginning of a receive character. If the RxD pin

is tied to ground, no 1-to-0 transition occurs. The SCI transmitter sends

a break character when the bootloader firmware starts, and this break

character can be fed back to the RxD pin to cause the jump to EEPROM.

Since TxD is configured as an open-drain output, a pullup resistor is

required.

to V Does Not

SS

Cause the SCI

to Receive a Break

$FF Character Is

Required before

Loading into RAM

The initial character (usually $FF) that sets the download baud rate is

often forgotten.

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Application Note

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Application Note

Original M68HC11

Versions Required

Exactly 256 Bytes

to be Downloaded

to RAM

Even users that know about the 256 bytes of download data sometimes

forget the initial $FF that makes the total number of bytes required for the

entire download operation equal to 256 + 1 or 257 bytes.

Variable-Length

Download

When on-chip RAM surpassed 256 bytes, the time required to serially

load this many characters became more significant. The variable-length

download feature allows shorter programs to be loaded without

sacrificing compatibility with earlier fixed-length download versions of

the bootloader. The end of a download is indicated by an idle RxD line

for at least four character times. If a personal computer is being used to

send the download data to the MCU, there can be problems keeping

characters close enough together to avoid tripping the end-of-download

detect mechanism. Using 1200 as the baud rate rather than the faster

default rate may help this problem.

Assemblers often produce S-record encoded programs which must be

converted to binary before bootloading them to the MCU. The process of

reading S-record data from a file and translating it to binary can be slow,

depending on the personal computer and the programming language

used for the translation. One strategy that can be used to overcome this

problem is to translate the file into binary and store it into a RAM array

before starting the download process. Data can then be read and

downloaded without the translation or file-read delays.

The end-of-download mechanism goes into effect when the initial $FF is

received to set the baud rate. Any amount of time may pass between

reset and when the $FF is sent to start the download process.

EPROM/OTP

Versions

of M68HC11

Have an EPROM

Emulation Mode

The conditions that configure the MCU for EPROM emulation mode are

essentially the same as those for resetting the MCU in bootstrap mode.

While RESET is low and mode select pins are configured for bootstrap

mode (low), the MCU is configured for EPROM emulation mode.

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Application Note

The port pins that are used for EPROM data I/O lines may be inputs or

outputs, depending on the pin that is emulating the EPROM output

enable pin (OE). To make these data pins appear as high-impedance

inputs as they would on a non-EPROM part in reset, connect the

PB7/(OE) pin to a pullup resistor.

Bootloading

a Program

to Perform

The bootloader ROM must be turned off before performing the

checksum program. To remove the boot ROM from the memory map,

clear the RBOOT bit in the HPRIO register. This is normally a write-

protected bit that is 0, but in bootstrap mode it is reset to 1 and can be

written. If the boot ROM is not disabled, the checksum routine will read

the contents of the boot ROM rather than the user’s mask ROM or

EPROM at the same addresses.

a ROM Checksum

Inherent Delays

Caused

This problem is troublesome in cases where one MCU is bootloading to

another MCU.

by Double

Buffering

of SCI Data

Because of transmitter double buffering, there may be one character in

the serial shifter as a new character is written into the transmit data

register. In cases such as downloading in which this 2-character pipeline

is kept full, a 2-character time delay occurs between when a character is

written to the transmit data register and when that character finishes

transmitting. A little more than one more character time delay occurs

between the target MCU receiving the character and echoing it back. If

the master MCU waits for the echo of each downloaded character before

sending the next one, the download process takes about twice as long

as it would if transmission is treated as a separate process or if verify

data is ignored.

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Application Note

Boot ROM Variations

Different versions of the M68HC11 have different versions of the

bootstrap ROM program. Table 3 summarizes the features of the boot

ROMs in 16 members of the M68HC11 Family.

The boot ROMs for the MC68HC11F1, the MC68HC711K4, and the

MC68HC11K4 allow additional choices of baud rates for bootloader

communications. For the three new baud rates, the first character used

to determine the baud rate is not $FF as it was in earlier M68HC11s. The

intercharacter delay that terminates the variable-length download is also

different for these new baud rates. Table 3 shows the synchronization

characters, delay times, and baud rates as they relate to E-clock

frequency.

Commented Boot ROM Listing

Listing 3. MC68HC711E9 Bootloader ROM contains a complete

commented listing of the boot ROM program in the MC68HC711E9

version of the M68HC11. Other versions can be found in Appendix B of

the M68HC11 Reference Manual and in the freeware area of the

Motorola Web site.

Table 3. Bootloader Baud Rates

Baud Rates at E Clock =

Sync

Character

Timeout

Delay

2 MHz 2.1 MHz 3 MHz 3.15 MHz 4 MHz 4.2 MHz

$FF

$F0

$FD

4 characters

7812

1200

8192 11,718 12,288 15,624 16,838

1260 1800 1890 2400 2520

4.9 characters 9600 10,080 14,400 15,120 19,200 20,160

17.3 characters 5208

13 characters 3906

5461

4096

7812

5859

8192

6144

10,416 10,922

7812 8192

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Application Note

Listing 3. MC68HC711E9 Bootloader ROM

1

2

3

4

****************************************************

* BOOTLOADER FIRMWARE FOR 68HC711E9 - 21 Aug 89

****************************************************

* Features of this bootloader are...

*

5

6

7

8

9

10

11

* Auto baud select between 7812.5 and 1200 (8 MHz)

* 0 - 512 byte variable length download

* Jump to EEPROM at $B600 if 1st download byte = $00

* PROGRAM - Utility subroutine to program EPROM

* UPLOAD - Utility subroutine to dump memory to host

* Mask I.D. at $BFD4 = $71E9

12

13

****************************************************

* Revision A -

14

*

15

16

17

* Fixed bug in PROGRAM routine where the first byte

* programmed into the EPROM was not transmitted for

* verify.

18

19

20

* Also added to PROGRAM routine a skip of bytes

* which were already programmed to the value desired.

*

21

22

23

24

* This new version allows variable length download

* by quitting reception of characters when an idle

* of at least four character times occurs

*

25

****************************************************

26

27

28

* EQUATES FOR USE WITH INDEX OFFSET = $1000

*

29 0008

30 000E

31 0016

32 0023

33

PORTD

TCNT

TOC1

EQU

$08

$0E

$16

$23

TFLG1

* BIT EQUATES FOR TFLG1

34 0080

35

OC1F

*

EQU

$80

36 0028

37 002B

38 002D

39 002E

40 002F

41 003B

42

SPCR

BAUD

SCCR2

SCSR

SCDAT

PPROG

EQU

$28

$2B

$2D

$2E

$2F

$3B

(FOR DWOM BIT)

* BIT EQUATES FOR PPROG

43 0020

44 0001

45

ELAT

EPGM

*

EQU

$20

$01

46

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Application Note

47

48

* MEMORY CONFIGURATION EQUATES

*

49 B600

50 B7FF

51

EEPMSTR EQU

EEPMEND EQU

*

$B600

$B7FF

Start of EEPROM

End of EEPROM

52 D000

53 FFFF

54

EPRMSTR EQU

EPRMEND EQU

*

$D000

$FFFF

Start of EPROM

End of EPROM

55 0000

56 01FF

RAMSTR

RAMEND

EQU

$0000

$01FF

57

58

59

* DELAY CONSTANTS

*

60 0DB0

61 021B

62

DELAYS

DELAYF

*

EQU

3504

539

Delay at slow baud

Delay at fast baud

63 1068

64

PROGDEL EQU

*

4200

2 ms programming delay

At 2.1 MHz

65

66

67 BF00

****************************************************

ORG $BF00

68

****************************************************

69

70

71

72

73

* Next two instructions provide a predictable place

* to call PROGRAM and UPLOAD even if the routines

* change size in future versions.

*

74 BF00 7EBF13

75 BF03

PROGRAM JMP

UPLOAD EQU

PRGROUT

*

EPROM programming utility

Upload utility

76

77

78

79

80

****************************************************

* UPLOAD - Utility subroutine to send data from

* inside the MCU to the host via the SCI interface.

* Prior to calling UPLOAD set baud rate, turn on SCI

* and set Y=first address to upload.

81

82

83

84

85

86

87

* Bootloader leaves baud set, SCI enabled, and

* Y pointing at EPROM start ($D000) so these default

* values do not have to be changed typically.

* Consecutive locations are sent via SCI in an

* infinite loop. Reset stops the upload process.

****************************************************

88 BF03 CE1000

89 BF06 18A600

90 BF09 1F2E80FC

91 BF0D A72F

92 BF0F 1808

93 BF11 20F3

94

LDX

LDAA

#$1000

0,Y

Point to internal registers

Read byte

Wait for TDRE

Send it

UPLOOP

BRCLR SCSR,X $80 *

STAA

INY

SCDAT,X

UPLOOP

BRA

Next...

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Application Note

95

96

97

98

****************************************************

* PROGRAM - Utility subroutine to program EPROM.

* Prior to calling PROGRAM set baud rate, turn on SCI

* set X=2ms prog delay constant, and set Y=first

* address to program. SP must point to RAM.

99

100

101

102

103

* Bootloader leaves baud set, SCI enabled, X=4200

* and Y pointing at EPROM start ($D000) so these

* default values don't have to be changed typically.

* Delay constant in X should be equivalent to 2 ms

104

105

106

*

at 2.1 MHz X=4200; at 1 MHz X=2000.

* An external voltage source is required for EPROM

* programming.

107

108

109

* This routine uses 2 bytes of stack space

* Routine does not return. Reset to exit.

****************************************************

110 BF13

PRGROUT EQU

PSHX

LDX

*

111 BF13 3C

112 BF14 CE1000

113 BF17

Save program delay constant

Point to internal registers

#$1000

114

* Send $FF to indicate ready for program data

115

116 BF17 1F2E80FC

117 BF1B 86FF

118 BF1D A72F

119

BRCLR SCSR,X $80 *

Wait for TDRE

LDAA

STAA

#$FF

SCDAT,X

120 BF1F

WAIT1

EQU

*

121 BF1F 1F2E20FC

122 BF23 E62F

123 BF25 18E100

124 BF28 271D

125 BF2A 8620

126 BF2C A73B

127 BF2E 18E700

128 BF31 8621

129 BF33 A73B

130 BF35 32

131 BF36 33

132 BF37 37

133 BF38 36

134 BF39 E30E

135 BF3B ED16

136 BF3D 8680

137 BF3F A723

138

BRCLR SCSR,X $20 *

Wait for RDRF

Get received byte

See if already programmed

If so, skip prog cycle

Put EPROM in prog mode

LDAB

CMPB

BEQ

SCDAT,X

$0,Y

DONEIT

#ELAT

PPROG,X

0,Y

#ELAT+EPGM

PPROG,X

LDAA

STAA

STAB

LDAA

STAA

PULA

PULB

PSHB

PSHA

ADDD

STD

Write the data

Turn on prog voltage

Pull delay constant

into D-reg

But also keep delay

keep delay on stack

Delay const + present TCNT

Schedule OC1 (2ms delay)

TCNT,X

TOC1,X

#OC1F

LDAA

STAA

TFLG1,X

Clear any previous flag

139 BF41 1F2380FC

140 BF45 6F3B

141

BRCLR TFLG1,X OC1F * Wait for delay to expire

CLR

PPROG,X

Turn off prog voltage

*

142 BF47

DONEIT

EQU

*

143 BF47 1F2E80FC

144 BF4B 18A600

145 BF4E A72F

146 BF50 1808

147 BF52 20CB

148

BRCLR SCSR,X $80 *

Wait for TDRE

Read from EPROM and...

Xmit for verify

Point at next location

Back to top for next

LDAA

STAA

INY

$0,Y

SCDAT,X

BRA

WAIT1

* Loops indefinitely as long as more data sent.

149

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Application Note

150

151

****************************************************

* Main bootloader starts here

152

153

****************************************************

* RESET vector points to here

154

155 BF54

BEGIN

EQU

*

156 BF54 8E01FF

157 BF57 CE1000

158 BF5A 1C2820

159 BF5D CCA20C

160 BF60 A72B

161

LDS

LDX

BSET

LDD

STAA

#RAMEND

#$1000

SPCR,X $20

#$A20C

BAUD,X

Initialize stack pntr

Point at internal regs

Select port D wire-OR mode

BAUD in A, SCCR2 in B

SCPx = ÷4, SCRx = ÷4

* Writing 1 to MSB of BAUD resets count chain

162 BF62 E72D

163 BF64 CC021B

164 BF67 ED16

165

STAB

LDD

STD

SCCR2,X

#DELAYF

TOC1,X

Rx and Tx Enabled

Delay for fast baud rate

Set as default delay

166

* Send BREAK to signal ready for download

BSET SCCR2,X $01 Set send break bit

BRSET PORTD,X $01 * Wait for RxD pin to go low

167 BF69 1C2D01

168 BF6C 1E0801FC

169 BF70 1D2D01

170 BF73

BCLR

SCCR2,X $01

Clear send break bit

171 BF73 1F2E20FC

172 BF77 A62F

173

BRCLR SCSR,X $20 *

LDAA SCDAT,X

* Data will be $00 if BREAK OR $00 received

Wait for RDRF

Read data

174 BF79 2603

175 BF7B 7EB600

176 BF7E

BNE

JMP

NOTZERO

EEPMSTR

*

Bypass JMP if not 0

Jump to EEPROM if it was 0

NOTZERO EQU

177 BF7E 81FF

178 BF80 2708

179

CMPA

BEQ

#$FF

BAUDOK

$FF will be seen as $FF

If baud was correct

* Or else change to ÷104 (÷13 & ÷8) 1200 @ 2MHZ

180 BF82 1C2B33

181 BF85 CC0DB0

182 BF88 ED16

183 BF8A

184 BF8A 18CE0000

185

BSET

LDD

STD

EQU

LDY

BAUD,X $33

#DELAYS

TOC1,X

*

Works because $22 -> $33

And switch to slower...

delay constant

BAUDOK

#RAMSTR

Point at start of RAM

186 BF8E

187 BF8E EC16

188 BF90

WAIT

EQU

LDD

EQU

*

TOC1,X

*

Move delay constant to D

WTLOOP

189 BF90 1E2E2007

190 BF94 8F

191 BF95 09

192 BF96 8F

193 BF97 26F7

194 BF99 200F

195

BRSET SCSR,X $20 NEWONE Exit loop if RDRF set

XGDX

DEX

Swap delay count to X

Decrement count

XGDX

BNE

BRA

Swap back to D

Loop if not timed out

Quit download on timeout

WTLOOP

STAR

196 BF9B

NEWONE

EQU

*

197 BF9B A62F

198 BF9D 18A700

199 BFA0 A72F

200 BFA2 1808

201 BFA4 188C0200

202 BFA8 26E4

LDAA

STAA

INY

CPY

BNE

SCDAT,X

$00,Y

SCDAT,X

Get received data

Store to next RAM location

Transmit it for handshake

Point at next RAM location

See if past end

#RAMEND+1

WAIT

If not, Get another

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Application Note

203

204 BFAA

STAR

EQU

LDX

LDY

JMP

*

205 BFAA CE1068

206 BFAD 18CED000

207 BFB1 7E0000

208 BFB4

#PROGDEL

#EPRMSTR

RAMSTR

Init X with programming delay

Init Y with EPROM start addr

** EXIT to start of RAM **

209

210

****************************************************

* Block fill unused bytes with zeros

211

212 BFB4 000000000000

000000000000

0000000000

BSZ

$BFD1-*

213

214

215

****************************************************

* Boot ROM revision level in ASCII

216

217 BFD1 41

218

*

(ORG

FCC

$BFD1)

"A"

****************************************************

* Mask set I.D. ($0000 FOR EPROM PARTS)

219

220

*

(ORG

FDB

$BFD2)

$0000

221 BFD2 0000

222

223

****************************************************

* '711E9 I.D. - Can be used to determine MCU type

224

*

(ORG

FDB

$BFD4)

$71E9

225 BFD4 71E9

226

227

228

****************************************************

* VECTORS - point to RAM for pseudo-vector JUMPs

229

230 BFD6 00C4

231 BFD8 00C7

232 BFDA 00CA

233 BFDC 00CD

234 BFDE 00D0

235 BFE0 00D3

236 BFE2 00D6

237 BFE4 00D9

238 BFE6 00DC

239 BFE8 00DF

240 BFEA 00E2

241 BFEC 00E5

242 BFEE 00E8

243 BFF0 00EB

244 BFF2 00EE

245 BFF4 00F1

246 BFF6 00F4

247 BFF8 00F7

248 BFFA 00FA

249 BFFC 00FD

250 BFFE BF54

251 C000

FDB

END

$100-60

$100-57

$100-54

$100-51

$100-48

$100-45

$100-42

$100-39

$100-36

$100-33

$100-30

$100-27

$100-24

$100-21

$100-18

$100-15

$100-12

$100-9

SCI

SPI

PULSE ACCUM INPUT EDGE

PULSE ACCUM OVERFLOW

TIMER OVERFLOW

TIMER OUTPUT COMPARE 5

TIMER OUTPUT COMPARE 4

TIMER OUTPUT COMPARE 3

TIMER OUTPUT COMPARE 2

TIMER OUTPUT COMPARE 1

TIMER INPUT CAPTURE 3

TIMER INPUT CAPTURE 2

TIMER INPUT CAPTURE 1

REAL TIME INT

IRQ

XIRQ

SWI

ILLEGAL OP-CODE

COP FAIL

CLOCK MONITOR

RESET

$100-6

$100-3

BEGIN

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Application Note

Symbol Table:

Symbol Name

Value Def.# Line Number Cross Reference

BAUD

002B *00037 00160 00180

BF8A *00183 00178

BF54 *00155 00250

021B *00061 00163

0DB0 *00060 00181

BF47 *00142 00124

B7FF *00050

B600 *00049 00175

0020 *00043 00125 00128

0001 *00044 00128

BAUDOK

BEGIN

DELAYF

DELAYS

DONEIT

EEPMEND

EEPMSTR

ELAT

EPGM

EPRMEND

EPRMSTR

NEWONE

NOTZERO

OC1F

PORTD

PPROG

PRGROUT

PROGDEL

PROGRAM

RAMEND

RAMSTR

SCCR2

SCDAT

SCSR

FFFF *00053

D000 *00052 00206

BF9B *00196 00189

BF7E *00176 00174

0080 *00034 00136 00139

0008 *00029 00168

003B *00041 00126 00129 00140

BF13 *00110 00074

1068 *00063 00205

BF00 *00074

01FF *00056 00156 00201

0000 *00055 00184 00207

002D *00038 00162 00167 00169

002F *00040 00091 00118 00122 00145 00172 00197 00199

002E *00039 00090 00116 00121 00143 00171 00189

0028 *00036 00158

SPCR

STAR

BFAA *00204 00194

TCNT

000E *00030 00134

TFLG1

TOC1

UPLOAD

UPLOOP

WAIT

0023 *00032 00137 00139

0016 *00031 00135 00164 00182 00187

BF03 *00075

BF06 *00089 00093

BF8E *00186 00202

WAIT1

WTLOOP

BF1F *00120 00147

BF90 *00188 00193

Errors: None

Labels: 35

Last Program Address: $BFFF

Last Storage Address: $0000

Program Bytes: $0100 256

Storage Bytes: $0000

0

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Order this document

by EB184/D

Motorola Semiconductor Engineering Bulletin

EB184

Enabling the Security Feature on the MC68HC711E9

Devices with PCbug11 on the M68HC711E9PGMR

By Edgar Saenz

Austin, Texas

Introduction

The PCbug11 software, needed along with the M68HC711E9PGMR to

program MC68HC711E9 devices, is available from the download

section of the Microcontroller Worldwide Web site

http://www.motorola.com/semiconductors/.

Retrieve the file pcbug342.exe (a self-extracting archive) from the

MCU11 directory.

Some Motorola evaluation board products also are shipped with

PCbug11.

NOTE: For specific information about any of the PCbug11 commands, see the

appropriate sections in the PCbug11 User's Manual (part number

M68PCBUG11/D2), which is available from the Motorola Literature

Distribution Center, as well as the Worldwide Web at

http://www.motorola.com/semiconductors/. The file is also on the

software download system and is called pcbug11.pdf.

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To Execute the Program

Use this step-by-step procedure to program the MC68HC711E9 device.

Step 1

•

Before applying power to the programming board, connect the

M68HC711E9PGMR serial port P2 to one of your PC COM ports

with a standard 25-pin RS-232 cable. Do not use a null modem

cable or adapter which swaps the transmit and receive signals

between the connectors at each end of the cable.

•

Place the MC68HC711E9 part in the PLCC socket on your board.

Insert the part upside down with the notched corner pointing

toward the red power LED.

•

Make sure both S1 and S2 switches are turned off.

Apply +5 volts to +5-V, +12 volts (at most +12.5 volts) to V , and

PP

ground to GND on your programmer board’s power connector, P1.

The remaining TXD/PD1 and RXD/PD0 connections are not used

in this procedure. They are for gang programming MC68HC711E9

devices, which is discussed in the M68HC711E9PGMR Manual.

You cannot gang program with PCbug11.

•

Ensure that the "remove for multi-programming" jumper, J1, below

the +5-V power switch has a fabricated jumper installed.

Step 2

Apply power to the programmer board by moving the +5-V switch to the

ON position. From a DOS command line prompt, start PCbug11this way:

C:\PCBUG11\ > PCBUG11 –E PORT = 1

with the E9PGMR connected to COM1

or

C:\PCBUG11\ > PCBUG11 –E PORT = 2

with the E9PGMR connected to COM2

PCbug11 only supports COM ports 1 and 2. If the proper connections

are made and you have a high-quality cable, you should quickly get a

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PCbug11 command prompt. If you do receive a Comms fault error,

check the cable and board connections. Most PCbug11 communications

problems can be traced to poorly made cables or bad board

connections.

Step 3

Step 4

PCbug11 defaults to base 10 for its input parameters.

Change this to hexadecimal by typing: CONTROL BASE HEX.

Clear the block protect register (BPROT) to allow programming of the

MC68HC711E9 EEPROM.

At the PCbug11 command prompt, type: MS 1035 00.

Step 5

The CONFIG register defaults to hexadecimal 103F on the

MC68HC711E9. PCBUG11 needs adressing parameters to allow

programming of a specific block of memory so the following parameter

must be given.

At the PCbug11 command prompt, type: EEPROM 0.

Then type: EEPROM 103F 103F.

Step 6

Step 7

Erase the CONFIG to allow byte programming.

At the PCbug11 command prompt, type: EEPROM ERASE BULK 103F.

You are now ready to download the program into the EEPROM and

EPROM.

At the PCbug11command prompt, type:

LOADSC:\MYPROG\MYPROG.S19.

For more details on programming the EPROM, read the engineering

bulletin Programming MC68HC711E9 Devices with PCbug11 and the

M68HC11EVB, Motorola document number EB187.

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Step 8

You are now ready to enable the security feature on the MCHC711E9.

At the PCbug11 command prompt type: MS 103F 05.

Step 9

Step 10

After the programming operation is complete, verifyng the CONFIG on

the MCHC711E9 is not possible because in bootstrap mode the default

value is always forced.

The part is now in secure mode and whatever code you loaded into

EEPROM will be erased if you tried to bring the microcontroller up in

either expanded mode or bootstrap mode.

NOTE: It is important to note that the microcontroller will work properly in secure

mode only in single chip mode.

NOTE: If the part is placed in bootstrap or expanded, the code in EEPROM and

RAM will be erased and the microcontroller cannot be reused. The

security software will constantly read the NOSEC bit and lock the part.

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EB188

Enabling the Security Feature on M68HC811E2 Devices

with PCbug11 on the M68HC711E9PGMR

By Edgar Saenz

Austin, Texas

Introduction

The PCbug11 software, needed along with the M68HC711E9PGMR to

program MC68HC811E2 devices, is available from the download

section of the Microcontroller Worldwide Web site

http://www.motorola.com/semiconductors/.

Retrieve the file pcbug342.exe (a self-extracting archive) from the

MCU11 directory.

Some Motorola evaluation board products also are shipped with

PCbug11.

NOTE: For specific information about any of the PCbug11 commands, see the

appropriate sections in the PCbug11 User's Manual (part number

M68PCBUG11/D2), which is available from the Motorola Literature

Distribution Center, as well as the Worldwide Web at

http://www.motorola.com/semiconductors/. The file is also on the

software download system and is called pcbug11.pdf.

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To Execute the Program

Once you have obtained PCbug11, use this step-by-step procedure.

Step 1

•

Before applying power to the programming board, connect the

M68HC711E9PGMR serial port P2 to one of your PC COM ports

with a standard 25 pin RS-232 cable. Do not use a null modem

cable or adapter which swaps the transmit and receive signals

between the connectors at each end of the cable.

•

Place your MC68HC811E2 part in the PLCC socket on your

board.

Insert the part upside down with the notched corner pointing

toward the red power LED.

•

Make sure both S1 and S2 switches are turned off.

Apply +5 volts to +5 volts and ground to GND on the programmer

board’s power connector, P1. Applying voltage to the V pin is

PP

not necessary.

Step 2

Apply power to the programmer board by moving the +5-volt switch to

the ON position.

From a DOS command line prompt, start PCbug11 this way:

•

C:\PCBUG11\> PCBUG11 –A PORT = 1

when the E9PGMR connected to COM1 or

C:\PCBUG11\> PCBUG11 –A PORT = 2

when the E9PGMR connected to COM2

PCbug11only supports COM ports 1 and 2.

Step 3

PCbug11 defaults to base ten for its input parameters.

Change this to hexadecimal by typing

CONTROL BASE HEX

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Step 4

Clear the block protect register (BPROT) to allow programming of the

MC68HC811E2 EEPROM.

At the PCbug11 command prompt, type

MS 1035 00

Step 5

PCbug11 defaults to a 512-byte EEPROM array located at $B600. This

must be changed since the EEPROM is, by default, located at $F800 on

the MC68HC811E2.

At the PCbug11 command prompt, type

EEPROM 0

Then type: EEPROM F800 FFFF

EEPROM 103F 103F

This assumes you have not relocated the EEPROM by previously

reprogramming the upper 4 bits of the CONFIG register. But if you have

done this and your S records reside in an address range other than

$F800 to $FFFF, you will need to first relocate the EEPROM.

Step 6

Erase the CONFIG to allow programming of NOSEC bit (bit 3). It is also

recommended to program the EEPROM at this point before

programming the CONFIG register. Refer to the engineering bulletin

Programming MC68HC811E2 Devices with PCbug11 and the

M68HC711E9PGMR, Motorola document number EB184.

At the PCbug11command prompt, type

EEPROM ERASE BULK 103F

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Step 7

You are now ready to enable the security feature on the MCHC811E2.

At the PCbug11 command prompt, type

MS 103F 05

The value $05 assumes the EEPROM is to be mapped from $0800 to

$0FFF.

Step 8

Step 9

After the programming operation is complete, verifying the CONFIG on

the MCHC811E2 is not possible because in bootstrap mode the default

value is always forced.

The part is now in secure mode and whatever code you loaded into

EEPROM will be erased if you tried to bring the microcontroller up in

either expanded mode or bootstrap mode. The microcontroller will work

properly in the secure mode only in single chip mode.

NOTE: If the part is placed in bootstrap mode or expanded mode, the code in

EEPROM and RAM will be erased the microcontroller can be reused.

EB188

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EB296

Programming MC68HC711E9 Devices with PCbug11

and the M68HC11EVBU

By John Bodnar

Austin, Texas

Introduction

The PCbug1software, needed along with the M68HC11EVBU to

program MC68HC711E9 devices, is available from the download

section of the Microcontroller Worldwide Web site

http://www.motorola.com/semiconductors/.

Retrieve the file pcbug342.exe (a self-extracting archive) from the

MCU11 directory.

Some Motorola evaluation board products also are shipped with

PCbug11.

For specific information about any of the PCbug11 commands, see the

appropriate sections in the PCbug11 User's Manual (part number

M68PCBUG11/D2), which is available from the Motorola Literature

Distribution Center, as well as the Worldwide Web at

http://www.motorola.com/semiconductors/. The file is also on the

software download system and is called pcbug11.pdf.

EB296

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Programming Procedure

Once you have obtained PCbug11, use this step-by-step procedure to

program your MC68HC711E9 part.

Step 1

•

Before applying power to the EVBU, remove the jumper from J7

and place it across J3 to ground the MODB pin.

Place a jumper across J4 to ground the MODA pin. This will force

the EVBU into special bootstrap mode on power up.

•

Remove the resident MC68HC11E9 MCU from the EVBU.

Place your MC68HC711E9 in the open socket with the notched

corner of the part aligned with the notch on the PLCC socket.

•

Connect the EVBU to one of your PC COM ports. Apply +5 volts

to V and ground to GND on the power connector of your EVBU.

DD

Also take note of P4 connector pin 18. In step 5, you will connect a +12-

volt (at most +12.5 volts) programming voltage through a 100-Ω current

limiting resistor to the XIRQ pin. Do not connect this programming

voltage until you are instructed to do so in step 5.

Step 2

•

From a DOS command line prompt, start PCbug11 with

– C:\PCBUG11\> PCBUG11 –E PORT = 1

with the EVBU connected to COM1

– C:\PCBUG11\> PCBUG11 –E PORT = 2

with the EVBU connected to COM2

PCbug11 only supports COM ports 1 and 2. If you have made the

proper connections and have a high quality cable, you should

quickly get a PCbug11 command prompt. If you do receive a

Comms fault error, check your cable and board connections.

Most PCbug11 communications problems can be traced to poorly

made cables or bad board connections.

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Step 3

Step 4

Step 5

•

PCbug11 defaults to base 10 for its input parameters; change this

to hexadecimal by typing

CONTROL BASE HEX

You must declare the addresses of the EPROM array to PCbug11.

To do this, type

EPROM D000 FFFF

You are now ready to download your program into the EPROM.

•

Connect +12 volts (at most +12.5 volts) through a 100-Ω current

limiting resistor to P4 connector pin 18, the XIRQ* pin.

At the PCbug11 command prompt type

LOADS C:\MYPROG\ISHERE.S19

Substitute the name of your program into the command above.

Use a full path name if your program is not located in the same

directory as PCbug11.

Step 8

After the programming operation is complete, PCbug11 will display this

message

Total bytes loaded: $xxxx

Total bytes programmed: $yyyy

•

You should now remove the programming voltage from P4

connector pin 18, the XIRQ* pin.

Each ORG directive in your assembly language source will cause

a pair of these lines to be generated. For this operation, $yyyy will

be incremented by the size of each block of code programmed

into the EPROM of the MC68HC711E9.

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•

PCbug11 will display the above message whether or not the

programming operation was successful. As a precaution, you

should have PCbug11 verify your code.

At the PCbug11 command prompt type

VERF C:\MYPROG\ISHERE.S19

Substitute the name of your program into the command above.

Use a full path name if your program is not located in the same

directory as PCbug11.

If the verify operation fails, a list of addresses which did not

program correctly is displayed. Should this occur, you probably

need to erase your part more completely. To do so, allow the

MC68HC711E9 to sit for at least 45 minutes under an ultraviolet

light source. Attempt the programming operation again. If you

have purchased devices in plastic packages (one-time

programmable parts), you will need to try again with a new,

unprogrammed device.

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HOW TO REACH US:

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P.O. Box 5405

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1-800-521-6274 or 480-768-2130

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Tokyo 106-8573, Japan

81-3-3440-3569

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Information in this document is provided solely to enable system and software implementers to use Motorola products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or

integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume

any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Motorola

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Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,

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names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

M68HC11E/D

Rev. 5

6/2003

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型号：	MC68HC11E9CB3
厂家：	MOTOROLA
描述：	Microcontrollers 微控制器微控制器和处理器外围集成电路
文件：	总268页 (文件大小：3562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC68HC11E9CB3 [MOTOROLA]

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