MC68HC812A4PV8 [MOTOROLA]
Microcontroller, 16-Bit, EEPROM, 6800 CPU, 8MHz, HCMOS, PQFP112, LQFP-112;
| 型号： | MC68HC812A4PV8 |
| 厂家： | 
MOTOROLA |
| 描述： | Microcontroller, 16-Bit, EEPROM, 6800 CPU, 8MHz, HCMOS, PQFP112, LQFP-112 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总16页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM63P631A/D
SEMICONDUCTOR TECHNICAL DATA
MCM63P631A
Product Preview
64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P631A is a 2M bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family, Pow-
erPC , and Pentium microprocessors. It is organized as 64K words of 32 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). CMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-
trolled through positive–edge–triggered noninverting registers.
TQ PACKAGE
TQFP
CASE 983A–01
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P631A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggeredoutput register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs
are LVTTL compatible.
•
MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)
Single 3.3 V + 10%, – 5% Power Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Sleep Mode (ZZ)
PB1 Version 2.0 Compatible
Single–Cycle Deselect Timing
•
•
•
•
•
•
•
•
•
JEDEC Standard 100–Pin TQFP Package
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
9/30/97
Motorola, Inc. 1997
FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K
BURST
COUNTER
CLR
2
16
ADSC
ADSP
64K x 32 ARRAY
K2
2
SA
SA1
SA0
16
14
ADDRESS
REGISTER
SGW
SW
WRITE
REGISTER
a
32
32
SBa
WRITE
REGISTER
b
SBb
SBc
4
DATA–IN
REGISTER
DATA–OUT
REGISTER
WRITE
REGISTER
c
K
WRITE
REGISTER
d
SBd
K2
K
SE1
SE2
SE3
ENABLE
REGISTER
ENABLE
REGISTER
G
DQa – DQd
ZZ
MCM63P631A
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQc
DQc
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
NC
DQb
DQb
2
3
4
V
V
DD
SS
V
V
DQb
DQb
DD
SS
5
6
7
DQc
DQc
DQc
DQc
8
9
10
DQb
DQb
V
V
SS
DD
V
V
SS
DD
11
12
13
14
15
DQc
DQb
DQb
DQc
NC
V
SS
NC
V
DD
NC
16
17
V
ZZ
65
64
63
DD
V
SS
DQd
DQd
18
19
20
DQa
DQa
62
61
V
DD
V
V
DD
SS
V
21
22
23
24
25
SS
60
59
58
DQd
DQa
DQa
DQa
DQa
DQd
DQd
DQd
57
56
V
V
V
SS
DD
DQd
DQd
NC
26
27
28
29
55
54
53
52
51
SS
V
DD
DQa
DQa
NC
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCM63P631A
3
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
84
83
ADSC
Input
Synchronous Address Status Controller: Active low, is used to latch a
new external address. Used to initiate a READ, WRITE or chip
deselect.
ADSP
Input
Synchronous Address Status Processor: Initiates READ or chip
deselect cycle (exception — chip deselect does not occur when ADSP
is asserted and SE1 is high).
ADV
DQx
Input
I/O
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
(d) 18, 19, 22, 23, 24, 25, 28, 29
86
89
G
K
Input
Input
Asynchronous Output Enable.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 81, 82, 99, 100
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
SE1
Input
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW overrides SBx.
98
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
92
88
SE2
SE3
Input
Input
Input
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
SGW
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
64
SW
ZZ
Input
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4, 11, 15, 20, 27, 41,
54, 61, 65, 70, 77, 91
V
DD
Supply Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
V
SS
Supply Ground.
1, 14, 16, 30, 38, 39,
42, 43, 50, 51, 66, 80
NC
—
No Connection: There is no connection to the chip.
MCM63P631A
MOTOROLA FAST SRAM
4
TRUTH TABLE (See Notes 1 through 5)
Address
Used
3
2, 4
Next Cycle
Deselect
SE1
1
SE2
X
X
0
SE3
X
1
ADSP
ADSC
ADV
X
X
X
X
X
X
X
0
G
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
Write
None
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
Deselect
None
0
X
X
X
X
X
X
1
Deselect
None
0
X
1
X
Deselect
None
X
X
0
X
0
X
Deselect
None
X
0
X
5
5
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
External
External
Next
1
READ
0
1
0
READ
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
Next
0
0
Next
0
1
High–Z
DQ
Next
1
0
0
Current
Current
Current
Current
External
Next
X
X
1
1
1
High–Z
DQ
1
0
1
1
High–Z
DQ
1
1
0
0
X
0
X
X
X
X
X
High–Z
High–Z
High–Z
High–Z
High–Z
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES:
X
1
X
X
X
X
X
X
X
X
Next
0
Current
Current
X
1
1
1
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t
) following G going low.
GLQX
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This READ assumes the RAM was previously deselected.
MCM63P631A
5
MOTOROLA FAST SRAM
ASYNCHRONOUS TRUTH TABLE
Operation
Read
ZZ
L
G
L
I/O Status
Data Out (DQx)
High–Z
Read
L
H
X
X
X
Write
L
High–Z
Deselected
Sleep
L
High–Z
H
High–Z
LINEAR BURST ADDRESS TABLE (LBO = V
)
SS
1st Address (External)
X . . . X00
2nd Address (Internal)
X . . . X01
3rd Address (Internal)
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X01
X . . . X10
X . . . X00
X . . . X10
X . . . X11
X . . . X01
X . . . X11
X . . . X00
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = V
)
DD
1st Address (External)
X . . . X00
2nd Address (Internal)
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X01
X . . . X11
X . . . X10
X . . . X10
X . . . X00
X . . . X01
X . . . X11
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
Read
SGW
H
SW
H
L
SBa
X
SBb
X
SBc
X
SBd
X
Read
H
H
H
H
H
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
H
L
L
H
H
H
H
L
H
L
H
H
H
L
H
H
L
H
H
L
H
H
H
L
H
L
L
L
L
L
L
X
X
X
X
X
MCM63P631A
6
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (See Note 1)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Symbol
Value
Unit Notes
Power Supply Voltage
V
DD
– 0.5 to + 4.6
V
V
Voltage Relative to V
for Any
V , V
in out
– 0.5 to V + 0.5
DD
SS
Pin Except V
DD
Output Current (per I/O)
I
± 20
mA
out
Package Power Dissipation
Ambient Temperature
Die Temperature
P
1.6
0 to 70
W
°C
°C
°C
°C
2
2
D
T
A
T
110
J
Temperature Under Bias
Storage Temperature
NOTES:
T
bias
– 10 to 85
– 55 to 125
T
stg
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
40
25
°C/W
1, 2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
17
9
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
MCM63P631A
7
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to V
= 0 V)
SS
Parameter
Supply Voltage
Symbol
Min
3.135
– 0.5
2.0
Typ
3.3
—
Max
3.6
Unit
V
V
DD
Input Low Voltage
V
IL
0.8
V
Input High Voltage
V
IH
—
V
+ 0.5
V
DD
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
(I)
Min
—
Typ
—
Max
± 1
Unit
µA
Notes
Input Leakage Current (0 V ≤ V ≤ V
in
)
I
1, 2
DD
lkg
Output Leakage Current (0 V ≤ V ≤ V
in
)
I (O)
lkg
—
—
± 1
µA
DD
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max, V = Max)
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
I
—
—
—
—
—
—
—
—
TBD
mA
3, 4, 5
DDA
DD
CMOS Standby Supply Current (Device Deselected, Freq = 0,
= Max, All Inputs Static at CMOS Levels)
I
—
—
—
—
—
—
TBD
2
mA
mA
mA
mA
6, 7
2, 7, 8
6, 9
SB2
V
DD
Sleep Mode Supply Current (Sleep Mode, Freq = Max, V
= Max,
I
ZZ
DD
– 0.2 V)
All Other Inputs Static at CMOS Levels, ZZ ≥ V
DD
TTL Standby (Device Deselected, Freq = 0, V
All Inputs Static at TTL Levels)
= Max,
I
TBD
TBD
DD
SB3
Clock Running (Device Deselected, Freq = Max,
= Max, All Inputs Toggling at CMOS Levels)
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
I
—
—
—
—
—
—
—
—
6, 7
SB4
V
DD
Static Clock Running (Device Deselected, Freq = Max,
= Max, All Inputs Static at TTL Levels)
MCM63P631A–117
MCM63P631A–100
MCM63P631A–75
MCM63P631A–66
I
—
—
—
—
—
—
—
—
TBD
mA
6, 9
SB5
V
DD
Output Low Voltage (I
= 8 mA)
V
—
—
—
0.4
—
V
V
OL
OL
Output High Voltage (I
= – 4 mA)
V
OH
2.4
OH
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of ± 5 µA.
2. ZZ pin has an internal pulldown and will exhibit leakage currents of ± 5 µA.
3. Reference AC Operating Conditions and Characteristics for input and timing (V /V , t /t , pulse level 0 to 3.0 V).
IH IL r f
4. All addresses transition simultaneously low (LSB) and then high (MSB).
5. Data states are all zero.
6. Device in Deselected mode as defined by the Truth Table.
7. CMOS levels are V ≤ V
in
+ 0.2 V or ≥ V
– 0.2 V.
DD
SS
8. Device in Sleep Mode as defined by the Asynchronous Truth Table.
9. TTL levels are V ≤ V or ≥ V
.
IH
in IL
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Min
—
Typ
3
Max
Unit
pF
Input Capacitance
C
5
8
in
Input/Output Capacitance
C
—
6
pF
I/O
MCM63P631A
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
63P631A–117
117 MHz
63P631A–100
100 MHz
63P631A–75
75 MHz
63P631A–66
66 MHz
Parameter
Symbol
Min
8.5
3.4
3.4
—
Max
—
Min
10
4
Max
—
Min
13
5.2
5.2
—
—
0
Max
—
—
—
7
Min
15
6
Max
—
—
—
8
Unit Notes
Cycle Time
t
ns
ns
ns
ns
ns
KHKH
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
t
—
—
KHKL
KLKH
KHQV
t
—
4
—
6
t
4.5
4.5
—
—
—
0
4.5
4.5
—
—
—
0
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
Setup Times:
t
—
5
5
GLQV
t
t
0
—
—
—
7
—
—
—
8
ns
ns
ns
ns
ns
ns
5
5
KHQX1
KHQX2
1.5
0
—
1.5
0
—
1.5
0
1.5
0
t
—
—
5
GLQX
GHQZ
t
—
5.5
5.5
—
—
1.5
2.5
5.5
5.5
—
—
2
—
2
5, 6
5, 6
t
1.5
2.5
7
8
KHQZ
2.5
—
2.5
—
Address
t
ADKH
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
t
ADSKH
DVKH
t
t
WVKH
t
EVKH
Hold Times:
0.5
—
0.5
—
0.5
—
0.5
—
ns
Address
ADSP, ADSC,
ADV
Data In
Write
Chip Enable
t
KHAX
t
KHADSX
t
KHDX
t
KHWX
t
KHEX
Sleep Mode Standby
t
—
2 x
—
2 x
—
2 x
—
2 x
t
KHKH
ns
ns
ns
ZZS
t
t
t
KHKH
KHKH
KHKH
Sleep Mode Recovery
t
2 x
—
2 x
—
2 x
—
2 x
t
KHKH
—
ZZREC
t
t
t
KHKH
KHKH
KHKH
Sleep Mode High to Q High–Z
NOTES:
t
—
15
—
15
—
15
—
15
ZZQZ
1. Write applies to all SBx, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. This parameter is sampled and is not 100% tested.
6. Measured at ± 200 mV from steady state.
OUTPUT
R
= 50 Ω
Z
= 50 Ω
L
0
V
= 1.5 V
T
Figure 1. AC Test Load
MCM63P631A
9
MOTOROLA FAST SRAM
MCM63P631A
10
MOTOROLA FAST SRAM
MCM63P631A
11
MOTOROLA FAST SRAM
APPLICATION INFORMATION
The MCM63P631A BurstRAM is a high speed synchro-
Allowed, and Sleep Mode. Each mode has its own set of
constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
nous SRAM intended for use primarily in secondary or level
two (L2) cache memory applications. L2 caches are found in
a variety of classes of computers — from the desktop per-
sonal computer to the high–end servers and transaction pro-
cessing machines. For simplicity, the majority of L2 caches
today are direct mapped and are single bank implementa-
tions. These caches tend to be designed for bus speeds in
the range of 33 to 66 MHz. At these bus rates, non–pipelined
(flow–through) BurstRAMs can be used since their access
times meet the speed requirements for a minimum–latency,
zero–wait state L2 cache interface. Latency is a measure
(time) of “dead” time the memory system exhibits as a result
of a memory request.
For those applications that demand bus operation at great-
er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe-
lined (register/register) version of the 64K x 32 BurstRAM
(MCM63P631A) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create addi-
tional bus loading and can cause the system to otherwise
miss its timing requirements. The access time (clock–to–val-
id–data) of a pipelined BurstRAM is inherently faster than a
non–pipelined device by a few nanoseconds. This does not
come without cost. The cost is latency — “dead” time.
Since most L2 caches are tied to the processor bus and
bus speeds continue to increase over time, pipelined (R/R)
BurstRAMs are the best choice in achieving zero–wait state
L2 cache performance. For cost–sensitive applications that
require zero–wait state L2 cache bus speeds of up to 75 MHz,
pipelined BurstRAMs are able to provide fast clock to valid
data times required of these high speed buses.
times prior to sleep and t
nanoseconds after
ZZREC
recovering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to
sleep, initiation of either a read or write operation is not al-
lowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to be-
ing in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep cur-
rent (I ). All inputs are allowed to toggle — the RAM will not
ZZ
be selected and perform any reads or writes. However, if in-
puts toggle, the I (max) specification will not be met.
ZZ
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and Pentium–based systems, these SRAMs can be used in
other high speed L2 cache or memory applications that do
not require the burst address feature. Most L2 caches de-
signed with a synchronous interface can make use of the
MCM63P631A. The burst counter feature of the BurstRAM
can be disabled, and the SRAM can be configured to act
upon a continuous stream of addresses. See Figure 2.
CONTROL PIN TIE VALUES (H ≥ V , L ≤ V
IH
)
IL
SLEEP MODE
Non–Burst
ADSP ADSC ADV
SE1
LBO
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P631A. It allows the system designer to place
the RAM in the lowest possible power condition by asserting
ZZ. The sleep mode timing diagram shows the different
modes of operation: Normal Operation, No READ/WRITE
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
MCM63P631A
12
MOTOROLA FAST SRAM
K
ADDR
W
A
B
C
D
E
F
G
H
G
DQx
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 2. Configured as Non–Burst Pipelined Synchronous SRAM
MCM63P631A
13
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
63P631A XX
X
X
Blank = Trays, R = Tape and Reel
Motorola Memory Prefix
Part Number
Speed (117 = 117 MHz, 100 = 100 MHz,
75 = 75 MHz, 66 = 66 MHz)
Package (TQ = TQFP)
Full Part Numbers — MCM63P631ATQ117
MCM63P631ATQ100
MCM63P631ATQ100R
MCM63P631ATQ117R
MCM63P631ATQ75
MCM63P631ATQ75R
MCM63P631ATQ66
MCM63P631ATQ66R
MCM63P631A
14
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X
80
e
0.20 (0.008)
H
A–B
D
2X 30 TIPS
e/2
0.20 (0.008)
C
A–B
D
–D–
51
50
81
B
B
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
E1/2
b1
31
100
1
30
c1
c
D1/2
D/2
b
D1
D
M
S
S
0.13 (0.005)
C
A–B
D
2X 20 TIPS
0.20 (0.008)
SECTION B–B
C
A–B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2
3
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
0.10 (0.004)
C
–H–
–C–
SEATING
PLANE
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
VIEW AB
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
S
0.05 (0.002)
S
1
0.25 (0.010)
GAGE PLANE
R2
A2
MILLIMETERS
INCHES
MIN
DIM
A
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
–––
0.002
0.053
0.009
0.009
0.004
0.004
A1
A2
b
b1
c
0.05
1.35
0.22
0.22
0.09
0.09
L2
L
R1
A1
L1
c1
D
D1
E
E1
e
VIEW AB
22.00 BSC
0.866 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
1
2
3
0
11
11
–––
13
13
0
11
11
–––
13
13
MCM63P631A
15
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
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