MC68HSC05C9ACFN [MOTOROLA]
8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44;
| 型号： | MC68HSC05C9ACFN |
| 厂家： | 
MOTOROLA |
| 描述： | 8-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQCC44, PLASTIC, LCC-44 时钟 外围集成电路 |
| 文件： | 总162页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC05C9A/D
REV 5
MC68HC05C9A
MC68HCL05C9A
MC68HSC05C9A
Advance Information
HCMOS
Microcontroller Unit
blank
MC68HC05C9A
MC68HCL05C9A
MC68HSC05C9A
Advance Information
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 1997, 2000
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .19
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .37
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .55
Section 7. Input/Output Ports . . . . . . . . . . . . . . . . . . . . .57
Section 8. Capture/Compare Timer . . . . . . . . . . . . . . . . .61
Section 9. Serial Communications Interface (SCI). . . . .73
Section 10. Serial Peripheral Interface (SPI). . . . . . . . . .91
Section 11. Instruction Set. . . . . . . . . . . . . . . . . . . . . . .103
Section 12. Electrical Specifications. . . . . . . . . . . . . . .121
Section 13. Mechanical Specifications . . . . . . . . . . . . .137
Section 14. Ordering Information . . . . . . . . . . . . . . . . .141
Appendix A. MC68HCL05C9A . . . . . . . . . . . . . . . . . . . .143
Appendix B. MC68HSC05C9A . . . . . . . . . . . . . . . . . . . .147
Appendix C. Self-Check Mode . . . . . . . . . . . . . . . . . . . .155
Appendix D. M68HC05Cx Family
Feature Comparisons . . . . . . . . . . . . .159
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Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Software-Programmable Options . . . . . . . . . . . . . . . . . . . . . . .22
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PB0–PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.6.10 PD0–PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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Section 3. Central Processor Unit (CPU)
3.1
3.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . .40
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Non-Maskable Software Interrupt (SWI). . . . . . . . . . . . . . . . . .42
External Interrupt (IRQ or Port B). . . . . . . . . . . . . . . . . . . . . . .42
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 5. Resets
5.1
5.2
5.3
5.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.5
5.5.1
5.5.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .50
COP Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.6
5.7
5.8
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
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Section 6. Low-Power Modes
6.1
6.2
6.3
6.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Section 7. Input/Output Ports
7.1
7.2
7.3
7.4
7.5
7.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Section 8. Capture/Compare Timer
8.1
8.2
Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.3
8.3.1
8.3.2
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Alternate Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .68
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . .70
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Section 9. Serial Communications Interface (SCI)
Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
9.1
9.2
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9.3
9.4
9.5
9.6
9.7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.8
9.8.1
9.8.2
Receiver Wakeup Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .78
Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Address Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.9
Receive Data In (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.10 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.11 Transmit Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.12 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.12.1 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.12.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.12.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
9.12.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.12.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Section 10. Serial Peripheral Interface (SPI)
10.1 Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.4.1 Master In/Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . .93
10.4.2 Master Out/Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . .93
10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . .97
10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . .99
10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . .101
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Section 11. Instruction Set
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
11.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .107
11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .108
11.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .109
11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .111
11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Section 12. Electrical Specifications
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
12.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.3 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.5 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
12.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .125
12.7 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .126
12.8 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
12.9 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12.10 5.0-Volt Serial Peripheral Interface Timing. . . . . . . . . . . . . . .132
12.11 3.3-Volt Serial Peripheral Interface Timing. . . . . . . . . . . . . . .133
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Section 13. Mechanical Specifications
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3 40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package
(Case 858-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
13.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
13.6 44-Lead Quad Flat Pack (QFP)
(Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Section 14. Ordering Information
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
14.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Appendix A. MC68HCL05C9A
A.1
A.2
A.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
A.4
DC Electrical Characeristics . . . . . . . . . . . . . . . . . . . . . . . . . .144
1.8–2.4-Volt Low-Power Output Voltage . . . . . . . . . . . . . .144
1.8–2.4-Volt Input Pullup Current. . . . . . . . . . . . . . . . . . . .144
2.5–3.6-Volt Low-Power Output Voltage . . . . . . . . . . . . . .145
2.6–3.6-Volt Input Pullup Current. . . . . . . . . . . . . . . . . . . .145
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . .146
A.4.1
A.4.2
A.4.3
A.4.4
A.4.5
Appendix B. MC68HSC05C9A
B.1
B.2
B.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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12
MC68HC05C9A — Rev. 5.0
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MOTOROLA
Table of Contents
B.4
B.4.1
B.4.2
DC Electrical Characeristics . . . . . . . . . . . . . . . . . . . . . . . . . .149
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . .149
Input Pullup Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
B.5
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
4.5–5.5-Volt High-Speed Control Timing . . . . . . . . . . . . . .150
2.4–3.6-Volt High-Speed Control Timing . . . . . . . . . . . . . .151
4.5–5.5-Volt High-Speed Control Timing . . . . . . . . . . . . . .152
2.4–3.6-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . .153
B.5.1
B.5.2
B.5.3
B.5.4
Appendix C. Self-Check Mode
C.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
C.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
C.3.1
C.3.2
Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Appendix D. M68HC05Cx Family
Feature Comparisons
MC68HC05C9A — Rev. 5.0
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MOTOROLA
Table of Contents
13
Table of Contents
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14
MC68HC05C9A — Rev. 5.0
Table of Contents
MOTOROLA
Advance Information — MC68HC05C9A
List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .23
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . .24
44-Lead PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .25
44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .26
2-1
2-2
2-3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5-1
5-2
5-3
5-4
5-5
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Power-On Reset and RESET . . . . . . . . . . . . . . . . . . . . . . . . . .49
COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
COP Reset Register (COPRST). . . . . . . . . . . . . . . . . . . . . . . .51
COP Control Register (COPCR). . . . . . . . . . . . . . . . . . . . . . . .52
6-1
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .56
7-1
7-2
Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
8-1
8-2
8-3
8-4
8-5
8-6
8-7
Capture/Compare Timer Block Diagram. . . . . . . . . . . . . . . . . .62
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .66
Timer Registers (TRH and TRL). . . . . . . . . . . . . . . . . . . . . . . .67
Alternate Timer Registers (ATRH and ATRL). . . . . . . . . . . . . .68
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . . . .69
Output Compare Registers (OCRH and OCRL). . . . . . . . . . . .70
MC68HC05C9A — Rev. 5.0
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List of Figures
15
List of Figures
Figure
Title
Page
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Serial Communications Interface Block Diagram . . . . . . . . . . .75
Rate Generator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SCI Examples of Start Bit Sampling Techniques . . . . . . . . . . .80
SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . . . .80
SCI Artificial Start Following a Frame Error . . . . . . . . . . . . . . .81
SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . . . .82
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . .83
9-10 SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . .85
9-11 SCI Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . . . . . .87
9-12 Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . . .89
10-1 Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10-2 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . .95
10-3 Serial Peripheral Interface Master-Slave Interconnection . . . .96
10-4 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . .97
10-5 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10-6 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12-1 Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12-2 Maximum Supply Current versus Internal
Clock Frequency, VDD = 5.5 V. . . . . . . . . . . . . . . . . . . . . .127
12-3 Maximum Supply Current versus Internal
Clock Frequency, VDD = 3.6 V. . . . . . . . . . . . . . . . . . . . . .127
12-4 TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .129
12-5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
12-6 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . .130
12-7 Power-On Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . .131
12-8 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
12-9 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .134
12-10 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13-1 40-Pin Plastic DIP Package (Case 711-03) . . . . . . . . . . . . . .138
13-2 42-Pin Plastic SDIP Package (Case 858-01) . . . . . . . . . . . . .138
13-3 44-Lead PLCC (Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . .139
13-4 44-Lead QFP (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . .140
C-1 Self-Check Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . .157
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16
MC68HC05C9A — Rev. 5.0
List of Figures
MOTOROLA
Advance Information — MC68HC05C9A
List of Tables
Table
Title
Page
4-1
5-1
Vector Addresses for Interrupts and Resets. . . . . . . . . . . . . . .43
COP Timeout Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
9-1
9-2
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . .89
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10-1 SPI Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11-1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .107
11-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .108
11-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .110
11-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .111
11-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
14-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B-1 High-Speed Operating Temperature Range. . . . . . . . . . . . . .148
C-1 Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . . . . .158
D-1 M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . . .160
MC68HC05C9A — Rev. 5.0
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MOTOROLA
List of Tables
17
List of Tables
Advance Information
18
MC68HC05C9A — Rev. 5.0
List of Tables
MOTOROLA
Advance Information — MC68HC05C9A
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
1.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Software-Programmable Options . . . . . . . . . . . . . . . . . . . . . . .22
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.6.7
1.6.8
1.6.9
1.6.10
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TCAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PB0–PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PD0–PD5 and PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.2 Introduction
The MC68HC05C9A HCMOS (high-density complementary metal-oxide
semiconductor) microcontroller is a member of the M68HC05 Family.
The MC68HC05C9A memory map consists of 15,936 bytes of user
ROM and 352 bytes of RAM. The MC68HC05C9A includes a serial
communications interface, a serial peripheral interface, and a 16-bit
capture/compare timer.
MC68HC05C9A — Rev. 5.0
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MOTOROLA
General Description
19
General Description
1.3 Features
Features of the MC68HC05C9A include:
•
•
•
•
•
•
•
M68HC05 CPU
Mask programmable interrupt capability on port B
Software programmable external interrupt sensitivity
15,936 bytes of read-only memory (ROM)
352 bytes of random-access memory (RAM)
Memory mapped input/output (I/O)
31 bidirectional I/O lines with high current sink and source
on PC7
•
•
•
•
Asynchronous serial communications interface (SCI)
Synchronous serial peripheral interface (SPI)
16-Bit capture/compare timer
Computer operating properly (COP) watchdog timer and clock
monitor
•
•
•
•
•
Power-saving wait and stop modes
On-chip crystal oscillator connections
Single 3.0 volts to 5.5 volts power supply requirement
ROM contents security(1) feature
Available packages:
– 40-pin dual in-line (DIP)
– 44-pin plastic leaded chip carrier (PLCC)
– 44-pin quad flat pack (QFP)
– 42-pin plastic shrink dual in-line (SDIP) packages
1.4 Mask Options
Eight mask options are available to select external interrupt capability
(including an internal pullup device) on each of the port B pins.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
Advance Information
20
MC68HC05C9A — Rev. 5.0
General Description
MOTOROLA
General Description
Mask Options
SELF-CHECK ROM — 239 BYTES
USER ROM — 15,936 BYTES
USER RAM — 352 BYTES
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
ARITHMETIC LOGIC
UNIT
CPU CONTROL
ACCUMULATOR
IRQ
M68HC05
MCU
INDEX REGISTER
RESET
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
STACK POINTER
0
0 0 0 0 0 1 1
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N C Z
CPU CLOCK
OSC1
OSC2
DIVIDE
BY TWO
INTERNAL
OSCILLATOR
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
INTERNAL CLOCK
COP
WATCHDOG
DIVIDE
BY FOUR
TIMER CLOCK
BAUD RATE
PD7
GENERATOR
CAPTURE/
SPI
SCI
TCAP
TCMP
PD5/SS
SS
COMPARE
TIMER
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
SCK
MOSI
MISO
TDO
RDI
VDD
VSS
POWER
Figure 1-1. Block Diagram
MC68HC05C9A — Rev. 5.0
Advance Information
21
MOTOROLA
General Description
General Description
1.5 Software-Programmable Options
The option register (OR), shown in Figure 1-2, contains the
programmable bits for these options:
•
Map two different areas of memory between RAM and ROM, one
of 48 bytes and one of 128 bytes
•
Edge-triggered only or edge- and level-triggered external interrupt
(IRQ pin and any port B pin configured for interrupt)
This register must be written to by user software during operation of the
microcontroller.
Address: $3FDF
Bit 7
RAM0
0
6
RAM1
0
5
0
4
0
3
0
2
0
1
IRQ
1
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 1-2. Option Register
RAM0 — Random-Access Memory Control Bit 0
This read/write bit selects between RAM or ROM in location $0020 to
$004F. This bit can be read or written at any time.
1 = RAM selected
0 = ROM selected
RAM1— Random-Access Memory Control Bit 1
This read/write bit selects between RAM or ROM in location $0100 to
$017F. This bit can be read or written at any time.
1 = RAM selected
0 = EPROM selected
IRQ — Interrupt Request Bit
This bit selects between an edge-triggered only or edge- and level-
triggered external interrupt. This bit is set by reset, but can be cleared
by software. This bit can be written only once.
1 = Edge and level interrupt option selected
0 = Edge-only interrupt option selected
Advance Information
22
MC68HC05C9A — Rev. 5.0
General Description
MOTOROLA
General Description
Functional Pin Descriptions
1.6 Functional Pin Descriptions
Figure 1-3, Figure 1-4, Figure 1-5, and Figure 1-6 show the pin
assignments for the available packages. A functional description of the
pins follows.
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
RESET
IRQ
N/C
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
VSS
VDD
2
OSC1
OSC2
TCAP
PD7
3
4
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Figure 1-3. 40-Pin PDIP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 3
should be tied to VDD
.
MC68HC05C9A — Rev. 5.0
Advance Information
23
MOTOROLA
General Description
General Description
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
RESET
IRQ
N/C
1
VDD
2
OSC1
OSC2
TCAP
PD7
3
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
N/C
4
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PC1
PC2
N/C
PB4
PB5
PB6
PB7
VSS
PC3
PC4
PC5
PC6
PC7
Figure 1-4. 42-Pin SDIP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 3
should be tied to VDD
.
Advance Information
24
MC68HC05C9A — Rev. 5.0
General Description
MOTOROLA
General Description
Functional Pin Descriptions
1
7
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
N/C
39
38
37
36
35
34
33
32
31
30
29
8
TCMP
9
PD5/SS
PD4/SCK
PD3/MOSI
PD2MISO
PD1/TDO
PD0/RDI
PC0
10
11
12
13
14
15
16
17
PB3
N/C
PC1
PC2
Figure 1-5. 44-Lead PLCC Pin Assignments
NOTE: The 44-pin PLCC pin assignment diagram is for compatibility with the
MC68HC705C9A. However, if MC68HC705C9A devices are to be used
in the same socket, pin 3 should be tied to VDD
.
For compatibility with MC68HC05C4A/C8A/C12A devices in 44-pin
PLCC, tie pins 17 and 18 together, and tie pins 39 and 40 together.
For compatibility with MC68HC705C8A 44-pin PLCC device, three sets
of pins should be tied together: pins 17 and 18, pins 39 and 40, and
pins 3, 4, and 44.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
General Description
25
General Description
1
TCMP
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
33
32
31
30
29
28
27
26
25
24
23
2
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
3
4
5
6
7
8
9
PC1
10
11
PC2
PC3
Figure 1-6. 44-Pin QFP Pin Assignments
NOTE: If MC68HC705C9A devices are to be used in the same socket, pin 43
should be tied to VDD
.
1.6.1 VDD and VSS
Power is supplied to the MCU using these two pins. VDD is the positive
supply and VSS is ground.
1.6.2 IRQ
This interrupt pin has an option that provides two different choices of
interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt
trigger as part of its input to improve noise immunity. Refer to Section 4.
Interrupts for more detail.
Advance Information
26
MC68HC05C9A — Rev. 5.0
General Description
MOTOROLA
General Description
Functional Pin Descriptions
1.6.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal or ceramic resonator connected to these pins provides a system
clock. The internal frequency is one-half the crystal frequency.
1.6.4 RESET
As an input pin, this active low RESET pin is used to reset the MCU to a
known startup state by pulling RESET low. As an output pin, the RESET
pin indicates that an internal MCU reset has occurred. The RESET pin
contains an internal Schmitt trigger as part of its input to improve noise
immunity. Refer to Section 5. Resets for more detail.
1.6.5 TCAP
This pin controls the input capture feature for the on-chip programmable
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity. Refer to Section 8. Capture/Compare
Timer for more detail.
1.6.6 TCMP
The TCMP pin provides an output for the output compare feature of the
on-chip programmable timer. Refer to Section 8. Capture/Compare
Timer for more detail.
1.6.7 PA0–PA7
These eight I/O lines comprise port A. The state of each pin is software
programmable and all port A pins are configured as inputs during reset.
Refer to Section 7. Input/Output Ports for more detail.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
General Description
27
General Description
1.6.8 PB0–PB7
These eight I/O lines comprise port B. The state of each pin is software
programmable and all port B pins are configured as inputs during reset.
Port B has mask option register enabled pullup devices and interrupt
capability selectable for any pin. Refer to Section 7. Input/Output Ports
for more detail.
1.6.9 PC0–PC7
These eight I/O lines comprise port C. The state of each pin is software
programmable and all port C pins are configured as inputs during reset.
PC7 has high current sink and source capability. Refer to Section 7.
Input/Output Ports for more detail.
1.6.10 PD0–PD5 and PD7
These seven I/O lines comprise port D. The state of each pin is software
programmable and all port D pins are configured as inputs during reset.
Refer to Section 7. Input/Output Ports for more detail.
Advance Information
28
MC68HC05C9A — Rev. 5.0
General Description
MOTOROLA
Advance Information — MC68HC05C9A
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
2.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.2 Introduction
The microcontroller unit (MCU) has a 16-Kbyte memory map. The
memory map consists of:
•
•
•
•
•
Input/output (I/O), control, and status registers
User random-access memory (RAM)
User read-only memory (ROM)
Self-check ROM
Reset and interrupt vectors
See Figure 2-1 and Figure 2-2.
Two control bits in the option register ($3FDF) allow the user to switch
between RAM and ROM at any time in two special areas of the memory
map, $0020–$004F (48 bytes) and $0100–$017F (128 bytes).
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Memory
29
Memory
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
PORT A DATA REGISTER
PORT B DATA REGISTER
I/O REGISTERS
32 BYTES
PORT C DATA REGISTER
PORT D DATA REGISTER
$001F
$0020
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PORT D DATA DIRECTION REGISTER
UNUSED
USER ROM
48 BYTES
RAM0 = 0
RAM
48 BYTES
RAM0 = 1
$004F
$0050
UNUSED
RAM
176 BYTES
SPI CONTROL REGISTER
SPI STATUS REGISTER
$00BF
$00C0
SPI DATA REGISTER
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
STACK
64 BYTES
$00FF
$0100
USER ROM
128 BYTES
RAM
128 BYTES
SCI DATA REGISTER
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
RAM1 = 0
RAM1 = 1
$017F
$0180
USER ROM
15,744 BYTES
COP RESET REGISTER
COP CONTROL REGISTER
UNUSED
$3EFF
$3F00
$3FF0
UNUSED (4 BYTES)
$3FF3
$3FF4
$3FF5
$3FF6
$3FF7
$3FF8
$3FF9
$3FFA
$3FFB
$3FFC
$3FFD
$3FFE
$3FFF
SELF-CHECK
ROM
AND VECTORS
239 BYTES
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SCI VECTOR (HIGH)
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
$3FDF
$3FEF
$3FF0
OPTION REGISTER
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
USER ROM VECTORS
16 BYTES
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$3FFF
Figure 2-1. Memory Map
Advance Information
30
MC68HC05C9A — Rev. 5.0
Memory
MOTOROLA
Memory
RAM
2.3 RAM
The main user RAM consists of 176 bytes at $0050–$00FF. This RAM
area is always present in the memory map and includes a 64-byte stack
area. The stack pointer can access 64 bytes of RAM in the range $00FF
down to $00C0.
NOTE: Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
Two additional RAM areas are available at $0020–$004F (48 bytes) and
$0100–$017F (128 bytes) (see Figure 2-1 and Figure 2-2.) These may
be accessed at any time by setting the RAM0 and RAM1 bits,
respectively, in the option register.
Refer to 1.5 Software-Programmable Options for additional
information.
2.4 ROM
The user ROM consists of 48 bytes of page zero ROM from $0020 to
$004F, 15,872 bytes of ROM from $0100 to $3EFF, and 16 bytes of user
vectors from $3FF0 to $3FFF.
2.5 ROM Security
2.6 I/O Registers
A security feature has been incorporated into the MC68HC05C9A to
help prevent external access to the contents of the ROM in any mode of
operation.
Except for the option register, all I/O, control and status registers are
located within one 32-byte block in page zero of the address space
($0000–$001F). A summary of these registers is shown in Figure 2-2.
More detail about the contents of these registers is given in Figure 2-3.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Memory
31
Memory
Address
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Register Name
Port A Data Register
Port B Data Register
Port C Data Register
Port D Data Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Port D Data Direction Register
Unused
Unused
Serial Peripheral Control Register
Serial Peripheral Status Register
Serial Peripheral Data Register
Baud Rate Register
Serial Communications Control Register 1
Serial Communications Control Register 2
Serial Communications Status Register
Serial Communications Data Register
Timer Control Register
Timer Status Register
Input Capture Register High
Input Capture Register Low
Output Compare Register High
Output Compare Register Low
Timer Register High
Timer Register Low
Alternate Timer Register High
Alternate Timer Register Low
Unused
COP Reset Register
COP Control Register
Reserved
Figure 2-2. I/O Register Summary
Advance Information
32
MC68HC05C9A — Rev. 5.0
MOTOROLA
Memory
Memory
I/O Registers
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PB1
PC1
PD1
PA0
$0000
(PORTA) Write:
See page 57.
Reset:
Unaffected by reset
Read:
Port B Data Register
(PORTB) Write:
See page 58.
PB7
PC7
PD7
PB6
PC6
PB5
PC5
PD5
PB4
PB3
PB2
PC2
PD2
PB0
PC0
PD0
$0001
$0002
$0003
$0004
$0005
$0006
Reset:
Unaffected by reset
Read:
Port C Data Register
(PORTC) Write:
See page 59.
PC4
PC3
Reset:
Unaffected by reset
Read:
Port D Data Register
(PORTD) Write:
See page 59.
PD4
PD3
Reset:
Unaffected by reset
Read:
Port A Data Direction Register
(DDRA) Write:
See page 57.
DDRA7 DDRA6 DDRA5 DDRA4
DDRA3
DDRA2 DDRA1 DDRA0
Reset:
0
0
0
0
0
0
0
0
Read:
Port B Data Direction Register
(DDRB) Write:
See page 58.
DDRB7 DDRB6 DDRB5 DDRB4
DDRB3
DDRB2 DDRB1 DDRB0
Reset:
0
0
0
0
0
DDRC3
0
0
0
0
Read:
Port C Data Direction Register
(DDRC) Write:
See page 59.
DDRC7 DDRC6 DDRC5 DDRC4
DDRC2 DDRC1 DDRC0
Reset:
0
DDRC7
0
0
0
0
0
0
0
Read:
Port D Data Direction Register
(DDRD) Write:
See page 59.
DDRC5 DDRC4
DDRC3
0
DDRC2 DDRC1 DDRC0
$0007
$0008
Reset:
0
0
0
0
0
0
Unimplemented
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 1 of 4)
MC68HC05C9A — Rev. 5.0
Advance Information
33
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0009
Unimplemented
Read:
SPI Control Register
SPIE
0
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
(SPCR) Write:
See page 97.
Reset:
0
0
0
0
0
0
1
0
U
0
U
0
Read: SPIF
WCOL
MODF
SPI Status Register
(SPSR) Write:
See page 99.
Reset:
Read:
0
0
0
0
0
0
0
0
SPI Data Register
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
(SPDR) Write:
See page 101.
Reset:
Unaffected by reset
SCP0
Read:
SCI Baud Rate Register
BAUD Write:
See page 89.
SCP1
SCR2
SCR1
SCR0
Reset:
—
R8
U
—
T8
0
0
M
—
WAKE
U
U
U
U
Read:
SCI Control Register 1
(SCCR1) Write:
See page 83.
Reset:
U
0
U
0
0
0
SBK
0
Read:
SCI Control Register 2
(SCCR2) Write:
See page 85.
TIE
0
TCIE
RIE
ILIE
TE
RE
RMW
Reset:
0
0
0
0
0
0
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
SCI Status Register
(SCSR) Write:
See page 87.
Reset:
Read:
1
1
0
0
0
0
0
—
SCI Data Register
SCD7
SDC6
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
(SCDR) Write:
See page 83.
Reset:
Unaffected by reset
= Reserved
= Unimplemented
R
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 2 of 4)
Advance Information
34
MC68HC05C9A — Rev. 5.0
Memory
MOTOROLA
Memory
I/O Registers
Addr.
Register Name
Bit 7
ICIE
0
6
5
4
3
2
1
Bit 0
Read:
0
0
0
Timer Control Register
OCIE
TOIE
IEDG
OLVL
$0012
(TCR) Write:
See page 64.
Reset:
0
0
0
0
0
0
0
0
U
0
0
0
Read: ICF
OCF
TOF
Timer Status Register
(TSR) Write:
See page 66.
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
Reset:
U
U
U
0
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register High
(ICRH) Write:
See page 69.
Reset:
Unaffected by reset
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Input Capture Register Low
(ICRL) Write:
See page 69.
Reset:
Unaffected by reset
Read:
Bit 15
Output Compare Register
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
High (OCRH) Write:
See page 70.
Reset:
Unaffected by reset
Read:
Bit 7
Output Compare Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Low (OCRL) Write:
See page 70.
Reset:
Unaffected by reset
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Timer Register High
(TRH) Write:
See page 67.
Reset:
1
1
1
1
1
1
1
1
Read: Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer Register Low
(TRL)
See page 67.
Reset:
1
1
1
1
1
1
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Alternate Timer Register High
(ATRH) Write:
See page 68.
Reset:
1
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 3 of 4)
MC68HC05C9A — Rev. 5.0
Advance Information
35
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Alternate Timer Register Low
$001B
$001C
(ATRL) Write:
See page 68.
Reset:
1
1
1
1
1
1
0
0
Unimplemented
Read:
COP Reset Register
$001D
(COPRST) Write: Bit 7
See page 51.
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reset:
0
0
0
0
0
Read:
0
COP Control Register
(COPCR) Write:
See page 52.
COPF
U
CME
0
COPE
0
CM1
0
CM0
0
$001E
$001D
$001E
$001F
Reset:
0
0
0
Unimplemented
Unimplemented
Reserved
R
R
R
R
R
R
R
R
R
= Unimplemented
= Reserved
U = Unaffected
Figure 2-3. Input/Output Registers (Sheet 4 of 4)
Advance Information
36
MC68HC05C9A — Rev. 5.0
Memory
MOTOROLA
Advance Information — MC68HC05C9A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . .40
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.2 Introduction
This section contains information describing the basic programmer’s
model and the registers contained in the central processor unit (CPU).
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Central Processor Unit (CPU)
37
Central Processor Unit (CPU)
3.3 CPU Registers
The microcontroller unit (MCU) contains five registers as shown in the
programming model of Figure 3-1. The interrupt stacking order is shown
in Figure 3-2.
7
7
0
A
X
ACCUMULATOR
0
0
0
INDEX REGISTER
13
13
PC
1
PROGRAM COUNTER
STACK POINTER
7
0
0
0
0
0
0
1
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
0
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
STACK
1
1
1
I
N
T
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
E
R
R
U
P
T
DECREASING
MEMORY
ADDRESSES
PCL
UNSTACK
Figure 3-2. Interrupt Stacking Order
Advance Information
38
MC68HC05C9A — Rev. 5.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
3.3.2 Index Register (X)
The index register is an 8-bit register used for the indexed addressing
value to create an effective address. The index register may also be
used as a temporary storage area.
3.3.3 Program Counter (PC)
The program counter is a 14-bit register that contains the address of the
next byte to be fetched.
3.3.4 Stack Pointer (SP)
The stack pointer contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $0FF. The stack pointer is then
decremented as data is pushed onto the stack and incremented as data
is pulled from the stack.
When accessing memory, the eight most significant bits are permanently
set to 00000011. These eight bits are appended to the six least
significant register bits to produce an address within the range of $00FF
to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Central Processor Unit (CPU)
39
Central Processor Unit (CPU)
3.3.5 Condition Code Register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the
results of the instruction just executed, and the fifth bit indicates whether
interrupts are masked. These bits can be individually tested by a
program, and specific actions can be taken as a result of their state.
Each bit is explained here.
Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer, serial communications interface (SCI),
serial peripheral interface (SPI), and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was 0.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions and during
shifts and rotates.
Advance Information
40
MC68HC05C9A — Rev. 5.0
Central Processor Unit (CPU)
MOTOROLA
Advance Information — MC68HC05C9A
Section 4. Interrupts
4.1 Contents
4.2
4.3
4.4
4.5
4.6
4.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Non-Maskable Software Interrupt (SWI). . . . . . . . . . . . . . . . . .42
External Interrupt (IRQ or Port B). . . . . . . . . . . . . . . . . . . . . . .42
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
SCI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Introduction
The MC68HC05C9A microcontroller unit (MCU) can be interrupted by
five different sources: four maskable hardware interrupts, and one non-
maskable software interrupt:
•
•
•
•
•
External signal on the IRQ pin or port B pins
16-bit programmable timer
Serial communications interface (SCI)
Serial peripheral interface (SPI)
Software interrupt instruction (SWI)
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
return from interrupt (RTI) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Interrupts
41
Interrupts
Unlike RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
NOTE: The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at
the end of an instruction execution, the external interrupt is serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources.
Figure 4-1 shows the interrupt processing flow.
4.3 Non-Maskable Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is
executed regardless of the state of the I bit in the CCR. If the I bit is 0
(interrupts enabled), SWI executes after interrupts which were pending
when the SWI was fetched, but before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
4.4 External Interrupt (IRQ or Port B)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $3FFA and $3FFB.
Advance Information
42
MC68HC05C9A — Rev. 5.0
Interrupts
MOTOROLA
Interrupts
External Interrupt (IRQ or Port B)
Table 4-1. Vector Addresses for Interrupts and Resets
Priority
(1 = Highest)
Vector
Address
Function
Source
Local Mask Global Mask
Power-on reset
RESET pin
Reset
None
None
1
$3FFE–$3FFF
COP watchdog
Same priority
as instruction
Software interrupt (SWI)
External interrupt
User code
None
None
None
I bit
$3FFC–$3FFD
$3FFA–$3FFB
IRQ pin
Port B pins
ICF bit
2
ICIE bit
OCIE bit
TOIE bit
Timer interrupts
OCF bit
TOF bit
I bit
3
$3FF8–$3FF9
TDRE bit
TC bit
TCIE bit
SCI interrupts
SPI interrupts
RDRF bit
OR bit
I bit
I bit
4
5
$3FF6–$3FF7
$3FF4–$3FF5
RIE bit
ILIE bit
SPIE bit
IDLE bit
SPIF bit
MODF bit
When any of the port B pullups are enabled, each pin becomes an
additional external interrupt source which is executed identically to the
IRQ pin. Port B interrupts follow the same edge/edge-level selection as
the IRQ pin. The branch instructions BIL and BIH also respond to the
port B interrupts in the same way as the IRQ pin. See 7.4 Port B.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger operation is selectable. The sensitivity is software-controlled
by the IRQ bit in the option register ($3FDF).
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse can be latched
and serviced as soon as the I bit is cleared.
MC68HC05C9A — Rev. 5.0
MOTOROLA
Advance Information
43
Interrupts
Interrupts
4.5 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $3FF8 and $3FF9.
4.6 SCI Interrupt
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF6 and $3FF7.
4.7 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$3FF4 and $3FF5.
Advance Information
44
MC68HC05C9A — Rev. 5.0
Interrupts
MOTOROLA
Interrupts
SPI Interrupt
FROM RESET
I BIT
IN CCR
SET?
Y
N
IRQ OR PORT B
EXTERNAL
INTERRUPT
Y
Y
Y
Y
CLEAR IRQ
REQUEST LATCH
N
INTERNAL
TIMER
INTERRUPT
N
INTERNAL
SCI
INTERRUPT
N
INTERNAL
SPI
INTERRUPT
N
STACK
PC, X, A, CCR
FETCH NEXT
INSTRUCTION
SET I BIT IN
CC REGISTER
LOAD PC FROM:
SWI
INSTRUCTION
?
Y
SWI: $3FFC–$3FFD
IRQ: $3FFA–$3FFB
TIMER: $3FF8–$3FF9
SCI: $3FF6–$3FF7
SPI: $3FF4–$3FF5
N
RTI
INSTRUCTION
?
Y
N
EXECUTE
INSTRUCTION
RESTORE REGISTERS
FROM STACK:
CCR, A, X, PC
Figure 4-1. Interrupt Flowchart
MC68HC05C9A — Rev. 5.0
Advance Information
45
MOTOROLA
Interrupts
Interrupts
Advance Information
46
MC68HC05C9A — Rev. 5.0
Interrupts
MOTOROLA
Advance Information — MC68HC05C9A
Section 5. Resets
5.1 Contents
5.2
5.3
5.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.5
5.5.1
5.5.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .50
COP Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5.6
5.7
5.8
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.2 Introduction
The MC68HC05C9A microcontroller unit (MCU) can be reset four ways:
•
•
•
•
Initial power-on reset function
Active low input to the RESET pin
Computer operating properly (COP)
Clock monitor
MC68HC05C9A — Rev. 5.0
Advance Information
47
MOTOROLA
Resets
Resets
A reset immediately stops the operation of the instruction being
executed, initializes some control bits, and loads the program counter
with a user-defined reset vector address. Figure 5-1 is a block diagram
of the reset sources.
CLOCK MONITOR
COP WATCHDOG
VDD
POWER-ON RESET
STOP
R
RST
TO CPU AND
SUBSYSTEMS
RESET
D
Q
RESET
LATCH
INTERNAL CLOCK
Figure 5-1. Reset Sources
5.3 Power-On Reset (POR)
A power-on reset (POR) occurs when a positive transition is detected on
DD. The power-on reset is strictly for power turn-on conditions and
V
should not be used to detect a drop in the power supply voltage. There
is a 4064 internal processor clock cycle (tCYC) oscillator stabilization
delay after the oscillator becomes active. The RESET pin will output a
logic 0 during the 4064-cycle delay. If the RESET pin is low after the end
of this 4064-cycle delay, the MCU will remain in the reset condition until
RESET is driven high externally.
Advance Information
48
MC68HC05C9A — Rev. 5.0
Resets
MOTOROLA
Resets
RESET Pin
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL). However, to
differentiate between an external reset and an internal reset (generated
from the COP or clock monitor), any externally driven reset must be
active (logic 0) for at least eight tcyc
.
t
VDDR
V
DD
(2)
OSC1
4064
t
CYC
t
CYC
INTERNAL
(1)
CLOCK
INTERNAL
ADDRESS
(1)
NEW
PC
NEW
PC
NEW
PC
NEW
PC
BUS
$3FFE
$3FFF
$3FFE $3FFE
$3FFE
$3FFE
PCH
$3FFF
PCL
INTERNAL
DATA
(1)
NEW
PCH
NEW
PCL
OP
OP
DUMMY
DUMMY
BUS
CODE
CODE
t
RL
NOTE 4
RESET
NOTE 3
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is meant to represent only time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. RESET outputs VOL during 4064 power-on reset cycles.
Figure 5-2. Power-On Reset and RESET
MC68HC05C9A — Rev. 5.0
Advance Information
49
MOTOROLA
Resets
Resets
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against
program run-away failures. A timeout of the COP timer generates a COP
reset. The COP watchdog is a software error detection system that
automatically times out and resets the MCU if not cleared periodically by
a program sequence.
The COP is controlled with two registers, one to reset the COP timer and
the other to enable and control COP and clock monitor functions.
Figure 5-3 shows a block diagram of the COP.
CM1
CM0
INTERNAL
CPU
CLOCK
÷4
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
215
217
219
221
16-BIT TIMER SYSTEM
213
COP
÷4
÷2
÷2
÷2
÷2
÷2
÷2
COPRST
Figure 5-3. COP Block Diagram
Advance Information
50
MC68HC05C9A — Rev. 5.0
Resets
MOTOROLA
Resets
Computer Operating Properly (COP) Reset
5.5.1 COP Reset Register
The COP reset register (COPRST), shown in Figure 5-4, is a write-only
register used to reset the COP.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
= Unimplemented
Figure 5-4. COP Reset Register (COPRST)
The sequence required to reset the COP timer is:
•
•
Write $55 to the COP reset register
Write $AA to the COP reset register
Both write operations must occur in the order listed, but any number of
instructions may be executed between the two write operations provided
that the COP does not time out between the two writes. The elapsed time
between software resets must not be greater than the COP timeout
period. If the COP should time out, a system reset will occur and the
device will be re-initialized in the same fashion as a power-on reset or
reset.
Reading this register does not return valid data.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Resets
51
Resets
5.5.2 COP Control Register
The COP control register (COPCR), shown in Figure 5-5, performs
these functions:
•
•
•
Enables clock monitor function
Enables COP function
Selects timeout duration of COP timer
And flags these conditions:
•
•
COP timeout
Clock monitor reset
Address: $001E
Bit 7
6
0
5
0
4
COPF
U
3
CME
0
2
COPE
0
1
CM1
0
Bit 0
CM0
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
U = Undetermined
Figure 5-5. COP Control Register (COPCR)
COPF — Computer Operating Properly Flag
Reading the COP control register clears COPF.
1 = COP or clock monitor reset has occurred.
0 = No COP or clock monitor reset has occurred.
CME — Clock Monitor Enable Bit
This bit is readable any time, but may be written only once.
1 = Clock monitor enabled
0 = Clock monitor disabled
Advance Information
52
MC68HC05C9A — Rev. 5.0
Resets
MOTOROLA
Resets
Computer Operating Properly (COP) Reset
COPE — COP Enable Bit
This bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
Bits 7–5 — Not Used
These bits always read as 0.
Table 5-1. COP Timeout Period
Timeout Period
(f = 2.0 MHz)
Timeout Period
(f = 4.0 MHz)
15
CM1
CM0
f
/2 Divide By
OP
OSC
OSC
0
0
1
1
0
1
0
1
1
4
32.77 ms
131.07 ms
524.29 ms
2.097 s
16.38 ms
65.54 ms
262.14 ms
1.048 s
16
64
MC68HC05C9A — Rev. 5.0
Advance Information
53
MOTOROLA
Resets
Resets
5.6 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software must pull the device out of wait mode periodically and reset the
COP to prevent a system reset.
5.7 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an IRQ is used to
exit stop mode, the COP counter will not be reset after the 4064-cycle
delay and will have that many cycles already counted when control is
returned to the program.
In the event that an inadvertent STOP instruction is executed, the COP
will not provide a reset. The clock monitor function provides protection
for this situation.
5.8 Clock Monitor Reset
The clock monitor circuit can provide a system reset if the clock stops for
any reason, including stop mode. When the CME bit in the COP control
register is set, the clock monitor detects the absence of the internal bus
clock for a certain period of time. The timeout period is dependent on the
processing parameters and varies from 5 µs to 100 µs, which implies
that systems using a bus clock rate of 200 kHz or less should not use the
clock monitor.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system via the bidirectional
RESET pin for four bus cycles if the clock is slow or until the clocks
recover in the case where the clocks are absent.
Advance Information
54
MC68HC05C9A — Rev. 5.0
Resets
MOTOROLA
Advance Information — MC68HC05C9A
Section 6. Low-Power Modes
6.1 Contents
6.2
6.3
6.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.2 Introduction
6.3 Stop Mode
This section describes the low-power stop and wait modes.
The STOP instruction places the microcontroller unit (MCU) in its lowest-
power consumption mode. In stop mode, the internal oscillator is turned
off, halting all internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer
interrupt request and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or reset. See Figure 6-1.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Low-Power Modes
55
Low-Power Modes
(1)
OSC1
t
RL
RESET
t
LIH
(2)
IRQ
t
4064 t
ILCH
CYC
(3)
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
Notes:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option
RESET OR INTERRUPT
VECTOR FETCH
3. IRQ pin level and edge-sensitive mask option
Figure 6-1. Stop Recovery Timing Diagram
6.4 Wait Mode
The WAIT instruction places the MCU in a low-power consumption
mode, but wait mode consumes more power than stop mode. All central
processor unit (CPU) action is suspended, but the timer, serial
communications interface (SCI), serial peripheral interface (SPI), and
the oscillator remain active. Any interrupt or reset will cause the MCU to
exit wait mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and I/O lines remain in their previous state. The
timer, SCI, and SPI may be enabled to allow a periodic exit from the wait
mode.
Advance Information
56
MC68HC05C9A — Rev. 5.0
Low-Power Modes
MOTOROLA
Advance Information — MC68HC05C9A
Section 7. Input/Output Ports
7.1 Contents
7.2
7.3
7.4
7.5
7.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.2 Introduction
This section briefly describes the 31 input/output (I/O) lines arranged as
one 7-bit and three 8-bit ports. All of these port pins are programmable
as either inputs or outputs under software control of the data direction
registers.
NOTE: To avoid a glitch on the output pins, write data to the I/O port data
register before writing a 1 to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. The contents of the port A data
register are indeterminate at initial power-up and must be initialized by
user software. Reset does not affect the data registers, but clears the
data direction registers, thereby returning the ports to inputs. Writing a 1
to a DDR bit sets the corresponding port bit to output mode. A block
diagram of the port logic is shown in Figure 7-1.
MC68HC05C9A — Rev. 5.0
Advance Information
57
MOTOROLA
Input/Output Ports
Input/Output Ports
DATA DIRECTION
REGISTER BIT
INTERNAL
HC05
I/O
LATCHED OUTPUT
DATA BIT
OUTPUT
PIN
CONNECTIONS
INPUT
REG.
BIT
INPUT
I/O
Figure 7-1. Port A I/O Circuit
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. The contents of the
port B data register are indeterminate at initial powerup and must be
initialized by user software. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs.
Writing a one to a DDR bit sets the corresponding port pin to output
mode. Each of the port B pins has an optional external interrupt
capability that can be enabled by mask option.
The interrupt option also enables a pullup device when the pin is
configured as an input. The edge or edge- and level-sensitivity of the
IRQ pin will also pertain to the enabled port B pins. Care needs to be
taken when using port B pins that have the pullup enabled. Before
switching from an output to an input, the data should be preconditioned
to a 1 to prevent an interrupt from occurring. The port B logic is shown in
Figure 7-2.
Advance Information
58
MC68HC05C9A — Rev. 5.0
Input/Output Ports
MOTOROLA
Input/Output Ports
Port C
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. The contents of the
port C data register are indeterminate at initial powerup and must be
initialized by user software. Reset does not affect the data registers, but
clears the data direction registers, thereby returning the ports to inputs.
Writing a 1 to a DDR bit sets the corresponding port bit to output mode.
PC7 has a high current sink and source capability. Figure 7-1 is also
applicable to port C.
7.6 Port D
Port D is a 7-bit bidirectional port. Four of its pins are shared with the SPI
subsystem and two more are shared with the SCI subsystem. The port
D data register is at $0003 and the data direction register is at $0007.
The contents of the port D data register are indeterminate at initial
powerup and must be initialized by user software. During reset all seven
bits become valid input ports because the DDR bits are cleared and the
special function output drivers associated with the SCI and SPI
subsystems are disabled, thereby returning the ports to inputs. Writing
a 1 to a DDR bit sets the corresponding port bit to output mode.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Input/Output Ports
59
Input/Output Ports
VDD
VDD
DISABLED
ENABLED
PORT B EXTERNAL INTERRUPT
MASK OPTION
READ $0005
WRITE $0005
RESET
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
READ $0001
PBX
EDGE ONLY
SOFTWARE CONTROLLED OPTION
EDGE AND LEVEL
VDD
D
C
Q
Q
EXTERNAL
INTERRUPT
REQUEST
FROM OTHER
PORT B PINS
R
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-2. Port B I/O Logic
Advance Information
60
MC68HC05C9A — Rev. 5.0
Input/Output Ports
MOTOROLA
Advance Information — MC68HC05C9A
Section 8. Capture/Compare Timer
8.1 Content
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.3
8.3.1
8.3.2
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.4
Timer I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Timer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . .68
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . .70
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.2 Introduction
This section describes the operation of the 16-bit capture/compare timer.
Figure 8-1 shows the structure of the capture/compare subsystem.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Capture/Compare Timer
61
Capture/Compare Timer
INTERNAL BUS
INTERNAL
PROCESSOR
CLOCK
HIGH LOW
BYTE BYTE
8-BIT
BUFFER
÷4
HIGH LOW
BYTE BYTE
OUTPUT
COMPARE
REGISTER
HIGH
BYTE
$16
$17
LOW
BYTE
INPUT
CAPTURE
REGISTER
16-BIT FREE
RUNNING
COUNTER
$14
$15
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
EDGE
DETECT
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
D
CLK
Q
OUTPUT
LEVEL
REG.
TIMER
STATUS
REG.
$13
ICF OCF TOF
C
RESET
TIMER
CONTROL
REG.
$12
ICIE OCIE TOIE IEDG OLVL
OUTPUT EDGE
LEVEL INPUT
(TCMP) (TCAP)
INTERRUPT CIRCUIT
Figure 8-1. Capture/Compare Timer Block Diagram
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the input/output (I/O) registers
for the input capture and output compare functions are pairs of 8-bit
registers.
Advance Information
62
MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer Operation
Because the counter is 16 bits long and preceded by a fixed divide-by-4
prescaler, the counter rolls over every 262,144 internal clock cycles.
Timer resolution with a 4-MHz crystal is 2 µs.
8.3.1 Input Capture
The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the TCAP pin, it latches the contents of the timer registers into
the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the TCAP
pin. Latching values into the input capture registers at successive edges
of opposite polarity measures the pulse width of the signal.
8.3.2 Output Compare
The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.
The programmer can use the output compare register to measure time
periods, to generate timing delays, or to generate a pulse of specific
duration or a pulse train of specific frequency and duty cycle on the
TCMP pin.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Capture/Compare Timer
63
Capture/Compare Timer
8.4 Timer I/O Registers
These I/O registers control and monitor timer operation:
•
•
•
•
•
•
Timer control register (TCR)
Timer status register (TSR)
Timer registers (TRH and TRL)
Alternate timer registers (ATRH and ATRL)
Input capture registers (ICRH and ICRL)
Output compare registers (OCRH and OCRL)
8.4.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these
functions:
•
•
•
•
•
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Address: $0012
Bit 7
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
U
Bit 0
OLVL
0
Read:
ICIE
Write:
Reset:
0
0
0
0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
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MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or logic 0
appears on the TCMP pin when a successful output compare occurs.
Reset clears the OLVL bit.
1 = TCMP goes high on output compare.
0 = TCMP goes low on output compare.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Capture/Compare Timer
65
Capture/Compare Timer
8.4.2 Timer Status Register
The timer status register (TSR), shown in Figure 8-3, contains flags to
signal these conditions:
•
•
•
An active signal on the TCAP pin, transferring the contents of the
timer registers to the input capture registers
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
A timer roll over from $FFFF to $0000
Address: $0013
Bit 7
6
5
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ICF
OCF
TOF
U
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity
occurs on the TCAP pin. Clear the ICF bit by reading the timer status
register with ICF set and then reading the low byte ($0015) of the
input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set and then reading
the low byte ($0017) of the output compare registers. Resets have no
effect on OCF.
TOF — Timer Overflow Flag
The TOF bit is set automatically when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
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MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
8.4.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contain the
current high and low bytes of the 16-bit counter. Reading TRH before
reading TRL causes TRL to be latched until TRL is read. Reading TRL
after reading the timer status register clears the timer overflow flag
(TOF). Writing to the timer registers has no effect.
Address: $0018 — TRH
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
1
1
1
1
1
1
1
1
$0019 — TRL
Address:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
MC68HC05C9A — Rev. 5.0
Advance Information
67
MOTOROLA
Capture/Compare Timer
Capture/Compare Timer
8.4.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5,
contain the current high and low bytes of the 16-bit counter. Reading
ATRH before reading ATRL causes ATRL to be latched until ATRL is
read. Reading ATRL has no effect on the timer overflow flag (TOF).
Writing to the alternate timer registers has no effect.
Address: $001A — ATRH
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
1
1
1
1
1
1
1
1
$001B — ATRL
Address:
Bit 7
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE: To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.
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MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer I/O Registers
8.4.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.
Address: $0014 — ICRH
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unaffected by reset
Address: $0015 — ICRL
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE: To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.
MC68HC05C9A — Rev. 5.0
MOTOROLA
Advance Information
69
Capture/Compare Timer
Capture/Compare Timer
8.4.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
Address: $0016 — OCRH
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Write:
Read:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unaffected by reset
$0017 — OCRL
Address:
Bit 7
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Write:
Read:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the CCR.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the CCR.
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MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Capture/Compare Timer
Timer During Wait Mode
8.5 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, but the
timer remains active. If interrupts are enabled, a timer interrupt will cause
the processor to exit wait mode.
8.6 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if
STOP is exited by an interrupt. If STOP is exited by reset, the counters
are forced to $FFFC. During STOP, if at least one valid input capture
edge occurs at the TCAP pins, the input capture detect circuit is armed.
This does not set any timer flags or wake up the microcontroller unit
(MCU). But if an interrupt is used to exit stop mode, there is an active
input capture flag and data from the first valid edge that occurred during
the stop mode. If reset is used to exit stop mode, then no input capture
flag or data remains, even if a valid input capture edge occurred.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Capture/Compare Timer
71
Capture/Compare Timer
Advance Information
72
MC68HC05C9A — Rev. 5.0
Capture/Compare Timer
MOTOROLA
Advance Information — MC68HC05C9A
Section 9. Serial Communications Interface (SCI)
9.1 Content
9.2
9.3
9.4
9.5
9.6
9.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SCI Receiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Transmitter Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.8
9.8.1
9.8.2
Receiver Wakeup Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .78
Idle Line Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Address Mark Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.9
Receive Data In (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.10 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.11 Transmit Data Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.12 SCI I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
SCI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
MC68HC05C9A — Rev. 5.0
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MOTOROLA
Serial Communications Interface (SCI)
73
Serial Communications Interface (SCI)
9.2 Introduction
This section describes the on-chip asynchronous serial communications
interface (SCI). The SCI allows full-duplex, asynchronous, RS232 or
RS422 serial communication between the microcontroller unit (MCU)
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator.
9.3 Features
Features of the SCI include:
•
•
•
•
•
•
Standard mark/space non-return-to-zero format
Full-duplex operation
32 programmable baud rates
Programmable 8-bit or 9-bit character length
Separately enabled transmitter and receiver
Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
•
Interrupt-driven operation capability with five interrupt flags:
– Transmitter data register empty
– Transmission complete
– Transmission data register full
– Receiver overrun
– Idle receiver input
•
•
Receiver framing error detection
1/16 bit-time noise detection
Advance Information
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MC68HC05C9A — Rev. 5.0
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Features
INTERNAL BUS
SCI INTERRUPT
+
TRANSMIT
DATA
REGISTER
RECEIVE
$0011
DATA
$0011
REGISTER
$000F
SCCR2
&
&
&
&
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
7
6
5
4
3
2
1
0
TRANSMIT
DATA SHIFT
REGISTER
RECEIVE
DATA SHIFT
REGISTER
TDO
PIN
RDI
PIN
+
5
SCSR
$0010
1
7
6
4
3
2
TRDE
TC
RDRF IDLE
OR
NF
FE
WAKEUP
UNIT
7
TE
SBK
FLAG
CONTROL
TRANSMITTER
CONTROL
RECEIVER
CONTROL
RECEIVER
CLOCK
7
R8
6
T8
5
4
M
3
WAKE
2
1
0
SCCR1
$000E
Figure 9-1. Serial Communications Interface Block Diagram
NOTE: The serial communications data register (SCI SCDR) is controlled by the
internal R/W signal. It is the transmit data register when written to and
the receive data register when read.
MC68HC05C9A — Rev. 5.0
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75
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
9.4 SCI Receiver Features
Features of the SCI receiver include:
•
•
•
•
•
•
Receiver wakeup function (idle line or address bit)
Idle line detection
Framing error detection
Noise detection
Overrun detection
Receiver data register full flag
9.5 SCI Transmitter Features
Features of the SCI transmitter include:
•
•
•
Transmit data register empty flag
Transmit complete flag
Send break
9.6 Functional Description
A block diagram of the SCI is shown in Figure 9-1. Option bits in serial
control register1 (SCCR1) select the wakeup method (WAKE bit) and
data word length (M bit) of the SCI. SCCR2 provides control bits that
individually enable the transmitter and receiver, enable system
interrupts, and provide the wakeup enable bit (RWU) and the send break
code bit (SBK). Control bits in the baud rate register (BAUD) allow the
user to select one of 32 different baud rates for the transmitter and
receiver.
Data transmission is initiated by writing to the serial communications
data register (SCDR). Provided the transmitter is enabled, data stored in
the SCDR is transferred to the transmit data shift register. This transfer
of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter
interrupts are enabled). The transfer of data to the transmit data shift
Advance Information
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MC68HC05C9A — Rev. 5.0
Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
Functional Description
register is synchronized with the bit rate clock (see Figure 9-2). All data
is transmitted least significant bit first. Upon completion of data
transmission, the transmission complete flag (TC) in the SCSR is set
(provided no pending data, preamble, or break is to be sent) and an
interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble, or break (in the
transmit data shift register) has been sent, the TC bit will be set also.
This will also generate an interrupt if the transmission complete interrupt
enable bit (TCIE) is set. If the transmitter is disabled during a
transmission, the character being transmitted will be completed before
the transmitter gives up control of the TDO pin.
When SCDR is read, it contains the last data byte received, provided that
the receiver is enabled. The receive data register full flag bit (RDRF) in
the SCSR is set to indicate that a data byte has been transferred from
the input serial shift register to the SCDR; this will cause an interrupt if
the receiver interrupt is enabled. The data transfer from the input serial
shift register to the SCDR is synchronized by the receiver bit rate clock.
The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR
may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and
the IDLE bit (which detects idle line transmission) in SCSR is set. This
allows a receiver that is not in the wakeup mode to detect the end of a
message, or the preamble of a new message, or to re-synchronize with
the transmitter. A valid character must be received before the idle line
condition or the IDLE bit will not be set and idle line interrupt will not be
generated.
SCP0–SCP1
SCR0–SCR2
SCI TRANS
CLOCK (TX)
SCI PRESCALER
SELECT
CONTROL
SCI RATE
SELECT
CONTROL
OSC FREQ
(fOSC
SCI RECEIVE
CLOCK (RT)
BUS FREQ
(fOP
÷ 16
÷ 2
)
)
N
M
Figure 9-2. Rate Generator Division
MC68HC05C9A — Rev. 5.0
Advance Information
77
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
9.7 Data Format
Receive data or transmit data is the serial data that is transferred to the
internal data bus from the receive data input pin (RDI) or from the
internal bus to the transmit data output pin (TDO). The non-return-to-
zero (NRZ) data format shown in Figure 9-3 is used and must meet
these criteria:
•
The idle line is brought to a logic 1 state prior to transmission/
reception of a character.
•
•
•
A start bit (logic 0) is used to indicate the start of a frame.
The data is transmitted and received least significant bit first.
A stop bit (logic 1) is used to indicate the end of a frame. A frame
consists of a start bit, a character of eight or nine data bits, and a
stop bit.
•
A break is defined as the transmission or reception of a low
(logic 0) for at least one complete frame time.
CONTROL BIT M SELECTS
8- OR 9-BIT DATA
IDLE LINE
0
1
2
3
4
5
6
7
8
0
START
STOP
START
Figure 9-3. Data Format
9.8 Receiver Wakeup Operation
The receiver logic hardware also supports a receiver wakeup function
which is intended for systems having more than one receiver. With this
function a transmitting device directs messages to an individual receiver
or group of receivers by passing addressing information as the initial
byte(s) of each message. The wakeup function allows receivers not
addressed to remain in a dormant state for the remainder of the
unwanted message. This eliminates any further software overhead to
service the remaining characters of the unwanted message and thus
improves system performance.
Advance Information
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MC68HC05C9A — Rev. 5.0
Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
Receiver Wakeup Operation
The receiver is placed in wakeup mode by setting the receiver wakeup
bit (RWU) in the SCCR2 register. While RWU is set, all of the receiver-
related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot
become set).
NOTE: The idle line detect function is inhibited while the RWU bit is set.
Although RWU may be cleared by a software write to SCCR2, it would
be unusual to do so.
Normally, RWU is set by software and is cleared automatically in
hardware by one of these methods: idle line wakeup or address mark
wakeup.
9.8.1 Idle Line Wakeup
In idle line wakeup mode, a dormant receiver wakes up as soon as the
RDI line becomes idle. Idle is defined as a continuous logic high level on
the RDI line for 10 (or 11) full bit times. Systems using this type of
wakeup must provide at least one character time of idle between
messages to wake up sleeping receivers, but must not allow any idle
time between characters within a message.
9.8.2 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is
used to indicate whether it is an address (logic 1) or data (logic 0)
character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wakeup would set
the MSB of the first character of each message and leave it clear for all
other characters in the message. Idle periods may be present within
messages and no idle time is required between messages for this
wakeup method.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Serial Communications Interface (SCI)
79
Serial Communications Interface (SCI)
9.9 Receive Data In (RDI)
Receive data is the serial data that is applied through the input line and
the SCI to the internal bus. The receiver circuitry clocks the input at a
rate equal to 16 times the baud rate. This time is referred to as the RT
rate in Figure 9-4 and as the receiver clock in Figure 9-6.
16X INTERNAL SAMPLING CLOCK
RT CLOCK EDGES FOR ALL THREE EXAMPLES
3RT
0
1RT 2RT
START
4RT 5RT 6RT 7RT
IDLE
RDI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
START
NOISE
RDI
RDI
1
0
0
1
NOISE
START
0
0
0
0
Figure 9-4. SCI Examples of Start Bit Sampling Techniques
The receiver clock generator is controlled by the baud rate register;
however, the SCI is synchronized by the start bit, independent of the
transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop
bit are sampled three times at RT intervals 8RT, 9RT, and 10RT
(1RT is the position where the bit is expected to start), as shown in
Figure 9-5. The value of the bit is determined by voting logic which takes
the value of the majority of the samples. A noise flag is set when all three
samples on a valid start bit or data bit or the stop bit do not agree.
PREVIOUS BIT
SAMPLES
NEXT BIT
RDI
16RT 1RT
8RT
9RT
10RT
16RT 1RT
Figure 9-5. SCI Sampling Technique Used on All Bits
Advance Information
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MC68HC05C9A — Rev. 5.0
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Start Bit Detection
9.10 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more
sample times (referred to as the start edge verification samples in
Figure 9-4). If at least two of these three verification samples detect a
logic 0, a valid start bit has been detected; otherwise, the line is assumed
to be idle. A noise flag is set if all three verification samples do not detect
a logic 0. Thus, a valid start bit could be assumed with a set noise flag
present.
If a framing error has occurred without detection of a break (10 0s for 8-
bit format or 11 0s for 9-bit format), the circuit continues to operate as if
there actually was a stop bit, and the start edge will be placed artificially.
The last bit received in the data shift register is inverted to a logic 1, and
the three logic 1 start qualifiers (shown in Figure 9-4) are forced into the
sample shift register during the interval when detection of a start bit is
anticipated (see Figure 9-6); therefore, the start bit will be accepted no
sooner than it is anticipated.
DATA
EXPECTED STOP
DATA SAMPLES
DATA
ARTIFICIAL EDGE
START BIT
RDI
a) Case 1: Receive Line Low During Artificial Edge
DATA
EXPECTED STOP
START EDGE
DATA
RDI
START BIT
DATA SAMPLES
b) Case 2: Receive Line High During Expected Start Edge
Figure 9-6. SCI Artificial Start Following a Frame Error
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If the receiver detects that a break (RDRF = 1, FE = 1, receiver data
register = $003B) produced the framing error, the start bit will not be
artificially induced and the receiver must actually detect a logic 1 before
the start bit can be recognized (see Figure 9-7).
EXPECTED STOP
BREAK
DETECTED AS VALID START EDGE
START BIT
RDI
START
START EDGE
QUALIFIERS VERIFICATION
SAMPLES
DATA SAMPLES
Figure 9-7. SCI Start Bit Following a Break
9.11 Transmit Data Out (TDO)
Transmit data is the serial data from the internal data bus that is applied
through the SCI to the output line. Data format is as discussed in
9.7 Data Format and shown in Figure 9-3. The transmitter generates a
bit time by using a derivative of the RT clock, thus producing a
transmission rate equal to 1/16th that of the receiver sample clock.
9.12 SCI I/O Registers
These I/O registers control and monitor SCI operation:
•
•
•
•
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
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SCI I/O Registers
9.12.1 SCI Data Register
The SCI data register (SCDR), shown in Figure 9-8, is the buffer for
characters received and for characters transmitted.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SCD7
SDC6
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Unaffected by reset
Figure 9-8. SCI Data Register (SCDR)
9.12.2 SCI Control Register 1
The SCI control register 1 (SCCR1), shown in Figure 9-9, has these
functions:
•
Stores ninth SCI data bit received and ninth SCI data bit
transmitted
•
•
Controls SCI character length
Controls SCI wakeup method
Address: $000E
Bit 7
6
T8
U
5
4
M
U
3
WAKE
U
2
0
1
0
Bit 0
Read:
R8
Write:
Reset:
U
0
0
= Unimplemented
U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit at the same time that the
SCDR receives the other eight bits. Resets have no effect on the R8
bit.
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T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that the SCDR is loaded into the transmit register.
Resets have no effect on the T8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are 8 bits long
or 9 bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Resets have
no effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Method Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit (MSB) position of a
received character or an idle condition on the PD0/RDI pin. Resets
have no effect on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
9.12.3 SCI Control Register 2
SCI control register 2 (SCCR2), shown in Figure 9-10, has these
functions:
•
•
•
•
•
•
Enables the SCI receiver and SCI receiver interrupts
Enables the SCI transmitter and SCI transmitter interrupts
Enables SCI receiver idle interrupts
Enables SCI transmission complete interrupts
Enables SCI wakeup
Transmits SCI break characters
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
Address: $000F
Bit 7
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
TIE
Write:
Reset:
0
Figure 9-10. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TDRE flag
becomes set. Resets clear the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC flag
becomes set. Resets clear the TCIE bit.
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receiver Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the RDRF flag
or the OR flag becomes set. Resets clear the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Resets clear the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
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TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Resets clear the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Resets clear the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of standby state.
Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
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SCI I/O Registers
9.12.4 SCI Status Register
The SCI status register (SCSR), shown in Figure 9-11, contains flags to
signal these conditions:
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data SCDR complete
Receiver input idle
Noisy data
Framing error
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
TDRE
TC
RDRF
IDLE
OR
NF
FE
1
1
0
0
0
0
0
—
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty Flag
This clearable, read-only flag is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic 0 to
avoid an instant interrupt request when turning the transmitter on.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Flag
This clearable, read-only flag is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TDRE
generates an interrupt request if the TCIE bit in SCCR2 is also set.
Clear the TC bit by reading the SCSR with TC set, and then writing to
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the SCDR. Reset sets the TC bit. Software must initialize the TC bit
to logic 0 to avoid an instant interrupt request when turning the
transmitter on.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Flag
This clearable, read-only flag is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in the SCCR2 is also set. Clear the
RDRF bit by reading the SCSR with RDRF set and then reading the
SCDR.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Flag
This clearable, read-only flag is set when 10 or 11 consecutive
logic 1s appear on the receiver input. IDLE generates an interrupt
request if the ILIE bit in the SCCR2 is also set. Clear the ILIE bit by
reading the SCSR with IDLE set and then reading the SCDR.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun Flag
This clearable, read-only flag is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in the SCCR2 is also set. The data in
the shift register is lost, but the data already in the SCDR is not
affected. Clear the OR bit by reading the SCSR with OR set and then
reading the SCDR.
1 = Receive shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only flag is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
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Serial Communications Interface (SCI)
SCI I/O Registers
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR flag is set and the FE flag is not set. Clear the
FE bit by reading the SCSR and then reading the SCDR.
1 = Framing error
0 = No framing error
9.12.5 Baud Rate Register
The baud rate register (BAUD), shown in Figure 9-12, selects the baud
rate for both the receiver and the transmitter.
Address: $000D
Bit 7
6
5
SCP1
0
4
3
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
Read:
Write:
Reset:
SCP0
—
—
0
—
= Unimplemented
U = Unaffected
Figure 9-12. Baud Rate Register (BAUD)
SCP1 — SCP0–SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0.
Table 9-1. Baud Rate Generator
Clock Prescaling
Baud Rate
SCP1 and SCP0
Generator Clock
0 0
0 1
1 0
1 1
Internal clock ÷ 1
Internal clock ÷ 3
Internal clock ÷ 4
Internal clock ÷ 13
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Serial Communications Interface (SCI)
SCR2 — SCR0–SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 9-2. Resets have no effect on the SCR2–SCR0 bits.
Table 9-2. Baud Rate Selection
SCR2, SCR1,
and SCR0
SCI Baud Rate
(Baud)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Prescaled clock ÷ 1
Prescaled clock ÷ 2
Prescaled clock ÷ 4
Prescaled clock ÷ 8
Prescaled clock ÷ 16
Prescaled clock ÷ 32
Prescaled clock ÷ 64
Prescaled clock ÷ 128
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Section 10. Serial Peripheral Interface (SPI)
10.1 Content
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10.4.1
10.4.2
10.4.3
10.4.4
Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . .93
Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . .93
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.6.1
10.6.2
10.6.3
Serial Peripheral Control Register. . . . . . . . . . . . . . . . . . . .97
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . .99
Serial Peripheral Data I/O Register. . . . . . . . . . . . . . . . . .101
10.2 Introduction
The serial peripheral interface (SPI) is an interface built into the device
which allows several M68HC05 microcontroller units (MCU), or
M68HC05 MCU plus peripheral devices, to be interconnected within a
single printed circuit board. In an SPI, separate wires are required for
data and clock. In the SPI format, the clock is not included in the data
stream and must be furnished as a separate signal. An SPI system may
be configured in one containing one master MCU and several slave
MCUs or in a system in which an MCU is capable of being a master or a
slave.
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Serial Peripheral Interface (SPI)
10.3 Features
SPI features include:
•
•
•
•
•
•
•
•
•
Full-duplex, 4-wire synchronous transfers
Master or slave operation
Bus frequency divided by 2 (maximum) master bit frequency
Bus frequency (maximum) slave bit frequency
Four programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Write collision flag protection
Master-master mode fault protection capability
10.4 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described here.
Each signal function is described for both the master and slave modes.
NOTE: Any SPI output line has to have its corresponding data direction register
bit set. If this bit is clear, the line is disconnected from the SPI logic and
becomes a general-purpose input line. When the SPI is enabled, any
SPI input line is forced to act as an input regardless of what is in the
corresponding data direction register bit.
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MOTOROLA
Serial Peripheral Interface (SPI)
SPI Signal Description
SS
CPOL = 0
CPHA = 0
SCK
CPOL = 0
CPHA = 1
SCK
SCK
CPOL = 1
CPHA = 0
CPOL = 1
CPHA = 1
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
10.4.1 Master In/Slave Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Master Out/Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
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Serial Peripheral Interface (SPI)
10.4.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line a half cycle before the clock edge (SCK), in order for the slave
device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the
operation of the SPI.
10.4.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.The SS line on the master must be tied high. In master
mode, if the SS pin is pulled low during a transmission, a mode fault error
flag (MODF) is set in the SPSR. In master mode the SS pin can be
selected as a general-purpose output by writing a 1 in bit 5 of the port D
data direction register, thus disabling the mode fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to VSS as long as CPHA = 1 clock modes are used.
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Serial Peripheral Interface (SPI)
Functional Description
10.5 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the input/output (I/O) operation
has been completed.
S
PD2/
MISO
M
M
SPI SHIFT REGISTER
PD3/
MOSI
S
7
6 5 4 3 2 1 0
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL
CLOCK
(XTAL ÷2)
SPIE
SPE
SPIF
WCOL
MODF
MSTR
DIVIDER
SPI
CONTROL
SPI INTERRUPT REQUEST
PD5/
SS
÷ 2
÷ 4 ÷ 16 ÷ 32
SPI
SPI CLOCK (MASTER)
CLOCK
LOGIC
SELECT
CLOCK
MASTER
PD4/
SCK
SPI
CLOCK
SLAVE
SPR1 SPR0
MSTR CPHA CPOL
7
6
5
4
3
2
1
0
SPI CONTROL REGISTER (SPCR) SPIE
SPE
DWOM MSTR CPOL CPHA SPR1 SPR2 $000A
SPI STATUS REGISTER (SPSR) SPIF WCOL
SPI DATA REGISTER (SPDR) BIT 7 BIT 6
0
MODF
BIT 4
0
0
0
0
$000B
BIT 5
BIT 3
BIT 2
BIT 1
BIT 0 $000C
Figure 10-2. Serial Peripheral Interface Block Diagram
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
The SPI is double buffered on read, but not on write. If a write is
performed during data transfer, the transfer occurs uninterrupted, and
the write will be unsuccessful. This condition will cause the write collision
(WCOL) status bit in the SPSR to be set. After a data byte is shifted, the
SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5/SS
7
6
5
4
3
2
1
0
7 6 5 4 3 2 1 0
I/O PORT
SPDR ($000C)
SPDR ($000C)
PD4/SCK
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface
Master-Slave Interconnection
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Serial Peripheral Interface (SPI)
SPI Registers
10.6 SPI Registers
This subsection describes the three registers in the SPI which provide
control, status, and data storage functions. These registers are:
•
•
•
Serial peripheral control register (SPCR)
Serial peripheral status register (SPSR)
Serial peripheral data I/O register (SPDR)
10.6.1 Serial Peripheral Control Register
The SPI control register (SPCR), shown in Figure 10-4, controls these
functions:
•
•
•
•
•
•
Enables SPI interrupts
Enables the SPI system
Selects between standard CMOS or open drain outputs for port D
Selects between master mode and slave mode
Controls the clock/data relationship between master and slave
Determines the idle level of the clock pin
Address: $000A
Bit 7
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
Read:
SPIE
Write:
Reset:
0
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
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SPE — Serial Peripheral System Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI system enabled
0 = SPI system disabled
DWOM — Port D Wire-OR Mode Option Bit
This read/write bit disables the high side driver transistors on port D
outputs so that port D outputs become open-drain drivers. DWOM
affects all seven port D pins together.
1 = Port D outputs act as open-drain outputs.
0 = Port D outputs are normal CMOS outputs.
MSTR — Master Mode Select Bit
This read/write bit selects master mode operation or slave mode
operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA=1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
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MOTOROLA
Serial Peripheral Interface (SPI)
SPI Registers
SPR1 and SPR0 — SPI Clock Rate Select Bits
These read/write bits select one of four master mode serial clock
rates, as shown in Table 10-1. They have no effect in slave mode.
Table 10-1. SPI Clock Rate Selection
SPR1 and SPR0
SPI Clock Rate
Internal clock ÷ 2
Internal clock ÷ 4
Internal clock ÷ 16
Internal clock ÷ 32
0 0
0 1
1 0
1 1
10.6.2 Serial Peripheral Status Register
The SPI status register (SPSR), shown in Figure 10-5, contains flags to
signal these conditions:
•
•
•
SPI transmission complete
Write collision
Mode fault
Address: $000B
Bit 7
6
5
0
4
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
SPIF
WCOL
MODF
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. SPI Status Register
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
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Serial Peripheral Interface (SPI)
SPIF set) followed by an access of the SPDR. Following the initial
transfer, unless SPSR is read (with SPIF set) first, attempts to write to
SPDR are inhibited.
WCOL — Write Collision Bit
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is 0, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is 1, a transfer is said to begin the first time SCK
becomes active while SS is low and the transfer ends when the SPIF
flag gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
MODF — Mode Fault Flag
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear, and is set only when the master device has its SS pin pulled
low. Setting the MODF bit affects the internal serial peripheral
interface system in these ways:
1. An SPI interrupt is generated if SPIE = 1.
2. The SPE bit is cleared. This disables the SPI.
3. The MSTR bit is cleared, thus forcing the device into the
slave mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state during
this clearing sequence or after the MODF bit has been cleared. It is
also necessary to restore DDRD after a mode fault.
Bits 5 and 3–0 — Not Implemented
These bits always read 0.
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MOTOROLA
Serial Peripheral Interface (SPI)
SPI Registers
10.6.3 Serial Peripheral Data I/O Register
The serial peripheral data I/O register (SPDR), shown in Figure 10-6, is
used to transmit and receive data on the serial bus. Only a write to this
register will initiate transmission/reception of another byte and this will
only occur in the master device. At the completion of transmitting a byte
of data, the SPIF status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places
data directly into the shift register for transmission.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Unaffected by reset
Figure 10-6. SPI Data Register (SPDR)
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Serial Peripheral Interface (SPI)
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MOTOROLA
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Section 11. Instruction Set
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .107
Read-Modify-Write Instructions. . . . . . . . . . . . . . . . . . . . .108
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .109
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .111
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
11.2 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 CMOS (complementary metal-oxide semiconductor) Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
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Instruction Set
11.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction. The eight addressing modes are:
•
•
•
•
•
•
•
•
Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
11.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
11.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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MOTOROLA
Instruction Set
Addressing Modes
11.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
11.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
11.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used random-access
memory (RAM) or input/output (I/O) location.
11.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
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Instruction Set
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
11.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
11.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
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MOTOROLA
Instruction Set
Instruction Types
11.4 Instruction Types
The MCU instructions fall into these five categories:
•
•
•
•
•
Register/memory instructions
Read-modify-write instructions
Jump/branch instructions
Bit manipulation instructions
Control instructions
11.4.1 Register/Memory Instructions
These instructions operate on central processor unit (CPU) registers and
memory locations. Most of them use two operands. One operand is in
either the accumulator or the index register. The CPU finds the other
operand in memory.
Table 11-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Instruction Set
Instruction Set
11.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence be-
cause it does not write a replacement value.
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Instruction Set
Instruction Set
Instruction Types
11.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Table 11-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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MOTOROLA
Instruction Set
Instruction Types
11.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 11-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
11.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 11-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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MOTOROLA
Instruction Set
Instruction Set
11.5 Instruction Set Summary
.
Table 11-6. Instruction Set Summary (Sheet 1 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
ii
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
B9 dd
C9 hh ll
D9 ee ff
E9
F9
Add with Carry
A ← (A) + (M) + (C)
↕ —
↕ —
— —
↕
↕
↕
↕
↕
↕
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
ii
2
3
4
5
4
3
BB dd
CB hh ll
DB ee ff
EB
FB
Add without Carry
A ← (A) + (M)
A ← (A) ∧ (M)
↕
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
ii
2
3
4
5
4
3
B4 dd
C4 hh ll
D4 ee ff
E4
F4
Logical AND
↕ —
ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
5
3
3
6
5
Arithmetic Shift Left
(Same as LSL)
— —
— —
↕
↕
↕
↕
↕
↕
C
0
68
78
ff
b7
b7
b0
b0
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37 dd
47
57
5
3
3
6
5
C
Arithmetic Shift Right
67
77
ff
Branch if Carry Bit
Clear
BCC rel
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
Branch if Carry Bit Set
(Same as BLO)
BCS rel
BEQ rel
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
— — — — —
REL
REL
25
27
rr
rr
3
3
Branch if Equal
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MOTOROLA
Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 2 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
Branch if Half-Carry
Bit Clear
BHCC rel
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
Branch if Half-Carry
Bit Set
BHCS rel
BHI rel
PC ← (PC) + 2 + rel ? H = 1
PC ← (PC) + 2 + rel ? C ∨ Z = 0
PC ← (PC) + 2 + rel ? C = 0
— — — — —
— — — — —
— — — — —
REL
REL
REL
29
22
24
rr
rr
rr
3
3
3
Branch if Higher
Branch if Higher or
Same
BHS rel
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
— — — — —
REL
REL
2F
2E
A5
B5 dd
C5 hh ll
D5 ee ff
rr
rr
ii
3
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
2
3
4
5
4
3
Bit Test
Accumulator with
Memory Byte
(A) ∧ (M)
— —
↕
↕ —
E5
F5
ff
p
Branch if Lower
(Same as BCS)
BLO rel
BLS rel
PC ← (PC) + 2 + rel ? C = 1
— — — — —
— — — — —
REL
REL
25
23
rr
rr
3
3
Branch if Lower or
Same
PC ← (PC) + 2 + rel ? C ∨ Z = 1
Branch if Interrupt
Mask Clear
BMC rel
BMI rel
BMS rel
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
2C
2B
2D
rr
rr
rr
3
3
3
Branch if Minus
Branch if Interrupt
Mask Set
BNE rel
BPL rel
BRA rel
Branch if Not Equal
Branch if Plus
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
26
2A
20
rr
rr
rr
3
3
3
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if bit n clear
PC ← (PC) + 2 + rel ? Mn = 0
— — — — ↕
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MOTOROLA
Instruction Set
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 3 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1
PC ← (PC) + 2 + rel ? 1 = 0
Mn ← 1
— — — — ↕
BRN rel
Branch Never
Set Bit n
— — — — —
— — — — —
REL
21
rr
3
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to
Subroutine
BSR rel
— — — — —
REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F dd
4F
5F
5
3
3
6
5
Clear Byte
— — 0 1 —
6F
7F
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
ii
2
3
4
5
4
3
B1 dd
C1 hh ll
D1 ee ff
E1
F1
Compare
Accumulator with
Memory Byte
(A) – (M)
— —
— —
↕
↕
↕
↕
↕
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← ( ) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
53
63
73
5
3
3
6
5
M
A ← ( ) = $FF – (M)
A
Complement Byte
(One’s Complement)
X ← (X) = $FF – (M)
1
M ← ( ) = $FF – (M)
ff
M
M ← ( ) = $FF – (M)
M
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MOTOROLA
Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 4 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
CPX #opr
IMM
DIR
EXT
IX2
IX1
IX
A3
ii
2
3
4
5
4
3
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
B3 dd
C3 hh ll
D3 ee ff
E3
F3
Compare Index
Register with
Memory Byte
(X) – (M)
— —
— —
— —
↕
↕
↕
↕
1
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A dd
4A
5A
6A
7A
5
3
3
6
5
Decrement Byte
↕ —
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
ii
2
3
4
5
4
3
B8 dd
C8 hh ll
D8 ee ff
E8
F8
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) ⊕ (M)
↕ —
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
5C
5
3
3
6
5
Increment Byte
— —
↕
↕ —
6C
7C
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
— — — — —
EC
FC
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
— — — — —
ED
FD
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
ii
2
3
4
5
4
3
B6 dd
C6 hh ll
D6 ee ff
E6
F6
Load Accumulator with
Memory Byte
A ← (M)
— —
↕
↕ —
ff
MC68HC05C9A — Rev. 5.0
Advance Information
115
MOTOROLA
Instruction Set
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 5 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
ii
2
3
4
5
4
3
BE dd
CE hh ll
DE ee ff
EE
FE
Load Index Register
with Memory Byte
X ← (M)
— —
↕
↕
↕ —
ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
68
78
5
3
3
6
5
Logical Shift Left
(Same as ASL)
C
0
— —
↕
↕
↕
↕
b7
b0
ff
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34 dd
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0
b7
b0
ff
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
11
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
ii
5
3
3
6
5
Negate Byte
(Two’s Complement)
— —
↕
↕
↕
ff
NOP
No Operation
— — — — —
INH
9D
AA
BA dd
CA hh ll
DA ee ff
2
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
ii
2
3
4
5
4
3
Logical OR
Accumulator with
Memory
A ← (A) ∨ (M)
— —
↕
↕ —
EA
FA
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39 dd
49
59
5
3
3
6
5
Rotate Byte Left
through Carry Bit
C
— —
— —
↕
↕
↕
↕
↕
↕
b7
b0
69
79
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36 dd
46
56
5
3
3
6
5
Rotate Byte Right
through Carry Bit
C
b7
b0
66
76
ff
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
Advance Information
116
MC68HC05C9A — Rev. 5.0
Instruction Set
MOTOROLA
Instruction Set
Instruction Set Summary
Table 11-6. Instruction Set Summary (Sheet 6 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I
N Z C
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
Return from Interrupt
↕
↕
↕
↕
↕
INH
INH
80
A2
B2 dd
C2 hh ll
D2 ee ff
6
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
— — — — —
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
ii
2
3
4
5
4
3
Subtract Memory Byte
and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— —
↕
↕
↕
E2
F2
ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
4
5
6
5
4
Store Accumulator in
Memory
M ← (A)
— —
↕
↕ —
E7
F7
ff
Stop Oscillator and
Enable IRQ Pin
STOP
— 0 — — —
INH
8E
2
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
4
5
6
5
4
Store Index
Register In Memory
M ← (X)
— —
— —
↕
↕
↕ —
EF
FF
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
ii
2
3
4
5
4
3
B0 dd
C0 hh ll
D0 ee ff
Subtract Memory Byte
from
Accumulator
A ← (A) – (M)
↕
↕
E0
F0
ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
— 1 — — —
INH
83
10
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
MC68HC05C9A — Rev. 5.0
Advance Information
117
MOTOROLA
Instruction Set
Instruction Set
Table 11-6. Instruction Set Summary (Sheet 7 of 7)
Effect
Source
Form
on CCR
Operation
Description
H
I N Z C
Transfer
TAX
Accumulator to Index
Register
X ← (A)
— — — — —
— — — — —
— — — — —
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D dd
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for
Negative or Zero
(M) – $00
A ← (X)
ff
Transfer Index
Register to
Accumulator
TXA
INH
INH
9F
8F
2
2
Stop CPU Clock and
Enable
WAIT
—
↕ — — —
Interrupts
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP
X
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
Z
Zero flag
hh ll High and low bytes of operand address in extended addressing
#
∧
∨
Immediate value
Logical AND
Logical OR
I
Interrupt mask
ii
Immediate operand byte
IMM Immediate addressing mode
INH Inherent addressing mode
⊕
( )
–( )
←
?
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
IX
IX1
IX2
M
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
If
:
↕
Concatenated with
Set or cleared
N
Negative flag
n
Any bit
—
Not affected
11.6 Opcode Map
See Table 11-7.
Advance Information
118
MC68HC05C9A — Rev. 5.0
Instruction Set
MOTOROLA
Instruction Set
Opcode Map
MC68HC05C9A
MOTOROLA
—
Rev. 5.0
Advance Information
119
Instruction Set
Instruction Set
Advance Information
120
MC68HC05C9A — Rev. 5.0
Instruction Set
MOTOROLA
Advance Information — MC68HC05C9A
Section 12. Electrical Specifications
12.1 Contents
12.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
12.3 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.5 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
12.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .125
12.7 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .126
12.8 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
12.9 3.3-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12.10 5.0-Volt Serial Peripheral Interface Timing. . . . . . . . . . . . . . .132
12.11 3.3-Volt Serial Peripheral Interface Timing. . . . . . . . . . . . . . .133
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
Electrical Specifications
121
Electrical Specifications
12.2 Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit
(MCU) can be exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD
.
Rating
Symbol
Value
Unit
V
–0.3 to +7.0
V
Supply voltage
DD
Input voltage
Normal operation
Self-check mode (IRQ pin only)
V
V
–0.3 to V + 0.3
V
In
SS
DD
V
V
–0.3 to 2 x V + 0.3
TST
SS
DD
Current drain per pin
I
25
mA
(Excluding V and V
)
SS
DD
T
–65 to +150
°C
Storage temperature range
STG
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.6 5.0-Volt DC Electrical Characteristics for
guaranteed operating conditions.
Advance Information
122
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Temperature
12.3 Operating Temperature
Characteristic
Symbol
Value
T to T
0 to +70
–40 to +125
Unit
Operating temperature range
MC68HC05C9AP, FN, B, FB
MC68HC05C9AMP, MFN, MB, MFB
L
H
T
°C
A
12.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance plastic dual in-line (PDIP)
θ
60
°C/W
JA
Thermal resistance plastic-leaded chip carrier
(PLCC)
θ
70
°C/W
JA
θ
95
60
°C/W
°C/W
Thermal resistance quad flat pack (QFP)
Thermal resistance plastic shrink DIP (SDIP)
JA
θ
JA
VDD
R2
SEE TABLE
TEST
POINT
C
SEE TABLE
R1
SEE TABLE
V
= 4.5 V
DD
Pins
R1
R2
C
PA7–PA0
PB7–PB0
3.26 Ω
2.38 Ω
50 pF
PC7–PC0
PD5–PD0, PD7
V
= 3.0 V
DD
Pins
R1
R2
C
PA7–PA0
PB7–PB0
10.91 Ω
6.32 Ω
50 pF
PC7–PC0
PD5–PD0, PD7
Figure 12-1. Test Load
MC68HC05C9A — Rev. 5.0
Advance Information
123
MOTOROLA
Electrical Specifications
Electrical Specifications
12.5 Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ = TA + (PD × θJA) (1)
where:
TA = Ambient temperature, °C
JA = Package thermal resistance, junction to ambient, °C/W
θ
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user determined)
For most applications, PI/O « PINT and can be neglected.
The following is an approximate relationship between PD and TJ
(neglecting PJ):
PD = K ÷ (TJ + 273°C)
(2)
(3)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Advance Information
124
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-Volt DC Electrical Characteristics
12.6 5.0-Volt DC Electrical Characteristics
(1) (2)
Symbol
Min
Typ
Max
Unit
Characteristic
Output voltage
I
I
= 10.0 µA
= –10.0 µA
V
V
—
—
—
0.1
—
V
Load
Load
OL
V
–0.1
OH
DD
Output high voltage
(I
= –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
TCMP, PD7, PD0
V
V
V
V
–0.8
–0.8
–0.8
—
—
—
—
—
—
V
V
OH
DD
DD
DD
(I
(I
= –1.6 mA) PD5–PD1
= –5.0 mA) PC7
Load
Load
Output low voltage
(I
= 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
V
OL
Load
PD7, PD5–PD0, TCMP
= 10 mA) PC7
—
—
—
—
0.4
0.4
(I
Load
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
0.7 × V
—
—
V
V
V
IH
DD
DD
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
V
0.2 × V
DD
IL
DD
OZ
SS
Supply current (4.5–5.5 Vdc @ f = 2.1 MHz)
OP
(3)
Run
Wait
Stop
—
—
3.5
1.0
5.25
3.25
mA
mA
(4)
(5)
I
25°C
0 to 70°C
–40 to +125°C
—
—
—
1.0
2.0
7.0
20.0
40.0
50.0
µA
µA
µA
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
I
—
1.0
10
µA
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
I
I
—
0.5
1
µA
µA
In
In
(6)
Input pullup current
PB7–PB0 (with pullup)
5
—
60
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
C
C
—
—
—
—
12
8
pF
Out
In
1. V = 5.0 Vdc 10%, V = 0 Vdc, T = –40 to +125°C, unless otherwise noted
DD
SS
A
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, port B = V
,
DD
DD
all other inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2
IL
IH
DD
L
4. Wait I measured using external square wave clock source; all I/O pins configured as inputs, port B = V , all other
DD
DD
inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected
IL
IH
DD
L
DD
linearly by the OSC2 capacitance.
5. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V
IH
DD
6. Input pullup current measured with V = 0.2 V
IL
MC68HC05C9A — Rev. 5.0
Advance Information
125
MOTOROLA
Electrical Specifications
Electrical Specifications
12.7 3.3-Volt DC Electrical Characteristics
(1) (2)
Characteristic
Symbol
Min
Typ
Max
Unit
Output voltage
I
I
= 10.0 µA
= –10.0 µA
V
V
—
—
—
0.1
—
V
Load
Load
OL
V
–0.1
OH
DD
Output high voltage
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
TCMP, PD7, PD0
V
V
V
V
–0.3
–0.3
–0.3
—
—
—
—
—
—
V
V
OH
DD
DD
DD
(I
(I
= –0.4 mA) PD5–PD1
= –1.5 mA) PC7
Load
Load
Output low voltage
(I
= 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
V
OL
PD7, PD5–PD0, TCMP
= 6 mA) PC7
—
—
—
—
0.3
0.3
(I
Load
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
0.7 × V
—
—
V
V
V
IH
DD
DD
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
V
0.2 × V
DD
IL
DD
OZ
SS
Supply current (3.0–3.6 Vdc @ f = 1.0 MHz)
OP
(3)
Run
Wait
Stop
—
—
1.0
500
1.6
900
mA
µA
(4)
(5)
I
I
25°C
0 to 70°C
–40 to +125°C
—
—
—
1.0
1.0
2.5
8
16
20
µA
µA
µA
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
—
1.0
10
µA
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
I
I
—
0.5
1
µA
µA
In
In
(6)
Input pullup current
PB7–PB0 (with pullup)
0.5
—
20
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
C
C
—
—
—
—
12
8
pF
Out
In
1. V = 3.3 Vdc 0.3 Vdc, V = 0 Vdc, TA = –40 to +125°C, unless otherwise noted
DD
SS
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, port B = V
,
DD
DD
all other inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2
IL
IH
DD
L
4. Wait I measured using external square wave clock source; all I/O pins configured as inputs, port B = V , all other
DD
DD
inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected
IL
IH
DD
L
DD
linearly by the OSC2 capacitance.
5. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V
IH
DD
6. Input pullup current measured with V = 0.2 V
IL
Advance Information
126
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt DC Electrical Characteristics
VDD = 5.5 V
T = –40° to 85°
5.00 mA
4.00 mA
3.00 mA
2.00 mA
1.00 mA
I
T
I
A
W
50 mA
STOP IDD
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 12-2. Maximum Supply Current versus Internal Clock Frequency, VDD = 5.5 V
VDD = 3.6 V
T = –40° to 85°
1.50 mA
1.00 mA
500 mA
STOP IDD
0.5 MHz
1.0 MHz
Figure 12-3. Maximum Supply Current versus Internal Clock Frequency, VDD = 3.6 V
MC68HC05C9A — Rev. 5.0
Advance Information
127
MOTOROLA
Electrical Specifications
Electrical Specifications
12.8 5.0-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
Crystal
External clock
f
—
dc
4.2
4.2
MHz
OSC
Internal operating frequency (f
Crystal
External clock
÷ 2)
OSC
f
—
dc
2.1
2.1
MHz
OP
t
480
—
—
100
100
—
ns
ms
ms
Cycle time
cyc
Crystal oscillator startup time
t
OXOV
t
—
Stop recovery startup time (crystal oscillator)
ILCH
t
1.5
t
RESET pulse width
RL
cyc
Timer
Resolution
(2)
t
4.0
—
—
—
t
cyc
ns
RESL
, t
t
125
Input capture pulse width
Input capture pulse period
TH TL
t
(3)
t
TLTL
cyc
t
125
—
—
—
ns
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
ILIH
(4)
t
t
cyc
ILIL
OSC1 pulse width
t
, t
90
ns
OH OL
1. V = 5.0 Vdc 10%, V = 0 Vdc, T = –40 to +125°C, unless otherwise noted
DD
SS
A
2. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt
TLTL
service routine plus 24 t
.
CYC
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
CYC
Advance Information
128
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Control Timing
12.9 3.3-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
Crystal
External clock
f
—
dc
2.0
2.0
MHz
OSC
Internal operating frequency (f
Crystal
External clock
÷ 2)
OSC
f
—
dc
1.0
1.0
MHz
OP
t
1000
—
—
100
100
—
ns
ms
ms
Cycle time
cyc
Crystal oscillator start-up time
t
OXOV
t
—
Stop recovery start-up time (crystal oscillator)
ILCH
t
1.5
t
RESET pulse width
RL
cyc
Timer
Resolution
(2)
t
4.0
—
—
—
t
cyc
ns
RESL
, t
t
125
Input capture pulse width
Input capture pulse period
TH TL
t
(3)
t
TLTL
cyc
t
250
—
—
—
ns
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
ILIH
(4)
t
t
cyc
ILIL
OSC1 pulse width
t
, t
200
ns
OH OL
1. V = 3.3 Vdc 0.3 Vdc, V = 0 Vdc, T = –40 to +125°C, unless otherwise noted
DD
SS
A
2. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt
TLTL
service routine plus 24 t
.
CYC
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
CYC
(1)
(1)
(1)
tTH
tTL
tTLTL
TCAP PIN
1. Refer to timer resolution data in 12.8 5.0-Volt Control Timing and 12.9 3.3-Volt Control Timing.
Figure 12-4. TCAP Timing Relationships
MC68HC05C9A — Rev. 5.0
Advance Information
129
MOTOROLA
Electrical Specifications
Electrical Specifications
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t ) is either 125 ns (f = 2.1 MHz)
ILIH
OP
or 250 ns (f = 1 MHz). The period tILIL should not be less than the number of t
cycles it takes to
OP
CYC
execute the interrupt service routine plus 19 t
cycles.
CYC
tILIH
IRQ1
.
.
.
NORMALLY
USED WITH
WIRED-OR
IRQN
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,
the next interrupt is recognized.
Figure 12-5. External Interrupt Timing
OSC(1)
RESET
IRQ(2)
tRL
tILIH
4064 tCYC
IRQ(3)
INTERNAL
CLOCK
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF4
Notes:
RESET OR INTERRUPT
VECTOR FETCH
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
Figure 12-6. Stop Recovery Timing Diagram
Advance Information
130
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Control Timing
NOTE 1
VDD
OSC1 PIN(2)
4064 tCYC
INTERNAL
CLOCK(3)
INTERNAL
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
ADDRESS BUS(3)
INTERNAL
NEW
PCH
NEW
PCL
DATA BUS(3)
NOTE 4
RESET PIN
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
4. RESET outputs VOL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
INTERNAL
CLOCK(1)
INTERNAL
$3FFE
$3FFE
$3FFE
$3FFE
$3FFF
NEW PC
ADDRESS BUS(1)
INTERNAL
NEW
PCH
NEW
PCL
OP
CODE
DATA BUS(1)
RESET(2)
tRL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
MC68HC05C9A — Rev. 5.0
MOTOROLA
Advance Information
131
Electrical Specifications
Electrical Specifications
12.10 5.0-Volt Serial Peripheral Interface Timing
Characteristic(1)
No.
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
480
—
—
tCYC
ns
Enable lead time
Master
Slave
tLead(M)
tLead(S)
Note(2)
240
—
—
ns
ns
ns
ns
ns
ns
Enable lag time
Master
Slave
tLag(M)
tLag(S)
Note(2)
720
—
—
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
Slave access time (time to data active from
high-impedance state)
8
9
tA
0
120
240
ns
ns
Slave disable time (hold time to high-impedance state)
tDIS
—
Data Valid
10
11
12
13
Master (before capture edge)
tV(M)
tV(S)
0.25
—
—
240
tCYC(M)
ns
Slave (after enable edge)(3)
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
1. V = 5.0 Vdc 10%; V = 0 Vdc, T = –40 to +125°C, unless otherwise noted. Refer to Figure 12-9 and Figure 12-10
DD
SS
A
for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Advance Information
132
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface Timing
12.11 3.3-Volt Serial Peripheral Interface Timing
Characteristic(1)
No.
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
1.0
fOP
MHz
Cycle time
Master
Slave
1
2
3
4
5
6
7
tCYC(M)
tCYC(S)
2.0
1.0
—
—
tCYC
ns
Enable lead time
Master
Slave
tLead(M)
tLead(S)
Note 2
500
—
—
ns
ns
ns
ns
ns
ns
Enable lag time
Master
Slave
tLag(M)
tLag(S)
Note 2
1.5
—
—
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
—
—
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
—
—
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
200
200
—
—
Data hold time (inputs)
Master
Slave
t
200
200
—
—
H(M)
tH(S)
Slave access time (time to data active
from high-impedance state)
8
9
tA
0
250
500
ns
ns
Slave disable time (hold time to high-impedance state)
tDIS
—
Data valid
10
11
12
13
Master (before capture edge)
tV(M)
tV(S)
0.25
—
—
500
tCYC(M)
ns
Slave (after enable edge)(3)
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tCYC(M)
ns
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
200
2.0
ns
µs
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
200
2.0
ns
µs
1. V = 3.3 Vdc 0.3 Vdc; V = 0 Vdc, T = –40 to +125°C, unless otherwise noted. Refer to Figure 12-9 and
DD
SS
A
Figure 12-10 for timing diagrams.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C9A — Rev. 5.0
Advance Information
133
MOTOROLA
Electrical Specifications
Electrical Specifications
SS
INPUT
SS pin of master held high.
12
13
12
13
1
5
4
SCK (CPOL = 0)
OUTPUT
NOTE
NOTE
4
5
12
SCK (CPOL = 1)
OUTPUT
6
7
MISO
INPUT
MSB IN
BITS 6–1
BITS 6–1
LSB IN
10 (ref)
11
MASTER MSB OUT
10
11 (ref)
MOSI
OUTPUT
MASTER LSB OUT
12
13
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
INPUT
SS pin of master held high.
1
13
12
12
SCK (CPOL = 0)
OUTPUT
5
4
NOTE
NOTE
4
5
13
SCK (CPOL = 1)
OUTPUT
6
7
MISO
INPUT
MSB IN
BITS 6–1
BITS 6–1
LSB IN
10 (ref)
MOSI
11
MASTER MSB OUT
10
11
MASTER LSB OUT
12
OUTPUT
13
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 12-9. SPI Master Timing Diagram
Advance Information
134
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-Volt Serial Peripheral Interface Timing
SS
INPUT
1
13
12
3
SCK (CPOL = 0)
INPUT
5
4
4
5
2
SCK (CPOL = 1)
INPUT
8
12
11
13
9
MISO
INPUT
SLAVE
6
MSB OUT
7
BITS 6–1
BITS 6–1
SLAVE LSB OUT
NOTE
10
11
MOSI
OUTPUT
MSB IN
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
13
12
1
SCK (CPOL = 0)
INPUT
5
4
4
5
2
3
SCK (CPOL = 1)
INPUT
10
12
10
13
9
8
MISO
OUTPUT
NOTE
SLAVE
6
MSB OUT
7
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
MOSI
INPUT
MSB IN
LSB IN
Note: Not defined but normally LSB of character previously transmitted
a) SPI Slave Timing (CPHA = 1)
Figure 12-10. SPI Slave Timing Diagram
MC68HC05C9A — Rev. 5.0
Advance Information
135
MOTOROLA
Electrical Specifications
Electrical Specifications
Advance Information
136
MC68HC05C9A — Rev. 5.0
Electrical Specifications
MOTOROLA
Advance Information — MC68HC05C9A
Section 13. Mechanical Specifications
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.3 40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package
(Case 858-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
13.5 44-Lead Plastic-Leaded Chip Carrier (PLCC)
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
13.6 44-Lead Quad Flat Pack (QFP)
(Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
13.2 Introduction
This section describes the dimensions of the plastic dual in-line package
(DIP), plastic shrink dual in-line package (SDIP), plastic-leaded chip
carrier (PLCC), and quad flat pack (QFP) MCU packages.
Package dimensions available at the time of this publication are
provided in this section.
To make sure that you have the latest case outline specifications,
contact one of the following:
•
•
Local Motorola Sales Office
World Wide Web at http://www.mcu.motsps.com
Follow World Wide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC05C9A — Rev. 5.0
Advance Information
137
MOTOROLA
Mechanical Specifications
Mechanical Specifications
13.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
40
21
20
B
1
MILLIMETERS
INCHES
DIM
MIN
MAX
MIN
MAX
A
B
C
D
F
51.69
13.72
3.94
52.45
14.22
5.08
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
L
A
C
0.36
0.56
N
1.02
1.52
2.54 BSC
0.100 BSC
G
H
J
J
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
K
SEATING
PLANE
M
H
G
F
D
K
L
15.24 BSC
0.600 BSC
0°
0.51
1°
1.02
0°
0.020
1°
0.040
M
N
Figure 13-1. 40-Pin Plastic DIP Package (Case 711-03)
13.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01)
-A-
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
42
1
22
21
-B-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
INCHES
MIN MAX
MILLIMETERS
MIN MAX
L
DIM
A
B
C
D
F
1.435 1.465 36.45 37.21
0.540 0.560 13.72 14.22
H
C
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
3.94
0.36
0.81
5.08
0.56
1.17
G
H
J
1.778 BSC
7.62 BSC
0.300 BSC
-T-
SEATING
PLANE
0.008 0.015
0.115 0.135
0.600 BSC
0.20
2.92
0.38
3.43
K
L
N
G
15.24 BSC
M
F
M
N
0° 15°
0.020 0.040
0°
0.51
15°
1.02
K
J 42 PL
0.25 (0.010)
D 42 PL
M
S
B
M
S
A
T
0.25 (0.010)
T
Figure 13-2. 42-Pin Plastic SDIP Package (Case 858-01)
Advance Information
138
MC68HC05C9A — Rev. 5.0
Mechanical Specifications
MOTOROLA
Mechanical Specifications
44-Lead Plastic-Leaded Chip Carrier (PLCC) (Case 777-02)
13.5 44-Lead Plastic-Leaded Chip Carrier (PLCC) (Case 777-02)
M
S
S
N
0.007(0.180)
T
L-M
B
D
-N-
YBRK
-M-
M
S
S
0.007(0.180)
T
L-M
N
U
Z
-L-
V
X
G1
0.010 (0.25)
W
D
44
1
S
S
S
N
T
L-M
VIEW D-D
M
M
S
S
S
S
A
R
0.007(0.180)
0.007(0.180)
T
T
L-M
L-M
N
N
M
S
S
N
0.007(0.180)
T
L-M
H
Z
J
K1
E
0.004 (0.10)
G
K
C
SEATING
PLANE
-T-
G1
F
VIEW S
S
S
N
S
M
S
S
0.010 (0.25)
T
L-M
0.007(0.180)
T
L-M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1.DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
DIM
A
MIN
MAX
0.695
0.695
0.180
0.110
0.019
MIN
17.40
17.40
4.20
MAX
17.65
17.65
4.57
0.685
0.685
0.165
0.090
0.013
B
C
E
2.29
2.79
F
0.33
0.48
G
H
0.050 BSC
1.27 BSC
4.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETER-
0.026
0.020
0.025
0.650
0.650
0.032
0.66
0.51
0.81
J
K
0.64
R
0.656
0.656
0.048
0.048
0.056
0.020
10°
16.51
16.51
1.07
16.66
16.66
1.21
1.21
1.42
0.50
10°
U
MINED
V
0.042
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940140). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
W
X
0.042
0.042
1.07
1.07
Y
2°
0.610
2°
15.50
1.02
Z
G1
K1
0.630
16.00
0.040
Figure 13-3. 44-Lead PLCC (Case 777-02)
MC68HC05C9A — Rev. 5.0
Advance Information
139
MOTOROLA
Mechanical Specifications
Mechanical Specifications
13.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33
23
34
22
B
B
-A,B,D-
-A-
-B-
L
B
V
DETAIL A
DETAIL A
44
12
1
11
F
-D-
A
C
BASE METAL
M
S
S
S
0.20 (0.008)
A-B
A-B
D
0.05 (0.002) A-B
S
J
N
M
S
0.20 (0.008)
D
H
D
M
S
S
D
0.20 (0.008)
C
A-B
M
DETAIL C
SECTION B–B
E
C
DATUM
PLANE
-H-
-C-
SEATING
PLANE
0.01 (0.004)
H
G
M
MILLIMETERS
MIN MAX
INCHES
MIN MAX
NOTES:
DIM
A
B
C
D
E
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
9.90 10.10
9.90 10.10
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
M
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ĆCĆ.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCHAND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
2.10
0.30
2.00
0.30
2.45
0.45
2.10
0.40
T
F
0.80 BSC
G
H
J
Ċ
0.25
0.23
0.95
Ċ
0.010
DATUM
-H-
PLANE
0.13
0.65
0.005 0.009
0.026 0.037
0.315 REF
R
K
L
8.00 REF
M
N
Q
R
S
5°
0.13
10°
0.17
7°
5°
0.005 0.007
0° 7°
10°
0°
0.13
K
0.30
0.005 0.012
Q
W
12.95 13.45
0.510 0.530
T
0.13
0°
Ċ
Ċ
0.005
0°
Ċ
Ċ
X
U
V
12.95 13.45
Ċ
0.510 0.530
0.016
W
X
0.40
1.6 REF
Ċ
0.063 REF
DETAIL C
Figure 13-4. 44-Lead QFP (Case 824A-01)
Advance Information
140
MC68HC05C9A — Rev. 5.0
Mechanical Specifications
MOTOROLA
Advance Information — MC68HC05C9A
Section 14. Ordering Information
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
14.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
14.2 Introduction
This section contains ordering information for the available package
types.
14.3 MC Order Numbers
Table 14-1 shows the MC order numbers for the available package
types.
Table 14-1. MC Order Numbers
Temperature
Package Type
Order Number
Range
0°C to 70°C
MC68HC05C9AP
MC68HC05C9AMP
MC68HC05C9AB
40-pin plastic dual in-line
package (DIP)
–40°C to 125°C
0°C to 70°C
42-pin shrink dual in-line
package (SDIP)
–40°C to 125°C
0°C to 70°C
MC68HC05C9AMB
MC68HC05C9AFN
MC68HC05C9AMFN
MC68HC05C9AFB
MC68HC05C9AMFB
44-lead plastic-leaded
chip carrier (PLCC)
–40°C to 125°C
0°C to 70°C
44-pin quad flat pack
(QFP)
–40°C to 125°C
1. P = Plastic dual in-line package (PDIP)
2. B = Shrink dual in-line package (SDIP)
3. FN = Plastic-leaded chip carrier (PLCC)
4. FB = Quad flat pack (QFP)
MC68HC05C9A — Rev. 5.0
Advance Information
141
MOTOROLA
Ordering Information
Ordering Information
Advance Information
142
MC68HC05C9A — Rev. 5.0
Ordering Information
MOTOROLA
Advance Information — MC68HC05C9A
Appendix A. MC68HCL05C9A
A.1 Contents
A.2
A.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
A.4
DC Electrical Characeristics . . . . . . . . . . . . . . . . . . . . . . . . . .144
1.8–2.4-Volt Low-Power Output Voltage . . . . . . . . . . . . . .144
1.8–2.4-Volt Input Pullup Current. . . . . . . . . . . . . . . . . . . .144
2.5–3.6-Volt Low-Power Output Voltage . . . . . . . . . . . . . .145
2.6–3.6-Volt Input Pullup Current. . . . . . . . . . . . . . . . . . . .145
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . .146
A.4.1
A.4.2
A.4.3
A.4.4
A.4.5
A.2 Introduction
Appendix A describes the MC68HCL05C9A, a low-power version of the
MC68HC05C9A. The technical data applying to the MC68HC05C9A
applies to the MC68HCL05C9 with the exceptions given in this
appendix.
A.3 Operating Temperature
The data shown here replaces the corresponding data in
12.3 Operating Temperature.
Rating
Symbol
Value
T to T
Unit
Operating temperature range
L
H
T
°C
A
(1)
0 to +70
MC68HCL05C9AP, FN, B, FB
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
MC68HC05C9A — Rev. 5.0
Advance Information
143
MOTOROLA
MC68HCL05C9A
MC68HCL05C9A
A.4 DC Electrical Characeristics
The data in 12.6 5.0-Volt DC Electrical Characteristics and
12.7 3.3-Volt DC Electrical Characteristics applies to the
MC68HCL05C9A with the exceptions given here.
A.4.1 1.8–2.4-Volt Low-Power Output Voltage
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Output high voltage
(I
= –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
V
V
V
–0.3
TCMP, PD7, PD0
V
DD
DD
DD
—
—
—
—
—
—
V
OH
(I
(I
= –0.2 mA) PD5–PD1
–0.3
–0.3
Load
= –0.75 mA) PC7
Load
Output low voltage
(I
= 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, PD7,
Load
V
V
OL
PD5–PD0, TCMP
= 2.0 mA) PC7
—
—
—
—
0.3
0.3
(I
Load
1. V = 1.8–2.4 Vdc
DD
A.4.2 1.8–2.4-Volt Input Pullup Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Input pullup current
PB7–PB0 (with pullup)
I
0.45
1.5
6.5
µA
In
1. V = 1.8–2.4 Vdc
DD
Advance Information
144
MC68HC05C9A — Rev. 5.0
MC68HCL05C9A
MOTOROLA
MC68HCL05C9A
DC Electrical Characeristics
A.4.3 2.5–3.6-Volt Low-Power Output Voltage
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Output high voltage
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
TCMP, PD7, PD0
Load
V
V
V
– 0.3
V
DD
DD
DD
—
—
—
—
—
—
V
OH
– 0.3
– 0.3
(I
(I
= –0.4 mA) PD5–PD1
Load
= –1.5 mA) PC7
Load
Output low voltage
(ILOAD = 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0, PD7,
V
V
OL
PD5–PD0, TCMP
(ILOAD = 5.0 mA) PC7
—
—
—
—
0.3
0.3
1. V = 2.5–3.6 Vdc
DD
A.4.4 2.6–3.6-Volt Input Pullup Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Input pullup current
PB7–PB0 (with pullup)
I
1
5
16
µA
In
1. V = 2.5–3.6 Vdc
DD
MC68HC05C9A — Rev. 5.0
Advance Information
145
MOTOROLA
MC68HCL05C9A
MC68HCL05C9A
A.4.5 Low-Power Supply Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Supply current (4.5–5.5 Vdc @ f
= 2.1 MHz)
= 1.0 MHz)
= 500 kHz)
= 500 kHz)
Bus
Bus
Bus
Bus
(2)
Run
—
—
3.5
1.6
4.25
2.25
mA
mA
(3)
Wait
I
I
I
I
DD
DD
DD
DD
(4)
Stop
—
—
1
2
15
25
µA
µA
25°C
0°C to +70°C (standard)
Supply current (2.4–3.6 Vdc @ f
(2)
Run
—
—
1.00
0.7
1.4
1.0
mA
mA
(3)
Wait
(4)
Stop
—
—
1
1
5
10
µA
µA
25 °C
0 °C to +70 °C (standard)
Supply current (2.5–3.6 Vdc @ f
(2)
Run
—
—
500
300
750
500
µA
µA
(3)
Wait
(4)
Stop
—
—
1
1
5
10
µA
µA
25 °C
0 °C to +70 °C (standard)
Supply current (1.8–2.4 Vdc @ f
(2)
Run
—
—
300
250
600
400
µA
µA
(3)
Wait
(4)
Stop
—
—
1
1
2
5
µA
µA
25 °C
0 °C to +70 °C (standard)
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs,
DD
port B = V , all other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs;
DD
IL
IH
DD
C = 20 pF on OSC2
L
3. Wait I measured using external square wave clock source; all I/O pins configured as inputs, port B = V , all other
DD
DD
inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected
IL
IH
DD
L
DD
linearly by the OSC2 capacitance.
4. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V
IH
DD
Advance Information
146
MC68HC05C9A — Rev. 5.0
MC68HCL05C9A
MOTOROLA
Advance Information — MC68HC05C9A
Appendix B. MC68HSC05C9A
B.1 Contents
B.2
B.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
B.4
B.4.1
B.4.2
DC Electrical Characeristics . . . . . . . . . . . . . . . . . . . . . . . . . .149
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . .149
Input Pullup Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
B.5
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
4.5–5.5-Volt High-Speed Control Timing . . . . . . . . . . . . . .150
2.4–3.6-Volt High-Speed Control Timing . . . . . . . . . . . . . .151
4.5–5.5-Volt High-Speed Control Timing . . . . . . . . . . . . . .152
2.4–3.6-Volt High-Speed SPI Timing . . . . . . . . . . . . . . . . .153
B.5.1
B.5.2
B.5.3
B.5.4
B.2 Introduction
Appendix B describes the MC68HSC05C9A, a high-speed version of the
MC68HC05C9A. The technical data applying to the MC68HC05C9A
applies to the MC68HSC05C9A with the exceptions given in this
appendix.
MC68HC05C9A — Rev. 5.0
Advance Information
MOTOROLA
MC68HSC05C9A
147
MC68HSC05C9A
B.3 Operating Temperature
The data shown here replaces the corresponding data in
12.3 Operating Temperature.
Table B-1. High-Speed Operating Temperature Range
Rating
Symbol
Value
Unit
(1)
T to T
Operating temperature range
L
H
T
°C
0 to +70
–40 to +85
MC68HSC05C9AP, FN, B, FB
MC68HSC05C9ACP, CFN, CB, CFB
A
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
C = Extended temperature range (–40°C to +85°C)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
Advance Information
148
MC68HC05C9A — Rev. 5.0
MC68HSC05C9A
MOTOROLA
MC68HSC05C9A
DC Electrical Characeristics
B.4 DC Electrical Characeristics
The data in 12.6 5.0-Volt DC Electrical Characteristics and
12.7 3.3-Volt DC Electrical Characteristics applies to the
MC68HSC05C9A with the exceptions given here.
B.4.1 High-Speed Supply Current
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Supply current (4.5–5.5 Vdc @ f
= 4.0 MHz)
Bus
(2)
Run
—
—
7.00
2.00
11.0
6.50
mA
mA
(3)
Wait
Stop
I
(4)
DD
—
—
—
1
1.0
7.0
20
40
50
µA
µA
µA
25°C
0°C to 70°C (standard)
–40°C to 85°C (standard)
Supply current (2.4–3.6 Vdc @ f
= 2.0 MHz)
Bus
(2)
Run
—
—
2.50
1.00
4.00
2.00
mA
mA
(3)
Wait
I
(4)
DD
Stop
—
—
—
1
1.0
2.5
8
16
20
µA
µA
µA
25°C
0°C to 70°C (standard)
–40°C to 85°C (standard)
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, port B = V , all
DD
DD
other inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2
IL
IH
DD
L
3. Wait I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all other
DD
DD
inputs V = 0.2 V, V = V –0.2 V; no dc loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected
IL
IH
DD
L
DD
linearly by the OSC2 capacitance
4. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V
IH
DD
B.4.2 Input Pullup Current
Characteristic
Symbol
Min
Typ
Max
Unit
Input pullup current (V = 4.5–5.5 V)
PB7–PB0 (with pullup)
DD
I
5
1
15
60
µA
In
Input pullup current (V = 2.4–3.6 V)
DD
I
5
16
µA
In
PB7–PB0 (with pullup)
MC68HC05C9A — Rev. 5.0
Advance Information
149
MOTOROLA
MC68HSC05C9A
MC68HSC05C9A
B.5 Control Timing
The data in 12.8 5.0-Volt Control Timing and 12.9 3.3-Volt Control
Timing applies to the MC68HSC05C9A with the exceptions given here.
B.5.1 4.5–5.5-Volt High-Speed Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal
External clock
f
—
dc
8.2
8.2
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
4.1
4.1
MHz
Crystal
External clock
OP
t
Cycle time
244
—
100
100
—
ns
ms
ms
cyc
t
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width
Timer
OXOV
t
ILCH
t
t
1.5
RL
cyc
(2)
t
t
4.0
64
RESL
—
—
—
cyc
Resolution
Input capture pulse width
Input capture pulse width
t
or t
l
ns
TH
TL
(3)
t
t
Note
cyc
THT
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
64
—
—
—
ns
ILIH
(4)
t
t
Note
ILIL
cyc
t
or t
OSC1 pulse width
50
ns
OH
OL
1. V = 4.5–5.5 Vdc
DD
2. Because a 2-bit prescaler in the timer must count four internal cycles (t ), this is the limiting minimum factor in determining
cyc
the timer resolution.
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
cyc
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
cyc
Advance Information
150
MC68HC05C9A — Rev. 5.0
MC68HSC05C9A
MOTOROLA
MC68HSC05C9A
Control Timing
B.5.2 2.4–3.6-Volt High-Speed Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal
External Clock
f
—
dc
4.2
4.2
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
2.1
2.1
MHz
Crystal
External clock
OP
t
Cycle time
480
—
—
100
100
—
ns
ms
ms
cyc
t
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width
Timer
OXOV
t
—
ILCH
t
t
1.5
RL
cyc
(2)
t
t
4.0
125
RESL
—
—
—
cyc
Resolution
Input capture pulse width
Input capture pulse width
t
or t
TL
ns
TH
(3)
t
t
Note
cyc
THTL
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
125
—
—
—
ns
ILIH
(4)
t
t
Note
ILIL
cyc
t
or t
OSC1 pulse width
90
ns
OH
OL
1. V = 2.4–3.6 Vdc
DD
2. Because a 2-bit prescaler in the timer must count four internal cycles (t ), this is the limiting minimum factor in determining
cyc
the timer resolution.
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
cyc
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
cyc
MC68HC05C9A — Rev. 5.0
Advance Information
151
MOTOROLA
MC68HSC05C9A
MC68HSC05C9A
B.5.3 4.5–5.5-Volt High-Speed Control Timing
Characteristic(1)
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
4.1
fOP
MHz
Cycle time
1
2
Master
Slave
tcyc(M)
tcyc(S)
2.0
244
—
—
tcyc
ns
Enable lead time
Master
Slave
Note(2)
122
tLead(M)
tLead(S)
—
—
ns
Enable lag time
Master
Slave
Note(2)
366
3
4
5
6
7
tLag(M)
tLag(S)
—
—
ns
ns
ns
ns
ns
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
166
93
—
—
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
166
93
—
—
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
49
49
—
—
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
49
49
—
—
Slave access time (time to data active from
high-impedance state)
8
9
tA
0
61
ns
ns
Slave disable time (hold time to high-impedance state)
tDIS
—
122
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
10
11
12
13
tV(M)
tV(S)
0.25
—
—
122
tcyc(M)
ns
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tcyc(M)
ns
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
50
1.0
ns
µs
Fall time (70% VDD to 20% VDD, CL = 200 pF)
tFM
tFS
—
—
50
1.0
ns
µs
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
1. VDD = 4.5–5.5 Vdc
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
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MC68HSC05C9A
MOTOROLA
MC68HSC05C9A
Control Timing
B.5.4 2.4–3.6-Volt High-Speed SPI Timing
Characteristic(1)
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
dc
0.5
2.1
fOP
MHz
Cycle time
1
2
Master
Slave
tcyc(M)
tcyc(S)
2.0
480
—
—
tcyc
ns
Enable lead time
Master
Slave
Note(2)
240
tLead(M)
tLead(S)
—
—
ns
Enable lag time
Master
Slave
Note(2)
720
3
4
5
6
7
tLag(M)
tLag(S)
—
—
ns
ns
ns
ns
ns
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
—
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
—
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
100
—
—
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
100
—
—
Slave access time (time to data active from
high-impedance state)
8
9
tA
0
120
240
ns
ns
Slave disable time (hold time to high-impedance state)
tDIS
—
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
10
11
12
13
tV(M)
tV(S)
0.25
—
—
240
tcyc(M)
ns
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
—
—
tcyc(M)
ns
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
Fall time (70% VDD to 20% VDD, CL = 200 pF)
tFM
tFS
—
—
100
2.0
ns
µs
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
1. V = 2.4–3.6 Vdc
DD
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C9A — Rev. 5.0
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MC68HSC05C9A
MC68HSC05C9A
Advance Information
154
MC68HC05C9A — Rev. 5.0
MC68HSC05C9A
MOTOROLA
Advance Information — MC68HC05C9A
Appendix C. Self-Check Mode
C.1 Contents
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
C.3 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
C.3.1
C.3.2
Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
C.2 Introduction
This appendix describes the self-check mode.
MC68HC05C9A — Rev. 5.0
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155
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Self-Check Mode
Self-Check Mode
C.3 Self-Check Mode
Self-check mode is entered upon the rising edge of RESET if the IRQ pin
is at Vtst and the TCAP pin is at logic 1.
C.3.1 Self-Check Tests
The self-check read-only memory (ROM) at mask ROM location
$3F00–$3FEF determines if the microcontroller unit (MCU) is
functioning properly.
These tests are performed:
1. Input/output (I/O) — Functional test of ports A, B, and C
2. Random-access memory (RAM) — Counter test for each RAM
byte
3. Timer — Test of counter register and OCF bit
4. Serial communications interface (SCI) — Transmission test;
checks for RDRF, TDRE, TC, and FE flags
5. ROM — Exclusive OR with odd ones parity result
6. Serial peripheral interface (SPI) — Transmission test; checks for
SPIF and WCOL flags
The self-check circuit is shown in Figure C-1.
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MC68HC05C9A — Rev. 5.0
Self-Check Mode
MOTOROLA
Self-Check Mode
Self-Check Mode
V
V
DD
DD
10 V
V
DD
MC34064
MC68HC05C9A
4.7 kΩ
RESET
V
DD
1
2
3
4
5
40
39
38
37
36
IRQ
NC
OSC1
OSC2
TCAP
PD7
4 MHz
PA7
PA6
10 MΩ
20 pF
V
DD
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
TCMP
6
35
34
33
32
31
30
29
28
20 pF
10K
PD5/SS
7
1 MΩ
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
8
9
10
11
12
13
PC0
PC1
PC2
PB2
PB3
14
15
27
26
CMOS
BUFFER
(MC74HC125)
PB4
PB5
PB6
PB7
PC3
16
17
18
19
20
25
24
PC4
PC5
PC6
PC7
23
22
21
V
SS
V
DD
Notes:
1. VDD = 5.0 V
2. TCMP = NC
Figure C-1. Self-Check Circuit Schematic
MC68HC05C9A — Rev. 5.0
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Self-Check Mode
Self-Check Mode
C.3.2 Self-Check Results
Table C-1 shows the LED codes that indicate self-check test results.
Table C-1. Self-Check Circuit LED Codes
PC3
Off
Off
Off
Off
Off
Off
PC2
On
On
On
Off
Off
Off
PC1
On
Off
Off
On
On
Off
PC0
Off
On
Off
On
Off
On
Remarks
I/O failure
RAM failure
Timer failure
SCI failure
ROM failure
SPI failure
Flashing
All others
No failure
Device failure
Perform these steps to activate the self-check tests:
1. Apply 10 V (2 x VDD) to the IRQ pin.
2. Apply a logic 1 to the TCAP pin.
3. Apply a logic 0 to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR), or
for a time, tRL, for any other reset. For the value of tRL, see 12.8 5.0-Volt
Control Timing and 12.9 3.3-Volt Control Timing.
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MC68HC05C9A — Rev. 5.0
Self-Check Mode
MOTOROLA
Advance Information — MC68HC05C9A
Appendix D. M68HC05Cx Family Feature Comparisons
Refer to Table D-1 for a comparison of the features for all the
M68HC05C Family members.
MC68HC05C9A — Rev. 5.0
Advance Information
159
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M68HC05Cx Family Feature Comparisons
M68HC05Cx Family Feature Comparisons
Advance Information
MC68HC05C9A
— Rev. 5.0
160
M68HC05Cx Family Feature Comparisons
MOTOROLA
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MC68HC05C9A/D
REV 5
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