MC68HSR705J1ACDWR2 [MOTOROLA]
8-BIT, OTPROM, 2.1MHz, MICROCONTROLLER, PDSO20, SOIC-20;
| 型号： | MC68HSR705J1ACDWR2 |
| 厂家： | 
MOTOROLA |
| 描述： | 8-BIT, OTPROM, 2.1MHz, MICROCONTROLLER, PDSO20, SOIC-20 可编程只读存储器 时钟 光电二极管 外围集成电路 |
| 文件： | 总162页 (文件大小：1517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC705J1A/D
Rev. 3.0
HC 5
MC68HC705J1A
MC68HRC705J1A
MC68HSC705J1A
MC68HSR705J1A
HCMOS Mic roc ontrolle r Units
TECHNICAL DATA
Technical Data
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
© Motorola, Inc., 1999
Technical Data
2
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data — MC68HC705J1A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .19
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .43
Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . .67
Section 5. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .77
Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . .85
Section 7. Computer Operating Properly
(COP) Module . . . . . . . . . . . . . . . . . . . . . . . . .95
Section 8. External Interrupt Module (IRQ). . . . . . . . . . .99
Section 9. Multifunction Timer Module . . . . . . . . . . . . .107
Section 10. Electrical Specifications. . . . . . . . . . . . . . .115
Section 11. Mechanical Specifications . . . . . . . . . . . . .129
Section 12. Ordering Information . . . . . . . . . . . . . . . . .133
Appendix A. MC68HRC705J1A . . . . . . . . . . . . . . . . . . .135
Appendix B. MC68HSC705J1A . . . . . . . . . . . . . . . . . . .139
Appendix C. MC68HSR705J1A . . . . . . . . . . . . . . . . . . .143
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
List of Sections
3
List of Sections
Technical Data
4
MC68HC705J1A — Rev. 3.0
MOTOROLA
List of Sections
Technical Data — MC68HC705J1A
Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5
1.5.1
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DD SS
1.5.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .26
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.2.1
1.5.2.2
1.5.2.3
1.5.2.4
1.6
1.7
1.8
1.9
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IRQ/V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PP
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .33
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Table of Contents
5
Table of Contents
2.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM/OTPROM Programming. . . . . . . . . . . . . . . . . . . . .36
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .37
EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.6.1
2.6.2
2.6.3
2.7
2.8
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . .41
Section 3. Central Processor Unit (CPU)
3.1
3.2
3.3
3.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.5
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.6.1
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . .53
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .54
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . .55
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .57
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.6.1.1
3.6.1.2
3.6.1.3
3.6.1.4
3.6.1.5
3.6.1.6
3.6.1.7
3.6.1.8
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.2.5
Technical Data
6
MC68HC705J1A — Rev. 3.0
Table of Contents
MOTOROLA
Table of Contents
3.7
3.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Section 4. Resets and Interrupts
4.1
4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1
4.3.2
4.3.3
4.3.4
4.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .74
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.4.1
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
Section 5. Low-Power Modes
5.1
5.2
5.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.4
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .79
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Table of Contents
7
Table of Contents
Section 6. Parallel Input/Output (I/O) Ports
6.1
6.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .88
Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . .90
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .91
Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.4.1
6.4.2
6.4.3
6.5
6.6
5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .93
3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .93
Section 7. Computer Operating Properly (COP) Module
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.2
7.3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .96
COP Watchdog Timeout Period. . . . . . . . . . . . . . . . . . . . . .96
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .96
7.3.1
7.3.2
7.3.3
7.4
7.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.6
7.6.1
7.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Technical Data
8
MC68HC705J1A — Rev. 3.0
Table of Contents
MOTOROLA
Table of Contents
Section 8. External Interrupt Module (IRQ)
8.1
8.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.3
8.3.1
8.3.2
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .102
PP
8.4
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .104
8.5
8.5.1
8.5.2
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
5.0-Volt External Interrupt Timing Characteristics . . . . . . .105
3.3-Volt External Interrupt Timing Characteristics . . . . . . .105
Section 9. Multifunction Timer Module
9.1
9.2
9.3
9.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.5
9.5.1
9.5.2
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Timer Status and Control Register. . . . . . . . . . . . . . . . . . .110
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.6
9.6.1
9.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Section 10. Electrical Specifications
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .117
10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Table of Contents
9
Table of Contents
10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119
10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .120
10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .124
10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Section 11. Mechanical Specifications
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11.3 Plastic Dual In-Line Package (Case 738). . . . . . . . . . . . . . . .130
11.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .130
11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . .131
Section 12. Ordering Information
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Appendix A. MC68HRC705J1A
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .136
A.4 Typical Internal Operating Frequency
for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .138
Technical Data
10
MC68HC705J1A — Rev. 3.0
Table of Contents
MOTOROLA
Table of Contents
Appendix B. MC68HSC705J1A
B.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .140
B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .140
B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .142
Appendix C. MC68HSR705J1A
C.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . .143
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . .144
C.5 RC Oscillator Connections (No External Resistor) . . . . . . . . .145
C.6 Typical Internal Operating Frequency versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .147
Index
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Table of Contents
11
Table of Contents
Technical Data
12
MC68HC705J1A — Rev. 3.0
MOTOROLA
Table of Contents
Technical Data — MC68HC705J1A
List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .24
Crystal Connections with
Oscillator Internal Resistor Mask Option. . . . . . . . . . . . .26
1-5
1-6
1-7
1-8
Crystal Connections without
Oscillator Internal Resistor Mask Option. . . . . . . . . . . . .26
Ceramic Resonator Connections
with Oscillator Internal Resistor Mask Option . . . . . . . . .27
Ceramic Resonator Connections
without Oscillator Internal Resistor Mask Option. . . . . . .27
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . .28
2-1
2-2
2-3
2-4
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EPROM Programming Register (EPROG). . . . . . . . . . . . . .37
Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . .39
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . .48
4-1
4-2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .69
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
List of Figures
13
List of Figures
Figure
Title
Page
4-3
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4-4
4-5
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .73
4-6
4-7
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5-1
5-2
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .83
Stop/Halt/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
Parallel I/O Port Register Summary . . . . . . . . . . . . . . . . . . .86
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .87
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .88
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .89
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .90
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .91
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .92
7-1
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8-1
8-2
IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .100
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8-3
8-4
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .104
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .105
9-1
9-2
9-3
9-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . .108
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Timer Status and Control Register (TSCR) . . . . . . . . . . . .110
Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . .112
10-1
PA0–PA7, PB0–PB5 Typical High-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .121
Technical Data
14
MC68HC705J1A — Rev. 3.0
List of Figures
MOTOROLA
List of Figures
Figure
Title
Page
10-2
PA0–PA3, PB0–PB5 Typical Low-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .121
PA4–PA7 Typical Low-Side Driver Characteristics . . . . . .122
10-3
10-4
Typical Operating I (25°C) . . . . . . . . . . . . . . . . . . . . . . .123
DD
10-5
10-6
10-7
10-8
10-9
Typical Wait Mode I (25°C) . . . . . . . . . . . . . . . . . . . . . .123
DD
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .126
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .126
Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .127
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
A-1
A-2
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . .136
Typical Internal Operating Frequency
for Various V at 25°C — RC Oscillator
DD
Option Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
B-1
B-2
Typical High-Speed Operating I (25°C) . . . . . . . . . . . . .140
DD
Typical High-Speed Wait Mode I (25°C) . . . . . . . . . . . .141
DD
C-1
Typical Internal Operating Frequency
at 25°C for High-Speed RC Oscillator Option . . . . . . . .144
RC Oscillator Connections (No External Resistor). . . . . . .145
Typical Internal Operating Frequency
C-2
C-3
versus Temperature (OSCRES Bit = 1) . . . . . . . . . . . .146
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
List of Figures
15
List of Figures
Technical Data
16
MC68HC705J1A — Rev. 3.0
MOTOROLA
List of Figures
Technical Data — MC68HC705J1A
List of Tables
Table
Title
Page
1-1
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . .53
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .54
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .56
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .57
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4-1
4-2
4-3
4-4
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
External Interrupt Timing (V = 5.0 Vdc) . . . . . . . . . . . . . . .73
DD
External Interrupt Timing (V = 3.3 Vdc) . . . . . . . . . . . . . . .73
DD
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .75
6-1
6-2
9-1
Port A Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Port B Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . .112
12-1
A-1
Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
MC68HRC705J1A (RC Oscillator Option)
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
B-1
C-1
MC68HSC705J1A (High Speed) Order Numbers . . . . . . .142
MC68HSR705J1A (High-Speed RC Oscillator
Option) Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . .147
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
List of Tables
17
List of Tables
Technical Data
18
MC68HC705J1A — Rev. 3.0
MOTOROLA
List of Tables
Technical Data — MC68HC705J1A
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5
1.5.1
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DD SS
1.5.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .26
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.2.1
1.5.2.2
1.5.2.3
1.5.2.4
1.6
1.7
1.8
1.9
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
IRQ/V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PP
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
General Description
19
General Description
1.2 Introduction
The MC68HC705J1A is a member of Motorola’s low-cost,
high-performance M68HC05 Family of 8-bit microcontroller units
(MCUs). The M68HC05 Family is based on the customer-specified
integrated circuit (CSIC) design strategy. All MCUs in the family use the
popular M68HC05 central processor unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
On-chip memory of the MC68HC705J1A includes 1240 bytes of
erasable, programmable read-only memory (EPROM). In packages
without the transparent window for EPROM erasure, the 1240 EPROM
bytes serve as one-time programmable read-only memory (OTPROM).
The MC68HRC705J1A is a resistor-capacitor (RC) oscillator mask
option version of the MC68HC705J1A and is discussed in Appendix A.
MC68HRC705J1A.
A high-speed version of the MC68HC705J1A, the MC68HSC705J1A, is
discussed in Appendix B. MC68HSC705J1A.
The MC68HSR705J1A, discussed in Appendix C. MC68HSR705J1A,
is a high-speed version of the MC68HRC705J1A.
A functional block diagram of the MC68HC705J1A is shown in
Figure 1-1.
Technical Data
20
MC68HC705J1A — Rev. 3.0
General Description
MOTOROLA
General Description
Introduction
OSC1
OSC2
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
INTERNAL
OSCILLATOR
DIVIDE
BY 2
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
CPU CONTROL
CPU REGISTERS
ALU
RESET
IRQ/V
PB5
PB4
PB3
PB2
PB1
PB0
68HC05 CPU
PP
ACCUMULATOR
INDEX REGISTER
STK PTR
0 0 0 0 0 0 0 0 1 1
PROGRAM COUNTER
CONDITION CODE
PA7*
PA6*
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
1 1 1 H I N Z C
REGISTER
STATIC RAM (SRAM) — 64 BYTES
USER EPROM — 1240 BYTES
*10-mA sink capability
**External interrupt capability
MASK OPTION REGISTER (EPROM)
Figure 1-1. Block Diagram
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
21
General Description
General Description
1.3 Features
Features of the MC68HC705J1A include:
• Peripheral modules:
– 15-stage multifunction timer
– Computer operating properly (COP) watchdog
• 14 bidirectional input/output (I/O) lines, including:
– 10-mA sink capability on four I/O pins
– Mask option register (MOR) and software programmable
pulldowns on all I/O pins
– MOR selectable interrupt on four I/O pins, a keyboard scan
feature
• MOR selectable sensitivity on external interrupt (edge- and
level-sensitive or edge-sensitive only)
• On-chip oscillator with connections for:
– Crystal
– Ceramic resonator
– Resistor-capacitor (RC) oscillator
– External clock
• 1240 bytes of EPROM/OTPROM, including eight bytes for user
vectors
• 64 bytes of user random-access memory (RAM)
• Memory-mapped I/O registers
• Fully static operation with no minimum clock speed
• Power-saving stop, halt, wait, and data-retention modes
• External interrupt mask bit and acknowledge bit
• Illegal address reset
• Internal steering diode and pullup resistor from RESET pin to V
DD
Technical Data
22
MC68HC705J1A — Rev. 3.0
MOTOROLA
General Description
General Description
Programmable Options
1.4 Programmable Options
The options in Table 1-1 are programmable in the mask option register
(MOR).
Table 1-1. Programmable Options
Feature
Option
COP watchdog timer
Enabled or disabled
External interrupt triggering
Port A IRQ pin interrupts
Port pulldown resistors
STOP instruction mode
Edge-sensitive only or edge- and level-sensitive
Enabled or disabled
Enabled or disabled
Stop mode or halt mode
Crystal oscillator internal resistor Enabled or disabled
EPROM security
Enabled or disabled
Enabled or disabled
Short oscillator delay counter
1.5 Pin Assignments
Figure 1-2 shows the MC68HC705J1A pin assignments.
1.5.1 V and V
DD
SS
V
and V are the power supply and ground pins. The MCU operates
SS
DD
from a single power supply.
Very fast signal transitions occur on the MCU pins, placing high,
short-duration current demands on the power supply. To prevent noise
problems, take special care as Figure 1-3 shows, by placing the bypass
capacitors as close as possible to the MCU. C2 is an optional bulk
current bypass capacitor for use in applications that require the port pins
to source high current levels.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
General Description
23
General Description
OSC1
OSC2
PB5
RESET
IRQ/V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PP
PA0
PB4
PA1
PB3
PB2
PB1
PB0
PA2
PA3
PA4
PA5
PA6
PA7
V
DD
V
SS
Figure 1-2. Pin Assignments
V+
V
DD
V
DD
C2
C1
+
C1
0.1 µF
MCU
C2
V
SS
V
SS
Figure 1-3. Bypassing Layout Recommendation
Technical Data
24
MC68HC705J1A — Rev. 3.0
MOTOROLA
General Description
General Description
Pin Assignments
1.5.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by any of these:
1. Crystal (See Figure 1-4 and Figure 1-5.)
2. Ceramic resonator (See Figure 1-6 and Figure 1-7.)
3. Resistor/capacitor (RC) oscillator (Refer to Appendix A.
MC68HRC705J1A and Appendix C. MC68HSR705J1A.)
4. External clock signal (See Figure 1-8.)
The frequency, f , of the oscillator or external clock source is divided
osc
by two to produce the internal operating frequency, f .
op
1.5.2.1 Crystal Oscillator
Figure 1-4 and Figure 1-5 show a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable startup and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances.
To minimize output distortion, mount the crystal and capacitors as close
as possible to the pins. An internal startup resistor of approximately
2 MΩ is provided between OSC1 and OSC2 for the crystal oscillator as
a programmable mask option.
NOTE: Use an AT-cut crystal and not an AT-strip crystal because the MCU can
overdrive an AT-strip crystal.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
25
General Description
General Description
V
SS
MCU
XTAL
C3
OSC1
OSC2
XTAL
C4
C3
27 pF
C4
27 pF
V
DD
C2 C1
V
SS
Figure 1-4. Crystal Connections with
Oscillator Internal Resistor Mask Option
V
SS
C3
MCU
OSC1
OSC2
R
XTAL
R
10 MΩ
C4
V
DD
XTAL
C3
27 pF
C4
27 pF
C2 C1
V
SS
Figure 1-5. Crystal Connections without
Oscillator Internal Resistor Mask Option
1.5.2.2 Ceramic Resonator Oscillator
To reduce cost, use a ceramic resonator instead of the crystal. The
circuits shown in Figure 1-6 and Figure 1-7 show ceramic resonator
circuits. Follow the resonator manufacturer’s recommendations, as the
resonator parameters determine the external component values
required for maximum stability and reliable starting. The load
capacitance values used in the oscillator circuit design should include all
stray capacitances.
Technical Data
26
MC68HC705J1A — Rev. 3.0
General Description
MOTOROLA
General Description
Pin Assignments
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2 as
a programmable mask option.
V
SS
MCU
C3
OSC1
OSC2
CERAMIC
RESONATOR
C4
C3
27 pF
C4
27 pF
V
DD
C2 C1
V
SS
Figure 1-6. Ceramic Resonator Connections
with Oscillator Internal Resistor Mask Option
V
SS
C3
C4
MCU
OSC1
OSC2
R
R
10 MΩ
V
DD
CERAMIC
RESONATOR
C2 C1
C3
27 pF
C4
27 pF
V
SS
Figure 1-7. Ceramic Resonator Connections
without Oscillator Internal Resistor Mask Option
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
27
General Description
General Description
1.5.2.3 RC Oscillator
Refer to Appendix A. MC68HRC705J1A and Appendix C.
MC68HSR705J1A.
1.5.2.4 External Clock
An external clock from another complementary metal-oxide
semiconductor (CMOS)-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in
Figure 1-8. This configuration is possible regardless of whether the
crystal/ceramic resonator or the RC oscillator is enabled.
MCU
EXTERNAL
CMOS CLOCK
Figure 1-8. External Clock Connections
1.6 RESET
Applying a logic 0 to the RESET pin forces the MCU to a known startup
state. An internal reset also pulls the RESET pin low. An internal resistor
to V pulls the RESET pin high. A steering diode between the RESET
DD
and V pins discharges any RESET pin voltage when power is
DD
removed from the MCU. The RESET pin contains an internal Schmitt
trigger to improve its noise immunity as an input. Refer to Section 4.
Resets and Interrupts for more information.
Technical Data
28
MC68HC705J1A — Rev. 3.0
General Description
MOTOROLA
General Description
IRQ/V
PP
1.7 IRQ/VPP
The external interrupt/programming voltage pin (IRQ/V ) drives the
PP
asynchronous IRQ interrupt function of the CPU. Additionally, it is used
to program the user EPROM and mask option register. (See Section 2.
Memory and Section 8. External Interrupt Module (IRQ).)
The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/V input requires an
PP
external resistor to V for wired-OR operation. If the IRQ/V pin is not
DD
PP
used, it must be tied to the V supply.
DD
The IRQ/V pin contains an internal Schmitt trigger as part of its input
PP
to improve noise immunity. The voltage on this pin should not exceed
V
except when the pin is being used for programming the EPROM.
DD
NOTE: The mask option register can enable the PA0–PA3 pins to function as
external interrupt pins.
1.8 PA0–PA7
These eight input/output (I/O) lines comprise port A, a general-purpose,
bidirectional I/O port. See Section 8. External Interrupt Module (IRQ)
for information on PA0–PA3 external interrupts.
1.9 PB0–PB5
These six I/O lines comprise port B, a general-purpose, bidirectional I/O
port.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
General Description
29
General Description
Technical Data
30
MC68HC705J1A — Rev. 3.0
MOTOROLA
General Description
Technical Data — MC68HC705J1A
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .33
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.6
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM/OTPROM Programming. . . . . . . . . . . . . . . . . . . . .36
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .37
EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.6.1
2.6.2
2.6.3
2.7
2.8
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . .41
2.2 Introduction
This section describes the organization of the on-chip memory
consisting of:
• 1232 bytes of user erasable, programmable read-only memory
(EPROM), plus eight bytes for user vectors
• 64 bytes of user random-access memory (RAM)
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Memory
31
Memory
2.3 Memory Map
Port A Data Register (PORTA)
Port B Data Register (PORTB)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
↓
Unimplemented
Data Direction Register A (DDRA)
Data Direction Register B (DDRB)
Unimplemented
Timer Status and Control Register (TSCR)
Timer Control Register (TCR)
$0000
IRQ Status and Control Register (ISCR)
I/O Registers
32 Bytes
↓
$001F
$0020
↓
Unimplemented
$000F
$0010
$0011
$0012
↓
Unimplemented
160 Bytes
Pulldown Register Port A (PDRA)
Pulldown Register Port B (PDRB)
$00BF
$00C0
↓
RAM
64 Bytes
Unimplemented
EPROM Programming Register (EPROG)
Unimplemented
$00FF
$0100
↓
$0017
$0018
$0019
↓
Unimplemented
512 Bytes
$02FF
$0300
↓
$001E
$001F
EPROM
1232 Bytes
Reserved
$07CF
$07D0
↓
(1)
COP Register (COPR)
$07F0
$07F1
$07F2
↓
Unimplemented
30 Bytes
Mask Option Register (MOR)
$07ED
$07EE
$07EF
$07F0
↓
Reserved
Test ROM
2 Bytes
$07F7
$07F8
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
Timer Interrupt Vector High
Timer Interrupt Vector Low
External Interrupt Vector High
External Interrupt Vector Low
Software Interrupt Vector High
Software Interrupt Vector Low
Reset Vector High
Registers and EPROM
16 Bytes
$07FF
Reset Vector Low
(1) Writing to bit 0 of $07F0 clears the computer
operating properly (COP) watchdog.
Figure 2-1. Memory Map
Technical Data
32
MC68HC705J1A — Rev. 3.0
MOTOROLA
Memory
Memory
Input/Output Register Summary
2.4 Input/Output Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
(PORTA) Write:
See page 87.
Reset:
Read:
Unaffected by reset
PB4 PB3
Unaffected by reset
0
0
Port B Data Register
PB5
PB2
PB1
PB0
$0001
$0002
$0003
(PORTB) Write:
See page 90.
Reset:
Unimplemented
Unimplemented
Read:
Data Direction Register A
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
$0004
(DDRA) Write:
See page 88.
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
Data Direction Register B
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
$0005
$0006
$0007
(DDRB) Write:
See page 91.
Reset:
0
0
0
0
0
0
0
0
Unimplemented
Unimplemented
Read: TOF
RTIF
0
0
TOFR
0
0
RTIFR
0
Timer Status and Control
TOIE
0
RTIE
RT1
1
RT0
1
$0008
Register (TSCR) Write:
See page 110.
Reset:
0
0
= Unimplemented
R = Reserved
Figure 2-2. I/O Register Summary (Sheet 1 of 3)
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
33
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Timer Counter Register
$0009
$000A
(TCR) Write:
See page 112.
Reset:
Read:
0
IRQE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQF
IRQ Status and Control
Register (ISCR) Write:
R
0
IRQR
0
See page 104.
Reset:
0
0
0
0
0
$000B
↓
Unimplemented
Unimplemented
$000F
Read:
Pulldown Register A
$0010
$0011
(PDRA) Write: PDIA7
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
See page 89.
Reset:
Read:
0
Pulldown Register B
(PDRB) Write:
See page 92.
PDIB5
0
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
0
PDIB0
0
Reset:
0
0
$0012
↓
Unimplemented
Unimplemented
$0017
Read:
0
0
0
R
0
0
R
0
0
0
R
0
EPROM Programming
ELAT
0
MPGM
0
EPGM
0
$0018
Register (EPROG) Write:
R
See page 37.
Reset:
0
= Unimplemented
R = Reserved
Figure 2-2. I/O Register Summary (Sheet 2 of 3)
Technical Data
34
MC68HC705J1A — Rev. 3.0
MOTOROLA
Memory
Memory
RAM
Addr.
$0019
↓
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
$001E
Unimplemented
Reserved
$001F
$07F0
$07F1
R
R
R
R
R
R
R
R
Read:
COP Register
(COPR) Write:
See page 97.
COPC
0
Reset:
Read:
Mask Option Register
SOSCD EPMSEC OSCRES SWAIT
SWPDI
0
PIRQ
0
LEVEL COPEN
(MOR) Write:
See page 39.
Reset:
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
2.5 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM
and the stack RAM. Before processing an interrupt, the central
processor unit (CPU) uses five bytes of the stack to save the contents of
the CPU registers. During a subroutine call, the CPU uses two bytes of
the stack to store the return address. The stack pointer decrements
when the CPU stores a byte on the stack and increments when the CPU
retrieves a byte from the stack.
NOTE: Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
35
Memory
Memory
2.6 EPROM/OTPROM
A microcontroller unit (MCU) with a quartz window has 1240 bytes of
erasable, programmable ROM (EPROM). The quartz window allows
EPROM erasure with ultraviolet light.
NOTE: Keep the quartz window covered with an opaque material except when
programming the MCU. Ambient light can affect MCU operation.
In an MCU without the quartz window, the EPROM cannot be erased
and serves as 1240 bytes of one-time programmable ROM (OTPROM).
These addresses are user EPROM/OTPROM locations:
• $0300–$07CF
• $07F8–$07FF, used for user-defined interrupt and reset vectors
The computer operating properly (COP) register (COPR) is an
EPROM/OTPROM location at address $07F0.
The mask option register (MOR) is an EPROM/OTPROM location at
address $07F1.
2.6.1 EPROM/OTPROM Programming
The two ways to program the EPROM/OTPROM are:
1. Manipulating the control bits in the EPROM programming register
to program the EPROM/OTPROM on a byte-by-byte basis
2. Programming the EPROM/OTPROM with the M68HC705J
in-circuit simulator (M68HC705JICS) available from Motorola
Technical Data
36
MC68HC705J1A — Rev. 3.0
Memory
MOTOROLA
Memory
EPROM/OTPROM
2.6.2 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM.
Address: $0018
Bit 7
0
6
0
5
0
4
0
3
2
ELAT
0
1
MPGM
0
Bit 0
EPGM
0
Read:
Write:
Reset:
0
R
0
R
0
R
0
R
0
0
= Unimplemented
R = Reserved
Figure 2-3. EPROM Programming Register (EPROG)
ELAT — EPROM Bus Latch Bit
This read/write bit latches the address and data buses for
EPROM/OTPROM programming. Clearing the ELAT bit automatically
clears the EPGM bit. EPROM/OTPROM data cannot be read while
the ELAT bit is set. Reset clears the ELAT bit.
1 = Address and data buses configured for EPROM/OTPROM
programming the EPROM
0 = Address and data buses configured for normal operation
MPGM — MOR Programming Bit
This read/write bit applies programming power from the IRQ/V pin
PP
to the mask option register. Reset clears MPGM.
1 = Programming voltage applied to MOR
0 = Programming voltage not applied to MOR
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/V pin to the
PP
EPROM. To write the EPGM bit, the ELAT bit must be set already.
Reset clears EPGM.
1 = Programming voltage (IRQ/V pin) applied to EPROM
PP
0 = Programming voltage (IRQ/V pin) not applied to EPROM
PP
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Memory
37
Memory
NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and clears EPGM. ELAT must be set first by a separate
instruction.
Bits [7:3] — Reserved
Take these steps to program a byte of EPROM/OTPROM:
1. Apply the programming voltage, V , to the IRQ/V pin.
PP
PP
2. Set the ELAT bit.
3. Write to any EPROM/OTPROM address.
4. Set the EPGM bit and wait for a time, t
5. Clear the ELAT bit.
.
EPGM
2.6.3 EPROM Erasing
The erased state of an EPROM bit is logic 0. Erase the EPROM by
2
exposing it to 15 Ws/cm of ultraviolet light with a wave length of
2537 angstroms. Position the ultraviolet light source one inch from the
EPROM. Do not use a shortwave filter.
2.7 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls these options:
• COP watchdog (enable or disable)
• External interrupt pin triggering (edge-sensitive only or edge- and
level-sensitive)
• Port A external interrupts (enable or disable)
• Port pulldown resistors (enable or disable)
• STOP instruction (stop mode or halt mode)
• Crystal oscillator internal resistor (enable or disable)
• EPROM security (enable or disable)
• Short oscillator delay (enable or disable)
Technical Data
38
MC68HC705J1A — Rev. 3.0
Memory
MOTOROLA
Memory
Mask Option Register
Take these steps to program the mask option register:
1. Apply the programming voltage, V , to the IRQ/V pin.
PP
PP
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, t
4. Clear the MPGM bit.
.
MPGM
5. Reset the MCU.
Address: $07F1
Bit 7
6
5
4
3
SWPDI
0
2
PIRQ
0
1
Bit 0
Read:
Write:
Reset:
SOSCD EPMSEC OSCRES SWAIT
LEVEL COPEN
0
0
0
0
0
0
Figure 2-4. Mask Option Register (MOR)
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 t . Setting SOSCD enables a short oscillator stabilization
cyc
delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Security Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Internal Resistor Bit
The OSCRES bit enables a 2-MΩ internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE: Program the OSCRES bit to logic 0 in devices using RC oscillators.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
39
Memory
Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bit is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MCU enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 t occurs after
cyc
exiting halt mode.
1 = Halt mode enabled
0 = Halt mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devices. The SWPDI bit overrides the pulldown inhibit bits in the port
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sensitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
Technical Data
40
MC68HC705J1A — Rev. 3.0
Memory
MOTOROLA
Memory
EPROM Programming Characteristics
2.8 EPROM Programming Characteristics
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Programming voltage
V
16.0
16.5
17.0
V
PP
IRQ/V
PP
Programming current
IRQ/V
I
—
3.0
10.0
mA
ms
PP
PP
Programming time
Per array byte
MOR
t
EPGM
4
4
—
—
—
—
t
MPGM
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, T = –40°C to +105°C
A
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
41
Memory
Memory
Technical Data
42
MC68HC705J1A — Rev. 3.0
MOTOROLA
Memory
Technical Data — MC68HC705J1A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2
3.3
3.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.5
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.6.1
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . .53
Read Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .54
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . .55
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .57
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
3.6.1.1
3.6.1.2
3.6.1.3
3.6.1.4
3.6.1.5
3.6.1.6
3.6.1.7
3.6.1.8
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.2.5
3.7
3.8
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Central Processor Unit (CPU)
43
Central Processor Unit (CPU)
3.2 Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations. See Figure 3-1.
Features include:
• 2.1-MHz bus frequency
• 8-bit accumulator
• 8-bit index register
• 11-bit program counter
• 6-bit stack pointer
• Condition code register (CCR) with five status flags
• 62 instructions
• Eight addressing modes
• Power-saving stop, wait, halt, and data-retention modes
3.3 CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
3.4 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
Technical Data
44
MC68HC705J1A — Rev. 3.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Arithmetic/Logic Unit
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
7
7
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
ACCUMULATOR (A)
0
0
0
INDEX REGISTER (X)
15 14 13 12 11 10
9
0
8
0
7
1
6
1
0
0
0
0
0
0
STACK POINTER (SP)
15 14 13 12 11 10
9
8
7
6
0
0
0
0
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
1
6
1
5
1
4
3
I
2
1
0
H
N
Z
C
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
45
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.5 CPU Registers
The M68HC05 CPU contains five registers that control and monitor
microcontroller unit (MCU) operation:
• Accumulator
• Index register
• Stack pointer
• Program counter
• Condition code register
CPU registers are not memory mapped.
3.5.1 Accumulator
The accumulator (A) is a general-purpose 8-bit register. The CPU uses
the accumulator to hold operands and results of ALU operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.5.2 Index Register
In the indexed addressing (X) modes, the CPU uses the byte in the index
register to determine the conditional address of the operand. The index
register also can serve as a temporary storage location or a counter.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
Technical Data
46
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
3.5.3 Stack Pointer
The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset or after the reset stack
pointer instruction (RSP), the stack pointer is preset to $00FF. The
address in the stack pointer decrements after a byte is stacked and
increments before a byte is unstacked.
Bit
Bit
0
15 14 13 12 11 10
9
0
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
= Unimplemented
Figure 3-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Central Processor Unit (CPU)
47
Central Processor Unit (CPU)
3.5.4 Program Counter
The program counter (PC) is a 16-bit register that contains the address
of the next instruction or operand to be fetched. The five most significant
bits of the program counter are ignored and appear as 00000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
Bit
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
Loaded with vector from $07FE and $07FF
Figure 3-5. Program Counter (PC)
3.5.5 Condition Code Register
The condition code register (CCR) is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Bit 7
1
6
1
5
1
4
H
U
3
I
2
N
U
1
Z
U
Bit 0
C
Read:
Write:
Reset:
1
1
1
1
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
Technical Data
48
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
CPU Registers
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD (add without carry) or ADC
(add with carry) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Normally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return-from-interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result
of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Central Processor Unit (CPU)
49
Central Processor Unit (CPU)
3.6 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes.
3.6.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
3.6.1.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
3.6.1.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
Technical Data
50
MC68HC705J1A — Rev. 3.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
3.6.1.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
3.6.1.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
3.6.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or input/output
(I/O) location.
3.6.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE).
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Central Processor Unit (CPU)
51
Central Processor Unit (CPU)
The k value is typically in the index register, and the address of the
beginning of the table is in the byte following the opcode.
3.6.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
3.6.1.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset because the assembler determines the proper offset
and verifies that it is within the span of the branch.
Technical Data
52
MC68HC705J1A — Rev. 3.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set
3.6.2 Instruction Types
The MCU instructions fall into these five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
3.6.2.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 3-1. Register/Memory Instructions
Instruction
Add memory byte and carry bit to accumulator
Add memory byte to accumulator
AND memory byte with accumulator
Bit test accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare accumulator
CMP
CPX
EOR
LDA
Compare index register with memory byte
EXCLUSIVE OR accumulator with memory byte
Load accumulator with memory byte
Load index register with memory byte
Multiply
LDX
MUL
ORA
SBC
STA
OR accumulator with memory byte
Subtract memory byte and carry bit from accumulator
Store accumulator in memory
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
53
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.6.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write instructions on registers with write-only
bits.
Table 3-2. Read-Modify-Write Instructions
Instruction
Arithmetic shift left (same as LSL)
Arithmetic shift right
Mnemonic
ASL
ASR
(1)
Bit clear
BCLR
(1)
Bit set
BSET
Clear register
CLR
COM
DEC
INC
Complement (one’s complement)
Decrement
Increment
Logical shift left (same as ASL)
Logical shift right
LSL
LSR
NEG
ROL
ROR
Negate (two’s complement)
Rotate left through carry bit
Rotate right through carry bit
Test for negative or zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
Technical Data
54
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set
3.6.2.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
NOTE: Do not use BRCLR or BRSET instructions on registers with write-only
bits.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
55
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 3-3. Jump and Branch Instructions
Instruction
Branch if carry bit clear
Branch if carry bit set
Branch if equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if half-carry bit clear
Branch if half-carry bit set
Branch if higher
Branch if higher or same
Branch if IRQ pin high
Branch if IRQ pin low
Branch if lower
BHS
BIH
BIL
BLO
Branch if lower or same
Branch if interrupt mask clear
Branch if minus
BLS
BMC
BMI
Branch if interrupt mask set
Branch if not equal
Branch if plus
BMS
BNE
BPL
Branch always
BRA
Branch if bit clear
BRCLR
BRN
BRSET
BSR
Branch never
Branch if bit set
Branch to subroutine
Unconditional jump
Jump to subroutine
JMP
JSR
Technical Data
56
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set
3.6.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 3-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit clear
Branch if bit clear
Branch if bit set
Bit set
BRCLR
BRSET
BSET
NOTE: Do not use bit manipulation instructions on registers with write-only bits.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
57
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.6.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 3-5. Control Instructions
Instruction
Clear carry bit
Mnemonic
CLC
CLI
Clear interrupt mask
No operation
NOP
RSP
RTI
Reset stack pointer
Return from interrupt
Return from subroutine
Set carry bit
RTS
SEC
SEI
Set interrupt mask
Stop oscillator and enable IRQ pin
Software interrupt
STOP
SWI
Transfer accumulator to index register
Transfer index register to accumulator
Stop CPU clock and enable interrupts
TAX
TXA
WAIT
Technical Data
58
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set Summary
3.7 Instruction Set Summary
Table 3-6. Instruction Set Summary (Sheet 1 of 6)
Effect
Source
Operation
Form
on CCR
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
ADC opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
Add with Carry
ADC opr,X
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ADC opr,X
ADC ,X
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
ADD opr
Add without Carry
ADD opr,X
A ← (A) + (M)
↕ — ↕ ↕ ↕
ADD opr,X
ADD ,X
AND #opr
AND opr
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
AND opr
Logical AND
A ← (A) (M)
— — ↕ ↕ —
AND opr,X
AND opr,X
AND ,X
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38
48
58
68
78
5
3
3
6
5
C
0
Arithmetic Shift Left (Same as LSL)
— — ↕ ↕ ↕ INH
IX1
IX
b7
b7
b0
b0
ff
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕ INH
IX1
IX
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
3
3
3
3
BEQ rel
BHCC rel
BHCS rel
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
59
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 3-6. Instruction Set Summary (Sheet 2 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
22 rr
24 rr
2F rr
2E rr
3
3
3
3
BHS rel
BIH rel
BIL rel
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
Technical Data
60
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set Summary
Table 3-6. Instruction Set Summary (Sheet 3 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
dd
3F
4F
5F
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
5
3
3
6
5
Clear Byte
— — 0 1 —
6F
7F
ff
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
(A) – (M)
— — ↕ ↕
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
Complement Byte (One’s Complement)
— — ↕ ↕ 1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
Compare Index Register with Memory Byte
(X) – (M)
— — ↕ ↕ ↕
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
Decrement Byte
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory Byte
A ← (A) (M)
— —
↕
—
↕
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
61
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 3-6. Instruction Set Summary (Sheet 4 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
hh ll
ee ff
ff
JMP opr
DIR
EXT CC
IX2
IX1
IX
BC
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Unconditional Jump
PC ← Jump Address
— — — — —
DC
EC
FC
dd
hh ll
ee ff
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT CD
IX2
IX1
IX
BD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
— — — — —
DD
ED
FD
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
— —
↕
—
↕
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
X ← (M)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— — ↕
↕ ↕
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0
↕
b7
b0
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
0 — — — 0
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
— — ↕
↕ ↕
NOP
— — — — —
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
A ← (A) (M)
— —
↕
—
↕
Technical Data
62
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Instruction Set Summary
Table 3-6. Instruction Set Summary (Sheet 5 of 6)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
dd
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
Rotate Byte Left through Carry Bit
— —
— —
↕
↕
↕ ↕
↕ ↕
b7
b0
ff
dd
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
b7
b0
ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕
INH
80
9
↕ ↕ ↕ ↕
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— — ↕
↕ ↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— —
↕
—
↕
STOP
— 0 — — —
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
— —
↕
—
↕
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
— —
↕ ↕
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
63
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 3-6. Instruction Set Summary (Sheet 6 of 6)
Effect
on CCR
Source
Form
Operation
Description
H I N Z C
— 1 — — —
— — — — —
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAX
Transfer Accumulator to Index Register
Test Memory Byte for Negative or Zero
X ← (A)
(M) – $00
A ← (X)
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
— —
—
↕ ↕
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
PCH Program counter high byte
dd
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
PCL
REL
rel
rr
SP
X
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
dd rr
DIR
ee ff
EXT
ff
Index register
Zero flag
H
Z
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
3.8 Opcode Map
See Table 3-7.
Technical Data
64
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Table 3-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
0
3
DIR 2
5
BRCLR0
DIR 2
5
BRSET1
DIR 2
5
BRCLR1
DIR 2
5
BRSET2
DIR 2
5
BRCLR2
DIR 2
5
BRSET3
DIR 2
5
BRCLR3
DIR 2
5
BRSET4
DIR 2
5
BRCLR4
DIR 2
5
BRSET5
DIR 2
5
BRCLR5
DIR 2
5
BRSET6
DIR 2
5
BRCLR6
DIR 2
5
BRSET7
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
6
RTS
INH
2
2
2
2
2
2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
CMP
IX2 2
IX1 1
4
CMP
IX1 1
IX
3
BCLR0
BRN
CMP
CMP
CMP
1
2
3
3
DIR 2
5
REL
3
1
IMM 2
2
DIR 3
3
EXT 3
4
IX
3
11
5
4
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
CPX
AND
BIT
SBC
CPX
AND
BIT
2
DIR 2
5
REL
3
1
5
INH
3
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
3
6
5
10
SWI
INH
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
CPX
CPX
CPX
3
3
3
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX 1
5
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
4
4
DIR 2
5
BCLR2 BCS/BLO
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
BIT
BIT
BIT
5
5
3
DIR 2
5
REL
3
IMM 2
2
DIR 3
3
LDA
DIR 3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
5
3
3
6
5
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
LDA
STA
6
6
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
IMM 2
EXT 3
5
IX2 2
6
IX1 1
5
IX
4
2
4
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
7
7
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
1
1
1
1
1
1
1
INH
2
2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
EOR
IX1 1
IX
3
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
8
8
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX
3
4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
ADC
9
9
3
DIR 2
5
REL 2
3
DIR 1
5
INH 1
3
INH 2
3
IX1 1
6
IX
5
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
ORA
IX1 1
IX
3
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
SEI
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
2
IMM 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX
3
4
BCLR5
BMI
ADD
ADD
ADD
ADD
JMP
JSR
LDX
STX
3
DIR 2
5
REL
3
INH 2
2
IMM 2
DIR 3
2
EXT 3
3
IX2 2
4
IX1 1
3
IX
2
5
3
3
6
5
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
INH
JMP
JMP
3
DIR 2
5
REL 2
3
DIR 1
4
INH 1
3
INH 2
3
IX1 1
5
IX
4
2
6
DIR 3
5
EXT 3
6
IX2 2
7
IX1 1
6
IX
5
2
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR 2
5
REL 2
3
DIR 1
INH 1
INH 2
IX1 1
IX
INH 2
REL 2
2
DIR 3
3
EXT 3
4
IX2 2
5
IX1 1
4
IX
3
2
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR 2
5
DIR 2
5
BCLR7
DIR 2
REL
3
1
INH
2
WAIT
INH 1
2
2
IMM 2
DIR 3
4
EXT 3
5
STX
EXT 3
IX2 2
6
IX1 1
5
IX
4
5
3
3
6
5
BRCLR7
BIH
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
CLR
TXA
INH
STX
3
DIR 2
REL 2
IX1 1
IX 1
2
DIR 3
IX2 2
IX1 1
IX
MSB
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
Number of Cycles
LSB
5
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Central Processor Unit (CPU)
Technical Data
66
MC68HC705J1A — Rev. 3.0
MOTOROLA
Central Processor Unit (CPU)
Technical Data — MC68HC705J1A
Section 4. Resets and Interrupts
4.1 Contents
4.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.3
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1
4.3.2
4.3.3
4.3.4
4.4
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .74
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4.4.1
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.2 Introduction
Reset initializes the microcontroller unit (MCU) by returning the program
counter to a known address and by forcing control and status bits to
known states.
Interrupts temporarily change the sequence of program execution to
respond to events that occur during processing.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Resets and Interrupts
67
Resets and Interrupts
4.3 Resets
A reset immediately stops the operation of the instruction being
executed, initializes certain control and status bits, and loads the
program counter with a user-defined reset vector address. These
sources can generate a reset:
• Power-on reset (POR) circuit
• RESET pin
• Computer operating properly (COP) watchdog
• Illegal address
ILLEGAL ADDRESS
COP WATCHDOG
POWER-ON RESET
V
DD
TO CPU AND
PERIPHERAL
MODULES
RST
S
RESET PIN
D
Q
CK
INTERNAL CLOCK
RESET
LATCH
Figure 4-1. Reset Sources
Technical Data
68
MC68HC705J1A — Rev. 3.0
MOTOROLA
Resets and Interrupts
Resets and Interrupts
Resets
4.3.1 Power-On Reset
A positive transition on the V pin generates a power-on reset.
DD
NOTE: The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-t (internal clock cycle) delay after the oscillator becomes
cyc
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains in the reset condition until all
reset sources are inactive.
V
DD
OSCILLATOR STABILIZATION DELAY
(NOTE 1)
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
$07FE
$07FE
$07FE
$07FE
$07FE
$07FE
$07FF
ADDRESS BUS
INTERNAL
DATA BUS
NEW PCL
NEW PCH
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 4-2. Power-On Reset Timing
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
69
Resets and Interrupts
Resets and Interrupts
4.3.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 t generates an external
cyc
reset. A Schmitt trigger senses the logic level at the RESET pin.
INTERNAL
CLOCK
INTERNAL
$07FE
$07FE
$07FE
$07FE
$07FF NEW PC NEW PC
ADDRESS BUS
NEW
PCH
NEW
PCL
OP
CODE
INTERNAL
DATA BUS
DUMMY
tRL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 4-3. External Reset Timing
Table 4-1. External Reset Timing
Characteristic
RESET pulse width
Symbol
Min
Max
Unit
t
t
1.5
—
RL
cyc
4.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
4.3.4 Illegal Address Reset
An opcode fetch from an address not in random-access memory (RAM)
or erasable, programmable read-only memory (EPROM) generates a
reset.
Technical Data
70
MC68HC705J1A — Rev. 3.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
4.4 Interrupts
These sources can generate interrupts:
• Software interrupt (SWI) instruction
• External interrupt pins:
– IRQ/V
PP
– PA0–PA3
• Timer:
– Real-time interrupt flag (RTIF)
– Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
4.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.4.2 External Interrupt
An interrupt signal on the IRQ/V pin latches an external interrupt
PP
request. When the CPU completes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Resets and Interrupts
71
Resets and Interrupts
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ/V pin can latch another interrupt
PP
request during the interrupt service routine. As soon as the I bit is
cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 4-4 shows the IRQ/V pin interrupt logic.
PP
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
IRQF
IRQE
V
DD
EXTERNAL
INTERRUPT
REQUEST
IRQ
D
Q
PA3
PA2
PA1
PA0
LATCH
CK
CLR
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 4-4. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The external interrupt sensitivity bit (LEVEL) in the mask option register
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/V pin can be negative-edge triggered only or negative-edge and
PP
low-level triggered. Port A external interrupt pins can be positive-edge
triggered only or both positive-edge and high-level triggered. The
level-sensitive triggering option allows multiple external interrupt
sources to be wire-ORed to an external interrupt pin. An external
interrupt request, shown in Figure 4-5, is latched as long as any source
is holding an external interrupt pin low.
Technical Data
72
MC68HC705J1A — Rev. 3.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
t
ILIL
t
IRQ PIN
ILIH
t
IRQ
ILIH
1
.
.
.
IRQ
n
IRQ (INTERNAL)
Figure 4-5. External Interrupt Timing
(1)
Table 4-2. External Interrupt Timing (V = 5.0 Vdc)
DD
Characteristic
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
Symbol
Min
Max Unit
tILIH
125
—
—
ns
(2)
tILIL
t
cyc
Note
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. The minimum, tILIL, should not be less than the number of interrupt service routine cycles
plus 19 t
.
cyc
(1)
Table 4-3. External Interrupt Timing (V = 3.3 Vdc)
DD
Characteristic
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
Symbol
Min
Max Unit
tILIH
250
—
—
ns
(2)
tILIL
t
cyc
Note
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. The minimum, tILIL, should not be less than the number of interrupt service routine cycles
plus 19 t
.
cyc
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
73
Resets and Interrupts
Resets and Interrupts
4.4.3 Timer Interrupts
The timer can generate these interrupt requests:
• Real time
• Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
4.4.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
4.4.3.2 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
4.4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
• Stores the CPU registers on the stack in the order shown in
Figure 4-6
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-6.
Technical Data
74
MC68HC705J1A — Rev. 3.0
Resets and Interrupts
MOTOROLA
Resets and Interrupts
Interrupts
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
•
•
•
UNSTACKING
ORDER
5
4
3
2
1
1
2
3
4
5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
STACKING
ORDER
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-6. Interrupt Stacking Order
Table 4-4. Reset/Interrupt Vector Addresses
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Function
Source
Power-on
RESET pin
COP
Reset
None
None
None
1
$07FE–$07FF
$07FC–$07FD
(1)
watchdog
illegal address
Software
interrupt
(SWI)
Same priority
as instruction
User code
None
IRQE
External
interrupt
IRQ/V pin
I bit
I bit
2
3
$07FA–$07FB
$07F8–$07F9
PP
Timer
interrupts
RTIF bit
TOF bit
RTIE bit
TOIE bit
1. The COP watchdog is programmable in the mask option register.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
75
Resets and Interrupts
Resets and Interrupts
FROM RESET
YES
I BIT SET?
NO
YES
YES
EXTERNAL
CLEAR IRQ LATCH
INTERRUPT?
NO
TIMER
INTERRUPT?
STACK PC, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CCR, A, X, PC
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 4-7. Interrupt Flowchart
Technical Data
76
MC68HC705J1A — Rev. 3.0
MOTOROLA
Resets and Interrupts
Technical Data — MC68HC705J1A
Section 5. Low-Power Modes
5.1 Contents
5.2
5.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .78
5.4
Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .79
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.2 Introduction
The microcontroller unit (MCU) can enter these low-power standby
modes:
• Stop mode — The STOP instruction puts the MCU in its lowest
power-consumption mode.
• Wait mode — The WAIT instruction puts the MCU in an
intermediate power-consumption mode.
• Halt mode — Halt mode is identical to wait mode, except that an
oscillator stabilization delay of 1 to 4064 internal clock cycles
occurs when the MCU exits halt mode. The stop-to-wait
conversion bit, SWAIT, in the mask option register, enables halt
mode.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Low-Power Modes
77
Low-Power Modes
Enabling halt mode prevents the computer operating properly
(COP) watchdog from being inadvertently turned off by a STOP
instruction.
• Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at V voltages as low
DD
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consumption state during which it retains data, but
the CPU cannot execute instructions.
5.3 Exiting Stop and Wait Modes
The events described in this subsection bring the MCU out of stop mode
and load the program counter with the reset vector or with an interrupt
vector.
Exiting stop mode:
• External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/V pin or
PP
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Exiting wait mode:
• External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and loads the program counter with the
contents of locations $07FE and $07FF.
• External interrupt — A high-to-low transition on the IRQ/V pin or
PP
a low-to-high transition on an enabled port A external interrupt pin
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Technical Data
78
MC68HC705J1A — Rev. 3.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Effects of Stop and Wait Modes
• COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
• Timer interrupt — Real-time interrupt requests and timer overflow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
5.4 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the effects described in this
subsection on MCU modules.
5.4.1 Clock Generation
The STOP instruction:
The STOP instruction disables the internal oscillator, stopping the
CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral
clocks begin running after the oscillator stabilization delay.
NOTE: The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
The WAIT instruction:
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral
clocks immediately begin running.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
79
Low-Power Modes
Low-Power Modes
5.4.2 CPU
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the
oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
• Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
5.4.3 COP Watchdog
The STOP instruction:
• Clears the COP watchdog counter
• Disables the COP watchdog clock
NOTE: To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE: Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
Technical Data
80
MC68HC705J1A — Rev. 3.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Effects of Stop and Wait Modes
After exit from stop mode by reset:
• The COP watchdog counter immediately begins counting from
$0000.
• The COP watchdog counter is cleared at the end of the oscillator
stabilization delay and begins counting from $0000 again.
The WAIT instruction:
The WAIT instruction has no effect on the COP watchdog.
NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
5.4.4 Timer
The STOP instruction:
• Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and
control register, disabling timer interrupt requests and removing
any pending timer interrupt requests
• Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately
resumes counting from the last value before the STOP instruction and
continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization
delay, the timer resumes operation from its reset state.
The WAIT instruction:
The WAIT instruction has no effect on the timer.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
81
Low-Power Modes
Low-Power Modes
5.4.5 EPROM/OTPROM
The STOP instruction:
The STOP instruction during erasable, programmable read-only
memory (EPROM) programming clears the EPGM bit in the EPROM
programming register, removing the programming voltage from the
EPROM.
The WAIT instruction:
The WAIT instruction has no effect on EPROM/one-time
programmable read-only memory (OTPROM) operation.
5.4.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at V voltages as low as 2.0 Vdc.
DD
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the V voltage. The RESET pin must remain low
DD
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return V to normal operating voltage.
DD
2. Return the RESET pin to logic 1.
Technical Data
82
MC68HC705J1A — Rev. 3.0
MOTOROLA
Low-Power Modes
Low-Power Modes
Timing
5.5 Timing
OSC
(NOTE 1)
t
RL
RESET
t
ILIH
IRQ/V
PP
(NOTE 2)
OSCILLATOR STABILIZATION DELAY
IRQ/V
(NOTEP3P)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
$07FE
(NOTE 4)
$07FE
$07FE
$07FE
$07FE
$07FF
Notes:
RESET OR INTERRUPT
VECTOR FETCH
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
Figure 5-1. Stop Mode Recovery Timing
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
83
Low-Power Modes
Low-Power Modes
STOP
SWAIT
BIT SET?
YES
HALT
WAIT
NO
CLEAR I BIT IN CCR
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
YES
YES
EXTERNAL
RESET?
EXTERNAL
RESET?
YES
EXTERNAL
RESET?
NO
NO
NO
YES
YES
YES
YES
YES
YES
EXTERNAL
INTERRUPT?
EXTERNAL
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
NO
NO
NO
TIMER
INTERRUPT?
TIMER
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
RESET STABILIZATION TIMER
NO
NO
COP
RESET?
COP
RESET?
END OF
YES
STABILIZATION
DELAY?
NO
NO
NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 5-2. Stop/Halt/Wait Flowchart
Technical Data
84
MC68HC705J1A — Rev. 3.0
MOTOROLA
Low-Power Modes
Technical Data — MC68HC705J1A
Section 6. Parallel Input/Output (I/O) Ports
6.1 Contents
6.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .88
Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Port A LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . .90
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .91
Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.4.1
6.4.2
6.4.3
6.5
6.6
5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .93
3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .93
6.2 Introduction
Fourteen bidirectional pins form one 8-bit input/output (I/O) port and one
6-bit I/O port. All the bidirectional port pins are programmable as inputs
or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either V or
DD
V
Although the I/O ports do not require termination for proper
SS.
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
85
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
(PORTA) Write:
See page 87.
Reset:
Read:
Unaffected by reset
PB4 PB3
Unaffected by reset
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
Port B Data Register
PB5
PB2
PB1
PB0
$0001
$0004
$0005
$0010
$0011
(PORTB) Write:
See page 90.
Reset:
Read:
Data Direction Register A
(DDRA) Write:
See page 88.
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
Data Direction Register B
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
(DDRB) Write:
See page 91.
Reset:
Read:
0
0
0
0
0
0
0
0
Pulldown Register A
(PDRA) Write: PDIA7
See page 89.
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
Reset:
Read:
0
Pulldown Register B
(PDRB) Write:
See page 92.
PDIB5
0
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
0
PDIB0
0
Reset:
= Unimplemented
Figure 6-1. Parallel I/O Port Register Summary
Technical Data
86
MC68HC705J1A — Rev. 3.0
MOTOROLA
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
Port A
6.3 Port A
Port A is an 8-bit bidirectional port.
6.3.1 Port A Data Register
The port A data register (PORTA) contains a latch for each port A pin.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
PA0
Read:
Write:
Reset:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Unaffected by reset
Figure 6-2. Port A Data Register (PORTA)
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Parallel Input/Output (I/O) Ports
87
Parallel Input/Output (I/O) Ports
6.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
Figure 6-3. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 6-4 shows the I/O logic of port A.
READ DDRA
WRITE DDRA
DDRAx
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
WRITE PORTA
PAx
PAx
(PA0–PA3 TO
IRQ MODULE)
READ PORTA
WRITE PDRA
100-µA
PULLDOWN
PDRAx
RESET
SWPDI
Figure 6-4. Port A I/O Circuitry
Technical Data
88
MC68HC705J1A — Rev. 3.0
MOTOROLA
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
Port A
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 6-1 summarizes the operation
of the port A pins.
Table 6-1. Port A Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects the data register but does not affect input.
6.3.3 Pulldown Register A
Pulldown register A (PDRA) inhibits the pulldown devices on port A pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port A pins as inputs with enabled pulldown devices.
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: PDIA7
Reset:
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
0
= Unimplemented
Figure 6-5. Pulldown Register A (PDRA)
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
89
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
6.3.4 Port A LED Drive Capability
The outputs for the upper four bits of port A (PA4–PA7) can drive
light-emitting diodes (LEDs). PA4–PA7 can sink approximately 10 mA of
current to V .
SS
6.3.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. See Section 8.
External Interrupt Module (IRQ).
6.4 Port B
Port B is a 6-bit bidirectional port.
6.4.1 Port B Data Register
The port B data register (PORTB) contains a latch for each port B pin.
Address: $0001
Bit 7
6
0
5
4
3
2
1
Bit 0
PB0
Read:
Write:
Reset:
0
PB5
PB4
PB3
PB2
PB1
Unaffected by reset
= Unimplemented
Figure 6-6. Port B Data Register (PORTB)
PB[5:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
Technical Data
90
MC68HC705J1A — Rev. 3.0
Parallel Input/Output (I/O) Ports
MOTOROLA
Parallel Input/Output (I/O) Ports
Port B
6.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output.
Address: $0005
Bit 7
0
6
0
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 6-7. Data Direction Register B (DDRB)
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 6-8 shows the I/O logic of port B.
READ DDRB
WRITE DDRB
DDRBx
WRITE PORTB
PBx
PBx
READ PORTB
WRITE PDRB
100-µA
PULLDOWN
PDRBx
RESET
SWPDI
Figure 6-8. Port B I/O Circuitry
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
91
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 6-2 summarizes the operation
of the port B pins.
Table 6-2. Port B Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Pin
Write
(1)
0
1
Input, high-impedance
Output
Latch
Latch
Latch
1. Writing affects the data register, but does not affect input.
6.4.3 Pulldown Register B
Pulldown register B (PDRB) inhibits the pulldown devices on port B pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask option register is programmed to logic 1,
reset initializes all port B pins as inputs with enabled pulldown devices.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PDIB5
0
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
0
PDIB0
0
= Unimplemented
Figure 6-9. Pulldown Register B (PDRB)
PDIB[7:0] — Pulldown Inhibit B Bits
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Technical Data
92
MC68HC705J1A — Rev. 3.0
MOTOROLA
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
5.0-Volt I/O Port Electrical Characteristics
6.5 5.0-Volt I/O Port Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Current drain per pin excluding PA4–PA7
Output high voltage
Typ
I
—
25
—
mA
V
V
–0.8
—
—
V
OH
DD
(I
= –0.8 mA) PA0–PA7, PB0–PB5
Load
Output low voltage
(I
= 1.6 mA) PA0–PA3, PB0–PB5
—
—
—
—
0.4
0.4
V
Load
Load
V
OL
(I
= 10.0 mA) PA4–PA7
Input high voltage
PA0–PA7, PB0–PB5
V
0.7 x V
V
—
—
V
V
IH
DD
DD
Input low voltage
PA0–PA7, PB0–PB5
V
I
V
0.2 x V
±1
IL
SS
DD
I/O ports hi-z leakage current
PA0–PA7, PB0–PB5 (without individual pulldown activated)
—
0.2
80
µA
µA
IL
Input pulldown current
PA0–PA7, PB0–PB5 (with individual pulldown activated)
I
35
200
IL
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C.
6.6 3.3-Volt I/O Port Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Current drain per pin excluding PA4–PA7
Output high voltage
Typ
I
—
25
—
mA
V
V
–0.3
DD
—
—
V
OH
(I
= –0.2 mA) PA0–PA7, PB0–PB5
Load
Output low voltage
(I
= 0.4 mA) PA0–PA3, PB0–PB5
V
—
—
—
—
0.3
0.3
V
Load
Load
OL
(I
= 5.0 mA) PA4–PA7
Input high voltage
PA0–PA7, PB0–PB5
V
0.7 x V
V
—
—
V
V
IH
DD
DD
Input low voltage
PA0–PA7, PB0–PB5
V
V
0.2 x V
±1
IL
SS
DD
I/O ports hi-z leakage current
PA0–PA7, PB0–PB5 (without individual pulldown activated)
I
—
0.1
30
µA
µA
IL
Input pulldown current
PA0–PA7, PB0–PB5 (with individual pulldown activated)
I
12
100
IL
1. VDD = 3.3 Vdc ± 10%, VSS= 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C.
MC68HC705J1A — Rev. 3.0
TechnicalData
93
MOTOROLA
Parallel Input/Output (I/O) Ports
Parallel Input/Output (I/O) Ports
Technical Data
MC68HC705J1A — Rev. 3.0
MOTOROLA
94
Parallel Input/Output (I/O) Ports
Technical Data — MC68HC705J1A
Section 7. Computer Operating Properly (COP) Module
7.1 Contents
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.3
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .96
COP Watchdog Timeout Period. . . . . . . . . . . . . . . . . . . . . .96
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .96
7.3.1
7.3.2
7.3.3
7.4
7.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.6
7.6.1
7.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.2 Introduction
The computer operating properly (COP) watchdog resets the
microcontroller (MCU) in case of software failure. Software that is
operating properly periodically services the COP watchdog and prevents
COP reset. The COP watchdog function is programmable by the
COPEN bit in the mask option register.
Features include:
• Protection from runaway software
• Wait and halt mode operation
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Computer Operating Properly (COP) Module
95
Computer Operating Properly (COP) Module
7.3 Operation
Operation of the COP is described in this subsection.
7.3.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/V pin
PP
voltage is between V and V . Periodically clearing the counter starts
SS
DD
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE: The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
7.3.2 COP Watchdog Timeout Period
The COP watchdog timer function is implemented by dividing the output
of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. See timer status and control register
in Section 9. Multifunction Timer Module.
NOTE: The minimum COP timeout period is seven times the RTI period. The
COP is cleared asynchronously with the value in the RTI divider; hence,
the COP timeout period will vary between 7x and 8x the RTI period.
7.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see Figure 7-1).
Technical Data
96
MC68HC705J1A — Rev. 3.0
Computer Operating Properly (COP) Module
MOTOROLA
Computer Operating Properly (COP) Module
Interrupts
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/V pin voltage.
PP
If the main program executes within the COP timeout period, the clearing
routine should be executed only once. If the main program takes longer
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE: Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
7.4 Interrupts
The COP watchdog does not generate interrupts.
7.5 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
Address: $07F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
0
= Unimplemented
Figure 7-1. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Computer Operating Properly (COP) Module
97
Computer Operating Properly (COP) Module
7.6 Low-Power Modes
The STOP and WAIT instructions have these effects on the COP
watchdog.
7.6.1 Stop Mode
The STOP instruction clears the COP watchdog counter and disables
the clock to the COP watchdog.
NOTE: To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
Upon exit from stop mode by external reset:
• The counter begins counting from $0000.
• The counter is cleared again after the oscillator stabilization delay
and begins counting from $0000 again.
Upon exit from stop mode by external interrupt:
• The counter begins counting from $0000.
• The counter is not cleared again after the oscillator stabilization
delay and continues counting throughout the oscillator
stabilization delay.
NOTE: Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
7.6.2 Wait Mode
The WAIT instruction has no effect on the COP watchdog.
NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
Technical Data
98
MC68HC705J1A — Rev. 3.0
Computer Operating Properly (COP) Module
MOTOROLA
Technical Data — MC68HC705J1A
Section 8. External Interrupt Module (IRQ)
8.1 Contents
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.3
8.3.1
8.3.2
IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .102
PP
8.4
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .104
8.5
8.5.1
8.5.2
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
5.0-Volt External Interrupt Timing Characteristics . . . . . . .105
3.3-Volt External Interrupt Timing Characteristics . . . . . . .105
8.2 Introduction
The external interrupt (IRQ) module provides asynchronous external
interrupts to the CPU. These sources can generate external interrupts:
• IRQ/V pin
PP
• PA0–PA3 pins
Features include:
• Dedicated external interrupt pin (IRQ/V )
PP
• Selectable interrupt on four input/output (I/O) pins (PA0–PA3)
• Programmable edge-only or edge- and level-interrupt sensitivity
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
External Interrupt Module (IRQ)
99
External Interrupt Module (IRQ)
8.3 Operation
The interrupt request/programming voltage pin (IRQ/V ) and port A
PP
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single ORing function to be latched by the
IRQ latch. Figure 8-1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If
the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. This interrupt is serviced by the interrupt service routine
located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 8-2
shows the sequence of events caused by an interrupt.
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
(MOR LEVEL BIT)
IRQF
V
DD
EXTERNAL
INTERRUPT
REQUEST
IRQ
LATCH
CK
D
Q
PA3
PA2
PA1
PA0
IRQE
CLR
PIRQ
(MOR)
RESET
IRQ VECTOR FETCH
IRQR
Figure 8-1. IRQ Module Block Diagram
Technical Data
100
MC68HC705J1A — Rev. 3.0
MOTOROLA
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
Operation
FROM RESET
YES
I BIT SET?
NO
YES
YES
EXTERNAL
CLEAR IRQ LATCH
INTERRUPT?
NO
TIMER
INTERRUPT?
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CCR, A, X, PCH, PCL
EXECUTE INSTRUCTION
INSTRUCTION?
NO
Figure 8-2. Interrupt Flowchart
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
101
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
8.3.1 IRQ/V Pin
PP
An interrupt signal on the IRQ/V pin latches an external interrupt
PP
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low
level on the IRQ/V pin latches an external interrupt request. Edge- and
PP
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/V pin low.
PP
If level-sensitive triggering is selected, the IRQ/V input requires an
PP
external resistor to V for wired-OR operation. If the IRQ/V pin is not
DD
PP
used, it must be tied to the V supply.
DD
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/V pin latches an external interrupt request. A subsequent
PP
external interrupt request can be latched only after the voltage level on
the IRQ/V pin returns to logic 1 and then falls again to logic 0.
PP
The IRQ/V pin contains an internal Schmitt trigger as part of its input
PP
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed V .
DD
8.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/V pin except for the inverted phase (logic 1, rising edge). The
PP
active state of the IRQ/V pin is a logic 0 (falling edge).
PP
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
Technical Data
102
MC68HC705J1A — Rev. 3.0
External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
Operation
If edge- and level-sensitive triggering is selected, a rising edge or a high
level on a PA0–PA3 pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. As long as any source is holding a PA0–PA3 pin high,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edge on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE: The branch if interrupt pin is high (BIH) and branch if interrupt pin is low
(BIL) instructions apply only to the level on the IRQ/V pin itself and not
PP
to the output of the logic OR function with the PA0–PA3 pins. The state
of the individual port A pins can be checked by reading the appropriate
port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
External Interrupt Module (IRQ)
103
External Interrupt Module (IRQ)
8.4 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as
logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
Address: $000A
Bit 7
IRQE
1
6
0
5
0
4
0
3
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
IRQF
R
0
IRQR
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 8-3. IRQ Status and Control Register (ISCR)
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The external interrupt request flag is a clearable, read-only bit that is
set when an external interrupt request is pending. Reset clears the
IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
The STOP and WAIT instructions set the IRQE bit so that an external
interrupt can bring the MCU out of these low-power modes. In addition,
reset sets the I bit which masks all interrupt sources.
Technical Data
104
MC68HC705J1A — Rev. 3.0
External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
External Interrupt Timing
8.5 External Interrupt Timing
t
ILIL
t
IRQ PIN
ILIH
t
IRQ
ILIH
1
.
.
.
IRQ
n
IRQ (INTERNAL)
Figure 8-4. External Interrupt Timing
8.5.1 5.0-Volt External Interrupt Timing Characteristics
(1)
Symbol
Min
Max
Unit
Characteristic
(2)
t
IRQ interrupt pulse width low (edge-triggered)
1.5
1.5
1.5
1.5
—
t
ILIH
cyc
(3)
t
t
IRQ interrupt pulse width (edge- and level-triggered)
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse width high (edge- and level-triggered)
Note
—
ILIH
cyc
t
t
t
ILIL
cyc
cyc
(3)
t
Note
ILIH
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. t = 1/fop; fop = fosc/2.
3. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 t
cyc
.
cyc
8.5.2 3.3-Volt External Interrupt Timing Characteristics
(1)
Symbol
Min
Max
Unit
Characteristic
(2)
t
IRQ interrupt pulse width low (edge-triggered)
1.5
1.5
1.5
1.5
—
t
ILIH
cyc
(3)
t
t
IRQ interrupt pulse width (edge- and level-triggered)
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse width high (edge- and level-triggered)
Note
—
ILIH
cyc
t
t
t
ILIL
cyc
cyc
(3)
t
Note
ILIH
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. t = 1/fop; fop = fosc/2.
3. The minimum, tILIL, should not be less than the number of interrupt service routine cycles plus 19 t
cyc
.
cyc
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
105
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
Technical Data
MC68HC705J1A — Rev. 3.0
MOTOROLA
106
External Interrupt Module (IRQ)
Technical Data — MC68HC705J1A
Section 9. Multifunction Timer Module
9.1 Contents
9.2
9.3
9.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.5
9.5.1
9.5.2
I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Timer Status and Control Register. . . . . . . . . . . . . . . . . . .110
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.6
9.6.1
9.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.2 Introduction
The multifunction timer provides a timing reference with programmable
real-time interrupt (RTI) capability. Figure 9-1 shows the timer
organization.
Features include:
• Timer overflow
• Four selectable interrupt rates
• Computer operating properly (COP) watchdog timer
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Multifunction Timer Module
107
Multifunction Timer Module
RESET
OVERFLOW
INTERNAL CLOCK
TIMER COUNTER REGISTER
÷ 4
(XTAL ÷ 2)
BITS [0:7] OF 15-STAGE
RIPPLE COUNTER
RESET
INTERRUPT
REQUEST
TIMER STATUS/CONTROL REGISTER
RTI RATE SELECT
RESET
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
BITS [8:14] OF 15-STAGE RIPPLE COUNTER
COP RESET
÷ 8
S
Q
R
RESET
Figure 9-1. Multifunction Timer Block Diagram
Technical Data
108
MC68HC705J1A — Rev. 3.0
MOTOROLA
Multifunction Timer Module
Multifunction Timer Module
Operation
Addr.
Register Name
Bit 7
6
5
4
3
0
2
0
1
Bit 0
Read: TOF
RTIF
Timer Status and Control
TOIE
RTIE
RT1
RT0
$0008
Register (TSCR) Write:
See page 110.
TOFR
0
RTIFR
0
Reset:
0
0
0
0
1
1
Read: TMR7
Write:
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Timer Counter Register
(TCR)
$0009
See page 112.
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-2. I/O Register Summary
9.3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage allows a timer interrupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system. For
information on the COP, refer to the Section 7. Computer Operating
Properly (COP) Module.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Multifunction Timer Module
109
Multifunction Timer Module
9.4 Interrupts
These timer sources can generate interrupts:
• Timer overflow flag (TOF) — The TOF bit is set when the first eight
stages of the counter roll over from $FF to $00. The timer overflow
interrupt enable bit, TOIE, enables TOF interrupt requests.
• Real-time interrupt flag (RTIF) — The RTIF bit is set when the
selected RTI output becomes active. The real-time interrupt
enable bit, RTIE, enables RTIF interrupt requests.
9.5 I/O Registers
These registers control and monitor the timer operation:
• Timer status and control register (TSCR)
• Timer counter register (TCR)
9.5.1 Timer Status and Control Register
The read/write timer status and control register (TSCR) performs these
functions:
• Flags timer interrupts
• Enables timer interrupts
• Resets timer interrupt flags
• Selects real-time interrupt rates
Address: $0008
Bit 7
TOF
6
5
TOIE
0
4
RTIE
0
3
0
2
1
RT1
1
Bit 0
RT0
1
Read:
Write:
Reset:
RTIF
0
RTIFR
0
TOFR
0
0
0
= Unimplemented
Figure 9-3. Timer Status and Control Register (TSCR)
Technical Data
110
MC68HC705J1A — Rev. 3.0
MOTOROLA
Multifunction Timer Module
Multifunction Timer Module
I/O Registers
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output
becomes active. RTIF generates a real-time interrupt request if RTIE
is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing
to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as logic 0. Reset clears TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as logic 0. Reset clears RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits
These read/write bits select one of four real-time interrupt rates, as
shown in Table 9-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE: Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
111
Multifunction Timer Module
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
Table 9-1. Real-Time Interrupt Rate Selection
Number
of Cycles
to RTI
Number
of Cycles
to COP Reset
RTI
COP Timeout
RT1:RT0
(1)
(1)
Period
Period
14
17
0 0
0 1
1 0
1 1
8.2 ms
16.4 ms
32.8 ms
65.5 ms
65.5 ms
131.1 ms
262.1 ms
524.3 ms
2
2
2
= 16,384
2
2
2
= 131,072
= 262,144
= 524,288
= 1,048,576
15
18
19
= 32,768
16
= 65,536
17
20
2
= 131,072
2
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in Figure 9-4.
Address: $0009
Bit 7
Read: TMR7
Write:
6
5
4
3
2
1
Bit 0
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-4. Timer Counter Register (TCR)
Power-on clears the entire counter chain and the internal clock begins
clocking the counter. After 4064 cycles (or 16 cycles if the SOSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Technical Data
112
MC68HC705J1A — Rev. 3.0
Multifunction Timer Module
MOTOROLA
Multifunction Timer Module
Low-Power Modes
9.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low
power-consumption standby states.
9.6.1 Stop Mode
The STOP instruction has these effects on the timer:
• Clears the timer counter
• Clears interrupt flags (TOF and RTIF) and interrupt enable bits
(TOFE and RTIE) in TSCR, removing any pending timer interrupt
requests and disabling further timer interrupts.
9.6.2 Wait Mode
The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Multifunction Timer Module
113
Multifunction Timer Module
Technical Data
114
MC68HC705J1A — Rev. 3.0
MOTOROLA
Multifunction Timer Module
Technical Data — MC68HC705J1A
Section 10. Electrical Specifications
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .117
10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119
10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .120
10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.11 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . .124
10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.2 Introduction
This section contains electrical and timing specifications.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Electrical Specifications
115
Electrical Specifications
10.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep V and V
within the range
In
Out
V
≤ (V or V ) ≤ V . Connect unused inputs to the appropriate
In Out DD
SS
voltage level, either V or V .
SS
DD
(1)
Symbol
Value
Unit
Rating
V
Supply voltage
Current drain per pin (excluding
–0.3 to +7.0
V
DD
I
25
mA
V
V
, V , and PA4–PA7)
DD SS
V
V
– 0.3 to V + 0.3
SS DD
Input voltage
In
V
– 0.3
SS
IRQ/V pin
V
V
PP
PP
to 2 x V + 0.3
DD
T
Storage temperature range
1. Voltages are referenced to V
–65 to +150
°C
STG
.
SS
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 10.7 5.0-Volt DC Electrical Characteristics and
10.8 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
116
MC68HC705J1A — Rev. 3.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Temperature Range
10.4 Operating Temperature Range
Value
Package Type
Symbol
Unit
(T to T )
L
H
(1)
(2)
(3)
T
0 to 70
°C
°C
°C
MC68HC705J1AP , DW , S
A
(4)
T
–40 to +85
–40 to +105
MC68HC705J1AC P, CDW, CS
A
(5)
T
MC68HC705J1AV P, VDW, VS
A
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (cerdip)
4. C = extended temperature range
5. V = automotive temperature range
10.5 Thermal Characteristics
Characteristic
Thermal resistance
Symbol
Value
Unit
(1)
MC68HC705J1AP
θ
60
°C/W
JA
(2)
MC68HC705J1ADW
(3)
MC68HC705J1AS
1. P = plastic dual in-line package (PDIP)
2. DW = small outline integrated circuit (SOIC)
3. S = ceramic DIP (cerdip)
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
117
Electrical Specifications
Electrical Specifications
10.6 Power Considerations
The average chip junction temperature, T , in °C can be obtained from:
J
T = T + (P x θ )
(1)
J
A
D
JA
Where:
T = ambient temperature in °C
A
θ
= package thermal resistance, junction to ambient in °C/W
JA
P = P
+ P
I/O
D
INT
P
P
= I × V = chip internal power dissipation
CC CC
= power dissipation on input and output pins (user-determined)
INT
I/O
For most applications, P < P
and can be neglected.
I/O
INT
Ignoring P , the relationship between P and T is approximately:
I/O
D
J
K
P =
(2)
(3)
D
T + 273°C
J
Solving equations (1) and (2) for K gives:
= P x (T + 273°C) + θ x (P )
2
D
A
JA
D
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring P (at equilibrium) for a
D
known T . Using this value of K, the values of P and T can be obtained
A
D
J
by solving equations (1) and (2) iteratively for any value of T .
A
Technical Data
118
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
5.0-Volt DC Electrical Characteristics
10.7 5.0-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
= 10.0 µA
V
V
—
—
—
0.1
—
V
Load
Load
OL
V
V
– 0.1
I
= –10.0 µA
DD
OH
Output high voltage
(I = –0.8 mA) PA0–PA7, PB0–PB5
V
– 0.8
—
—
—
V
V
OH
DD
Load
Output low voltage
0.4
0.4
(I
= 1.6 mA) PA0–PA3, PB0–PB5
V
—
Load
Load
OL
(I
= 10.0 mA) PA4–PA7
Input high voltage
V
0.7 × V
V
—
—
V
V
IH
DD
DD
PA0–PA7, PB0–PB5, IRQ/V , RESET, OSC1
PP
Input low voltage
V
V
0.2 × V
DD
IL
SS
PA0–PA7, PB0–PB5, IRQ/V , RESET, OSC1
PP
Supply current
(3)
Run mode
—
—
3.5
0.45
6.0
2.75
mA
mA
(4)
Wait mode
I
DD
(5)
Stop mode
—
—
0.2
2.0
10
20
µA
µA
25°C
–40 to 105°C
I/O ports hi-z leakage current
I
I
I
—
35
0.2
80
±1
µA
µA
µA
IL
IL
IL
PA0–PA7, PB0–PB5 (without individual pulldown activated)
Input pulldown current
200
–85
PA0–PA7, PB0–PB5 (with individual pulldown activated)
Input pullup current
RESET
–15
–35
(6)
Input current
I
—
0.2
±1
µA
pF
In
RESET, IRQ/V , OSC1
PP
Capacitance
C
Ports (as inputs or outputs)
—
—
—
—
12
8
Out
RESET, IRQ/V , OSC1, OSC2
C
PP
In
Crystal/ceramic resonator oscillator mode internal resistor
R
1.0
2.0
3.0
MΩ
osc
(7)
OSC1 to OSC2
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. Typical values at midpoint of voltage range, 25°C only
3. Run mode IDD is measured using external square wave clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads;
less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V
6. Only input high current rated to +1 µA on RESET.
7. The Rosc value selected for RC oscillator versions of this device is unspecified. See Appendix C. MC68HSR705J1A for
additional information.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
119
Electrical Specifications
Electrical Specifications
10.8 3.3-Volt DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
= 10.0 µA
V
V
—
—
—
0.1
—
V
Load
Load
OL
V
V
– 0.1
I
= –10.0 µA
DD
OH
Output high voltage
(I = –0.2 mA) PA0–PA7, PB0–PB5
V
– 0.3
—
—
—
V
V
OH
DD
Load
Output low voltage
0.3
0.3
(I
= 0.4 mA) PA0–PA3, PB0–PB5
V
—
Load
Load
OL
(I
= 5.0 mA) PA4–PA7
Input high voltage
V
0.7 × V
V
—
—
V
V
IH
DD
DD
PA0–PA7, PB0–PB5, IRQ/V , RESET, OSC1
PP
Input low voltage
V
V
0.2 × V
DD
IL
SS
PA0–PA7, PB0–PB5, IRQ/V , RESET, OSC1
PP
Supply current
(3)
Run Mode
—
—
1.2
0.25
4.0
1.5
mA
mA
(4)
Wait Mode
I
DD
(5)
Stop Mode
—
—
0.1
1.0
5
10
µA
µA
25°C
–40 to 105°C
I/O ports hi-z leakage current
I
I
I
—
12
0.1
30
±1
µA
µA
µA
IL
IL
IL
PA0–PA7, PB0–PB5 (without individual pulldown activated)
Input pulldown current
100
–45
PA0–PA7, PB0–PB5 (with individual pulldown activated)
Input pullup current
RESET
–10
–25
(6)
Input current
I
—
0.1
±1
µA
pF
In
RESET, IRQ/V , OSC1
PP
Capacitance
C
Ports (as inputs or outputs)
—
—
—
—
12
8
Out
RESET, IRQ/V , OSC1, OSC2
C
PP
In
Crystal/ceramic resonator oscillator mode internal resistor
R
1.0
2.0
3.0
MΩ
osc
(7)
OSC1 to OSC2
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
2. Typical values at midpoint of voltage range, 25°C only
3. Run mode IDD is measured using external square wave clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads;
less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all ports configured as inputs; VIL = 0.2 V; VIH = VDD – 0.2 V. Wait mode IDD is measured using external square wave
clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs; VIL = 0.2 V;
VIH = VDD – 0.2 V
6. Only input high current rated to +1 µA on RESET.
7. The Rosc value selected for RC oscillator versions of this device is unspecified. See Appendix C. MC68HSR705J1A for
additional information.
Technical Data
120
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Driver Characteristics
10.9 Driver Characteristics
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
0
V
= 5.0 V
V
= 3.3 V
DD
DD
100 mV
0
0
−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
0
−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
I
I
OH
OH
Notes:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOH = –0.8 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOH = –0.2 mA.
Figure 10-1. PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics
25 °C NOMINAL PROCESSING
2
2
SEE NOTE
SEE NOTE
25 °C NOMINAL PROCESSING
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
0
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
0
V
= 5.0 V
V
= 3.3 V
DD
DD
0
2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
0
2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
I
I
OL
OL
Notes:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 10-2. PA0–PA3, PB0–PB5 Typical Low-Side Driver Characteristics
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
121
Electrical Specifications
Electrical Specifications
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
0
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
0
V
= 5.0 V
V
= 3.3 V
DD
DD
0
10 mA 20 mA 30 mA 40 mA 50 mA
0
10 mA 20 mA 30 mA 40 mA 50 mA
I
I
OL
OL
Notes:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 10.0 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 5.0 mA.
Figure 10-3. PA4–PA7 Typical Low-Side Driver Characteristics
Technical Data
122
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
Typical Supply Currents
10.10 Typical Supply Currents
6.0 mA
5.0 mA
SEE NOTE 1
SEE NOTE 2
5.5 V
4.0 mA
3.0 mA
4.5 V
2.0 mA
1.0 mA
0
3.6 V
3.0 V
0
1.0 MHz
2.0 MHz
INTERNAL OPERATING FREQUENCY (f
)
OP
Notes:
1. At VDD = 5.0 V, devices are specified and tested for IDD ≤ 6.0 mA @ fOP = 2.1 MHz.
2. At VDD = 3.3 V, devices are specified and tested for IDD ≤ 4.0 mA @ fOP = 1.0 MHz.
Figure 10-4. Typical Operating I (25°C)
DD
SEE NOTE 2
SEE NOTE 1
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
0
5.5 V
4.5 V
3.6 V
3.0 V
0
1.0 MHz
2.0 MHz
INTERNAL OPERATING FREQUENCY (f
)
OP
Notes:
1. At VDD = 5.0 V, devices are specified and tested for IDD ≤ 2.75 mA @ fOP = 2.1 MHz.
2. At VDD = 3.3 V, devices are specified and tested for IDD ≤ 1.5 mA @ fOP = 1.0 MHz.
Figure 10-5. Typical Wait Mode I (25°C)
DD
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
123
Electrical Specifications
Electrical Specifications
10.11 EPROM Programming Characteristics
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Programming voltage
V
16.0
16.5
17.0
V
PP
IRQ/V
PP
Programming current
IRQ/V
I
—
3.0
10.0
mA
ms
PP
PP
Programming time
Per array byte
MOR
t
4
4
—
—
—
—
EPGM
t
MPGM
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted
A
10.12 5.0-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
f
Crystal oscillator option
External clock source
—
dc
4.2
4.2
MHz
osc
Internal operating frequency (f ÷ 2)
osc
f
—
dc
2.1
2.1
MHz
ns
Crystal oscillator
External clock
op
Cycle time (1 ÷ f
)
t
476
1.5
1.5
1.5
1.5
1.5
200
—
—
—
OP
cyc
t
t
RESET pulse width low
RL
cyc
t
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse width low (edge- and level-triggered)
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse width (edge- and level-triggered)
OSC1 pulse width
ILIH
cyc
(2)
t
t
Note
ILIL
cyc
t
t
—
IHIL
cyc
(2)
t
t
Note
IHIH
cyc
t
, t
—
ns
OH OL
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted
A
2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc or the interrupt service routine will be re-entered.
Technical Data
124
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt Control Timing
10.13 3.3-Volt Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal oscillator option
External clock source
f
—
dc
2.0
2.0
MHz
osc
Internal operating frequency (f ÷ 2)
osc
f
—
dc
1.0
1.0
MHz
ns
Crystal oscillator
External clock
op
Cycle time (1 ÷ fOP)
t
1000
1.5
—
—
—
cyc
t
t
RESET pulse width low
RL
cyc
t
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse width low (edge- and level-triggered)
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse width (edge- and level-triggered)
OSC1 pulse width
1.5
ILIH
cyc
(2)
t
t
1.5
Note
ILIL
cyc
t
t
1.5
—
IHIL
cyc
(2)
t
t
1.5
Note
IHIH
cyc
t
, t
400
—
ns
OH OL
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, T = –40°C to +105°C, unless otherwise noted
A
2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc or the interrupt service routine will be re-entered.
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
125
Electrical Specifications
Electrical Specifications
t
ILIL
t
IRQ PIN
ILIH
t
IRQ
ILIH
1
.
.
.
IRQ
n
IRQ (INTERNAL)
Figure 10-6. External Interrupt Timing
OSC (NOTE 1)
RESET
t
RL
t
ILIH
IRQ (NOTE 2)
IRQ (NOTE 3)
4064 t
cyc
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
(NOTE 4)
07FE
07FE
07FE
07FE
07FF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
Figure 10-7. Stop Mode Recovery Timing
Technical Data
126
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-Volt Control Timing
V
DD
(NOTE 1)
4064 t
cyc
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
07FE
07FE
07FE
07FE
07FE
07FE
07FF
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 10-8. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
07FE
07FE
07FE
07FE
07FF
NEW PC
DUMMY
NEW PC
ADDRESS BUS
INTERNAL
DATA BUS
NEW
PCH
NEW
PCL
OP
CODE
t
RL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 10-9. External Reset Timing
MC68HC705J1A — Rev. 3.0
TechnicalData
127
MOTOROLA
Electrical Specifications
Electrical Specifications
Technical Data
128
MC68HC705J1A — Rev. 3.0
MOTOROLA
Electrical Specifications
Technical Data — MC68HC705J1A
Section 11. Mechanical Specifications
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
11.3 Plastic Dual In-Line Package (Case 738). . . . . . . . . . . . . . . .130
11.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .130
11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . .131
11.2 Introduction
The MC68HC705J1A, the resistor-capacitor (RC) oscillator, and
high-speed option devices described in Appendix A.
MC68HRC705J1A, Appendix B. MC68HSC705J1A, and Appendix C.
MC68HSR705J1A are available in the following packages:
• 738-03 — plastic dual in-line package (PDIP)
• 751D-04 — small outline integrated circuit (SOIC)
• 732-03 — ceramic DIP (cerdip) (windowed)
The figures shown here give the latest package information at the time
of this publication. To make sure that you have the latest package
specifications, contact one of these:
• Local Motorola Sales Office
• Motorola Mfax
– Phone 602-244-6609
– EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://www.mcu.motsps.com
Follow Mfax or Worldwide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Mechanical Specifications
129
Mechanical Specifications
11.3 Plastic Dual In-Line Package (Case 738)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MIN MAX
1.010 1.070 25.66 27.17
MILLIMETERS
DIM
A
B
C
D
E
MIN MAX
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
6.10
3.81
0.39
6.60
4.57
0.55
-T-
SEATING
PLANE
K
M
1.27 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
1.27
1.77
F
E
N
G
J
2.54 BSC
0.21
2.80
0.38
3.55
G
F
J
20 PL
K
L
7.62 BSC
0°
0.51
D
20 PL
M
M
0.25 (0.010)
T B
0°
0.020 0.040
15°
15°
1.01
M
N
M
M
T A
0.25 (0.010)
11.4 Small Outline Integrated Circuit (Case 751)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
-B-
P 10 PL
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
1
10
D 20 PL
J
MILLIMETERS
MIN MAX
12.65 12.95
INCHES
MIN MAX
M
S
S
0.010 (0.25)
T
A
B
DIM
A
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
B
7.40
2.35
0.35
0.50
7.60
2.65
0.49
0.90
F
C
D
F
R X 45°
1.27 BSC
G
J
0.25
0.10
0°
0.32
0.25
7°
0.010 0.012
0.004 0.009
K
C
M
P
0° 7°
0.395 0.415
10.05 10.55
0.25 0.75
-T-
SEATING
PLANE
R
0.010 0.029
M
K
G 18 PL
Technical Data
130
MC68HC705J1A — Rev. 3.0
MOTOROLA
Mechanical Specifications
Mechanical Specifications
Ceramic Dual In-Line Package (Case 732)
11.5 Ceramic Dual In-Line Package (Case 732)
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
INCHES
A
DIM MIN
MAX
A
B
C
D
F
G
H
J
K
L
M
N
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055 0.065
0.100 BSC
0.020 0.050
0.008 0.012
0.125 0.160
0.300 BSC
L
F
N
J
H
K
M
G
0
15
D
0.010 0.040
SEATING
PLANE
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
131
Mechanical Specifications
Mechanical Specifications
Technical Data
132
MC68HC705J1A — Rev. 3.0
MOTOROLA
Mechanical Specifications
Technical Data — MC68HC705J1A
Section 11.
Section 12. Ordering Information
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.2 Introduction
This section contains ordering information for the available package
types.
12.3 MCU Order Numbers
Table 12-1 lists the MC order numbers.
Table 12-1. Order Numbers
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
(1)
Order Number
(2)
MC68HC705J1AP
MC68HC705J1AC
0 to 70°C
–40 to +85°C
–40 to +105°C
(3)
PDIP
738-03
20
P
P
(4)
MC68HC705J1AV
(5)
0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HC705J1ADW
MC68HC705J1ACDW
MC68HC705J1AVDW
SOIC
751D-04
732-03
20
20
(6)
0 to 70°C
MC68HC705J1AS
Cerdip
–40 to +85°C
–40 to +105°C
MC68HC705J1ACS
MC68HC705J1AVS
1. Refer to Appendix A. MC68HRC705J1A, Appendix B. MC68HSC705J1A, and
Appendix C. MC68HSR705J1A for ordering information on optional high-speed and
resistor-capacitor oscillator devices.
2. P = Plastic dual in-line package (PDIP)
3. C = Extended temperature range
4. V = Automotive temperature range
5. DW = Small outline integrated circuit (SOIC)
6. S = Ceramic dual in-line package (cerdip)
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
133
Ordering Information
Technical Data
134
MC68HC705J1A — Rev. 3.0
MOTOROLA
Ordering Information
Technical Data — MC68HC705J1A
Appendix A. MC68HRC705J1A
A.1 Contents
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .136
A.4 Typical Internal Operating Frequency
for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .138
A.2 Introduction
This appendix introduces the MC68HRC705J1A, a resistor-capacitor
(RC) oscillator mask option version of the MC68HC705J1A. All of the
information in this document applies to the MC68HRC705J1A with the
exceptions given in this appendix.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
MC68HRC705J1A
135
MC68HRC705J1A
A.3 RC Oscillator Connections
For greater cost reduction, the RC oscillator mask option allows the
configuration shown in Figure A-1 to drive the on-chip oscillator. Mount
the RC components as close as possible to the pins for startup
stabilization and to minimize output distortion.
OSC1
R
OSC2
MCU
R
V
DD
C2 C1
V
SS
Figure A-1. RC Oscillator Connections
NOTE: The optional internal resistor is not recommended for configurations that
use the RC oscillator connections as shown in Figure A-1. For such
configurations, the oscillator internal resistor (OSCRES) bit of the mask
option register should be programmed to a logic 0.
Technical Data
136
MC68HC705J1A — Rev. 3.0
MC68HRC705J1A
MOTOROLA
MC68HRC705J1A
Typical Internal Operating Frequency for RC Oscillator Option
A.4 Typical Internal Operating Frequency for RC Oscillator Option
Figure A-2 shows typical internal operating frequencies at 25°C for the
RC oscillator option.
NOTE: Tolerance for resistance is ±50%. When selecting resistor size, consider
the tolerance to ensure that the resulting oscillator frequency does not
exceed the maximum operating frequency.
10
1
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
0.1
0.01
1
10
100
1000
10000
RESISTANCE (kΩ)
Figure A-2. Typical Internal Operating Frequency
for Various V at 25°C — RC Oscillator Option Only
DD
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
137
MC68HRC705J1A
MC68HRC705J1A
A.5 Package Types and Order Numbers
Table A-1. MC68HRC705J1A (RC Oscillator Option)
Order Numbers
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
(1)
Order Number
(2)
MC68HRC705J1AP
MC68HRC705J1AC
0 to 70°C
–40 to +85°C
–40 to +105°C
(3)
PDIP
738-03
20
P
P
(4)
MC68HRC705J1AV
(5)
0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HRC705J1ADW
MC68HRC705J1ACDW
MC68HRC705J1AVDW
SOIC
751D-04
732-03
20
20
(6)
0 to 70°C
MC68HRC705J1AS
Cerdip
–40 to +85°C
–40 to +105°C
MC68HRC705J1ACS
MC68HRC705J1AVS
1. Refer to Section 12. Ordering Information for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. V = automotive temperature range
5. DW = small outline integrated circuit (SOIC)
6. S = ceramic dual in-line package (cerdip)
Technical Data
138
MC68HC705J1A — Rev. 3.0
MOTOROLA
MC68HRC705J1A
Technical Data — MC68HC705J1A
Appendix B. MC68HSC705J1A
B.1 Contents
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .140
B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .140
B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .142
B.2 Introduction
This appendix introduces the MC68HSC705J1A, a high-speed version
of the MC68HC705J1A. All of the information in this document applies
to the MC68HSC705J1A with the exceptions given in this appendix.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
MC68HSC705J1A
139
MC68HSC705J1A
B.3 5.0-Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Supply current (f = 4.0 MHz)
OP
I
—
4.25
0.57
7.0
3.25
mA
Run
Wait
DD
B.4 3.3-Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Supply current (f = 2.1 MHz)
OP
I
—
1.4
0.28
4.25
1.75
mA
Run
Wait
DD
B.5 Typical Supply Currents
7.0 mA
6.0 mA
5.0 mA
SEE NOTE 1
5.5 V
SEE NOTE 2
4.0 mA
3.0 mA
4.5 V
2.0 mA
1.0 mA
0
3.6 V
3.0 V
0
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
INTERNAL OPERATING FREQUENCY (f
)
OP
Notes:
1. At VDD = 5.0 V, high-speed devices are specified and tested for
DD ≤ 7.0 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, high-speed devices are specified and tested for
DD ≤ 4.25 mA @ fOP = 2.1 MHz.
I
I
Figure B-1. Typical High-Speed Operating I (25°C)
DD
Technical Data
140
MC68HC705J1A — Rev. 3.0
MOTOROLA
MC68HSC705J1A
MC68HSC705J1A
Typical Supply Currents
SEE NOTE 1
5.5 V
SEE NOTE 2
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
0
4.5 V
3.6 V
3.0 V
0
1.0 MHz
2.0 MHz
3.0 MHz
4.0 MHz
INTERNAL OPERATING FREQUENCY (f
)
OP
Notes:
1. At VDD = 5.0 V, high-speed devices are specified and tested for
DD ≤ 3.25 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, high-speed devices are specified and tested for
DD ≤ 1.75 mA @ fOP = 2.1 MHz.
I
I
Figure B-2. Typical High-Speed Wait Mode I (25°C)
DD
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
141
MC68HSC705J1A
MC68HSC705J1A
B.6 Package Types and Order Numbers
Table B-1. MC68HSC705J1A (High Speed) Order Numbers
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
(1)
Order Number
(2)
0 to 70°C
–40 to +85°C
MC68HSC705J1AP
MC68HSC705J1AC
PDIP
SOIC
Cerdip
738-03
751D-04
732-03
20
20
20
(3)
P
(4)
0 to 70°C
–40 to +85°C
MC68HSC705J1ADW
MC68HSC705J1ACDW
(5)
0 to 70°C
–40 to +85°C
MC68HSC705J1AS
MC68HSC705J1ACS
1. Refer to Section 12. Ordering Information for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (cerdip)
Technical Data
142
MC68HC705J1A — Rev. 3.0
MOTOROLA
MC68HSC705J1A
Technical Data — MC68HC705J1A
Appendix C. MC68HSR705J1A
C.1 Contents
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . .143
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . .144
C.5 RC Oscillator Connections (No External Resistor) . . . . . . . . .145
C.6 Typical Internal Operating Frequency versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .147
C.2 Introduction
This appendix introduces the MC68HSR705J1A, a high-speed version
of the MC68HRC705J1A. All of the information in this document applies
to the MC68HSR705J1A with the exceptions given in this appendix.
C.3 RC Oscillator Connections (External Resistor)
Refer to Appendix A. MC68HRC705J1A for a description of the
resistor-capacitor (RC) oscillator connections with external resistor.
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
143
MC68HSR705J1A
MC68HSR705J1A
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option
10
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
1
10
100
1
RESISTANCE (kΩ)
Figure C-1. Typical Internal Operating Frequency
at 25°C for High-Speed RC Oscillator Option
For lower frequency operation characteristics, refer to Appendix A.
MC68HRC705J1A.
NOTE: Tolerance for resistance is ±50 percent. When selecting resistor size,
consider the tolerance to ensure that resulting oscillator frequency does
not exceed the maximum operating frequency.
Technical Data
144
MC68HC705J1A — Rev. 3.0
MC68HSR705J1A
MOTOROLA
MC68HSR705J1A
RC Oscillator Connections (No External Resistor)
C.5 RC Oscillator Connections (No External Resistor)
For maximum cost reduction, the RC oscillator mask connections shown
in Figure C-2 allow the on-chip oscillator to be driven with no external
components. This can be accomplished by programming the oscillator
internal resistor (OSCRES) bit in the mask option register to a logic 1.
When programming the OSCRES bit for the MC68HSR705J1A, an
internal resistor is selected which yields typical internal oscillator
frequencies as shown in Figure C-3. The internal resistance for this
device is different than the resistance of the selectable internal resistor
on the MC68HC705J1A and the MC68HSC705J1A devices.
NOTE: This option is not available on the ROM version of this device
(MC68HC05J1A).
OSC1
R
OSC2
MCU
V
DD
C2 C1
V
EXTERNAL CONNECTIONS LEFT OPEN
SS
Figure C-2. RC Oscillator Connections (No External Resistor)
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
MC68HSR705J1A
145
MC68HSR705J1A
C.6 Typical Internal Operating Frequency versus Temperature
(No External Resistor)
3.00
2.50
2.00
1.50
1.00
0.50
0.00
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
–50
0
50
100
150
TEMPERATURE (°C)
Figure C-3. Typical Internal Operating Frequency
versus Temperature (OSCRES Bit = 1)
NOTE: Due to process variations, operating voltages, and temperature
requirements, the internal resistance and tolerance are unspecified.
Typically for a given voltage and temperature, the frequency should not
vary more than ±500 kHz. However, this data is not guaranteed. It is the
user’s responsibility to ensure that the resulting internal operating
frequency meets the user’s requirements.
Technical Data
146
MC68HC705J1A — Rev. 3.0
MC68HSR705J1A
MOTOROLA
MC68HSR705J1A
Package Types and Order Numbers
C.7 Package Types and Order Numbers
Table C-1. MC68HSR705J1A (High-Speed
(1)
RC Oscillator Option) Order Numbers
Package
Type
Case
Outline
Pin
Count
Operating
Temperature
Order Number
(2)
0 to 70°C
–40 to +85°C
MC68HSR705J1AP
MC68HSR705J1AC
PDIP
SOIC
Cerdip
738-03
751D-04
732-03
20
20
20
(3)
P
(4)
0 to 70°C
–40 to +85°C
MC68HSR705J1ADW
MC68HSR705J1ACDW
(5)
0 to 70°C
–40 to +85°C
MC68HSR705J1AS
MC68HSR705J1ACS
1. Refer to Section 12. Ordering Information for standard part ordering information.
2. P = plastic dual in-line package (PDIP)
3. C = extended temperature range
4. DW = small outline integrated circuit (SOIC)
5. S = ceramic dual in-line package (cerdip)
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
147
MC68HSR705J1A
MC68HSR705J1A
Technical Data
148
MC68HC705J1A — Rev. 3.0
MOTOROLA
MC68HSR705J1A
Technical Data — MC68HC705J1A
Index
A
accumulator register (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
central processor unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
computer operating properly (COP) module . . . . . . . . . . . . . . . . . . . 95
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
COP in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
COP in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
COP reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
COPEN bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MC68HC705J1A — Rev. 3.0
MOTOROLA
Technical Data
Index
149
Index
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CPU registers
accumulator register (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
program counter register (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
D
data direction registers
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 88
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 91
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
E
ELAT bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 125
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 119, 120
driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 140
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 143
operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
EPGM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
EPMSEC bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EPROM
EPROM security programmable option . . . . . . . . . . . . . . . . . . . . 23
EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Technical Data
150
MC68HC705J1A — Rev. 3.0
Index
MOTOROLA
Index
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 38
programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
programming register (EPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 37
external interrupt module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
external interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
external reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
G
general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
H
H bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I
I bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
interrupts
external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 72
external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
external interrupt module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 105
external interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
interrupt flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 101
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IRQ module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . 104
IRQ/V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99, 102
PP
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Index
151
Index
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
optional external interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
pin sensitivity selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
pin triggering option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
port A external interrupts programmable option. . . . . . . . . . . . . . 23
real-time interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 75
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
software interrupt vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 110
timer overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
IRQ/V pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 96, 102
PP
IRQE bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
IRQF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
IRQR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
L
LEVEL bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
COP timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
data-retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 82
effects on clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
effects on COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
effects on CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
effects on EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
exiting stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
flowchart (stop/halt/wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Technical Data
152
MC68HC705J1A — Rev. 3.0
Index
MOTOROLA
Index
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77, 80
stop recovery timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
timing of stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
M
mask option register (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MC68HC705J1A
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MC68HRC705J1A (RC oscillator option) . . . . . . . . . . . . . . . . . . . . 135
operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . . . . 139
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
typical operating current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
typical wait mode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . . . . 143
operating frequencies (with OSCRES bit set) . . . . . . . . . . . . . . 146
operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EPROM/OTPROM programming. . . . . . . . . . . . . . . . . . . . . . . . . 36
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
mask option register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Index
153
Index
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MPGM bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
multifunction timer module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
N
N bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
O
opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
options (mask). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
options (programmable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
MC68HRC705J1A (RC oscillator option). . . . . . . . . . . . . . . . . . 138
MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 142
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 147
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 133, 138, 142, 147
OSC1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OSC2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
oscillator
crystal oscillator internal resistor option . . . . . . . . . . . . . . . . . . . . 23
delay counter programmable option. . . . . . . . . . . . . . . . . . . . . . . 23
on-chip oscillator stabilization delay. . . . . . . . . . . . . . . . . . . . . . . 69
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OSCRES bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
P
PA0–PA3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
parallel input/output (I/O) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PIRQ bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Technical Data
154
MC68HC705J1A — Rev. 3.0
Index
MOTOROLA
Index
port A
data direction register (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . 88
data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O pin interrupts (PA0–PA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
LED drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
pulldown register (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
port B
data direction register (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . 91
electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I/O circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
pulldown register (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
programming model (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
pulldown register A (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
pulldown register B (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
pulldown resistors
programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
registers
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . 86
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Index
155
Index
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28, 70
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
COP watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
external reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
power-on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 75
resistors (pulldown)
programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RT1, RT0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
RTIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
RTIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
RTIFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
S
Schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29, 102, 103
SOSCD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
stack pointer register (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 98, 104
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 98
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
stop recovery timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
stop/halt mode programmable option . . . . . . . . . . . . . . . . . . . . . . . . 23
SWAIT bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SWPDI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Technical Data
156
MC68HC705J1A — Rev. 3.0
Index
MOTOROLA
Index
T
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
timer
block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74, 110
low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
timer status and control register (TSCR) . . . . . . . . . . . . . . . . . . 110
TOF bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TOFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
V
V
V
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DD
SS
W
WAIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 98, 104
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Z
Z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MC68HC705J1A — Rev. 3.0
MOTOROLA
TechnicalData
Index
157
Index
Technical Data
158
MC68HC705J1A — Rev. 3.0
MOTOROLA
Index
MC68HC705J1A Rev. 3.0
Technical Data Book
Please help us to continue improving the quality and usefulness of our data books by
completing this form and sending your comments to us. You can return the form by mail
or FAX it to 512-891-3236.
Thank you for your help and continued support!
1. How do you rate the quality of this data book?
High
Low
High
Low
Organization
Readability
Accuracy
Tables
Table of contents
Page size/binding
Overall impression
Figures
2. Are you able to find the information you need easily?
Yes
No
3. What are your recommendations for making this data book more useful?
4. What additional information would you like to see included in future data books?
PLEASE
PASTE
POSTAGE
HERE
Motorola
6501 William Cannon Drive West
Mail Stop OE17
Austin, Texas 78735-8598
USA
Attention: MMD Publications Department
Second: fold back along this line
Please supply the following information (optional).
Name: ____________________________________________________________
Company Name: ____________________________________________________
Title: ______________________________________________________________
Address:___________________________________________________________
City: __________________________________________State:______Zip:_______
Phone Number: _____________________________________________________
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into
the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered trademarks of
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217.
1-303-675-2140 or 1-800-441-2447. Customer Focus Center, 1-800-521-6274
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku,
Tokyo 106-8573 Japan. 81-3-3440-8573
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong. 852-26668334
Mfax™, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/;
TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1999
MC68HC705J1A/ D
相关型号：
©2020 ICPDF网 联系我们和版权申明