MC74AC161D [MOTOROLA]
SYNCHRONOUS PRESETTABLE BINARY COUNTER; 同步可预置二进制计数器![MC74AC161D](http://pdffile.icpdf.com/pdf1/p00070/img/icpdf/MC74AC161D_368632_icpdf.jpg)
型号: | MC74AC161D |
厂家: | ![]() |
描述: | SYNCHRONOUS PRESETTABLE BINARY COUNTER |
文件: | 总12页 (文件大小:312K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SYNCHRONOUS
PRESETTABLE
BINARY COUNTER
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed
synchronous modulo-16 binary counters. They are synchronously presettable for
application in programmable dividers and have two types of Count Enable inputs
plus a Terminal Count output for versatility in forming synchronous multistage
counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input
that overrides all other inputs and forces the outputs LOW. The MC74AC163/
74ACT163 has a Synchronous Reset input that overrides counting and parallel
loading and allows the outputs to be simultaneously reset on the rising edge of
the clock.
N SUFFIX
CASE 648-08
PLASTIC
• Synchronous Counting and Loading
• High-Speed Synchronous Expansion
• Typical Count Rate of 125 MHz
• Outputs Source/Sink 24 mA
• ′ACT161 and ′ACT163 Have TTL Compatible Inputs
V
TC
15
Q
Q
Q
Q
3
CET
10
PE
9
CC
0
1
2
16
14
13
12
11
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
1
2
3
4
5
6
7
8
*R
CP
P
P
P
P
3
CEP GND
0
1
2
PE P
CEP
P
P
P
0
1
2 3
PIN NAMES
CET
CP
*R Q
TC
CEP
CET
CP
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Q Q Q
1 2 3
0
MR
SR
(′161) Asynchronous Master Reset Input
(′163) Synchronous Reset Input
Parallel Data Inputs
P –P
0
3
*MR for
*SR for
′
161
PE
Parallel Enable Input
′
163
Q –Q
TC
Flip-Flop Outputs
Terminal Count Output
0
3
FACT DATA
5-1
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
FUNCTIONAL DESCRIPTION
The MC74AC161/74ACT161 and MC74AC163/74ACT163
count modulo-16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip-flops are driven in parallel through a clock buffer. Thus all
changes of the Q outputs (except due to Master Reset of the
′161) occur as a result of, and synchronous with, the
LOW-to-HIGH transition of the CP input signal. The circuits
have four fundamental modes of operation, in order of
precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count-up and hold. Five control inputs —
Master Reset (MR, ′161), Synchronous Reset (SR, ′163),
Parallel Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET) determine the mode of operation, as
shown in the Mode Select Table. A LOW signal on MR
overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the next
rising edge of CP. A LOW signal on PE overrides counting and
(′161) or SR (′163) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or
CET inhibits counting.
The MC74AC161/74ACT161 and MC74AC163/74ACT163
use D-type edge-triggered flip-flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
TheTerminalCount(TC)outputisHIGHwhenCETisHIGH
and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways. Please refer to the
MC74AC568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers.
Logic Equations: Count Enable = CEP•CET•PE
TC = Q
0•Q1•Q2•Q3•CET
allowsinformationontheParallelData(P )inputstobeloaded
n
intotheflip-flopsonthenextrisingedgeofCP.WithPEandMR
STATE DIAGRAM
MODE SELECT TABLE
Action on the Rising
PE
*SR
CET
CEP Clock Edge ( )
0
1
2
3
4
5
6
7
8
L
X
L
H
H
H
X
X
H
L
X
X
H
X
L
Reset (Clear)
Load (P → Q )
Count (Increment)
No Change (Hold)
No Change (Hold)
15
14
13
12
H
H
H
H
n
n
X
*For ′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
11
10
9
LOGIC DIAGRAM
P
P
1
P
P
3
0
2
PE
′161
′163
CEP
CET
′
163
ONLY
TC
′
161
CP
CP
CP
ONLY
D
D
CP
Q
D
Q
C
DETAIL A
DETAIL A
DETAIL A
Q
0
Q
0
DETAIL A
MR
SR
′
′
161
163
Q
3
Q
2
Q
Q
1
0
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
FACT DATA
5-2
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
V
V
V
–0.5 to +7.0
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to V
+0.5
V
in
CC
V
out
–0.5 to V
+0.5
V
CC
I
I
I
±20
mA
mA
mA
°C
in
DC Output Sink/Source Current, per Pin
±50
±50
out
CC
DC V
or GND Current per Output Pin
Storage Temperature
CC
T
stg
–65 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
Max
6.0
Unit
V
′AC
V
Supply Voltage
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
150
40
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
ns/V
t , t
r f
25
10
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
r f
ns/V
8.0
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current — High
140
85
°C
°C
J
T
A
–40
25
I
I
–24
24
mA
mA
OH
Output Current — Low
OL
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
FACT DATA
5-3
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
DC CHARACTERISTICS
74AC
= +25°C
74AC
T
A
=
V
(V)
CC
Symbol
Parameter
Unit
Conditions
T
A
–40°C to +85°C
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
– 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V
CC
= 0.1 V
OUT
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
–12 mA
–24 mA
–24 mA
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
I
IN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
µA
V = V , GND
I
CC
I
I
I
5.5
5.5
75
mA
mA
V
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
–75
= 3.85 V Min
OHD
Maximum Quiescent
Supply Current
5.5
8.0
80
µA
V
IN
= V or GND
CC
* All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
Note: I and I
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
IN CC
CC
FACT DATA
5-4
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74AC161
74AC161
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
Unit
L
C
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
3.3
5.0
70
110
111
167
60
95
f
t
t
t
t
t
t
t
t
MHz
ns
3-3
3-6
3-6
3-6
3-6
3-6
3-6
3-6
3-6
max
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
3.3
5.0
2.0
1.5
7.0
5.0
12.0
9.0
1.5
1.0
13.5
9.5
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PHL
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
3.3
5.0
1.5
1.5
7.0
5.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.0
6.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
8.5
6.5
14.0
11.0
2.5
2.0
15.5
11.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
5.5
3.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
6.5
5.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
Propagation Delay
3.3
5.0
2.0
1.5
6.0
5.5
12.0
9.5
1.5
1.5
13.5
10.0
ns
MR to Q
n
Propagation Delay
MR to TC
3.3
5.0
3.5
2.5
10.0
8.5
15.0
13.0
3.0
2.5
17.5
13.5
ns
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74AC163
74AC163
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
Unit
L
C
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
3.3
5.0
70
110
95
140
60
95
f
t
t
t
t
t
t
MHz
ns
3-3
3-6
3-6
3-6
3-6
3-6
3-6
max
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
3.3
5.0
2.0
1.5
7.5
5.5
12.5
9.0
1.5
1.0
13.5
9.5
PLH
PHL
PLH
PHL
PLH
PHL
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
3.3
5.0
1.5
1.5
8.5
6.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.5
7.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
11.0
8.0
14.0
11.0
2.5
2.0
15.5
11.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
7.5
5.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
8.5
6.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-5
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74AC161
74AC161
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
= 50 pF
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
to CP
3.3
5.0
6.0
3.5
13.5
8.5
16.0
10.5
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-9
3-9
3-9
3-9
3-9
3-9
3-6
3-6
3-6
3-9
s
P
n
Hold Time, HIGH or LOW
to CP
3.3
5.0
–7.0
–4.0
–1.0
0
–0.5
0
h
s
P
n
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
6.5
4.0
11.5
7.5
14.0
8.5
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
–6.0
–3.5
0
0.5
0
1.0
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.0
2.0
6.0
4.5
7.0
5.0
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
–3.5
–2.0
0
0
0
0.5
h
w
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
2.0
2.0
3.5
2.5
4.0
3.0
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
2.0
2.0
4.0
3.0
4.5
3.5
3.3
5.0
3.0
2.5
5.5
4.5
7.5
6.0
MR Pulse Width, LOW
Recovery TIme
MR to CP
3.3
5.0
–2.0
–1.0
–0.5
0
0
0.5
rec
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-6
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74AC163
74AC163
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
= 50 pF
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
to CP
3.3
5.0
5.5
4.0
13.5
8.5
16.0
10.5
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-6
3-6
s
P
n
Hold Time, HIGH or LOW
to CP
3.3
5.0
–7.0
–5.0
–1.0
0
–0.5
0
h
s
P
n
Setup Time, HIGH or LOW
SR to CP
3.3
5.0
5.5
4.0
14
9.5
16.5
11.0
Hold Time, HIGH or LOW
SR to CP
3.3
5.0
–7.5
–5.5
–1.0
–0.5
–0.5
0
h
s
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
5.5
4.0
11.5
7.5
14.0
8.5
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
–7.5
–5.0
–1.0
–0.5
–0.5
0
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.5
2.5
6.0
4.5
7.0
5.0
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
–4.5
–3.0
0
0
0
0.5
h
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
3.0
2.0
3.5
2.5
4.0
3.0
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
3.0
2.0
4.0
3.0
4.5
3.5
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-7
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
DC CHARACTERISTICS
74ACT
= +25°C
74ACT
T
A
=
V
(V)
CC
Symbol
Parameter
Unit
Conditions
T
A
–40°C to +85°C
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
– 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V
CC
= 0.1 V
OUT
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
Maximum Low Level
Input Voltage
IL
or V
– 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= –50 µA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IN IL IH
4.5
5.5
3.86
4.86
3.76
4.76
V
V
–24 mA
–24 mA
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
I = 50 µA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN IL
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
24 mA
I
OL
24 mA
I
IN
Maximum Input
Leakage Current
5.5
±0.1
±1.0
µA
V = V , GND
I
CC
∆I
Additional Max. I /Input
CC
5.5
5.5
5.5
0.6
1.5
75
mA
mA
mA
V = V
I
– 2.1 V
CCT
CC
I
V
= 1.65 V Max
= 3.85 V Min
OHD
†Minimum Dynamic
Output Current
OLD
OLD
I
–75
V
V
OHD
CC
I
Maximum Quiescent
Supply Current
5.5
8.0
80
µA
= V or GND
CC
IN
* All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
FACT DATA
5-8
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT161
74ACT161
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
Unit
L
C
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
f
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
115
125
100
MHz
ns
3-3
3-6
3-6
3-6
3-6
3-6
3-6
3-6
3-6
max
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
1.5
1.5
2.0
1.5
1.5
1.5
1.5
2.5
8.0
8.0
9.5
10.5
11.0
12.5
8.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
10.5
11.5
12.5
13.5
10.0
10.5
11.0
14.5
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PHL
Propagation Delay
ns
CP or Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
11.0
11.0
7.5
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
8.0
9.5
ns
Propagation Delay
8.0
10.0
13.5
ns
MR to Q
n
Propagation Delay
MR to TC
10.0
ns
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms — See Section 3)
74ACT163
74ACT163
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
Unit
L
C
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Count
Frequency
f
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
140
105
MHz
ns
3-3
3-6
3-6
3-6
3-6
3-6
3-6
max
Propagation Delay
CP to Q (PE Input HIGH or LOW)
n
1.5
1.5
2.5
3.0
2.0
2.0
5.5
6.0
7.0
8.0
5.5
6.0
10.0
11.0
11.5
13.5
9.0
1.5
1.5
2.0
2.0
1.5
2.0
11.0
12.0
13.5
15.0
10.5
11.0
PLH
PHL
PLH
PHL
PLH
PHL
Propagation Delay
ns
CP to Q (PE Input HIGH or LOW)
n
Propagation Delay
CP to TC
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
10.0
ns
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-9
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74ACT161
74ACT161
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
= 50 pF
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
to CP
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
7.0
9.5
0
11.5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-9
3-9
3-9
3-9
3-9
3-9
3-6
3-6
3-6
3-9
s
P
n
Hold Time, HIGH or LOW
to CP
–3.0
6.0
–3.5
4.0
–2.0
2.0
2.0
3.0
0
h
s
P
n
Setup Time, HIGH or LOW
PE to CP
8.5
– 0.5
5.5
0
9.5
– 0.5
6.5
0
Hold Time, HIGH or LOW
PE to CP
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
h
w
w
w
Clock Pulse Width (Load)
HIGH or LOW
3.0
3.0
3.0
0
3.5
3.5
7.5
0.5
Clock Pulse Width (Count)
HIGH or LOW
MR Pulse Width, LOW
Recovery Time
MR to CP
rec
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
FACT DATA
5-10
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
AC OPERATING REQUIREMENTS
74ACT163
74ACT163
= –40°C
T
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
Symbol
Parameter
to +85°C
= 50 pF
Unit
L
C
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
to CP
t
t
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
10.0
0.5
10.0
–0.5
8.5
–0.5
5.5
0
12.0
0.5
11.5
–0.5
10.5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-9
3-6
3-6
s
P
n
Hold Time, HIGH or LOW
to CP
–5.0
4.0
h
s
P
n
Setup Time, HIGH or LOW
SR to CP
Hold Time, HIGH or LOW
SR to CP
–5.5
4.0
h
s
Setup Time, HIGH or LOW
PE to CP
Hold Time, HIGH or LOW
PE to CP
–5.5
2.5
h
s
Setup Time, HIGH or LOW
CEP or CET to CP
6.5
0.5
3.5
3.5
Hold Time, HIGH or LOW
CEP or CET to CP
–3.0
2.0
h
w
w
Clock Pulse Width
HIGH or LOW
3.5
3.5
Clock Pulse Width (Count)
HIGH or LOW
2.0
* Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Value
Parameter
Unit
Test Conditions
Typ
4.5
45
C
C
Input Capacitance
Power Dissipation Capacitance
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
PD
CC
FACT DATA
5-11
MC74AC161 MC74ACT161 MC74AC163 MC74ACT163
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
NOTES:
CASE 648–08
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
ISSUE R
16
1
9
8
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T
A
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–B–
P 8 PL
M
S
0.25 (0.010)
B
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
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JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
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