MC74F256N [MOTOROLA]
DUAL 4-BIT ADDRESSABLE LATCH; 双4位可寻址锁存器
| 型号： | MC74F256N |
| 厂家： | 
MOTOROLA |
| 描述： | DUAL 4-BIT ADDRESSABLE LATCH |
| 文件： | 总4页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC54/74F256
DUAL 4-BIT
ADDRESSABLE LATCH
TheMC54/74F256dualaddressablelatchhasfourdistinctmodesofopera-
tion which are selectable by controlling the Clear and Enable inputs (see
Function Table). In the addressable latch mode, data at the Data (D) inputs
is written into the addressed latches. The addressed latches will follow the
Data input with all unaddressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous states and are un-
affected by the Data or Address inputs. To eliminate the possibility of entering
erroneousdata in the latches, the enable should be held HIGH (inactive)while
the address lines are changing. In the dual 1-of-4 decoding or demultiplexing
mode (MR = E = LOW), addressed outputs will follow the level of the D inputs
with all other outputs LOW. In the clear mode, all outputs are LOW and unef-
fected by the Address and Data inputs.
DUAL 4-BIT
ADDRESSABLE LATCH
FAST SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
• Combines Dual Demultiplexer and 8-Bit Latch
• Serial-to-Parallel Capability
• Output from Each Storage Bit Available
16
1
• Random (Addressable) Data Entry
• Easily Expandable
• Common Clear Input
• Useful as Dual 1-of-4 Active HIGH Decoder
N SUFFIX
PLASTIC
CASE 648-08
16
CONNECTION DIAGRAM
1
V
MR
15
E
D
Q
Q
Q
Q
0b
CC
16
b
3b
12
2b
11
1b
10
14
13
9
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
1
2
3
4
5
6
8
7
MC54FXXXJ
MC74FXXXN Plastic
MC74FXXXD SOIC
Ceramic
A
A
D
Q
Q
Q
Q
3a
GND
0
1
a
0a
1a
2a
FUNCTION TABLE
Inputs
Outputs
Operating Mode
MR
E
D
A
A
Q
Q
Q
Q
3
0
1
0
1
2
LOGIC SYMBOL
Master Reset
L
H
X
X
X
L
L
L
L
3
13
L
L
L
L
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
Q=d
L
Q=d
L
L
L
Q=d
L
L
L
L
Demultiplex (Active
HIGH Decoder when
D = H)
L
L
L
D
D
b
a
A
E
14
15
1
2
0
H
L
Q=d
A
MR
Store (Do Nothing)
H
H
X
X
X
q
0
q
q
2
q
3
1
1
1
Q
Q
Q
Q
Q
Q
Q
Q
0a 1a 2a 3a 0b 1b 2b 3b
H
H
H
H
L
L
L
L
d
d
d
d
L
H
L
L
L
H
H
Q=d
q
q
2
q
2
q
3
q
3
q
3
Addressable
Latch
q
0
q
0
q
0
Q=d
4
5
6
7
9
10 11 12
q
1
q
1
Q=d
H
q
2
Q=d
H = HIGH Voltage Level Steady State
L = LOW Voltage Level Steady State
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW-to-HIGH Enable transition.
q = Lower case letters indicate the state of the referenced output established during the last cycle
in which it was addressed or cleared.
FAST AND LS TTL DATA
4-123
MC54/74F256
LOGIC DIAGRAM
E
D
A
A
MR
D
b
a
0
1
Q
Q
Q
Q
Q
Q
Q
Q
3b
0a
1a
2a
3a
0b
1b
2b
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
4.5
–55
0
Typ
5.0
25
Max
5.5
125
70
Unit
V
Supply Voltage
54, 74
54
V
CC
T
Operating Ambient Temperature Range
°C
A
74
25
I
I
Output Current — High
Output Current — Low
54, 74
54, 74
–1.0
20
mA
mA
OH
OL
FAST AND LS TTL DATA
4-124
MC54/74F256
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Unit
V
Test Conditions
V
V
V
2.0
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
IH
Input LOW Voltage
0.8
V
IL
Input Clamp Diode Voltage
–1.2
V
V = MIN, I = –18 mA
CC IN
IK
54, 74
74
2.5
2.7
V
I
I
I
= –1.0 mA
V
V
V
= MIN
OL
OL
OL
CC
CC
CC
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input LOW Current
OH
OL
V
= –1.0 mA
= 20 mA
= 4.75 V
= MIN
V
0.5
20
V
µA
mA
mA
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
I
IH
0.1
= MAX, V = 7.0 V
IN
I
I
–0.6
= MAX, V = 0.5 V
IN
IL
Output Short Circuit Current
(Note 2)
–60
–150
mA
V
= MAX, V
= 0 V
OS
CC
OUT
Power Supply Current
Total, Output HIGH
Total, Output LOW
42
60
mA
mA
V
V
= MAX
= MAX
CC
I
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-125
MC54/74F256
AC CHARACTERISTICS
54/74F
54F
= –55 to +125°C
74F
T
= +25°C
T
A
T = 0 to 70°C
A
A
V
C
= +5.0 V
= 50 pF
V
= 5.0 V ±10%
V
CC
C
= 5.0 V ± 5%
= 50 pF
L
CC
L
CC
C
= 50 pF
L
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Propagation Delay
E to Q
Unit
t
t
4.0
3.0
10.5
7.0
4.0
3.0
13
8.5
4.0
3.0
12
7.5
PLH
PHL
ns
n
t
t
Propagation Delay
to Q
3.5
3.0
9.0
7.0
3.5
2.5
11.5
8.5
3.5
2.5
10
7.5
PLH
PHL
ns
ns
ns
D
n
n
t
t
Propagation Delay
to Q
3.5
4.0
14
9.5
3.5
4.0
15.5
11
3.5
4.0
14.5
10
PLH
PHL
A
n
n
Propagation Delay
MR to Q
t
5.0
9.0
4.5
11.5
4.5
10
PHL
n
AC OPERATING REQUIREMENTS
54/74F
= +25°C
54F
= –55 to +125°C
74F
T
V
T
V
T = 0 to 70°C
A
A
A
Unit
= +5.0 V
= 5.0 V ±10%
V
CC
= 5.0 V ± 5%
CC
CC
Min
Max
Min
Max
Min
Max
Symbol
t (H)
t (L)
s
Parameter
Setup Time, HIGH or LOW
4.0
4.0
5.0
5.0
4.0
4.0
s
ns
ns
ns
ns
D to E
n
t (H)
t (L)
h
Hold Time, HIGH or LOW
D to E
n
2.0
2.0
2.0
2.0
2.0
2.0
h
t (H)
Setup Time, HIGH or LOW
(a)
A to E
4.0
4.0
4.0
4.0
4.0
4.0
s
t (L)
s
t (H)
Hold Time HIGH or LOW
0
0
0
0
0
0
h
(b)
A to E
t (L)
h
t
E Pulse Width
4.0
4.0
4.0
4.0
4.0
4.0
ns
ns
W
W
t
MR Pulse Width
NOTES:
1. The Address to Enable setup time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
1. addressed and the other latches are not affected.
2. The Address to Enable hold time is the time after the LOW-to-HIGH Enable transition that the Address must be stable so that the correct latch is addressed
1. and the other latches are not affected.
FAST AND LS TTL DATA
4-126
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