MC74HC365ND [MOTOROLA]
HC/UH SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16;
| 型号： | MC74HC365ND |
| 厂家： | 
MOTOROLA |
| 描述： | HC/UH SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16 |
| 文件： | 总6页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
High–Performance Silicon–Gate CMOS
16
16
The MC54/74HC365 is identical in pinout to the LS365. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is a high–speed hex buffer with 3–state outputs and two
common active–low Output Enables. When either of the enables is high, the
buffer outputs are placed into high–impedance states. The HC365 has
noninverting outputs.
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
Low Input Current: 1 µA
16
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
ORDERING INFORMATION
•
Chip Complexity: 90 FETs or 22.5 Equivalent Gates
MC54HCXXXJ
Ceramic
Plastic
TSSOP
MC74HCXXXN
MC74HCXXXDT
LOGIC DIAGRAM
2
3
5
7
A0
A1
A2
A3
A4
A5
Y0
Y1
Y2
Y3
Y4
Y5
PIN ASSIGNMENT
OUTPUT
4
1
2
16
15
V
CC
OUTPUT
ENABLE 2
ENABLE 1
A0
6
Y0
A1
3
4
5
6
7
8
14
13
12
11
10
9
A5
Y5
A4
Y4
A3
Y3
10
12
14
9
Y1
A2
11
13
Y2
GND
1
15
OUTPUT ENABLE 1
OUTPUT ENABLE 2
PIN 16 = V
PIN 8 = GND
CC
FUNCTION TABLE
Inputs
Output
Y
Enable Enable
1
2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = don’t care
Z = high impedance
10/95
REV 6
Motorola, Inc. 1995
MC54/74HC365
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
TSSOP Package†
750
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
= V – 0.1 V
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
20 µA
|I
|
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
IH
20 µA
|I
|
out
V
in
= V
|I
|I
|
|
6.0 mA
7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH
out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V
|
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IL
20 µA
|I
out
V
= V
|I
|I
|
|
6.0 mA
7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IL
out
out
I
in
Maximum Input Leakage Current
V
= V
or GND
6.0
± 0.1
± 1.0
± 1.0
µA
CC
MOTOROLA
2
MC54/74HC365
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
6.0
± 0.5
± 5.0
± 10
µA
OZ
V
V
= V or V
= V or GND
in
IL IH
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0 µA
or GND
6.0
8
80
160
µA
CC
in
I
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
PLH
PHL
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
ns
ns
PLZ
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
PZL
PZH
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
TLH
THL
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
40
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
SWITCHING WAVEFORMS
V
CC
50%
t
t
f
r
OUTPUT ENABLE
GND
V
CC
90%
50%
10%
t
t
PLZ
PZL
INPUT A
HIGH
GND
IMPEDANCE
50%
t
t
PHL
PLH
OUTPUT Y
OUTPUT Y
10%
90%
V
V
OL
90%
50%
10%
t
t
PHZ
PZH
OUTPUT Y
OH
50%
HIGH
IMPEDANCE
t
t
THL
TLH
Figure 1.
Figure 2.
3
MOTOROLA
MC54/74HC365
TEST CIRCUITS
TEST POINT
TEST POINT
1 k
OUTPUT
CONNECT TO V
WHEN
CC
Ω
OUTPUT
TESTING t
PLZ
AND t .
PZL
DEVICE
DEVICE
CONNECT TO GND WHEN
TESTING t AND t
UNDER
TEST
UNDER
TEST
.
PHZ PZH
C *
C *
L
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3.
Figure 4.
LOGIC DETAIL
TO OTHERS
FIVE BUFFERS
ONE OF 6
BUFFERS
V
CC
Y
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
MOTOROLA
4
MC54/74HC365
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
NOTES:
16
1
9
8
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
–B
–
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
—
0.39
1.27 BSC
MAX
19.93
7.49
5.08
0.50
0.750
0.240
—
0.015
0.050 BSC
–T
SEAT
–
ING
N
K
PLANE
F
G
J
K
L
M
N
0.055
0.100 BSC
0.008
0.125
0.065
1.40
2.54 BSC
0.21
3.18
1.65
E
M
0.015
0.170
0.38
4.31
J 16 PL
F
G
0.300 BSC
15
0.040
7.62 BSC
15
1.01
0.51
M
S
0.25 (0.010)
T
B
D 16 PL
°
°
0°
0°
M
S
0.25 (0.010)
T
A
0.020
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A
–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
9
B
1
8
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
F
C
L
0.740
0.250
0.145
0.015
0.040
S
0.070
1.77
SEATING
PLANE
–T
0.100 BSC
0.050 BSC
0.015
0.130
0.305
2.54 BSC
1.27 BSC
0.38
3.30
7.74
–
M
K
0.008
0.110
0.295
0.21
2.80
7.50
H
J
G
D 16 PL
0.25 (0.010)
M
S
0°
10°
0°
10°
M
M
T
A
0.020
0.040
0.51
1.01
5
MOTOROLA
MC54/74HC365
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
0.10 (0.004)
M
S
S
T
U
V
NOTES:
S
0.15 (0.006) T
U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
B
–U–
SECTION N–N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T
U
A
M
MILLIMETERS
INCHES
–V–
DIM
A
B
C
D
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
0.193
0.169
–––
0.002
0.020
F
F
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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CODELINE
MC54/74HC365/D
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