MC74HC4514DWD [MOTOROLA]
Decoder/Driver, CMOS, PDSO24;
| 型号： | MC74HC4514DWD |
| 厂家： | 
MOTOROLA |
| 描述： | Decoder/Driver, CMOS, PDSO24 解码器 解复用器 |
| 文件： | 总9页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
The MC74HC4514 is identical in pinout to the MC14514B metal–gate
CMOS device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors; they are compatible with LSTTL outputs.
This device consists of a 4–bit storage latch with a Latch Enable and Chip
Select input. When a low signal is applied to the Latch Enable input, the
Address is stored, and decoded. When the Chip Select input is high, all
sixteen outputs are forced to a low level.
24
1
DW SUFFIX
SOIC PACKAGE
CASE 751E–04
24
1
The Chip Select input is provided to facilitate the chip–select, demultiplex-
ing, and cascading functions.
ORDERING INFORMATION
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using the Chip Select as a
data input.
MC74HCXXXXN
MC74HCXXXXDW
Plastic
SOIC
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
PIN ASSIGNMENT
Low Input Current: 1 µA
LATCH
1
2
3
4
5
6
24
23
22
21
20
19
V
CC
ENABLE
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
CHIP
A0
A1
Y7
Y6
Y5
SELECT
A3
•
Chip Complexity: 268 FETs or 67 Equivalent Gates
A2
Y10
Y11
LOGIC DIAGRAM
Y4
Y3
7
18
17
16
15
14
13
Y8
8
Y9
11
Y1
9
Y14
Y15
Y12
Y13
Y0
9
Y1
Y2
10
11
12
10
Y2
8
Y0
Y3
7
Y4
6
GND
2
3
Y5
Y6
Y7
Y8
Y9
A0
A1
A2
A3
5
4
BINARY
ADDRESS
INPUTS
4–BIT
STORAGE
LATCH
4–TO–16
LINE
DECODER
ACTIVE–HIGH
OUTPUTS
18
17
20
19
14
13
16
21
Y10
Y11
Y12
LATCH
1
Y13
Y14
Y15
ENABLE
15
CHIP
SELECT
PIN 24 = V
CC
PIN 12 = GND
10/95
REV 6
Motorola, Inc. 1995
MC74HC4514
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 1.5 to V
+ 1.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 25
± 50
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
CC
and GND Pins
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
0
V
CC
V
T
A
– 55 + 125
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
out
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
IL
out
CC
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
in
|I
|
20 µA
out
V
in
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
IH IL out
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
|I
|I
|
|
4.0 mA
5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
in
in
IH IL out
out
I
Maximum Input Leakage Current
V
V
= V
= V
or GND
6.0
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
CC
I
Maximum Quiescent Supply
Current (per Package)
or GND
8
80
160
CC
in
CC
I
= 0 µA
out
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
MC74HC4514
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
,
Maximum Propagation Delay, Chip Select to Output Y
(Figures 1 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
PLH
PHL
t
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 5)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
ns
PLH
t
t
t
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
PHL
PLH
PHL
Maximum Propagation Delay, Latch Enable to Output Y
(Figures 3 and 5)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
TLH
THL
C
Maximum Input Capacitance
—
10
10
10
pF
in
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Package)*
pF
70
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V
. For load considerations, see Chapter 2 of the
PD CC
CC CC
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Input A to Latch Enable
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
Minimum Hold Time, Latch Enable to Input A
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
h
t
w
Minimum Pulse Width, Latch Enable
(Figure 3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
t , t
r
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
f
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC74HC4514
SWITCHING WAVEFORMS
t
t
r
f
V
CC
90%
VALID
VALID
CHIP
SELECT
50%
10%
V
CC
GND
INPUT A
50%
t
t
PHL
PLH
GND
90%
50%
10%
t
t
PHL
PLH
OUTPUT Y
50%
OUTPUT Y
t
t
THL
TLH
Figure 1.
Figure 2.
VALID
t
w
V
CC
V
CC
INPUT A
50%
LATCH
ENABLE
50%
50%
GND
t
GND
t
su
h
t
t
PHL
PLH
V
CC
LATCH
ENABLE
50%
50%
OUTPUT Y
GND
Figure 3.
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 5. Test Circuit
MOTOROLA
4
MC74HC4514
FUNCTION TABLE
Address Inputs
PIN DESCRIPTIONS
Selected
Output
(High)
ADDRESS INPUTS
Latch
Chip
Enable Select
A0, A1, A2, A3 (Pins 2, 3, 21, 22)
A3 A2 A1 A0
Address Inputs. These inputs are decoded to produce a
high level on one of 16 outputs. The inputs are arranged
such that A3 is the most–significant bit and A0 is the least–
significant bit. The decimal equivalent of the binary input
address indicates which of the 16 data outputs, Y0–Y15, is
selected.
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
Y0
Y1
Y2
Y3
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
Y4
Y5
Y6
Y7
OUTPUTS
H
Y0 – Y15 (Pins 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14,
13, 16, 15)
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
Y8
Y9
Y10
Y11
Active–High Outputs. These outputs produce a high level
when selected (Latch Enable = H, Chip Select = L) and are at
a low level when not selected.
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
Y12
Y13
Y14
Y15
CONTROL INPUTS
Latch Enable (Pin 1)
H
Latch Enable Input. A low level on this input stores the
data on the Address data inputs in the 4–bit latch. A high
level on the Latch Enable input makes the latch transparent
and allows the outputs to follow the inputs. Note that the data
is latched only while the Latch Enable input is at a low level.
All
Outputs = L
X
L
H
L
X
X
X
X
X
X
X
X
Latched
Data
Chip Select (Pin 23)
Chip Select Input. A high on this input produces a low level
on all outputs, regardless of what appears at the address or
Latch Enable inputs. A low level on the Chip Select input
allows the selected output to produce a high level.
TIMING DIAGRAM
INPUT A
LATCH ENABLE
CHIP SELECT
OUTPUT Y
5
MOTOROLA
MC74HC4514
EXPANDED LOGIC DIAGRAM
Y0
11
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
Y1
9
Y2
10
2
A0
DATA
Q
Y3
8
Y4
7
LE
Q
Q
Y5
6
3
A1
DATA
Y6
5
Y7
4
Q
Q
LE
Y8
18
21
A2
DATA
Y9
17
Y10
20
Q
Q
LE
Y11
19
22
A3
DATA
Y12
14
Y13
13
LATCH
ENABLE
1
Q
LE
Y14
16
Y15
15
CHIP
23
SELECT
MOTOROLA
6
MC74HC4514
MICROPROCESSOR MEMORY DECODING
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
0000–00FF
0100–01FF
0200–02FF
0300–03FF
0400–04FF
0500–05FF
0600–06FF
0700–07FF
0800–08FF
0900–09FF
0A00–0AFF
0B00–0BFF
0C00–0CFF
0D00–0DFF
CHIP
SELECT
A12
A11
A10
A9
A3
A2
A1
A0
Y9
Y10
Y11
Y12
Y13
A8
LATCH
ENABLE
+ V
Y14
Y15
0E00–0EFF
0F00–0FFF
TO DEVICE SELECTS
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1000–10FF
1100–11FF
1200–12FF
1300–13FF
1400–14FF
1500–15FF
1600–16FF
1700–17FF
1800–18FF
1900–19FF
1A00–1AFF
1B00–1BFF
1C00–1CFF
1D00–1DFF
1E00–1EFF
1F00–1FFF
HC04
CHIP
SELECT
A3
A2
A1
A0
Y9
Y10
Y11
Y12
Y13
Y14
Y15
LATCH
ENABLE
+ V
7
MOTOROLA
MC74HC4514
CODE TO CODE CONVERSION — HEXADECIMAL TO BCD
+ V
Y0
Y1
Y2
Y3
COMMON CATHODE LEDs
A3
A2
A1
A0
Y4
Y5
Y6
Y7
Y8
Y9
LATCH
Y10
Y11
Y12
Y13
Y14
Y15
ENABLE
R = 2 k
CHIP
SELECT
GND
A3
A2
A1
A0
ALL DIODES GENERAL
PURPOSE GERMANIUM
R = 10 k
R = 2 kΩ
HC4050
HC4050
MOTOROLA
8
MC74HC4514
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 724–03
ISSUE D
–A–
NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
24
1
13
12
–B–
4. CONTROLLING DIMENSION: INCH.
INCHES
MILLIMETERS
L
DIM
A
B
C
D
E
MIN
MAX
1.265
0.270
0.175
0.020
MIN
31.25
6.35
3.69
0.38
MAX
32.13
6.85
4.44
0.51
C
1.230
0.250
0.145
0.015
NOTE 1
–T–
SEATING
PLANE
K
0.050 BSC
1.27 BSC
F
G
J
K
L
M
N
0.040
0.100 BSC
0.007
0.110
0.300 BSC
0.060
1.02
2.54 BSC
0.18
2.80
7.62 BSC
1.52
N
M
E
0.012
0.140
0.30
3.55
G
J 24 PL
F
M
M
0.25 (0.010)
T
B
D 24 PL
0
15
0.040
0
0.51
15
1.01
0.020
M
M
0.25 (0.010)
T A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
–A–
NOTES:
24
13
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
F
R X 45
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
–T–
SEATING
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com –TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CODELINE
MC74HC4514/D
◊
相关型号：
MC74HC4514DWR2
HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDSO24, 0.300 INCH, PLASTIC, SOIC-24
MOTOROLA
©2020 ICPDF网 联系我们和版权申明