MC74HCT373ADWD [MOTOROLA]
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SOIC-20;
| 型号： | MC74HCT373ADWD |
| 厂家： | 
MOTOROLA |
| 描述： | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SOIC-20 锁存器 |
| 文件： | 总8页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
20
High–Performance Silicon–Gate CMOS
The MC54/74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D–type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs. When
Latch Enable is taken low, data meeting the setup and hold times
becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high–impedance state.
Thus, data may be latched even when the outputs are not enabled.
The HCT373A is identical in function to the HCT573A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT533A, which has inverting outputs.
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
20
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW
MC74HCTXXXASD
MC74HCTXXXADT
Ceramic
Plastic
SOIC
SSOP
TSSOP
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 196 FETs or 49 Equivalent Gates
LOGIC DIAGRAM
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
20
V
CC
3
2
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
2
3
19
18
Q7
D7
4
D0
D1
6
7
4
17
D6
8
9
Q1
Q2
5
16
15
14
13
12
11
Q6
Q5
D5
D4
Q4
DATA
INPUTS
NONINVERTING
OUTPUTS
6
13
12
15
16
19
D2
7
14
17
18
D5
D6
D7
D3
8
Q3
9
LATCH
ENABLE
GND
10
11
1
PIN 20 = V
CC
PIN 10 = GND
LATCH ENABLE
OUTPUT ENABLE
FUNCTION TABLE
Inputs
Output
Design Criteria
Internal Gate Count*
Value
49
Units
ea.
ns
Output Latch
Enable Enable
D
Q
L
L
L
H
H
L
H
L
X
X
H
Internal Gate Propagation Delay
Internal Gate Power Dissipation
1.5
L
No Change
Z
5.0
µW
pJ
H
X
X = don’t care
Z = high impedance
Speed Power Product
.0075
* Equivalent to a two–input NAND gate.
2/97
REV 7
Motorola, Inc. 1997
MC54/74HCT373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
V
out
– 0.5 to V
+ 0.5
V
CC
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
.
DC Supply Current, V
and GND Pins
CC
in out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
450
level (e.g., either GND or V ).
CC
SSOP or TSSOP Package†
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
L
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
SSOP or TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
out
CC
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
6.0 mA
4.5
5.5
0.26
0.33
0.4
out
I
in
Maximum Input Leakage Current
V
in
= V
or GND
± 0.1
± 1.0
± 1.0
µA
CC
MOTOROLA
2
MC54/74HCT373A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
85 C
125 C
Unit
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
5.5
± 0.5
± 5.0
± 10
µA
OZ
V
= V or V
in
IL
IH
or GND
V
out
= V
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
5.5
5.5
4.0
40
160
µA
CC
in
CC
= 0 µA
I
out
≥ –55 C
25 C to 125 C
∆I
CC
Additional Quiescent Supply
Current
V
V
= 2.4 V, Any One Input
mA
in
in
= V
or GND, Other Inputs
CC
= 0 µA
2.9
2.4
l
out
NOTE: 1. Total Supply Current = I
+ Σ∆I
.
CC
CC
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
t
,
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
32
30
35
12
35
42
ns
PLH
t
PHL
,
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
40
38
44
15
48
45
53
18
ns
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PZL
PZH
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Latch)*
pF
65
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, Input t = t = 6.0 ns)
r f
CC
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
10
13
15
ns
t
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
10
13
15
15
18
ns
ns
ns
h
t
w
Minimum Pulse Width, Latch Enable
(Figure 2)
12
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
3
MOTOROLA
MC54/74HCT373A
EXPANDED LOGIC DIAGRAM
D0
3
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
4
7
8
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
LATCH
ENABLE
11
1
OUTPUT
ENABLE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
SWITCHING WAVEFORMS
t
t
f
r
t
w
3 V
3 V
2.7 V
LATCH ENABLE
1.3 V
1.3 V
INPUT D
Q
1.3 V
0.3 V
GND
GND
t
t
PHL
PLH
t
t
PLH
PHL
90%
1.3 V
10%
Q
1.3 V
t
t
THL
TLH
Figure 1.
Figure 2.
3 V
OUTPUT
ENABLE
1.3 V
GND
VALID
t
t
PLZ
PZL
3 V
HIGH
IMPEDANCE
INPUT D
1.3 V
t
1.3 V
GND
3 V
Q
t
10%
90%
su
h
V
V
OL
t
t
PHZ
PZH
LATCH ENABLE
1.3 V
OH
GND
1.3 V
Q
HIGH
IMPEDANCE
Figure 3.
Figure 4.
MOTOROLA
4
MC54/74HCT373A
TEST CIRCUITS
TEST POINT
1 k
TEST POINT
CONNECT TO V
WHEN
.
PZL
CC
AND t
Ω
OUTPUT
OUTPUT
TESTING t
PLZ
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
C *
L
L
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 5.
Figure 6.
5
MOTOROLA
MC54/74HCT373A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
6
MC54/74HCT373A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE B
Y14.5M, 1982.
20X K REF
0.12 (0.005)
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
0.25 (0.010)
M
S
S
T
U
V
N
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
M
20
11
10
L/2
N
B
F
L
DETAIL E
K
PIN 1
IDENT
1
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
–U–
A
–V–
J
J1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
7.07
5.20
1.73
0.05
0.63
MAX
7.33
5.38
1.99
0.21
0.95
MIN
MAX
0.288
0.212
0.078
0.008
0.037
K1
M
S
0.20 (0.008)
T U
0.278
0.205
0.068
0.002
0.024
SECTION N–N
–W–
0.65 BSC
0.026 BSC
C
0.59
0.09
0.09
0.25
0.25
7.65
0
0.75
0.20
0.16
0.38
0.33
7.90
8
0.023
0.003
0.003
0.010
0.010
0.301
0
0.030
0.008
0.006
0.015
0.013
0.311
8
0.076 (0.003)
SEATING
PLANE
–T–
D
G
DETAIL E
K1
L
M
H
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
S
0.15 (0.006)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
0.15 (0.006)
T U
M
A
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
6.40
4.30
–––
0.05
0.50
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
–V–
0.252
0.169
–––
0.002
0.020
N
F
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
7
MOTOROLA
MC54/74HCT373A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://www.mot.com/SPS/
MC74HCT373A/D
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相关型号：
MC74HCT373ADWR2
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20
MOTOROLA
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